ISPLSI2064VE-280LT44 [ETC]
Electrically-Erasable Complex PLD ; 电可擦除可编程逻辑器件复杂\n
| 型号： | ISPLSI2064VE-280LT44 |
| 厂家： | 
ETC |
| 描述： | Electrically-Erasable Complex PLD
|
| 文件： | 总16页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 2064VE
3.3V In-System Programmable
High Density SuperFAST™ PLD
Features
Functional Block Diagram
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
Input Bus
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
ispLSI 2064V Devices
Output Routing Pool (ORP)
B7
B6
B5
B4
Global Routing Pool
(GRP)
A0
A1
A2
A3
B3
B2
B1
B0
D
D
D
D
Q
Q
Q
Q
• 3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
Logic
Array
GLB
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 280MHz Maximum Operating Frequency
— tpd = 3.5ns Propagation Delay
A4
A5
A6
A7
— Electrically Erasable and Reprogrammable
— Non-Volatile
Output Routing Pool (ORP)
Input Bus
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
0139A/2064V
• IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
Description
The ispLSI 2064VE is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VE features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VE offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2064VE device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7(seeFigure1). Thereareatotalof16GLBsinthe
ispLSI 2064VE device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/ExclusiveORarray, andfouroutputswhichcan
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright©2001LatticeSemiconductorCorp.Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2001
2064ve_07
1
Specifications ispLSI 2064VE
Functional Block Diagram
Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions)
Generic Logic
Blocks (GLBs)
Generic Logic
Blocks (GLBs)
Input Bus
Input Bus
Output Routing Pool (ORP)
B6 B5
Output Routing Pool (ORP)
Megablock
Megablock
B7
B4
B7
B6
B5
B4
I/O 47
I/O 46
I/O 45
I/O 44
I/O 23
I/O 22
I/O 21
I/O 20
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
A0
A1
A2
B3
B2
B1
B0
A0
A1
A2
B3
B2
B1
B0
I/O 4
I/O 5
I/O 6
I/O 7
I/O 43
I/O 42
I/O 41
I/O 40
Global Routing Pool
(GRP)
Global Routing Pool
(GRP)
I/O 8
I/O 9
I/O 39
I/O 38
I/O 37
I/O 36
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 35
I/O 34
I/O 33
I/O 32
I/O 4
I/O 5
I/O 6
I/O 7
I/O 19
I/O 18
I/O 17
I/O 16
A3
A3
GOE0/IN 3
TMS/IN 2
TCK/IN 3
TDO/IN 2
TDI/IN 0
TDI/IN 0
A4
A5
A6
A7
A4
A5
A6
A7
TMS/IN 1
TDO/IN 1
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
Input Bus
RESET
BSCAN
BSCAN
0139B/2064VE
0139B/2064VE.32IO
The 64-I/O 2064VE contains 64 I/O cells, while the 32- Y1, Y2) or an asynchronous clock can be selected on a
I/O version contains 32 I/O cells. Each I/O cell is directly GLB basis. The asynchronous or Product Term clock
connected to an I/O pin and can be individually pro- can be generated in any GLB for its own clock.
grammed to be a combinatorial input, output or
Programmable Open-Drain Outputs
bi-directional I/O pin with 3-state control. The signal
levelsareTTLcompatiblevoltagesandtheoutputdrivers
can source 4 mA or sink 8 mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5-Volt signal levels to support
mixed-voltage systems.
In addition to the standard output configuration, the
outputs of the ispLSI 2064VE are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064VE device contains
two Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064VE device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
2
Specifications ispLSI 2064VE
1
Absolute Maximum Ratings
Supply Voltage V ................................................... -0.5 to +5.4V
cc
Input Voltage Applied..................................... -0.5 to +5.6V
Off-State Output Voltage Applied .................. -0.5 to +5.6V
Storage Temperature..................................... -65 to 150°C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ............ 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Commercial
Industrial
MIN.
3.0
MAX.
3.6
UNITS
V
V
V
V
T = 0°C to + 70°C
A
VCC
Supply Voltage
3.0
3.6
T = -40°C to + 85°C
A
Input Low Voltage
Input High Voltage
V – 0.5
0.8
VIL
SS
2.0
5.25
VIH
Table 2-0005/2064V
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock and Global Output Enable Capacitance
TYPICAL
UNITS
TEST CONDITIONS
VCC = 3.3V, V = 0.0V
8
6
pf
pf
pf
C1
C2
C3
IN
VCC= 3.3V, VI/O = 0.0V
10
VCC= 3.3V, VY = 0.0V
Table 2-0006/2064VE
Erase Reprogram Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10000
–
Cycles
Table 2-0008/2064VE
3
Specifications ispLSI 2064VE
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
≤ 1.5 ns 10% to 90%
+ 3.3V
1.5V
1.5V
R
1
See Figure 2
Device
Output
Test
Point
Table 2-0003/2064VE
3-state levels are measured 0.5V from
steady-state active level.
R
2
C *
L
Output Load Conditions (see Figure 2)
TEST CONDITION
R1
316Ω
∞
R2
CL
*
C includes Test Fixture and Probe Capacitance.
A
B
348Ω
348Ω
348Ω
35pF
35pF
35pF
L
0213A/2064V
Active High
Active Low
316Ω
Active High to Z
at VOH-0.5V
∞
348Ω
5pF
C
Active Low to Z
at VOL+0.5V
316Ω
348Ω
5pF
Table 2-0004/2064V
DC Electrical Characteristics
Over Recommended Operating Conditions
3
SYMBOL
VOL
VOH
IIL
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
IOL= 8 mA
MIN.
–
TYP. MAX. UNITS
–
–
–
–
–
–
–
–
0.4
–
V
V
IOH = -4 mA
2.4
–
Input or I/O Low Leakage Current
0V ≤ V ≤ V (Max.)
-10
10
µA
µA
µA
µA
µA
mA
IN
IL
(V – 0.2)V ≤ V ≤ VCC
–
IN
CC
Input or I/O High Leakage Current
IIH
V ≤ V ≤ 5.25V
–
10
IN
CC
BSCAN Input Low Leakage Current
I/O Active Pull-Up Current
0V ≤ V ≤ V
–
-150
-150
-100
IIL-isp
IIL-PU
IOS1
IN
IL
0V ≤ V ≤ V
–
IN
IL
Output Short Circuit Current
V = 3.3V, VOUT= 0.5V
–
CC
V = 0.0V, V = 3.0V
ICC2, 4
IL
IH
–
90
–
mA
Operating Power Supply Current
fCLOCK = 1 MHz
Table 2-0007/2064VE
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at VCC= 3.3V and TA= 25°C.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC
.
4
Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
TEST3
COND.
-280
-200
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX.
A
A
A
–
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback2
–
–
3.5
5.5
–
–
–
4.5
7.0
–
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
280
182
300
2.3
–
200
133
200
3.0
–
MHz
MHz
MHz
ns
max
1
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
–
–
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
–
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
–
2.5
–
3.5
–
ns
co1
0.0
3.0
–
0.0
4.0
–
ns
h1
–
–
–
ns
su2
A
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
3.3
–
4.5
–
ns
co2
0.0
–
0.0
–
ns
h2
A
–
5.5
–
6.0
–
ns
r1
3.5
–
4.0
–
ns
rw1
B
C
B
C
–
14 Input to Output Enable
6.0
6.0
3.5
3.5
–
8.0
8.0
5.0
5.0
–
ns
ptoeen
ptoedis
goeen
goedis
wh
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
1.6
1.6
2.5
2.5
ns
–
–
–
ns
wl
Table 2-0030A/2064VE v.0.0
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
5
Specifications ispLSI 2064VE
External Timing Parameters
Over Recommended Operating Conditions
TEST3
COND.
-135
-100
PARAMETER
#
DESCRIPTION1
UNITS
MIN. MAX. MIN. MAX.
A
A
A
–
1
2
3
4
5
6
7
8
9
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback2
–
–
7.5
10.0
–
–
–
10.0
13.0
–
ns
ns
t
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd1
pd2
135
100
143
5.0
–
100
77
100
6.5
–
MHz
MHz
MHz
ns
max
1
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
(
)
–
–
max (Ext.)
max (Tog.)
su1
tsu2 + tco1
–
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
–
4.0
–
5.0
–
ns
co1
0.0
6.0
–
0.0
8.0
–
ns
h1
–
–
–
ns
su2
A
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
5.0
–
6.0
–
ns
co2
0.0
–
0.0
–
ns
h2
A
–
9.0
–
12.5
–
ns
r1
5.0
–
6.5
–
ns
rw1
B
C
B
C
–
14 Input to Output Enable
12.0
12.0
7.0
7.0
–
15.0
15.0
9.0
9.0
–
ns
ptoeen
ptoedis
goeen
goedis
wh
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
3.5
3.5
5.0
5.0
ns
–
–
–
ns
wl
Table 2-0030B/2064VE v.0.0
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
6
Specifications ispLSI 2064VE
Internal Timing Parameters1
Over Recommended Operating Conditions
-280
-200
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
20 Input Buffer Delay
–
–
0.4
0.8
–
–
0.5
1.1
ns
ns
t
io
21 Dedicated Input Delay
tdin
GRP
grp
GLB
22 GRP Delay
–
0.4
–
0.6
ns
t
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
1.1
1.6
2.3
2.3
2.3
0.0
–
–
–
1.4
1.9
2.9
2.9
2.9
0.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
28 GLB Register Bypass Delay
–
–
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
0.6
1.7
–
1.2
1.8
–
gsu
–
–
gh
0.2
0.4
4.1
2.9
0.3
0.4
4.3
3.9
gco
–
–
gro
–
–
ptre
–
–
ptoe
ptck
0.8 2.9
1.0 4.0
ORP
36 ORP Delay
–
–
1.2
0.4
–
–
1.5
0.5
ns
ns
t
orp
37 ORP Bypass Delay
torpbp
Outputs
38 Output Buffer Delay
–
–
–
–
–
1.2
1.8
2.3
2.3
1.2
–
–
–
–
–
1.5
2.0
3.0
3.0
2.0
ns
ns
ns
ns
ns
t
t
t
t
t
ob
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
0.7 0.7
0.9 0.9
1.2 1.2
1.4 1.4
ns
ns
t
gy0
tgy1/2
Global Reset
gr
45 Global Reset to GLB
–
3.5
–
3.6
ns
t
Table 2-0036A/2064VE v.0.0
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Specifications ispLSI 2064VE
Internal Timing Parameters1
Over Recommended Operating Conditions
-135
-100
2
PARAMETER
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
Inputs
tio
tdin
20 Input Buffer Delay
–
–
0.5
1.7
–
–
0.7
2.5
ns
ns
21 Dedicated Input Delay
GRP
22 GRP Delay
–
1.2
–
1.8
ns
tgrp
GLB
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
3.7
3.7
4.7
4.7
4.7
0.5
–
–
–
5.2
4.7
6.2
6.2
6.2
1.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
28 GLB Register Bypass Delay
–
–
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
1.2
3.8
–
1.7
4.8
–
–
–
0.3
1.1
6.1
6.9
0.3
3.1
7.1
9.1
–
–
–
–
tptre
–
–
tptoe
tptck
ORP
1.6 5.0
2.6 5.6
36 ORP Delay
–
–
1.5
0.5
–
–
1.7
0.7
ns
ns
torp
37 ORP Bypass Delay
torpbp
Outputs
tob
tsl
toen
38 Output Buffer Delay
–
–
–
–
–
1.6
2.0
3.4
3.4
3.6
–
–
–
–
–
1.6
2.0
3.4
3.4
5.6
ns
ns
ns
ns
ns
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
todis
tgoe
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.6 1.6
1.8 1.8
2.4 2.4
2.6 2.6
ns
ns
tgy0
tgy1/2
Global Reset
tgr
45 Global Reset to GLB
–
5.8
–
7.1
ns
Table 2-0036B/2064VE v.0.0
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Specifications ispLSI 2064VE
ispLSI 2064VE Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
39
I/O Pin
(Output)
I/O Pin
(Input)
#24
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0,1
0491/2064
Derivations of
t
su,
= Logic + Reg su - Clock (min)
= ( io + grp + 20ptxor) + ( gsu) - (tio + tgrp + tptck(min))
th and tco from the Product Term Clock
t
t
t
su
t
t
t
t
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
= (0.4 + 0.4 + 2.3) + (0.6) - (0.4 + 0.4 + 0.8)
2.1ns
2.3ns
6.3ns
h
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
= (0.4 + 0.4 + 2.9) + (1.7) - (0.4 + 0.4 + 2.3)
co
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
= (0.4 + 0.4 + 2.9) + (0.2) + (1.2 + 1.2)
Note: Calculations are based on timing specifications for the ispLSI 2064VE-280L.
Table 2-0042/2064VE
9
Specifications ispLSI 2064VE
Power Consumption
used. Figure 3 shows the relationship between power
and operating speed.
Power consumption in the ispLSI 2064VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
Figure 3. Typical Device Power Consumption vs fmax
180
160
ispLSI 2064VE
140
120
100
80
0
50
100
150
200
250
300
fmax (MHz)
Notes: Configuration of four 16-bit counters
Typical current at 3.3V, 25° C
I
I
can be estimated for the ispLSI 2064VE using the following equation:
(mA) = 8 + (# of PTs * 0.67) + (# of Nets * Fmax * 0.0045)
CC
CC
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
estimate is based on typical conditions (V
= 3.3V, room temperature) and an assumption of two GLB
is sensitive to operating
CC
CC
loads on average exists. These values are for estimates only. Since the value of I
conditions and the program in the device, the actual I
CC
should be verified.
CC
0127/2064VE
10
Specifications ispLSI 2064VE
64-I/O Signal Descriptions
Signal Name
Description
RESET
Active Low (0) Reset pin resets all the registers in the device.
Global Output Enable input pins.
GOE 0, GOE1
Y0, Y1, Y2
Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
BSCAN
Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
TCK/IN 3
TMS/IN 1
TDO/IN 2
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
GND
VCC
NC1
I/O
Ground (GND)
Vcc
No Connect
Input/Output Pins – These are the general purpose I/O pins used by the logic array.
1. NC pins are not to be connected to any active signals, VCC or GND.
32-I/O Signal Descriptions
Signal Name
Description
GOE 0/IN 3
This pin performs one of two functions. It can be programmed to function as a Global Output Enable
pin or a Dedicated Input pin.
GOE 1/Y0
This pin performs one of two functions. (1) It can be programmed to function as a GLobal Output Enable
or a Dedicated Clock input. (2) This clock input is connected to one of the clock inputs of all GLBs on
the device.
RESET/Y1
BSCAN
This pin performs two functions: (1) Active Low (0) Reset pin which resets all of the registers in the
device. (2) When active low (0), it functions as a dedicated clock input.
Input – Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. (2) When BSCAN is high, it functions as a dedicated input
pin.
TMS/IN 2
TDO/IN 1
TCK/Y2
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated clock input.
GND
VCC
NC1
I/O
Ground (GND)
Vcc
No Connect
Input/Output pins – These are the general purpose I/O pins used by the logic array.
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2064VE
64-I/O Signal Locations
I/O Locations
100
100
TQFP
44
TQFP
44
PLCC
Signal
RESET
GOE 0, GOE 1 F9, E1
100-Ball caBGA 100-Pin TQFP
Signal caBGA
D2
11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
G1
F3
E4
H1
G2
J1
H2
K1
J2
K2
H3
J3
G4
H4
K4
H5
F5
17
18
19
20
22
23
24
26
27
28
29
30
32
33
34
35
40
41
42
43
45
46
47
48
49
51
52
53
55
56
57
58
67
68
69
70
72
73
74
76
77
78
79
80
82
83
84
85
90
91
92
93
95
96
97
98
99
1
9
15
16
17
18
19
20
21
22
25
26
27
28
29
30
31
32
37
38
39
40
41
42
43
44
3
62, 13
10
11
12
13
14
15
16
19
20
21
22
23
24
25
26
31
32
33
34
35
36
37
38
41
42
43
44
1
Y0, Y1, Y2
E3, F6, F8
10, 65, 60
E5
F2
15
16
59
37
BSCAN
TDI/IN 0
TCK/IN 3
TMS/IN 1
G10
J5
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
I/O 36
I/O 37
I/O 38
I/O 39
I/O 40
I/O 41
I/O 42
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
I/O 48
I/O 49
I/O 50
I/O 51
I/O 52
I/O 53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
TDO/IN 2
GND
B6
87
B7, F1, G9, K6
14, 39, 61, 86
VCC
NC1
A5, E2, F10, J4 12, 36, 63, 89
J6
K7
H6
K8
G6
J7
K9
J8
A6, A8, C3, C4, 4, 9, 21, 25,
D1, D6, D8, E7, 31, 38, 44, 50,
E9, E10, F4,
G3, G5, H7, H8, 75, 81, 88, 94,
K3, K5 100
54, 64, 66, 71,
K10
J9
4
5
6
7
8
9
1. NC pins are not to be connected to any active signals,
VCC or GND.
J10
H9
H10
G7
G8
D10
E8
F7
2
3
4
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32-I/O Signal Locations
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Signal
GOE 0/ IN 3
GOE 1/Y0
44-Pin TQFP
40
44-Pin PLCC
C10
D9
B10
C9
A10
B9
A9
C8
B8
D7
C7
A7
C6
E6
B5
A4
C5
A3
D5
B4
A2
B3
A1
B2
B1
C2
C1
D4
D3
2
5
11
29
7
35
RESET/Y1
BSCAN
TDI/IN 0
TMS/IN 2
TDO/IN 1
TCK/Y2
GND
13
8
14
30
18
27
17, 39
6, 28
—
36
24
33
1, 23
12, 34
—
VCC
NC1
1. NC pins are not to be connected to any active signals,
VCC or GND.
2
3
5
6
7
8
12
Specifications ispLSI 2064VE
Signal Configuration
ispLSI 2064VE 100-Ball caBGA Signal Diagram (0.8mm Ball Pitch/10.0 x 10.0mm Body Size)
10
9
8
7
6
5
4
3
2
1
I/O
39
I/O
41
I/O
46
I/O
50
I/O
52
I/O
55
I/O
57
NC1
NC1
VCC
A
B
C
D
E
F
A
B
C
D
E
F
I/O
37
I/O
40
I/O
43
TDO/
IN 2
I/O
49
I/O
54
I/O
56
I/O
58
I/O
59
GND
I/O
35
I/O
38
I/O
42
I/O
45
I/O
47
I/O
51
I/O
60
I/O
61
NC1
NC1
I/O
32
I/O
36
I/O
44
I/O
53
I/O
62
I/O
63
NC1
NC1
RESET
NC1
I/O
33
I/O
48
I/O
2
GOE
1
NC1
NC1
NC1
BSCAN
Y0
VCC
GOE
0
I/O
34
I/O
16
I/O
1
TDI/
IN 0
VCC
Y2
Y1
NC1
GND
TCK/
IN 3
I/O
31
I/O
30
I/O
21
I/O
12
I/O
4
I/O
0
GND
NC1
NC1
G
H
J
G
H
J
I/O
29
I/O
28
I/O
19
I/O
15
I/O
13
I/O
10
I/O
6
I/O
3
NC1
NC1
I/O
27
I/O
26
I/O
24
I/O
22
I/O
17
TMS/
IN 1
I/O
11
I/O
8
I/O
5
VCC
I/O
25
I/O
23
I/O
20
I/O
18
I/O
14
I/O
9
I/O
7
GND
NC1
NC1
K
K
ispLSI 2064VE
Bottom View
10
9
8
7
6
5
4
3
2
1
100-BGA/2064VE
1
NCs are not to be connected to any active signals, VCC or GND.
Note: Ball A1 indicator dot on top side of package.
13
Specifications ispLSI 2064VE
Pin Configuration
ispLSI 2064VE 100-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/14.0 x 14.0mm Body Size)
I/O 57
I/O 58
I/O 59
1NC
I/O 60
I/O 61
I/O 62
I/O 63
1NC
Y0
RESET
VCC
GOE 1
GND
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC1
I/O 38
I/O 37
I/O 36
NC1
I/O 35
I/O 34
I/O 33
I/O 32
NC1
Y1
NC1
VCC
GOE 0
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ispLSI 2064VE
Top View
BSCAN
TDI/IN 0
I/O 0
Y2
TCK/IN 3
I/O 31
I/O 30
I/O 29
I/O 28
NC1
I/O 27
I/O 26
I/O 25
I/O 1
I/O 2
I/O 3
1NC
I/O 4
I/O 5
I/O 6
1NC
100 TQFP/2064VE
1. NC pins are not to be connected to any active signals, VCC or GND.
14
Specifications ispLSI 2064VE
Pin Configuration
ispLSI 2064VE 44-Pin PLCC Pinout Diagram (0.05in Lead Pitch/0.65 x 0.65in Body Size)
6
5 4 3 2 1 44 43 42 41 40
I/O 28
I/O 29
I/O 30
I/O 31
GOE1/Y0
VCC
7
8
39
38
37
I/O 18
I/O 17
I/O 16
9
10
11
12
13
36 TMS/IN 2
35
34
RESET/Y1
VCC
ispLSI 2064VE
BSCAN
TDI/IN 0
I/O 0
33 TCK/Y2
Top View
14
15
16
17
32
31
30
29
I/O 15
I/O 14
I/O 13
I/O 12
I/O 1
I/O 2
18 19 20 21 22 23 24 25 26 27 28
44 PLCC/2064VE
Pin Configuration
ispLSI 2064VE 44-Pin TQFP Pinout Diagram (0.8mm Lead Pitch/10.0 x 10.0mm Body Size)
44 43 42 41 40 39 38 37 36 35 34
I/O 28
I/O 29
I/O 30
1
2
33
32
31
I/O 18
I/O 17
I/O 16
3
4
5
6
7
I/O 31
GOE1/Y0
VCC
30
29
28
27
TMS/IN 2
RESET/Y1
VCC
ispLSI 2064VE
Top View
BSCAN
TCK/Y2
TDI/IN 0
I/O 0
8
26
25
24
23
I/O 15
I/O 14
I/O 13
I/O 12
9
I/O 1
10
11
I/O 2
12 13 14 15 16 17 18 19 20 21 22
44 TQFP/2064VE
15
Specifications ispLSI 2064VE
Part Number Description
ispLSI
– XXX X XXXX X
2064VE
Device Family
Grade
Blank = Commercial
I = Industrial
Device Number
Speed
280 = 280 MHz
200 = 200 MHz
135 = 135 MHz
100 = 100 MHz
Package
T100 = 100-Pin TQFP
B100 = 100-Ball caBGA
T44 = 44-Pin TQFP
J44 = 44-Pin PLCC
fmax
fmax
fmax
fmax
Power
L = Low
0212/2064VE
ispLSI 2064VE Ordering Information
COMMERCIAL
FAMILY
fmax (MHz)
280
tpd (ns)
3.5
3.5
3.5
4.5
4.5
4.5
4.5
7.5
7.5
7.5
7.5
10
I/Os
64
64
32
64
64
32
32
64
64
32
32
64
64
32
32
ORDERING NUMBER
PACKAGE
ispLSI 2064VE-280LT100
ispLSI 2064VE-280LB100
ispLSI 2064VE-280LT44
ispLSI 2064VE-200LT100
ispLSI 2064VE-200LB100
ispLSI 2064VE-200LJ44
ispLSI 2064VE-200LT44
ispLSI 2064VE-135LT100
ispLSI 2064VE-135LB100
ispLSI 2064VE-135LJ44
ispLSI 2064VE-135LT44
ispLSI 2064VE-100LT100
ispLSI 2064VE-100LB100
ispLSI 2064VE-100LJ44
ispLSI 2064VE-100LT44
100-Pin TQFP
100-Ball caBGA
44-Pin TQFP
100-Pin TQFP
100-Ball caBGA
44-Pin PLCC
44-Pin TQFP
100-Pin TQFP
100-Ball caBGA
44-Pin PLCC
44-Pin TQFP
100-Pin TQFP
100-Ball caBGA
44-Pin PLCC
44-Pin TQFP
280
280
200
200
200
200
ispLSI
135
135
135
135
100
100
10
100
10
100
10
Table 2-0041A/2064VE
INDUSTRIAL
FAMILY
ispLSI
fmax (MHz)
135
tpd (ns)
7.5
I/Os
64
ORDERING NUMBER
ispLSI 2064VE-135LT100I
ispLSI 2064VE-135LT44I
PACKAGE
100-Pin TQFP
44-Pin TQFP
135
7.5
32
Table 2-0041B/2064VE
16
相关型号：
ISPLSI2064VE-280LTN100
EE PLD, 5.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, TQFP-100
LATTICE
©2020 ICPDF网 联系我们和版权申明