IT3205BE_技术文档

MT6516 Design Notice V1.0

2009 / April

WCP/SA

Change Notice

▪ 2009/05/11 Initial document

▪ 2009/06/22 Add IQ 510ohm

2

Outline

▪ MT6516 Main Features & Package

▪ Design Notice

– MT6516 schematic design notice

– PMIC MT6326 design notice

– Audio part design notice

– Speech part design notice

– Camera design notice

– Display design notice

– DDR memory layout rule

– USB 2.0 high speed design notice

▪ Factory Mode and Engineer Mode

▪ Download and META Link

▪ MT6516 Memory Support Plan

▪ Appendix - Peripherals Design Notice

– WIFI/BT Co-module Application Note

– MT3326 GPS application note

– DTV part design note

– FM design notice

3

MT6516 Main Feature

▪

Separate Application (ARM9) and hard real-time ▪

High Performance Memory controller @

104MHz, support

– 32-bit / 16-bit LP-DDR SDRAM

– 4 chip selects : support up to 4 DRAM

devices

– NAND-boot supported

Modem (ARM7)

Multi-Cores with HW coprocessors SoC

– Application: ARM926EJS 416MHz

– Modem: ARM7 (52MHz/104MHz) + 2

DSP(104MHz)

– NAND data storage supported

– CEVA DSP (312MHz) for video and

unpredictable multimedia application on

Smartphone

▪

Peripherals

– Dual SIM

– 3 x SDIO, 3 x I2C, 1 x I2S, 4 x UART

– 1-wire interface, 7 x PWM

– 8 x 8 Key Matrix

▪

65nm process. Ultra low power design.

Graphics, Display, Image, Camera, Video

multimedia hardware accelerators.

– Touch panel interface

– USB 2.0 high speed integrate with PHY.

– 2D Graphics - support Window Mobile Bitblt

function

– 3D Graphics - Support OpenGL ES 1.1

Common/Common Lite profile

– 3D Performance: fill rate = 32M, triangle rate =

3.7M

▪

Wide range of resolution up to WVGA size

Various display Interface Support

– 8080 host IF (MIPI DBI)

– 8/9/16/32-bit Serial IF

– RGB interface (MIPI DPI)

– MIPI DSI interface

4

MT6516 Design Package Building Blocks

MT6611 & MT5921

WiFi/BT Co-module

MT3326

GPS Receiver

MT5151

DTV Receiver

MT6140D+SKY77344

EDGE Transceiver

UART

SDIO

UART

SDIO

BPI

Modem MCU

MT6326

PMIC

Apps. Processor

I2C

ARM926EJS

416Mhz

ARM7 104Mhz

I2C

AR1000 FM

Multimedia ASIC

2D

MP3

3D

3D Scaler

EMI

NFI

Internal

Memory

MCP Memory

1G DDR

2G NAND

TI BQ27500

Smart battery

(Optional)

I2C

H.264

JPEG codec

Parallel Camera I/F

SDIO

LCM I/F

Camera

5MP Autofocus

SIM Interface

(Dual SIM

capable)

T-Flash Card

2.8＂ LCD

QVGA

5

MT6516 Package

Body Size

Ball Count

Ball Pitch

e1 / e2

Ball Dia.

Package Thk.

A (Max.)

1.2

Stand Off

A1

Substrate Thk.

D

E

N

b

C

15

564

0.378 / 0.535

0.3

0.21

0.26

6

Table 1 Definition of TFBGA 15mm*15mm, 564-ball, 0.378 mm pitch Package (Unit: mm)

Design Notice -

MT6516 Schematic Design Notice

Schematic Notice (1/7): Boot-up selection

H\L

H(DVDD)

L(GND)

Enable one JTAG functionDisable

IONEJTAG

IBOOT

SECU_EN

IADMUX

boot from external memor boot from bootrom

Enable secure booting Disable

ADMux memory device AD-Demux memory device

Coresight enable,

burn efuse

Coresight disable

Normal

ICORESIGHT

FSOURCE

●MT6516 currently only support DDR memory, so this selection always choose GND

●Connect FSOURCE to GND by 0ohm, otherwise the UUID number will be unstable.

8

Schematic Notice (2/7)

The AVDD Power must follow the connection show above

to avoid the influence between AFE, RFE and MBUF

9

Schematic Notice (3/7)

Connect AU_VCM_NO

to GND

Add 2 capacitors (1uF, 0.1uF)

in AVDD12_PLL

10

Schematic Notice (4/7)

VDD

•For better interoperability

R506

47K

R507

47K

R502

47K

R503

47K

R504

47K

R505

47K

and stability, please

reserve 47k ohm in each

memory card interface

line.

SD_CARD_SOCKET (SKT SD/MMC Standard Ty

8

7

6

5

4

1 MCDA1

1 MCDA0

DAT1

DAT0

VSS2

CLK

VDD

9

1 MCCK

Shield

10

11

12

3

2

1 MCCM0

1 MCDA3

CMD

CD/DAT3

1

1 MCDA2

DAT2

T503

T504

T505

T506

T507

T501

T502

TF_5015880801-A

J501

C504

1u

11

Schematic Notice (5/7)

Add a diode between MT6516 PWR_KEY

and MT6326 PWRKEY

Add a 1k resistor to avoid ESD damage.

MT6516

Add a diode and a EINT

to MT6326 PWRKEY

MT6326 PMIC

Power Key Bottom

12

Schematic Notice (6/7) :Debug Port

ARM7 (Modem side) JTAG

U100E

AD34

AD38

AB36

AC33

AC35

AB34

AM32

AK30

AN33

AP34

AR35

AL31

16

JTRST_B

JZTRST_B

16

JTRST_B J2TRST_B

16

JTCK

JTDI

JTMS

JTDO

JRTCK

JZTCK

JZTDI

16

JTCK

JTDI

J2TCK

J2TDI

J2TMS

J2TDO

J2RTCK

JZTMS

JZTDO

JZRTCK

JTMS

JTDO

JRTCK

tk65_18

T38

IONEJTAG

16

IONEJTAG

MT6516-564/P0.53/B0.27(15X15)/IAC

ARM9 (AP side) JTAG

Use only one JTAG to control AP and modem side MCU

13

Schematic Notice (7/7) : NFI Interface

▪ To support 1.8 V NAND MCP, you need to

– Connect VDD33_LCD of BB part to 1.8 V

– Check if LCM module IO can support 1.8V first. Connect LCM IO power pin

(VDDIO) to 1.8 V (see LCM Selection Guide to 1.8 V LCM section)

2

1

BB

LCM IO

‧Beware that NAND flash, parallel LCM, and VDD33_NLD must use same power domain !

14

RF IQ Connection ( Remember add 510ohm

Between Baseband and MT6140D)

15

Reset Button Design Suggestion

1. Basically, the MT6516 phone don’t need reset button.

(Users remove battery when system hang)

2. There are two kinds of suggestion design of reset

button.

1. Only add a pull low button on SYSRST_B pin

1. Advantage : cost effective

2. Disadvantage : User must press pwrkey to restart system

SW702

2

1

SYSRST_B

KSW

2. Add a reset chip on pwrkey pin and SYSRST_B pin.

1. Advantage : User can press reset then direct restart the phone.

2. Disadvantage : Need a extra reset chip

Reset chip that only

generate one pulse

SW702

reset chip

2

1

SYSRST_B

PWRKEY

KSW

16

Default UART Dispatch Notice

Download Bootloader, META Link, Production Line

Test Point

UART1

User Define, Default Use for AGPS

COPY HERE

UART2

User Define, Default Use for Bluetooth

UART3

Data Log for Debugging, Boot-Up Selection and

Setting. Modem side META link.

UART4

Download Image BIN file, Active Sync, Mass Storage,

RNDIS

USB Port

17

Reference Power Distribution

‧MT6516

‧MT6326

Core Power

VCORE

VDDK (52 Balls)

USB Core Power

1.3V

AVDD12_USB

General IO

VDD33

ETM IO

VDD33_TRACER

VDD

2.8V

MIPI Power

VDD33_MIPI/MIPI_TX/MIPI_RX

VDD33_SPI

SPI Power

NAND/LCM Power

VDD33_NLD

EMI Power (LPDDR)

VM 1.8V

VDD33_EMI (6 Balls)

Camera I/O Power

VDD33_CAMERA

VCAM_A

SCL1/SDA1 Power

VDD33_I2C (Camera)

SIM1 Power

AVDD30_VSIM

VDD33_MC0/1/2

VSIM

SDIO1/SDIO2/SDIO3 Power

VSDIO

SIM2 Power

AVDD30_VSIM2

AVDD33_USB

VGP

USB PHY Power ¹⁸

VUSB 3.3V

MT6516 reference phone PCB layer define

Layer

No.

Die.

Con.

suggest

thickness(mil)

Name

ꢀDefine

Material

Suggestion

Via

SolderMask SolderMask

Add Plating plating

Copper foil 0.5 oz

0.4

1.4

ꢀ

1 COMP(L1)

H oz+plating

ꢀRF Trace

ꢀ

PP

Copper foil 1.0 oz

CORE

Copper foil 1.0 oz

PP

Copper foil 1.0 oz

CORE

Copper foil 1.0 oz

PP

Copper foil 1.0 oz

CORE

Copper foil 1.0 oz

PP

PP 1080 65%

4.3

2.82

ꢀ

2 L2

0.50 oz+plating

1.3

ꢀSignal

PP 1080 65%

Copper 1.0 oz

FR-4 Core 4mil

Copper 1.0 oz

PP 7628 50%

Copper 1.0 oz

FR-4 Core 4mil

Copper 1.0 oz

PP 1080 65%

0.50 oz+plating

PP 1080 65%

4.3

2.82

1.3

4

ꢀ

3 L3

ꢀ

ꢀGND

ꢀ

4 L4

ꢀ

1.3

8.38

1.3

4

ꢀRF Trace

ꢀ

5 L5

ꢀ

ꢀGND

ꢀ

6 L6

ꢀ

1.3

2.82

1.3

2.82

ꢀSignal

ꢀ

7 L7

ꢀ

ꢀSignal

ꢀ

8 SOLD(L8)

ꢀ

Copper foil 0.5 oz

ꢀRF Trace

ꢀ

Add Plating plating

SolderMask SolderMask

H oz+plating

1.4

0.4

ꢀ

Board

Thickness

=1.00mm

+/-

39.06

ꢀ

10%mm

19

MT6326 PMIC Design Notice

MT6326 PMIC

DC-DC

VPA 1.3~3.4V/600mA

3G PA

(For 3G PA)

Analog Switch

VGP1 1.8/2.8/100mA

V3GTX 2.8_3_3.3V/200mA

V3GRX 2.8_3_3.3V/100mA

3G Transceiver

LDOs

3G Transceiver

Backup Battery

Current Sink *8

(Current sharing)

LCM

Module

(MUX)

2 DC-DC

(For Vcore)

DVFS

Vcore1 1.2(0.9_1.8V(1.5)/600mA

Vcore2 1.2(0.9_1.8V(1.5)/600mA

Base Band

Processor

Boost Converter

1. Back Light

2. Flash Light

3. USB OTG

DC-DC (For

Vmem)

Vm 1.8_2.8V/600 mA

Essential LDOs

VA

VIO_2.8V/150mA

VA_2.8V/150mA

Vrtc1_2.8V/2mA

USB

Device

Flash

Memory

VIO

RAM

Vrtc2_1.2_1.5V/0.1mA

VSIM1 1.8_3V/100mA

VRTC1

VRTC2

VSIM1

VGP2

1

4

7

2

5

8

0

3

6

9

#

I2C

KP LED Driver

(Open Drain)

SIM1

SIM2

Control

VSIM2 1.8_3V/100mA

Vibrator Driver

(Open Drain)

Basic Feature

LDOs

VUSB, VBT

VCAM_D

VCAM_A

M

Reset

Generator

VUSB 3.3V/100mA

VBT 2.8_3V/100mA

BlueTooth

VCAM_D 1.3_1.5_1.8_2.8V/100mA

VCAM_A 1.8_2.5_2.8V/250mA

Camera Sensor

(AF)

Audio Switch

Class-D

Audio Amplifier 1

2G Transceiver

LDOs

VRF, VTCXO

2-in-1

Receiver

VRF 2.8V/250mA

VTCXO 2.8V/50mA

2G Transceiver

Class-D

Audio Amplifier 2

VWIFI2V8 2.8_3_3.3V/150mA

VWIFI3V3 2.8_3_3.3V/300mA

WIFI

Extra LDOs

WIFI

General Purpose

Charger

Controller

Charger

In

PMOS

+Rsense

VSDIO 2.8_3.3V/350mA

SDIO Device

MT6326

21

MT6326 PMIC LDO

Regulator

Output Voltage

Output Current Output Components

Notes

0.9~1.35

1.8

0.9~1.35

1.8

VCORE

600

2.2uH + 4.7uF

Max. output current = 100mA when set to < 1.1V

VCORE 2

VM

Max. output current = 100mA when set to < 1.1V

Max. output current = 450mA when set to 2.8V

1.8

2.8

VBAT should keep 600mV higher than V3GPA to

keep good regulation.

V3GPA

1.3~3.4

600

2.2uH + 4.7uF

V3GTX

V3GRX

VRF

2.5/2.8/3/3.3

200

100

250

50

4.7uF

1uF

2.5/2.8/3/3.3

2.8

VTCXO

VA

2.8

150

250

300

150

100

300

100

4.7uF

1uF

2.8

1.5/1.8/2.5/2.8

2.5/2.8/3/3.3

2.8

For AVDD, FM power requirement

VCAMA

VWIFI3V3

VWIFI2V8

VIO

For VDD and peripheral I/O requirement

VSIM

1.8/3.0

1uF

VUSB

1uF

3.3

VBT

1.3/1.5/1.8/2.5/2.8/3.0/3.3

2.8/3

1uF

VCAMD

VSDIO

VGP1

1uF

4.7uF

1uF

1.3/1.5/1.8/2.5/2.8/3.0

1.3/1.5/ /2.5

1.8

VGP2

100

1uF

2.8/3.0

1.5/1.2

VRTC

0.1

2

1uF

22

BAT_BACKUP

2.8

Backup battery

VBAT Input Filter

●In red frame , all component should be

in shielding case.

▪ VBAT input should reserve enough filter to prevent interference to

RF performance.

▪ All above component should be as close to MT6326 IC as possible

23

Class-D Audio Amplifier Output Filter

▪ Reserve 2 stage filter at output stage of Class-D to prevent

interference to RF performance.

▪ 1^ststage filter should be close to IC, 2^ndstage filter should be close

to loud speaker.

▪ All the traces from IC to 2^ndstage filter should not exposed to

prevent interference to RF performance.

24

Class-D : 2-in-1 Receiver Function

▪ MT6326 has 2 in 1 receiver

function , when use external

amplifier , must connect

RECIN_P and RECIN_N.

R4

R2

▪ The typical value of R1 and

R2 are 20 ohm each , and

suggest R3 and R4 to be 4

ohm (32–20–8=4)

R1

▪ Due to value variation of R1

and R2 are higher , so maybe

suffer audio volume.

R3

25

Class-D : Audio Amplifier Power Output

▪ Although MT6326 class-D power

output is 1W at 8 Ω , because

congenital power source limitation is

4.2V from VBAT , but compare with

other discrete amplifiers , MT6326

equal other amplifier in performance.

TI Poutput Profile

26

Boost1 For Parallel Backlight LCM or other 5V

requirement

▪ Reserve filter at input/output to prevent interference to RF

performance.

▪ L200/L201/C205/C279 should be in shield case and close near

MT6326

27

Boost2 For Serial Backlight LCM

●In this red frame,

all components are

reserved only.

▪ Reserve discrete B/L driver to prevent any improper design

causing interference to RF performance.

28

IC Protection: PWRKEY and BAT_ON

Please reserve 1k resistor on phone PCB to protect PWRKEY no matter if PWRKEY

connect to any I/O connector or not.

Please reserve 1k resistor on phone

PCB to protect BAT_ON pin if

BAT_ON is used to detect battery.

29

IC Protection: VBAT

Phone

I/O Cable

VBAT

V+

Power Supply

V-

MT6326

GND

Reserve

1000uF or above capacitor at the

output of power supply, and at the

end of connector cable.

1. 22uF Capacitor

2. Zener diode

on phone.

MT6326 has lower VBAT voltage rating. (Max. 4.3V.) Some protection should reserve to

prevent the damage by voltage surge.

•Design notice in Phone side:

1. At least 22uF capacitor.

2. Add Zener diode (5.1V) to protect the IC against low frequency voltage surge. Put it

between battery connector and MT6326.

Notice: If using IO connector or test point to supply VBAT for download, manufacture, or

repair, should let VBAT trace passing zener diode and 22uF capacitor before entering IC.

Notice: Using 5.1V zener will introduce some leakage when VBAT = 4.2V.

•Design notice in Power Supply side:

Add 1000uF (or above) capacitor at the output of the power supply to reduce the voltage

bounce caused by long power cable. And the power cable should be as short as possible.

Also add 1000uF (or above) capacitor at the end of power cable (near phone side).

30

IC Protection: CHRIN

MT6305

/MT6318

MT6223/35/38

/MT6326

External

OVP/OCP

Max. Charger Input

Charger OVP Point

15V

9V

7V

30V

6.8V

External OVP/OCP:

OVP/OCP Qualified Vendor :

1. TI – BQ24314

NC

R201

0

U202

IN

TO CHRIN

F201

1

8

CHRIN

VCHG

OUT

FUSE(1A 0603)

C235

2

3

4

7

6

5

C205

1uF

Notice :

VSS

NC

ILIM

VBAT

/CE

You can get better charger protection by

using external OVP/OCP device.

25K

/fault

BQ24316

VBAT

R202

220K

31

IC Protection: OVP + Charger

MT6305 MT6223/35/38

External

/MT6318

/MT6326

OVP/OCP

Max. Charger Input

Charger OVP Point

15V

9V

30V

6.17V(APL3206)

6.8V(APL3206A)

9V

7V

External OVP + Charger :

OVP/OCP + Charger Qualified Vendor :

1. ANPEC - APL3206 QBI

Notice :

You can get better charger protection by

using external OVP/OCP device.

32

Bypass Capacitor: Vcore and VM

▪ Reserve enough bypass capacitors both at

Vcore and VM to obtain good system

stability.

33

DVDD12_MIPI Power Connection

▪ MT6326 Vcore1 default is 1.3V , and MIPI_1.2V power spec. is

1.1~1.3V , so if need to use MIPI could connect Vcore2(if not used).

Besides , must add external LDO for MIPI_1.2V.

34

Bypass Capacitor: Layout Rule For Vcore

●Current Source

▪ Due to MT6516 have many Vcore (VDDK) balls , and these balls

scatter around package of MT6516. Please put bypass capacitor

around MT6516 to increase system reliably.

35

Bypass Capacitor: AVDD and VDD

▪ Reserve required input filter for

ABB as specified in left

schematics.

▪ AVDD28_MBUF suggest to

connect to VTCXO.

▪ Reserve 1uF for I/O power input.

36

Layout Notice: Charging Path

VCHG

U204

40mil

6mil

ISENSE

1

2

ACIN

ACIN CHRIN

6mil

CHRIN

6

5

40mil

Rsense

GATDRV

8

7

OUT

0.2

3

GND

6mil

BATSNS

4

R219

10K

VBAT

APL3206 QBI

VBAT

40mil

▪ Charging related component (U204, Rsense, R219) should be close

to battery connector.

▪ Minimum trace width are marked on the schematics above.

▪ ISENSE and BATSNS should be connected as the figure above.

▪ The trace from Rsense to battery connector (Marked in Red) should

not share with other VBAT traces.

▪ ISENSE/BATSNS should be routed as differential traces which are

away from noisy signals.

37

Layout Notice: Charger OVP IC

▪ The exposed pad of the charger OVP IC should connect to a large

copper ground plane to get good thermal performance.

▪ The exposed pad should has at least 6 GND via connecting to

inner layer.

Exposed pad to a

large copper ground

VCHG

U204

ISENSE

40mil

6mil

1

2

ACIN

ACIN CHRIN

CHRIN

6mil

6

5

40mil

Rsense

GATDRV

8

7

OUT

0.2

3

GND

BATSNS

6mil

4

R219

10K

VBAT

APL3206 QBI

VBAT

40mil

38

Layout Notice: VBAT Traces

Boost1 Converter

Class-D

Boost2 Converter

Buck Converter

Analog LDOs

▪ The VBAT for the 5 blocks show above (Class-D, Buck converter,

Boost1, Boost2 converter and Analog LDOs) should star-connect to the

39

bulk capacitor near battery connector.

Layout Notice: VBAT Traces

▪ Star-connect different

VBAT group to BATTERY

Connector directly

Boost2

Class-D Amplifier

Analog LDOs

Charging path

Buck and boost

converters

Bulk capacitor near

Battery Connector

RF PA

40

GND merge, other GND (Mark by

Black) should be isolate.

Class-D GND

L1

L2

L3

L5

L6

L4

▪ The GND for

L8

L7

Class-D should

isolated carefully.

41

Layout Notice: GND_VREF Traces

Pin67 (GND_VREF)

Capacitor for VREF

▪ VREF capacitor

(1uF) should be

close to IC.

▪ GND_VREF (GND

for VREF) should

isolate carefully.

The trace should

isolated and protected

by GND

The trace should

connect to GND of

battery connector

42

Layout Notice: Class-D Output

▪ The output trace (Marked in above

schematics) should be differential, and

protected by GND.

▪ 1^stfilter should be as close to IC as

possible. (As the left figure showed.)

▪ The trace width should be

– 8 ohm speaker: 25 mil.

– 4 ohm speaker: 40 mil.

43

Layout Notice: Boost1

▪ Components should be as close to IC

as possible.

▪ L200/D200/L201/C205/D200/C208

should be close and parallel to each

other.

▪ The direction of L200/D200 should

arrange as the arrowhead in left figure.

▪ Must add D204 to prevent feedback of

VBUS when turn off boost1.

44

MT6516 Design Notice (Audio)

Outline

▪ Analog gain setting

▪ RC value

▪ PCB layout

▪ Audio feature

– MP3 decoder

– 3D surround effect

– EQ 2.0

– Audio AGC

– Audio Compensation Filter

▪ For audio features, please refer to

– L1_Audio_Design_and_Interface.pdf

– Audio_Post-Processing_Interface_V1.13.pdf

– Audio Customization v1.0.pdf

46

Audio Block Diagram

Audio Buffer

Audio Amp-L

Audio

AU_MOUTL

LCH-DAC

Audio Signal

AU_MOUTR

Audio

RCH-DAC

Audio Amp-R

AU_FMINL

AU_FMINR

FM/AM radio

chip

Stereo-to-

Mono

Voice Signal

Voice Buffer

Voice DAC

Voice Amp-1

AU_OUT0_P

AU_OUT0_N

AU_VIN0_P

Microphone PGA

PGA

Voice Signal

AU_VIN0_N

AU_VIN1_N

Voice ADC

47

AU_VIN1_P

setting in

engineering

mode

audio

Buffer

[dB]

voice

Buffer

[dB]

Audio Buffer Gain

240

224

208

192

176

160

144

128

112

96

23

20

17

14

11

8

6

▪ Analog gain setting

– LoudSPK mode

4

•Audio buffer

2

– 112= -1dB

0

–Positive gain results distortion

-2

•External amplifier

5

-4

–increasing external amplifier gain for louder volume

2

-6

– Earphone mode

-1

-8

•Audio buffer

-4

-10

-12

-14

-16

-18

-20

-22

– 112= -1dB

80

-7

–Positive gain results distortion

64

-10

-13

-16

-19

-22

•External RC trade-off

48

32

16

0

48

C

47u (4V)

150 R1 1

R1 2

HP Jack

External RC value

MP3_OUTL

MP3_OUTR

R2

150

3

AGND

▪ RC value on mp3_out path

C R1

1

1) Bandwidth:

f_c=

R=R1+R2

2πRC

R 2

R1 + R 2

2) Amplitude degradation:

amplitude [dB ] = 20 log

3) Larger resistance, better bass, smaller volume;

4) Larger capacitance, better bass, higher cost, larger PCB area.

(V_rms)²

5) Pout < Earphone speaker rated power

P_out=

6) example:

R 2

• (R1, C, Fc, Amplitude)

– (100ohm, 47uF, 25.65Hz, -12.3dB)

49

External RC value

▪ Different types of capacitors have different distortion.

– distortion: Tantalum cap. > MLCC X5R > MLCC Y5V

– Don’t use MLCC Y5V in audio path/ mic0/ FM_IN

• Capacitors’ THD+N vs. Frequency are showed as below:

• green: X5R (+/-10%); Audio Precision Analyzer Rin=100kohm

• red: X5R (+/-10%); Audio Precision Analyzer Rin=100kphm

• blue: Y5V (+80%, -20%); Audio Precision Analyzer Rin=300ohm

MediaTek

02/21/08 21:55:08

• cyan: Y5V (+8^E0^X%^TER,^NA-^L2^S0^OU%^RC)^E;^TA^HDu^+Nd^Vio^{S F}P^REr^Qe^Uc^ENi^Cs^Yion Analyzer Rin=300ohm

+0

-20

-40

d

B

-60

-80

-100

-120

20

50

100

200

500

1k

2k

5k

10k

20k

Hz

Sweep Trace Color

Line Style Thick Data

Axis Comment

1

2

5

7

1

Blue

Cyan

Green Solid

Red Solid

Solid

3

DSP Anlr.THD+N Ratio A Left 6238EVB (200mVrms, AA=100

DSP Anlr.THD+N Ratio A Left 6238EVB (200mVrms, AA=300

DSP Anlr.THD+N Ratio A Left 6235EVB (200mVrms, AA=100

DSP Anlr.THD+N Ratio A Left 6235EVB (200mVrms, AA=300

cap_THD+NvsFreq.at27

50

External RC value

▪ Tantalum capacitor

– Can’t be operated under reverse bias,

• HP EINT can’t be on earphone path.

– Permissible reverse voltage:

– The reason of damage by reverse voltage

• Reverse voltage will damage Ta2O5,

• After Ta2O5 is broken, there is large current passed through

tantalum capacitor.

51

External RC value

▪ HP EINT suggestion

– 18-pin I/O

• An extra pin for HP EINT and accessory need a pull-low resister.

– 6-pin earphone jack

• Two extra pull-low resistors on CH-L/R

L306

BLM18BD252SN1

MIC_HP

100

R308

C322

TCTP0J476M8R-Y2

CAP-0805

1

2

4

3

5

6

J302

earphone

2,3

MP3_OUTL

GND

MIC

OUTL

OUTR

NA

B300

B301

BLM18BD252SN1

0603

0402

C323

B302

0603

R380

4.7k

C324

33pF

100pF

2,3

AU_MOUTR

AU_MOUTL

MP3_OUTR

MP3_OUTL

2,3

NA

0402

MP3_ER

100

0402

TCTP0J476M8R-Y2

R312

C325

2,3

MP3_OUTR

VR318 VR317 VR316 VR315 VR314 PHONEJACK(AJR4R-6KXXX1)

C328

33pF

0402

CAP-0805

R381

4.7k

0402

C326

1nF

C327

1nF

C329

1nF

0402

0402 0402 0402 0402 0402

14

FM_ANT

0402

R314

0402

1K

2

EINT7_HEADSET

C330

2.2uF

0402

EINT7_HEADSET:

H= earphone plug in

L= earphone plug out

52

Audio Traces

▪ Crosstalk issue

– avoid CH-L and CH-R’s signal interfering to each other

– (1) PCB layout

• protected audio R & L stereo trace by GND separately.

Crosstalk=45dB

Crosstalk=70dB

53

In headset mode, please separate L/R channel and microphone trace by GND.

Audio Traces

▪ Crosstalk issue

– (2) earphone accessory:

• Separated GND of CH-L and CH-R.

• connect the GND of CH-L and CH-R at the end of earphone jack.

Not connect the GND at earphone microphone.

MIC+

L

HP

R

x

O

– (3) The bead at FM ANT on earphone path may degrade

crosstalk about 15dB.

• Choose bead with low DRC bead and good THD+N

• It is a trade-off between FM feature and crosstalk performance.

54

I/O connector (10pins)

▪ UART + USB + Earphone

VDD

T907

AVSC18S05E007

TP901

TP906 TP905

R916

47K

TN904

J903

1

2

1 UTXD1

TXD

D903

VCHG/USB_PWR

VCHG+

RXD

SDM20U40-7/RB520S-30

1

2

3

1 URXD1

4

1 USB_DM

D-

5

7 FM_ANT

GND_FM

D+

6

1 USB_DP

3 XMP3_L

L902BLM18BD252SN1

L903BLM18BD252SN1

L904BLM18BD252SN1

7

MP3_L

MIC

L901

BLM18BD252SN1-(0603)

8

3 XMIC

9

3 XMP3_R

MP3_R

AccDet

10

T911

T910

T909

C906

33p

C907

33p

C908

33p

C903 1n

C904 1n

C905 1n

ESD9X5.0ST5G

Mini 10pin I/O A

ESD9X5.0ST5G

R318

1K

1 EINT0_ACC_DET

HEADSET DETECTION

55

Case Study (1)

▪ Audio pop noise

– LoudSPK mode

• Tuning external audio amplifier ON/OFF delay time

• mp3_outL/R to external amplifier input must add coupling

capacitor to avoid voltage drop.

– Earphone mode

• Turn on de-pop function by software

• Tantalum capacitor +/- reverse mounting.

56

Case Study (2)

▪ Loudness without distortion

– LoudSPK mode

• Audio buffer gain <112

• Increase external audio amplifier gain

– Earphone mode

• Audio buffer gain <112

• decrease resistance on earphone path

– Increase capacitance for good bandwidth

– Microphone PGA

• uplink speech volume

– nvram_default_audio.c: #define GAIN_NOR_MIC_VOL3

– Engineering mode: audio, normal mode. microphone, volume3

• sound recorder/video recording volume

– nvram_default_audio.c: #define GAIN_NOR_MIC_VOL4

– Engineering mode: audio, normal mode. microphone, volume4

• FM recorded file playback

– Increase FM_record_PGA if FM playback volume is small.

– mcu\1audio\afe2.c: #define FM_RADIO_RECORDING_VOLUME

57

MT6516 Design Notice (Speech)

New Proposed Microphone Circuit

▪ Advantage

– 10uf capacitor is not needed any more

– Less passive components are needed

▪ Circuit: Normal mode

2

AU_MICBIAS_P

R302

2K

R300

2K

0402

VR300

0402

L300

C300

100nF

MIC/OD4/ID1

MIC

2

MICP0

2000@1GHz

0402

33pF

C306

MIC+

1

2

MIC300

33pF

C305

10K

R301

59

C310

100nF

2

MICN0

0402

New Proposed Microphone Circuit

▪ Circuit: Headset mode

AU_MICBIAS_P

R303

2K

C314

C318

100nF

2

MICN1

MICP1

0402

33pF

C332

0402

R306

2k

R317

10k

0402

C311

100pF

100nF

MIC_HP

0402

C321

33pF

R318

1k

0402

Headset GND

0402

2

AUXADIN5

60

New Proposed Microphone Circuit

▪ Layout consideration-Normal mode

2

AU_MICBIAS_P

Connect the 4 GND

together and then

connect to the main

GND by a single via

R302

2K

R300

2K

Should be routed in

differential

0402

VR300

0402

L300

C300

100nF

MIC/OD4/ID1

MIC

2

MICP0

2000@1GHz

0402

33pF

C306

MIC+

1

2

MIC300

33pF

C305

10K

R301

C310

100nF

Rload

2

MICN0

0402

Vr

Should be routed in

differential

61

New Proposed Microphone Circuit

▪ Layout consideration-Headset mode

AU_MICBIAS_P

Should be routed in

differential

R303

2K

C314

C318

100nF

2

MICN1

0402

33pF

C332

0402

R306

2k

R317

10k

0402

C311

100pF

100nF

MICP1

MIC_HP

0402

C321

33pF

0402

R318

1k

Should be routed in

differential

0402

Headset GND

0402

2

AUXADIN5

Connect the 4 GND

together and then

connect to the main

62

GND by a single via

How to Optimized Rload

▪ The Rload can be calculated by the follow procedure

– Measure the voltage on the microphone MIC_P in a quite

environment

– Select a Rload to let Vr has almost the same voltage as MIC_P

63

MT6516 Camera Design Notice

Camera Design Note – Parallel Interface

▪ All camera pins are dedicated

▪ Layout notice

– CMMCLK, CMPCLK need to be well shielded by GND plane

▪ BB side power level

– VDD33_CAMERA (AJ9, AK10) = Camera side IO level DOVDD

MT6516 (Pin definition)

AH8

Camera side

VSYNC

HSYNC

PCLK

J1

CMVREF

CMHREF

CMPCLK

CMMCLK

SDA1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VCAM_A

VCAM_D

AVDD

DVDD

DOVDD

DGND

AGND

STROBE

SIOD

AT2

CMSTROBE

SDA

SCL

R1

R2

4.7K

26

27

28

29

30

31

32

33

34

35

AG9

DGND

MDP1

MDN1

DGND

MCP

RDP1

RDN1

SIOC

CMRST

RESETB

VSYNC

HSYNC

PWDN

MCLK

CMVREF

CMHREF

CMPDN

CMMCLK

CMPCLK

CMDAT9

CMDAT8

CMDAT7

CMDAT6

CMDAT5

CMDAT4

CMDAT3

CMDAT2

CMDAT1

CMDAT0

AR3

MCLK

RCP

RCN

J2

MCN

AP2

SIOD

DGND

MDP0

MDN0

DGND

RDP0

RDN0

PCLK

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

DGND

SCL1

AG5

SIOC

VCAM_A VCAM_D

CMRST

CMPDN

AJ7

AM4

RESETB

PWDN

AV2,AL9,AT4,AM8,AU3

AN7,AN5,AK8,AP4,AL7

AN3

Hirose FX12B-40P-0.4SV

CMDAT0~CMDAT9

CAM_STROBE

DATA0 ~ DATA9

STROBE

65

Camera Design Note – MIPI (CSI-2) Interface

▪

All MIPI DSI pins are dedicated that connect from BB to LCM

–

1 CLK Lane + 2 Data Lanes

▪

BB side TVRT (pin G5) connect 1.8K 1% resistor to GND and close to BB

Layout notice

–

All signal pairs need to 50ohm impedance matching for single end and 100ohm for differential

All signal length need be equal and well shielded by GND plane

▪

BB side power level

–

VDD33_CAMERA (AJ9, AK10) = Camera side IO level DOVDD

DVDD12_MIPI (J7, K8) connect to VCORE(1.2V)

DVDD28_MIPITX (H8, J9), DVDD28_MIPIRX(J5), AVDD28_MIPITX (G7), and VDD33_MIPI (L11) connect to

VDD (2.8V)

MT6516 (Pin definition)

H2

Camera side

MDP1

J1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VCAM_A

VCAM_D

AVDD

DVDD

DOVDD

DGND

AGND

STROBE

SIOD

RDP1

RDN1

RCP

G1

G3

MDN1

CMSTROBE

SDA

SCL

R1

R2

4.7K

26

27

28

29

30

31

32

33

34

35

DGND

MDP1

MDN1

DGND

MCP

RDP1

RDN1

SIOC

MCP

CMRST

RESETB

VSYNC

HSYNC

PWDN

MCLK

CMVREF

CMHREF

CMPDN

CMMCLK

CMPCLK

CMDAT9

CMDAT8

CMDAT7

CMDAT6

CMDAT5

CMDAT4

CMDAT3

CMDAT2

CMDAT1

CMDAT0

RCP

RCN

F2

MCN

J2

MCN

DGND

MDP0

MDN0

DGND

RDP0

RDN0

PCLK

RDP0

RDN0

E3

MDP0

DATA9

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

DGND

VCAM_A VCAM_D

E1

MDN0

CMRST

CMPDN

AJ7

AM4

RESETB

PWDN

Hirose FX12B-40P-0.4SV

CAM_STROBE

AN3

STROBE

66

MT6516 LCM Design Notice

Display Interfaces

▪ Various Interface Support

– 8080 host IF (MIPI DBI)

– 8/9/16/32-bit Serial IF

– RGB interface (MIPI DPI)

– MIPI DSI interface

▪ High performance LCD controller enable wide range of display resolution

– Landscape or Portrait mode.

– From 128x96(SubQCIF) ~ 852x480(WVGA)

▪ Advance color processing

– Embedded LCD Gamma correction table.

– Color correction matrix.

– true color support.

– Contrast, brightness adjustment.

– 6 overlay layers with per-pixel alpha channel and gamma table

– 2x or 4x temporal dithering

68

Free Datasheet http://www.Datasheet-PDF.com/

LCM Design Note – CPU (Host) Interface

▪ LCM side must have FMARK(F_Sync) frame update HW pin

and need to connect to LPTE(W3) for tearing free Tier-1

performance

▪ LCM side IOVCC reserve VMEM(1.8V) & VDD(2.8V) option for

R505

3

1.8V NAND application

VMEM

2

1

VDD

C501

2.2u

0

▪ BB side power level

J500

1

2

3

4

5

6

7

8

9

VR501

IOVCC

VCI

– VDD33_NLD (pin AA9, AC9, W9) = LCM side IOVCC level

GND1

LED6A

LED5A

LED4A

LED3A

LED2A

LED1A

GND2

LCM_ID

LED_CA6

LED_CA5

LED_CA4

LED_CA3

LED_CA2

LED_CA1

R513

C500

2.2u

MT6516 (Pin definition)

LCM side

/CS

10

11

VR500

ADC2_LCMID

0

12

13

14

15

16

LPCE0B

LWRB

LPA0

W1

AA1

Y4

LPCE0B_MAIN_LCM

/CS

/WR

RS

/RD

/RESET

LWRB

LPA0

LRDB

/WR

LRSTB

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

37

NLD17

NLD16

NLD15

NLD14

NLD13

NLD12

NLD11

NLD10

NLD9

NLD8

NLD7

NLD6

NLD5

NLD4

NLD3

NLD2

NLD1

NLD0

LPTE

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

FMARK

RS

LRDB

Y2

/RD

LRSTB

W7

/RESET

AA5, AF2, AP6, AE3, AB8, AD4,

AC7, AJ1, AH2, AL1, AG3, AF4,

AC5, AK2, AD6, AJ3, AD8, AN1

NLD17~NLD0

LPTE

D17~D0

35

36

IM3

IM0

38

R504

NC

BLC

GPIO29_MAIN_LCM_BLC

39

40

41

42

43

44

W3

FMARK / F_Sync

GND3

XL

YD

XR

YU

TP_X-

TP_Y-

TP_X+

TP_Y+

GND4

LCD-44PIN-CON

69

LCM Design Note – RGB (DPI) Interface

▪

RGB (DPI) interface separated into two groups

– 3 wire (or 4 wire) SPI interface for LCM initial code setting

– Image databus (Dedicated pins and connect from BB to LCM directly)

Layout notice

– DPICK, LSCK must well isolated by GND plane

– All Image signal length need to be equal as best.

BB side power level

– VDD33_NLD (pin AA9, AC9, W9) = LCM side IOVCC(VDDI) level

MT6516 (Pin definition)

V4

LCM side

SPI_CS

SPI_SDI

SPI_CLK

VSYNC

HSYNC

DENB

LSCE0B

LSDA

U1

LSCK

U5

DPIVSYNC

DPIHSYNC

DPIDE

AA3

W5

AB2

AC1

DPICK

DCK

NLD8 ~ NLD13

NLD14 ~ NLD19

NLD20 ~ NLD25

LRSTB

AL1,AH2,AJ1,AC7,AD4,AB8

AE3,AB6,AF2,AA5,AG1,Y8

AC3,AA7,AD2,AE1,AB4,Y6

W7

B0 ~ B5

G0 ~ G5

R0 ~ R5

RST

70

LCM Design Note – MIPI (DSI) Interface

▪

All MIPI DSI pins are dedicated that connect from BB to LCM

–

1 CLK Lane + 2 Data Lanes

▪

F_Sync for MIPI DSI command mode connect to dedicated pin LPTE

BB side TVRT (pin G5) connect 1.8K 1% resistor to GND and close to BB

Layout notice

–

All signal pairs need to 50ohm impedance matching for single end and 100ohm for differential

All signal length need be equal and well shielded by GND plane

▪

BB side power level

–

VDD33_NLD (pin AA9, AC9, W9) = LCM side IOVCC(VDDI) level

DVDD12_MIPI (J7, K8) connect to VCORE(1.2V)

DVDD28_MIPITX (H8, J9), DVDD28_MIPIRX(J5), AVDD28_MIPITX (G7), and VDD33_MIPI (L11) connect to VDD (2.8V)

MT6516 (Pin definition)

C1

LCM side

TDP0

VCI_LCM

J1

PAD_TDP0

PAD_TDN0

PAD_TDP1

PAD_TDN1

PAD_TCP

PAD_TCN

LRSTB

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

GND

TDP0

TDN0

DATAP0

DATAN0

GND

DATAP1

DATAN1

GND

CLKP

CLKN

GND

VCI

RESET

GND

LEDA

LEDK

F_Sync

GND

D2

A3

B4

B2

C3

W7

W3

TDN0

TDP1

TDN1

TDP1

TCP

TCN

TDN1

LCM_RST

TCP

LEDA

LEDK

LPTE

TCN

RESET

F_Sync / TE

LPTE

71

High Speed Memory Layout Rule

Mobile DDR SDRAM

Outline

▪ Overview

▪ High speed memory layout considerations

–

Placement

Suggested routing order

Ground/Power plane

Signal layout

Other general layout considerations

▪ Check list

73

Overview

DDR SDRAM signals

▪ We can categorize DDR SDRAM interfaces into 4 groups as

follows.

▪ Signal quality could be degraded by any PCB layout issue.

▪ We must take care of different groups of DDR SDRAM.

74

High Speed Memory Layout Considerations

▪ It is recommended that the PCB layout of memory

interface is the first priority for your design.

▪ We can check memory PCB layout characteristics in

the following order:

1. Placement

2. Suggested routing order

3. Ground/Power plane

4. Signal layout

5. Other general layout considerations

75

High Speed Memory Layout Considerations

▪ Placement

– Memory device must place as close to BB Chip as possible

– Avoiding extra long trace (Max trace1500mil)

– Avoiding other high frequency devices place close to Memory

– Route these traces smoothly, reduce the via counts and avoiding traces

interlace if possible

– You can swap byte in order to reduce traces interlace if there has restriction in

placement (only for SD/DDR RAM)

Byte1

Byte0

Byte1

Byte0 Byte1

Byte1 Byte0

Swap

– “Swap byte” means to connect DQS0 from BB chip to memory DQS1 in order

to reduce the interlacing of data traces, e.g. D[0:7] from BB chip to memory

D[8:15].

– Note: Swap the corresponding DQS ,DQM and DQx at the same time.

76

High Speed Memory layout considerations

▪ Layout routing

– Please route traces by the following order:

1. Power/GND plane

2. Data group

3. Clock group

4. Command/Address/control groups

– Because high frequency signal integrity is highly related to

solid ground and power plane, data groups are operating at

twice the clock frequency.

– It is recommended that the designer takes care of the layout

routing in the very beginning of the design.

77

High Speed Memory Layout Considerations

▪ Ground/Power plane

– A solid power/ground plane must be provided near all traces routing layers.

– It will minimize the ground return current to get better performance.

– There are 2 methods for reference:

1. It is recommended all traces are routed above a solid GND plane, and there is a power

plane (memory power domain) under the GND plane if possible.

e.g. 1st layer : Traces

2^nd/3^rdlayer: Trace (strongly recommended - the same group of traces routed on the

same layer)

4rd layer: GND

5th layer: Power plane (VMEM) if possible, which is under the traces of memory interface.

BB

VMEM power trace

Traces

Power plane (VMEM)

Bypass cap of VMEM should be

connected to the power plane.

Memory

78

High Speed Memory Layout Considerations

2. All traces are routed above a solid GND plane , and under a DC

power plane (VBAT domain) to provide good shield (the traces

of memory interface protected by VBAT and GND)

e.g. 1st layer : VBAT

2nd layer: Trace (strongly recommended - the same group

of traces routed on the same layer)

3rd layer: Trace

4th layer: GND

Note: All power trace bypass capacitors must be placed as close to the

devices' power pins as possible, and all capacitor's GND should have

the shortest and widest trace to the GND plane.

79

Suggested Layer Definition

▪ Layer definition

– 相鄰層避免走平行線

6 Layer for EVB

L1 Signal (vertical)

L2 Signal (horizontal)

L3 GND

(0)

(X)

L4 Power

L5 Signal (vertical)

L6 Signal (horizontal)

L1

Signal

PP (3mil)

▪ Stack-up

PP厚度較薄,L1及L2的Signal有最

短的 return path

L2

Signal

PP (3mil)

GND

Core (廠商自行配)

POWER

L3

L4

L5

L6

建議CORE的厚度最厚,以保持其它

層的PP厚度較薄

PP (3mil)

Signal

PP厚度較薄,L5及L6的Signal有最

短的 return path

PP (3mil)

Signal

80

High Speed Memory Layout Considerations

▪ If we take a good power plane under traces, we can get good

power trace impedance performance.

No power plane

There are a power plane under memory

Interface traces

The impedance reduce to half

When added power plane

81

High Speed Memory Layout Considerations

Add a power plane on PCB to enhance performance (reducing signal jitter)

@IO pad

of receiver

Data jitter=1.22ns

Strobe jitter=145ps

Data jitter=1.04ns

Strobe jitter=85.6ps

Data jitter=0.892ns

Strobe jitter=78.5ps

@output

of receiver

Data jitter=1ns

Strobe jitter=348ps

Data jitter=0.775ns

Strobe jitter=261ps

@output

of receiver

Data jitter=0.584ns

Strobe jitter=110ps

@output

of receiver

@IO pad

of driver

@IO pad

of driver

@IO pad

of driver

P-P= 598mV

P-P= 499mV

P-P= 307mV

Added power

plane under BB

chip and DRAM

Best

Added a small

power plane

under BB chip

Better

Only power trace

Not good

82

High Speed Memory Layout Considerations

Signal layout

▪ We categorized all signals into 4

groups, prioritized as follows:

– 1st priority: Data group

– 2nd priority: Clock group

– 3rd priority: Control/Command

groups

▪ If possible, control trace

impedance between BB chip and

DRAM, trace impedance is

related to PCB dielectric constant,

trace width, trace thickness, and

routing method (using microstrip

or stripline).

▪ The performance will get better if

signal trace impedance is under

control.

83

High Speed Memory Layout Considerations

1. Data group (1/2)

– DQx and DQS must be routed in a group and routed in the same layer

and reduce via counts if possible.

e.g.

D[0:7] is aligned to DQS[0];

D[8:15] is aligned to DQS[1].

So, D[0:7] must be routed in a group with DQS[0],

and D[8:15] must be routed in a group with DQS[1].

84

High Speed Memory Layout Considerations

1. Data group (2/2) (Remind : power/GND plane is the most important)

–

Within the same data group: (Max. trace length – 500 mil )< Trace length < (Max. trace

length)

–

Between different data group: (Max. trace length – 500 mil )< Trace length < (Max. trace

length)

| DQS - Clock trace length | < 300 mil

–

If possible, control data trace impedance to ensure it meets the requirement

(please check input impedance of memory).

–

Within the same group if DQx trace width is W, the space between DQx is 1.5 W.

To reduce the crosstalk on DQSx , GND shielding is required.

If the trace width is W , the trace space between DQSx and GND is at least 1.5W, and the

width between DQS0 and DQS1 is at least 3W.

–

Do not route data group traces in parallel for a long distance.

Serpentine Spacing

DQSx

GND Via required on entire GND shield

12mil

DQS1 trace width: W

DQS0 trace width: W space width: 1.5W

85

High Speed Memory Layout Considerations

2. Clock group (1/2)

– There are a differential pair of high speed clocks in the DDR SDRAM memory

device, so we need to take care of these traces to ensure the clock integrity.

– Route these 2 clock traces in parallel and keep equal trace length.

– Control clock trace impedance (please check memory device). If clock trace is W the

space between clk and /clk is at least 1.5W and there need GND shield wrap around

the clock differential pair. The space GND and Clock trace at least 1.5W , and the

GND shield need enough GND via if we can not give enough GND via , we would

rather take GND shield off , and the space to adjacent signals is at least 2W.

Differential clock pair (trace width: W)

GND need GND VIA on whole GND shield

Space width 1.5W

1.5W

86

High Speed Memory Layout Considerations

2. Clock group (2/2)

– Away from other high frequency traces

– Each clock trace must have solid power and ground plane

near the entire route.

– Each clock trace is recommended to route on the same layer

to reduce Via number, and to keep the same trace

characteristics.

87

High Speed Memory Layout Considerations

3. Control/Command groups

▪ Every trace must have solid power and ground plane near the

entire route.

▪ Every trace is recommended to route on same layer to reduce Via

number, and to keep the same trace characteristics.

▪ Route address traces from priority A0 (most toggled ) to

A15 (less toggled), and A0 should be close to ground if possible.

|Trace length - Clock trace length| < 500 mil

Within CMD/ADR group:

|Max. (CMD/ADR trace length) – Min. (CMD/ADR trace length)|

<250 mil

▪ Remind : power ground is the most important , you just need to

meet the traces match criterion as possible

▪ If serpentine is needed , the spacing is at least 12mil

88

Check List

▪

Placement

–

Memory device must placed as close to the BB chip as possible.

Avoid extra long trace (Max. trace: 1500 mil) and other high frequency devices placed close to memory

Route these traces smoothly, reduce the Via counts and avoiding traces interlacing if possible

▪

Considerations on ground/power plane (power/GND plane is the most important )

–

It is recommended all traces to be routed above a solid GND plane, and there is a power plane (memory

power domain) under GND plane if possible.

e.g. 1st layer: Traces

2nd layer: Trace (strongly recommended — the same group of traces routed on the same layer)

3rd layer: GND

4th layer: Power plane (VMEM) if possible, the plane is under the traces of memory interface.

Or all traces are routed above a solid GND plane, and under a DC power plane (VBAT domain) to provide

a good shield (the traces of memory interface protected by VBAT and GND).

e.g. 1st layer : VBAT

2nd layer: Trace (strongly recommended — the same group of traces routed on the same layer)

3rd layer: Trace

4th layer: GND

▪

Trace length is as match as possible , All traces refer to clock , within 500mil length difference is

acceptable (DDR , DQS and DQ is a group , and DDR clock ,/clock are within 100mil)

If serpentine is needed , the spacing is at least 12mil

Serpentine Spacing

12mil

DQSx

89

MT6516 USB Design Notes

Schematics and Cable Design

MTK USB2.0 Solution Introduction

▪ This document introduces MTK USB2.0 design and some points for

attention.

– MTK USB2.0/ OTG device can operate at USB2.0 High-Speed (HS)

mode (480Mb/s) and Full-Speed (FS) mode (12Mb/s).

▪ General HS eye diagram is shown as below. The output swing is

differential 0.4V. Bad eye diagram will lead to certification fail or signal

integrity problem.

91

USB Pin Definition

▪ USB2.0 pin out description.

– General pins

1

Symbol

Type

IO

Description

PAD_USB_VBUS

* Comparator used for detecting changes of VBUS voltage.

2

3

4

5

PAD_USB_DM

PAD_USB_DP

AVDD3_USB

AVSS33_USB

IO

USB serial differential bus (minus)

USB serial differential bus (positive)

Analog 3.3V supply

VDD

GND Analog 3.3V ground

6

PAD_USB_VRT

IO

Analog 5.1K reference resistor

Analog 1.2V supply.

7

8

AVDD12_USB

AVSS12_USB

VDD

GND Analog 1.2V ground

– Optional pins for supporting OTG

9

Symbol

Type

IO

Description

PAD_USB_ID

Optional function for USB OTG ID pin for detecting

slave plug in.

92

Schematics Design for USB2.0 Device (2/2)

▪ MT6516 (Device Only)

Must be 5.1K ohm, 1%

Place close to IC

Don’t have to

connect VBUS/ID

Reserve bead and bypass capacitor

for USB 1.2, 3.3V Power

93

Schematics Design for USB2.0 High Speed

▪ Beware of USB_VRT pin should keep away from noise source and

high speed clock data like camera databus.

▪ Reserve 0402 cap (NC) on DP/DM for ESD protection and rise

time/fall time tuning for USB-IF compliance test.

▪ If want to get USB-IF OTG logo, should use micro-AB connector.

94

USB/ Charger Detection

▪ Used for MT6516 and later on MTK ICs (MT6268/MT6516/MT6253)

▪ When charger interrupt happens, turn on D- pull high 100K ohm

resistor and check the polarity of D-

– If the D- is LOW, it is USB charger, otherwise it is a standard or a non-

standard charger

Standard charger

side

Non-standard

charger side

Inside MTK USB

USB side

Inside MTK USB

D+ data line

VUSB

R4

VUSB

R4

VUSB

R4

R1

15K ohm

100K ohm

D- data line

R2

15K ohm

95

USB/ Charger Detection (Cont.)

▪ Then check whether it is standard or non-standard charger. Turn

on D+/D- internally 15K ohm pull low resistor and D+ 1.5K ohm

pull high resistor at the same time.

– Check D- polarity. If the D- is HIGH, it is standard charger, otherwise it

is a non-standard charger.

Standard charger

side

Non-standard

charger side

Inside MTK USB

VUSB

R3

1.5K ohm

D+ data line

D- data line

D+ data line

D- data line

R2

15K ohm

96

High Speed USB Layout Checklist (1/2)

▪ General design and layout rules

– With minimum trace lengths, route clock source and HS USB

differential pairs first. Keep maximum possible distance between

clocks/periodic signals to USB differential pairs to minimize crosstalk.

– Route HS USB signal pairs together with equal length by using a

minimum vias and corners. This reduces signal reflections and

impedance changes.

– Maintain parallelism between USB differential signals with the trace

spacing needed to achieve 90 ohms differential impedance.

– When it becomes necessary to turn 90°, use two 45° turns or an arc

instead of making a single 90° turn. This reduces reflections on the

signal by minimizing impedance discontinuities.

– Do not route USB traces under crystals, oscillators, clock synthesizers,

magnetic devices or ICs that use and/or duplicate clocks.

97

High Speed USB Layout Checklist (2/2)

▪ General design and layout rules (Conti.)

– Stubs on HS USB signals should be avoided, as stubs will cause

signal reflections and affect signal quality.

– Avoid crossing over anti-etch if possible. Crossing over anti-etch

(plane splits) increases inductance and radiation levels by forcing a

greater loop area. Likewise, avoid changing layers with high-speed

traces as much as practical.

– Keep HS USB signals away from high current area. The current

transient during state transitions could induce noise to USB.

98

Stubs

▪ Avoid creating unnecessary stubs on data lines, if a stub is

unavoidable (for example: ESD issue), please keep the stub as

short as possible.

Avoid creating stubs if possible

D-

D+

Proper way to connect

resistors or varistors

99

Poor Routing Techniques

▪ Cross a plane split.

▪ Creating a stub with a test point.

▪ Failure to maintain parallelism.

Failure to maintain parallelism

of USB2.0 data lines

Proper routing technique

maintains spacing guidelines

Ground or

Power plane

Don’t cross

plane splits

Avoid creating stubs

TP

100

Case Study (1/5)

▪ Case 1:

– 2A36/2A37 should be removed. Large cap at USB_DP/USB_DM will

lead to bad jitter performance.

– Measured eye at board is shown below. It will occur turn-around error

at system application.

101

Case Study (2/5)

▪ Case 2:

– After bead, at least 0.1uF capacitor between VDD33_USB,

VDD12_USB and ground must be added as follows.

– Measured eye diagram has bad jitter performance.

102

Case Study (3/5)

▪ Case 3:

– Some time we got worse jitter due to poor layout, then VUSB33 and

VUSB12 are coupled by noise.

– It is improved by increasing bypass capacitor C221 and C235.

Chip side

Improved after modification

Before modification

103

Case Study (4/5)

▪ Case 4:

– Customer wants to share USB data pins with audio/UART pins through the

same 5-wire USB connector by using analog switch.

– Different analog switches cause different attenuation of signals; please make

sure component and layout will get proper eye diagram.

– No suggestion on using analog switch, 11-pin USB connector could be used

instead.

Fairchild FSUSB42

Add different analog switch

Fairchild FSUSB30

Original design without analog switch

104

Case Study (5/5)

▪ Case 5:

– Sometimes customer may design a special connector for USB, such

as 18-pin I/O.

– Poor cable will cause poor performance.

– Please follow USB cable design guide.

Cable with large series resistance

Design with normal USB cable

105

Cable with proper series resistance

Conclusions

▪ Layout and component selection are critical for USB2.0

high speed performance

– Need to follow the design rule or there might be compatibility

issue happens

▪ Grounding and shielding are both critical when design

USB2.0 high speed capable cables

– It can maintain USB signal quality with little jitter/ signal

distortion caused by cable design

▪ Please refer to “MTK USB2.0/ OTG Design Guide “ for

more detail.

106

MT6516 Factory Mode &

Engineer Mode Notice

Engineer Mode and Factory mode

▪ Factory mode

– Enter phone menu

– Enter “*#66*# ”, then dial

▪ Engineer mode

– Enter phone menu

– Enter “*#3646633#”, then dial

108

Factory Mode Menu Tree

109

Engineer Mode Menu Tree

110

Flash Tool Download Flow

▪ Bootloader Download

Download Bootloader

– Use UART1 to

download bootloader

▪ Windows Mobile image

download

– Connect both UART1

and USB to download

full WinMo image

Download Image

▪ Flash tool can combine

the two steps above.

(Must connect both

UART1 and USB to PC

first !)

▪ Please refer to flash

tool document in detail.

111

Download tool

選擇 Load 目錄裡的

Flash.Bin

MT6516_mldrnandforMTK.nb0

MT6516_EBOOTNAND.nb0

Then press Download all

112

META Link (AP Side)

▪ Install Smartphone META tool.

▪ How to enter META mode (UART1)

– If target have not been in META mode, click “Reconnect” button, then connect

phone;

– Phone will power on and enter into META mode automatically

▪ UART can support up to 115200bps baud rate

113

META Link (Modem Side)

▪

Install smartphone META tool (for first time)

▪

Link UART4 on handset to PC

Open hyper terminal on PC and set correct

COM port and parameters.

▪

Press “send key” and “end key” to power on.

▪

Set boot to META mode: Enter 9->3->1

Enter 0->0, continue to boot to META mode

Close hyper terminal, switch UART4 to

UART1. (UART1 link to PC)

▪

Wait about 12 seconds.

Execute META tool

Choose UART and enable “connect target

already in META mode” in option menu.

▪

Can backup/restore calibration data in

“update parameter” as feature phone.

114

MT6516 Memory Support Plan

MTK MVG (Memory Verification Group)

Apr 2009

EDGE Smart Phone

Segment

Platform

EDGE Smart Phone

MT6516

(2G/1G) +1G (x32)

NAND + MobileDDR MCP

MCP

MCP Type

NAND(SLC, 2K page) + 133/166MHz MobileDDR

Samsung K522F1GACM-A060 (2G+1G, 1.8V*, BGA137) Æ W0919

Elpida EHD013011MA-60 (2G+1G, 1.8V, BGA137) Æ W0921

Toshiba TYA000B801CFLP40 (2G+1G, 1.8V, BGA137) Æ W0922

Numonyx NANDBAR4N5BZBC5E (2G+1G, 1.8V, BGA137) Æ W0923

Micron MT29C2G24MAKLAJA-6 (2G+1G, 1.8V, BGA137) Æ W0924

Hynix H8BCS0PJ0MCP-56M (1G+1G, 1.8V, BGA137) Æ W0925

Samsung K522H1GACD-A060 (2G+1G, 1.8V, BGA137) Æ W0926

Micron MT29C1G24MAVLAJA-6 (1G+1G, 1.8V, BGA137) Æ W0927

Micron MT29C1G24MACLAJA-6 (2G+1G, 1.8V, BGA137) Æ W0928

Memory P/N

(Week available)

* Voltage supply of NAND flash.

** For^Cd^oe^pv^yri^igc^he^ts^{© M}n^eo^dt^iai^Tn^ekc^Ilⁿu^cd^.e^Ald^{l rig}in^htsth^ree^serw^vee^de^.ks available, ¹p¹l⁶ease contact with MTK PM for status update.

Appendix

Peripherals Design Notice (GPS/DTV)

MT6516

WIFI/BT Co-module Application Note

2009/4

WCP/RP1/W.Wei

Outline

z Module function block and reference design

¾ Module function block

¾ Module reference design

¾ Reference interface assignment

¾ Key component list

zSchematic and layout design guide

¾ Schematic design guide

¾ Layout design guide

119

Wi-Fi/BT Combo Module Product Definition

▪ Full-featured Wi-Fi 802.11b/g and BT 2.1 + EDR combo module

▪ Small-size package: 9.5×10.5×1.4 mm LGA (< 10×10 mm)

▪ MTK’s proprietary superior Wi-Fi/BT co-existence performance

▪ Wi-Fi and BT co-existence shares the 26 MHz clock frequency.

▪ Metal EM interference shielding

▪ Antenna: Dual antenna (mandatory)/Single antenna (optional)

▪ RoHS complaint

Sample: Sep. 2008

MP: 2009/02

120

MTK Combo Module Block Diagram

3.3V

1.8V

ANT1

SDIO/SPI Interface

Switch

BPF

Balun

PA

Wi-Fi SoC

(MT5921P WLCSP)

GPIO

32k Sleep Clock

ANT2

Coexistence

EEPROM

Ref Clock

Combo

Filter

UART Interface

Bluetooth SOC

(MT6611 WLCSP)

PCM Interface

VBAT

Tx/Rx

121

Wi-Fi Features

▪

Advanced Wi-Fi features

– 802.11b/g/e/i/h/k/w compatible

– IEEE 802.11e QoS (WMM/WMM-PS)

– Background scan for specific SSID networks

– IEEE 802.11i advanced security (WEP/TKIP/AES/WPA/WPA2)

– 802.11e optional U-APSD, DLS

– 802.11 power saving mode

– Wakeup by specific packet (pattern search)

– Thermo-sensor to resist temperature change

▪

Voice over WLAN (VoWLAN)

– UMA (Unlicensed Mobile Access) technology

– VoIP over WLAN

Software support

– Win CE 5.0

– Win Mobile v5.0/6.1

– Win Mobile v7.0 (planning)

– Linux v2.6 (planning)

▪

Wi-Fi certified

122

Bluetooth Features

▪

Radio features

– Fully compliant with Bluetooth 2.1+EDR

– Low-IF Architecture with high performance linearity

– Supports Bluetooth class 2 and 3

– Tx transmit power: 4 dBm

– 90 dBm sensitivity with excellent interference rejection

performance

– 3.5 x 3.5 x 0.6 mm (max.), 0.5 mm pitch WLCSP

▪

Baseband features

– Up to 7 simultaneous active ACL links

– Supports 3 simultaneous SCO and eSCO links SCO and

scatternet

– Supports lower power mode

(Sniff, Hold and Park mode)

– Ultra low power consumption in sleep mode

– Supports AFH and PTA for WLAN/BT coexistence

MT6611 Function Block

Software features

– Supports standard HCI interface

– Supports more than 15 profiles in MediaTek platform

123

Module Share Clock with Daisy chain

●MT5921+Mt6611 Module

26MHz

OSC.

● WiFi power need to power on to keep daisy chain working normally.

● WiFi can be shut down only as BT power off.

124

Co-module Reference Design

0

R923

INPUT Power

0402

VBT

0

R924

0402

VDD18

VWIFI_3.0

R926

100k

R905

100k

R906

100k

R907

100k

R908

100k

ANT_SEL_N

ANT_SEL_P

C914

1uF 0402

U901

C913

4.7uF

R901

100k

R902

100K

DVDD28

0603

41

40

39

38

37

36

35

34

33

32

31

30

29

28

1

2

PAVDD33

TP902

SDIO_D1

SDIO_CMD

SDIO_D0

SDIO_D3

SDIO_CLK

SDIO_D2

2,5

VWIFI_3V3

PAVDD33

GND

SD_D1

SD_CMD

SD_D0

0402

3

2,5

WLAN_LED

GND

4

SD_D3

PAVDD33

5

2,5

GND

SD_CLK

SD_D2

TP30MIL

6

GND

BT_2V8

7

BT+WLAN MODULE

OSC_EN

BT_GPIO1

BT_VCC28OUT

GND

OSC_EN

WLAN_CLK

GND

WLAN_CLK

SRCKLENA

8

SDIO Interface

C900

2.2uF

9

C900 close to pin8

VDD18

BT_CLK

10

11

12

13

14

BT_CLK

BT_LDO28EN

BT_VBAT

BT_GPIO4

GND

VDD18

0R R903

0R R904

100K R909

0402

MM8130-2600B

C901

1uF 0402

BT_ANT

0603

2

BTLDO28EN

SRCLKENA

GND

J900

VBAT

0402

C902

4.7uF

1

4

2

BT_ANT

GND

PAD1.35X1.5

3

C903 1.2pF

0603

0402

WiFi_ANT

C906

NC

0402

C907

0.5pF

0402

ANT901

2

PADX2(2.X2.2/P2.5)

COAXIAL/CON/MM8130-2600B

CO_MODULE

1nH

J901 MM8130-2600B

2

1

4

R910

NC

0402

C908

3

L900

0402

L901

2.2pF

NC

UART

0402

Interface

COAXIAL/CON/MM8130-2600B

0R R911

2

GPIO123

GPIO115

GPIO122

BTLDO28EN

BT_32K

2

0R R912

0R R913

2

GPIO116

WLAN_32K

0R R918 0402

PCM

Interface

URXD3

UTXD3

2

INT_N

EINT5

2

0402

0R R914

BT_SYSRST_B

0R R915 0402

0402

2

EXT_RST_N

GPIO133_WIFI_EN

2

VWIFI_3V3

2

EINT1

BT_GPIO0

2

0402

+2.8V

Host UART CTS pin connect to GND

2,5

SDIO_D1

MC1DA1

2,5

2

DAICLK

BT_PCMCLK

BT_PCMIN 2

BT_PCMOUT

2

DAIPCMOUT

DAIPCMIN

DAISYNC

AME8801

SDIO_CMD

SDIO_D0

SDIO_D3

SDIO_CLK

SDIO_D2

MC1CM0

MC1DA0

MC1DA3

MC1CK

2

BT_PCMSYNC

2

1

2

3

5

4

Vin Vout

GND

Y900

C909

1uF

4

3

1

OSC_EN

VDD

E/D

C910

1uF

0603

C911

2.2uF

2,5

EN BYP

0R R927

RTS

0603

C912

1nF

0603

MC1DA2

2

GPIO132

BT_GPIO1

WLAN_CLK

BT_CLK

2

SOT-25-5

26MHz

Oscillator

125

O/P GND

R916

0R

0402

TCVCXO 26MHz

TCXO3225

0402

R917

910R

0402

Interface Assignment

Type

I/O

Function

BT_RSTB

BT_32K

Type

I/O

Function

WIFI_RSTB

WLAN_32K

GPIO122

GPIO115

UTXD3

GPIO133

GPIO116

MC1CM0

MC1DA0

MC1DA1

MC1DA2

MC1DA3

MC1CK

UART

PCM

URXD3

DAICLK

DAIPCMOUT

DAIPCMIN

DAISYNC

SDIO

I/F

I/O

INT5

WiFi_interrupt

I/O

INT1

BT_interrupt

●MT6611 PCM/UART power domain support 2.8~3.3v,

26MHz Oscillator List

not support 1.8V

Item

Part number

Vendor

Designator

Y900

SMA026000-3DR3T0

(Load 15pF, 2.8V~3.3V)

Aker

8W26000011

(Load 15pF, 2.8V~3.3V)

TXC

EPSON

亞陶

Y900

26MHz

Oscillator

SG-310SCN.

(Load 15pF, 2.8V~3.3V)

FK2600008

126

Y900

(Load 15pF, 2.8V~3.3V)

WiFi interface Selection

TRSW_N

ANT_SEL_P

0

1

SDIO

SPI

Main Clock Frequency Selection

WLAN_ACT

ANT_SEL_P

OSC_FREQ0

0

1

20MHz

26MHz

40MHz

●Fixed

0

1

0

127

Schematic Design Guide(1)_Power Supply

zPAVDD33 is a dedicated input pin for module internal PA power supply and please connect it to 3.3V.

zDVDD28, DVDD33 and DVDDMIO are the WiFi portion digital IO power source, please connected to 3.0V

for optimum Tx performance.

zVDD18 is the WiFi RF/analog/digital LDO input pin and can be connected to DC/DC 1.8V power source

without degrading the module performance.

1

2

41

40

39

38

37

36

35

34

33

32

PAVDD33

GND

SD_D1

SD_CMD

SD_D0

3

WLAN_LED

GND

4

SD_D3

5

GND

SD_CLK

SD_D2

6

GND

7

WiFi/BT MODULE

BT_GPIO1

BT_VCC28OUT

GND

OSC_EN

WLAN_CLK

GND

8

BT_VCC28OUT

9

10

VDD18

BT_CLK

VDD18

128

BT Power Domain (2)

▪ Distributed into two domains: V_BAT and 2.8V

– V_BAT power source could come from phone battery and BT_VCC28 is

the internal LDO output pin.

– The BT 2.8V internal LDO was controlled by BTLDO28EN pin connected

to host GPIO.

5

37

36

35

34

33

32

31

30

29

28

GND

SD_CLK

6

GND

SD_D2

BT_VCC28OUT

2.2uF

7

BT_GPIO1

BT_VCC28OUT

GND

OSC_EN

WLAN_CLK

GND

WiFi+BT MODULE

8

9

10

11

12

13

14

BT_CLK

BT_LDO28EN

BT_VBAT

BT_GPIO4

GND

VDD18

V_BAT

BTLDO28EN

SRCLKENA

GND

BT_ANT

GND

4.7uF

129

Schematic Design Guide(3)_Clock Source

zThe WiFi/BT device can share a same clock with a daisy chain function .This mechanism allows Bluetooth can

work normally without extra power consumption even WiFi operating in the sleep mode.

zThe oscillator with 2.8~3.3V operated voltage , 20ppm tolerance and 15pF load capacitance is recommended

●32KHz clock for device sleep mode

- The 32KHz source come from BB GPIO output..

25

BT_32K

(GPIO115)

50

(GPIO116)

WLAN_32K

130

Schematic Design Guide(4)_Interface

zPlease add 100K pull resistors for the SDIO data pin except SD_CLK pin.

zFor BT UART interface, please note to connect the MT6516 host UART CTS pin to GND.

BT UART Interface

WiFi SDIO Interface

131

MT5921 Power Sequence

In order to prevent from the IO driving unpredictable signals, it is

recommended that the 1.8V is applied before IO power or they are applied

at the same time.

132

MT5921 Power On /Reset Timing

The power on reset time is related to the frequency of main reference clock

source. The normal functions are not ready until the power-on-reset was done.

133

MT6611 Power On Initialization

▪ Hardware reset sequence & timing requirement

– (1) Set BT_LDO_EN to high

– (2) Wait for at least 2ms

– (3) Set BT_RESET to high

– (4) Wait for at least 1000ms

– (5) MT6611 is ready for receive HCI command

(5)

(4)

(3)

(2)

BT_RESET

(1)

BT_LDO_EN

134

Module Layout Guide – 1/4

Layer1

z Please place the bypass capacitors to the

3.3/2.8/1.8V power rail as close as possible.

z Please keep 50 ohm transmission for The

WiFi/BT RF trace.

zPlease isolate the WiFi/BT main clock

trace with GND

zPlease reserve the 9 square GND PAD for

better performance for module

WLAN_CLK

BT_ANT :50ohm trace

135

Reference Layout – 2/4

Layer1

Layer2

136

Reference Layout – 3/4

Layer3

Layer4

137

Reference Layout – 4/4

Layer6

Layer5

138

Module Footprint Layout Guide

Pin1

139

Module SMT Reflow profile

140

MT3326 Application Design Note

2009 / 04

Agenda

▪ MTK GPS Overview

– MT3326 GPS Feature

– MT3326 System Block

▪ MTK GPS Reference Design

– MT3326 Schematic Design Note

– MT3326 PCB Design Note

– MT3326 QVL

– MT3326 Debug SOP

– MT3326 ATE Tool

▪ MTK GPS Tier One Performance

▪ Summary

▪ Q&A

142

MT3326 Features

▪ Dimensions:

▪ Low Power Consumption:

– 48-pin QFN lead-free package (6 x 6 x 0.85 mm)

– Acquisition mode : 39 mA

– Tracking mode : 26 mA

▪ Specification:

– Host-based GPS receiver

– 22 tracking/66 acquisition channel GPS receiver

– Supports WAAS/EGNOS/MSAS/GAGAN

– Supports up to 210 PRN channels

– Jammer detection and reduction

– Indoor/outdoor multi-path detection and

compensation

– Supports A-GPS with FCC E911 compliance

– Maximum fix update rate up to 10 Hz

▪ Reference Clock Support:

– TCXO Frequency : 12.6 MHz ~ 40.0 MHz

MT3326

▪ Interfaces:

– 2 UARTs , SPI , I²C , GPIO

Compact Layout Area : 12 x 12 mm

143

MT3326 Functional Blocks

UART2_TX

UART2_RX

Passive Antenna

29_RX0

26_TX0

MT6516

External

LNA

BPI _BUS6

(Optional)

MTK GPS IC

MT3326

GPIO

SAW

GPS_PWR_EN

22_SYNC

TCXO

0.5 ppm

LDO

2V8

PMIC

2.8 V

MT6326

Optional: If 2.8V voltage can be provide by PMIC, the external LDO

can be eliminated.

• GPIO Pull Low Æ GPS Receiver Off

• GPIO Pull High Æ GPS Receiver On

144

MTK GPS Reference Design

MTK GPS Phone Total Solution

GPS Antenna Review

Tier-1 Field Trial

Reference Design

17 May 2000 13:18:10

17 May 2000 13:18:39

57 pF

CH1

S22

LOG

5

dB/

REF

0

dB

1

:

-29

.

366

dB

1

.

575

420

000

GHz

CH1

S22

1

U

FS

1

:

53

.

414

-824

.

22

m

122

.

1

.

575

420

000

GHz

PRm

CH1

Markers

CH1

Markers

PRm

MARKER

1

2

:

54

.

098

69

MARKER

1.57542 GHz

1

BW

:

.

019597108

576044505

GHz

-304

57604

m

1.57542 GHz

1

.

GHz

cent

:

1

3

:

-4

95

.

941

6016

Q

:

8

0

.

4

2

.

56624

GHz

4

:

40

.

080

146

1

_

l

o

s

:

-29

.

366

dB

Cor

Avg

10

Cor

Avg

10

-28

.

58584

Hld

1

2

3

4

1

2

CENTER

1

.

575

000

GHz

SPAN

.

200

000

GHz

CENTER

1

.

575

000

GHz

SPAN

.

200

000

GHz

MTK GPS SW Build in

Factory Tool Support

MTK GPS

Total Solution

146

MT3326 Reference Circuit

GPS RF front end

UART

TCXO

LDO

147

MT3326 Reference Circuit (2/4)

GPS RF Front End

Passive Antenna :

Decoupling Capacitor for

Noise filtering

Circular Polarization Patch

Antenna is recommend

Mixer Input Matching :

LNA Input Matching :

Please place these components

close to MT3326_Pin 46

Please place these

components close to LNA

Input

Antenna Matching

SAW Filter :

For filtering jamming

148

MT3326 Reference Circuit (3/4)

Frequency :16.368 MHz

TCXO

Frequency Stability : +/- 0.5ppm

TCXO

RAKON/IT3205BE/16.368MHz

2V8

4

3

C1011 10nF

2V8

Reserve 0 ohm to isolate the

impact of PCB GND

VCC OUT

C1013

1uF

1

2

NC

GND

U1007

temperature variation on TCXO.

R1001

0R

Stabilize the LDO output Voltage

LDO

TCXO VCC :

POWER

2V8

C1017

1uF

Avoid the noise interference for

frequency stability

U1005

4

1

3

VBAT

VIN VOUT

CE

C1018

1uF (X5R)

2 GP019_GPS_PWR_EN

XC6221A182NR

R1002

100K

GPIO from MT6516 to control

LDO On/ OFF

149

MT3326 Reference Circuit (4/4)

MT3326 Supply voltage :

*Analog Voltage : RF_1V5

* Digital Voltage : Core_1V2

GPS_UART0 connect to

MT6515 UART interface

LDO I/O P Capacitor :

Place these Capacitors close to the

MT3326 LDO input Pin and

output Pin for stabilizing voltage

Optional : Connect to MT6516 BPI_BUS.

150

PCB Design Flow

Layout 1:

Layout 2 :

Placement

RF Trace

TCXO --- Clock Trace

Layout 3:

Layout 5:

Layout 4:

LDO -- 2V8

Interface Connect with

MT6238

Digital Power -- Core_1V2

Analog Power -- RF_1V5

151

PCB Component Placement (1/3)

The route of reference clock is

the shortest to avoid interfering

by other noise

Keep the RF path from antenna to

MT3326 as short as possible

TCXO

MT3326

SAW Filter

LDO

External LNA

The Capacitors close to analog

and digital voltage output

152

PCB Component Placement (2/3)

If the location of GPS function block is far away from GPS antenna Pad, please

place the first-stage SAW filter and external LNA close to GPS antenna port for

reducing RF path loss.

SAW filter & External LNA

MT 3326

BAD !!

GOOD !!

153

GPS Antenna Placement (3/3)

GPS Antenna

12X12X7 Active Patch

BT Antenna

Metal PIFA is recommended.

It can be mounted on Speaker

Holder. Chip antenna is also

an option.

GPS Placement

10.5mmX10.4mm

Near GPS Antenna

90mm GND Length

for triple band

Pen

GSM Antenna

Material is plastic near GSM ANT.

Place GSM Cal Kit below pen. It

occupy less GSM ANT Area.

Metal monopole on bottom.

Avoid GSM TX interfere with

GPS RX.

15mm clearance

for triple band

154

Proposal of GPS Patch Antenna for Slim Phone

12mm

z Probe-Feed RHCP Patch (Fig.1)

Patch Size: 12X12X4, 13X13X4

Vendors: Whayu, Yageo, CIRO, Microgate, Amotech

z Probe-Feed LP Patch (Fig.2)

Patch Size: 15X10X4, 16X6X5

Vendors: Whayu, Yageo, CIRO, Microgate, Amotech

Fig.1

15mm / 16mm

12X12X4

15X10X4

16X6X5

Fig.2

155

PCB Layout Design Note (1)

▪ RF Part :

▪ RF Path keep as short as possible for reducing RF signal transmitted loss.

▪ All RF traces have to do impedance control (50 Ohm) for good sensitivity.

▪ RF traces route on the surface layer and far away from other high speed signal trace are

recommended.

▪ Isolate external LNA input and output pin by copper plane.

▪ To keep the digital signal trace far away from the GPS layout area.

▪ Clear the metal below all matching component area to reduce the parasitic capacitance.

Clear the metal below

the RF trace and Pad !!!

High Parasitic capacitance couldn’t

reach optimal RF match

156

PCB Layout Design Note (2)

▪ TCXO Part:

▪ Keep TCXO clock trace as short as possible.

▪ Keep the noisy traces far away from TCXO clock traces.

▪ TCXO clock traces enclosed by PCB copper is recommended.

▪ Position TCXO far away from any high temperature component like as GSM_PA to

avoid the frequency drift.

GPS signal Input

TCXO

TCXO Clock Input

Pin 46

MT3326

The Best Position :

Pin 11

1. Clock trace is the shortest

2. It’s easy to route

TCXO

157

PCB Layout Design Note (3)

▪ Power Line Part

▪ Power trace should keep as low impedance and adequately add de-coupling capacitor

^{for noise filtering}.

- Recommended width of power trace : Main Trace: 20 mils at least

Branch into IC pin/ball: 10 mils at least

▪ Keep de-coupling capacitors close to the power pin of GPS chipset and external LDO.

▪ Use many, many via holes to connect the power traces between layers.

Use many via holes to

connect the power traces

between layers

158

Qualified Vender List -- TCXO

Component

Part number

Manufacturer

Rakon

TEW

Vendor

IT3205BE/IT3205CE

TTS14NSB-A8

Aurum Tech Inc.

Unifirst Enterprise

TG-5005CE-21G

EPSON TOYOCOM EPSON TOYOCOM

TCXO (16.368 MHz)

+/- 0.5ppm

1300269-16-16.368MHz

KT3225F16368ACW28TA0

ENG3090B

ITTI

Kyocera

NDK

Kyocera

NDK

7Q16300001-16.368MHz

TXC

TCXO (16.368 MHz)

+/- 2.0ppm

TCO-5869M

EPSON TOYOCOM EPSON TOYOCOM

IT2205BE 16.368 MHz

Rakon

Aurum Tech Inc.

Kyocera

TCXO 2520

(16.368 MHz )

KT2520Y16368ACW28TMA Kyocera

159

Qualified Vender List -- LNA & LDO

Component

Part number

NJG1117HA8

Manufacturer

JRC

Vendor

東鞍

External LNA

UPC8231

NEC

MAX2659

MAXIM

Torex

AME

MAXIM

敏茜

XC6215/XC6401

AME8801CEEVZ

TK71728

LDO_2V8

AME

華成

TOKO

160

Qualified Vender List --GPS Antenna

Circular-Polarized Patch

Antenna Vendor

Size (mm³)

12X12X4, 13X13X4, 15X15X4

Whayu

Yageo

12X12X4, 15X15X4

15X15X4

Mag.layers

CIRO

12X12X4, 13X13X4, 15X15X4

13X13X4

Amotech

161

MT3326 HW Debug SOP

Verify voltage level of all power

Supplies

Check Connection of UART

TXD & RXD

Check GPS HW Configuration

GPIO Setting & PMIC 2.8V

GPS Function Ok!

162

MTK GPS Phone Manufacture Flow

MT3326 No need !!

Radiation

MiniGPS

FW

Download

Conductive

ATE

Assembly

Multi- Channel

Antenna

Single Channel

PCBA

Or Open Sky

Com port

Baud rate

Unit

CNR

Current is good?

Download OK?

TTFF and Hot Start

are good?

163

Mini GPS Tool (PC Version)

Feature

GPS Status

TTFF Test

NMEA Output

Update Rate

Baudrate

WAAS

Log NMEA

32 Channel

Firmware Ver.

Usage

Customers

Production line

End users

164

Test Instruments (1/2)

Multi-Channel GPS Satellite Simulation System

Spirent STR4500

Spirent GSS6560

165

Test Instruments (2/2)

Areoflex

Single channel GPS-101 GPS Satellite Simulator

VNA

SA

SG

NFA

166

DTV Application Note

Outline

z DTV function block and reference design

¾ DTV function block

¾ DTV reference design

zReference interface assignment and key component

¾ Reference interface assignment

¾ Key component

zSchematic and layout design guide

¾ Schematic design guide

¾ Layout design guide

168

DTV Function Block and Reference Design

DTV Function Block

z DTV solution consists of MT5151, MT5162 tuner and one low-power SDRAM. It's

integrated in MCM TFBGA-124 package to provide high integration level and high

performance solution.

z MTK DTV solution provides worldwide DVBT compliant standard in VHF and UHF

reception via the common SDIO/SPI interface.

I

Q

AGC

TSIF

I/Q ADC &

Time Domain

Freq. Domain

FEC

RF Interface

Processing

Silicon

Tuner

TSPD

I2C

Demod &

Time Slicing

CPU

TS Demux

Control

Low-Power

SDIO

SPI

Memory

Controller

Host

Interface

Memory

Host

MPE-FEC

SDRAM

170

DTV Reference Design (Dual-Band: VHF & UHF)

RF 2.8V

LDO

POWER

C1201

1uF

U1200

DTV_DVDD28

VCC_RF

4

1

3

VBAT

GPIO121_DTV_PWR_EN

VCC_RF

VIN VOUT

CE

0603

R1225

4.7K

R1202

NC

C1208

0.1UF

2

XC6221A282NR

SSOT-24-4/XC6221

C1123

1uF (X5R)

JTAG_TDO

TXD232A

TOP_MODE10

TOP_MODE8

0402

R1211

0402

100K

R1208

NC

R1210

4.7K

Strap Pin

DTV_DVDD28

C1203

DTV_DVDD12

C1204

DTV_VDD18Q

C1205

0402

RXD232A

0.1uF

4

RXD232A

TXD232A

0402

VCC_PA

DTV_2V8

TXD232A

0402

DTV_DVDD28

DTV_AVDD28

C1207

DTV_DVDD28

C1209

DTV_DVDD12

C1230

DTV_AVDD12

C1211

0603

2.2uF

0.1uF

VCC_RF

C1290

0.1uF

0402

CLOSE U1

0402

DTV_1V2

VCORE2

DTV_DVDD28

C1214

DTV_VDD18Q

C1215

DTV_VDD18

C1216

0402

1

TP1213

TP1214

DTV_AVDD12

DTV_DVDD12

26M XTAL

DTV_1V2

TP1215

TP30MIL

TP1216

TP30MIL

TP1213~1217

DTV_DVDD12

C1218

BLM15EG121SN1

L1204

0.1uF

TP1217

TP30MIL

Test pin靠近ball擺放

, 不要被其他數位線跨越

0603

2.2uF

TP30MIL

0402

VCC_RF

DTV_VDD18Q

DTV_AVDD28

C1224

DTV_VDD18

C1231

DTV_VDD18

C1225

C1221

0.1uF

VGP2

DTV_1V8

0.1uF

C1227

0402

0603

2.2uF

C1228

0.1uF

0402

CLOSE U1

0402

CLOSE U1

0402

CLOSE U1

DTV_VDD18

X1200

TXC 26M

C1232

NC

U1201

/MT5151_RESET

0402

2

GPIO128

3

1

UHF

OUT

VCON

Dig out layer

2 of this xtal

and layer is solide ground

3

Balun

0402

TCXO3225

SAW Filter

C1233 1uF

R13

T4

VCOMON

VCOREGOUT

VDD18

XTAL_P

LQW15AN19NG00

L1210

T14

T16

R15

P14

N13

P16

N15

M16

M14

L15

K16

H14

F14

G13

J15

H16

G15

F16

E15

D16

D14

B14

C13

E13

A13

A15

B16

C15

P4

R3

T2

R1

P2

N1

N3

M2

L3

K4

J5

H4

J1

G5

G7

J3

K2

L1

H2

G1

F4

G3

F2

E3

E1

D2

C1

B2

XOREGOU T

AVSS12_2

XOCR EG

AVDD12_2

AVDD12_1

AVSS12_1

DGND

VDD12

TSPD_TUNER

XTALPD

RESET_TUNER

EJTAG_TRST

EJTAG_TCK

EJTAG_TMS

EJTAG_TDI

EJTAG_TDO

EJTAG_RTCK

EJTAG_SRST

VDD28

DTV_VDD18

DTV_DVDD12

C12304402

470nF

VDD12

UHF

RXD232A

TXD232A

DTV_AVDD12

TP1200

0402

1

UART_RX

UART_TX

VDD28

VDD12

GND_SX1

VDD_SX1

VCOCREG

GND_SX1

GND_RX1

RFN_U

TP30MITLP1201

C1237

100pF

DTV_DVDD28

DTV_DVDD12

LQW15AN13NG00

U1202

LP92H (B8763)

VCC_RF BLM15EG121SN1

C1235

C1236

L1212

L1211

C1239

C1240

100pF

TP30MIL

0402

DTV_DVDD12

R1226

6.8pF

1

0402

In

0.1uF

LQW15AN19NG00

L1214

0402

5.6pF

L1213

12pF

0402

Z1206

0402

R1228

0402

C1241

82pF

JTAG_RST#

JTAG_TCK

JTAG_TMS

DTV ANT

R1227

0402

1

4

2

3

0402

1

TP1205

TP1206

NC

Unbal Bal

0402

C1253

LQW15AN15NG00

0402

L1215

nc

TP1207

TP30MIL

JTAG_TDI

TP1208

TP30MIL

GND Bal

JTAG_TDO

JTAG_RTCK

JTAG_SRST

DTV_DVDD28

DTV_DVDD12

LQW15AN15NG00

FILTER/SMD/LP92A/EPCOS

TP1209

TP30MIL

EJTAG Debug pin

RFP_U

RFN_L

RFP_L

VDD_RX1

VDD12

RESET

RFVGA_CTRL

DGND

0402

C1243

82pF

L1216

MT5151 MCM

TP1210

TP30MIL

DLP11SN900HL2

0.5pF

0402

(Test pin排列整齊

)

0402

TP1211

TP30MIL

0402

DTV_DVDD12

/MT5151_RESET

RF_AGC_T

J903 MM8130-2600B

PAD/1P/3.58X5.56

0402

BLM15EG121SN1

L/CHOKE/SMD/DLP11SN

VDD12

DGND

VCC_RF

C1244

C1245

100pF

2

1

0402

SPI_MISO

SPI_MOSI

MC2DA1 2,5

2,5

SDIO_DATA_3

SDIO_DATA_2

SDIO_DATA_1

SDIO_DATA_0

SDIO_CLK

SDIO_CMD

VDD28

0.1uF

ANT903

3

4

Put more ground via between UHF network and VHF

^netwB^orkalun

DGND

DTV_VDD18Q

DTV_DVDD28

SDIO/SPI MUX pin to MT6516

MC2DA0

MC2CK

MC2CM0

VDD18Q

VDD28

0402

DTV_DVDD28

VDD28

COAXIAL/CON/MM8130-2600B

VHF

SDIO is mux pin with SPI

D801

VHF

ESD1P0RFL

C1246

15nH, 5%, LQW15A, wirewound

L1239

27pF

6.8pF

L1240

R1230

33pF

Z1207

C1298

C1299

L1217

L1218

1

4

2

3

Unbal Bal

1000pF

L1219

33nH, 5%, LQW15A, wirewound

0402

LQW15AN82NG00

0402

LQW15ANR10J00

0402

R1231

12pF

R1232

NC

nc

VCC_RF

C1248

0402

GND Bal

0402

C1247

C1249

0.1uF

DLP11SN900HL2

C1213

22pF

L1241

LQW15AN33NG00

15pF

1000pF

0402

L/CHOKE/SMD/DLP11SN

TBGA124(7x7)/B0.32/P0.4/SMD

0402

靠近RFVGA_CTRL ball

R1233 1K

C1251R1234 1K

47nF

RF_AGC_T

RF_AGC

靠近RF_AGC ball

Diplexer &

ANT Matching

C1252

47n0F402

0402

VHF

Band-select

Sam modified 12/19

0402

Filter

171

DTV Reference Design (UHF band only)

RF 2.8V

LDO

POWER

C1201

1uF

U1200

DTV_DVDD28

VCC_RF

4

1

3

VBAT

GPIO121_DTV_PWR_EN

VIN VOUT

CE

0603

R1225

4.7K

R1202

NC

C1208

0.1UF

2

XC6221A282NR

SSOT-24-4/XC6221

C1123

1uF (X5R)

JTAG_TDO

TXD232A

TOP_MODE10

TOP_MODE8

0402

R1211

0402

100K

R1208

NC

R1210

4.7K

Strap Pin

DTV_DVDD28

C1203

DTV_DVDD12

C1204

DTV_VDD18Q

C1205

0402

RXD232A

0.1uF

4

RXD232A

TXD232A

0402

VCC_PA

DTV_2V8

TXD232A

0402

DTV_DVDD28

DTV_AVDD28

C1207

DTV_DVDD28

C1209

DTV_DVDD12

C1230

DTV_AVDD12

C1211

0603

2.2uF

0.1uF

VCC_RF

C1290

0.1uF

0402

CLOSE U1

0402

DTV_1V2

VCORE2

DTV_DVDD28

C1214

DTV_VDD18Q

C1215

DTV_VDD18

C1216

0402

1

TP1213

TP1214

TP1215

DTV_AVDD12

DTV_DVDD12

DTV_1V2

26M XTAL

, 不要被其他數位線跨越

TP30MIL

TP1216

TP30MIL

TP1213~1217

DTV_DVDD12

C1218

BLM15EG121SN1

L1204

0.1uF

TP1217

TP30MIL

Test pin靠近ball擺放

0603

2.2uF

TP30MIL

0402

VCC_RF

DTV_VDD18Q

DTV_AVDD28

C1224

DTV_VDD18

C1231

DTV_VDD18

C1225

C1221

0.1uF

VGP2

DTV_1V8

0.1uF

C1227

0402

0603

2.2uF

C1228

0.1uF

0402

CLOSE U1

0402

CLOSE U1

0402

CLOSE U1

DTV_VDD18

X1200

TXC 26M

C1232

NC

U1201

/MT5151_RESET

0402

2

GPIO128

3

1

OUT

VCON

Dig out layer

2 of this xtal

UHF

SAW Filter

Balun

and layer is solide ground

3

0402

TCXO3225

DTV ANT

C1233 1uF

R13

T4

VCOMON

VCOREGOUT

VDD18

XTAL_P

LQW15AN19NG00

L1210

T14

T16

R15

P14

N13

P16

N15

M16

M14

L15

K16

H14

F14

G13

J15

H16

G15

F16

E15

D16

D14

B14

C13

E13

A13

A15

B16

C15

P4

R3

T2

R1

P2

N1

N3

M2

L3

XOREGOUT

AVSS12_2

XOCREG

AVDD12_2

AVDD12_1

AVSS12_1

DGND

VDD12

TSPD_TUNER

XTALPD

RESET_TUNER

EJTAG_TRST

EJTAG_TCK

EJTAG_TMS

EJTAG_TDI

EJTAG_TDO

EJTAG_RTCK

EJTAG_SRST

VDD28

DTV_VDD18

DTV_DVDD12

C12304402

470nF

VDD12

UHF

RXD232A

TXD232A

DTV_AVDD12

TP1200

0402

1

UART_RX

UART_TX

VDD28

VDD12

GND_SX1

VDD_SX1

VCOCREG

GND_SX1

GND_RX1

RFN_U

TP30MITLP1201

C1237

100pF

PAD/1P/3.58X5.56

ANT903

DTV_DVDD28

DTV_DVDD12

J903 MM8130-2600B LQW15AN13NG00

L1212

U1202

LP92H (B8763)

VCC_RF BLM15EG121SN1

L1211

C1239

C1240

100pF

TP30MIL

0402

DTV_DVDD12

R1226

6.8pF

2

1

0402

In

0.1uF

3

4

LQW15AN19NG00

L1214

K4

J5

0402

Z1206

R1228

NC

C1241

82pF

0402

JTAG_RST#

JTAG_TCK

JTAG_TMS

R1227

0402

1

2

3

0402

H4

J1

G5

G7

J3

1

TP1205

TP1206

Unbal Bal

0402

C1253

LQW15AN15NG00

L1215

nc

TP1207

TP30MIL

JTAG_TDI

4

TP1208

TP30MIL

GND Bal

JTAG_TDO

JTAG_RTCK

JTAG_SRST

DTV_DVDD28

DTV_DVDD12

FILTER/SMD/LP92A/EPCOS

TP1209

TP30MIL

EJTAG Debug pin

(Test pin排列整齊

RFP_U

RFN_L

RFP_L

VDD_RX1

VDD12

RESET

0402

C1243

82pF

L1216

MT5151 MCM

K2

L1

TP1210

TP30MIL

DLP11SN900HL2

0.5pF

0402

)

D801

TP1211

TP30MIL

H2

G1

F4

G3

F2

E3

E1

D2

C1

B2

TP30MIL

0402

DTV_DVDD12

/MT5151_RESET

RF_AGC_T

ESD1P0RFL

0402

BLM15EG121SN1

L/CHOKE/SMD/DLP11SN

VDD12

DGND

VCC_RF

C1244

C1245

100pF

Put more ground via between UHF network

0402

SPI_MISO

SPI_MOSI

MC2DA1 2,5

2,5

RFVGA_CTRL

DGND

SDIO_DATA_3

SDIO_DATA_2

SDIO_DATA_1

SDIO_DATA_0

SDIO_CLK

SDIO_CMD

VDD28

0.1uF

2,5

DGND

DTV_VDD18Q

DTV_DVDD28

SDIO/SPI MUX pin to MT6516

MC2DA0

MC2CK

COAXIAL/CON/MM8130-2600B

VDD18Q

VDD28

0402

MC2CM0

DTV_DVDD28

VDD28

SDIO is mux pin with SPI

Delete VHF network

For UHF band only

ANT Matching &

RF connector

VCC_RF

C1249

0.1uF

TBGA124(7x7)/B0.32/P0.4/SMD

0402

靠近RFVGA_CTRL ball

R1233 1K

C1251R1234 1K

47nF

RF_AGC_T

RF_AGC

靠近RF_AGC ball

C1252

47n0F402

0402

172

Reference Interface Assignment and

Key Component

Reference Interface Assignment

Type

GPIO

Function

RSTB

LDO EN

GPIO128

GPIO121

MC0CM0

MC0DA0

MC0DA1

MC0DA2

MC0DA3

MC0CK

SDIO (4-bit)

RSTB

MT5151 BGA

SDIO

I/F

2.8V 1.8V 1.2V

2.8V

RF LDO

PMU

Example in MT6516

LDO EN

174

Key Component

z There are four key components on DVBT reference design, SAW filter,

crystal, Balun, and high Q wirewround inductor.

Item

Filter

Part number

B8763 (LP92H)

FL2600025

Vendor

EPCOS

eCERA

Murata

Designator

U1202

Crystal

Balun

X1200

DLP11SN900HL2

Z1206, Z1207

L1212,L1210,L1214,L1239,L1241,L1240

L1213,L1217,L1218

Inductor

LQW15A series

Murata

175

Schematic and Layout Design Guide

Schematic Design Guide

z The ESD protection of RF input is poor, ESD device should be added to

protect RF circuit.

z UHF SAW filter & VHF hybrid filter should be added in RF path to filter

out-band and GSM interference signal.

z To ensure good performance, the frequency accuracy of crystal should

meet +/- 30 ppm requirement with loading capacitance SPEC of 10pF.

z In order to have better power noise immunity, RF 2.8V supply voltage is

provided by stand-alone LDO.

z IO-2.8V and SDRAM-1.8V should be provided by linear regulation power.

Core-1.2V could be DC-DC power.

z RF Balun is strongly suggested to use for optimal RF performance

177

DTV Layout Guide – 1/3

BT+WLAN

z DTV placement should keep away

DTV

from GSM and CDMA related

circuits.

GPS

z Don't place DTV near noisy

components, such as PMIC,

memory or other clock-wise/ high-

swing signal.

MT6516

z RF trace of DTV should keep

away from high speed signal, such

as LCD and camera data bus.

PMIC

z To avoid any other noisy layout

closer to RF ANT port

GSM

RF

GSM

PA

z Put solid ground polygon and

ground via surround layout area for

metal casing.

178

DTV Layout Guide – 2/3

z Keep RF trace on same layer, don't use

via on RF trace as possible as you can.

RF

Front-end

RF

Balun

z To avoid interference, use shielding case

to cover DTV related circuits.

Bypass

Cap. C1204

z Put RF Balun as closer as possible to chip

input. And Make routing symmetrically.

Bypass

Cap. C1203

z Put RF front-end routing in 50ohm trace

and let those inductors in orthogonal

direction with each others.

Shielding

case

RFAGC out

R-C

z Place 2.8V RF LDO and crystal near to

Bypass

Cap. C1209

MT5151 as possible as you can.

z Dig out the copper plating under Crystal

pad output (pin3) to chip in inner layer .

RFAGC In

R-C

crystal

z RF trace should keep 50ohm impedance

and as short as possible.

Bypass

Cap. C1214

z Place bypass capacitors close to power

pin.

Bypass

Cap. C1230

z Put DTV’s off-chip components surround

by it in sequence to minimize rounting.

z Put RFAGC in/ out R-C network as closer

as possible to pin

179

DTV Layout Guide – 3/3

z As below shown, make a dig-out clearance

Dig-out

Layer2

Layer3

gap (>= 6mil) to cut ground plane from

layer 2 to layer 6 to isolate RF and digital

GND.

Dig-out

z Dig out layer 2 ploygon under RF front-end

network

Start to cut

GND plane

Balls inside this RF

Area:

End to cut

GND plane

B16~P16;G15~N15;F14~M14;

G13;D12~H12;E11~L11;F10~K10

;G9~L9;F8~K8

180

Reference Layout – 1/4

Layer1

Layer2

181

Reference Layout – 2/4

Layer3

Layer4

182

Reference Layout – 3/4

Layer5

Layer6

183

Reference Layout – 4/4

Layer7

Layer8

(other function

placement

instead of DTV)

184

www.mediatek.com

FM Radio Design Guidelines

MTK FM Solution Connection

FM audio

output

MTK BB series

(except MT6205)

MT6188 or

MT6189CN

System audio

output

Control interface

187

FM Design

188

Layout Guidelines

▪ Placement

– Place the FM chip near the earphone jack. Avoid high-speed digital devices, such as

memory devices, near the RF signal area.

– Bypass cap for power should be placed beside the VCCVCO pin (MT6188 pin 9; MT6189

pin 13).

▪ Routing

– FM antenna trace should have a 50Ω impedance.

– Power should be routed to the bypass cap and the VCCVCO pin first, then to all other

power pins on the FM chip. See the following pages for example.

– Apply a single solid ground for all FM block ground signals. See the following pages for

example.

– Protect the following areas with GND vias and planes:

•

RF signal from the earphone jack all the way to the FM chip;

32.768 kHz or 26 MHz signal;

VCO inductor (MT6188 pins 11,12; MT6189 pins 15,16);

Loop filter of MT6189 (connected to pin 17).

189

Power Feeding Network Layout Guidelines

▪ It is recommended to connect power of MT6189 and MT6188 sequentially, and

placing the capacitance beside VCCVCO. (Examples below.)

▪ The FM power should be monopolized: do not connect other blocks to VCC_FM.

This capacitor cannot

be placed here.

Do not connect to other

blocks through FM block.

Bad

Good

VDD

VCCAMP

VDD

VCCST

VCCRF

VCCST

VCCRF

VCCVCO

MT6188

MT6189

190

Ground Layout

▪ Ground GNDVCO, the loop filter, and front-end matching on the same

ground plane.

– Using different ground planes connected by wire makes the FM signal

susceptible to interference with another signals on the system.

– This rule is applicable for both MT6189 and MT6188: all GND pins must be

located on the same ground plane.

All ground pins are connected by wires.

This design contains no ground plane.

Bad

Good

MT6189

191

Other System Considerations for FM

▪ Rule 1: Protect the BB 32.768kHz crystal layout

– If the 32.768kHz signal is corrupted by digital signals, FM channel locking may

be unstable.

– BB 32.768kHz crystal layout rules:

• Place the 32.768kHz crystal unit close to the BB, and L2 beneath crystal

needs to be complete ground. The crystal must be protected by ground

vias and ground planes.

• Do not route power, MCP, FM I2C traces near 32.768kHz crystal unit.

• The 32.768kHz traces between crystal unit and BB should be on top layer.

▪ Rule 2: Backlight driver adoption

– USE a charge pump backlight driver.

– DO NOT USE a DC-DC backlight driver in projects with FM application. Doing

so may cause increased noise levels when the backlight is on.

192

Audio Interface Design

▪ 2.5mm/3.5mm Earphone

▪ Mini USB Earphone

193

Audio Interface Design Guidelines

▪ On earphone pins AFL, AFR, and MIC:

– Place 1 nF shunt capacitors (shunt to earphone GND pin) closest to the

earphone jack.

To improve earphone echo performance, connect the 3 capacitors from each

pin to the earphone GND pin separately. (See next page.)

– Place the BLM18BD252SN1 series bead second closest to the earphone

jack.

– No other components can be closer to the earphone jack.

▪ Place a series 150 nH inductor on earphone GND pin as antenna

matching.

▪ Earphone GND wire (FM_ANT) should not be connected to the

earphone connector shell.

▪ An earphone longer than 150 cm is recommended for better

performance.

194

Audio Interface Design Concept

Add beads on headset related pins, to

avoid interference (or bypass) path.

Add caps on L, R paths, to

provide extra path for FM.

These beads should be placed as close

to the phone jack as possible.

Matching

inductor

Earphone Connector

FM tuner

MT6188

FM_ANT

Earphone_GND

MIC

22uH

MIC

E-L

MIC

E-L

E-R

NC

L

R

E-R

others

This point is the

earphone GND.

PCB

Earphone

195

Wireless Sensitivity Enhancement

▪ Each earphone suggestions improves wireless sensitivity

significantly. The following table shows the improvement amount

based on MTK’s experiments.

Improvement

amount

Series beads on earphone AFL, AFR, and

MIC pins

14.5 dB

1 nF shunt cap between earphone AFL,

2~3 dB

AFR, MIC, and GND pins

Earphone length > 150 cm

1~2 dB

196

2.5mm/3.5mm Earphone Design

197

Audio Interface Reference Circuit

(2.5mm or 3.5mm Earphone Jack)

Shunt these earphone

lines with 1nF caps.

Add beads on these lines. These beads should be

placed as close to the earphone jack as possible.

B401 2500 Ohm @ 100 MHz

B402 2500 Ohm @ 100 MHz

B403 2500 Ohm @ 100 MHz

To audio amp,

mic circuits

1

2

XMICP

C401

1nF

J401

1

XSPK_R

XSPK_L

3

5

4

2

XSPK_R

XSPK_L

C402

1nF

6

7_{NP_NC1}

8 _{NP_NC2}

MINI_JACK_6P

C403

1nF

C404

33pF

C405

33pF

ESD400

VCE

ESD401

ESD402

VCE

L101

1

2

L101

22uH

150nH

FM_ANT {1}

Connect this 22uH inductor to mobile

phone ground. BLM18BD252SN1 can

be used instead of a 22 uH inductor.

Series 150 nH inductor

for antenna matching.

These caps cannot be closer to

the earphone jack than the beads.

198

Mini USB Earphone Design

▪ With only 1 GND pin on IO connector

▪ With 2 GND pins on IO connector

199

Mini USB IO Connector Design Recommendation:

Only 1 GND Pin on IO Connector

Charger: Connect these pins.

Earphone: DO NOT connect these pins.

Accessory interior design suggestion

▪

The earphone GND wire MUST be used for the FM

antenna. Inside the earphone, the GND wire CANNOT be

connected to any other wire or to the outer shell in any way.

Other wires inside the earphone CANNOT be connected to

PCB GND.

▪

The 22uH inductor cannot tolerate high current. For high

current application, such as a charger, connect the charger

GND wire inside the charger to both the GND/FM_ANT pin

and the charger outer shell.

In this example, the earphone GND wire is connected to IO

connector pin6, and the charger GND wire is connected to

pin6 and the charger outer shell.

Earphone GND wire connection.

Charger GND wire connection.

IO connector pin description

IO pin name

Function

Notes for PCB design

GND for all Mini USB accessories and FM

antenna.

CANNOT be directly connected to PCB ground. MUST be

connected to PCB ground through a 22uH inductor.

GND/FM ANT

4 outer shell pins of the IO connector. Mainly

used for better connector strength. Can also

serve as charger GND.

These 4 pins are directly connected to PCB ground.

DO NOT connect these pins to the GND/FM_ANT pin.

MECH_GND

200

Audio Interface Reference Circuit:

Only 1 GND Pin on IO Connector

Series 150 nH inductor

for antenna matching.

L201

Connect this 22uH inductor

to mobile phone ground.

FM_ANT

150nH

L202

22uH

Shunt these earphone lines with 1nF caps.

To audio amp,

mic circuits

IO200

T205

VCE

1

2

11

12

13

14

NC

MECH_GND

L204

MP3_OUTL0

MP3_OUTL

MP3_OUTR

UTXD1

BLM18BD252SN1

C223

1nF

3

MP3_OUTR0

T204

L205

UTXD1

URXD1

4

BLM18BD252SN1

ESD203

C225

1nF

5

URXD1

VCE

6

GND/FM_ANT

MIC_IN

C224

1nF

7

MIC0

L206

8

USB_DM

USB_DP

VCHG

BLM18BD252SN1

T204

VCE

9

USB_DM0

USB_DP0

R209

R210

33R

10

Mini USB 10 Pin Plug

VCHG

These caps cannot be

closer to the earphone

jack than the beads.

Add beads on these lines. These

beads should be placed as close to

the earphone jack as possible.

T211

ESD210

201

Mini USB IO Connector Design Recommendation:

2 GND Pins on IO Connector

Inside earphone, DO NOT

connect these pins.

Accessory interior design suggestion

▪

The earphone GND wire MUST be used for the FM antenna.

Inside the earphone, the GND wire CANNOT be connected to

any other wire or to the outer shell in any way. Other wires

inside the earphone CANNOT be connected to PCB GND.

The 22uH inductor cannot tolerate high current. For high

current applications, such as a charger, use another IO

connector pin if available. The charger GND wire inside the

charger can also be connected to the charger outer shell.

In this example, the earphone GND wire is connected to IO

connector pin6, and the charger GND wire is connected to

pin1 and possibly the charger outer shell as well.

Charger GND

wire connection

Earphone GND

wire connection

IO connector pin description

IO pin name

Function

Note for PCB design

Earphone GND, also FM antenna.

CANNOT be directly connected to PCB ground. MUST be

connected to PCB ground through a 22uH inductor.

EAR_GND/FM_ANT

CKT_GND

GND for Mini USB accessory, with large GND

current.

This pin is directly connected to PCB ground.

DO NOT connect this pin to the EAR_GND/FM_ANT pin.

4 outer shell pins of the IO connector. Mainly

used for better connector strength. Can also be

served as charger GND.

These 4 pins are directly connected to PCB ground.

DO NOT connect these pins to EAR_GND/FM_ANT.

MECH_GND

202

Audio Interface Reference Circuit:

2 GND Pins on IO Connector

Series 150 nH

inductor for

antenna matching.

Connect this 22uH inductor

to mobile phone ground.

L201

FM_ANT

150nH

L202

22uH

Shunt these earphone

lines with 1nF caps.

To audio amp,

mic circuits

IO200

T205

VCE

1

2

11

CKT_GND

MP3_OUTL

MP3_OUTR

UTXD1

MECH_GND

L204

MP3_OUTL0

12

13

14

BLM18BD252SN1

C223

1nF

3

MP3_OUTR0

T204

L205

UTXD1

URXD1

4

BLM18BD252SN1

ESD203

C225

1nF

5

URXD1

VCE

6

GND/FM_ANT

MIC_IN

C224

1nF

7

MIC0

L206

8

USB_DM

USB_DP

VCHG

BLM18BD252SN1

T204

VCE

9

USB_DM0

USB_DP0

R209

R210

33R

10

Mini USB 10 Pin Plug

VCHG

These caps cannot be

closer to the earphone

jack than the beads.

Add beads on these lines. These

beads should be placed as close to

the earphone jack as possible.

T211

203

ESD210

Component Replacement Suggestions

▪ Series beads on earphone pins AFL, AFR, and MIC

– Suggested: 0603-size BLM18BD252SN1 bead

However, if board space is limited, 0402-size bead BLM15BD182SN1 or

BLM15HD182SN1 can be used instead.

▪ Inductor connecting earphone GND wire to board GND

– Suggested: 22 uH inductor or BLM18BD252SN1 bead

However, if the earphone GND pin serves as the only GND path for the

charger, then this component must be able to tolerate high current. The

components in the table below can be used instead.

Murata

part number

Inductor

value

Self-resonant

frequency

Rated

current

Size

Notes

LQH2MCN1R0M02

LQM21PN1R0MC0D

1.0 uH

0603

0805

100 MHz

90 MHz

485 mA

800 mA

Usable, but its wireless performance is the worst

among the three. Not recommended unless such a

high current is required.

LQM21PNR47MC0D

0.47 uH

0805

100 MHz

1100 mA

204

FM Design Checklist

Item

Done!

Checkpoint

1

Series beads are placed on the AFL, AFR, and MIC pins of the earphone jack.

□

1 nF shunt caps are placed between the AFL, AFR, MIC, and GND pins of the earphone

jack.

2

3

4

5

6

7

8

□

The earphone is longer than 150 cm.

The VCC bypass cap is placed beside the VCCVCO pin, and the VCC feeding network

routed is properly.

Follow the FM system layout guide.

The FM antenna path is routed using a 50Ω RF trace, and a 150 nH inductor is used for

antenna matching.

MT6189 projects only: A high Q inductor is used (for the 15 nH VCO inductor).

Mini USB earphones: Follow MTK’s suggestion for GND connection on PCB and inside

earphone.

If you require MTK’s assistance in FM design, please prepare this checklist and submit it

along with schematics, layout files and earphone schematics/data sheet.

205

More Detailed FM Earphone

Antenna Illustrations

▪ Illustration of FM earphone antenna

▪ FM earphone antenna pin definition

▪ FM earphone antenna troubleshooting

206

Illustration of FM Earphone Antenna (1/2)

▪ On next page, there is an illustration to explain the respective purposes of each

components. It can help customers to know how to enhance FM wireless

performance.

▪ Besides FM schematics, wrong earphone pin definition also destroys FM wireless

performance.

▪ Notice that the only one path from Earphone_GND to PCB_GND is via FM_ANT

Pin and 22uH. If there are another paths existing, FM receiving signal would

degrade seriously. This issues frequently happens on customers’ projects.

▪ Four pins are enough on earphone including R, L, MIC, and Earphone_GND.

▪ Only Earphone_GND can be used as FM Antenna.

▪ Place all FM related components near earphone jack in PCB layout.

207

Illustration of FM Earphone Antenna (2/2)

4. 150 nH

Earphone antenna

matching

1. Serial Beads 2.5 kOhm @100MHz

5. Earphone length

Avoid FM signal loss through R, L,

and MIC traces.

165 cm is recommended.

4

3

1

2

5

Earphone Connector

FM_ANT Earphone_GND

MIC MIC

22uH

FM tuner

MT6188

MIC

150 nH

L

E-L

E-R

E-L

E-R

NC

R

50 ohm

others

PCB

Earphone

3. 22 uH

● Earphone GND connects to

2. Parallel 1.0 nF CAP_short @100MHz

PCB GND only via this 22 uH.

Conduct FM signal to FM input from R, L, and MIC

traces. FM receiving signal can be enhanced.

● RF choke @100MHz

208

FM Earphone Antenna Pin Definition (1/3)

▪ The following illustrates the correct pin definition for the FM

earphone antenna:

Earphone Connector

PCB

Earphone

FM_ANT

Earphone_GND

MIC

E-L

MIC

E-L

E-R

NC

E-R

PCB_GND

others

209

FM Earphone Antenna Pin Definition (2/3)

▪ Some incorrect pin definitions

– Case 1: Floating FM_ANT pin

PCB

Earphone

FM_ANT

MIC

E-L

E-R

Earphone_GND

PCB_GND

others

– Case 2: Earphone_GND connects to both FM_ANT pin and PCB_GND

PCB

Earphone

Earphone_GND

FM_ANT

MIC

E-L

MIC

E-L

E-R

GND

E-R

PCB_GND

others

210

FM Earphone Antenna Pin Definition (3/3)

▪ Some incorrect pin definitions

– Case 3: Unnecessary GND pin used on the earphone side

PCB

Earphone

Earphone_GND

FM_ANT

MIC

E-L

MIC

E-L

E-R

GND

E-R

PCB_GND

others

– Case 4: Unnecessary signal pins used on the earphone side

PCB

Earphone

Earphone_GND

FM_ANT

MIC

E-L

E-R

MIC

E-L

E-R

PCB_GND

others

211

FM Earphone Antenna Troubleshooting

▪ Simple troubleshooting techniques:

a. Check that only four earphone pins are used. (Case 3, Case 4)

b. Remove the 22 uH inductor.

c. Plug in the earphone.

d. Use a digital multimeter to check whether the connections between PCB_GND,

FM_ANT pin, and Earphone_GND pin are OPEN or SHORT.

FM_ANT

to

FM_ANT

to

PCB_GND

to

Issue

Earphone_GND

PCB_GND

Earphone_GND

SHORT

OPEN

SHORT

Correct

Case 1

Case 2

SHORT

212


型号：	IT3205BE
厂家：	ETC
描述：	MT6516 Design Notice V1.0
文件：	总212页 (文件大小：6493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IT3205BE [ETC]

相关型号：

IT3205CE

IT3420-10

IT3420-10A

IT3420-12

IT3420-12A

IT3420-16

IT3420-16A

IT3420-20

IT3420-20A

IT3420-24

IT3420-24A

IT3420-28