KAC-1310_技术文档

IMAGE SENSOR SOLUTIONS

D E V I C E

P E R F O R M A N C E

S P E C I F I C A T I O N

KODAK KAC-1310

Image Sensor

1280 (H) x 1024 (V)

SXGA CMOS Image Sensor

November 7, 2002

Revision 4

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IMAGE SENSOR SOLUTIONS

TABLE OF CONTENTS

TABLE OF FIGURES........................................... 3

TIMING ............................................................... 31

START OF ROW READOUT (SOF)...................... 31

HORIZONTAL DATA SYNC (VCLK) ..................... 31

DATA VALID (HCLK)......................................... 31

STROBE SIGNAL ............................................... 33

Example Timing Summary:........................ 35

LIST OF TABLES................................................. 3

SUMMARY SPECIFICATION .............................. 5

PIN DEFINITIONS................................................ 6

RECOMMENDED HARDWARE FOR KAC-1310

SENSOR EVALUATION: ........................................ 7

I²C-COMPATIBLE SERIAL INTERFACE.......... 36

KAC-1310 I²C BUS PROTOCOL........................ 37

START SIGNAL................................................ 37

SLAVE ADDRESS TRANSMISSION ....................... 37

ACKNOWLEDGMENT.......................................... 37

DATA TRANSFER .............................................. 37

STOP SIGNAL ................................................... 37

REPEATED START SIGNAL............................... 38

I²C BUS CLOCKING AND SYNCHRONIZATION....... 38

REGISTER WRITE ............................................. 38

REGISTER READ............................................... 38

DEVICE DESCRIPTION....................................... 8

PIXEL ARCHITECTURE....................................... 10

COLOR FILTERS AND LENSLETS......................... 11

FRAME CAPTURE MODES.................................. 11

CONTINUOUS FRAME ROLLING SHUTTER CAPTURE

MODE (CFRS) ................................................. 11

CFRS VIDEO ENCODED DATA STREAM............. 12

SINGLE FRAME ROLLING SHUTTER CAPTURE MODE

(SFRS) ........................................................... 12

WINDOW OF INTEREST (WOI) CONTROL............ 12

SUB-SAMPLING CONTROL (RESOLUTION) .......... 12

VIRTUAL FRAME (VF)........................................ 13

REGISTER LIST REFERENCE......................... 41

C^INF^TR^EGS^RI^AN^TT^IOEG^NR^TA^IMTI^EON^...T^..I^.M^...E^..^....^..^...^..^..^..^..^..^..^...^..^..^....^....^..^..^....^....^...^...^....^..^..^..^.1¹3³

SFRS INTEGRATION TIME................................. 14

FRAME RATE.................................................... 14

CFRS FRAME RATE ......................................... 14

SFRS FRAME RATE ......................................... 15

ANALOG SIGNAL PROCESSING CHAIN..... 16

(ASP).............................................................. 16

FRAME RATE CLAMP (FRC).............................. 16

COLUMN DIGITAL OFFSET VOLTAGE ADJUST

DETAILED REGISTER BLOCK ASSIGNMENTS

............................................................................ 44

COLOR GAIN REGISTERS 00_HÆ 03_H.................. 44

REFERENCE VOLTAGE ADJUST REGISTERS (0A_H,

0B_H)................................................................. 46

POWER CONFIGURATION REGISTERS (0C_H) ....... 47

RESET CONTROL REGISTER (0E_H)..................... 48

EXPOSURE GAIN A REGISTER (10_H) .................. 49

TRISTATE CONTROL REGISTER (12_H)................. 49

COLUMN DOVA DC REGISTER (20_H) ................ 51

EXPOSURE GAINB (21_H) ................................... 52

PGA GAIN MODE (22_H)..................................... 53

ADC DOVA (23_H)............................................ 54

CAPTURE MODE CONTROL (40_H)....................... 55

SUB-SAMPLE CONTROL (41_H)............................ 56

TRIGGER AND STROBE CONTROL REGISTER

(42_H)................................................................ 57

PROGRAMMABLE WINDOW OF INTEREST (WOI)

(45_H-4C_H)......................................................... 58

INTEGRATION TIME CONTROL (4E_HÆ 4F_H) ........ 61

PROGRAMMABLE VIRTUAL FRAME (50_HÆ 53_H) .. 62

SOF AND VCLK DELAY REGISTERS (54_HAND 55_H)

........................................................................ 64

SOF & VCLK WIDTH REGISTER (56_H) .............. 65

READOUT DIRECTION REGISTER (57_H)............... 66

INTERNAL TIMING CONTROL REGISTERS (5F_HAND

60_H)................................................................. 67

CLAMP CONTROL AND HCLK DELAY REGISTER

(64_H)................................................................ 68

ENCODED SYNC REGISTER (65_H)...................... 69

MOD64 COLUMN OFFSET CORRECTION REGISTER

(80_H-BF_H)......................................................... 70

(CDOVA) ........................................................ 16

PROGRAMMABLE GAIN AMPLIFIER (PGA) .......... 17

^GAR^INa^Mw^OG^Da^Ei^Sn^..M^...o^..d^..e^..:^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^..^....^....^....^..^..^...^...^....^.1¹7⁷

Lin1 Gain Mode:......................................... 17

Lin2 Gain Mode:......................................... 17

WHITE BALANCE CONTROL PGA (WB GAIN)..... 19

EXPOSURE GAIN PGA (EXP GAIN A/B) ............. 20

GLOBAL DIGITAL OFFSET VOLTAGE ADJUST

(GDOVA)........................................................ 20

ANALOG TO DIGITAL CONVERTER (ADC) ........... 20

PERFORMANCE................................................ 21

TEST CONDITIONS ............................................ 21

IMAGING PERFORMANCE................................... 21

QUANTUM EFFICIENCY...................................... 23

DYNAMIC RANGE .............................................. 25

TEMPORAL NOISE............................................. 25

OPERATION ...................................................... 28

INITIALIZATION (STANDBY MODE)....................... 28

STANDBY MODE ............................................... 28

OUTPUT TRISTATE............................................ 28

READOUT ORDER ............................................. 28

READOUT SPEED.............................................. 29

INTERNAL BIAS CURRENT CONTROL .................. 30

STORAGE AND HANDLING............................. 71

MECHANICAL DRAWINGS .............................. 73

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IMAGE SENSOR SOLUTIONS

QUALITY ASSURANCE AND RELIABILITY.... 75

Table 3 continued. Electro-Optical Characteristics

............................................................................ 22

Table 4: Absolute Maximum Ratings.................. 26

Table 5: Recommended Operating Conditions .. 26

Table 6: DC Electrical Characteristics................ 27

Table 7: Power Dissipation................................. 27

Table 8: Pixel Data Bus and Sync Timing

ORDERING INFORMATION.............................. 76

AVAILABLE PART CONFIGURATIONS................... 76

TABLE OF FIGURES

Figure 1. Pinout Diagram...................................... 6

Figure 2: KAC-1310 Pin Connection Schematic .. 7

Figure 3: KAC-1310 Block Diagram ..................... 8

Figure 4: Optional Bayer RGB Pattern CFA....... 11

Figure 5: Optional Bayer CMY Pattern CFA....... 11

Figure 6: Increase of sensitivity due to microlenses

............................................................................ 11

Figure 7: WOI Definition ..................................... 12

Figure 8: Virtual Frame Definition....................... 13

Figure 9: RGB Bayer ½ x ½ Sub-sample Example.

Sub-sample Control Register(41_h) = xxx10101_b. 13

Figure 10: Conceptual block diagram of CDS.... 16

Figure 11: FRC Conceptual Block Diagram ....... 16

Figure 12: PGA Gain Modes .............................. 18

Figure 13: Color Gain Register Selection........... 19

Figure 14: KAC-1310 Typical Monochrome

Specification ....................................................... 32

Table 9: I²C-compatible Serial Interface Timing

Specification ....................................................... 40

Table 10. I²C Address Range Assignments....... 41

Table 11: I²C Address Assignments (0_h- 3F_h) .... 42

Table 12: I²C Address Assignments (40_h- FF_h). 43

Table 13: PGA Color 1 Gain Register (00_h)........ 44

Table 14: PGA Color 2 Gain Register (01_h)........ 45

Table 15: PGA Color 3 Gain Register (02_h)........ 45

Table 16: PGA Color 4 Gain Register (03_h)........ 45

Table 17: Negative Voltage Reference Register

(0A_h).................................................................... 46

Table 18: Positive Voltage Reference Register

(0B_h).................................................................... 46

Table 19: Power Configuration Register (0C_h)... 47

Table 20: Reset Control Register (0E_h).............. 48

Table 21: A Exposure Gain A Register (10_h)...... 49

Table 22: Tristate Control Register (12_h)............ 50

Table 23: Column DOVA DC Offset (20_h) .......... 51

Table 24: Exposure Gain B (21_h)........................ 52

Table 25: PGA Gain Mode (22_h)......................... 53

Table 26: ADC DOVA Register (23_h).................. 54

Table 27: Capture Mode Register (40_h).............. 55

Table 28: Sub-Sample Control Register (41_h).... 56

Table 29: TRIGGER and STROBE Control

Spectral Response ............................................. 23

Figure 15: KAC-1310 Typical Bayer RGB Spectral

Response............................................................ 23

Figure 16: KAC-1310 Typical Bayer CMY Spectral

Response............................................................ 24

Figure 17: Dynamic Range with respect to Mclk

Frequency........................................................... 25

Figure 18: Temporal Noise Dependence on

External Resistor ................................................ 25

Figure 19: Power Consumption Dependence on

External Resistor ................................................ 30

Figure 20: CFRS Default Frame Sync Waveforms

............................................................................ 31

Figure 21: CFRS Default Row Sync Waveforms 32

Figure 22: Single Frame Capture Mode (SFRS) 32

Figure 23: Pixel Data Bus Timing Diagram ........ 33

Figure 24: STROBE Output Waveforms ............ 34

Figure 25: I²C Bus WRITE Cycle........................ 36

Figure 26: I²C Bus READ Cycle ......................... 39

Figure 27: I²C Bus Timing................................... 40

Figure 28: Recommended Reflow Soldering

Register (42_h)...................................................... 57

Table 30: WOI Row Pointer MSB Register (45_h) 58

Table 31: WOI Row Pointer LSB Register (46_h). 58

Table 32: WOI Column Pointer MSB Register (49_h)

............................................................................ 59

Table 33: WOI Column Pointer LSB Register (4A_h)

............................................................................ 59

Table 34: WOI Row Depth MSB Register (47_h) . 59

Table 35: WOI Row Depth LSB Register (48_h) .. 60

Table 36: WOI Column Width MSB Register (4B_h)

............................................................................ 60

Table 37: WOI Column Width LSB Register (4C_h)

............................................................................ 60

Table 38: Integration Time MSB Register (4E_h). 61

Table 39: Integration Time LSB Register (4F_h) .. 61

Table 40: Virtual Frame Row Depth MSB (50_h) . 62

Table 41: Virtual Frame Row Depth LSB (51_h) .. 62

Table 42: Virtual Frame Column Width MSB (52_h)

............................................................................ 63

Table 43: Virtual Frame Column Width LSB (53_h)

............................................................................ 63

Table 44: SOF Delay Register (54_h)................... 64

Table 45: VCLK Delay Register (55_h)................. 64

Table 46: SOF & VCLK Width Register (56_h)..... 65

System Thermal Profile ...................................... 72

Figure 29: 48-Pin Terminal Ceramic Leadless Chip

Carrier (Bottom View)......................................... 73

Figure 30: CLCC-IB package vertical

Dimensioning...................................................... 74

LIST OF TABLES

Table 1: KAC-1310 Pin Definitions....................... 6

Table 2. Video Encoded Signal Definitions ........ 12

Table 3. Electro-Optical Characteristics............. 21

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IMAGE SENSOR SOLUTIONS

Table 47: Readout Direction Register (57_h)........ 66

Table 48: Internal Timing Control Register (5F_h) 67

Table 49: Internal Timing Control Register (60_h) 67

Table 50: Clamp Control and HCLK Delay

Register (64_h)...................................................... 68

Table 51: Encoded Sync Register (65_h) ............. 69

Table 52: Mod64 Column Offset Correction

Register (80_h-BF_h)............................................... 70

Table 53: 48 Ceramic LCC – Matrix Format....... 74

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IMAGE SENSOR SOLUTIONS

SUMMARY SPECIFICATION

KODAK KAC-1310 SXGA CMOS

IMAGE SENSOR 1280 (H) x 1024 (V)

Parameter

Value

Total Number of Pixels

1296 (H) x 1046 (V)

Number of Effective

Pixels

1288 (H) x 1032 (V)

Number of Active Pixels

Pixel Size

1280 (H) x 1024 (V)

6.0 µm (H) x 6.0 µm (V)

7.68 mm (H) x 6.14mm (V)

(~1/2”)

Imager Size

Chip Size

14.22 mm (H) x 14.22 mm (V)

40% mono / 64% color

5:4

Optical Fill-Factor

Aspect Ratio

Features

SUMMARY SPECIFICATION

•

½” Color SXGA Advanced CMOS Image Sensor

1280 x 1024 active imaging pixels - progressive

scan

Saturation Signal

Quantum Efficiency

Responsivity

40,000 electrons

46% peak CMY

1.2 V/Lux-sec peak CMY

70 e- rms

•

Monochrome or Bayer (RGB or CMY) Color Filters

6.0µm pitch square pixels with microlenses

Kodak patented pinned photodiode architecture;

high blue QE, low dark current, lag free

High sensitivity, quantum efficiency, and charge

conversion efficiency

•

Total Dark Noise

Dark Current

True Correlated Double Sampling for low read

noise

6250 e-/pixel/sec

•

Low fixed pattern noise and wide dynamic range

Antiblooming control and Continuous variable

speed rolling electronic shutter

Dark Current Doubling

Temperature

9

^oC

•

Single 3.3V power supply; Single master clock

Digitally programmable via I²C-compatible interface

Dynamic Range

>54dB

200x

Pixel addressability to support ‘Window of Interest’

Blooming Suppression

windowing, resolution, and sub-sampling

•

External sync signal for use with strobe flash

On-chip 20x programmable gain for white balance

and exposure gain

•

10-bit, pipelined algorithmic RSD ADC

15 fps full SXGA at 20MHz Master Clock Rate

48 pin CLCC package

Dark reference pixels with automatic Frame Rate

Dark Clamp

•

Encoded Sync data stream

Column offset correction circuitry

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IMAGE SENSOR SOLUTIONS

PIN DEFINITIONS

42

41

40

39

38

37

36

35

34

33

32

31

0.205" (5.21mm)

Legend:

P = VDD

G = VSS

I = Input

Optical

Center

O = Output

D = Digital

A = Analog

Column

0

Die Center

1

Die Placement

position tolerance

±100um (±4mil)

2

3

4

5

Row 0

0.002" (52um)

(0,0)

0.280" (7.11mm)

6

10

11

12

13

14

15

16

17

18

7

8

9

Figure 1. Pinout Diagram

No.

Description

Power Value

Description

Power Value

No. Name

Type

Name

Type

1

2

3

4

5

6

7

8

9

INIT

VDD

Sensor Initialize

Digital Power

I

D

25 VDD_PIX

Pixel Array Power

Analog Ground

Digital Ground

Digital Power

P

G

P

A

D

3.3 V

0 V

P

G

P

O

I

D

A

3.3 V

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

VSSA

VSS

Digital Ground

0 V

VSSA

VDDA

CFRCA

CFRCB

TST_VRO

TST_VSO

Analog Ground

VDD

3.3 V

3.3k Ω

Analog Power

3.3 V

0.1µF

SCLK

SDATA

PIX0

PIX1

PIX2

PIX3

PIX4

VDD

I²C Serial Clock Line

I²C Serial Data Line

Output Bit 0=1₁₀Weight

Output Bit 1=2₁₀Weight

Output Bit 2=4₁₀Weight

Output Bit 3=8₁₀Weight

Output Bit 4=16₁₀Weight

Digital Power

I/O

O

P

Frame Rate Clamp Capacitor A

Frame Rate Clamp Capacitor B

Analog Test Reference Output

Analog Test Signal Output

Analog Test Reference Input

Analog Test Signal Input

Analog Ground

10 TST_VRI

11 TST_VSI

12 VSSA

13 VDDA

14 CVREFM

15 CVREFP

16 CVAGA

17 VAGRET

18 CVAGB

19 EXTRESA

20 EXTRESB

I

G

P

O

I

A

0 V

3.3 V

0 V

Analog Power

3.3 V

0.1µF

VSS

Digital Ground

G

O

I

ADC Bottom Bias Ref Capacitor

ADC Top Bias Ref Capacitor

Common Mode Capacitor Input

Return for VAG external caps

Common Mode Reference Capacitor

External Bias Resistor

PIX5

PIX6

PIX7

PIX8

PIX9

MCLK

VCLK

HCLK

Output Bit 5=32₁₀Weight

Output Bit 6=64₁₀Weight

Output Bit 7=128₁₀Weight

Output Bit 8=256₁₀Weight

Output Bit 9=512₁₀Weight

Master Clock = Pixel Rate

Line Sync

0.1µF

39k Ω

External Bias Resistor

I

O

I

21

NC

Pixel Sync

22 VSSA

23 VDDA

24 TST_INJ

Analog Ground

Analog Power

G

P

I

A

0 V

46 TRIGGER

47 STROBE External Sync for Strobe Flash

48 SOF Start of Frame Sync

Sensor Trigger Signal

3.3 V

O

Pixel Row 1046./1047 Inj Bbias In

Table 1: KAC-1310 Pin Definitions

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IMAGE SENSOR SOLUTIONS

ANALOG Ferrite

VDD

Ferrite

DIGITAL

VDD

0.1uF 0.01uF 0.001uF

0.001uF 0.01uF 0.1uF

GND

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

INIT

SOF

STROBE

TRIGGER

HCLK

VCLK

MCLK

PIX9

VDD

3

VSS

4

VSSA

5

VDDA

0.1 uF

6

CFRCA

CFRCB

TST_VRO

TST_VSO

TST_VRI

TST_VSI

VSSA

0.1 uF

7

8

PIX8

9

PIX7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

PIX6

PIX5

VSS

VDDA

VDD

0.1 uF

CVREFM

CVREFP

PIX4

PIX3

CVAGA

VAGRET

CVAGB

EXTRESA

EXTRESB

TST_BGV

VSSA

PIX2

0.1 uF

PIX1

0.1 uF

PIX0

SDATA

SCLK

VDD

39K ohm

VSS

VSSA

VDD_PIX

VDDA

TST_INJ

GND

Figure 2: KAC-1310 Pin Connection Schematic

Recommended Hardware for KAC-1310 Sensor Evaluation:

1. Kodak Evaluation Board and cable (for parts list and pricing contact our Sales Office @

http://www.kodak.com/go/imagers)

2. National Instruments Framegrabber PCI-1422 LVDS (http://www.ni.com)

3. Calibre I²C Adapter PCI93 LV (http://www.calibreuk.com)

4. Windows NT, 98 or 2000 Operating System.

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IMAGE SENSOR SOLUTIONS

DEVICE DESCRIPTION

TEST TEST TEST TEST TEST TEST

8

9

10 11 21 24

1296

2Dark + 4Isolation

SOF 48

VCLK

44

HCLK 45

47

STROBE

SXGA ACI Image Sensor Array

TRIGGER 46

INIT

MCLK 43

1

PIX0

PIX1

PIX2

PIX3

PIX4

PIX5

PIX6

PIX7

PIX8

PIX9

1280

31

32

33

34

35

38

39

40

41

42

12Dark + 4Isolation

1

0

1

Column

Sequencer

& Drivers

Column Decode, Sensing, CDS, and Muxing

^-3.10 → 8.76 dB

^-6.38 → 17.49 dB

Exposure

PGA A&B

0.48 →

WB

PGA

10 Bit

RSD

Pipelined

ADC

CFRCA

CFRCB

Frame

Rate

Clamp

6

7

Global

Dova

1.5x

3.5dB

Column

DOVA

2.0x

6dB

0.70 →

2.74x

7.49x

6

CVREFM

14

Mux and

Bandgap

6

Color Sequencer

CVREFP 15

I²C Serial

Reference

and Bias

30 SDATA

6

EXTRESA

Interface and

19

SCLK

Generation

29

Register Decode

EXTRESB

20

16 17 18

3

4

12 22 26 27 37

36 28

2

5

13 23 25

Figure 3: KAC-1310 Block Diagram

The KAC-1310 is a solid state CMOS Active

CMOS Imager (ACI^TM) that integrates the

functionality of complete analog image acquisition,

digitizer, and digital signal processing system on a

single chip. The image sensor comprises a SXGA

format pixel array with 1280x1024 active

elements. The image size is fully programmable

to user-defined windows of interest. The pixels

are on a 6.0µm pitch. High sensitivity and low

sensor is available in a Monochrome version

without microlenses, or Bayer (RGB or CMY)

patterned Color Filter Arrays (CFAs) with standard

microlenses to further enhance sensitivity.

Integrated timing and programming controls allow

video or still image capture progressive scan

modes. Frame rates are programmable while

keeping the Master Clock frequency constant.

User programmable row and column start/stop

allow windowing down to a 1x1 pixel window for

noise are

a

characteristic of the pinned

photodiode²architecture utilized in the pixels. The

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IMAGE SENSOR SOLUTIONS

digital zoom of a panable viewport. Subsampling

immunity, signal to noise ratio, and system

dynamic range. The sensor uses an industry

standard two-line I²C-compatible serial interface. It

operates with a single 3.3V power supply with no

additional biases and requires only a single Master

Clock for operation up to 20 MHz. It is housed in a

48 pin ceramic LCC package.

provides reduced resolution while maintaining

constant field of view.

The analog video output of the pixel array is

processed by an on-chip analog signal pipeline.

Correlated Double Sampling (CDS) eliminates the

pixel reset temporal and pattern noise. The Frame

Rate Clamp (FRC) enables real time optical black

The KAC-1310 is designed taking into

consideration interfacing requirements to standard

video encoders. In addition to the 10 bit Bayer

(RGB or CMY) encoded data stream, the sensor

outputs the valid frame, line, and pixel sync

level calibration and offset correction.

The

of

programmable

analog

gain

consists

exposure/global gain to map the signal swing to

the ADC input range, and white balance gain to

perform color balance in the analog domain. The

ASP signal chain consists of (1) Column op-amp

(1.5x fixed gain); (2) Column DOVA(1.5x fixed

gain); (3) White Balance PGA (0.70 Æ 2.74x); (4)

Global PGA (0.48 Æ 7.50x); and (5) Global DOVA

(2.0x fixed gain). These Digitally Programmable

Amplifiers (DPGAs) allow real time color gain

correction for Auto White Balance (AWB) as well

as exposure gain adjustment. Offset calibration

can be done on a per column basis and globally.

This per-column offset correction can be applied

by using stored values in the on chip registers. A

10-bit Redundant Signed Digit (RSD) ADC

converts the analog data to a 10-bit digital word

signals needed for encoding.

The sensor

interfaces with a variety of commercially available

video image processors to allow encoding into

various standard video formats. In addition, the 3

sync signals can be integrated into the video data

stream eliminating the need of the 3 sync outputs

The KAC-1310 is an elegant and extremely

flexible single chip solution that simplifies a system

designer’s tasks of image sensing, processing,

digital conversion, and digital signal processing to

a high performance, low cost, low power IC. It

supports a wide range of low-power, portable,

consumer digital imaging applications.

stream.

The fully differential analog signal

processing pipeline serves to improve noise

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IMAGE SENSOR SOLUTIONS

Pixel Architecture

The KAC-1310 sensor comprises a 1280x1024

In addition to the imaging pixels, there are

additional pixels called dark and isolation pixels at

the periphery of the imaging section (see Figure

3). The dark pixels are covered by a light blocking

shield rendering the pixels underneath insensitive

to photons. These pixels provide the sensor

means to measure the dark level offset which is

used downstream in the signal processing chain to

perform auto black level calibration. The isolation

pixels are provided at the array’s periphery to

eliminate inexact measurements due to light piping

into the dark pixels adjacent to active pixels and

for extra pixels needed for color interpolation

algorithms. Electronic shuttering, also known as

electronic exposure timing in photographic terms,

is a standard feature. The pixel integration time

can be widely varied from a small fraction of a

given frame readout time to the entire frame time.

active pixel array and supports progressive

readout. The basic operation of the pixel relies on

the photoelectric effect where, due to its physical

properties, silicon is able to detect photons of light.

The photons generate electron-hole pairs in direct

proportion to the intensity and wavelength of the

incident illumination.

The application of an

appropriate bias allows the user to collect the

electrons and meter the charge in the form of a

useful parameter such as voltage.

The pixel architecture is based on a “four

transistor” (4T) Advanced CMOS Imager^TM1pixel

which requires all pixels in a row to have common

Reset, Transfer, and Row Select controls. In

addition all pixels have common supply (V_DD) and

ground (V_SS) connections. This optimized cell

architecture provides enhancements such as

noise reduction, fill factor maximization, and anti-

blooming. The use of pinned photodiodes²and

proprietary transfer gate devices in the photo-

elements enables enhanced sensitivity in the

entire visual spectral range and a low lag

operation. The nominal photo-responses of the

KAC-1310 are shown in Figure 14 (monochrome

sensor without microlenses), Figure 15 (Bayer

RGB sensor with microlenses) and Figure 16

(Bayer CMY sensor with microlenses).

¹Advanced CMOS Imager (ACI) is a Kodak trademark

²Patents held jointly by Kodak and Motorola

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Color Filters and Lenslets

The KAC-1310 family is offered with the option of

lenslet arrays can improve the fill factor (aperture

ratio) of the sensor by approximately 1.6x

depending on the F-number of the lens used in the

camera system. Microlenses yield the greatest

benefits when the main lens has a high F-number

or a highly telecentric design. The fill factor of the

pixels without microlenses is ~40%.

monolithic polymer color filter arrays (CFA’s). The

combination of an extremely planarized process

and proprietary color filter technology results in

CFA’s with superior spectral and transmission

properties. It is available in Bayer RGB (Figure 4)

or CMY (Figure 5) patterns. The complimentary

Bayer CMY array provides a 50% increase in

sensitivity over primary RGB pattern and are often

the best choice for low light applications. This is

due to the higher quantum efficiency (QE) and

Incident Light

Microlenses

larger wavelength spread per color.

If the

application is utilizing a color correction matrix,

then this matrix will automatically convert the CMY

to RGB. Other wise a simple matrix must be

applied to affect the conversion from CMY to RGB

space.

Active Photodiode Area

col

0

1

2

G1

B

3

row

Figure 6: Increase of sensitivity due to microlenses

G1

R

Frame Capture Modes

B

G2

R

G2

R

There are two frame capture modes:

1) Continuous Frame Rolling Shutter (CFRS)

2) Single Frame Rolling Shutter (SFRS)

G1

B

G1

B

G2

The sensor can be put into either one of these

modes by writing either “1” or “0” to cms bit (bit 6)

of Capture Mode Control Register (40_h) (Table 47

on page 66).The KAC-1310 uses a progressive

readout mode. Progressive scanning refers to

non-interlaced or sequential row-by-row scanning

of the entire sensor in a single pass. The image

readout happens at one instant of time.

Figure 4: Optional Bayer RGB Pattern CFA

col

0

1

Y1

M

2

C

3

Y1

M

row

C

Continuous Frame Rolling Shutter

Capture Mode (CFRS)

Y2

C

Y2

C

The default mode of image capture is the

Continuous Frame Rolling Shutter Capture Mode

(CFRS). In this mode the TRIGGER input pin is

ignored. This mode is most suitable for full motion

video capture and will yield SXGA sized Frame

Rates up to 15 FPS at 20 MHz MCLK and VGA

frames at >30 FPS. In this mode the image

integration and row readout take place in parallel.

While a row of pixels is being readout, another row

or rows are being integrated. Since the integration

time (T_int) must be equal for all rows, the start of

integration for rows is staggered.

Y1

M

Y1

M

Y2

Figure 5: Optional Bayer CMY Pattern CFA

Applications requiring higher sensitivity can benefit

from the microlens arrays shown in Figure 6. The

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CFRS Video Encoded Data Stream

The Encoded Sync Control Register (65_h) (Table

51 on page 69) allows the user to select how the

output pixel data stream in CFRS mode is

encoded/formatted. In default mode, internally

generated signals SOF, VCLK, HCLK etc. drive

the integration and readout of the pixel data

frames, but only the valid pixel data is readout of

the sensor. When a “1” is written to bit 5, it causes

the output pixel data to be encoded with four (4)

10-bit pixel codes at the beginning of each line for

SOF, VCLK and End Of Frame (EOF) signals.

Operation in this mode will allow a camera system

to capture streaming video and re-construct the

frame afterwards when the SOF, VCLK, and

HCLK signals are no longer available. The Video

Encoded Signal Definitions, (Table 2), defines the

four (4) 10-bit pixel code data that represents the

SOF, VCLK, and EOF signals.

that can be found in register 42_h, Table 29 on page

53.

The TRIGGER signal can be generated internally

by the sensor or be driven via Pin #46 of the

sensor. To set whether the signal is generated

internally or externally, along with other setting of

this signal, refer to TRIGGER and STROBE

Control register (42_h), Table 29 on page 53.

Window of Interest (WOI) Control

The pixel data to be read out of the device is

defined as a ‘Window of Interest’ (WOI). The

window of interest can be defined anywhere on

the pixel array at any size. The user provides the

upper-left pixel location and the size in both rows

and columns to define the WOI. The WOI is

defined using the WOI Pointer, WOI Depth, and

WOI Width registers, (Table 30 on page 58

through Table 37 on page 60). Please refer to

Figure 7 for a pictorial representation of the WOI

within the active pixel array. Any pixels not

included in the WOI will be skipped over and never

readout (note: the minimum valid values are 2 for

the WOI row pointer (wrp), and 0 for the WOI

column pointer (wcp)). The first pixel readout will

always be the first pixel of the WOI.

Signal

Description

Data

SOF

Start of Row

readout (i.e.

Readout of Row

1)

[3FF][3FF][3FF][3FF]

Note: 3FF_h= 1023_d

000_h= 0_d

VCLK

EOF

Start of Row

readout of

Rows 2+

[3FF][3FF][000][000]

Readout of last [000][000][000][000]

Row complete

0

1295

0

Table 2. Video Encoded Signal Definitions

ACTIVE PIXEL ARRAY

WOI Pointer (wcp,wrp)

Single Frame Rolling Shutter capture

mode (SFRS)

Window of Interest (WOI)

In this mode of capture, the start of integration is

triggered by the TRIGGER signal. Similar to the

CFRS capture mode, readout of each row follows

the integration of that row. The imager can be

placed in SFRS capture mode using register 40_h

(see Table 27 on page 55). In this mode the

imager will remain idle until the TRIGGER pin is

pulled high. The imager then begins integration

followed by image readout. If the TRIGGER input

is still high when the SFRS Frame is finished

reading out, then a second Frame is started.

Detailed timing can be found in Figure 24 on page

34. There are additional controls for SFRS mode

WOI Column Depth (wcd)

1047

Figure 7: WOI Definition

Sub-Sampling Control (Resolution)

The WOI can be sub-sampled in either

monochrome or color pixel space in both the

horizontal and vertical direction independently.

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The resolution of each axis can be set to four

Virtual Frame (VF)

1

different sampling rates: full, ½, ¼, or /₈. Sub-

Changing the WOI does not change the Frame

Rate of the imager. This is done by varying the

size of a Virtual Frame surrounding the WOI.

Refer to Figure 8 for a pictorial description of the

Virtual Frame and its relationship to the WOI.

sampling the imager by ¼ in both horizontal and

1

vertical directions results in only /₁₆of the pixels

being readout.

The frame readout rate can

therefore be increased by 16x. The user controls

the sub-sampling via the Sub-Sample Control

Register (41_h), Table 28 on page 56. An example

of RGB Bayer space sub-sampling is shown in

Figure 9. If the imager is set as a color imager

then the sub-sampling is done by reading out two

cols/rows and then skipping two. This prevents the

sub-sampling from breaking up a color kernel. If

the imager is set to Monochrome mode the sub-

sampling will skip every other col/row performing a

more uniform reduction is resolution. Activating

Sub-Sampling alone will not increase the Frame

Rate. The Frame Rate is controlled by the Virtual

Frame (see “Virtual Frame (VF)”). For example, if

The VF is a method for defining the horizontal and

vertical blanking (over clocking) in Frame

Readout. As the WOI is adjusted, the total Frame

Size is set by the VF. To maintain constant Frame

Rate, the KAC-1310 adjusts the number of

blanking pixels to account for changes in the WOI.

The VF can be set to any size. If the VF is greater

than the WOI then the readout is padded with

blanking pixels (invalid dark pixels). The WOI and

the VF may both be larger than the actual imager

size. In this case the WOI is also padded with

blanking pixels (invalid dark pixels). Figure 8

illustrates a WOI smaller than the VF. If the WOI is

set larger than the VF, then the WOI will be

clipped by the VF and the Frame Rate will still be

equal to the VF size.

1

Sub-Sampling is first turned on to /₈x /₈mode,

1

the WOI will shrink by /₆₄. To keep the Frame

Rate constant, the KAC-1310 fills in the rest of the

rows and columns with blanking pixels. The Virtual

Frame can now be reduced by 1/8 x 1/8 to take

advantage of the Sub-Sampled WOI. The Frame

Rate will now have increased by 64x with no

compromise to the field of view (in CFRS mode).

0

vcw[13:0]

0

WOI Pointer (wcp,wrp)

G

B

G

B

G

B

G

B

G

B

G

B

R

G

R

G

R

G

R

G

R

G

R

G

B

G

B

G

B

G

B

G

B

G

B

R

G

R

G

R

G

R

G

R

G

R

G

B

G

B

G

B

G

B

G

B

G

B

R

G

R

G

R

G

R

G

R

G

R

G

B

G

B

G

B

G

B

G

B

G

B

R

G

R

G

R

G

R

G

R

G

R

G

B

G

B

G

B

G

B

G

B

G

B

R

G

R

G

R

G

R

G

R

G

R

G

B

G

B

G

B

G

B

G

B

G

B

R

G

R

G

R

G

R

G

R

G

R

G

Window of Interest (WOI)

WOI Column Depth (wcd)

Blanking Rows

Virtual Frame

vrd[13:0]

Figure 8: Virtual Frame Definition

Integration Time

Figure 9: RGB Bayer ½ x ½ Sub-sample Example.

Sub-sample Control Register(41_h) = xxx10101_b

CFRS Integration Time

The Integration Time in CFRS is defined and

quantized by the time to read out a single row.

Once a Virtual Frame has been defined, the time

to read out one row can be calculated. Any integer

multiple of the Row Time (T_row) can be selected.

The number of Row Times desired for integration

time is programmed into the Integration Time

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Registers. The Integration Time is defined by a

where cint_dis the number of virtual frame row

times desired for integration time.

combination of the width of the VF and the

Integration Time Registers (4E_hand 4F_h), (Table

38 and Table 39 on page 61); and can be

expressed as:

Note: In CFRS operation, the integration time is

limited (clipped) by the readout time (which is also

the Frame Time). In SFRS mode, the Frame Time

is expanded to include any programmed

integration time. Thus in SFRS operation there is

no boundary to the integration time.

Integration Time (T_int) = (cint_d+ 1) * T_row

where cint_dis the number of virtual frame row

times desired for integration time. Therefore, the

integration time can be adjusted in steps of VF row

times.

Frame Rate

The Frame Rate can be defined as the time

required to readout an entire frame of data plus

the required blanking time. There is a different

relationship between the Frame Rate and Virtual

Frame for CFRS and SFRS mode operation.

Row Time (T_row) = (vcw_d+shA_d+shB_d+19) * MCLK_period

If the integration time is programmed to be larger

than the VF then it will be truncated to the number

of rows in the VF. The VF must be increased

before the Integration Time can be increased

further.

CFRS Frame Rate

In CFRS, the Frame Rate of the imager is

controlled by varying the size of the Virtual Frame

surrounding the WOI, and is independent of

Integration Time. Refer to Figure 8 for a pictorial

description of the Virtual Frame (VF) and its

relationship to the WOI. In CFRS operation, the

Frame Rate (FR) (Frame Rate = 1/Frame Time) is

defined by the VF size and clock speed (MCLK).

The Frame Time (FT) and can be expressed as:

NOTE: The upd bit of Reg 4E_his used to indicate

a change to cint[13:0]. Since multiple I²C writes

may be needed to complete desired frame to

frame integration time changes, the upd bit signals

that all desired programming has been completed,

and to apply these changes to the next frame

captured. This prevents undesirable changes in

integration time that may result from I²C writes that

span the “End of Frame” boundary. This upd bit

has to be toggled from its previous state in order

for the new value of cint[13:0] to be

accepted/updated by the sensor and take effect.

i.e. If its previous state is “0”, when writing a new

cint value, first write cint[7:0] to register 4F_h, then

write both cint [13:8] and “1” to the upd bit to

register 4E_h. The upd bit should be sent as close

to the Start of Frame as possible to ensure a

smooth transition from the old integration time to

the new.

FT =(vrd_d+1) * T_row

where vrd_ddefines the number of rows in the

virtual frame. The user controls vrd_dvia the Virtual

Frame Row Depth registers (Table 40 and Table

41 on page 62).

If the VF width (vcw_d) is <1296, then the timing

block holds the two Frame Rate Clamp (FRC)

rows to a length of 1296 even while all of the other

rows are shorter. This is to ensure enough time for

the clamping circuit. If the FRC is turned off (see

Clamp Control and HCLK Delay Register (64_h), it

is recommended that the CFRCA and CFRCB

pins be tied to ground directly (i.e. no 0.1 µF

capacitor).

SFRS Integration Time

Just as with operation in CFRS mode, the

integration time is defined by a number of Row

Times. As before:

NOTE: The WOI and Integration Time will be

clipped by the VF.

Row Time (T ) = (vcw_d+shA_d+shB_d+19) * MCLK_period

row

where vcw_ddefines the number of columns in the

virtual frame. The user controls vcw_dvia the

Virtual Frame Column Width registers (Table 42

and Table 43 on page 63).

Integration Time (T_int) = (cint_d+ 1) * T_row

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SFRS Frame Rate

There are two main differences when running in

Rather than have the user change the VF depth

(vrd), the imager uses the WOI depth (wrd).

SFRS mode versus CFRS mode. The first is that

the Frame Rate is no longer the readout rate. In

SFRS mode there is no overlap of the Integration

and the readout. Therefore, at the top of each

Frame, Integration must first occur then readout.

The Frame Rate is now Integration plus readout.

Therefore, the Frame Rate equations are:

Frame Time (T_frame) =

Integration Time (T_int)+ Readout Time (T_rd)

Where:

The second major difference is the length of

readout. In CFRS mode, the only reason for

making the VF length larger than the WOI length

(vrd > wrd) is to add vertical blanking rows to

control the time between frames. In SFRS mode,

the time between frames is controlled by the

TRIGGER input pin, and therefore vertical

blanking serves no purpose.

Integration Time (T_int) = (cint_d+ 1) * T_row

Readout Time (T_rd) = T_row* (wrd_d+1)

Row Time (T_row) = (vcw_d+shA_d+shB_d+19) * MCLK_period

Frame Rate = 1/Frame Time

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ANALOG SIGNAL PROCESSING CHAIN

(ASP)

The KAC-1310’s analog signal processing (ASP)

chain incorporates Correlated Double Sampling

(CDS), Frame Rate Clamp (FRC), two Digitally

Programmable Gain Amplifiers (DPGA), Offset

Correction (DOVA), and a 10-bit Analog to Digital

Converter (ADC). See Figure 3 for a block

diagram of the ASP chain.

Cap FRCA

0.1µF

CFRCA

V_CM

FRCLMP

+

1x

BUF

-

+

V+

V-

V_CM

Diff

-

+

BUF

-

Correlated Double Sampling (CDS)

FRCLMP

V_CM

The uncertainty associated with the reset action of

a capacitive node results in a reset noise which is

proportional to kTC; ‘C’ being the capacitance of

the node, ‘T’ the temperature, and ‘k’ the

Cap FRCB

CFRCB

0.1µF

Boltzmann constant.

A

common way of

eliminating this noise source in all image sensors

is to use Correlated Double Sampling. The output

signal is sampled twice, once for its reset

(reference) level and once for the actual video

signal. These values are sampled and held while

a difference amplifier subtracts the reference level

from the signal output. Double sampling of the

signal eliminates correlated noise sources.

Figure 11: FRC Conceptual Block Diagram

processed and held to establish pixel reference

level at the CFRCA and CFRCB pins. During this

period, the FRC’s differential outputs (V⁺and V^-on

the Diff Amp) shown in Figure 11 are clamped to

V_cm. Together, these actions help to eliminate the

dark level offset, simultaneously establishing the

desired zero code at the ADC output. The user

can disable the FRC via the Clamp Control and

HCLK Delay Register (64_h), (Table 50 on page 68)

which allows the ASP chain to drift in offset. If the

FRC is disabled, it is recommended that the

CFRCA and CFRCB pins be grounded. Care

should be exercised in choosing the capacitors for

the CFRCA and CFRCB pins to reflect different

Frame Rates. For small WOI or fast Frame Rates,

a smaller capacitor may be used.

S&H Reset

V+

+

Diff

OpAmp

Pixel

Output

V-

-

S&H Signal

Figure 10: Conceptual block diagram of CDS

Column Digital Offset Voltage Adjust

(CDOVA)

Frame Rate Clamp (FRC)

The FRC (Figure 11) is designed to provide a

feed-forward dark level compensation. In the

automatic FRC mode, the optical black level

reference is reestablished each time that the

image sensor begins a new frame. The KAC-1310

uses optical black (dark) pixels to establish this

reference.

A programmable per-column offset adjustment is

available on the KAC-1310.

There are 64

registers that can be programmed with an offset

that is added to each 64th column (Mod64 Column

Offset Registers; Table 52 on page 70). Each

register is 6 bits, (5 bits plus 1 sign bit), providing

±32 register values. This set of 64 values is then

repeatedly applied to each bank of 64 columns in

the sensor via the column DOVA stage of the ASP

chain.

The dark pixel sample period is automatically

controlled internally and it is set to skip the first 3

dark rows and then sample the next 2 dark rows.

When “dark clamping” is active, each dark pixel is

In addition to the per-column offset, there is a

global column offset that can be added to every

column. This is used to remove any variation of

the dark level with respect to varying gain. The

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DC offset is loaded as a 6-bit value into the

Programmable Gain Amplifier (PGA)

Gain Modes

Column DOVA DC Offset Register, (Table 23 on

page 51). The Column DOVA stage has only six

bits of total range. The value in Register 20_hand

80_h-BF_hare added together prior to application to

the column. If the sum is greater than ±31, it will

be truncated to ±31.

Three different gain modes are available when the

sensor is performing White Balance and Exposure

gain. The gain mode is set using Register 22_h

described in Table 25, page 53. The three gain

modes are:

Raw Gain Mode (WB and Exposure)

Gain ≈0.6950 + 0.02175 * Reg_d

≈1.3475 + 0.04350 * (Reg_d- 31)

0 <Reg_d<31

32 <Reg_d<63

(0.0695x Æ1.36925x)

(1.3910x Æ2.7395x)

Lin1 Gain Mode (WB and Exposure)

Gain ≈0.6950 + 0.04350 * Reg_d

0 <Reg_d<47

0 <Reg_d<63

(0.695x Æ2.7395x)

(0.483x Æ7.488x)

Lin2 Gain Mode (Exposure gain stage only)

Gain ≈0.483 + 0.11119 * (Reg 10_h)_d

Raw Gain Mode:

The three gain stages are each designed as two-

piece linear gain stages where the gain increment

doubles for the second half of the programmable

range. The gain increment is 0.02175 for the first

32 programmable steps, and precisely twice that

(0.04350) for the last 32 programmable steps.

step of the lower register is skipped, providing 16

uniform gain steps of 0.04350. As a result, the

entire gain stage now appears to be a linear gain

stage with 48 uniform steps of 0.04350.

Lin2 Gain Mode:

This mode is only available for the exposure gain

Lin1 Gain Mode:

mode.

In this mode, both gain stages are

Some applications do not need the finer gain

increment provided by the Raw Gain Mode in the

first 32 register values. In Lin1 mode, every other

automatically coordinated to affect a single gain

stage. The gain step size of Lin2 Mode is almost,

but not completely uniform. Any one step may

deviate from the mean step size of 0.11119 by a

small amount. This is due to the fact that Lin2

Mode actually varies two gain stages with fixed

step sizes to make one equivalent gain step.

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Gain of DPGA for Raw, Lin1, and Lin2 modes

8

7

6

5

Lin2

4

3

2

Lin1

Raw Mode

(upper range)

1

0

Raw Mode

(lower range)

0

5

10

15

20

25

30

35

40

45

50

55

60

DPGA Register Value (Decimal)

Figure 12: PGA Gain Modes

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White Balance Control PGA (WB Gain)

[For the purposes of illustration, the following

discussion assumes a Bayer RGB color pattern;

with the appropriate correlation (as shown in

Figure 13), the CMY Bayer pattern may be

substituted throughout.]

consideration before changes occur. In most

applications, users will be able to assign

predefined settings such as daylight, fluorescent,

tungsten, and halogen to cover a wide gamut of

illumination conditions.

The sensor produces three primary color outputs,

Red, Green, and Blue. These are monochrome

signals that represent luminance values in each of

the primary colors. When added in equal amounts

they mix to make neutral color. White balancing is

a technique where the gain coefficients of the

Green1, Red, Blue, and Green2 pixels comprising

the Bayer RGB pattern are set so as to equalize

their outputs for neutral gray color scenes. Since

the sensitivity of the two green pixels in the Bayer

pattern may not be equal, an individual color gain

register is provided for each component of the

Bayer pattern.

Both DPGA designs use switched capacitors to

minimize accumulated offset and improve

measurement accuracy and dynamic range. The

white balance gain registers are 6-bits and can be

programmed to allow gain of 0.695x to 2.74x in

varying steps depending on which gain mode is

selected (RAW or LIN mode).

The WB Gain Stage (PGA WB) is a two-segment

piecewise Linear gain stage. In Raw Mode this

stage produces smaller gain steps for the first half

of its gain range, and larger gain steps for second

half of its gain range. This allows fine adjustment

for color ratios as well as a large gain swing.

If the piecewise linear mode is difficult to manage

and the fine steps are not required, this gain stage

can be placed into Lin1 Mode. In this mode every

other gain step is skipped for the first 1/3 of the

gain range. This produces the same gain range

but with uniform gain steps throughout the range.

Once all color gain registers are loaded with the

desired gain coefficients, white balance is

achieved in real time and in analog space. The

appropriate values are selected and applied to the

pixel output via a high speed path, the delay of

which is much shorter than the pixel clock rate.

Real time updates can be performed to any of the

gain registers. However, latency associated with

the I²C interface should be taken into

6

C / G1 (0)

DPGA

6

Y1 / R (1)

Y2 / B (2)

M / G2 (3)

6

0.7x-2.7x

6

G1(0)

B(2)

R(1)

C(0)

Y1(1)

M(3)

G2(3)

Y2(2)

Figure 13: Color Gain Register Selection

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IMAGE SENSOR SOLUTIONS

Exposure Gain PGA (Exp Gain A/B)

The Exposure (Global) Gain consists of two Gain

stages (A and B) in series. Each of these gain

stages has a Raw and Lin1 mode as described in

the previous WB Gain section. Thus all colors can

be amplified by the value in Exp GainA (reg 10_h)

and then again by Exp GainB (reg 21_h) to

compensate for varying exposure of the scene.

The easiest way to implement this is to program

Exp GainB at unity and then adjust Exp GainA

until it is at its maximum of 2.7395x. Then

increase the Exp GainB until the final exposure

gain is reached. The gains of the two Exp Gain

stages are controlled by Registers 10_hand 21_h,

(Table 21 and Table 24 on pages 49 and 52). The

Exp Gain Mode is defined in Register 22_h, (Table

25 on page 53).

algorithmic technique is used to yield an ADC with

superior characteristics for imaging applications.

Integral Noise Linearity (INL) and Differential

Noise Linearity (DNL) performance is specified at

±1.0 and ±0.5, respectively, with no missing

codes. The input dynamic range of the ADC is

programmed via

a

Programmable Voltage

The positive reference

Reference Generator.

voltage (VREFP) and negative reference voltages

(VREFM) can be programmed from 2.5V to 1.25V

and 0V to 1.25V respectively in steps of 5mV via

the Reference Voltage Registers (Table 17 and

Table 18 on page 46). This feature is used

independently or in conjunction with the PGAs to

maximize the system dynamic range based on

incident illumination. The default input range for

the ADC is 1.86V for VREFP and 0.59V for

VREFM hence allowing a 10-bit digitization of a

1.3V peak-to-peak signal.

The dual gain-stage implementation of the Exp

Gain may cause difficulty in some auto-exposure

routines; this can be avoided by setting the Exp

Gain to Lin2 Mode. In Lin2 Mode, Reg 10_his used

to set both gain stages in an attempt to give

uniform gain steps across the entire 7.5x range of

the two Exp Gain stages. Only one register is

used to simplify user programming, and thus the

gain step size is increased to ~0.11119 to allow

the full range to be accessed by a single 6-bit

register. Note that the gain step size is almost but

not completely uniform. Any one step may deviate

from the mean step size of 0.11119 by a small

amount.

mV

10dn

2(V ⁺−V ⁻) 2(1.86 − 0.59)

mV

=

= 2.48 _10dn

1024

If the 20x gain provided by the PGAs is not

sufficient, the ADC references can be used to

apply additional gain to the ASP. To increase the

gain the ADC references need to be moved closer

to V_cm(1.25V). This should be used only after the

PGAs have been used to their fullest since moving

the ADC references too far will degrade the ADC

performance. The effective gain of the ADC block

will be:

Global Digital Offset Voltage Adjust

(GDOVA)

A programmable global offset adjustment is

available on the KAC-1310. A user defined offset

value is loaded via a 6-bit signed magnitude

programming code via the ADC DOVA Register,

(Table 26 on page 54).

2.48

Gain =

+

−

2(V −V

)

1024

Ex. If Reg 0A_h=Reg 0B_h≡BA_hthen the ADC Gain =

Offset correction allows fine-tuning of the signal to

remove any additional residual error, which may

have accumulated in the analog signal path. This

function is performed directly before analog to

digital conversion and allows the user to set the

‘black’ level in the ADC range.

2.

2.48

Gain =

=1.98

2(1.57−0.93)

1024

Analog to Digital Converter (ADC)

The user should connect 0.1 µF capacitors to

CVREFP (pin 15) and CVREFM (pin 14) (see

Figure 2) to accurately hold the biases.

The ADC is a fully differential, low power circuit. A

pipe-lined, Redundant Signed Digit (RSD)

20

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IMAGE SENSOR SOLUTIONS

PERFORMANCE

Test Conditions

Temperature

25°C

Operating Frequency

10 MHz MCLK

Light Source

White Light LED

Operation

Nominal Voltages and Default Timing

70 ms

Integration Time

Bright Field Condition

70% Saturation

Imaging Performance

Parameter

Symbol

N_sat

Typ

40,000

34

Unit

Notes

Saturation Signal

electrons

QE

Peak Quantum Efficiency

Monochrome no µLens @ 550nm

%

1

Red w/µLens @ 650nm

Green w/µLens @ 540nm

Blue w/µLens @ 460nm

Cyan w/µLens @ 530nm

Magenta w/µLens @ 650nm

Yellow w/µLens @ 590nm

Global

38

37

1

%

20

%

46

%

45

%

46

%

PRNU

S

Photoresponse Non-uniformity

Responsivity

4

% rms

Local

1.5

% rms

2

3

Monochrome no µLens

1.11

59,800

0.5

V/lux-sec

e-/lux-sec

V/lux-sec

e-/lux-sec

V/lux-sec

e-/lux-sec

V/lux-sec

e-/lux-sec

V/lux-sec

e-/lux-sec

V/lux-sec

e-/lux-sec

V/lux-sec

e-/lux-sec

Red w/µLens

Green w/µLens

Blue w/µLens

27,100

0.6

32,200

0.32

17,500

1.04

55,800

0.81

43,600

1.2

Cyan w/µLens

Magenta w/µLens

Yellow w/µLens

64,700

Table 3. Electro-Optical Characteristics

Notes:

1. Refers to nominal spectral response values as provided in Figures 3, 4, and 5. QE range is +/- 20%

2. For a 100 x 100 pixel region under uniform illumination with output signal equal to 70% of saturation signal.

3. Measurements assume a 3200K source with Hoya CM500 filter. All values referenced at the floating diffusion

node.

To calculate values at the sensor outputs, on-chip gain stages should be linearly applied to the given values.

21

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5 8 5 - 7 2 2 - 4 3 8 5

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IMAGE SENSOR SOLUTIONS

Symbol

Parameter

Typ

Unit

fA/pixel

%

Notes

I_d

Photodiode Dark Current

1 / 4

4

Lag

X_ab

n_e- _total

DR

Pixel Charge Transfer Inefficiency

Blooming Margin - shuttered light

Total System (equivalent) Noise Floor

System Dynamic Range

Resolution

<1

5

6

7

200x

X Vsat

e^-rms

dB

70

54

9, 12, 13

10

bits

f_max

Maximum MCLK

Nominal MCLK

20

10

MHz

Degrees

mm

8

9

11

f_nom

φ

A - X

Acceptance Angle in Horizontal direction

Acceptance Angle in Vertical direction

Image Array Size

15

27

φ

A - Y

7.7 x 6.1 (~¹/₂")

6.0 x 6.0

0 - 15

Pixel Size

µm

Frame Rate

FPS

Fill Factor

40 / 64

%

10

Table 3 continued. Electro-Optical Characteristics

Notes:

4. Measured at sensor temperatures of 25 ^oC / 40 ^oC

5. Transfer inefficiency of photosite.

6. X_abrepresents the increase above the saturation-irradiance level (Vsat) that the device can be exposed to before

blooming of the pixel will occur.

7. Includes amplifier noise, dark pattern noise and dark current shot noise at 10 MHz data rates.

8. All performance specs are not guanteed at this speed.

9. All Imager specs are held between 1 MHz and 10 MHz

10. Monochrome sensor without microlens / color sensor with microlens

11. Angle at which Responsivity is reduced by 3dB.

12. DR is defined as the standard deviation of temporal noise divided by the mean signal at saturation.

13. Saturation signal is defined as the maximum sensor output achieved while maintaining < 2% response non-

linearity.

22

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4

•

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5 8 5 - 7 2 2 - 4 3 8 5

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Quantum Efficiency

40

35

30

25

20

15

10

5

0

350

450

550

650

750

850

950

1050

Wavelength (nm)

Figure 14: KAC-1310 Typical Monochrome Spectral Response

40

35

30

25

20

15

10

5

BLUE

GREEN

RED

0

350

450

550

650

750

850

950

1050

Wavelength (nm)

Figure 15: KAC-1310 Typical Bayer RGB Spectral Response

23

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IMAGE SENSOR SOLUTIONS

50

45

40

35

30

25

20

15

10

5

MAGENTA

CYAN

YELLOW

0

350

450

550

650

750

850

950

1050

Wavelength (nm)

Figure 16: KAC-1310 Typical Bayer CMY Spectral Response

24

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5 8 5 - 7 2 2 - 4 3 8 5

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IMAGE SENSOR SOLUTIONS

Dynamic Range

10.0

60

57

54

51

48

45

42

39

36

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

0

5

10

15

20

Freq (MHz)

Figure 17: Dynamic Range with respect to Mclk Frequency

Temporal Noise

7

6

5

4

3

2

1

0

10

20

30

40

50

60

External Resistance (kOhms)

Figure 18: Temporal Noise Dependence on External Resistor

25

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5 8 5 - 7 2 2 - 4 3 8 5

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IMAGE SENSOR SOLUTIONS

Symbol

Parameter

Value

-0.5 to 3.8

-0.5 to (V_DD+ 0.5)

±50

Unit

V

V_DDDC Supply Voltage

V_inDC Input Voltage

V_outDC Output Voltage

V

I_IODC Current Drain per Pin, Any Single Input or Output

I_DDDC Current Drain, V_DDand V_SSPins

T_STGStorage Temperature Range

mA

°C

±100

-65 to +150

300

T_LLead Temperature (10 second soldering)

Notes:

- Voltages referenced to VSS

- Maximum Ratings are those values beyond which damage to the device may occur.

- V_SS= AV_SS= DV_SS= V_SSO(DV_SS= V_SSof Digital circuit, AV_SS= V_SSof Analog Circuit)

-

V_DD= AV_DD= DV_DD= V_DDO(DV_DD= V_DDof Digital circuit, AV_DD= V_DD of Analog Circuit)

Table 4: Absolute Maximum Ratings

Symbol

Parameter

Min

3.0

Max

Unit

V_DD

T_A

DC Supply Voltage, V_DD= 3.3V (Nominal)

Commercial Operating Temperature

Junction Temperature

3.6

40

55

V

0

°C

T_J

Notes:

•

All parameters are characterized for DC conditions after thermal equilibrium has been established.

Unused inputs must always be tied to an appropriate logic level, e.g. either VSS or VDD

For proper operation it is recommended that Vin and Vout be constrained to the range VSS<(Vin or Vout)<

VDD

Table 5: Recommended Operating Conditions

26

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IMAGE SENSOR SOLUTIONS

Symbol

Characteristic

Condition

T_A= 0 °C to 40 °C

Min Max

Unit

V_IH

V_IL

I_in

Input High Voltage

2.0

V_DD+ 0.3

V

Input Low Voltage

-0.3

0.8

5

Input Leakage Current, No Pull-up Resistor

Output High Current

Vin = V_DDor V_SS

-5

µA

mA

V

I_OH

I_OL

V_DD= Min, V_OHMin = 0.8*V_DD

V_DD= Min, V_OLMax = 0.4V

V_DD=Min, I_OH= -100mA

V_DD= Min, I_OL= 100mA

-3

3

Output Low Current

V_OH

V_OL

I_OZ

I_DD

Output High Voltage

V_DD- 0.2

Output Low Voltage

0.2

10

15

V

3-State Output Leakage Current

Maximum Standby Supply Current

Output = High Impedance, Vout = V_DDor V_SS

I_OUT= 0mA, Vin = V_DDor V_SS

-10

0

µA

mA

V_DD= 3.3V + 0.3V; V_DDreferenced to V_SS; Ta = 0 C to 40 C

Table 6: DC Electrical Characteristics

Symbol

Parameter

Condition

Typ

250

Unit

P_DYN

P_STDBY

P_AVG

Dynamic Power

Standby Power

Average Power

13.5 MHz MCLK Clock frequency

STDBY Pin Logic High

mW

25

13.5 MHz Operation (using STDBY)

200

V_DD= 3.0V, V_DDreferenced to V_SS, 25 °C

Table 7: Power Dissipation

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IMAGE SENSOR SOLUTIONS

OPERATION

The KAC-1310 includes initialization, standby

sensor can also be put in the stand by mode via

the sby bit (“0”) on the Power Configuration

Register (OC_h) (Table 19, page 47). The registers

retain their programmed values and are not reset

to default when the power configuration register is

used to enter/exit standby mode.

modes, and external reference voltage outputs to

afford the user additional application flexibility.

Initialization (Standby Mode)

The INIT input (pin 42) controls hardware re-

initialization of the KAC-1310. This serves to

assure controlled chip and system startup. The

chip enters standby mode when INIT is asserted

via a logic high input. This state must be held a

minimum of 1 ms. The chip remains in low-power

mode while in the INIT state.

The user may also reduce power consumption by

placing the KAC-1310’s outputs in the tri-state

mode. This action may be accomplished by setting

the dbt bit on the Power Configuration Register

(0C_h). In addition, further power savings can be

obtained by increasing the external resistance

value (see section 4.6).

When INIT is removed (logic low), the chip begins

initialization. An additional 1 ms “wait period”

should be allowed after INIT goes low. This

ensures that the start-up routines within the KAC-

1310 have run to completion, and that all holding

and bypass capacitors, etc. have achieved their

Output Tristate

The Tristate Control Register (12_h), (Table 22 on

page 50) is used to set the chip outputs into

tristate. This functionality is useful if these outputs

are on a buss that is being shared by other

devices. When the tsctl bit is reset (ie “0”) the

SOF, VCLK, HCLK, and STROBE output pins are

placed in tristate mode. The 10 ADC output pins

can be tristated by resetting the tspix bit (“0”).

required steady-state values.

Start-up tasks

include resetting registers to their default values,

resetting all internal counters and latches, and

initializing the analog signal processing chain.

Standby Mode

The standby mode option is implemented to allow

the user to reduce system power consumption

during periods that do not require operation of the

KAC-1310. This feature allows the user to extend

battery life in low power applications.

Readout Order

Register 57_h(Table 47 on page 66) allows the

user to change the direction of readout of the

columns or rows.

This can be used to

compensate for and orientation of the imager in

the optical system. The rrc when enabled causes

the column data to be readout in the reverse

direction as compared to the normal readout

direction. The rrr when enabled causes the row

data to be readout in the reverse direction as

compared to the normal readout direction. The

normal readout direction of the imager is shown in

Figure 2 on page 7 (ie. bottom-to-top; left-to-right).

By utilizing this mode, the user may reduce

dynamic power consumption from 400mW (full

power, full speed), to <50 mW in the standby

mode (note that dynamic power consumption is

also reduced in slower conversion speed

applications).

The standby mode is activated by applying an

active high signal to the INIT pin (#42). The

28

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4

•

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5 8 5 - 7 2 2 - 4 3 8 5

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Readout Speed

The imager will hold all specifications from 1 MHz

degradation in sensor performance will occur

when operating in excess of 20 MHz. When

operating at speeds greater than 10 MHz, it is

possible that horizontal banding might occur. This

is due to one of the sample and hold stages not

settling. If this condition is observed, it can be

rectified by widening the SHA and SHB pulses in

registers 5F_h(page 67) and 60_h(page 67).

to 10 MHz. The nominal maximum speed is 10

MHz (10FPS). The imager will work well beyond

this nominal maximum speed. As the speed

increases beyond 10 MHz, the power consumption

increases slightly, temporal noise rises linearly

resulting in a decrease in dynamic range (see

Figure 17), and ADC INL degrades. Severe

Note: this will change the T_rowequation given on page 34.

Further image improvements can also be obtained by increasing the power of the chip with the external

resistor (see “Internal Bias Current Control”).

Note: When increasing the SHA and SHB pulses, the SOF Delay ( Register 54_h) will need to be increased

as well in order to place the syncs back in the same position relative to the first WOI valid pixel.

29

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Internal Bias Current Control

The ASP chain has internally generated bias

currents that result in an operating power

consumption of nearly 400mW. By attaching a

resistor between pin 19, EX-TRESA; and pin 20,

EXTRESB; the user can reduce the power

the power savings that can be achieved with an

external resistor at nominal clock rate (10 MHz).

An external resistance (R_ext) of 39 kΩ is

recommended for optimal sensor performance.

Additional power savings can be achieved at lower

clock rates.

consumption of the device.

This feature is

enabled by writing a 1_bto bit res of the Power

Configuration Register (0C_h). Figure 19 depicts

600

Internal Resistor

500

400

300

200

100

0

10

15

20

25

30

External Resistance(kOhms)

Figure 19: Power Consumption Dependence on External Resistor

35

40

45

50

55

60

30

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

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IMAGE SENSOR SOLUTIONS

TIMING

The waveforms depicted on the following pages

Horizontal Data Sync (VCLK)

show the output data stream for the KAC-1310

under various operating conditions. The individual

SOF, VCLK, and HCLK pulse positions and widths

can be moved and inverted using registers 40_h

(Table 27, page 55), 54_h(Table 44, page 63), 55_h

(Table 45, page 64), 56_h(Table 46, page 65), and

64_h(Table 50, page 68).

This signal triggers the readout of the sequential

rows of the frame. This signal is an output and can

be read via Pin #44 of the sensor. The VCLK

signal delay in relation to SOF, as well as its

length can be set via the VCLK Delay Register

(Table 45, page 64), and the SOF&VCLK Signal

Length Control Register, (Table 46, page 65).

Start of Row Readout (SOF)

Data Valid (HCLK)

This signal triggers the start of the first row

readout of the frame. This signal is an output and

can be read via Pin #48 of the sensor. The SOF

signal delay as well as its length can be set via the

SOF Delay Register (Table 44, page 64), and the

SOF & VCLK Signal Length Control Register,

(Table 46, page 65).

This signal triggers a single active pixel data has

been readout (example Column 2 of Row 5 data

has been read out). This signal is an output and

can be read via Pin #45 of the sensor. The HCLK

signal delay can be set via the HCLK Delay

Register (Table 50, page 68).

Frame Time = 1064 row times

Row Time = 1338 MCLKs

WOI = 1280 Columns x 1024 Rows

starting at row 16, column 8

SOF

VCLK

HCLK

Figure 20: CFRS Default Frame Sync Waveforms

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MCLK

SOF

Row Time = vcw_d+ 39

VCLK

HCLK

row 16

row 17

Pixel Array Values

ADC[9:0]

Valid Pixel Data

Figure 21: CFRS Default Row Sync Waveforms

TRIGGER

T = (cint_d+ 1)*Row Time

SOF

VCLK

HCLK

Standard Frame

Timing (Figure 18)

Figure 22: Single Frame Capture Mode (SFRS)

Symbol

Characteristic

Min

Typ

Max

Unit

f_max

t_htrig

t_sutrig

t_dsof

MCLK maximum frequency

TRIGGER hold time w.r.t. MCLK

1

3.5

3.0

8

10

-

20

9

MHz

ns

TRIGGER setup time w.r.t. MCLK

MCLK to SOF delay time

-

8.5

21.5

22

ns

13

13.5

13

5

ns

t_dvclk

t_drhclk

t_dfhclk

t_dadc

t_dblank

MCLK to VCLK delay time

8.5

7.5

3

ns

Rising edge of MCLK to rising edge of HCLK delay time

Falling edge of MCLK to falling edge of HCLK delay time

MCLK to ADC[9:0] delay time

22

ns

10.5

21.5

ns

8

13

ns

MCLK to BLANK delay time

8

ns

Table 8: Pixel Data Bus and Sync Timing Specification

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MCLK

t_htrig

t_sutrig

TRIGGER

t_dsof

SOF

t_dvclk

VCLK

t_drhclk

t_dfhclk

HCLK

t_dadc

ADC[9:0]

Figure 23: Pixel Data Bus Timing Diagram

Strobe Signal

The Strobe signal is an output pin on the KAC-

1310 sensor. It can be activated by writing a “1” to

vsg (bit 5) of the Trigger and Strobe Control

Register (Table 29, page 57) while operating in

SFRS mode. When activated, the Strobe signal

goes high when all rows are integrating

before the last row begins to integrate. The start of

the strobe signal can also be set by the user. In

default mode, when the strobe is activated, the

signal fires two row periods before the first row

begins to readout and lasts for a length of one

T_row. A timing diagram for the Strobe signal is

shown below in Figure 24.

simultaneously and ends on row period (T_row

)

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4

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T_frame

TRIGGER

1st row of

integration

T_int

2nd row of

integration

3rd row of

integration

last row of

integration

T_int

SOF

VCLK

STROBE

T_row

T_{strobe 2}

T_row

T_{strobe 1}

T_row

Figure 24: STROBE Output Waveforms

To ensure that the Strobe signal fires, the

integration time must be large enough to ensure

that all rows are integrating simultaneously for at

least 2 row periods (T_row) where

4) Sample & hold time (shA_d) = 10

5) Sample & hold time (shB_d) = 10

6) MCLK = 10 MHz

Variables

Row Time (T_row) = (vcw_d+shA_d+shB_d+19)* MCLK_period

Integration Time (cint_dmin) is the main variable used

to control the time of the Strobe signals.

To accomplish this , one must ensure that the

integration time (cint_d) is more than 2 row periods

(T_row) larger than the active Window of Interest

Row depth (wrd_d). Therefore, minimum integration

time:

T_intmin= (cint_dmin+1)* T_row

Calculations

T_row= (vcw_d+ 10+10+19) * MCLK_period

= (1290 + 39) * 1e-7

= 132.9µs

T_intmin= (cint_dmin+1)* T_row

where cint_dmin= wrd_d+ 3.

T_strobe1= T_row

T_intmin= (cint_dmin+ 1) * T_row

= (wrd_d+ 3 +1) * T_row= (1023 + 4) * 132.9µs

= 136.48 ms

T_strobe2= T_intmin– (wrd_d+1)*T_row

An example of Strobe related calculations is

T_strobe2= T_intmin– (wrd_d+1)*T_row

= 136.48 ms – [(1023+1)* 132.9µs]

= 390.4 µs

provided

below:

Assumptions

1) Active Window of Interest = 1280 X 1024

ie. (wcwd) = 1279, (wrdd) = 1023

T_Frame= T_int+ T_rd

= [(wrd_d) +( cint_d)+2] * T_row

= (1023 + 1026 + 2) * 132.9µs

= 272.6 ms

2) Virtual Column Width (vcwd) = 1290

3) Virtual Row Depth (vrdd)=1034

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Example Timing Summary:

Signal

T_row

Value

132.9 µs

136.48 ms

132.9 µs

390.4 µs

272.6 ms

T_intmin

T_strobe1

T_strobe2

T_Frame

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I²C-COMPATIBLE SERIAL INTERFACE

The I²C is an industry standard which is also

compatible with the Motorola bus (called M-Bus)

that is available on many microprocessor

products. The I²C contains a serial two-wire half-

duplex interface that features bi-directional

operation, master or slave modes, and multi-

master environment support. The clock frequency

on the system is governed by the slowest device

on the board. The SDATA and SCLK are the bi-

directional data and clock pins, respectively.

These pins are open drain and will require a pull-

up resistor to VDD of 1.5 ΚΩ to 10ΚΩ (see Table

1).

the Program Control Register for verification or

test considerations. The KAC-1310 is a slave only

device that supports a maximum clock rate

(SCLK) of 1/24^thMCLK while reading or writing

only one register address per I²C start/stop cycle.

The following sections will be limited to the

methods for writing and reading data into the KAC-

1310 register.

For a complete reference to I²C, see “The I²C Bus

from Theory to Practice” by Dominique Paret and

Carll-Fenger, published by John Wiley & Sons,

ISBN 0471962686 or refer to Philip Standard

online at:

The I²C is used to write the required user system

data into the Program Control Registers in the

KAC-1310. The I²C bus can also read the data in

http://www.us2.semiconductors.philips.com/i2c/.

MSB

1

LSB

7

MSB

1

LSB

8

2

3

4

5

6

8

9

2

3

4

5

6

7

9

SCLK

AD7 AD6 AD5 AD4 AD3 AD2 AD1

D7

D6

D5

D4

D3

D2

D1

D0

SDATA

0

1

0

1

KAC-1310 I²C Bus Address

KAC-1310 Register Address

Ack Bit

from

Start Signal

Ack Bit

from

Write

KAC-1310

MSB

1

LSB

8

5

9

2

3

4

6

7

SCLK

D7

D6 D5

D4

D3

D2

D1

D0

SDATA

Data to write KAC-1310 Register

Ack Bit Stop

from

Signal

KAC-1310

Figure 25: I²C Bus WRITE Cycle

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KAC-1310 I²C Bus Protocol

The KAC-1310 uses the I²C bus to write or read

slaves in the system may have the same address.

The KAC-1310 is configured to be a slave only.

one register byte per start/stop I²C cycle as shown

in Figure 25 and Figure 26. These figures will be

used to describe the various parts of the I²C

protocol communications as it applies to the KAC-

Data Transfer

Once successful slave addressing is achieved,

data transfer can proceed between the master and

the selected slave in a direction specified by the

R/W bit sent by the calling master. Note that for

the first byte after a start signal (in Figure 25 and

Figure 26), the R/W bit is always a “0” designating

a write transfer. This is required since the next

data transfer will contain the register address to be

read or written. All transfers that come after a

calling address cycle are referred to as data

transfers, even if they carry sub-address

information for the slave device. Each data byte is

8 bits long. Data may be changed only while

SCLK is low and must be held stable while SCLK

is high as shown in Figure 25. There is one clock

pulse on SCLK for each data bit, the MSB being

transferred first.

1310.

KAC-1310 I²C bus communication is

basically composed of following parts: START

signal, KAC-1310 slave address (0110011_b)

transmission followed by

a

R/W bit, an

acknowledgment signal from the slave, 8-bit data

transfer followed by another acknowledgment

signal, STOP signal, Repeated START signal, and

clock synchronization.

START Signal

When the bus is free, i.e. no master device is

engaging the bus (both SCLK and SDATA lines

are at logical “1”),

a

master may initiate

communication by sending a START signal. As

shown in Figure 25 on page 36, a START signal is

defined as a high-to-low transition of SDATA while

SCLK is high. This signal denotes the beginning of

a new data transfer and wakes up all the slaves on

the bus.

Each data byte has to be followed by an

acknowledge bit, which is signaled from the

receiving device by pulling the SDATA low at the

ninth clock. So one complete data byte transfer

needs nine clock pulses. If the slave receiver

does not acknowledge the master, the SDATA line

must be left high by the slave. The master can

then generate a stop signal to abort the data

transfer or a start signal (repeated start) to

commence a new calling. If the master receiver

does not acknowledge the slave transmitter after a

byte transmission, it means 'end of data' to the

slave, so the slave releases the SDATA line for

the master to generate STOP or START signal.

Slave Address Transmission

The first byte of a data transfer, immediately after

the START signal, is the slave address transmitted

by the master. This is a 7-bit calling address

followed by a R/W bit. The 7-bit address for the

KAC-1310, starting with the MSB (AD7), is

0110011_b. The transmitted calling address on the

SDATA line may only be changed while SCLK is

low as shown in Figure 25. The data on the

SDATA line is valid on the High to Low signal

transition on the SCLK line. The R/W bit following

the 7-bits tells the slave the desired direction of

data transfer: 1 = Read transfer, the slave

transitions to a slave transmitter and sends the

data to the master; 0 = Write transfer, the master

transmits data to the slave.

Stop Signal

The master can terminate the communication by

generating a STOP signal to free the bus.

However, the master may generate a START

signal followed by a calling command without

generating a STOP signal first. This is called a

Repeated START. A STOP signal is defined as a

low-to-high transition of SDATA while SCLK is at

logical “1” (see Figure 25). The master can

generate a STOP even if the slave has generated

an acknowledge bit at which point the slave must

release the bus.

Acknowledgment

Only the slave with a calling address that matches

the one transmitted by the master will respond by

sending back an acknowledge bit. This is done by

pulling the SDATA line low at the 9^thclock (see

Figure 26 on page 39). If an acknowledgement is

not received, many I²C master devices will

assume that the slave device is not functioning.

No two

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•

KAC-1310 slave sends acknowledgment by

forcing the SDATA Low during the 9^thclock, if

the Calling Address was received

Master transmits the KAC-1310 Register

Address

Repeated START Signal

A Repeated START signal is a START signal

generated without first generating a STOP signal

to terminate the communication. This is used by

the master to communicate with another slave or

•

KAC-1310 slave sends acknowledgment by

forcing the SDATA Low during the 9^thclock

after receiving the Register Address

Master transmits the data to be written into the

register at the previously received Register

Address

with the same slave in

a

different mode

(transmit/receive mode) without releasing the bus.

As shown in Figure 26, page 39, a Repeated

START signal is being used during the read cycle

and to redirect the data transfer from a write cycle

(master transmits the register address to the

slave) to a read cycle (slave transmits the data

from the designated register to the slave).

•

KAC-1310 slave sends acknowledgment by

forcing the SDATA Low during the 9^thclock

after receiving the data to be written into the

Register Address

I²C Bus Clocking and synchronization

•

The Master transmits STOP to end the write

cycle

Open drain outputs are used on the SCLK outputs

of all master and slave devices so that the clock

can be synchronized and stretched using wire-

AND logic. This means that the slowest device

will keep the bus from going faster than it is

capable of receiving or transmitting data.

Register Read

Reading the KAC-1310 registers is accomplished

with the following I²C transactions (see Figure 26,

page 39):

•

Master transmits a START

After the master has driven SCLK from High to

Low, all the slaves drive SCLK Low for the

required period that is needed by each slave

device and then releases the SCLK bus. If the

slave SCLK Low period is greater than the master

SCLK Low period, the resulting SCLK bus signal

Low period is stretched. Therefore, synchronized

clocking occurs since the SCLK is held low by the

device with the longest Low period. Also, this

method can be used by the slaves to slow down

the bit rate of a transfer. The master controls the

length of time that the SCLK line is in the High

state. The data on the SDATA line is valid when

the master switches the SCLK line from a High to

a Low. Slave devices may hold the SCLK low

after completion of one byte transfer (9 bits). In

such case, it halts the bus clock and forces the

master clock into wait states until the slave

releases the SCLK line.

Master transmits the KAC-1310 Slave Calling

Address with “WRITE” indicated (BYTE=66_h,

102_d, 01100110_b)

•

KAC-1310 slave sends acknowledgment by

forcing the SDATA Low during the 9^thclock, if

the Calling Address was received

•

Master transmits the KAC-1310 Register

Address

KAC-1310 slave sends acknowledgment by

forcing the SDATA Low during the 9^thclock

after receiving the Register Address

Master transmits a Repeated START

Master transmits the KAC-1310 Slave Calling

Address with “READ” indicated (BYTE = 67_h,

103_d, 01100111_b)

•

KAC-1310 slave sends acknowledgment by

forcing the SDATA Low during the 9^thclock, if

the Calling Address was received

•

At this point, the KAC-1310 transitions from a

“Slave-Receiver” to a “Slave-Transmitter”

KAC-1310 sends the SCLK and the Register

Data contained in the Register Address that

was previously received from the master;

KAC-1310 transitions to slave-receiver

Master does not send an acknowledgment

(NAK)

Register Write

Writing the KAC-1310 registers is accomplished

with the following I²C transactions (see Figure 25

page 36):

•

Master transmits a START

Master transmits STOP to end the read cycle

Master transmits the KAC-1310 Slave Calling

Address with “WRITE” indicated (BYTE=66_h,

102_d, 01100110_b)

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1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCLK

LSB

MSB

AD7 AD6 AD5 AD4 AD3 AD2 AD1

D7

D6

D5

D4

D3

D2

D1

D0

XX

SDATA

0

1

0

1

KAC-1310 I²C Bus Address

KAC-1310 Register Address

Ack Bit

from

Repeated

Start

Start Signal

Write Ack Bit

from

KAC-1310

Signal

KAC-1310

At this point the KAC-1310

5

8

9

1

2

3

4

6

7

SCLK

transitions from a "SLAVE-receiver"

to a "SLAVE-transmitter

MSB

LSB

AD7 AD6 AD5 AD4 AD3 AD2 AD1

SDATA

0

1

0

1

KAC-1310 I²C Bus Address

Read Ack Bit

from

KAC-1310

The KAC-1310 transitions from a

"SLAVE-transmitter" to a "SLAVE-receiver"

after the register data is sent

5

8

9

1

2

3

4

6

7

SCLK

MSB

LSB

D7

D6 D5

D4

D3

D2

D1

D0

SDATA

Data to write KAC-1310 Register

No Ack Bit from MASTER terminates the transfer

Stop

Signal from MASTER

Single Byte Transfer to Master

Figure 26: I²C Bus READ Cycle

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Symbol

Characteristic

Min

Max

Unit

f_max

M1

M2

SCLK maximum frequency

Start condition SCLK hold time

50

4

1/24 MCLK

KHz¹

3

-

T_MCLK

SCLK low period

8

SCLK/SDATA rise time [from V_IL= (0.2)*V_DDto V_IH

=

M3

M4

M5

M6

M7

M8

M9

C_I

(0.8)*V_DD

]

-

4

-

0.3

-

µs²

3

SDATA hold time

T_MCLK

µs²

SCLK/SDATA fall time (from Vh = 2.4V to VI = 0.5V)

SCLK high period

0.3

-

4

-

T_MCLK

3

SDATA setup time

-

T_MCLK

pF

Start / Repeated Start condition SCLK setup time

Stop condition SCLK setup time

Capacitive for each I/O pin

-

10

200

10

Cbus

Rp

Capacitive bus load for SCLK and SDATA

Pull-up Resistor on SCLK and SDATA

-

pF

kΩ⁴

1.5

Table 9: I²C-compatible Serial Interface Timing Specification

Notes:

1. SCLK frequency maximum limit is 1/24 MCLK frequency.

2. The capaitive load is 200pF

3. The unit TMCLK is the period of the input master clock; the frequency of MCLK is assumed 10.0 MHz.⁴A pull-up

resistor to VDD is required on each of the SCLK and SDATA lines; for a maximum bus capacitive load of 200pF,

the minimum value of Rp should be selected in order to meet specifications. I2C is a proprietary Philips interface

bus.

M2

M5

M3

M6

V_IH

V_IL

SCLK

M1

M9

M4

M7

M8

SDATA

Figure 27: I²C Bus Timing

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REGISTER LIST REFERENCE

Note: In each table where a suffix code is used; h = hex, b = binary, and d = decimal.

The I²C addressing is broken up into groups and assigned to a specific digital block. The designated

block is responsible for driving the internal control bus, when the assigned range of addresses is present

on the internal address bus. The grouping designation and assigned range are listed in Table 10. Each

block contains registers that are loaded and read by the digital and analog blocks to provide configuration

control via the I²C serial interface.

Address Range

00_h– 2F_h

Block Name

Analog Register Interface

Sensor Interface

40_h– 7F_h

80_h- BF_h

Column Offset Coefficients

Table 10. I²C Address Range Assignments

Table 11 and Table 12 contain all the I²C address assignments. The table includes a column indicating

whether the register values are shadowed with respect to the sensor interface. If the register is

shadowed, the sensor interface will only be updated upon frame boundaries, thereby eliminating intra-

frame artifacts resulting from register changes.

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Hex

Ref

Address

Register Function

Default

Table

Shadowed?

00_h

01_h

02_h

03_h

04_h

05_h

06_h

07_h

08_h

09_h

0A_h

0B_h

0C_h

0D_h

0E_h

0F_h

10_h

11_h

12_h

13_h

DPGA Color 1 Gain Register (Green1 or Cyan)

DPGA Color 2 Gain Register (Red or Yellow1)

DPGA Color 3 Gain Register (Blue or Yellow2)

DPGA Color 4 Gain Register (Green2 or Magenta)

Unused

0E_h

Table 13, pg 44

Table 14, pg 45

Table 15, pg 45

Table 16, pg 45

Yes

Factory Use Only

Negative ADC Reference Register

Positive ADC Reference Register

Power Configuration Register

Factory Use Only

76_h

80_h

00_h

Table 17, pg 46

Table 18, pg 46

Table 19, pg 47

No

Reset Control Register

00_h

50_h

0E_h

Table 20, pg 48

Table 21, pg 49

Table 22, pg 50

No

Device Identification (read only)

PGA Exposure (Global) Gain A Register

Unused

Yes

Tristate Control Register

Factory Use Only

03_h

Unused

14_hÆ 1F_h

20_h

Column DOVA DC Register

PGA Exposure Global Gain B Register

PGA Gain Mode Register

ADC DOVA Register

00_h

0E_h

00_h

Table 23, pg 51

Table 24, pg 52

Table 25, pg 53

Table 26, pg 54

No

Yes

No

21_h

22_h

23_h

No

Unused

24_hÆ 3F_h

Table 11: I²C Address Assignments (0_h- 3F_h)

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Hex

Ref

Address

Register Function

Default

Table

Shadowed?

40_h

41_h

42_h

Capture Mode Register

2A_h

10_h

02_h

Table 27, pg 55

Table 28, pg 56

Table 29, pg 57

Yes

Sub-Sample Control Register

TRIGGER and Strobe Control Register

Unused

43_hÆ 44_h

45_h

WOI Row Pointer MSB Register

WOI Row Pointer LSB Register

WOI Row Depth MSB Register

WOI Row Depth LSB Register

WOI Column Pointer MSB Register

WOI Column Pointer LSB Register

WOI Column Width MSB Register

WOI Column Width LSB Register

Unused

00_h

10_h

03_h

FF_h

00_h

08_h

04_h

FF_h

Table 30, pg 58

Table 31, pg 58

Table 34, pg 59

Table 35, pg 60

Table 32, pg 59

Table 33, pg 59

Table 36, pg 60

Table 37, pg 60

Yes

46_h

47_h

48_h

49_h

4A_h

4B_h

4C_h

4D_h

4E_h

4F_h

50_h

51_h

52_h

53_h

54_h

55_h

56_h

57_h

Integration Time MSB Register

Integration Time LSB Register

Virtual Frame Row Depth MSB Register

Virtual Frame Row Depth LSB Register

Virtual Frame Column Width MSB Register

Virtual Frame Column Width LSB Register

SOF Delay Register

04_h

FF_h

04_h

27_h

05_h

13_h

4C_h

02_h

0E_h

04_h

Table 38, pg 61

Table 39, pg 61

Table 40, pg 62

Table 41, pg 63

Table 42, pg 63

Table 43, pg 63

Table 44, pg 64

Table 45, pg 64

Table 46, pg 65

Table 47, pg 66

Yes

No

VCLK Delay Register

SOF & VLCK Width Register

Readout Direction Control Register

Unused

58_hÆ 5E_h

5Fh

Internal Timing Control Register (SHA)

Internal Timing Control Register (SHB)

Factory Use Only

0A_h

Table 48, pg 67

Table 49, pg 67

Yes

60_h

61_hÆ 63_h

64_h

Clamp Control and HCLK Delay Register

Encoded Sync Register

Unused

5C_h

00_h

Table 50, pg 68

Table 51, pg 69

Yes

65_h

66_h

Factory Use Only

67_hÆ 68_h

69_hÆ 7F_h

80_hÆ BF_h

C0_hÆ FF_h

Unused

Mod64 Col Offset Registers

Unused

00_h

Table 52, pg 70

Table 12: I²C Address Assignments (40_h- FF_h)

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DETAILED REGISTER BLOCK ASSIGNMENTS

This section describes in further detail the

functional operation of the various KAC-1310

programmable registers.

register is programmable given the gain function

defined in the table. The user programs these

registers to account for changing light conditions

to assure a white balanced output. The default

value in each register provides for a unity gain for

the default Raw Mode. In addition, the default

CFA pattern color is listed in the title of each

register.

Color Gain Registers 00_hÆ 03_h

The four Color Gain Registers, Color Tile

Configuration Register, and four Color Tile Row

definitions define how white balance is achieved

on the device. Six-bit gain codes can be selected

for four separate colors: Table 13, Table 14, Table

15, and Table 16. Gain for each individual color

The Gain Mode is set by Register 22_h, Table 25 on

page 53.

Raw Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.02175 * Reg_d

≈ 1.3475 + 0.04350 * (Reg_d- 31)

0 < Reg_d< 31

32 < Reg_d< 63

(0.0695x Æ1.36925x)

(1.3910x Æ 2.7395x)

Lin1 Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.04350 * Reg_d

0 < Reg_d< 47

0 < Reg_d< 63

(0.695x Æ 2.7395x)

(0.483x Æ 7.488x)

Lin2 Gain Mode (Exposure gain stage only)

Gain ≈ 0.483 + 0.11119 * (Reg 10_h)_d

Address

00_h

Default

0E_h

PGA Color 1 Gain Code

Green1 or Cyan

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

cg1[0]

cg1[5]

cg1[4]

cg1[3]

cg1[2]

cg1[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused Unused

xx_b

5 - 0

Gain

See Gain Equation

001110_b

Default Gain in Raw mode = 1.0

Default Gain in Lin1 Mode = 1.3

Table 13: PGA Color 1 Gain Register (00_h)

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Address

01_h

Default

0E_h

PGA Color 2 Gain Code

Red or Yellow1

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

cg2[0]

cg2[5]

cg2[4]

cg2[3]

cg2[2]

cg2[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused Unused

xx_b

5 - 0

Gain

See Gain Equation

001110_b

Default Gain in Raw mode = 1.0

Default Gain in Lin1 Mode = 1.3

Table 14: PGA Color 2 Gain Register (01_h)

Address

02_h

Default

0E_h

PGA Color 3 Gain Code

Blue or Yellow2

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

cg3[0]

cg3[5]

cg3[4]

cg3[3]

cg3[2]

cg3[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused Unused

xx_b

5 - 0

Gain

See Gain Equation

001110_b

Default Gain in Raw mode = 1.0

Default Gain in Lin1 Mode = 1.3

Table 15: PGA Color 3 Gain Register (02_h)

Address

03_h

Default

0E_h

PGA Color 4 Gain Code

Green2 or Magenta

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

cg4[0]

cg4[5]

cg4[4]

cg4[3]

cg4[2]

cg4[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused Unused

xx_b

5 - 0

Gain

See Gain Equation

001110_b

Default Gain in Raw mode = 1.0

Default Gain in Lin1 Mode = 1.3

Table 16: PGA Color 4 Gain Register (03_h)

45

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Reference Voltage Adjust Registers (0A_h, 0B_h)

The analog register block allows programming the

input voltage range of the analog to digital

converter to match the saturation voltage of the

pixel array (this effectively sets the mV/dn

increased power consumption and increased

image artifacts. The following equation defines

the mV/DN at the input to the ADC:

If the 20x gain provided by the PGAs is not

sufficient, the ADC references can be used to

conversion ratio).

The voltage reference

generator can be programmed via two registers;

“positive” ADC reference voltage (prv) (2.5V to

1.25V) in Table 18, and “negative” ADC reference

voltage (nrv) (0 to 1.25V) in Table 17, in 5mV

steps. The default settings for prv produce a

1.86V positive reference. The default settings for

nrv produce a 0.59V negative reference. These

two references define the ADC analog input range.

When adjusting these values, the user should

keep the voltage range centered at 1.25V. These

ADC references can be adjusted to mV/DN of the

ADC. This effectively acts as another gain stage

just before the ADC. Excessive adjustment of

these values from their default can result in

+

−

mV 2(V −V ) 2(1.86−0.59)

mV

=

= 2.48

10dn

1024

apply additional gain to the ASP. To increase the

gain the ADC references need to be moved closer

to Vcm (1.25V). This should be used only after

the PGAs have been used to their fullest since

moving the ADC references too far will degrade

the ADC performance. The effective gain of the

ADC block will be:

2.48

Gain =

+

−

2(V −V

)

1024

Address

0A_h

Default

76_h

"Negative" ADC Reference Voltage

7 (msb)

nrv[7]

6

5

4

3

2

1

0 (lsb)

nrv[0]

nrv[6]

nrv[5]

nrv[4]

nrv[3]

nrv[2]

nrv[1]

Bit

Function Description

Reset

State

Number

Table 17: Negative Voltage Reference Register (0A_h)

Address

0B_h

Default

80_h

"Positive" ADC Reference Voltage

7 (msb)

prv[7]

6

5

4

3

2

1

0 (lsb)

prv[0]

prv[6]

prv[5]

prv[4]

prv[3]

prv[2]

prv[1]

Bit

Function Description

Reset

State

Number

7 - 0

Reference

Voltage = 2.5 - (5mV * prc_d)

10000000_b

(1.86V)

Table 18: Positive Voltage Reference Register (0B_h)

46

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Power Configuration Registers (0C_h)

The Power Configuration Register controls the

internal analog functionality that directly affects

power consumption of the device. A pair of

external precision resistor pins are available on

the KAC-1310 that may be used to more

accurately regulate the internal current sources.

This serves to minimize variations in power

consumption that are caused by variations in

internal resistor values as well as offer a method

to reduce the power consumption of the device.

The default for this control uses the internally

provided resistor which is nominally 12.5kΩ. This

feature is enabled by setting the res bit of the

Power Configuration Register and placing a

resistor between the EXTRESA and EXTRESB

pins. Figure 19 on page 30 depicts the power

savings that can be achieved with an external

resistor at the nominal clock rate of 10 MHz.

Power is further reduced at lower clock rates.

Figure 18 shows how the noise of the system is

affected by the EXTRES. It is recommended that

the External Resistor be kept at 39kΩ at nominal

speed. The optimal EXTRES value will change

based on system needs and chip frequency.

The KAC-1310 is put into a standby mode via the

I²C interface by setting the sby bit of the Power

Configuration Register. While the imager is in this

mode the power consumption is reduced

considerably (see Table 19). Also, the I²C

continues to work and any number of registers can

be programmed. Upon leaving standby state the

imager will remember all register settings and

apply them to the first imager captured.

Address

0C_h

Default

00_h

Power Configuration

7 (msb)

x

6

x

5

x

4

3

2

1

0 (lsb)

sby

fuo

res

fuo

Bit

Number

7 - 5

4

Function Description

Reset

State

xxx_b

0_b

Unused Unused

FUO

Factory Use

Only

3

Int/Ext

0_b= Internal Resistor

0_b

Resistor 1_b= External Resistor

2 - 1

0

FUO

Factory Use

Only

00_b

0_b

Software 0_b= Soft Standby Inactive

Standby 1_b= Soft Standby Active

Table 19: Power Configuration Register (0C_h)

47

K A C - 1 3 1 0 R e v

4

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w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Reset Control Register (0E_h)

1310 to the default state via the serial control

interface. All user programmable registers will

revert to default values. For each of these reset

bits a value of 0 must be sent to register 0Eh after

use to take the imager back out of reset mode.

Typically only the first two bits are needed. Bit 1

(ssr) resets all state machines and internal

registers, but leaves the programmable registers

intact. Bit 0 (sit) resets all registers, internal and

user programmable to default values.

Setting the asr, ssr, par, and sir bits of this

register will reset all the non-user programmable

registers to known reset state. All

a

programmable registers will retain their values.

This is useful in situations when control of the

KAC-1310 has been lost due to system interrupts

and the device needs only be restarted using the

earlier user programmed values. Setting the sit

bit allows the user to completely reset the KAC-

Address

0E_h

Default

00_h

Reset Control

7 (msb)

x

6

x

5

x

4

3

2

1

0 (lsb)

sit

asr

par

sir

ssr

Bit

Number

7 - 5

4

Function Description

Reset

State

xxx_b

0_b

Unused Unused

ASP(A2D) 0_b= Normal Mode

Reset

1_b= Reset registers in the ASP and ADC (state

machine reset)

3

2

Post ADC 0_b= Normal Mode

Reset

0_b

1_b= Reset non-programmable POST ADC internal registers to init state

Sensor 0_b= Normal Mode

Interface

1_b= Reset non-programmable Sensor Interface registers (state machines) to init

Reset

state

1

0

State

0_b= Normal Mode

0_b

Reset

1_b= Reset all non-programmable registers to default

state

Soft

0_b= Normal Mode

Reset

1_b= Reset all registers to default state (all programmed regs>default)

Table 20: Reset Control Register (0E_h)

48

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Exposure Gain A Register (10_h)

The PGA Exposure (Global) Gain Register allows

the user to set one of the global gains via a 6-bit

register. This is applied universally to all the pixel

outputs. This enables the user to account for

varying light conditions. The gain range depends

on the Exposure Gain Mode setting (Register 22_h,

Table 25 on page 53). In Raw or Lin1 mode both

Exposure Gain A (10_h) and Exposure Gain B (21_h)

are programmed as successive gains stages. If

Lin2 Mode is selected then Register 10_his used to

program both Exposure gain stages as if they

were one linear gain stage. Further discussion of

the Gain stages can be found the Programmable

Gain Amplifier section on page 17, and in the

Global Digital Offset Adjustment section on page

20. If register 10_his increased to its maximum and

still more gain is needed, Exposure Gain B can

then be increased, via Register 21_h, Table 24 on

page 52.

The gain equations of each gain mode are:

Raw Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.02175 * Reg_d

≈ 1.3475 + 0.04350 * (Reg_d- 31)

0 < Reg_d< 31

(0.0695x Æ1.36925x)

32 < Reg_d< 63 (1.3910x Æ 2.7395x)

Lin1 Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.04350 * Reg_d

0 < Reg_d< 47

0 < Reg_d< 63

(0.695x Æ 2.7395x)

(0.483x Æ 7.488x)

Lin2 Gain Mode (Exposure gain stage only)

Gain ≈ 0.483 + 0.11119 * (Reg 10_h)_d

NOTE: the gain step size of Lin2 Mode is almost, but not completely uniform. Any one step may deviate

from the mean step size of 0.11119 by a small amount. This is due to the fact that Lin2 Mode actually

varies two gain stages with fixed step sizes to make one equivalent gain step.

Address

10_h

Default

0E_h

Global Gain A

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

gg1[0]

gg1[5]

gg1[4]

gg1[3]

gg1[2]

gg1[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused Unused

xx_b

5 - 0

Gain

Gain equation depends on Gain Mode: Raw, Lin1, or Lin2 (Default is

unity gain for Raw mode)

001110_b

Table 21: A Exposure Gain A Register (10_h)

Tristate Control Register (12_h)

The Tristate Control Register is used to set the

chip outputs into tristate. This functionality is

useful if these outputs are on a bus that is being

shared by other devices. When the tsctl bit is

reset (ie “0”) the SOF, VCLK, HCLK, and STROBE

output pins are placed in tristate mode. The 10

ADC output pins can be tristated by resetting the

tspix bit (“0”).

49

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Address

12_h

Default

03_h

Tristate Control

7 (msb)

FUO

6

5

4

3

2

1

0 (lsb)

tspix

FUO

tsctl

Bit

Number

7 - 2

1

Function

Description

Reset

State

000000_b

1_b

FUO

Factory Use Only

Sync Tristate 0_b= HCLK, SOF, VCLK, and Strobe sync pins tristated

1_b= Sync pins driven

0

ADC Tristate 0_b= ADC outputs pins tristated

1_b= ADC output pins driven

1_b

Table 22: Tristate Control Register (12_h)

50

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Column DOVA DC Register (20_h)

Offset adjustments for the KAC-1310 are done in

separate sections of the ASP to facilitate FPN

removal and final image black level set. The

primary purpose of the Column DOVA DC

Register is to compensate for pre-gain offset. If

this register is set to zero the user may find that

the dark level of some chips may move with

different programmed gain values. In addition the

white balance gain stage can result in different

effective dark levels for different colors. These

effects MAY cause distortion with certain post

image signal processing. In these cases the

Column DOVA DC Register can be programmed

such that the dark pixel level is independent of

programmed gain values. The simplest method

for setting this register is to place the imager in the

dark and record the mean value for the dark

pixels. Then increase the global gain register

(10_h) to the maximum gain to be used in the

application. Adjust register 20_huntil the dark level

has returned to the level previously recorded with

unity gain. This process can be repeated again for

greater accuracy since the dark level at unity gain

will now have shifted slightly.

For many

applications, this register can be left in its default

state of 00_h. If during the calibration of this register

the value of any pixels are observed to be clipping

at zero counts, it is then necessary to temporarily

increase the ADC DOVA (reg 23_h) to avoid

clipping. Register 20_hshould not be used to adjust

the code value of the dark level for the ADC, this

should always be done with the ADC DOVA (reg

23_h)

The Column DOVA stage is also used to correct

for patterned column noise. This is done pre-gain.

The column pattern correction offsets are defined

in Reg 80_hÆ BF_h, see Table 52 on page 70. The

Column DOVA stage has only six bits of

programmability. Registers 20_his added to the

value in 80_hÆ BF_hfor that column. The final sum

is clipped to ±32_d.

Address

20_h

Default

00_h

Column DOVA DC

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

cdd[0]

cdd[5]

cdd[4]

cdd[3]

cdd[2]

cdd[1]

Bit

Number

7 - 6

5

Function Description

Reset

State

xx_b

Unused Unused

Sign

0_b= Positive Offset

1_b= Negative Offset

0_b

4 - 0

Column Offset = 2.6 * cdd_d(64 steps @ 2.6

00000_b

mV/step)

DC Offset

Table 23: Column DOVA DC Offset (20_h)

51

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Exposure GainB (21_h)

The PGA Exposure (Global) Gain Register allows

are programmed as successive gains stages. If

Lin2 Mode is selected then Register 10_his used to

program both Exposure gain stages as if they

were one linear gain stage. Further discussion of

the Gain stages can be found in “Programmable

Gain Amplifier” on page 17, and “Global Digital

Offset Adjust” on page 20. The gain equations of

each gain mode are:

the user to set one of the global gains via a 6 bit

register. This is applied universally to all the pixel

outputs. This enables the user to account for

varying light conditions. The gain range depends

on the Exposure Gain Mode setting (Register 22_h,

Table 25 on page 53). In Raw or Lin1 mode both

Exposure Gain A(10_h) and Exposure Gain B(21_h)

Raw Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.02175 * Reg_d

≈ 1.3475 + 0.04350 * (Reg_d- 31)

0 < Reg_d< 31

(0.0695x Æ1.36925x)

32 < Reg_d< 63 (1.3910x Æ 2.7395x)

Lin1 Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.04350 * Reg_d

0 < Reg_d< 47

(0.695x Æ 2.7395x)

Lin2 Gain Mode

This register is not used in this mode. See

Exposure Gain A, Table 21 on page 45 for

programming this mode.

Address

21_h

Default

Exposure Gain B

0E_h

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

gg2[0]

gg2[5]

gg2[4]

gg2[3]

gg2[2]

gg2[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused Unused

xx_b

5 - 0

Gain

Gain equation depends on Gain Mode: Raw, Lin1, or Lin2 (Default is

unity gain for Raw mode)

001110_b

Table 24: Exposure Gain B (21_h)

52

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

PGA Gain Mode (22_h)

There exist three different gain modes that are

gain modes are illustrated in Figure 12 on page

18. The three gain modes are:

available when the sensor is performing White

Balance and Exposure gain. Plots of the three

Raw Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.02175 * Reg_d

≈ 1.3475 + 0.04350 * (Reg_d- 31)

0 < Reg_d< 31

(0.0695x Æ1.36925x)

32 < Reg_d< 63 (1.3910x Æ 2.7395x)

0 < Reg_d< 47 (0.695x Æ 2.7395x)

0 < Reg_d< 63 (0.483x Æ 7.488x)

Lin1 Gain Mode (WB and Exposure)

Gain ≈ 0.6950 + 0.04350 * Reg_d

Lin2 Gain Mode (Exposure gain stage only)

Gain ≈ 0.483 + 0.11119 * (Reg 10_h)_d

NOTE: the gain step size of Lin2 Mode is almost, but not completely uniform. Any one step may deviate from the

mean step size of 0.11119 by a small amount. This is due to the fact that Lin2 Mode actually varies two gain stages

with fixed step sizes to make one equivalent gain step.

The wbm bit sets the gain mode for the WB gain (Register 0_h-3_h, pages 44 and 45).

The egm bits set the gain mode for the Exposure Gains Registers (10_hpage 49 and 21_hpage 52.)

Address

22_h

Default

00_h

PGA Gain Mode

7 (msb)

6

x

5

x

4

x

3

x

2

1

0 (lsb)

x

wbm

egm[1]

egm[0]

Bit

Reset

State

Function Description

Unused Unused

Number

7 - 3

xxxxx_b

WB Gain 0_b= Raw Gain Mode

2

0_b

Mode

1_b= Lin1 Gain Mode

00_b= Raw Gain Mode

01_b= Lin1 Gain Mode

1x_b= Lin2 Gain Mode

Exposure

1 - 0

00_b

Gain Mode

Table 25: PGA Gain Mode (22_h)

53

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

ADC DOVA (23_h)

The Global DOVA Register performs a final offset

offset range of ±124 dn. As an example, to

program an offset of +92 dn, the value of 010111_b

(23_d, 17_h) should be loaded. This offset is used to

place the dark level within the ADC range.

adjustment in analog space just prior to the ADC.

The 6-bit register uses its MSB to indicate positive

or negative offset. Each register value changes

the offset by 4 LSB code levels hence giving an

Address

23_h

Default

00_h

ADC DOVA

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

gd[0]

gd[5]

gd[4]

gd[3]

gd[2]

gd[1]

Bit

Number

7 - 6

5

Function Description

Reset

State

xx_b

Unused Unused

Sign

0_b= Positive Offset

1_b= Negative Offset

0_b

4 - 0

Column Offset (mV) = 12 * gd_d(64

00000_b

steps @ 12 mV/step)

DC Offset

Table 26: ADC DOVA Register (23_h)

54

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Capture Mode Control (40_h)

The Capture Mode Control Register defines how

When the hm bit is set, the HCLK sync is high

whenever valid WOI pixel data is being clocked

out and low during the other blanking intervals.

The HCLK does NOT toggle at the MCLK rate

when the hm bit is set. When hm is set the HCLK

will go high once at the beginning of the valid pixel

data and remain high until the last WOI pixel has

been clocked out. When the hm bit is set the he

bit is ignored. The sp bit is used to define whether

SOF is active high or low. SOF is active high by

default. The ve bit is used to determine whether

VCLK is output at the beginning of the virtual

frame rows or only for the WOI rows. The ve bit

defaults to VCLK on WOI rows only. The vp bit is

used to define whether VCLK is active high(the

default) or active low. The he bit is used to

determine whether HCLK is output continuously

(needed for some frame grabbers) or only for

pixels within the WOI (default). The hp bit is used

to define whether HCLK is active high (default) or

low.

the data is captured and how the data is to be

provided at the output. Setting the cms bit will

stop the current CFRS output data stream at the

end of the current frame and place the imager in

Single Frame Capture Mode (SFRS). While the

cms bit is set (SFRS), the output of frames can be

paused with the TRIGGER input pin. When the

TRIGGER pin is low (V_SS) the output of frames is

suspended. When the TRIGGER pin is high (V_DD)

frames are continuous. The default for cms is 0

(CFRS). In CFRS the frames are continuously

output and the TRIGGER pin is ignored. The

Frame Rate is slightly reduced when the cms is

set (SFRS) because care is taken in the startup

such that the first frame output is valid. This

causes a slight delay at the start of each frame.

See Figure 22 on page 32 for a timing diagram for

SFRS mode. With the cms low(=0), the Frame

Rate is faster, but the first frame will be invalid

(wrong integration time).

Address

40_h

Default

2A_h

Capture Mode Control

7 (msb)

FUO

6

cms

5

sp

4

ve

3

vp

2

he

1

hp

0 (lsb)

hm

Bit

Number

7

Function Description

Reset

State

0_b

FUO

Factory Use Only

6

5

RSCM

Mode

0_b= Continuous Frame Rolling Shutter (CFRS)

1_b= Single Frame Rolling Shutter (SFRS)

0_b= SOF sync active low

0_b

1_b

SOF

Phase

1_b= SOF sync active high

4

3

2

1

VCLK

Enable

VCLK

Phase

HCLK

Enable

HCLK

Phase

0_b= VCLK Sync on WOI rows only

1_b= VCLK Sync on WOI and Virtual Rows

0_b= Active low

0_b

1_b

0_b

1_b

1_b= Active high

0_b= Pixel sync on WOI pixels only

1_b= Continuous pixel sync

0_b= Active low

1_b= Active high

0

HCLK

Mode

0_b= Toggles - Toggles at MCLK rates defined by (he) bit

1_b= Continuous - Pixel Valid Envelope

0_b

Table 27: Capture Mode Register (40_h)

55

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Sub-sample Control (41_h)

The sub-sample Control Register is used to define

Bit cm can be cleared for monochrome imagers.

This allows the imager to skip single columns and

rows improving uniformity of sub-sampled MTF. In

color mode sub-sampling is done in column and

row pairs to conserve color integrity. The degree

of sub-sample is defined by rf [1:0] for the rows,

while the column sub-sample is independently

defined by cf [1:0]. Row binning (even/odd row

summing) is activated with the bn bit.

what pixels of the WOI are read and the method

they are output. See “Sub-Sampling Control

(Resolution)” on page 12 for details on the readout

modes. Sub-sampled frames readout faster than

the full frame image. Any pixel not selected in the

sub-sample mode is ignored, thereby not slowing

the Frame Rate.

Address

41_h

Default

10_h

Capture Mode Control

7 (msb)

x

6

5

4

3

2

1

0 (lsb)

cf[0]

FUO

bn

cm

rf[1]

rf[0]

cf[1]

Bit

Function Description

Reset

State

x_b

Number

7

6

Unused Unused

FUO

Factory Use

Only

0_b

5

4

Binning 0_b= Full WOI readout

1_b= Even/Odd Row Summing

0_b

1_b

Color

Mode

0_b= Monochrome Pattern Sampling (kernel=1)

1_b= Bayer Pattern Sampling (kernel=2)

3 - 2

Row Sub- 00_b= Full WOI readout

Sampling

00_b

01_b= Read one kernel, skip one (1/2 sampled)

Mode

10_b= Read one kernel, skip three (1/4 sampled)

11_b= Read one kernel, skip seven (1/8 sampled)

00_b= Full WOI readout

1 - 0

Column

00_b

Sub-Sampling 01_b= Read one kernel, skip one (1/2 sampled)

Mode

10_b= Read one kernel, skip three (1/4 sampled)

11_b= Read one kernel, skip seven (1/8 sampled)

Table 28: Sub-Sample Control Register (41_h)

56

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

TRIGGER and STROBE Control Register (42_h)

The saw bit allows the user to select how long the

STROBE signal is going to be on. If the bit is set

to 1, the STROBE output will go high when all

lines are concurrently integrating and will go low

when the integration time has completed and

readout has begun. It is during this period while

STROBE is high that a mechanical shutter must

open and close and/or flash must fire and quench

if these devices are being used with the imager. If

the shutter or flash operate at any other time

image artifacts can result. Note the integration

time must be greater than a frame readout time for

this output to be useful. The sae bit when enabled

will enable the STROBE signal to be generated

automatically by the sensor. This will only work in

Single Frame Rolling Shutter (SFRS) mode.

The se bit, when enabled, will allow for an external

signal to drive the trigger signal via the TRIGGER

pin on the chip. Enabling the sa bit forces the

trigger signal high until this bit is disabled. This

causes continuous frame processing in SFRS

mode. The sr bit, when enabled, causes the

TRIGGER signal to go high for exactly one clock

cycle, and then returns to a low. It remains low

until the sr bit is enabled again. This is used to

trigger a single frame capture via I²C rather than

the TRIGGER pin.

Address

42_h

TRIGGER and STROBE Control

Default

02_h

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

sr

sso

saw

sae

se

sa

Bit

Function Description

Reset

State

xx_b

Number

7 - 6

Unused Unused

5

4

Factory Use Only

Strobe Width 0_b= 1 line time

1_b= Pulse width is high while all rows are simultaneously integrating

0_b

3

2

1

STROBE 0_b= STROBE pin Disabled

Enable

0_b

1_b

1_b= STROBE pin Enabled

TRIGGER 0_b= External TRIGGER input pin Disabled (ignored)

Enable

1_b= External TRIGGER input pin Enabled

TRIGGER 0_b= No effect

Always On

1_b= TRIGGER input is internally held HIGH, TRIGGER input pin is

ignored

0

Software 0_b= No effect

0_b

TRIGGER

1_b= Triggers a single frame capture via I²C

Table 29: TRIGGER and STROBE Control Register (42_h)

57

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Programmable Window of Interest (WOI) (45_h-4C_h)

The WOI is defined by a set of registers that

indicate the upper-left starting point for the window

and another set of registers that define the size of

the window. Refer to Figure 7 on page 12 for a

pictorial representation of the WOI within the

WOI Row Depth, wrd[9:0] and the WOI Column

Depth, wcw[10:0] indicate the size of the WOI.

The user must be careful to create a WOI that is

completely confined within the Virtual Frame.

There is no logic in the sensor interface to prevent

the user from defining a WOI that addresses

nonexistent pixels.

active pixel array.

The WOI Row Pointer,

wrp[8:0], and the WOI Column Pointer, wcp[9:0],

mark the upper-left starting point for the WOI. The

Address

45_h

Default

00_h

WOI Row Pointer MSB

7 (msb)

x

6

x

5

x

4

x

3

x

2

1

0 (lsb)

wrp[8]

wrp[10]

wrp[9]

Bit

Number

7 - 3

Function Description

Reset

State

xxxxx_b

000_b

Unused Unused

2 - 0

WOI Row In conjunction with the WOI Row Pointer LSB Register, forms the

Pointer

11-bit WOI Row Pointer wrp[10:0]

Table 30: WOI Row Pointer MSB Register (45_h)

Address

46_h

Default

10_h

WOI Row Pointer LSB

7 (msb)

wrp[7]

6

5

4

3

2

1

0 (lsb)

wrp[0]

wrp[6]

wrp[5]

wrp[4]

wrp[3]

wrp[2]

wrp[1]

Bit

Function Description

Reset

State

Number

7 - 0

WOI Row In conjunction with the WOI Row Pointer MSB Register, forms the 11 00010000_b

Pointer

bit WOI Row Pointer wrp[10:0]

(16_d)

Table 31: WOI Row Pointer LSB Register (46_h)

58

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Address

49_h

Default

00_h

WOI Column Pointer MSB

7 (msb)

x

6

x

5

x

4

x

3

x

2

1

0 (lsb)

wcp[8]

wcp[10]

wcp[9]

Bit

Number

7 - 3

Function Description

Reset

State

xxxxx_b

000_b

Unused Unused

2 - 0

WOI Column In conjunction with the WOI Column Pointer LSB Register,

Pointer

forms the 11-bit WOI Column Pointer wcp[10:0]

Table 32: WOI Column Pointer MSB Register (49_h)

Address

4A_h

Default

08_h

WOI Column Pointer LSB

7 (msb)

wcp[7]

6

5

4

3

2

1

0 (lsb)

wcp[0]

wcp[6]

wcp[5]

wcp[4]

wcp[3]

wcp[2]

wcp[1]

Bit

Function Description

Reset

State

Number

7 - 0

WOI Column In conjunction with the WOI Column Pointer MSB Register,

00001000_b

(8_d)

Pointer

forms the 11-bit WOI Column Pointer wcp[10:0]

Table 33: WOI Column Pointer LSB Register (4A_h)

WOI Row Depth MSB

Address

47_h

Default

03_h

7 (msb)

x

6

x

5

x

4

x

3

x

2

1

0 (lsb)

wrd[8]

wrd[10]

wrd[9]

Bit

Number

7 - 3

Function Description

Reset

State

xxxxx_b

011_b

Unused Unused

2 - 0

WOI Row In conjunction with the WOI Row Depth LSB Register, forms the

Depth

11-bit WOI Row Depth wrd[10:0]

Table 34: WOI Row Depth MSB Register (47_h)

59

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Address

48_h

Default

FF_h

WOI Row Depth LSB

7 (msb)

wrd[7]

6

5

4

3

2

1

0 (lsb)

wrd[0]

wrd[6]

wrd[5]

wrd[4]

wrd[3]

wrd[2]

wrd[1]

Bit

Function Description

Reset

State

Number

7 - 0

WOI Row In conjunction with the WOI Row Depth MSB Register, forms

11111111_b

1024 Rows

Depth

the 11-bit WOI Row Depth wrd[10:0]

Desired = wrd_d+1

Table 35: WOI Row Depth LSB Register (48_h)

Address

4B_h

Default

WOI Column Width MSB

04_h

7 (msb)

x

6

x

5

x

4

x

3

x

2

1

0 (lsb)

wcw[10]

wcw[9]

wcw[8]

Bit

Number

7 - 3

Function Description

Reset

State

Unused Unused

xxxxxx_b

100_b

2 - 0

WOI Column In conjunction with the WOI Column Width LSB Register, forms

Width

the 11-bit WOI Column Width wcw[10:0]

Table 36: WOI Column Width MSB Register (4B_h)

Address

4C_h

Default

WOI Column Width LSB

FF_h

7 (msb)

wcw[7]

6

5

4

3

2

1

0 (lsb)

wcw[6]

wcw[5]

wcw[4]

wcw[3]

wcw[2]

wcw[1]

wcw[0]

Bit

Function Description

Reset

State

Number

7 - 0

WOI Column In conjunction with the WOI Column Width MSB Register, forms the

11111111

b

Width

11-bit WOI Column Width wcw[10:0]

wcw_d+1

Desired =

1280Columns

Table 37: WOI Column Width LSB Register (4C_h)

60

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Integration Time Control (4E_hÆ 4F_h)

The integration Time registers control the

integration time for the pixel array. Integration

time is measured in Virtual Row times. Refer to

Figure 8 on page 13 for a pictorial description of

the Virtual Frame and its relationship to the WOI

Frame. A Virtual Frame is the mechanism by

which the user controls the integration time and

frame time for the output data stream. By adding

additional rows or columns as ‘blanking’ to the

WOI to form the Virtual Frame, the user can

control the amount of blanking in both horizontal

and vertical space.

NOTE: The upd bit of Reg 4E_his used to indicate a change to cint[13:0]. Since multiple I²C writes may be needed to

complete desired frame to frame integration time changes, the upd bit signals that all desired programming has been

completed, and to apply these changes to the next frame captured. This prevents undesirable changes in integration

time that may result from I²C writes that span the “End of Frame” boundary. This upd bit has to be toggled from its

previous state in order for the new value of cint[13:0] to be accepted/updated by the sensor and take effect.

i.e. If its previous state is “0”, when writing a new cint value, first write cint[7:0] to register 4F_h, then write both cint

[13:8] and “1” to the upd bit to register 4E_h.

Integration Time = (cint_d+ 1) * (vcw_d+ shA_d+shB_d+19) * MCLK_period

where vcw_dis defined in registers 52_hand 53_h, Table 35 and Table 36 on page 60.

(NOTE ABOVE LEFT IN SINGLE COLUMN FORMAT FOR CONSISTENCY WITH OTHER “NOTES”)

Address

Default

Integration Time MSB

4E_h

04_h

7 (msb)

x

6

5

4

3

2

1

0 (lsb)

cint[8]

upd

cint[13]

cint[12]

cint[11]

cint[10]

cint[97]

Bit

Reset

State

Function Description

Unused Unused

Number

7

x_b

This bit must be toggled from its previous state to apply cint

to the integration time counter.

6

Update

0_b

Integration In conjuction with the Integration Time LSB Register, forms

5 - 0

000100_b

Time

the 14-bit Integration Time cint[13:0].

Table 38: Integration Time MSB Register (4E_h)

Address

4F_h

Default

FF_h

Integration Time LSB

7 (msb)

cint[7]

6

5

4

3

2

1

0 (lsb)

cint[0]

cint[6]

cint[5]

cint[4]

cint[3]

cint[2]

cint[1]

Bit

Reset

State

Function Description

Number

In conjuction with the Integration Time MSB Register, forms

the 14-bit Integration Time cint[13:0].

Integration

Time

11111111_b

1280 Rows

7 - 0

Integration Time = (cintd +1) * Trow

Table 39: Integration Time LSB Register (4F_h)

61

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Programmable Virtual Frame (50_hÆ 53_h)

A Virtual Frame is the mechanism by which the

user controls the integration time and frame time

for the output data stream. By adding additional

rows or columns as ‘blanking’ to the WOI to form

the Virtual Frame, the user can control the amount

of blanking in both horizontal and vertical space.

Both the Virtual Frame Row Depth, vrd[13:0], and

the Virtual Frame Column Width, vcw[13:0], have

a range of 0_dto 16384_d. The Virtual Frame

defines the maximum integration time. If the

integration register is programmed with more rows

than are in the Virtual Frame then the integration

time will be clipped to the number of rows in the

virtual frame.

The user should be careful to create a Virtual

Frame that is larger than the WOI. There is no

logic in the sensor interface to prevent the user

from defining a Virtual Frame smaller than the

WOI. Therefore, pixel data may be lost. The

Virtual Frame must be at least 1 row and 118

columns larger than the WOI.

Address

Default

05_h

Virtual Frame Column Width MSB

52_h

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

vcw[8]

vcw[13] vcw[12]

vcw[11] vcw[10] vcw[9]

Bit

Reset

State

Function

Unused

Description

Unused

Number

7 - 6

5 - 0

xx_b

In conjunction with the Virtual Frame Column Width

Virtual Column

Width

LSB Register, forms the 14-bit Virtual Frame Column 000101_b

Width vcw[13:0].

Table 40: Virtual Frame Row Depth MSB (50_h)

Address

53_h

Default

13_h

Virtual Frame Column Width LSB

7 (msb)

vcw[7]

6

5

4

3

2

1

0 (lsb)

vcw[0]

vcw[6]

vcw[5]

vcw[4]

vcw[3]

vcw[2]

vcw[1]

Bit

Reset

State

Function

Description

Number

In conjunction with the Virtual Frame Column Width

MSB Register, forms the 14-bit Virtual Frame

Column Width vcw[13:0]. WOI is always top-left

justified in Virtual Frame.

00010011_b

1300

Virtual Column

Width

7 - 0

Columns

vcw_dminimim = wcw_d+11

Table 41: Virtual Frame Row Depth LSB (51_h)

62

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Address

52_h

Default

05_h

Virtual Frame Column Width MSB

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

vcw[8]

vcw[13] vcw[12]

vcw[11] vcw[10] vcw[9]

Bit

Reset

State

Function

Unused

Description

Unused

Number

7 - 6

xx_b

In conjunction with the Virtual Frame Column Width

LSB Register, forms the 14-bit Virtual Frame

Column Width vcw[13:0].

Virtual Column

Width

5 - 0

000101_b

Table 42: Virtual Frame Column Width MSB (52_h)

Address

53_h

Default

13_h

Virtual Frame Column Width LSB

7 (msb)

vcw[7]

6

5

4

3

2

1

0 (lsb)

vcw[0]

vcw[6]

vcw[5]

vcw[4]

vcw[3]

vcw[2]

vcw[1]

Bit

Reset

State

Function

Description

Number

In conjunction with the Virtual Frame Column

Width MSB Register, forms the 14-bit Virtual

Frame Column Width vcw[13:0]. WOI is always

top-left justified in Virtual Frame.

00010011_b

1300

Virtual Column

Width

7 - 0

Columns

vcw_dminimim = wcw_d+11

Table 43: Virtual Frame Column Width LSB (53_h)

63

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

SOF and VCLK Delay Registers (54_hand 55_h)

This adjust can be used to vary the sync positions

(rising and falling edges) relative to valid pixel

data. In this way an acquisition system that uses

the sync pulses for display can be shifted to add or

avoid image borders. Adjusting the position or

length of the SOF or VCLK sync does NOT alter

the Frame Rate, the sync signal is simply shifted

and overlaps the valid line and pixel data. Moving

the rising edge of the SOF will also move the

rising edge of the VCLK. This is so that the VCLK

sync does not occur before the SOF pulse. The

delay adjust is in

½ cycles, it takes two

programmed counts to delay the rising edge by

one image pixel. These delays are measured

from the change of the row address, which is not

directly observable except to set the delay to 0.

Address

54_h

Default

4C_h

SOF Delay

7 (msb)

sofd[7]

6

5

4

3

2

1

0 (lsb)

sofd[0]

sofd[6]

sofd[5]

sofd[4]

sofd[3]

sofd[2]

sofd[1]

Bit

Function

Description

Reset

State

Number

7 - 0

SOF Delay Delay = sofd_d* 0.5 MCLK's

01001100_b

Table 44: SOF Delay Register (54_h)

Address

55_h

Default

02_h

VCLK Delay

7 (msb)

vckd[7]

6

5

4

3

2

1

0 (lsb)

vckd[6]

vckd[5]

vckd[4]

vckd[3]

vckd[2]

vckd[1]

vckd[0]

Bit

Function

Description

Reset

State

Number

7 - 0

VCLK Delay Delay = vckd_d* 0.5 MCLK's

Table 45: VCLK Delay Register (55_h)

00000010_b

64

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

SOF & VCLK Width Register (56_h)

The SOF & VCLK register moves the falling edge

of the sync pulses. The widths can be adjusted for

maximum compatibility with the frame capture

device. The sofw bit adjusts the width of the SOF

sync and vckw adjusts the width of the VCLK

pulse.

Address

56_h

Default

0E_h

SOF & VCLK Width

7 (msb)

x

6

x

5

x

4

x

3

2

1

0 (lsb)

sofw[1]

sofw[0]

vckw[1]

Vckw(0)

Bit

Number

7 - 4

Function Description

Reset

State

Unused Unused

xxxxb

3 - 2

SOF Contro 00_b= 1 MCLK Wide

01_b= 8 MCLKs Wide

11b

10_b= 64 MCLKs Wide

11_b= Full Row Wide

1 - 0

VCLK 00_b= 1 MCLK Wide

Control

01_b= 8 MCLKs Wide

10b

10_b= 64 MCLKs Wide

11_b= Full Row Wide

Table 46: SOF & VCLK Width Register (56_h)

65

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Readout Direction Register (57_h)

This register allows the user to change the

direction of readout of the columns or rows. This

can be used to compensate for and orientation of

the imager in the optical system. The rrc when

enabled causes the column data to be readout in

the reverse direction as compared to the normal

readout direction. The rrr when enabled causes

the row data to be readout in the reverse direction

as compared to the normal readout direction. The

normal readout direction of the imager is shown in

Figure 2 on page 7.

Address

57_h

Default

04_h

Readout Direction

7 (msb)

x

6

x

5

x

4

x

3

2

1

0 (lsb)

rrc

FUO

rrr

Bit

Number

7 - 4

3 - 2

1

Function

Description

Reset

State

xxxx_b

01_b

Unused

FUO

Unused

Factory Use Only

Reverse

0_b= Normal Readout (Bottom to Top)

0_b

Readout Row 1_b= Rows Readout in reverse order (Top to Bottom)

Reverse 0_b= Normal Readout (Left to Right)

0

0_b

Readout Col 1_b= Cols readout in reverse order (Right to Left)

Table 47: Readout Direction Register (57_h)

66

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Internal Timing Control Registers (5F_hand 60_h)

These registers are used to define the size of

internal timing pulse widths shA (sample & hold

sample) and shB (sample & hold reset). In default,

both are 10 MCLKs wide. A maximum of 64

MCLKs can be programmed for the shA delay and

another 64 MCLKs for the shB delay. Writing 00h

to either register will provide the maximum timing

delay of 64 MCLKs.

Address

5F_h

Default

0A_h

Internal Timing Control

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

shA[0]

shA[5]

shA[4]

shA[3]

shA[2]

shA[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused Unused

xxxx_b

5 - 0

shA

shA[5:0]=000000b=64 MCLKs Wide

shs[5:0]=000001b=1d MCLKs Wide

001010b

shA[5:0]=000001b=1d MCLKs Wide

shA[5:0]=000010b=2d MCLKs Wide

shA[5:0]=000011b=3d MCLKs Wide

|

shA[5:0]=111111b=63d MCLKs Wide

Table 48: Internal Timing Control Register (5F_h)

Address

60_h

Default

0A_h

Internal Timing Control

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

shB[0]

shB[5]

shB[4]

shB[3]

shB[2]

shB[1]

Bit

Number

7 - 6

Function Description

Reset

State

Unused

shB

Unused

xxxx_b

5 - 0

shB[5:0]=000000b=64 MCLKs Wide

shs[5:0]=000001b=1d MCLKs Wide

001010b

shB[5:0]=000001b=1d MCLKs Wide

shB[5:0]=000010b=2d MCLKs Wide

shB[5:0]=000011b=3d MCLKs Wide

|

Table 49: Internal Timing Control Register (60_h)

67

K A C - 1 3 1 0 R e v

4

•

w w w . k o d a k . c o m / g o / i m a g e r s

5 8 5 - 7 2 2 - 4 3 8 5

E m a i l : i m a g e r s @ k o d a k . c o m

IMAGE SENSOR SOLUTIONS

Clamp Control and HCLK Delay Register (64_h)

This register is used to delay the position of the

first HCLK, which corresponds to the first valid

pixel in each row. The delay is only useful when

the HCLK is not continuous. This delay can be

used to compensate for any latency in the user’s

capture device. In addition, this register also

allows one to disable the Frame Clamp if desired

for specific applications (see “Frame Rate Clamp

(FRC)”on page 16).

Address

64_h

Default

5C_h

Clamp Control and HCLK Delay

7 (msb)

x

6

5

4

3

2

1

0 (lsb)

fce[6]

FUO

hckd[2]

hckd[1]

hckd[0]

Bit

Function

Description

Reset

State

x_b

Number

7

6

Unused

Frame Clamp 0_b= Clamp Disabled

1_b

Enable

1_b= Clamp Enabled

5 - 3

2 - 0

FUO

011_b

100_b

HCLK Delay Syncs rising edge of HCLK to valid data from ADC

Delay = ((hckd[d]-4) x 0.5) - 16 MCLKs

Table 50: Clamp Control and HCLK Delay Register (64_h)

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IMAGE SENSOR SOLUTIONS

Encoded Sync Register (65_h)

It is possible to capture the image data without the

SOF, VCLK, or HCLK syncs. Once the encoded

Syncs are enabled, 4 10bit words are placed into

the data stream adding 4 pixel times per row. The

inserted codes tells the user when the row starts

and what type of row it is. Figure 24 on page 34

illustrates the encoded syncs in a data stream.

The vcb bit allows the user to force all the

Blanking data coming out of the ADC to be 0. The

vcg bit allows the user to enable/disable encoded

sync data in the output stream (see Table 2 on

page 12). The vcc bit allows the user to clip the

output active pixel data to lie between 1 and 1022

to avoid confusion with the encoded sync data in

the output stream.

Address

65_h

Default

00_h

Encoded Sync Control

7 (msb)

x

6

5

4

3

2

1

0 (lsb)

FUO

vcb

vsg

vcc

FUO

Bit

Function Description

Reset

State

x_b

Number

7

6

Unused Unused

Blanking 0_b= Dark Pixels Used for Blanking

1_b= H-Blanking and V-Blanking are forced to Dout=0

Encoded Sync 0_b= Normal Readout

0_b

5

4

0_b

Enable

1_b= Enable Encoded Syncs in Data Stream

Data Clipping 0_b= Normal Readout

1_b= Pixel Data of 0 and 1023 will be clipped to 1 and

1022

3 - 0

FUO

Factory Use

Only

0000_b

Table 51: Encoded Sync Register (65_h)

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IMAGE SENSOR SOLUTIONS

Mod64 Column Offset Correction Register (80_h-BF_h)

The Mod64 Column Offset registers are used to

reduce/eliminate collimated fixed pattern noise

to Column 1, 65, 129..., Register BF_hColumn

offset will be applied to Column 63, 127, 191...etc.

(FPN).

There are 64 registers that can be

programmed with individual offset values. They

will be applied to all the columns on a single image

frame on a Modular 64 basis. i.e. Register 80_h

Column offset will be applied to Column 0 , 64,

128..., Register 81_hColumn offset will be applied

The Column DOVA stage has only six bits of

programmability. Registers 20_his added to the

value in 80_hÆBF_hfor that column. The final sum

is truncated to ±32_d.

Address

80-BFh

Default

00_h

Mod64 Column Offset Correction

7 (msb)

x

6

x

5

4

3

2

1

0 (lsb)

mdd[5]

mdd[4]

mdd[3]

mdd[2]

mdd[1]

mdd[0]

Bit

Number

7 - 6

5

Function Description

Reset

State

xxb

Unused Unused

Sign

0b = Positive Offset

1b = Negative Offset

0b

4 - 0

Column Offset = 2.6 * mddd (64 step @

00000b

2.6mV/step)

Offset

Table 52: Mod64 Column Offset Correction Register (80_h-BF_h)

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IMAGE SENSOR SOLUTIONS

STORAGE AND HANDLING

Storage Conditions

Description

Temperature

Minimum

Maximum

Units

Conditions

Notes

-55

+70

@10%+/5%RH

1,2

°C

@49+/-2°C

Humidity

----

95+/-5

%RH

1,2

Temp.

Notes:

1. The tolerance on all relative humidity values is provided due to limitations in measurement instrument

accuracy.

2. The image sensor shall meet the specifications of this document after storage for 15 days at the specified

conditions.

Caution: This device contains limited protection against Electrostatic Discharge (ESD)

Devices should be handled in accordance with strict ESD protection procedures for Class 2 devices (JESD22 Human

Body Model) or Class B (Machine Model). Refer to Application Note MTD/PS-0224, “Electrostatic Discharge

Control”

Caution: Improper cleaning of the cover glass may damage these devices.

Refer to Application Note MTD/PS-0237, “Cover Glass Cleaning for Image Sensors”

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IMAGE SENSOR SOLUTIONS

REFLOW SOLDERING RECOMMENDATIONS

When using a reflow soldering system, the thermal profile shown in Figure 28 below is the maximum

thermal stress conditions recommended. If the temperature and/or time of the soldering process exceeds

that of the recommended profile, there is a possibility of damaging the sensor due to thermal stress.

225^oC

Peak Temperature

< 3^o/sec

215^oC

20 - 30 sec max

60 to 100 sec

Pre-heat

150^oC +/- 10^oC

< 3^o/sec

Time

Figure 28: Recommended Reflow Soldering System Thermal Profile

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IMAGE SENSOR SOLUTIONS

MECHANICAL DRAWINGS

47X

H

A

B

48X

A B C

D

4X R

C

M

0 . 0 0 6

0 . 0 1 0 M A B M C M

48

1

C

F

44X G

E

48X R1

REF

A

Dimension Minimum (inches)

Nominal (inches)

Maximum (inches)

A

B

0.555

0.525

---

0.56

0.54

0.572

0.545

0.094

0.024

0.067

0.095

C

D

E

---

0.016

0.055

0.075

0.02

0.061

0.085

0.04 BSC

0.04

F

G

H

J

0.033

0.555

0.525

0.047

0.572

0.545

0.56

K

0.54

R

R1

0.008 REF

0.028 REF

Figure 29: 48-Pin Terminal Ceramic Leadless Chip Carrier (Bottom View)

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IMAGE SENSOR SOLUTIONS

48 Ceramic LCC - Matrix Format

Metric (mm)

English (mils)

Nominal

Dimension

Description

Min

0.5

Nominal

Max

Min.

Max

A

B

C

D

E

F

Glass (Thickness)

0.55

0.6

19.69

39.00

27.76

15.00

0.50

21.65

44.00

28.54

17.00

1.00

23.62

49.00

29.33

19.00

2.00

Cavity (Depth)

0.9906

0.705

1.1176

0.725

1.2446

0.745

Die - Si (Thickness)

Bottom Layer (Thickness)

Die Attach - bondline (Thickness)

Glass Attach - bondline (Thickness)

Imager to Lid - outer surface (d)

Imager to Lid - inner surface (d)

Imager to seating plane - of pkg

0.381

0.4318

0.0254

0.9426

0.3926

1.1822

2.1248

1.5494

0.4826

0.0508

1.1777

0.5777

1.2784

2.378

0.0127

0.00635

0.70115

0.20115

1.0987

1.87795

1.397

0.25

1.00

2.00

G

H

J

27.60

7.92

37.11

15.46

46.54

83.65

61.00

46.37

22.74

50.33

93.62

67.00

43.26

73.93

55.00

A+B+F+DPkg (Th - total)

B+D

Base (Th)

1.7018

Reference Notes:

1 mil = 25.4µm

1 mm = 39.37 mil

Table 53: 48 Ceramic LCC – Matrix Format

A

F - Lid Seal thickness

G

H

B

J

D

C - Die

E - Die Attach thickness

Figure 30: CLCC-IB package vertical Dimensioning

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IMAGE SENSOR SOLUTIONS

QUALITY ASSURANCE AND RELIABILITY

Quality Strategy: All image sensors will conform

to the specifications stated in this document. This

will be accomplished through a combination of

statistical process control and inspection at key

points of the production process. Typical

specification limits are not guaranteed but

Immovable particles and scratches that are within

the imager pixel area and the corresponding cover

glass region directly above the pixel sites are also

not allowed. The cover glass is highly susceptible

to particles and other contamination. Touching the

cover glass must be avoided. See ISS Application

Note MTD/PS-0237, Cover Glass Cleaning, for

further information.

provided as

a

design target. For further

information refer to ISS Application Note MTD/PS-

0292, Quality and Reliability.

ESD Precautions: Devices are shipped in static-

safe containers and should only be handled at

static-safe workstations. See ISS Application Note

MTD/PS-0224, Electrostatic Discharge Control for

handling recommendations.

Replacement: All devices are warranted against

failure in accordance with the terms of Terms of

Sale. This does not include failure due to

mechanical and electrical causes defined as the

liability of the customer below.

Reliability: Information concerning the quality

assurance and reliability testing procedures and

results are available from the Image Sensor

Solutions and can be supplied upon request. For

further information refer to ISS Application Note

MTD/PS-0292, Quality and Reliability.

Liability of the Supplier: A reject is defined as an

image sensor that does not meet all of the

specifications in this document upon receipt by the

customer.

Liability of the Customer: Damage from

mechanical (scratches or breakage), electrostatic

discharge (ESD) damage, or other electrical

misuse of the device beyond the stated absolute

maximum ratings, which occurred after receipt of

the sensor by the customer, shall be the

responsibility of the customer.

Test Data Retention: Image sensors shall have

an identifying number traceable to a test data file.

Test data shall be kept for a period of 2 years after

date of delivery.

Mechanical: The device assembly drawing is

provided as a reference. The device will conform

to the published package tolerances.

Cleanliness: Devices are shipped free of mobile

contamination inside the package cavity.

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IMAGE SENSOR SOLUTIONS

ORDERING INFORMATION

Available Part Configurations

Type

Description

Glass Configuration

Sealed

KAC-1310

RGB with microlens

CMY with microlens

Sealed

Please contact Image Sensor Solutions for available part numbers.

Address all inquiries and purchase orders to:

Image Sensor Solutions

Eastman Kodak Company

Rochester, New York 14650-2010

Phone: (585) 722-4385

Fax: (585) 477-4947

E-mail: imagers@kodak.com

Kodak reserves the right to change any information contained herein without notice. All information

furnished by Kodak is believed to be accurate.

WARNING: LIFE SUPPORT APPLICATIONS POLICY

Kodak image sensors are not authorized for and should not be used within Life Support Systems without

the specific written consent of the Eastman Kodak Company. Product warranty is limited to replacement

of defective components and does not cover injury or property or other consequential damages.

Revision Changes

No.

Date

Description of Revision

4

11/6/02

Updated to new format.

Page 71: Revised ESD statements.

Page 75: Updated Cover Glass Cleaning Application Note document reference number.

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型号：	KAC-1310
厂家：	ETC
描述：	1280 (H) x 1024 (V) SXGA CMOS Image Sensor 1280 （H ）× 1024 （ V） SXGA CMOS图像传感器传感器图像传感器 CD
文件：	总76页 (文件大小：734K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KAC-1310 [ETC]

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