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L138-FI-236-RL [ETC]

MityDSP-L138F Processor Card;
L138-FI-236-RL
型号： L138-FI-236-RL
厂家： ETC    ETC
描述：

MityDSP-L138F Processor Card
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Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
FEATURES  
TI OMAP-L138 Dual Core Application  
Processor  
-
-
456 MHz (Max) C674x VLIW DSP  
. Floating Point DSP  
. 32 KB L1 Program Cache  
. 32 KB L1 Data Cache  
. 256 KB L2 cache  
. 1024 KB boot ROM  
. JTAG Emulation/Debug  
456 MHz (Max) ARM926EJ-S MPU  
. 16 KB L1 Program Cache  
. 16 KB L1 Data Cache  
. 8 KB Internal RAM  
(actual size)  
APPLICATIONS  
Embedded Instrumentation  
Industrial Automation  
. 64 KB boot ROM  
. JTAG Emulation/Debug  
Industrial Instrumentation  
Medical Instrumentation  
Embedded Control Processing  
Network Enabled Data Acquisition  
Test and Measurement  
Software Defined Radio  
Bar Code Scanners  
Power Protection Systems  
Portable Data Terminals  
On-Board Xilinx Spartan-6 FPGA  
-
Up To XC6SLX45  
. Up To 2,088 KBits Block RAM  
. Up To 6,822 Slices (6 Input LUTs)  
1050 Mbps data rate  
-
-
JTAG Interface/Debug  
Up To 256 MB mDDR2 CPU RAM  
Up To 512 MB Parallel NAND FLASH  
8 MB SPI based NOR FLASH  
Integrated Power Management  
Standard SO-DIMM-200 Interface  
BENEFITS  
Rapid Development / Deployment  
Multiple Connectivity and Interface Options  
Rich User Interfaces  
High System Integration  
Fixed & Floating Point Operations in Single  
CPU  
-
-
-
-
-
-
-
-
-
-
96 FPGA User I/O Pins  
10/100 EMAC MII / MDIO  
2 UARTS  
2 McBSPs  
2 USB Ports  
Video Output  
Camera/Video Input  
MMC/SD  
High Level OS Support  
-
-
-
-
Linux  
QNX 6.4  
Windows Embedded CE Ready  
ThreadX Real Time OS  
SATA  
Single 3.3V Power Supply  
Embedded Digital Signal Processing  
DESCRIPTION  
The MityDSP-L138F is a highly configurable, very small form-factor processor card that  
features a Texas Instruments OMAP-L138 456 MHz (max) Applications Processor  
(OMAP) tightly integrated with the Xilinx Spartan-6 Field Programmable Gate Array  
(FPGA), FLASH (NAND, and NOR) and mDDR2 RAM memory subsystems. The  
design of the MityDSP-L138F allows end users the capability to develop programs/logic  
images for both the OMAP and the FGPA. The MityDSP-L138F provides a complete  
and flexible digital processing infrastructure necessary for the most demanding embedded  
applications development.  
1
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
The onboard OMAP-L138 processor provides a dual CPU core topology. The OMAP-  
L138 includes an ARM926EJ-S micro-processor unit (MPU) capable of running the rich  
software applications programmer interfaces (APIs) expected by modern system  
designers. The ARM architecture supports several operating systems, including Linux  
and Windows Embedded CE. In addition to the ARM core, the OMAP-L138 also  
includes a TMS320C674x floating point digital signal processing (DSP) core. The DSP  
core supports the freely provided TI DSP/BIOS real-time kernel. Users can leverage the  
DSP to execute real-time compute algorithms (codecs, image/data processing,  
compression techniques, filtering, etc.)  
1.2V  
8MB NOR Flash  
(SPI interface)  
For uBoot  
Up To 512MB  
NAND Flash  
8-bit wide  
Up To 256MB  
mDDR Memory  
16-bit wide  
1.8V  
2.5V  
3.3V  
Power  
Management  
bootloader  
For root FFS  
EMIFA (16-bit)  
System  
Clocks  
JTAG  
JTAG  
Header  
JTAG/Emulator  
Emulator  
Header  
MMCSD 1  
EMAC RMII  
UHPI  
Texas Instruments  
OMAP-L138  
456-MHz ARM926EJ-S ™ RISC MPU  
456-MHz C674x VLIW DSP  
Xilinx  
Spartan-6  
FPGA  
uPP  
Up To XC6SLX45  
CSG324 pkg.  
LCD  
(Many pins are multiplexed between peripherals)  
VPIF I/O  
Boot  
Config  
FPGA I/O  
Banks can be  
1.8V, 2.5V, or  
3.3V  
SO-DIMM-200 (DDR2 Connector)  
Figure 1 MityDSP-L138F Block Diagram  
Figure 1 provides a top level block diagram of the MityDSP-L138F processor card. As  
shown in the figure, the primary interface to the MityDSP-L138F is through a standard  
SO-DIMM-200 card edge interface. The interface provides power, synchronous serial  
connectivity, and up to 96 pins of configurable FPGA I/O for application defined  
interfacing. Details of the SO-DIMM-200 connector interface are included in the SO-  
DIMM-200 Interface Description, as shown below.  
2
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
 
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
FPGA Bank I/O  
The MityDSP-L138F provides 96 lines of FPGA I/O directly to the SO-DIMM-200 card  
edge interface. The 96 lines of FPGA I/O are distributed across 2 banks of the FPGA.  
These I/O lines and their associated logic are completely configurable within the FPGA  
at the end user’s discretion.  
With the Xilinx Spartan-6 series FPGA, up to the XC6SLX45, each of the user controlled  
banks may be configured to operate on a different electrical interface standard based on  
input voltage provided at the card edge connector. The banks support 3.3V, 2.5V, and  
1.8V standard CMOS switching level technology. In addition, the I/O lines from the  
FPGA have been routed as differential pairs and support higher speed LVDS standards as  
well as SSTL 2.5 switching standards. Various forms of termination (pull-up/pull-down,  
digitally controlled impedance matching) are available within the FPGA switch fabric.  
Refer to the Xilinx Spartan 6 user’s guide for more information.  
OMAP-L138 mDDR2 Memory Interface  
The OMAP-L138 includes a dedicated DDR2 SDRAM memory interface shared between  
the onboard ARM and DSP cores. The MityDSP-L138F includes up to 256 MB of  
mDDR2 RAM integrated with the OMAP-L138 processor. The bus interface is capable  
of burst transfer rates of 600 MB / second. Note that the OSCIN frequency to the OMAP-  
L138 processor on the module is 24MHz.  
OMAP-L138 SPI NOR FLASH Interface  
The MityDSP-L138F includes 8 MB of SPI NOR FLASH. This FLASH memory is  
intended to store a factory provided bootloader, and typically a compressed image of a  
Linux kernel for the ARM core processor.  
EMIFA - FPGA / NAND FLASH Interface  
The OMAP-L138 and the Spartan-6 FPGA are connected using the DSP Asynchronous  
External Memory Interface (EMIFA). The EMIFA interface includes 3 chip select  
spaces. The EMIF interface supports multiple data width transfers and bus wait state  
configurations based on chip select space. 8, and 16 bit data word sizes may be used.  
Two of the three chip select lines (CE2, CE3) are reserved for the FPGA interface. The  
MityDSP-L138F also includes 4 lines between the FPGA and the OMAP for the purposes  
of generating interrupt signals.  
In addition to the FPGA, up to 512 MB of on-board NAND FLASH memory is  
connected to the OMAP-L138 using the EMIFA bus. The FLASH memory is 8 bits wide  
and is connected to third chip select line of the EMIFA (CE1). The FLASH memory is  
typically used to store the following types of data:  
- ARM Linux / Windows Embedded CE / QNX embedded root file-system  
- FPGA application images  
- runtime DSP or ARM software  
- runtime application data (non-volatile storage)  
3
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
OMAP-L138 Camera and Video Interfaces  
The OMAP-L138 includes an optional video port I/O interface commonly used to drive  
LCD screens as well as a camera input interface. These interfaces have been routed to  
the FPGA, which may be routed to the FPGA output pins on the SO-DIMM-200  
connector. By routing the video data through the FPGA, additional user customization  
and/or processing (e.g., overlays of video output, preprocessing or filtering of camera  
input) may be offloaded from the OMAP-L138 to the FPGA for computation intensive  
applications.  
Debug Interface  
Both the JTAG interface signals for the FPGA and the JTAG and emulator signals for the  
OMAP-L138 processor have been brought out to a Hirose header that is intended for use  
with an available Critical Link breakout adapter. This header can be removed for  
production units; please contact your Critical Link representative for details.  
This adapter is not included with individual modules but is included with each Critical  
Link Development Kit that is ordered. If an adapter, Critical Link (CL) part number  
80-000286, is needed please contact your Critical Link representative.  
Software and Application Development Support  
Users of the MityDSP-L138F are encouraged to develop applications and FPGA  
firmware using the MityDSP-L138F hardware and software development kit provided by  
Critical Link LLC.  
The development kit includes an implementation of an  
OpenEmbedded board support package providing an Angstrom based Linux distribution  
and compatible gcc compiler tool-chain with debugger. In addition, the development kit  
includes support libraries necessary to program the DSP core using the TI Code  
Composer Studio DSP compiler tool-chain.  
To support rapid FPGA and applications development, netlist components - compatible  
with the Xilinx ISE FPGA synthesis tool – for commonly used FPGA designs and a  
corresponding set of Linux loadable kernel modules and/or DSP interface APIs are  
included.  
The libraries provide the necessary functions needed to configure the  
MityDSP-L138F, program standalone embedded applications, and interface with the  
various hardware components both on the processor board as well as a custom  
application carrier card. The libraries include several interface “cores” – FPGA and DSP  
software modules designed to interface with various high performance data converter  
modules (ADCs, DACs, LCD and touchscreen interfaces, etc) – as well as bootloading  
and FLASH programming utilities.  
Growth Options  
The OMAP-L138 has been designed to support several upgrade options. These options  
include various speed grades, memory configurations, and operating temperature  
specifications including commercial and industrial temperature ranges. The available  
options are listed in the section below containing ordering information. For additional  
ordering information and details regarding these options, or to inquire about a particular  
configuration not listed below, please contact a Critical Link sales representative.  
4
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
ABSOLUTE MAXIMUM RATINGS  
OPERATING CONDITIONS  
If Military/Aerospace specified cards are  
required, please contact the Critical Link Sales  
Office or unit Distributors for availability and  
specifications.  
Ambient Temperature  
Range Commercial  
0oC to 70oC  
Ambient Temperature  
Range Industrial  
-40oC to 85oC  
Humidity  
0 to 95%  
Maximum Supply Voltage, Vcc  
3.5 V  
Non-condensing  
MIL-STD-810F  
Contact Critical  
Link for Details  
Storage Temperature Range  
Shock, Z-Axis  
-65oC to 80oC  
±10 g  
Shock, X/Y-Axis  
±10 g  
SO-DIMM-200 Interface Description  
The primary interface connector for the MityDSP-L138 is the SO-DIMM card edge  
interface which contains 4 types of signals:  
Power (PWR)  
Dedicated signals mapped to the OMAP-L138 device (D)  
Multi-function signals mapped to the OMAP-L138 device (M)  
Dedicated signals mapped to the Xilinx Spartan 6 device (F)  
Table 1 contains a summary of the MityDSP-L138 pin mapping.  
Table 1 SO-DIMM Pin-Out  
Pin Ball Type I/O  
Signal  
+3.3 V in  
+3.3 V in  
+3.3 V in  
GND  
Pin Ball Type  
I/O  
Signal  
1
3
5
7
-
-
-
-
-
PWR  
PWR  
PWR  
PWR  
PWR  
D
-
-
-
-
-
2
4
6
8
-
-
-
-
-
-
PWR  
PWR  
PWR  
PWR  
PWR  
D
-
-
-
-
-
+3.3 V in  
+3.3 V in  
+3.3 V in  
GND  
9
GND  
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
GND  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
K14  
J1  
I
RESET_IN#  
SATA_TX_P  
SATA_TX_N  
SATA_RX_P  
SATA_RX_N  
USB0_ID  
EXT_BOOT#  
GP0_7  
D
O
O
I
A4  
A3  
A2  
A1  
B4  
B1  
B2  
B3  
C2  
C3  
C4  
C5  
-
M
M
M
M
M
M
M
M
M
M
M
M
PWR  
PWR  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
-
J2  
D
GP0_10  
GP0_11  
GP0_15  
GP0_6  
GP0_14  
GP0_12  
GP0_5  
GP0_13  
GP0_1  
GP0_4  
L1  
L2  
P16  
P18  
P19  
N19  
M18  
M19  
K18  
-
D
D
D
D
D
D
D
D
I
I
I/O USB1_D_N  
I/O USB1_D_P  
O
I/O USB0_D_N  
I/O USB0_D_P  
O
-
USB0_VBUS  
D
D
USB0_DRVVBUS  
3V RTC Battery  
+3.3 V in  
GP0_3  
+3.3 V in  
+3.3 V in  
-
-
PWR  
PWR  
-
-
+3.3 V in  
-
-
5
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
Pin Ball Type I/O  
Signal  
Pin Ball Type  
I/O  
-
Signal  
41  
43  
45  
47  
-
PWR  
D
D
D
D
M
D
D
D
M
-
GND  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
-
D4  
E4  
F4  
PWR  
M
M
M
M
M
M
M
M
GND  
H17  
G17  
H16  
I/O SPI1_MISO  
I/O SPI1_MOSI  
I/O SPI1_ENA  
I/O SPI1_CLK  
I/O SPI1_SCS1  
I/O Reserved  
I/O I2C0_SCL  
I/O I2C0_SDA  
I/O UART2_TXD  
I2C1_SDA  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GP0_2  
GP0_0  
GP0_8  
GP0_9  
491 G19  
D5  
51  
53  
F18  
-
A12  
C11  
E12  
B11  
E11  
MMCSD0_DAT7  
MMCSD0_DAT6  
MMCSD0_DAT5  
MMCSD0_DAT4  
MMCSD0_DAT3  
552 G16  
572 G18  
59  
F16  
/
/
M
61  
F17  
M
I/O UART2_RXD  
I2C1_SCL  
62  
C10  
M
I/O  
MMCSD0_DAT2  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
-
PWR I/O GND  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
904  
92  
94  
96  
98  
100  
102  
104 K12  
106 K13  
108  
110  
112  
114 K15  
116 K16  
118  
120 K14  
122 H15  
124 H16  
126 H13  
128 H14  
130  
132  
134  
-
PWR  
M
M
M
M
M
M
M
M
M
M
PWR  
M
F
F
F
F
F
F
F
F
F
PWR  
F
F
F
F
F
F
F
F
F
F
PWR  
F
F
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
-
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
-
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
-
GND  
F19  
E18  
E16  
D17  
D19  
C17  
D16  
E17  
D18  
C19  
-
C18  
C16  
U17  
U18  
T17  
T18  
P17  
M
M
M
M
M
M
M
M
M
M
PWR  
M
M
F
F
F
F
F
F
F
F
I/O UART1_TXD  
A11  
B10  
A10  
E9  
D3  
E3  
E2  
E1  
F3  
C1  
MMCSD0_DAT1  
MMCSD0_DAT0  
MMCSD0_CMD  
MMCSD0_CLK  
MII_TXCLK  
MII_TXD3  
MII_TXD2  
MII_TXD1  
MII_TXD0  
MII_TXEN  
I/O UART1_RXD  
I/O MDIO_CLK  
I/O MDIO_DAT  
I/O MII_RXCLK  
I/O MII_RXDV  
I/O MII_RXD0  
I/O MII_RXD1  
I/O MII_RXD2  
I/O MII_RXD3  
-
GND  
-
D1  
GND  
MII_COL  
I/O MII_CRS  
I/O MII_RXER  
R16  
M14  
N14  
N15  
N16  
L12  
L13  
FPGA_SUSPEND  
B1 _48_P.M14  
B1_ 48_N.N14  
B1 _46_P.N15  
B1_ 46_N.N16  
B1 _44_P.L12  
B1_ 44_N.L13  
B1 _42_P.K12  
B1_ 42_N.K13  
GND  
B1 _40_P.L15  
B1_ 40_N.L16  
B1 _38_P.K15  
B1_ 38_N.K16  
B1 _36_P.J13  
B1_ 36_N.K14  
B1 _34_P.H15  
B1_ 34_N.H16  
B1 _32_P.H13  
B1_ 32_N.H14  
GND  
I/O B1 _47_P.U17  
I/O B1_ 47_N.U18  
I/O B1 _45_P.T17  
I/O B1_ 45_N.T18  
I/O B1_43_P.P17  
I/O B1_43_N.P18  
I/O B1_41_P.N17  
I/O B1_41_N.N18  
101 P18  
103 N17  
105 N18  
107  
-
PWR  
F
F
F
F
F
F
F
F
-
GND  
-
109 M16  
111 M18  
113 L17  
115 L18  
117 K17  
119 K18  
121  
123  
125 H17  
127 H18  
I/O B1_39_P.M16  
I/O B1_39_N.M18  
I/O B1_37_P.L17  
I/O B1_37_N.L18  
I/O B1_35_P.K17  
I/O B1_35_N.K18  
I/O B1_33_P.J16  
I/O B1_33_N.J18  
I/O B1_31_P.H17  
I/O B1_31_N.H18  
L15  
L16  
J13  
J16  
J18  
F
F
129  
-
PWR  
F
F
F
F
-
GND  
-
131 G16  
133 G18  
135 F17  
137 F18  
I/O B1_29_P.G16  
I/O B1_29_N.G18  
I/O B1_27_P.F17  
I/O B1_27_N.F18  
F15  
F16  
I/O  
I/O  
I/O  
I/O  
B1 _30_P.F15  
B1_ 30_N.F16  
B1 _28_P.H12  
B1_ 28_N.G13  
136 H12  
138 G13  
F
F
6
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
Pin Ball Type I/O  
Signal  
Pin Ball Type  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
-
Signal  
B1 _26_P.F14  
139 E16  
141 E18  
143 D17  
145 D18  
147 C17  
149 C18  
F
F
F
F
F
F
I/O B1_25_P.E16  
I/O B1_25_N.E18  
I/O B1_23_P.D17  
I/O B1_23_N.D18  
I/O B1_21_P.C17  
I/O B1_21_N.C18  
140  
F14  
F
142 G14  
F
B1_ 26_N.G14  
B0 _24_P.F13  
B0_ 24_N.E13  
B0 _22_P.D14  
B0_ 22_N.C14  
GND  
144  
146  
F13  
E13  
F
F
148 D14  
150 C14  
F
F
151  
-
PWR  
-
GND  
152  
-
PWR  
153 B16  
155 A16  
157 C15  
159 A15  
161 B14  
163 A14  
165 C13  
167 A13  
169 B12  
171 A12  
F
F
F
F
F
F
F
F
F
F
PWR  
F
F
F
F
F
F
F
F
F
F
PWR  
PWR  
PWR  
I/O B0_19_P.B16  
I/O B0_19_N.A16  
I/O B0_17_P.C15  
I/O B0_17_N.A15  
I/O B0_15_P.B14  
I/O B0_15_N.A14  
I/O B0_13_P.C13  
I/O B0_13_N.A13  
I/O B0_11_P.B12  
I/O B0_11_N.A12  
1543 F12  
1563 E12  
1583 D12  
1603 C12  
1623 F11  
1643 E11  
166 D11  
168 C11  
F
F
F
F
F
F
F
F
F
F
PWR  
F
F
F
F
F
F
F
F
F
F
PWR  
PWR  
PWR  
I/O3 B0 _20_P.F123  
I/O3 B0_ 20_N.E123  
I/O3 B0 _18_P.D123  
I/O3 B0_ 18_N.C123  
I/O3 B0 _16_P.F113  
I/O3 B0_ 16_N.E113  
I/O  
I/O  
B0 _14_P.D11  
B0_ 14_N.C11  
1703  
1723  
174  
176  
178  
180  
182  
184  
186  
188  
190  
192  
194  
196  
198  
200  
E7  
E8  
-
I/O3 B0 _12_P.E73  
I/O3 B0_ 12_N.E83  
173  
-
-
GND  
-
GND  
175 B11  
177 A11  
179 C10  
181 A10  
I/O B0_9_P.B11  
I/O B0_9_N.A11  
I/O B0_7_P.C10  
I/O B0_7_N.A10  
I/O B0_5_P.B9  
I/O B0_5_N.A9  
I/O B0_3_P.B8  
I/O B0_3_N.A8  
I/O B0_1_P.C7  
I/O B0_1_N.A7  
D9  
C9  
D8  
C8  
D6  
C6  
B6  
A
C5  
A5  
-
-
-
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
-
B0 _10_P.D9  
B0_ 10_N.C9  
B0 _8_P.D8  
B0_ 8_N.C8  
B0 _6_P.D6  
B0_ 6_N.C6  
B0 _4_P.B6  
B0_ 4_N.A6  
B0 _2_P.C5  
B0_ 2_N.A5  
GND  
183  
185  
187  
189  
191  
193  
195  
197  
199  
B9  
A9  
B8  
A8  
C7  
A7  
-
-
-
-
GND  
VCCO_1  
VCCO_1  
-
-
-
VCCO_0  
-
VCCO_0  
Note 1: Pin 49, SPI1_CLK, has a 100K Ohm pull-down resistor on the module  
Note 2: Pins 55 and 57 have 4.70K pull-up resistors on the module  
Note 3: The Xilinx 6SLX45 FPGA does not bond I/O Buffers to balls E7, E8, F11, E11,  
D12, C12, E12, and F12 of the package used for this module. For MityDSP-L138F  
configurations using this FPGA option, these edge connector signals should be treated as  
no-connects and will not function as FPGA I/O lines.  
Note 4: Pin 90, FPGA_SUSPEND, has a 4.7K Ohm pull-down resistor on the module  
The signal group description for the above pins is included in Table 2.  
7
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
Table 2 Signal Group Description  
Signal / Group  
3.3 V in  
EXT_BOOT#  
I/O  
N/A  
I
Description  
3.3 volt input power referenced to GND.  
Bootstrap configuration pin. Pull low to configure  
booting from external UART1.  
RESET_IN#  
SPI_XXXX  
I
Manual Reset. When pulled to GND for a minimum  
of 1 usec, resets the DSP processor.  
I/O  
The pins with an SPI_ prefix are direct connections  
to the OMAP-L138 pins supporting the SPI1  
interface. The SPI1_CLK, SPI1_ENA, SPI1_MISO,  
SPI1_MOSI pins must remain configured for the SPI  
function in order to support interfacing to the on-  
board SPI boot ROM. For details please refer to the  
OMAP-L138 processor specifications.  
MII_XXXX  
I/O  
The pins with an MII_ prefix are direct connections  
to the OMAP-L138 pins supporting the media  
independent interface (MII) function. The MII pins  
provide multiplex capability and may alternately be  
used as UART, GPIO, and SPI control pins. For  
details please refer to the OMAP-L138 processor  
specification.  
MDIO_XX  
GP0_X  
I/O  
IO  
The MDIO_CLK and MDIO_DAT signals are direct  
connects to the corresponding MDIO signals on the  
OMAP-L138 processor.  
configured for GPIO.  
These pins may be  
General Purpose / multiplexed pins. These pins are  
direct connects to the corresponding GP0[X] pins on  
the OMAP-L138 processor. The include support for  
the McASP, general purpose I/O, UART flow  
control, and McBSP 1. For details please refer to the  
OMAP-L138 processor specifications.  
SATA_TX_P/N  
SATA_RX P/N  
O
I
These pins are direct connects to the OMAP-L138  
SATA_TX differential Serial ATA controller pins.  
These pins are direct connects to the OMAP-L138  
SATA_RX differential Serial ATA controller pins.  
System Digital Ground.  
FPGA I/O pins. These pins are routed directly to  
FPGA pins ZZ. The “X” indicates which FPGA  
bank the pin is allocated. The bank is either 0 or 1.  
The FPGA fabric supports routing pins in  
differential pairs, the Y_P and Y_N portion of the  
name indicates the pair number and polarity. The  
pins have been routed in pairs with phase matched  
line lengths.  
GND  
BX_Y_P.ZZ,  
BX_Y_N.ZZ  
N/A  
IO  
VCCO_X  
I
FPGA Bank interface power input. These pins must  
8
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
Signal / Group  
I/O  
Description  
be tied to the desired voltage used for the FPGA  
Bank 0 or 1 interface pins. Please refer to the  
VCCO input pin specifications for the Xilinx  
Spartan 6 family of devices for further information.  
Typical values are 3.3V and 2.5 volts.  
USB0_XXXX,  
USB1_XXXX  
I/O  
The USBN_ prefixed pins are direct connects to the  
corresponding pins on the OMAP-L138 processor.  
For details please refer to the OMAP-L138 processor  
specifications.  
DEBUG INTERFACE  
Below is the pin-out for the Hirose 31 pin header (DF9-31P-1V(32)) that interfaces with  
an available adapter board, CL part number 80-000286, to debug the OMAP-L138 and  
FPGA.  
Debug Interface Connector Description (J2)  
Table 3 OMAP-L138 Hirose Connector  
Pin  
1
3
5
7
I/O  
Signal  
Pin  
2
4
6
8
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
I/O  
O
O
I
O
O
-
I
I
I
-
O
I
I
O
I
Signal  
OMAP EMU1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
OMAP EMU0  
OMAP TCK  
OMAP RTCK  
OMAP TDO  
OMAP VCC / 3.3V  
OMAP TDI  
OMAP TRST  
OMAP TMS  
GND  
FPGA VREF / VCCAUX  
FPGA TMS  
FPGA TCK  
FPGA TDO  
FPGA TDI  
9
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
9
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
ELECTRICAL CHARACTERISTICS  
Table 4: Electrical Characteristics  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Voltage supply, 3.3 volt input.  
3.2  
3.3  
TBS  
TBS  
300  
100  
3.4  
TBS  
TBS  
456  
-
Volts  
mA  
mA  
MHz  
MHz  
V33  
I33  
I33-max  
FCPU  
FEMIF  
Quiescent Current draw, 3.3 volt input  
Max current draw, positive 3.3 volt input.  
CPU internal clock Frequency (PLL output)  
EMIF bus frequency  
25  
-
Must be ½ CPU  
1.  
Power utilization of the MityDSP-L138F is heavily dependent on end-user application. Major factors  
include: ARM CPU PLL configuration, DSP Utilization FPGA utilization, and external DDR2 RAM  
utilization.  
ORDERING INFORMATION  
The following table lists the standard module configurations. For shipping status,  
availability, and lead time of these or other configurations please contact your Critical  
Link representative.  
Table 5: Standard Model Numbers  
ARM and  
DSP Speed  
456 MHz  
375 MHz  
456 MHz  
375 MHz  
456 MHz  
NOR  
Flash  
8MB  
8MB  
8MB  
8MB  
8MB  
Operating  
Temp  
Model  
FPGA  
NAND Flash  
RAM  
L138-FG-225-RC  
L138-DG-225-RI  
L138-FI-225-RC  
L138-DI-225-RI  
L138-FI-236-RL  
6SLX16  
6SLX16  
6SLX45  
6SLX45  
6SLX45  
256MB  
256MB  
256MB  
256MB  
512MB  
128MB  
128MB  
128MB  
128MB  
256MB  
0oC to 70o C  
-40oC to 85o C  
0oC to 70o C  
-40oC to 85o C  
-40oC to 70o C  
10  
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
MECHANICAL INTERFACE  
The mechanical outline of the MityDSP-L138F is illustrated in Figure 2, as shown below.  
Figure 2 MityDSP-L138F Mechanical Outline  
11  
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
 
Critical Link, LLC  
www.CriticalLink.com  
www.MityDSP.com  
MityDSP  
MityDSP-L138F Processor Card  
29-AUG-2013  
REVISION HISTORY  
Date  
7-NOV-2009  
10-NOV-2009  
15-JAN-2010  
16-MAR-2010  
6-APR-2010  
21-APR-2010  
26-JUL-2010  
11-FEB-2011  
Change Description  
Preliminary Draft, product overview  
Updates after initial review.  
Updates to features, applications and benefits  
Finalize connector pin-outs. Update mechanical outlines.  
Update product photo and speed grade.  
Update specifications and options.  
Update ordering information, images and mechanical drawing.  
Correct edge connector Table 1. Update speed grade to max  
456 MHz. Updated DDR rate to support 150 MHz clocking.  
Update model p/n table.  
02-JUN-2011  
12-JUL-2011  
Update edge connector Table 1 to indicate unavailable FPGA  
pins for 6SLX45 options.  
Update NAND to indicate 8 bit data width. Update block  
diagram accordingly.  
28-NOV-2011  
13-AUG-2012  
11-DEC-2012  
Update list of orderable part numbers.  
Fix typo in signal names for pins 79, 81, 83, and 84  
Update Debug Header information, added MIL-STD-810F and  
Up To notation for RAM and NAND  
29-AUG-2013  
Added OMAP-L138 processor pins and FPGA pins to Table 1  
with notes about on module resistors for specific pins as well as  
the OSCIN frequency.  
12  
Copyright © 2013, Critical Link LLC  
Specifications Subject to Change  
Mouser Electronics  
Authorized Distributor  
Click to View Pricing, Inventory, Delivery & Lifecycle Information:  
Critical Link:  
L138-DG-225-RI L138-DI-225-RI L138-FG-225-RC L138-FI-225-RC L138-FI-236-RL  

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