L29S800F_技术文档

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Revision history

Rev. No. Approved date

History

Initial issue

Remark (purpose)

Preliminary

A

July 17 2002

1

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

!

FEATURES

• Single 3.0 V read, program, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

2

Uses same software commands as E PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP(I)

• Minimum 100,000 program/erase cycles

• High performance

70 ns maximum access time

• Sector erase architecture

One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode

One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector

B = Bottom sector

TM

• Embedded Erase Algorithms

Automatically pre-programs and erases the chip or any sector

TM

• Embedded Program Algorithms

Automatically writes and verifies data at specified address

•Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY )

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode

• Low V write inhibit ＜ 2.5 V

CC

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Sector Protection set function by Extended sector Protect command

• Temporary sector unprotection

Temporary sector unprotection via the RESET pin

*: Embedded Erase^TMand Embedded Program ^TMare trademarks of Advanced Micro Devices, Inc.

2

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ GENERAL DESCRIPTION

The L29S800F/-B are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K

words of 16 bits each. The L29S800F/-B are offered in a 48-pin TSOP(I) package, These devices are

designed to be programmed in-system with the standard system 3.0 V V supply. 12.0 V V and 5.0

CC

PP

V V^CCare not required for write or erase operations. The devices can also be reprogrammed in standard

EPROM programmers.

The standard L29S800F/-B offer access times 70 ns and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip

enable ( CE ), write enable ( WE ), and output enable (

) controls.

OE

2

The L29S800F/-B are pin and command set compatible with JEDEC standard E PROMs. Commands

are written to the command register using standard microprocessor write timings. Register contents

serve as input to an internal state-machine which controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed for the programming and erase operations.

Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The L29S800F/-B are programmed by executing the program command sequence. This will invoke the

Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse

widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about

0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the

Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it

is not already programmed before executing the erase operation. During erase, the devices

automatically time the erase pulse widths and verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased

and reprogrammed without affecting other sectors. The L29S800F/-B are erased when shipped from

the factory.

The devices feature single 3.0 V power supply operation for both read and write functions. Internally

generated and regulated voltages are provided for the program and erase operations. A low V^CC

detector automatically inhibits write operations on the loss of power. The end of program or erase is

detected by Data Polling of DQ⁷, by the Toggle Bit feature on DQ⁶, or the RY/ BY output pin. Once the

end of a program or erase cycle has been completed, the devices internally reset to the read mode.

2

LST’s Flash technology combines years of EPROM and E PROM experience to produce the highest

levels of quality, reliability, and cost effectiveness. The L29S800F/-B memories electrically erase the

entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words

are programmed one byte/word at a time using the EPROM programming mechanism of hot electron

injection.

3

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

• One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes

• Individual-sector, multiple-sector, or bulk-erase capability

• Individual or multiple-sector protection is user definable.

(x8)

(x16)

(x8)

(x16)

16K byte

8K byte

FFFFFH

FBFFFH

F9FFFH

F7FFFH

EFFFFH

DFFFFH

CFFFFH

BFFFFH

AFFFFH

9FFFFH

8FFFFH

7FFFFH

6FFFFH

5FFFFH

4FFFFH

3FFFFH

2FFFFH

1FFFFH

0FFFFH

00000H

7FFFFH

7DFFFH

7CFFFH

7BFFFH

77FFFH

6FFFFH

67FFFH

5FFFFH

57FFFH

4FFFFH

47FFFH

3FFFFH

37FFFH

2FFFFH

27FFFH

1FFFFH

17FFFH

0FFFFH

07FFFH

00000H

64K byte

32K byte

8K byte

FFFFFH

EFFFFH

DFFFFH

CFFFFH

BFFFFH

AFFFFH

9FFFFH

8FFFFH

7FFFFH

6FFFFH

5FFFFH

4FFFFH

3FFFFH

2FFFFH

1FFFFH

0FFFFH

07FFFH

05FFFH

03FFFH

00000H

7FFFFH

77FFFH

6FFFFH

67FFFH

5FFFFH

57FFFH

4FFFFH

47FFFH

3FFFFH

37FFFH

2FFFFH

27FFFH

1FFFFH

17FFFH

0FFFFH

07FFFH

03FFFH

02FFFH

01FFFH

00000H

8K byte

32K byte

64K byte

8K byte

16K byte

L29S800F Sector Architecture

L29S800F-B Sector Architecture

4

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ BLOCK DIAGRAM

5

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

!

PIN ASSIGNMENTS

Table 1 L29S800F/-B Pin Configuration

Function

Address Inputs

A , A to A

-1

0

18

Data Inputs/Outputs

Chip Enable

DQ to DQ

0

15

CE

OE

Output Enable

Write Enable

WE

Ready/Busy Output

RY/ BY

Hardware Reset Pin/Temporary Sector

Unprotection

RESET

Selects 8-bit or 16-bit mode

No Internal Connection

Device Ground

BYTE

N.C.

V

SS

Device Power Supply

V

CC

6

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ LOGIC SYMBOL

Table 2 L29S800F/-B User Bus Operations (BYTE = V )

IH

Operation

Auto-Select Manufacturer Code (1)

Auto-Select Device Code (1)

Read (3)

A

DQ to DQ

0 15

RESET

CE OE WE

0

1

6

9

L

H

L

X

L

Code

H

X

H

L

V_ID

A₉

X

H

V_ID

L

H

Code

D_OUT

HIGH-Z

D_IN

L

A₀A₁A₆

Standby

X

Output Disable

X

H

V_ID

L

Write (Program/Erase)

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

Temporary Sector Unprotection

Reset (Hardware)/Standby

A₀A₁A₆A₉

L

X

H

X

V_ID

X

Code

X

H

X

HIGH-Z

7

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Table 3 L29S800F/-B User Bus Operations (BYTE = V )

IL

DQ¹⁵/

A^-1

Operation

A

0

A

1

A

6

A

9

DQ to DQ

RESET

CE OE WE

0

7

Auto-Select Manufacturer Code (1)

Auto-Select Device Code (1)

Read (3)

L

H

L

X

L

Code

D_OUT

HIGH-Z

D_IN

H

X

H

L

V_ID

A₉

X

H

V_ID

L

H

L

A₀A₁A₆

A_-1

X

Standby

X

Output Disable

X

H

V_ID

L

Write (Program/Erase)

Enable Sector Protection (2), (4)

Verify Sector Protection (2), (4)

Temporary Sector Unprotection

Reset (Hardware)/Standby

A_-1

L

A₀A₁A₆A₉

L

X

H

X

V_ID

X

L

Code

X

H

X

HIGH-Z

Legend: L = V , H = V , X = V or V ,

= Pulse input. See DC Characteristics for voltage levels.

IL

IH

IL

IH

Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence.

See Table 7.

2. Refer to the section on Sector Protection.

3. WE can be V if OE is V ,

at V initiates the write operations.

OE

IL

IH

4. V = 3.3 V ± 10%

CC

5. It is also used for the extended sector protection.

8

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ FUNCTIONAL DESCRIPTION

Read Mode

The L29S800F/-B have two control functions which must be satisfied in order to obtain data at the

outputs. CE is the power control and should be used for a device selection. OE is the output control

and should be used to gate data to the output pins if a device is selected.

Address access time (t_ACC) is equal to the delay from stable addresses to valid output data. The chip

enable access time (t_CE) is the delay from stable addresses and stable CE to valid data at the output

pins. The output enable access time is the delay from the falling edge of OE to valid data at the output

pins. (Assuming the addresses have been stable for at least t_ACC-t_OEtime.) When reading out a data

without changing addresses after power-up, it is necessary to input hardware reset or change

CE

from “H” or “L”

Standby Mode

There are two ways to implement the standby mode on the L29S800F/-B devices, one using both the

and RESET pins; the other via the pin only.

CE

When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at

_CC± 0.3 V. Under this condition the current consumed is less than 5 µA. The device can be read with

RESET

V

standard access time (t_CE) from either of these standby modes. During Embedded Algorithm operation,

V_CCactive current (I_CC2) is required even = “H”.

CE

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at V_SS

0.3 V ( = “H” or “L”). Under this condition the current is consumed is less than 5mA. Once the

±

CE

RESET pin is taken high, the device requires t

of wake up time before outputs are valid for read

RH

access.

In the standby mode the outputs are in the high impedance state, independent of the OE input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of

L29S800F/-B data. This mode can be used effectively with an application requested low power

consumption such as handy terminals.

To activate this mode, L29S800F/-B automatically switch themselves to low power mode when

L29S800F/-B addresses remain stably during access fine of 150 ns. It is not necessary to control CE ,

WE , and OE on the mode. Under the mode, the current consumed is typically 1µA (CMOS Level).

Since the data are latched during this mode, the data are read-out continuously. If the addresses are

changed, the mode is canceled automatically and L29S800F/-B read-out the data for changed

addresses.

Output Disable

With the

input at a logic high level (V ), output from the devices are disabled. This will cause the

IH

OE

output pins to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the devices and will identify its

manufacturer and type. This mode is intended for use by programming equipment for the purpose of

automatically matching the devices to be programmed with its corresponding programming algorithm.

This mode is functional over the entire temperature range of the devices.

To activate this mode, the programming equipment must force V_ID(11.5 V to 12.5 V) on address pin A .

9

Two identifier bytes may then be sequenced from the devices outputs by toggling address A from V

0

IL

9

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

to V . All addresses are DON’T CARES except A , A , A , and A_-1. (See Table 4.1.)

IH

0

1

6

The manufacturer and device codes may also be read via the command register, for instances when

theL29S800F/-B are erased or programmed in a system without access to high voltage on the A pin.

9

The command sequence is illustrated in Table 7. (Refer to Autoselect Command section.)

Byte 0 (A = V ) represents the manufacturer’s code (LST = 04H) and (A = V ) represents the

0

IL

0

IH

device identifier code (L29S800F = DAH and 29S800F-B = 5BH for x8 mode; L29S800F = 22DAH and

29S800F-B = 225BH for x16 mode). These two bytes/words are given in the tables 4.1 and 4.2. All

identifiers for manufactures and device will exhibit odd parity with DQ defined as the parity bit. In

7

order to read the proper device codes when executing the autoselect, A must be V . (See Tables 4.1

1

IL

and 4.2.)

Table 4 .1 L29S800F/-B Sector Protection Verify Autoselect Codes

*1

Type

Manufacture’s Code

L29S800F

Code (HEX)

A

to A

A

-1

12

18

6

1

0

X

04H

V

IL

V

IL

Byte

Word

Byte

DAH

22DAH

5BH

V

X

IL

X

V

IH

Device Code

V

X

IL

29S800F-B

X

V

IL

IH

Word

5BH

Sector

Addresses

*2

Sector Protection

V

IH

V

IL

V

01H

IL

*1: A^-1is for Byte mode.

*2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

Table 4 .2 Expanded Autoselect Code Table

Type

Code DQ₁₅DQ₁₄DQ₁₃DQ₁₂DQ₁₁DQ₁₀DQ₉DQ₈DQ₇DQ₆DQ₅DQ₄DQ₃DQ₂DQ₁DQ₀

Manufacture’s Code

04H A_-1/0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

(B) DAH A_-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

L29S800F

(W) 22DAH

0

1

0

1

0

Device

Code

(B) 5BH A_-1HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

29S800F-B

(W) 225BH

0

1

0

1

0

Sector Protection

01H A_-1/0

(B): Byte mode

(W): Word mode

10

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Write

Device erasure and programming are accomplished via the command register. The contents of the

register serve as inputs to the internal state machine. The state machine outputs dictate the function of

the device.

The command register itself does not occupy any addressable memory location. The register is a latch

used to store the commands, along with the address and data information needed to execute the

command. The command register is written by bringing

V . Addresses are latched on the falling edge of

to V , while

is at V and

is at

WE

CE

OE

IL

or

, whichever happens later; while data is

WE

CE

IH

latched on the rising edge of

or

, whichever happens first. Standard microprocessor write

WE

CE

timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing

parameters.

Sector Protection

The L29S800F/-B feature hardware sector protection. This feature will disable both program and erase

operations in any number of sectors (0 through 18). The sector protection feature is enabled using

programming equipment at the user’s site. The devices are shipped with all sectors unprotected.

Alternatively, LST may program and protect sectors in the factory prior to shipping the device.

To activate this mode, the programming equipment must force V on address pin A9 and control pin

ID

, (suggest V = 11.5 V),

= V , and A = V . The sector addresses (A , A , A , A , A ,

OE

CE

ID

IL 6 IL 18 17 16 15 14

A , and A ) should be set to the sector to be protected. Tables 5 and 6 define the sector address for

13

12

each of the nineteen (19) individual sectors. Programming of the protection circuitry begins on the

falling edge of the pulse and is terminated with the rising edge of the same. Sector addresses

WE

must be held constant during the

and algorithm.

pulse. See Figures 16 and 24 for sector protection waveforms

WE

To verify programming of the protection circuitry, the programming equipment must force V on

ID

address pin A with

and

12

at V and

at V . Scanning the sector addresses (A , A ,

CE

OE

WE

9

IL

IH 18 17

A , A , A , A , and A ) while (A , A , A ) = (0, 1, 0) will produce a logical “1” code at device output

16

15

14

13

6

1

0

DQ for a protected sector. Otherwise the devices will read 00H for unprotected sector. In this mode,

0

the lower order addresses, except for A , A , and A are DON’T CARES. Address locations with A =

0

1

6

1

V are reserved for Autoselect manufacturer and device codes.

IL

A

-1

requires to apply to V on byte mode.

IL

It is also possible to determine if a sector is protected in the system by writing an Autoselect command.

Performing a read operation at the address location XX02H, where the higher order addresses (A ,

18

A , A , A , A , A , and A ) are the desired sector address will produce a logical “1” at DQ for a

17

16

15

14

13

12

0

protected sector. See Tables 4.1 and 4.2 for Autoselect codes.

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the L29S800F/-B devices

in order to change data. The Sector Unprotection mode is activated by setting the pin to high

RESET

voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting

11

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

the sector addresses. Once the 12 V is taken away from the

sectors will be protected again. See Figures 17 and 25.

pin, all the previously protected

RESET

Hardware Reset

The L29S800F/-B devices may be reset by driving the RESET pin to V . The RESET pin has a

IL

pulse requirement and has to be kept low (V ) for at least 500 ns in order to properly reset the internal

IL

state machine. Any operation in the process of being executed will be terminated and the internal state

machine will be reset to the read mode 20 µs after the RESET pin is driven low. Furthermore, once

the RESET pin goes high, the devices require an additional t before it will allow read access. When

RH

the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the

data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the

data at that particular location will be corrupted. Please note that the RY/ BY output signal should be

ignored during the RESET pulse. See Figure 12 for the timing diagram. Refer to Temporary Sector

Unprotection for additional functionality.

If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing

sector(s) cannot be used.

12

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Table 5 Sector Address Tables (L29S800F)

Sector

Address

Address Range (×8) Address Range (×16)

A

18

A

17

A

16

A

15

A

14

A

13

A

12

00000H to 0FFFFH

10000H to 1FFFFH

20000H to 2FFFFH

30000H to 3FFFFH

40000H to 4FFFFH

50000H to 5FFFFH

60000H to 6FFFFH

70000H to 7FFFFH

80000H to 8FFFFH

90000H to 9FFFFH

A0000H to AFFFFH

B0000H to BFFFFH

C0000H to CFFFFH

D0000H to DFFFFH

E0000H to EFFFFH

F0000H to F7FFFH

F8000H to F9FFFH

FA000H to FBFFFH

FC000H to FFFFFH

00000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7BFFFH

7C000H to 7CFFFH

7D000H to 7DFFFH

7E000H to 7FFFFH

SA0

0

X

SA1

SA2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

1

0

1

X

13

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Table 6 Sector Address Tables (29S800F-B)

Sector

Address

Address Range (×8) Address Range (×16)

A

18

A

17

A

16

A

15

A

14

A

13

A

12

00000H to 03FFFH

04000H to 05FFFH

06000H to 07FFFH

08000H to 0FFFFH

10000H to 1FFFFH

20000H to 2FFFFH

30000H to 3FFFFH

40000H to 4FFFFH

50000H to 5FFFFH

60000H to 6FFFFH

70000H to 7FFFFH

80000H to 8FFFFH

90000H to 9FFFFH

A0000H to AFFFFH

B0000H to BFFFFH

C0000H to CFFFFH

D0000H to DFFFFH

E0000H to EFFFFH

F0000H to FFFFFH

00000H to 01FFFH

02000H to 02FFFH

03000H to 03FFFH

04000H to 07FFFH

08000H to 0FFFFH

10000H to 17FFFH

18000H to 1FFFFH

20000H to 27FFFH

28000H to 2FFFFH

30000H to 37FFFH

38000H to 3FFFFH

40000H to 47FFFH

48000H to 4FFFFH

50000H to 57FFFH

58000H to 5FFFFH

60000H to 67FFFH

68000H to 6FFFFH

70000H to 77FFFH

78000H to 7FFFFH

SA0

0

X

SA1

SA2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA3

1

X

SA4

X

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

14

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Table 7 L29S800F/-B Standard Command Definitions

Fourth Bus

First Bus Second Bus Third Bus

Read/Write

Bus

Write

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Command

Sequence

Write Cycle Write Cycle Write Cycle

Cycle

Cycles

Req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

1

3

4

6

XXXH F0H

—

RA

—

RD

—

Read/Reset

Autoselect

Program

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555H

AAH

2AAH

555H

2AAH

555H

2AAH

555H

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

555H

AAAH

55H

F0H

90H

A0H

80H

AAAH

555H

AAAH

AAH

—

555H

AAAH

PA

PD

AAH

—

555H

AAAH

555H

AAAH

2AAH

555H

2AAH

555H

AAAH

555H

AAAH

AAH

55H

10H

AAH

Chip Erase

Word

Byte

555H

AAAH

Sector

Erase

55H SA 30H

AAH

Sector Erase Suspend Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0H)

Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30H)

Sector Erase Resume

Notes: 1. Address bits A¹¹to A = X = “H” or “L” for all address commands except or Program Address (PA)

18

and sector Address (SA)

2. Bus operations are defined in Tables 2 and 3.

3. RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the WE pulse.

SA = Address of the sector to be erased. The combination of A¹⁸, A¹⁷, A¹⁶, A¹⁵, A¹⁴, A¹³, and A¹²

will uniquely select any sector.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of WE .

5. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A⁰to A¹⁰

Byte Mode: AAAH or 555H to addresses A^–1and A⁰to A¹⁰

6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

15

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Table 8 L29S800F/-B Extended Command Definitions

Bus

First Bus

Second Bus

Third Bus

Fifth Bus

Command

Write

Write Cycle

Sequence

Cycles

Req’d

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Word

Byte

555H

AAAH

XXXH

2AAH

555H

Set to

3

2

4

AAH

55H

20H

—

Fast Mode

AAAH

Word

Byte

Fast

Program

A0H

90H

60H

PA

PD

F0H*³

60H

—

*1

Word

Byte

XXXH

Reset from

Fast Mode

*1

Extended

Sector

Protect

Word

Byte

XXXH

SPA

40H

SPA

SD

*2

SPA : Sector address to be protected. Set sector address (SA) and (A , A , A ) = (0, 1, 0).

6

1

0

SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at

unprotected sector addresses.

*1:This command is valid while Fast Mode.

RESET

*2:This command is valid while

=V .

ID

*3:This data "00H" is also acceptable.

Command Definitions

Device operations are selected by writing specific address and data sequences into the command

register. Writing incorrect address and data values or writing them in the improper sequence will reset

the devices to the read mode. Table 7 defines the valid register command sequences. Note that the

Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase

operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting

the device to the read mode. Please note that commands are always written at DQ to DQ and DQ

0

7

8

to DQ bits are ignored.

15

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ = 1) to read/reset mode, the

5

read/reset operation is initiated by writing the Read/Reset command sequence into the command

register. Microprocessor read cycles retrieve array data from the memory. The devices remain

enabled for reads until the command register contents are altered.

The devices will automatically power-up in the read/reset state. In this case, a command sequence is

not required to read data. Standard microprocessor read cycles will retrieve array data. This default

value ensures that no spurious alteration of the memory content occurs during the power transition.

Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

16

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As

such, manufacture and device codes must be accessible while the devices reside in the target system.

PROM programmers typically access the signature codes by raising A to a high voltage. However,

9

multiplexing high voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the Autoselect command sequence into the

command register. Following the command write, a read cycle from address XX00H retrieves the

manufacture code of 04H. A read cycle from address XX01H for x16(XX02H for x8) returns the device

code (L29S800F = DAH and 29S800F-B = 5BH for x8 mode; L29S800F = 22DAH and 29S800F-B =

225BH for x16 mode). (See Tables 4.1 and 4.2.) All manufacturer and device codes will exhibit odd

parity with DQ defined as the parity bit. Sector state (protection or unprotection) will be informed by

7

address XX02H for x16 (XX04H for x8). Scanning the sector addresses (A , A , A , A , A , A ,

18

17

16

15

14

13

and A ) while (A , A , A ) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected

12

6

1

0

sector. The programming verification should be perform margin mode on the protected sector. (See

Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the

register, and also to write the Autoselect command during the operation, execute it after writing

Read/Reset command sequence.

Byte/Word Programming

The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus

cycle operation. There are two “unlock” write cycles. These are followed by the program set-up

command and data write cycles. Addresses are latched on the falling edge of CE or WE , whichever

happens later and the data is latched on the rising edge of CE or WE , whichever happens first. The

rising edge of CE or WE (whichever happens first) begins programming. Upon executing the

Embedded Program Algorithm command sequence, the system is not required to provide further

controls or timings. The device will automatically provide adequate internally generated program

pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ is equivalent to data written

7

to this bit at which time the devices return to the read mode and addresses are no longer latched. (See

Table 9, Hardware Sequence Flags.) Therefore, the devices require that a valid address to the devices

be supplied by the system at this particular instance of time. Hence, Data Polling must be performed

at the memory location which is being programmed.

Any commands written to the chip during this period will be ignored. If hardware reset occurs during

the programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot

be programmed back to a “1”. Attempting to do so may either hang up the device or result in an

apparent success according to the data polling algorithm but a read from read/reset mode will show

that the data is still “0”. Only erase operations can convert “0”s to “1”s.

TM

Figure 20 illustrates the Embedded Program

operations.

Algorithm using typical command strings and bus

17

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by

writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase

command.

Chip erase does not require the user to program the device prior to erase. Upon executing the

Embedded Erase Algorithm command sequence the devices will automatically program and verify the

entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is

not required to provide any controls or timings during these operations.

The automatic erase begins on the rising edge of the last WE pulse in the command sequence and

terminates when the data on DQ is “1” (See Write Operation Status section.) at which time the device

7

returns to read the mode.

Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming)

TM

Figure 21 illustrates the Embedded Erase

operations.

Algorithm using typical command strings and bus

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by

writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase

command. The sector address (any address location within the desired sector) is latched on the falling

edge of WE , while the command (Data=30H) is latched on the rising edge of WE . After time-out of

50 µs from the rising edge of the last sector erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 7. This

sequence is followed with writes of the Sector Erase command to addresses in other sectors desired

to be concurrently erased. The time between writes must be less than 50 µs otherwise that command

will not be accepted and erasure will start. It is recommended that processor interrupts be disabled

during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector

Erase command is written. A time-out of 50 ms from the rising edge of the last WE will initiate the

execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 µs

time-out window the timer is reset. (Monitor DQ to determine if the sector erase timer window is still

3

open, see section DQ , Sector Erase Timer.) Any command other than Sector Erase or Erase

3

Suspend during this time-out period will reset the devices to the read mode, ignoring the previous

command string. Resetting the devices once execution has begun will corrupt the data in the sector. In

that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation

Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any

sequence and with any number of sectors (0 to 18).

Sector erase does not require the user to program the devices prior to erase. The devices

automatically program all memory locations in the sector(s) to be erased prior to electrical erase

(Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not

affected. The system is not required to provide any controls or timings during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for

the last sector erase command pulse and terminates when the data on DQ is “1” (See Write

7

Operation Status section.) at which time the devices return to the read mode. Data polling must be

performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector

Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase

18

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

TM

Figure 21 illustrates the Embedded Erase

operations.

Algorithm using typical command strings and bus

Erase Suspend

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform

data reads from or programs to a sector not being erased. This command is applicable ONLY during

the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend

command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm.

Writing the Erase Suspend command during the Sector Erase time-out results in immediate

termination of the time-out period and suspension of the erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES

when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a

maximum of 20µs to suspend the erase operation. When the devices have entered the erase-

suspended mode, the RY/ BY output pin and the DQ bit will be at logic “1”, and DQ will stop

7

6

toggling. The user must use the address of the erasing sector for reading DQ and DQ to determine if

6

7

the erase operation has been suspended. Further writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the devices default to the erase-suspend-read mode.

Reading data in this mode is the same as reading from the standard read mode except that the data

must be read from sectors that have not been erase-suspended. Successively reading from the

erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ to toggle.

2

(See the section on DQ .)

2

After entering the erase-suspend-read mode, the user can program the device by writing the

appropriate command sequence for Program. This program mode is known as the

erase-suspend-program mode. Again, programming in this mode is the same as programming in the

regular Program mode except that the data must be programmed to sectors that are not

erase-suspended. Successively reading from the erase-suspended sector while the devices are in the

erase-suspend-program mode will cause DQ to toggle. The end of the erase-suspended Program

2

operation is detected by the RY/BY output pin, Data polling of DQ , or by the Toggle Bit I (DQ )

7

6

which is the same as the regular Program operation. Note that DQ must be read from the Program

7

address while DQ can be read from any address.

6

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further

writes of the Resume command at this point will be ignored. Another Erase Suspend command can be

written after the chip has resumed erasing.

19

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Extended Command

(1) Fast Mode

L29S800F/-B has Fast Mode function. This mode dispenses with the initial two unclock cycles

required in the standard program command sequence by writing Fast Mode command into the

command register. In this mode, the required bus cycle for programming is two cycles instead of

four bus cycles in standard program command. (Do not write erase command in this mode.) The

read operation is also executed after exiting this mode. To exit this mode, it is necessary to write

Fast Mode Reset command into the command register. (Refer to the Figure 27 Extended

algorithm.) The V active current is required even CE = V during Fast Mode.

CC

IH

(2) Fast Programming

During Fast Mode, the programming can be executed with two bus cycles operation. The

Embedded Program Algorithm is executed by writing program set-up command (A0H) and data

write cycles (PA/PD). (Refer to the Figure 27 Extended algorithm.)

(3) Extended Sector Protection

In addition to normal sector protection, the L29S800F/-B has Extended Sector Protection as

extended function. This function enable to protect sector by forcing V on RESET pin and write a

ID

command sequence. Unlike conventional procedure, it is not necessary to force V and control

ID

timing for control pins. The only RESET pin requires V for sector protection in this mode. The

ID

extended sector protect requires V on RESET pin. With this condition, the operation is initiated

ID

by writing the set-up command (60H) into the command register. Then, the sector addresses pins

(A , A , A , A , A , A and A ) and (A , A , A ) = (0, 1, 0) should be set to the sector to be

18

17

16

15

14

13

12

6

1

0

protected (recommend to set V for the other addresses pins), and write extended sector protect

IL

command (60H). A sector is typically protected in 150 ms. To verify programming of the protection

circuitry, the sector addresses pins (A , A , A , A , A , A and A ) and (A , A , A ) = (0, 1, 0)

18

17

16

15

14

13

12

6

1

0

should be set and write a command (40H). Following the command write, a logical “1” at device

output DQ will produce for protected sector in the read operation. If the output data is logical “0”,

0

please repeat to write extended sector protect command (60H) again. To terminate the operation, it

is necessary to set RESET pin to V .

IH

20

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Write Operation Status

Table 9 Hardware Sequence Flags

Status

Embedded Program Algorithm

Embedded Erase Algorithm

DQ

DQ DQ

DQ

2

7

6

5

3

Toggle

0

1

DQ7

Toggle

0

Erase Suspend Read

1

0

In Progress

(Erase Suspended Sector)

Erase Suspend Read

Erase

Suspended

Mode

Data

DQ7

Data Data Data Data

(Non-Erase Suspended Sector)

Erase Suspend Program

(Non-Erase Suspended Sector)

1

Toggle

0

(Note 1)

(Note 2)

Toggle

Embedded Program Algorithm

1

0

1

DQ7

N/A

Embedded Erase Algorithm

Erase

0

Toggle

Exceeded

Time Limits

Erase Suspend Program

Suspended

Mode

Toggle

1

0

N/A

DQ7

(Non-Erase Suspended Sector)

Notes: 1. Performing successive read operations from any address will cause DQ to toggle.

6

2. Reading the byte address being programmed while in the erase-suspend program mode will

indicate logic “1” at the DQ bit. However, successive reads from the erase-suspended sector

2

will cause DQ to toggle.

2

3. DQ and DQ are reserve pins for future use.

0

1

4. DQ is LST internal use only.

4

21

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

DQ₇

Data

Polling

The L29S800F/-B devices feature

Data

Polling as a method to indicate to the host that the Embedded

Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read

the devices will produce the complement of the data last written to DQ . Upon completion of the

7

Embedded Program Algorithm, an attempt to read the device will produce the true data last written to

DQ . During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ

7

output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a

Data

“1” at the DQ output. The flowchart for

Polling (DQ ) is shown in Figure 22.

7

Data

For chip erase and sector erase, the

in the six write pulse sequence.

Polling is valid after the rising edge of the sixth

pulse

WE

Polling must be performed at sector address within any of the

sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the

Embedded Algorithm operation is close to being completed, the L29S800F/-B data pins (DQ ) may

Data

7

change asynchronously while the output enable (

) is asserted low. This means that the devices are

OE

driving status information on DQ at one instant of time and then that byte’s valid data at the next instant

7

of time. Depending on when the system samples the DQ output, it may read the status or valid data.

7

Even if the device has completed the Embedded Algorithm operation and DQ has a valid data, the data

7

outputs on DQ to DQ may be still invalid. The valid data on DQ to DQ will be read on the successive

0

6

0

7

read attempts.

Data

The

Polling feature is only active during the Embedded Programming Algorithm, Embedded

Erase Algorithm or sector erase time-out. (See Table 9.)

Data

See Figure 9 for the

Polling timing specifications and diagrams.

DQ₆

Toggle Bit I

The L29S800F/-B also feature the “Toggle Bit I” as a method to indicate to the host system that the

Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (

toggling)

OE

data from the devices will result in DQ toggling between one and zero. Once the Embedded Program or

6

Erase Algorithm cycle is completed, DQ will stop toggling and valid data will be read on the next

6

successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth

pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid

WE

after the rising edge of the sixth

pulse in the six write pulse sequence. The Toggle Bit I is active

WE

during the sector time out.

In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 ms and

then stop toggling without the data having changed. In erase, the devices will erase all the selected

sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle

the toggle bit for about 100 µs and then drop back into read mode, having changed none of the data.

Either CE or

toggling will cause the DQ to toggle. In addition, an Erase Suspend/Resume

OE

6

command will cause the DQ to toggle.

6

See Figure 10 for the Toggle Bit I timing specifications and diagrams.

22

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

DQ₅

Exceeded Timing Limits

DQ will indicate if the program or erase time has exceeded the specified limits (internal pulse count).

5

Under these conditions DQ will produce a “1”. This is a failure condition which indicates that the

5

program or erase cycle was not successfully completed. Data Polling is the only operating function of

the devices under this condition. The CE circuit will partially power down the device under these

conditions (to approximately 2 mA). The

described in Tables 2 and 3.

and WE pins will control the output disable functions as

OE

The DQ failure condition may also appear if a user tries to program a non blank location without erasing.

5

In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the

system never reads a valid data on DQ bit and DQ never stops toggling. Once the devices have

7

6

exceeded timing limits, the DQ bit will indicate a “1.” Please note that this is not a device failure

5

condition since the devices were incorrectly used. If this occurs, reset the device with command

sequence.

DQ₃

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin.

DQ will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial

3

sector erase command sequence.

If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command,

DQ may be used to determine if the sector erase timer window is still open. If DQ is high (“1”) the

3

internally controlled erase cycle has begun; attempts to write subsequent commands to the device will

be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ is

3

low (“0”), the device will accept additional sector erase commands. To insure the command has been

accepted, the system software should check the status of DQ prior to and following each subsequent

3

Sector Erase command. If DQ were high on the second status check, the command may not have

3

been accepted.

See Table 9: Hardware Sequence Flags.

DQ₂

Toggle Bit II

This toggle bit II, along with DQ , can be used to determine whether the devices are in the Embedded

6

Erase Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ to toggle during the Embedded Erase

2

Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the

erase-suspended sector will cause DQ

to toggle. When the devices are in the

2

erase-suspended-program mode, successive reads from the byte address of the non-erase suspended

sector will indicate a logic “1” at the DQ bit.

2

DQ is different from DQ in that DQ toggles only when the standard program or Erase, or Erase

6

2

6

Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ ,

7

is summarized as follows:

For example, DQ and DQ6 can be used together to determine if the erase-suspend-read mode is in

2

progress. (DQ toggles while DQ does not.) See also Table 9 and Figure 18.

2

6

Furthermore, DQ can also be used to determine which sector is being erased. When the device is in

2

the erase mode, DQ toggles if this bit is read from an erasing sector.

2

23

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Mode

Program

DQ

2

7

6

Toggle

1

DQ7

Erase

0

Toggle

Erase-Suspend Read

(Erase-Suspended Sector)

(Note 1)

1

Toggle

Erase-Suspend Program

Toggle (Note 1)

1 (Note 2)

DQ7

Notes: 1. Performing successive read operations from any address will cause DQ to toggle.

6

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate

logic “1” at the DQ bit. However, successive reads from the erase-suspended sector will cause DQ

2

to toggle.

RY/BY

Ready/Busy

The L29S800F/-B provide a RY/ BY open-drain output pin as a way to indicate to the host system that the

Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are

busy with either a program or erase operation. If the output is high, the devices are ready to accept any

read/write or erase operation. When the RY/ BY pin is low, the devices will not accept any additional

program or erase commands. If the L29S800F/-B are placed in an Erase Suspend mode, the RY/ BY output

will be high.

During programming, the RY/ BY pin is driven low after the rising edge of the fourth WE pulse. During an

erase operation, the RY/ BY pin is driven low after the rising edge of the sixth WE pulse. The RY/ BY pin

will indicate a busy condition during the RESET pulse. Refer to Figure 11 and 12 for a detailed timing

diagram. The RY/ BY pin is pulled high in standby mode.

Since this is an open-drain output, RY/ BY pins can be tied together in parallel with a pull-up resistor to

V

CC

.

Byte/Word Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the L29S800F/-B devices. When this

pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ

0

to DQ . When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the

15

DQ /A pin becomes the lowest address bit and DQ to DQ bits are tri-stated. However, the command

15 -1

8

14

bus cycle is always an 8-bit operation and hence commands are written at DQ to DQ and the DQ to DQ

0

7

8

15

bits are ignored. Refer to Figures 13, 14 and 15 for the timing diagram.

Data Protection

The L29S800F/-B are designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the devices

automatically reset the internal state machine in the Read mode. Also, with its control register architecture,

alteration of the memory contents only occurs after successful completion of specific multi-bus cycle

command sequences.

The devices also incorporate several features to prevent inadvertent write cycles resulting form V_CC

power-up and power-down transitions or system noise.

24

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Low V_CCWrite Inhibit

To avoid initiation of a write cycle during V power-up and power-down, a write cycle is locked out for V

CC

less than 2.3 V (typically 2.4 V). If V

< V

, the command register is disabled and all internal

CC

LKO

program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent

writes will be ignored until the V level is greater than V

. It is the users responsibility to ensure that the

CC

LKO

control pins are logically correct to prevent unintentional writes when V is above 2.3 V.

CC

If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE , CE , or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = V , CE = V , or WE = V . To initiate a write cycle

IL

IH

CE and WE must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the devices with WE = CE = V and OE = V will not accept commands on the rising

IL

IH

edge of WE . The internal state machine is automatically reset to the read mode on power-up.

25

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ ABSOLUTE MAXIMUM RATINGS

Storage Temperature .......................................................................................…....–55°C to +125°C

Ambient Temperature with Power Applied ...................................................…........–40°C to +85°C

Voltage with respect to Ground All pins except A , OE , RESET (Note 1) ...….....–0.5 V to V +0.5 V

9

CC

V

CC

(Note 1) ............................................................................................…………...–0.5 V to +5.5 V

A , OE , and RESET (Note 2) ..................................................…….……........…..–0.5 V to +13.0 V

9

Notes: 1. Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negative

overshoot V to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are

SS

V

+0.5 V. During voltage transitions, outputs may positive overshoot to V +2.0 V for periods of

CC

up to 20 ns.

2. Minimum DC input voltage on A , OE and RESET pins are –0.5 V. During voltage transitions, A ,

9

RESET pins may negative overshoot V to –2.0 V for periods of up to 20 ns. Maximum

OE and

SS

DC input voltage on A , OE and RESET pins are +13.0 V which may positive overshoot to 14.0

9

V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (V – V

)

CC

IN

do not exceed 9 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Ambient Temperature (T ) ........................................................................................ –40°C to +85°C

A

V

Supply Voltages

CC

L29S800F-70/B....................................................................................................... +3.0 V to +3.6 V

L29S800F-90/B /-12/B ........................................................................................... +2.7 V to +3.6 V

Operating ranges define those limits between which the functionality of the devices are guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to

contact their LST representatives beforehand.

26

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ MAXIMUM OVERSHOOT

27

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ DC CHARACTERISTICS

Parameter

Symbol

Parameter Description

Test Conditions

Min.

Max. Unit

Input Leakage Current

Output Leakage Current

A , , RESET Inputs Leakage

-1.0

+1.0

µA

I

V

= V to V , V = V Max.

LI

IN

SS

CC

V

OUT

= V to V , V

= V

Max.

LO

SS CC CC

CC

V

CC

= V Max.

CC

OE

Current

9

—

35

22

25

12

15

µA

I

LIT

A ,

9

, RESET = 12.5 V

OE

Byte

= V ,

CE

f=10 MHz

OE

IL

IH

mA

Word

Byte

Word

I

V

CC

Active Current (Note 1)

CC1

= V ,

CE

f=5 MHz

CE

IL

IH

—

mA

µA

35

I

V

Active Current (Note 2)

Current (Standby)

= V ,

= V

CC2

CC

IL

IH

V

CC

= V Max.,

= V ± 0.3 V,

CE

CC

5

CC3

CC

RESET = V ± 0.3 V

CC

V

= V Max.,

CC

—

5

µA

I

V

Current (Standby, Reset)

CC4

CC5

CC

RESET = V ± 0.3 V

V_CC= V_CCMax.,

SS

= V_SS± 0.3 V,

CE

V

CC

Current

—

5

I

RESET = V ± 0.3 V

CC

(Automatic Sleep Mode) (Note 3)

Input Low Level

V

IN

= V ± 0.3 V or V ± 0.3 V

CC SS

—

-0.5

0.6

V

IL

Input High Level

2.0 V_CC+0.3

IH

Voltage for Autoselect and Sector

—

11.5

12.5

V

Protection (A ,

RESET )

OE

Output Low Voltage Level

Output High Voltage Level

Low V Lock-Out Voltage

ID

9

(Note 4)

0.45

—

V

I

= 4.0 mA, V = V Min.

CC CC

OL

OH

2.4

= –2.0 mA, V = V Min.

OH1

OH2

LKO

CC

—

V

_CC–0.4

= –100 µA

—

2.3

2.5

CC

Notes: 1. The I

current listed includes both the DC operating current and the frequency dependent

CC

component (at 10 MHz).

2. I active while Embedded Algorithm (program or erase) is in progress.

CC

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. (V – V ) do not exceed 9 V.

ID

CC

28

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ AC CHARACTERISTICS

• Read Only Operations Characteristics

Parameter

Symbols

-70

-90

-12

Description

Test Setup

Unit

(Note) (Note) (Note)

JEDEC Standard

t^AVAV

t^AVQV

t^RC

Read Cycle Time

—

Min.

70

90

120

ns

CE = V^IL

OE = V^IL

t^ACC

Address to Output Delay

Max. 70

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

t^CE

t^OE

t^DF

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

Max. 70

Max. 30

Max. 25

90

35

30

120

50

ns

OE = V^IL

—

30

Output Hold Time From Addresses,

CE or OE , Whichever Occurs First

t^AXQX

t^OH

—

Min.

0

ns

—

t^READY

—

Max. 20

Max.

20

5

20

5

µs

RESET Pin Low to Read Mode

t^ELFL

t^ELFH

5

ns

CE or BYTE Switching Low or High

Note: Test Conditions:

Output Load: 1 TTL gate and 30 pF (L29S800F/-B-70)

1 TTL gate and 100 pF (L29S800F/-B-90/-12)

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 1.5 V

Output:1.5 V

3.3V

IN3064

or Equivalent

2.7kΩ

Device

Under

Test

6.2kΩ

C_L

Diodes=IN3064

or Equivalent

Note:1.C_L=30pF including jig capacitance (-70)

2.C_L=100pF including jig capacitance(-90/-120)

Figure 4 Test Condition

29

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

• Write/Erase/Program Operations

Parameter Symbols

JEDEC Standard

L29S800F/-B

Description

Unit

-70

70

0

-90

90

0

-12

120

0

t^AVAV

t^AVWL

t^WLAX

t^DVWH

t^WHDX

—

t^WC

t^AS

Write Cycle Time

Min.

ns

µs

sec

µs

ns

Address Setup Time

Address Hold Time

Data Setup Time

t^AH

45

35

0

45

0

50

0

t^DS

t^DH

t^OES

Data Hold Time

Output Enable Setup Time

0

Output

Read

0

Enable Hold

Time

—

t^OEH

10

0

10

0

10

0

Toggle and Data Polling

t^GHWL

t^GHEL

t^CS

Read Recover Time Before Write

CE Setup Time

t^GHWL

t^GHEL

t^ELWL

t^WLEL

t^WHEH

t^EHWH

t^WLWH

t^ELEH

t^WHWL

t^EHEL

t^WHWH1

t^WHWH2

—

0

t^WS

0

Setup Time

WE

t^CH

0

CE Hold Time

t^WH

0

Hold Time

WE

t^WP

Write Pulse Width

35

25

8

45

25

8

50

30

8

t^CP

CE Pulse Width

t^WPH

t^CPH

t^WHWH1

t^WHWH2

t^VCS

t^VIDR

t^VLHT

t^WPP

t^OESP

t^CSP

t^RB

Write Pulse Width High

CE Pulse Width High

Byte Programming Operation

Sector Erase Operation (Note 1)

V^CCSetup Time

1

50

500

4

50

500

4

50

500

4

Rise Time to V^ID(Note 2)

Voltage Transition Time (Note 2)

Write Pulse Width (Note 2)

—

100

4

100

4

100

4

—

OE Setup Time to WE Active (Note 2)

CE Setup Time to WE Active (Note 2)

Recover Time From RY/ BY

—

4

—

0

t^RP

—

500

200

500

200

500

200

RESET Pulse Width

t^RH

—

RESET Hold Time Before Read

30

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

(Continued)

Parameter Symbols

JEDEC Standard

L29S800F/-B

Description

Unit

-70

30

90

30

-90

35

90

35

-12

50

90

50

—

t^FLQZ

t^FHQV

t^BUSY

t^EOE

Max.

Min.

ns

BYTE Switching Low to Output High-Z

BYTE Switching High to Output Active

Program/Erase Valid to RY/ BY Delay

Delay Time from Embedded Output Enable

Max.

Notes: 1. This does not include the preprogramming time.

2. This timing is for Sector Protection operation.

31

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

■ SWITCHING WAVEFORMS

32

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

t_RC

Addresses

Addresses Stable

t_ACC

CE

OE

t_DF

t_OE

t_OEH

WE

t_CE

High-Z

Outputs

Output Valid

Figure 5.1 AC waveforms for Read Operations

33

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

t_RC

Addresses Stable

Addresses

RESET

t_ACC

t_RH

t_OH

High-Z

Outputs

Output Valid

Figure 5.2 AC Waveforms for Hardware Reset/Read Operations

34

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

35

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

36

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

37

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

38

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

CE

The rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

t_BUSY

Figure 11 RY/BY Timing Diagram during Program/Erase Operations

WE

RESET

t_RP

t_RB

RY/BY

t_READY

Figure 12 RESET/RY/BY Timing Diagram

39

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

40

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

41

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

42

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

43

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

!

FLOW CHART

44

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

45

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

46

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

47

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

48

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Start

RESET=VID

(Note 1)

Perform Erase or

Program Operations

RESET=VIH

Temporary Sector

Unprotection Completed

(Note 2)

Notes:

1.All protected sectors are unprotected.

2.All previously protected are protected once again.

Figure 25 Temporary Sector Unprotection Algorithm

49

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

50

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

51

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

!

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

sec

μs

Word Programming Time

Byte Programming Time

—

16

8

360

300

Excludes system-level

overhead

Excludes system-level

overhead

Chip Programming Time

Program/Erase Cycle

—

8.4

—

25

—

sec

100,000

cycles

—

!

TSOP(I) PIN CAPACITANCE

Parameter

Parameter Description

Test Setup

V^IN= 0

Typ.

7.5

8

Max.

9.5

10

Unit

pF

Symbol

C^IN

Input Capacitance

C^OUT

Output Capacitance

V^OUT= 0

V^IN= 0

pF

C^IN2

Control Pin Capacitance

10

13

pF

Note: Test condition TA=25℃, f=1.0MHz

52

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

53

071802

L29S800F

8MEGABIT (1M×8 /512K×16)

3 VOLT CMOS FLASH MEMERY

PRELIMINARY

A

LinkSmart

Part Number Information

54

071802


型号：	L29S800F
厂家：	ETC
描述：	8MEGABIT (1M】8 /512K】16) 3 VOLT CMOS FLASH MEMERY 8MEGABIT （ 1M 】 8 / 512K 】 16 ） 3伏CMOS FLASH MEMERY
文件：	总54页 (文件大小：780K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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