L64767_技术文档

L64767

SMATV QAM Encoder

Datasheet

Introduction

LSI Logic’s L64767 SMATV QAM Encoder is a highly-integrated device

designed speciﬁcally for Satellite Master Antenna Television (SMATV)

applications. The L64767 is ideally suited to any application that requires

a low-power, highly integrated forward error correction (FEC)

transmission encoder. Typical applications include rooftop SMATV

systems, cable head-ends, and optical networks in ﬁber-deep networks.

Figure 1 shows a basic SMATV QAM system using the L64767. The

device can process input from either an MPEG-2 transport encoder, a

satellite receiver, or a transmission network.

Figure 1. L64767 SMATV QAM System

PPLLLL

MPEG-2 Transport

MUX

Cable

Plant

I

QPSK Satellite Receiver

LSI Logic

Passive

Filter

Analog

Mod

L64767

D/A

L64704

Q

Transmission

Network

MD97.1

The L64767 simpliﬁes the design process for FEC and modulation

encoding systems by providing built-in signal processing capabilities and

a byte-parallel, power saving architecture. The L64767’s ease of use will

help system engineers create the next generation of time-to-volume

sensitive digital products. In contrast, previous solutions for these

systems forced system engineers to use many programmable and

discrete devices on large circuit boards. These end products were

expensive and power-intensive, both of which are unacceptable for

today’s SMATV applications.

April 1999

1

The L64767 integrates CoreWare^®processing elements that conform to

the speciﬁcations described in the document DTVB1190/DTVC37,

Revision 3. Figure 2 shows the L64767’s major functional blocks.

Figure 2. L64767 Functional Blocks

Data In

8

10-bit

I

Sync/Error

Flag

Inserter

and

4

Diff.

Encoder

and

QAM

Mapper

Circular

FIFO

Buffer

Reed-

Solomon

Encoder

Bytes

to

m-tuple

Nyquist

Filter

8

Convolutional 8

Interleaver

Input

Sync

8

m

10-bit

Q

ICLK

Scrambler

OCLK

Global Control and Synchronization - Start/Stop Signals Generation

PLL

Microprocessor Interface

Test Scan Chain

DATA[7:0] DTACK_N READ

CS_N

AS_N

MD97.3

The CoreWare processing elements of the L64767 comprise the data

processing chain of the device and include:

♦

Input synchronizer

Circular FIFO buffer

Sync/error ﬂag inserter and scrambler

Reed-Solomon encoder

Convolutional interleaver

Bytes to m-tuple converter

Differential encoder and QAM mapper

Nyquist ﬁlter

2

L64767 SMATV QAM Encoder

In addition to the processing chain, the L64767 provides:

♦

Global control and synchronization components

Microprocessor interface for conﬁguring and monitoring internal

registers

♦

Test scan chain

The L64767 can accept byte-parallel or bit-serial input and provides

ﬂexible input synchronization support. It can automatically search for a

digital video broadcasting (DVB) or user-programmable 8-bit sync code.

Alternatively, the L64767 can use an external frame start signal to

indicate the beginning of a frame for input synchronization. By inserting

the Reed-Solomon (RS) check words into the circular FIFO buffer, the

device can also use an MPEG-2 input stream without gaps, or operate

on packets with gaps for RS check words.

The length of sync words and sync blocks is user-programmable, and

sync information can be reinserted as needed. The L64767 also provides

an error indication bit for MPEG-2 transport packet errors. Using this bit,

error ﬂags from a preceding device can be properly inserted in the

MPEG-2 transport stream.

The L64767 can process quadrature amplitude modulation (QAM) levels

of 16, 32, 64, 128, and 256. The QAM level is user-programmable.

L64767 SMATV QAM Encoder

3

Features

Beneﬁts

♦

SMATV DTVB1190/DTVC37,

Revision 3 compliant

♦

Directly connects to LSI Logic’s satellite

receiver/FEC

♦

Highly integrated, global

synchronization and clock control

Allows low-cost external ﬁlters (4-fold

oversampling mode)

♦

2- or 4-fold Nyquist ﬁlter oversampling

85° C ambient operation without special

cooling devices

Maskable interrupts for all error

conditions

Entire device or individual SMATV

CoreWare processing blocks available

♦

Individual module bypass

conﬁguration modes

♦

Easy interface to most input sources

♦

IEEE 1149.1 JTAG interface for testing

Continuous data-in, continuous data-out

operation

User-controllable input

synchronization schemes

♦

Input jitter handling and Reed-Solomon

gap insertion by 128-word circular FIFO

buffer

♦

Low-power (1 W), low-cost surface

mount package

♦

Up to 7.8 Mbaud operation

Up to 62 Mbits/second serial data

input

♦

Up to 10 Mbytes/second parallel data

input

♦

16, 32, 64, 128, 256 QAM modes

Reed-Solomon encoder

Frame sync-byte insertion

Convolutional data interleaving depth

(B = 12)

4

L64767 SMATV QAM Encoder

Functional Description

This section provides a brief description of the major blocks shown in

Figure 2.

Input Synchronizer

As shown in Figure 2, only the input synchronizer is driven by the input

clock. All other processing is done based on the OCLK. OCLK can be

two or four times the symbol clock (SCLK) frequency based on the

oversampling setting of the Nyquist ﬁlter.

ICLK is limited to a maximum of 62.5 MHz in serial input mode and

10 MHz in parallel input mode. The maximum symbol rate handled by

the L64767 is 7.5 Mbaud. Therefore, OCLK is limited to 15 MHz in 2-fold

oversampling mode and 30 MHz in 4-fold oversampling mode.

The input format for the L64767 is based on the data format speciﬁed in

the MPEG-2 system layer standard in relation to the DVB transport

framing structure. It requires a Reed-Solomon (204,188) protected

transport packet to consist of 204 bytes, including the sync byte plus

187 data bytes and 16 redundancy bytes.

This basic format has been adopted by the V4/MOD-B task force for a

multiprogram TV via satellite standard, and by the DVB group in Europe.

In a scrambled DVB data stream, one out of every eight synchronization

words is mod 2 complemented (inverted) in order to deﬁne the beginning

of a scrambling sequence.

The descrambled stream contains no inverted sync word. This MPEG-2

frame format is the basic input format for the L64767 device. The device

assumes that the inserted sync byte at the chip input can only have the

normal value, not the inverted one. You can insert gaps for Reed-Solomon

check bytes or make them available in the input stream.

To synchronize input, you can do one of the following:

♦

Send a frame start pulse at the FSTARTIN pin forcing the beginning

of each Reed-Solomon code block. Whenever FSTARTIN is

asserted, the L64767 reinserts the sync byte into the data stream

and inverts the sync word every eight blocks, as deﬁned by the DVB.

L64767 SMATV QAM Encoder

5

♦

Specify a unique sync byte to be inserted in the input stream in a

speciﬁed sync length distance

Synchronizing the L64767 with an input pulse will set byte and block

boundaries with the pulse. The sync byte you deﬁne can be reinserted

at the location of the pulse.

Circular FIFO Buffer

A dual-ported RAM implements the circular FIFO buffer in the L64767.

The circular buffer has a write pointer driven by ICLK, and a read pointer

driven by OCLK/4 (or OCLK/2 in 2-fold oversampling mode). Since there

are no built-in mechanisms to prevent collisions of these pointers, you

must conﬁgure the follow-up time and proper initial setup of the pointer

distance through the phase-locked loop (PLL) module of the L64767. The

circular FIFO buffer is illustrated in Figure 3.

You can ensure that the read pointer is directly opposite to the write

pointer most of the time by properly programming delay values. This

approach reduces the effect of PLL frequency swings that can occur

during phases of an unstable input signal. You can also select smaller

distances to reduce system delay.

Figure 3. Circular Read/Write FIFO Buffer

Write Pointer

Circular

Buffer

Read Pointer

Zero

128 Words

MD97.16

To initialize the circular FIFO buffer, download 0 to 127 cycles into the

read address pointer to specify the distance between the read and write

pointers. To do this, you can specify the FIFO delay value. When

specifying this value, you must use Gray code numbers with even parity

(an even number of 1s). Both the read and write pointers are Gray code

counter-driven. The write pointer is initialized to zero when the read

counter is loaded.

6

L64767 SMATV QAM Encoder

After initialization, both pointers run independently. The frequency

relationship of OCLK to ICLK determines how the read and write pointers

advance. The L64767 asserts its FIFOALARM pin whenever the two

pointers are equal. This information is also available through a

FIFO_ALARM_STORE bit.

Sync/Error Flag Inserter and Scrambler

By specifying the sync insertion mode, you can instruct the sync inserter

to insert sync bytes into the data stream. Sync insertion minimizes bit

errors in sync bytes (even if sync is already inserted in the stream). If

sync bytes are contained in the bit stream and are used for synchro-

nization of the device, regenerated sync bytes conceal single errors in

the sync pattern.

When an uncorrectable error has occurred (ERRORIN signal is HIGH),

the L64767 sets both the MPEG-2 transport_error_indicator bit in the

packet (the most signiﬁcant bit of the second byte in a packet) and

ERF_STORE. You can use ERF_STORE to check if an error has

occurred. You can also conﬁgure the L64767 to issue an interrupt for

these errors or continue processing without an interrupt.

The scrambler module performs energy dispersion of the data stream.

This module operates in parallel mode. For a complete description of the

functional characteristics of this module refer to the standards document

DTVB1190/DTVC37, Revision 3.

Reed-Solomon Encoder

Reed-Solomon (RS) codes aid in error correction by using redundant

check symbols in its code words. RS error correction codes are

systematic and operate on bytes rather than single-bit data streams. RS

codes are expressed, by convention, as two numbers. The ﬁrst indicates

the total code word length (N). The second indicates the number of

message bytes (K). The difference between these two numbers (N – K)

is the number of check bytes.

Convolutional Interleaver

The interleaver rearranges the ordering of a sequence of symbols in a

deterministic manner. Since the interleaver is convolutional, it requires

less memory than the conventional RAM-intensive block type interleavers.

L64767 SMATV QAM Encoder

7

The interleaver is a (B, N) periodic interleaver with the following

characteristics:

♦

The minimum separation at the interleaver output is B symbols for

any two symbols that are separated by less than N symbols at the

interleaver input.

♦

Any burst of b < B errors inserted by the channel results in single

errors at the deinterleaver output.

Bytes to m-tuple Converter

The bytes to m-tuples converter organizes bytes into symbols (tuples) of

m = 1, 2, 3, 4, 5, 6, 7, and 8 bits. To process the data stream, the L64767

feeds the converter packets of eight bytes together with a valid signal

from the general control unit. The order of the conversion process starts

with the MSB of the oldest byte ﬁrst (see the document

DTVB1190/DTVC37, Revision 3 for details).

Differential Encoder and QAM Mapper

This block performs differential encoding and mapping for 16 to 256 QAM,

as speciﬁed in the document DTVB1190/DTVC37, Revision 3.

Nyquist Filter

The Nyquist ﬁlter shapes signals for DVB compliance. This ﬁlter

implements the square root raised cosine ﬁltering function with roll off

factor of 15%, as speciﬁed in DTVB1190/DTVC37, Revision 3. You can

use other non-DVB ﬁltering functions by downloading the appropriate

ﬁlter coefﬁcients.

The precision of the internal computations and the width of the output

data bus are suitable up to 256 QAM. The ﬁlter interpolates the input

data by a factor of two or four so that the ﬁlter output data rate is two or

four times the ﬁlter input data rate. You specify the interpolation factor

(oversampling) using a conﬁguration register.

8

L64767 SMATV QAM Encoder

Global Control and Synchronization Module

The L64767’s clocking scheme uses two independent clock signals

(ICLK, OCLK) to control incoming data, internal data processing, and

decoded output data. These clocks provide the timing for two circular

FIFO buffers that read and write data. Data on the FIFO input is latched

with respect to the valid rising edges of ICLK. Data on the FIFO output

is read with respect to the valid rising edge of OCLK.

A FIFO control unit coordinates the operation of these two asynchronous

ports and issues the appropriate control signals. For proper operation of

the FIFO control unit, you must ensure that OCLK is frequency-locked to

ICLK.

The global control circuitry of the L64767 governs the entire data path

from an MPEG-2 input source, through the processing chain, and to the

ﬁnal output from the device. Global control ensures that the output data

stream is continuous (no gaps between the symbols), assuming that the

incoming data rate is constant. The output clock OCLK of the L64767 is

externally derived from the input clock ICLK, and is kept in sync through

a phase-locked loop (PLL) module locked to the appropriate ICLK versus

OCLK ratio. Short term variations of frequency offset are handled by the

128-byte circular FIFO buffer. Other variations are controlled by the

external PLL module.

You can check for overrun errors using the FIFO collision detection

feature. This provides immediate output on a pin when a collision is

detected and sends an interrupt-generating event on the microprocessor

interface.

Microprocessor Interface

The L64767 has a bidirectional microprocessor interface that allows you

to write to and read back from the 14 internal registers. During normal

operation, the L64767 requires no interaction with the microprocessor.

However, you must conﬁgure all registers after a reset operation to

guarantee that the device will function properly.

The default operational mode of the L64767 is used for DVB-compliant

operation at 64 QAM, and for four-fold oversampling. However, the chip

supports modes of operation from 16 to 256 QAM.

L64767 SMATV QAM Encoder

9

The internal registers you conﬁgure through the microprocessor deﬁne

the primary operational modes of the L64767. These modes and

conﬁgurations include the following, among many others:

♦

Input synchronization mode (whether to lock synchronization to sync

bytes or input pulses)

♦

Nyquist ﬁlter coefﬁcients

Delay value for proper FIFO initialization

The microprocessor interface is related to microcontrollers of the 68xxx

family. The L64767 is not dedicated to supporting high-speed burst

modes of DMA controllers with continuously asserted CS_N signal at the

interface.

If the L64767 detects an error, the error is indicated on output pins of the

L64767 and through the microprocessor interface. Error indications like

the FIFOALARM signal are helpful for debugging and troubleshooting.

Test Unit

A built-in scan chain executes the functionality test. The pins

SCAN_ENABLE, SCAN_MODE, and T_N are used for this purpose.

Signal Descriptions

This section describes the L64767’s interface signals. As shown in Figure 4,

these signals are grouped into the following categories:

♦

Input signals (for example, those from an LSI Logic L64704 for the

MPEG-2 TL MUX)

♦

Output signals (for example, to an analog QAM modulator)

Control signals (including test pins)

Microprocessor interface signals

Within each category, the signals are described in alphabetical order by

signal mnemonic.

10

L64767 SMATV QAM Encoder

Figure 4. L64767 Signals

Microprocessor Interface

FIFOALARM

FIRSTOUT

FSTARTOUT

SCLK

DIN[7:0]

DVALIDIN

Output to

Analog

QAM

Input from

L64704 or

MPEG-2 TL MUX

ERRORIN

FSTARTIN

ICLK

L64767

SMATV Encoder

Modulator

SMAENC_I[9:0]

SMAENC_Q[9:0]

SYNCOK

SSTARTIN

Control and Test Signals

MD97.118

Input Signals

This section describes the input signals to the L64767 from another

device such as the LSI Logic L64704 for the MPEG-2 TL MUX.

DIN[7:0]

Parallel/Serial Data In

Input

This is a level-sensitive, 8-bit data bus for parallel or

serial data input. Serial data is fed to DIN[0]. Data is

sampled at the rising edge of ICLK.

L64767 SMATV QAM Encoder

11

DVALIDIN

ERRORIN

FSTARTIN

Clock Enable Input

Input

This is an active HIGH, level-sensitive data signal. When

HIGH, the L64767 accepts data from DIN[7:0] on a

continuous basis. When LOW, the L64767 halts data

input to the internal FIFO buffer and other data processing

blocks. No new input from the DIN[7:0] pins is accepted.

Error Detection Flag

Input

This is an active HIGH, level-sensitive data signal. When

an uncorrectable error occurs, ERRORIN is HIGH. The

L64767 checks the status of ERRORIN at the ﬁrst bit of

a frame. If an error has occurred, the ERRORIN status is

copied to the MPEG-2 error indication bit if required.

External Sync Frame Start

Input

This is an active HIGH, level-sensitive data signal. Driving

FSTARTIN to HIGH marks the beginning of an MPEG-2

transport packet. If the incoming bitstream contains no

unique synchronization words, you must use this pin to

indicate the frame start. Synchronization with FSTARTIN

is forced into the chip and is not ﬂywheel stabilized. If the

sync insertion mode is programmed, the L64767 regen-

erates sync information and inserts it into the data stream

as programmed by the microprocessor interface.

ICLK

Input Clock

Input

This is a positive, edge-triggered input clock. The L64767

samples inputs DIN[7:0], DVALIDIN, ERRORIN, FSTARTIN,

and SSTARTIN on ICLK’s rising edge. ICLK is either a

byte clock or a bit clock, depending on the programming

of SERIN (bit 7 of Register 0).

SSTARTIN

Sync Sequence Start

Input

This is an active HIGH signal that marks the beginning of

a new, fully reset sequence. If the signal’s falling edge is

evaluated, all internal sequences (inverted sync,

scrambler, interleaver, and differential encoder) are

restarted with the next block start. If SSTARTIN is never

asserted, all internal sequences run free after the reset.

This pin has an internal pull-down resistor.

12

L64767 SMATV QAM Encoder

Output Signals

This section describes the output signals from the L64767 to another

device such as an analog QAM modulator.

FIFOALARM FIFO Collision Detected

Output

This alarm signal indicates the FIFO control has detected

equal pointers for read and write access. The collision is

probably caused by an unlocked external PLL-VCO

circuitry. The signal is synchronized with SCLK-driven

ﬂip-ﬂops for the output.

FIRSTOUT

First Block of a New Sequence Out

Output

This signal occurs together with FSTARTOUT and

indicates the head of a sync block, which has just reset

all internal sequences, as controlled by SSTARTIN.

FIRSTOUT is the acceptance of an SSTARTIN falling

edge delayed by all internal processing modules.

FSTARTOUT Frame Start

Output

FSTARTOUT is driven HIGH during the ﬁrst symbol in

every sync frame. The width of FSTARTOUT reﬂects the

number of bytes inserted by the gap parameter. A

one-cycle width indicates no additionally inserted gaps.

A width of 17 means 16 RS check bytes have been

inserted. FSTARTOUT is applied only in synchronization

word detection mode. If synchronization is forced by

FSTARTIN pulses, FSTARTOUT is constantly LOW.

SCLK

Symbol Clock

Output

SCLK is a clock output signal that is synchronous to

symbols and bytes processed internally.

SMAENC_I[9:0]

Symbol I Modulation

Output

These signals provide 10-bit digital values at the digital

ﬁlter output for D/A conversion and for analog modulation.

SMAENC_Q[9:0]

Symbol Q Modulation

Output

These signals provide 10-bit digital values at the digital

ﬁlter output for D/A conversion and for analog modulation.

L64767 SMATV QAM Encoder

13

SYNCOK

SYNC Detection/Phase Monitoring

Output

In internal sync mode, when this signal is HIGH, it

indicates a correct lock to the input sync sequence, and

the number of track steps required for synchronization is

fulﬁlled. If synchronization is forced by FSTARTIN pulses,

SYNCOK is constantly LOW.

Control Signals

This section describes the control signals for the L64767.

OCLK Output Processing Clock

Input

This is a positive edge-triggered clock signal. The L64767

internally processes data (through the scrambler,

interleaver, and Reed-Solomon encoder) based on a

fraction of OCLK. Data outputs (I, Q, FSTARTOUT) are

referenced to OCLK. OCLK is independent of ICLK.

PLL_OUT_CS PLL Current Source

Output

This signal is a 4.5-mA charge pump output from the

phase/frequency detector. The comparator is frequency-

and phase-sensitive. This signal is normally 3-state Z

level, and drives positive and negative current as

required. Depending on the conﬁguration, the current

source can be inverted.

PLL_OUT_EX PLL Phase Sensitive EXOR Comparator

Output

This signal is the output from the EXOR phase comparator.

PLL_OUT_LO PLL Phase Sensitive Lock Detector

Output

This signal is the output from the PLL lock detector.

RESET

Reset Input

This is a level-sensitive data signal. It resets all internal

data paths. Reset timing is asynchronous to the device

clocks and does not interfere with the active clock edges

of ICLK and OCLK for reproducible output values. Reset

affects all the configuration registers and filter coefficients,

which must be downloaded again after reset.

14

L64767 SMATV QAM Encoder

Test Signals

The eight signals described below control functions such as chip-level,

full scan tests, JTAG tests, and internal RAM tests. Five pins (TCK, TDI,

TDO, TMS, and TRST) are used for JTAG tests. The other three pins are

for SCAN_ENABLE, SCAN_MODE, and T_N (test output enable). Note

that the L64767 is in normal functional mode when SCAN_ENABLE,

SCAN_MODE, TCK, TDI, TMS, T_N, and TRST are left unconnected.

SCAN_ENABLE

Scan Enable

Input

This is a level-sensitive data signal with a pull-down

resistor. When HIGH, this signal enables scan chain shift.

In default normal operation, SCAN_ENABLE is LOW.

SCAN_MODE Scan Mode

Input

This is a level-sensitive signal with a pull-down resistor.

When this signal is HIGH, the chip is switched to scan

test mode. In default normal operation, SCAN_MODE is

LOW.

TCK

TDI

Test Mode Clock

Input

When HIGH, this is a rising or falling edge signal for the

JTAG test mode clock. In default normal operational

mode, TCK is LOW.

Test Data Input

Input

When HIGH, this level-sensitive signal provides JTAG

data input. In default normal operational mode, TDI is

LOW.

TDO

TMS

Test Data

This is the JTAG data output.

Output

Test Mode Select

Input

When HIGH, this level-sensitive signal enables the JTAG

test mode. In default normal operational mode, TMS is

LOW.

T_N

Test Output Enable

Input

This is an active LOW signal with a pull-up resistor that

disables the test mode when T_N is LOW. It switches all

3-stated buffers to high-impedance mode for test or

device selection on a common bus. In default normal

operation, T_N is HIGH.

L64767 SMATV QAM Encoder

15

TRST

JTAG Test Reset

Input

When HIGH, this level-sensitive data signal resets the

JTAG unit. In default normal operational mode, TRST is

LOW.

Microprocessor Interface Signals

This section describes the microprocessor interface signals of the L64767.

ADR[3:0]

Address for Internal Registers

Input

This is a level-sensitive, 4-bit address bus the L64767

uses along with the 8-bit data bus DATA[7:0], a read/write

strobe (READ), a chip select strobe (CS_N), and an

address strobe (AS_N) to read and write internal

registers. The address lines are used to select among

internal registers.

AS_N

CS_N

Address Strobe

Input

This is an active LOW address strobe input signal. It

latches the address on the ADR[3:0] bus on the falling

edge.

Chip Select

Input

This is an active LOW chip select strobe input signal.

During a read cycle, CS_N must be LOW to access the

on-chip data registers. The controller can latch the data

from the L64767 with the rising edge of CS_N. During a

write cycle, CS_N must go active LOW prior to data being

valid from the controller to the L64767. After the data has

met the minimum setup time, CS_N HIGH will strobe the

data. There is a minimum write time to allow for internal

synchronization.

DATA[7:0]

DTACK_N

Data Bus [7:0]

Bidirectional

This is a level-sensitive data signal. The bidirectional data

bus is used for input when writing data to the chip, and

as output when the chip is read. When not being read or

written, the data lines are 3-stated.

Data Acknowledge

Output

This is an active LOW output signal indicating that the

transaction on the data bus is completed.

16

L64767 SMATV QAM Encoder

INT_N

READ

Interrupt Request

Output

The L64767 drives INT_N LOW when the interrupt is

enabled and an interrupt condition occurs. INT_N is an

open drain output, requiring an external pull-up resistor

for operation.

Read/Write Strobe

Input

This level-sensitive data signal is an active LOW write

strobe input signal. The microprocessor must drive this

signal LOW to write to the L64767’s registers, and must

drive it HIGH to read from them.

Speciﬁcations

This section presents the electrical, timing, pinout, and packaging

speciﬁcations for the L64767.

Electrical Requirements

This section lists the DC electrical requirements for the L64767.

The tables in this section specify the electrical requirements for the

L64767 encoder.

♦

Table 1 provides the L64767’s absolute maximum electrical and

temperature ratings.

♦

Table 2 provides the L64767’s recommended operating conditions.

Table 3 lists the L64767’s DC characteristics.

Table 1. Absolute Maximum Ratings

Symbol Parameter

Limits¹

Unit

V_DD

V_IN

DC supply

-0.3 to +7

-0.3 to V_DD+0.3

±10

V

Input voltage

DC input current

I_IN

mA

°C

T_STG

Storage temperature range (plastic) -40 to +125

1. Referenced to V_SS

.

L64767 SMATV QAM Encoder

17

Table 2. Recommended Operating Conditions

Symbol Parameter

Limits

Unit

V_DD

T_A

DC supply

+4.75 to +5.25

0 to +85

V

Ambient temperature

°C

For values in Table 3, note that the L64767 is produced with LSI Logic’s

LCB300K HCMOS process, which is characterized by a 0.6-micron

drawn gate-length (0.45-micron effective channel length). Values in the

table are speciﬁed at V

speciﬁed range.

= 5 V ± 5% at ambient temperature over the

DD

The actual product characterization for the L64767 was not available at

the time of this printing.

Table 3. DC Operating Characteristics

Symbol Parameter

Condition¹

Min Typ Max Units

V_IL

V_IH

V_IL

Voltage input LOW, TTL

–

0.8

–

V

Voltage input HIGH, TTL

Voltage input LOW, CMOS

Voltage input HIGH, CMOS

Voltage output HIGH

2.0

1.5

V_IH

V_OH

V_OL

I_OZ

3.5

I_OH= -4.0 mA

I_OL= 4.0 mA

2.4 4.5

–

V

Voltage output LOW

–

0.1 0.4

Current 3-state leakage with V_DD= Max, V_OUT= V_SSor V_DD

pull-down

-10

±1 250

µA

I_IN

Current input leakage

V_DD= Max, V_IN= V_DDor V_SS

-10

±1

10

µA

Current input leakage with

pull-up

-220 ±1

I_IN

Current input leakage with

pull-down

V_DD= Max, V_IN= V_DDor V_SS

-10

±1 250

µA

I_DD

I_CC

Quiescent supply current

Dynamic supply current

V_IN= V_DDor V_SS

–

2

–

mA

ICLK = 62.5 MHz,

OCLK = 31.25 MHz,

V_DD= Max

200

P

Power dissipation

1

W

1. Speciﬁed at V_DD= 5 V ± 5% at ambient temperature over the speciﬁed range.

18

L64767 SMATV QAM Encoder

AC Timing

This section presents L64767 AC timing information, which was

simulated using a 16 MHz microprocessor. The numbers in column 1 of

Table 4 refer to the timing parameters shown in the timing diagrams that

follow. All parameters in this table apply for T = 0 °C

A

to 85 °C, V

= 4.75 V to 5.25 V, and an output load of 50 pF.

DD

The actual product characterization for the L64767 was not available at

the time of this printing.

Table 4. L64767 Timing Parameters

31/62 MHz

Max

Parameter

Description

Min

Unit

1

2

t_CYCLE

t_PWH

Clock Cycle OCLK

32

15

–

ns

Clock Pulse Width HIGH OCLK

3

4

5

6

7

8

9

t_PWL

Clock Pulse Width LOW OCLK

Clock Cycle ICLK

15

16

7

–

ns

t_{I_CYCLE}

t_{I_PWH}

t_{I_PWL}

t_{I_S}

Clock Pulse Width HIGH ICLK

Clock Pulse Width LOW ICLK

Input Setup Time to ICLK

Input Hold to ICLK

–

7

–

6

–

t_{I_H}

1

–

t_OD

Output Delay from OCLK

Reset Pulse Width HIGH

3

15

–

10 t_RWH

11 t_WK

50

1024

2244

Wake-up time after RESET, used

for RAM initialization during

microprocessor conﬁguration

access

–

ICLK cycles with

DVALIDIN = HIGH

OCLK cycles

–

12 t_SURCS

13 t_SUA

READ Setup Before CS_N LOW

1

2

-

ns

ADR[3:0] Setup Before AS_N

LOW

(Sheet 1 of 2)

L64767 SMATV QAM Encoder

19

Table 4. (Cont.) L64767 Timing Parameters

31/62 MHz

Max

Parameter

Description

Min

Unit

14 t_HLDA

15 t_DCSDTL

16 t_HLDD

ADR[3:0] Hold After AS_N LOW

CS_N LOW to DTACK_N LOW

1

-

ns

3 t_CYCLE+ 15

-

Write Data Hold After CS_N

HIGH

0

17 t_{CYCLE_CS}Minimum CS_N Width

2 t_CYCLE

-

ns

18 t_HLDRCS

19 t_WRREC

20 t_DCSDTH

21 t_DELZL

22 t_DELD

READ Hold After CS_N HIGH

1

-

Write Recovery Time

2 t_CYCLE

-

CS_N HIGH to DTACK_N HIGH

CS_N LOW to Data Driven

CS_N LOW to Data Valid

CS_N HIGH to Data 3-State

Data Setup Before CS_N Change

Delay from T_N

-

2 t_CYCLE+ 15

3 t_CYCLE+ 20

2 t_CYCLE+ 20

-

23 t_DELLZ

24 t_SUD

-

6

–

25 t_TDLY

15

(Sheet 2 of 2)

Figure 5. L64767 Synchronous AC Timing

1 & 4

2 & 5

3 & 6

OCLK

ICLK

7

8

Inputs

9

Outputs

MD97.33

20

L64767 SMATV QAM Encoder

Figure 6. L64767 Read Cycle

12

22

23

CS_N

21

DATA[7:0]

Valid

AS_N

13 14

17

ADR[3:0]

READ

Valid

18

20

15

DTACK_N

MD97.34

Figure 7. L64767 Write Cycle

17

19

12

16

CS_N

24

Valid

DATA[7:0]

AS_N

13 14

ADR[3:0]

READ

Valid

18

20

15

DTACK_N

MD97.35

L64767 SMATV QAM Encoder

21

Figure 8. L64767 RESET Timing Diagram

10

11

RESET

MD97.36

Figure 9. L64767 Bus 3-State Delay Timing

T_N

25

DATA[7:0]

SMAENC_I[9:0]

SMAENC_Q[9:0]

Pinout and Packaging

Figure 10 shows the signal pins of the L64767 SMATV encoder. It shows

the location, pin number, and signal for each pin on the 100-pin MQUAD

package. This pinout is followed by the mechanical dimensions of the

L64767’s package.

22

L64767 SMATV QAM Encoder

Mechanical Dimensions

Figure 11 provides packaging information for the 100-pin MQUAD (WE,

RECTANGULAR) L64767 chip.

Figure 11. 100-Pin MQUAD Mechanical Drawing (Cavity Up)

For board layout and manufacturing, obtain

the most recent engineering drawings from

your LSI Logic marketing representative by

requesting the outline drawing for package

code WE.

MD97.WE-1

24

L64767 SMATV QAM Encoder

Figure 11 (Cont.) 100-Pin MQUAD Mechanical Drawing (Cavity Up)

For board layout and

manufacturing, obtain the

most recent engineering

drawings from your LSI Logic

marketing representative by

requesting the outline drawing

for package code WE.

MD97.WE-2

L64767 SMATV QAM Encoder

25

L64767 Pin Descriptions

This section describes the signal pins of the L64767 SMATV encoder.

Table 5 summarizes the pins on the L64767. The table provides the

signal types for both output and input pins, and the drive capacity for

outputs. The summary is followed by Table 6, a pin list, which relates the

signal on each pin to a pin number on the 100-pin MQUAD package.

Table 5. L64767 Pin Description Summary

Drive

(mA)

Mnemonic

Description

Type

Active

DIN[7:0]

Parallel/Serial Data In

Clock Enable Input

Error Detection Flag

TTL Input

–

HIGH

DVALIDIN

ERRORIN

FSTARTIN

External Sync Frame

Start

ICLK

Input Clock

TTL Input

–

4

+

SSTARTIN

FIFOALARM

FIRSTOUT

Sync Sequence Start

FIFO Collision Detected

TTL Input with pull-down

Output

HIGH

First Block of a New

Sequence Out

Output

FSTARTOUT

SCLK

Frame Start

Output

4

HIGH

+

Symbol Clock

Output

SMAENC_I[9:0]

SMAENC_Q[9:0]

SYNCOK

Symbol I Modulation

Symbol Q Modulation

3-State Output

Output

HIGH

Sync Detection/Phase

Monitoring

OCLK

Output Processing Clock TTL Input

–

4

+

PLL_OUT_CS

PLL_OUT_EX

PLL Current Source

3-state Current Source

Output

3-state

HIGH

PLL Phase Sensitive

EXOR Comparator

(Sheet 1 of 2)

26

L64767 SMATV QAM Encoder

Table 5. (Cont.) L64767 Pin Description Summary

Drive

(mA)

Mnemonic

Description

Type

Active

PLL_OUT_LO

PLL Phase Sensitive Lock Output

Detector

4

HIGH

RESET

SCAN_ENABLE

SCAN_MODE

TCK

Reset

TTL Input

–

4

–

HIGH

+

Scan Enable

Scan Mode

TTL Input with pull-down

Output

Test Mode Clock

Test Data Input

Test Data

TDI

HIGH

LOW

HIGH

TDO

TMS

Test Mode Select

Test Output Enable

JTAG Test Reset

TTL Input with pull-down

TTL Input with pull-up

TTL Input with pull-down

TTL Input

T_N

TRST

ADR[3:0]

Address for Internal

Registers

AS_N

Address Strobe

Chip Select

TTL Input

–

4

–

LOW

HIGH

LOW

HIGH

CS_N

TTL Input

DATA[7:0]

DTACK_N

INT_N

Data Bus [7:0]

Bidirectional TTL I/O

Output

Data Acknowledge

Interrupt Request

Read/Write Strobe

Open Drain, driving LOW

TTL Input

READ

(Sheet 2 of 2)

L64767 SMATV QAM Encoder

27

Table 6. Pin List for the 100-pin MQUAD

Signal

1

2

3

4

5

6

7

8

SMAENC_I0

SMAENC_I1

VDD

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

SMAENC_Q7

VSS

VDD

SMAENC_Q8

SMAENC_Q9

SYNCOK

INT_N

DTACK_N

VDD

VSS

OCLK

VSS

VDD

VSS

VDD

SCLK

VDD

VSS

FIFOALARM

TDO

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

PLL_OUT_CS

VSS

VDD

TRST

SSTARTIN

TMS

FSTARTIN

ERRORIN

TDI

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

SCAN_ENABLE

T_N

VSS

VDD

SMAENC_I2

SMAENC_I3

SMAENC_I4

SMAENC_I5

SMAENC_I6

SMAENC_I7

VDD

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

VSS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

TCK

RESET

DVALIDIN

VSS

ICLK

DIN7

DIN6

DIN5

VSS

VDD

DIN4

DIN3

DIN2

SCAN_MODE

DIN1

VSS

SMAENC_I8

SMAENC_I9

VDD

DATA0

VSS

VDD

SMAENC_Q0

SMAENC_Q1

SMAENC_Q2

VSS

CS_N

READ

AS_N

VSS

VDD

VSS

VDD

SMAENC_Q3

SMAENC_Q4

SMAENC_Q5

SMAENC_Q6

FSTARTOUT

FIRSTOUT

PLL_OUT_LO

PLL_OUT_EX

ADR3

ADR2

ADR1

ADR0

DIN0

28

L64767 SMATV QAM Encoder

Notes

L64767 SMATV QAM Encoder

29

Notes

30

L64767 SMATV QAM Encoder

Notes

L64767 SMATV QAM Encoder

31

Sales Ofﬁces and Design Resource Centers

Korea

LSI Logic Corporation

Corporate Headquarters

Tel: 408.433.8000

New Jersey

Edison

Denmark

LSI Logic Development

Centre

Ballerup

Tel: 45.44.86.55.55

Fax: 45.44.86.55.56

LSI Logic Corporation of

Korea Ltd

Seoul

♦ Tel: 908.549.4500

Fax: 408.433.8989

Fax: 908.549.4802

♦ Tel: 82.2.561.2921

New York

Tel: 716.223.8820

Fax: 716.223.8822

Fax: 82.2.554.9327

NORTH AMERICA

Singapore

LSI Logic Pte Ltd

Singapore

Tel: 65.334.9061

Fax: 65.334.4749

France

LSI Logic S.A.

Paris

California

Irvine

♦ Tel: 714.553.5600

North Carolina

Raleigh

Tel: 919.783.8833

Fax: 919.783.8909

♦ Tel: 33.1.34.63.13.13

♦ Fax: 714.474.8101

Fax: 33.1.34.63.13.19

San Diego

Tel: 619.635.1300

Fax: 619.635.1350

Electronic Resources Ltd

Tel: 65.298.0888

Fax: 65.298.1111

Germany

LSI Logic GmbH

Munich

Oregon

Beaverton

Tel: 503.645.0589

Fax: 503.645.6612

♦ Tel: 49.89.4.58.33.0

Silicon Valley

Sales Ofﬁce

Tel: 408.433.8000

Fax: 408.954.3353

Design Center

Spain

LSI Logic S.A.

Madrid

Fax: 49.89.4.58.33.108

Stuttgart

Tel: 49.711.13.96.90

Fax: 49.711.86.61.428

Texas

Austin

Tel: 512.388.7294

Fax: 512.388.4171

♦ Tel: 34.1.3672200

Fax: 34.1.3673151

♦ Tel: 408.433. 8000

Fax: 408.433.2820

Sweden

LSI Logic AB

Stockholm

Hong Kong

AVT Industrial Ltd

Hong Kong

Tel: 852.2428.0008

Fax: 852.2401.2105

Colorado

Boulder

Tel: 303.447.3800

Fax: 303.541.0641

Dallas

♦ Tel: 214.788.2966

♦ Tel: 46.8.444.15.00

Fax: 214.233.9234

Fax: 46.8.750.66.47

Houston

Tel: 713.379.7800

Fax: 713.379.7818

Switzerland

LSI Logic Sulzer AG

Brugg/Biel

Tel: 41.32.536363

Fax: 41.32.536367

India

Florida

Boca Raton

Tel: 407.989.3236

Fax: 407.989.3237

LogiCAD India Private Ltd

Bangalore

Tel: 91.80.526.2500

Fax: 91.80.338.6591

Washington

Bellevue

Tel: 206.822.4384

Fax: 206.827.2884

Georgia

Atlanta

Tel: 770.395.3808

Fax: 770.395.3811

Taiwan

LSI Logic Asia-Paciﬁc

Taipei

Israel

LSI Logic

Ramat Hasharon

♦ Tel: 972.3.5.403741

Fax: 972.3.5.403747

Canada

Ontario

Ottawa

♦ Tel: 886.2.718.7828

Fax: 886.2.718.8869

Illinois

Schaumburg

♦ Tel: 613.592.1263

Cheng Fong Technology

Corporation

Tel: 886.2.910.1180

Fax: 886.2.910.1175

Netanya

♦ Tel: 847.995.1600

Fax: 613.592.3253

♦ Tel: 972.9.657190

Fax: 847.995.1622

Fax: 972.9.657194

Toronto

Kentucky

♦ Tel: 416.620.7400

Italy

LSI Logic S.P.A.

Milano

Bowling Green

Tel: 502.793.0010

Fax: 502.793.0040

Fax: 416.620.5005

Lumax International

Corporation, Ltd

Tel: 886.2.788.3656

Fax: 886.2.788.3568

Quebec

Montreal

♦ Tel: 39.39.687371

Maryland

Bethesda

Fax: 39.39.6057867

♦ Tel: 514.694.2417

Fax: 514.694.2699

Macro-Vision

♦ Tel: 301.897.5800

Japan

LSI Logic K.K.

Tokyo

Technology Inc.

Tel: 886.2.698.3350

Fax: 886.2.698.3348

Fax: 301.897.8389

INTERNATIONAL

Massachusetts

Waltham

♦ Tel: 81.3.5463.7821

Australia

Fax: 81.3.5463.7820

United Kingdom

LSI Logic Europe plc

Bracknell

Reptechnic Pty Ltd

New South Wales

Tel: 612.9953.9844

Fax: 612.9953.9683

♦ Tel: 617.890.0180

Fax: 617.890.6158

Osaka

♦ Tel: 81.6.947.5281

♦ Tel: 44.1344.426544

Minnesota

Minneapolis

Fax: 81.6.947.5287

Fax: 44.1344.481039

♦ Tel: 612.921.8300

♦ Sales Ofﬁces with Design

Fax: 612.921.8399

Resource Centers

To receive product literature, call us at 1-800-574-4286 (U.S. and Canada); +32.11.300.531 (Europe);

408.433.7700 (outside U.S., Canada, and Europe) and ask for Department JDS; or

visit us at http://www.lsilogic.com

ISO 9000 Certified

This document is preliminary. As such, it contains data

derived from functional simulations and performance esti-

mates. LSI Logic has not veriﬁed the functional descriptions

or electrical and mechanical speciﬁcations using production

parts.

LSI Logic Corporation reserves the right to make changes

to any products and services herein at any time without

notice. LSI Logic does not assume any responsibility or lia-

bility arising out of the application or use of any product or

service described herein, except as expressly agreed to in

writing by LSI Logic; nor does the purchase, lease, or use

of a product or service from LSI Logic convey a license

under any patent rights, copyrights, trademark rights, or any

other of the intellectual property rights of LSI Logic or of

third parties.

Printed on

Recycled Paper

Printed in USA

Order No. I15015.A

LSI Logic logo design and CoreWare are registered trade-

marks of LSI Logic Corporation. All other brand and product

names may be trademarks of their respective companies.

Doc. No. DB08-000006-01


型号：	L64767
厂家：	ETC
描述：	L64767 SMATV QAM Encoder data sheet 4/97 L64767 SMATV QAM编码器数据手册4/97\n 电视编码器
文件：	总32页 (文件大小：293K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L64767 [ETC]

相关型号：

L64767MC

L64767WE

L64777

L64780

L64781

L64782

L6480

L64801GC-20

L64801GC-25

L64801GM-20

L64801NC-20

L64801NC-25