L84225_技术文档

®

L84225100BaseTX/FX/10BaseT

Physical Layer Device

Technical Manual

Features

•

Single-chip 100BaseTX/100BaseFX/

10BaseT physical layer solution

•

Meets all applicable IEEE 802.3,

10BaseT, 100BaseTX and 100BaseFX

standards

•

Four independent Channels in One IC

3.3 V power supply with 5 V tolerant I/O

Dual Speed - 10/100 Mbps

On-chip wave shaping - no external

ﬁlters required

•

Adaptive Equalizer for 100BaseTX

Baseline Wander Correction

LED outputs

Half and Full Duplex

MII interface or reduced pin count MII

(RMII) interface to Ethernet Controller

–

Link, Activity, Collision

Full Duplex

•

MI interface for conﬁguration and status

Optional Repeater Interface

Far End Fault (for FX)

10/100

AutoNegotiation for 10/100, Full/Half

Duplex hardware controlled

•

160L PQFP

Contents

Description - - - - - - - - - - - - - - - - - - - - - 2 Speciﬁcations - - - - - - - - - - - - - - - - - - - 87

Pin Description - - - - - - - - - - - - - - - - - - 4 Ordering Information - - - - - - - - - - - - - 114

Functional Description - - - - - - - - - - - - -13 Revision History - - - - - - - - - - - - - - - - 114

Register Description- - - - - - - - - - - - - - -57 Surface Mount Packages- - - - - - - - - - 117

Application Information- - - - - - - - - - - - -70

Note:

Check for the latest revision of this document before start-

ing any designs. This document is available on the Web, at

www.lsilogic.com

MD400183/B

April, 2002

1 of 118

Description

The L84225 is a highly integrated Ethernet Transceiver for twisted pair

and ﬁber Ethernet applications. The L84225 can be conﬁgured for either

100 Mbps (100BaseFX or 100BaseTX) or 10 Mbps (10BaseT) Ethernet

operation.

The L84225 consists of four (4) separate and independent channels.

Each channel consists of: 4B5B/Manchester encoder, scrambler,

transmitter with wave shaping and on-chip ﬁlters, transmit output driver,

receiver with adaptive equalizer, ﬁlters, baseline wander correction, clock

and data recovery, descrambler, 4B5B/Manchester decoder, and

controller interface (MII or RMII).

The addition of internal output waveshaping circuitry and on-chip ﬁlters

eliminates the need for external ﬁlters normally required in 100BaseTX

and 10BaseT applications.

The L84225 can automatically conﬁgure itself for 100 or 10 Mbps and

Full or Half Duplex operation, for each channel independently, using the

on-chip AutoNegotiation algorithm.

The L84225 can access eleven 16-bit registers for each channel through

the Management Interface (MI) serial port. These registers comply with

Clause 22 of IEEE 802.3u and contain conﬁguration inputs, status

outputs, and device capabilities.

The L84225 is ideal as a media interface for 100BaseTX/

100BaseFX/10BaseT switching hubs, repeaters, routers, bridges, and

other multi port applications.

The L84225 is implemented in a low power CMOS technology and

operates with a 3.3V power supply.

2 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Pin Conﬁguration

LED0_3

LED1_3

LED2_3

LED0_2

LED1_2

LED2_2

GND

LED0_1

LED1_1

LED2_1

LED0_0

LED1_0

LED2_0

GND

1

2

3

4

5

6

7

8

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

SPEED_3

SPEED_2

CLKIN

LED3_3

LED3_2

LED3_1

LED3_0

SPEED_1

SPEED_0

ANEG

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

LEDDEF

RESET

GND

VDD

DPLX_0

DPLX_1

DPLX_2

DPLX_3

REPEATER

RMII_EN

VDD

MDC

REGDEF

MDIO

AD_REV

PHYAD2

PHYAD3

PHYAD4

GND

L84225

160 PQFP

Top View

VDD

RXD3_0

RXD2_0

RXD1_0

RXD0_0

RXDV_0

RXCLK_0

RXER_0/RXD4_0

TXER_0/TXD4_0

TXCLK_0

TXEN_0

TXD0_0

TXD1_0

TXD2_0

TXD3_0

COL_0

VDD

GND

CRS_3

COL_3

TXD3_3

TXD2_3

TXD1_3

TXD0_3

TXEN_3

TXCLK_3

TXER_3/TXD4_3

RXER_3/RXD4_3

RXCLK_3

RXDV_3

RXD0_3

RXD1_3

CRS_0

GND

VDD

82

81

Description

3 of 118

April, 2002

1 Pin Description

Pin Description

Power Supplies

Pin #

Pin Name

I/O

Description

Positive Supply. +3.3 5%Volts.

15

16

VDD

---

22

40

41

60

78

96

100

107

125

128

132

135

144

147

151

154

7

GND

---

Ground. 0 Volts.

14

21

39

56

59

77

95

108

121

122

127

131

134

141

146

150

153

160

4 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Pin Description (Cont.)

Media Interface

Pin # Pin Name

I/O

Description

126

136

145

155

TPOP_[3:0]/

FXIN_[3:0]

I/O

Twisted Pair Transmit Output, Positive.

Fiber Receive Input, Negative.

129

133

148

152

TPON_[3:0]/

FXIP_[3:0]

I/O

I

Twisted Pair Transmit Output, Negative.

Fiber Receive Input, Positive.

123

139

142

158

TPIP_[3:0]/

FXOP_[3:0]

Twisted Pair Receive Input, Positive.

Fiber Transmit Output, Positive.

124

138

143

157

TPIN_[3:0]/

FXON_[3:0]

Twisted Pair Receive Input, Negative.

Fiber Transmit Output, Negative.

130

137

149

156

SD_[3:0]/

FXEN_[3:0]

Fiber Interface Signal Detect Input.

Fiber Interface Enable.

When this pin in not tied to GND, the ﬁber interface is enabled and

this pin becomes a Signal Detect ECL input. The trip point for this

ECL input is determined by the voltage applied to the SD_THR

pin. When this pin is tied to GND, the ﬁber interface is disabled

(i.e., TP Interface is enabled).

159

140

SD_THR

REXT

---

Fiber Interface Signal Detect Threshold Reference.

The voltage applied to this pin sets the reference level for the ﬁber

interface SD input pin so that the device can directly connect SD

pin to both 3.3V and 5V ﬁber optic transceivers. Typically, this pin

is either tied to GND (for 3.3V) or to an external voltage divider (for

5V).

Transmit Current Set.

An external resistor connected between this pin and GND will set

the level for the transmit outputs.

Pin Description

5 of 118

April, 2002

Pin Description (Cont.)

Controller Interface (MII & RMII)

Pin # Pin Name

I/O

Description

87

69

50

31

TXCLK_[3:0]

TXEN_[3:0]

O

Transmit Clock Output. These interface outputs provide clocks to

external controllers. Transmit data from the controller on TXD,

TXEN, and TXER is clocked in on the rising edges of TXCLK and

CLKIN.

88

70

51

32

I

Transmit Enable Input. These interface inputs must be asserted

active high to allow data on TXD and TXER to be clocked in on

the rising edges of TXCLK and CLKIN.

[92:89] TXD[3:0]_3

[74:71] TXD[3:0]_2

[55:52] TXD[3:0]_1

[36:33] TXD[3:0]_0

Transmit Data Input. These interface inputs contain input nibble

data to be transmitted on the TP or FX outputs and are clocked in

on rising edges of TXCLK and CLKIN. In RMII mode, only

TXD[1:0] are used.

86

68

49

30

TXER_[3:0]/

TXD4_[3:0]

Transmit Error Input. These interface inputs initiate an error pat-

tern to be transmitted on the TP or FX outputs and are clocked in

on rising edges of TXCLK when TXEN is asserted.

If the channel is placed in the Bypass 4B5B Encoder mode, these

pins are reconﬁgured to be the ﬁfth TXD transmit data input,

TXD4. In RMII mode, these pins are not used.

84

66

47

28

RXCLK_[3:0]

CRS_[3:0]

O

Receive Clock Output. These interface outputs provide a clock to

the controller. Receive data on RXD, RXDV, and RXER is clocked

out to the controller on falling edges of RXCLK.

94

76

58

38

Carrier Sense Output. These interface outputs are asserted

active high when valid data is detected on the receive TP or FX

inputs and is clocked out on the falling edge of RXCLK.

83

65

46

27

RXDV_[3:0]

Receive Data Valid Output. These interface outputs are asserted

active high when valid decoded data is present on the RXD out-

puts and is clocked out on falling edges of RXCLK. In RMII mode,

these pins are not used.

[79:82] RXD[3:0]_3

[61:64] RXD[3:0]_2

[42:45] RXD[3:0]_1

[23:26] RXD[3:0]_0

Receive Data Output. These interface outputs contain recovered

nibble data from the TP or FX inputs and are clocked out on the

falling edges of RXCLK. In RMII mode, only RXD[1:0] are used.

6 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Pin Description (Cont.)

Controller Interface (MII & RMII) [Continued]

Pin # Pin Name

I/O

Description

85

67

48

29

RXER_[3:0]/

RXD4_[3:0]

O

Receive Error Output. These interface outputs are asserted

active high when coding or other speciﬁed errors are detected on

the TP or FX inputs and are clocked out on falling edges of

RXCLK.

If the channel is placed in the Bypass 4B5B Decoder mode, these

pins are reconﬁgured to be the ﬁfth RXD receive data output,

RXD4.

93

75

57

37

COL_[3:0]

O

Collision Output. These interface outputs are asserted active

high when collision between transmit and receive data is detected.

Management Interface (MI)

Pin # Pin Name I/O

Description

99

97

MDC

I

Management Interface (MI) Clock Input. This MI clock shifts

serial data into and out of MDIO on rising edges.

MDIO

I/O

Management Interface (MI) Data Input/Output. This bidirectional

pin contains serial data that is clocked in and out on rising edges

of the MDC clock.

98

REGDEF

I

Invalid Register Read Select This active low input controls the

Pullup default values that are read from invalid (unused) register

locations.

1 = All unused register locations return a value of ‘0000’ when

read.

0 = All unused register locations return a value of ‘ffff’ when read.

Note: Not available on Rev. B product. On Rev. B product all

invalid register locations return a value of ‘0000’ when read.

20

19

18

PHYAD[4:2]

I

MI Physical Device Address Input. These pins set the three

most signiﬁcant bits of the PHY address. The two least signiﬁcant

bits of the PHY address are set internally to match the channel

number, as shown below:

PHYAD1

PHYAD0

Channel 3

Channel 2

Channel 1

Channel 0

1

0

1

0

1

0

Pin Description

7 of 118

April, 2002

Pin Description (Cont.)

LED Drivers

Pin # Pin Name

I/O

Description

117

116

115

114

LED3_[3:0]

LED2_[3:0]

LED1_[3:0]

LED0_[3:0]

LEDDEF

O

LED Output. The default functions of these pins are 100 Mbps

Link Detect outputs assuming LEDDEF = 0. These pins can drive

an LED from both VDD and GND.

Please refer to Table 2 for LED description

3

6

10

13

O

I

LED Output. The default functions of these pins are Activity

Detect outputs assuming LEDDEF = 0. These pins can drive an

LED from both VDD and GND.

Please refer to Table 2 for LED description

2

5

9

LED Output. The default functions of these pins are Full Duplex

Detect outputs assuming LEDDEF = 0. These pins can drive an

LED from both VDD and GND.

12

Please refer to Table 2 for LED description

1

4

8

LED Output. The default functions of these pins are 10 Mbps Link

Detect outputs assuming LEDDEF = 0. These pins can drive an

LED from both VDD and GND.

11

Please refer to Table 2 for LED description.

110

LED Default Select Input. This pin changes the default selection

for the LEDs in the MI Serial Port Global Conﬁguration Register.

1 = LINK + ACT, COL, FDX, 10/100

0 = LINK100, ACT, FDX, LNK10

8 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Pin Description (Cont.)

Miscellaneous

Pin # Pin Name

I/O

Description

111

ANEG

I

AutoNegotiation Enable Input. This digital input, ANDed with

register bit 0.12, enables AutoNegotiation for all channels.

1 = AutoNegotiation On & Combined with Speed and Duplex pins,

control advertisement. See Table 1 for the different combinations.

0 = Off

120

119

113

112

SPEED_[3:0]

DPLX_[3:0]

I

Speed Selection Input. These digital inputs, ANDed with register

bit 0.13, select speed in each corresponding channel. Please refer

to Table 1 for the different combinations.

1 = 100 Mbps Mode

0 = 10 Mbps Mode

103

104

105

106

Duplex Selection Input. These digital inputs, ORed with register

bit 0.8, select the duplex mode in EACH corresponding channel.

They control advertisement when ANEG is enabled. See Table 1

for the different combinations.

1 = Full Duplex Mode

0 = Half Duplex Mode

102

REPEATER

I

Repeater Mode Enable Input. This digital input, ORed with reg-

ister bit 17.14, enables repeater mode for ALL channels.

1 = Repeater Mode Enabled

0 = Normal Operation

101

17

RMII_EN

AD_REV

I

Reduced Pin Count MII Interface Enable.

1 = RMII Mode Enabled

0 = MII Enabled

Address Reverse Input.

Pullup 1 = Normal

In this mode, physical ports 0-3 are mapped to MI addresses 0-3

in the same order.

0 = Reverse Address Mode Select

In this mode, physical ports 0-3 are mapped to MI addresses 3-0

respectively. This is the reverse to the normal order.

118

109

CLKIN

I

Clock Input. In MII mode, there must be a 25 MHz clock input to

this pin. In RMII mode, there must be a 50 MHz clock input to this

pin. TXCLK is generated from the input to this pin.

RESET

Hardware Reset Input.

Pullup 1 = Normal

0 = Device In Reset State

(Reset is complete 50 ms after RESET goes high).

Pin Description

9 of 118

April, 2002

Table 1

AutoNegotiation, Speed & Duplex Mode Combinations

Input Pins

Mode Selected

Forced Modes [Note2] Advertised Capabilities

Speed

[3:0]

Duplx

[3:0]

Aneg

Autoneg

Speed

DPLX

Speed

DPLX

0

1

0000

1111

0000

1111

0000

1111

0000

1111

0000

1111

0000

1111

Off

On

10

Half

Full

Half

Full

na

100

na

10

Half

na

10

Half/Full

Half/Full [3]

Half

na

10/100

na

Note 1: The single ANEG pin applies to all four channels. The four

Speed and DPLX apply to each individual channel. The pins above are

shown for all four channels, but each channel can be individually

conﬁgured for SPEED and DPLX by appropriately setting the pin for that

channel.

Note 2: Forced Modes assume that registers 0 and 4 are at default

values.

Note 3: the L84225 can be controlled either through the software or

through the hardware. If the device needs to be controlled through the

software (Registers 0 to 4), then these seven pins (ANEG, Speed[3:0],

Duplx[3:0]) have to be tied to their default values of 1, 1111, and 0000,

respectively.

10 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 2

Name

LED Deﬁnitions as per the LEDDEF Pin

Output State Description

LEDtied LEDtied

to GND

to Vdd LEDDEF

LED0¹

0 = 100 Mbps Link Detected

1 = 10 Mbps Link Detected

3-state = No Link

Off

On

Off

On

Off

On

Off

Blink

On

Off

On

Off

On

Off

On

Off

On

Off

On

Off

On

Blink

Off

On

Off

On

Off

On

LEDDEF = 1

(10/100)

LED1

0 = Full Duplex Mode Detect with Link Pass

1 = Half Duplex Mode Detect with Link Pass

3-state = No Link

(Fdx/Hdx)

LED2

(Col)

0 = Collision Detect

1 = No Collision

LED3

0 = Link Detect

(Link + Act) Blink = Link Detect + Activity

1 = No Link Detect or Activity

LED0¹

0 = 10 Mbps Link Detected

LEDDEF = 0

(Link10)

LED1

1 = No 10 Mbps Link Detected

0 = Full Duplex Mode Detect with Link Pass

1 = Half Duplex Mode Detect with Link Pass

3-state = No Link

(Fdx/Hdx)

LED2

Blink = Activity Occurred

(Stretch pulse to 100 ms)

(Act)

1 = No Activity

0 = Link100 Detected

1 = No Link100

Detected

On

Off

On

Off

On

Off

LED3

(Link100)

1. LED 0 becomes FEF when FX Interface is enabled.

0 = FEF detected

1 = No FEF detected

Pin Description

11 of 118

April, 2002

2 Functional Description

2.1 General

The L84225 is a complete 10/100 Mbps Ethernet Media Interface IC. The

L84225 has four separate and independent channels. Each channel has

the following main sections: controller interface, encoder, decoder,

scrambler, descrambler, clock and data recovery, twisted pair and ﬁber

interface transmitter, twisted pair and ﬁber interface receiver, and auto

negotiation. A Management Interface (MI) serial port, which provides

access to eleven registers for each channel, is common to all four

channels. Figure 1 shows the L84225 block diagram.

The L84225 can operate as a 100BaseTX or 100BaseFX device (100

Mbps mode) or as a 10BaseT device (10 Mbps mode). The 100 Mbps

and 10 Mbps modes differ in data rate, signaling protocol, and allowed

wiring as follows:

•

The 100 Mbps FX mode uses two ﬁber connections with 4B5B

encoded NRZI 125 MHz binary data through an ECL-type driver to

achieve a throughput of 100 Mbps.

The 100 Mbps TX mode uses two pairs of category 5, or better, UTP

or STP twisted pair cable with 4B5B encoded, scrambled, and MLT3

coded (ternary) 125 MHz data to achieve a throughput of 100 Mbps.

The 10 Mbps mode uses two pairs of category 3, or better, UTP or

STP twisted pair cable with Manchester encoded 10 MHz binary data

to achieve a 10 Mbps thruput.

The data symbol format on the ﬁber or twisted pair cable for the 100 and

10 Mbps modes is deﬁned in IEEE 802.3 speciﬁcations and shown in

Figure 2.

Functional Description

13 of 118

April, 2002

Figure 2

Frame Format

Ethernet MAC Frame

SFD DA SA

Interframe

GAP

Interframe

GAP

LLC Data

PREAMBLE

LN

FCS

100 Base-TX Data Symbols

IDLE

SSD PREAMBLE

SFD

DA

SA

LLC DATA FCS ESD IDLE

[ 1 1 1 1 ...]

[ 1 1 0 0 0 1 0 0 0 1 ]

[ 1 0 1 0 ...] 62 Bits Long

[ 1 1 ]

[ DATA ]

IDLE =

SSD =

Before/After

4B5B Encoding,

Scrambling, and

MLT3 Coding

PREAMBLE =

SFD =

DA, SA, LN, LLC DATA, FCS =

ESD =

[ 0 1 1 0 1 0 0 1 1 1 ]

100 Base-FX Data Symbols

SSD PREAMBLE

SFD

DA

SA

LN

LLC DATA FCS ESD IDLE

[ 1 1 1 1 ...]

[ 1 1 0 0 0 1 0 0 0 1 ]

[ 1 0 1 0 ...] 62 Bits Long

[ 1 1 ]

[ DATA ]

IDLE =

SSD =

Before/After

4B5B Encoding

PREAMBLE =

SFD =

DA, SA, LN, LLC DATA, FCS =

ESD =

[ 0 1 1 0 1 0 0 1 1 1 ]

10 Base-T Data Symbols

SFD DA SA

PREAMBLE

LN

LLC DATA FCS SOI

IDLE

[ NoTransitions ]

IDLE =

[ 1 0 1 0 ...] 62 Bits Long

[ 1 1 ]

PREAMBLE =

SFD =

DA, SA, LN, LLC DATA, FCS =

Before/After

Manchester

Encoding

[ DATA ]

[ 1 1 ] With No MID Bit

Transition

SOI =

On the transmit side for 100 Mbps operation, data is received on the

controller interface from an external Ethernet controller per the format

shown in Figure 3. The data is sent to the encoder for formatting. For TX

operation, the encoded data is sent to the scrambler. The encoded and

scrambled data is then sent to the TX transmitter. The transmitter

converts the encoded and scrambled data into MLT3 ternary format. The

transmitter then pre-shapes the output and drives the twisted pair cable.

14 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

For FX operation, the encoded data is converted to NRZI format, which

drives a binary (two-level) signal to the ﬁber transceiver interface (PMD).

On the receive side for 100BaseTX operation, the TX receiver removes

any high frequency noise from the input, equalizes the input signal to

compensate for the low pass effects of the cable, and qualiﬁes the data

with a squelch algorithm. The TX receiver then converts the data from

MLT3 coded twisted pair levels to internal digital levels. The output of the

receiver then goes to a clock and data recovery block which recovers a

clock from the incoming data, uses the clock to latch in valid data into

the device, and converts the data back to NRZ data. The data is then

unscrambled and decoded by the 4B5B decoder and descrambler,

respectively, and output to an external Ethernet controller by the

controller interface. 100Base FX receiver operation is the same as TX

except there is no equalizer, descrambler, and has a separate ECL

receiver.

10 Mbps operation is similar to the 100 Mbps operation, except:

•

There is no scrambler/descrambler.

The encoder/decoder is Manchester instead of 4B5B.

The data rate is 10 Mbps instead of 100 Mbps.

The twisted pair symbol data is two level Manchester instead of

ternary MLT3.

The FX interface is disabled for 10 Mbps operation.

The AutoNegotiation block automatically conﬁgures each channel for

either 100BaseTX or 10BaseT, and either Full or Half Duplex operation.

This conﬁguration is based on the capabilities selected for the channel

and capabilities detected from the remote device connected to the

channel.

The Management Interface (the MI serial port) is a two-pin bidirectional

link through which conﬁguration inputs can be set and channel status

outputs read.

Each block plus the operating modes are described in more detail in the

following sections. Since the L84225 can operate as a 100BaseFX,

100BaseTX, or 10BaseT device, each of the following sections describes

the performance in both 100 and 10 Mbps modes.

Functional Description

15 of 118

April, 2002

2.2 Controller Interface

2.2.1 General

The L84225 has three interfaces to an external controller: Media

Independent Interface (MII), Reduced pin MII (RMII), and Five Bit

Interface (FBI). MII is the default interface. RMII is selected by asserting

the RMII_EN pin, a global control (all channels effected). FBI is selected,

on a per port basis, by setting the bypass encoder bit in the MI serial

port Channel Conﬁguration register (Register 17).

2.2.2 MII - 100 Mbps

The MII is a nibble-wide packet data interface deﬁned in IEEE 802.3. The

L84225 meets all MII requirements outlined in IEEE 802.3. The L84225

can directly connect, without external logic, to any Ethernet controller or

other device that also complies with the IEEE 802.3 MII speciﬁcation.

The MII frame format is shown in Figure 3.

16 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Figure 3

MII Frame Format

a. MII Frame Format

TXEN = 1

TX_EN = 0

IDLE

TXEN = 0

IDLE

Start of

Frame

PREAMBLE

PRMBLE

DATA Nibbles

SFD

DATA 1 DATA 2 DATA N-1 DATA N

62 Bits

2 Bits

PREAMBLE = [ 1 0 1 0 ...] 62 Bits Long

SFD = [ 1 1 ]

DATAn = [Between 64−1518 Data Bytes]

IDLE = TXEN = 0

b. MII Nibble Order

First Bit

LSB

First

Nibble

MACs Serial Bit Stream

D0

D1

D2

D3

D4

D5

D6

D7

MSB

Second

Nibble

TXD0/RXD0

TXD1/RXD1

TXD2/RXD2

TXD3/RXD3

MII

Nibble

Stream

c. Transmit Preamble and SFD Bits

Signals

Bit Value

1

2

3

TXD0

TXD1

TXD2

TXD3

TXEN

X

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D0 D4

D1 D5

D2 D6

D3 D7

0

1

0

1

0

1

1. 1st preamble nibble transmitted.

2. 1st SFD nibble transmitted.

3. 1st data nibble transmitted.

4. D0 thru D7 are the ﬁrst 8 bits of the data ﬁeld.

d. Receive Preamble and SFD Bits

Signals

Bit Value

1

2

3

RXD0

RXD1

RXD2

RXD3

RXDV

X

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D0 D4

D1 D5

D2 D6

D3 D7

0

1

0

1

0

1

1. 1st preamble nibble received. Depending on mode, device may eliminate either all or some of the preamble

nibbles, up to 1st SFD nibble.

2. 1st SFD nibble received.

3. 1st data nibble received.

4. D0 thru D7 are the ﬁrst 8 bits of the data ﬁeld.

Functional Description

17 of 118

April, 2002

The MII consists of four transmit data bits (TXD[3:0]), transmit clock

(TXCLK), transmit enable (TXEN), transmit error (TXER), four receive

data bits (RXD[3:0]), receive clock (RXCLK), carrier sense (CRS),

receive data valid (RXDV), receive data error (RXER), and collision

(COL). The transmit clock (TXCLK) is a common signal for all four

channels. All other signals are separate for each channel. The transmit

and receive clocks operate at 25 MHz in 100 Mbps mode.

On the transmit side, the TXCLK output runs continuously at 25 MHz.

When no data is to be transmitted, TXEN must be deasserted. While

TXEN is deasserted, TXER and TXD[3:0] are ignored and no data is

clocked into the device. When TXEN is asserted on the rising edge of

TXCLK, data on TXD[3:0] is clocked into the device on rising edges of

the TXCLK output clock. TXD[3:0] input data is nibble wide packet data

whose format is speciﬁed in IEEE 802.3 and shown in Figure 3. When

all packet data has been latched into the device, TXEN must be

deasserted on the rising edge of TXCLK.

TXER is also clocked in on rising edges of the TXCLK clock. TXER is a

transmit error signal which, when asserted, will substitute an error nibble

in place of the normal data nibble that was clocked in on the TXD[3:0]

nibble at the same time as the TXER assertion. The error nibble is the

/H/ symbol, as deﬁned in IEEE 802.3 and shown in Table 3.

Since CLKIN (input clock) generates TXCLK (output clock), TXD[3:0],

TXEN, and TXER are also clocked in on the rising edges of CLKIN.

On the receive side, as long as a valid data packet is not detected, CRS

and RXDV are deasserted and RXD[3:0] is held low. When the start of

packet is detected, CRS is asserted on the falling edge of RXCLK. The

assertion of RXDV indicates that valid data is available on RXD[3:0].

Data may be externally latched using the rising edge of RXCLK. The

RXD[3:0] data has the same frame structure as the TXD[3:0] data,

speciﬁed in IEEE 802.3 and shown in Figure 3. When the end of packet

is detected, CRS and RXDV are deasserted, and RXD[3:0] is held low.

CRS and RXDV also stay deasserted if the channel is in Link Fail state.

RXER is a receive error output that is asserted when certain errors are

detected on a data nibble. RXER is asserted on the falling edge of

RXCLK for the duration of the RXCLK clock cycle during which the nibble

containing the error is output on RXD[3:0].

18 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

The collision output, COL, is asserted whenever the collision condition is

detected.

2.2.3 MII - 10Mbps

10 Mbps operation is identical to the 100 Mbps operation, except:

•

TXCLK and RXCLK clock frequency is 2.5 MHz.

TXER is ignored.

•

RXER is disabled and always held low.

Receive operation is modiﬁed as follows. On the receive side, when

the squelch circuit determines that invalid data is present on the TP

(Twisted Pair) inputs, the receiver is idle. During idle, RXCLK follows

TXCLK, RXD[3:0] is held low, and CRS and RXDV are deasserted.

When a start of packet is detected on the TP receive inputs, CRS is

asserted and the clock recovery process starts on the incoming TP

input data. After the receive clock has been recovered from the data,

the RXCLK is switched over to the recovered clock output and the

data valid signal RXDV is asserted on a falling edge of RXCLK. Once

RXDV is asserted, valid data is clocked out on RXD[3:0] on falling

edges of the RXCLK clock. The RXD[3:0] data has the same packet

structure as the TXD[3:0] data and is formatted as speciﬁed in IEEE

802.3 and shown in Figure 3. When the end of packet is detected,

CRS and RXDV are deasserted. CRS and RXDV also stay

deasserted as long as the channel is in the Link Fail State.

2.2.4 RMII - 100 Mbps

The RMII is a reduced pin count version of the MII deﬁned by an industry

group, the RMII Consortium. The RMII is a two-bit-wide packet data

interface that operates at 50 Mhz. The L84225 meets all the RMII

requirements outlined in the RMII Consortium speciﬁcations and can

directly connect to any Ethernet controller that also complies with the

RMII speciﬁcations.

The RMII is similar to the MII, except:

•

The data path is two bits wide instead of four.

Transmit and receive data is passed over TXD[1:0] and RXD[1:0]

pins, respectively.

Functional Description

19 of 118

April, 2002

•

The CLKIN clock frequency must be 50 MHz instead of 25 MHz.

All timing for both transmit and receive is referenced to a single clock

on CLKIN instead of TXCLK for transmit and RXCLK for receive.

•

An elastic buffer is present in the receive data path to account for

any difference between the CLKIN and receive data frequencies. The

elastic buffer is 32 bits in length. Input data from the receiver ﬁlls the

buffer to a predetermined threshold level before data is passed to the

RMII outputs. This threshold level can be conﬁgured to either 4 bits

or 16 bits by appropriately setting the RMII threshold select bit in the

MI serial port Global Conﬁguration register.

•

The MII RXDV and CRS inputs are combined into one signal that is

outputted on the CRS pin. CRS is asserted active high when

incoming packet data is detected on the receive inputs. It stays

asserted high until packet data is no longer detected, and it toggles

at a 25 MHz rate (low for ﬁrst di-bit of MII nibble, high for second,

etc.) from the end of the packet data detection until end of valid data

transfer from the elastic buffer. During this toggling interval, valid data

is still being output on RXD[1:0]. CRS is ﬁnally deasserted when all

data has been output from the internal elastic buffer on RXD[1:0].

•

RXD[1:0]=00 from start of CRS until valid data is ready to be output.

TXEN to CRS loopback is disabled.

Any packet that contains an error will assert RXER and substitute

RXD[1:0]=10 for all the data bits from the error detect point until the

end of packet.

2.2.5 RMII - 10 Mbps

10 Mbps RMII operation is identical to 100 Mbps RMII operation, except:

•

The CLKIN frequency remains at 50 Mhz (same as 100 Mbps

operation).

Each data di-bit must be input on TXD[1:0] for ten consecutive

CLKIN cycles.

Each data di-bit will be output on RXD[1:0] for ten consecutive

CLKIN cycles.

20 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

2.2.6 FBI - 100 Mbps

The Five Bit Interface (FBI), or Symbol Interface, is a ﬁve bit wide

interface produced when the 4B5B encoder/ decoder is bypassed. The

FBI is primarily used for repeaters or Ethernet controllers that have

integrated encoder/decoders.

The FBI is identical to the MII, except:

•

The FBI data path is ﬁve bits wide, not nibble wide like the MII.

TXER pin is changed to be the ﬁfth transmit data bit, TXD4.

RXER pin is changed to be the ﬁfth receive data bit, RXD4.

CRS is asserted as long as the device is in the Link Pass state (CRS

no longer asserted/deasserted at beginning/end of packet).

•

COL is not valid.

RXDV is not valid.

TXEN is ignored.

2.2.7 FBI - 10 Mbps

The FBI is not available in 10 Mbps mode.

2.2.8 Selection of MII, RMII, or FBI

MII is the default interface to the MAC controller. RMII is selected by

asserting the RMII_EN pin, a global control.

The FBI is automatically enabled when the 4B5B encoder/ decoder is

bypassed. Bypassing the encoder/decoder passes the 5B symbols

between the receiver/transmitter directly to the FBI without any alteration

or substitutions. The 4B5B encoder/decoder can be bypassed by setting

the bypass encoder bit in the MI serial port Channel Conﬁguration

register.

When the FBI is enabled, it may also be desirable to bypass the

scrambler/descrambler and disable the internal CRS loopback function.

The scrambler/ descrambler can be bypassed by setting the bypass

scrambler bit in the MI serial port Channel Conﬁguration register. The

internal CRS loopback can be disabled by setting the TXEN to CRS

loopback disable bit in the MI serial port Channel Conﬁguration register.

Functional Description

21 of 118

April, 2002

2.2.9 MII Disable

The MII and FBI inputs and outputs can be disabled by setting the MII

disable bit in the MI serial port Control register. When the MII is disabled,

the inputs are ignored, the outputs are placed in high impedance state,

and the TP output is high impedance.

2.2.10 TXEN to CRS Loopback Disable

The internal TXEN to CRS loopback can be disabled by appropriately

setting the TXEN to CRS loopback disable bit in the MI serial port

Channel Conﬁguration register. TXEN to CRS loopback is disabled in

RMII mode.

2.3 Encoder

2.3.1 4B5B Encoder - 100 Mbps

100BaseTX and 100BaseFX require that the data be 4B5B encoded.

4B5B coding converts the 4-bit data nibbles into 5-bit data words. The

mapping of the 4B nibbles to the 5B code words is speciﬁed in IEEE

802.3 and shown in Table 3. The 4B5B encoder on the L84225 takes 4B

nibbles from the controller interface, converts them into 5B words

according to Table 3, and sends the 5B words to the scrambler. The

4B5B encoder also substitutes the ﬁrst eight bits of the preamble with the

SSD delimiters (/J/K/ symbols) and adds an ESD delimiter (/T/R/

symbols) to the end of each packet, as deﬁned in IEEE 802.3 and shown

in Figure 2. The 4B5B encoder also ﬁlls the period between packets,

called the idle period, with a continuous stream of idle symbols, as

shown in Figure 2.

Table 3

4B/5B Symbol Mapping

Symbol Name

Description

5B Code

4B Code

0

1

2

3

4

Data 0

Data 1

Data 2

Data 3

Data 4

11110

01001

10100

10101

01010

0000

0001

0010

0011

0100

22 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 3

4B/5B Symbol Mapping (Cont.)

Symbol Name

Description

5B Code

4B Code

5

6

Data 5

Data 6

Data 7

Data 8

Data 9

Data A

Data B

Data C

Data D

Data E

Data F

01011

01110

01111

10010

10011

10110

10111

11010

11011

11100

11101

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

7

8

9

A

B

C

D

E

F

I

Idle

11111

0000

J

K

T

R

H

SSD #1

SSD #2

ESD #1

ESD #2

Halt

11000

10001

01101

00111

00100

0101

0000

Undeﬁned

---

Invalid codes

All others¹

0000¹

1. These 5B codes are not used. For decoder, these 5B codes are

decoded to 4B 0000. For encoder, 4B 0000 is encoded to 5B

11110, as shown in symbol Data 0.

Functional Description

23 of 118

April, 2002

2.3.2 Manchester Encoder - 10 Mbps

The Manchester encoding process combines clock and NRZ data such

that the ﬁrst half of the data bit contains the complement of the data, and

the second half of the data bit contains the true data, as speciﬁed in

IEEE 802.3. This guarantees that a transition always occurs in the middle

of the bit cell. The L84225 Manchester encoder converts the 10 Mbps

NRZ data from the controller interface into a single data stream for the

TP transmitter and adds a start of idle pulse (SOI) at the end of the

packet as speciﬁed in IEEE 802.3 and shown in Figure 2. The

Manchester encoding process is only done on actual packet data, and

the idle period between packets is not Manchester encoded, but ﬁlled

with link pulses.

2.3.3 Encoder Bypass

The 4B5B encoder can be bypassed by setting the bypass

encoder/decoder bit in the MI serial port Channel Conﬁguration register.

When this bit is set to bypass the encoder/decoder, 5B code words are

passed directly from the controller interface to the scrambler without any

alterations. Setting this bit automatically places the device in the FBI

mode, as described in Section 2.2, “Controller Interface,” page 16.

2.4 Decoder

2.4.1 4B5B Decoder - 100 Mbps

Since the FX or TX input data is 4B5B encoded on the transmit side, it

must also be decoded by the 4B5B decoder on the receive side. The

mapping of the 5B nibbles to the 4B code words is speciﬁed in IEEE

802.3 and shown in Table 3. The L84225 4B5B decoder takes the 5B

code words from the descrambler, converts them into 4B nibbles per

Table 3, and sends the 4B nibbles to the controller interface. The 4B5B

decoder also strips off the SSD delimiter (/J/K/ symbols) and replaces

them with two 4B Data 5 nibbles (/5/ symbol), and strips off the ESD

delimiter (/T/R/ symbols) and replaces it with two 4B Data 0 nibbles (/I/

symbol), per IEEE 802.3 speciﬁcations and shown in Figure 2.

The 4B5B decoder detects SSD, ESD and, codeword errors in the

incoming data stream as speciﬁed in IEEE 802.3. These errors are

indicated by asserting RXER output while the errors are being

transmitted across RXD[3:0], and they are also indicated by setting SSD,

24 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

ESD, and codeword error bits in the MI serial port Channel Status Output

register.

2.4.2 Manchester Decoder - 10 Mbps

In Manchester coded data, the ﬁrst half of the data bit contains the

complement of the data, and the second half of the data bit contains the

true data. The L84225 Manchester decoder converts the single data

stream from the TP receiver into NRZ data for the controller interface by

decoding the data and stripping off the SOI pulse. Since the clock and

data recovery block has already separated the clock and data from the

TP receiver, the Manchester decoding process to NRZ data is inherently

performed by that block.

2.4.3 Decoder Bypass

The 4B5B decoder can be bypassed by setting the bypass

encoder/decoder bit in the MI serial port Channel Conﬁguration register.

When this bit is set to bypass the encoder/decoder:

•

5B code words are passed directly to the controller interface from the

descrambler without any alterations.

CRS is asserted whenever the device is in the Link Pass state.

2.5 Clock and Data Recovery

2.5.1 Clock Recovery - 100 Mbps

Clock recovery is done with a PLL. If there is no valid data present on

the receive inputs, the PLL is locked to the 25 MHz TXCLK. When valid

data is detected on the receive inputs with the squelch circuit and when

the adaptive equalizer has settled, the PLL input is switched to the

incoming data stream. The PLL then recovers a clock by locking onto the

transitions of the incoming signal. The recovered clock frequency is a 25

MHz nibble clock, and that clock is output as the controller interface

signal RXCLK.

For FX operation, when the SD pin is asserted, the PLL input is switched

to the incoming data on the input.

Functional Description

25 of 118

April, 2002

2.5.2 Data Recovery - 100 Mbps

Data recovery is performed by latching in data from the receive inputs

with the recovered clock extracted by the PLL. The data is then

converted from a single bit stream into a nibble widedone by latching in

valid data from the receiver with the recovered clock extracted by the

PLL. The data is then converted from a single bit stream into a nibble-

wide data word.

2.5.3 Clock Recovery - 10 Mbps

The clock recovery process for 10 Mbps mode is identical to the 100

Mbps mode, except:

•

The recovered clock frequency is a 2.5 MHz nibble clock.

The PLL is switched from TXCLK to the TP input when the squelch

indicates valid data.

•

The PLL locks onto the preamble signal in less than 12 transitions

(bit times).

Some of the preamble data symbols are lost while the PLL is locking

onto the preamble. However, the data receiver block recovers

enough preamble symbols to pass at least 6 nibbles of preamble to

the controller interface, as shown in Figure 3.

2.5.4 Data Recovery

The data recovery process for 10 Mbps mode is identical to the 100

Mbps mode, except, the recovered clock frequency is a 2.5 MHz nibble

clock. As mentioned in Section 2.4.2, “Manchester Decoder - 10 Mbps,”

page 25, the data recovery process inherently performs decoding of

Manchester encoded data from the TP inputs.

2.6 Scrambler

2.6.1 100 Mbps

100BaseTX requires scrambling to reduce the radiated emissions on the

twisted pair. The L84225 scrambler takes the encoded data from the

4B5B encoder, scrambles it per the IEEE 802.3 speciﬁcations, and sends

it to the TP transmitter. The scrambler circuitry of the L84225 is designed

26 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

so that none of the individual scrambler sections on-chip will be

synchronous with the others to minimize EMI issues.

2.6.2 10 Mbps

A scrambler is not used in 10 Mbps mode.

2.6.3 Scrambler Bypass

The scrambler can be bypassed by setting the bypass

scrambler/descrambler bit in the MI serial port Channel Conﬁguration

register. When this bit is set, the 5B data bypasses the scrambler and

goes directly from the 4B5B encoder to the twisted pair transmitter.

2.7 Descrambler

2.7.1 100 Mbps

The L84225 descrambler takes the scrambled data from the data

recovery block, descrambles it per the IEEE 802.3 speciﬁcations, aligns

the data on the correct 5B word boundaries, and sends it to the 4B5B

decoder.

The algorithm for synchronization of the descrambler is the same as the

algorithm outlined in the IEEE 802.3 speciﬁcation. Once the descrambler

is synchronized, it will maintain synchronization as long as enough

descrambled idle pattern 1’s are detected within a given interval. To stay

in synchronization, the descrambler needs to detect at least 25

consecutive descrambled idle pattern 1’s in a 1 ms interval. If 25

consecutive descrambled idle pattern 1’s are not detected within the 1

ms interval, the descrambler goes out of synchronization and restarts the

synchronization process.

If the descrambler is in the unsynchronized state, the descrambler loss

of synchronization detect bit is set in the MI serial port Channel Status

Output register to indicate this condition. Once this bit is set, then it will

stay set until the descrambler achieves synchronization.

A descrambler is not used for FX operation.

Functional Description

27 of 118

April, 2002

2.7.2 10 Mbps

A descrambler is not used in 10 Mbps mode.

2.7.3 Descrambler Bypass

The descrambler can be bypassed by setting the bypass

scrambler/descrambler bit in the MI serial port Channel Conﬁguration

register. When this bit is set, the data bypasses the descrambler and

goes directly from the TP receiver to the 4B5B decoder.

2.8 Twisted Pair Transmitter

2.8.1 100 Mbps

The TP transmitter consists of an MLT3 encoder, waveform generator,

and line driver.

The MLT3 encoder converts the NRZI data from the scrambler into a

three level code required by IEEE 802.3. MLT3 coding uses three levels

and converts 1's to transitions between the three levels, and converts 0's

to no transitions or changes in level.

The purpose of the waveform generator is to shape the transmit output

pulse. The waveform generator takes the MLT3 three level encoded

waveform and uses an array of switched current sources to control the

shape of the twisted pair output signal in order to meet IEEE 802.3

requirements. The output of the switched current sources then goes

through a low pass ﬁlter in order to "smooth" the output and remove any

high frequency components. In this way, the waveform generator pre-

shapes the output waveform transmitted onto the twisted pair cable to

meet the pulse template requirements outlined in IEEE 802.3. The

waveform generator eliminates the need for any external ﬁlters on the TP

transmit output. The line driver converts the shaped and smoothed

waveform to a current output that can drive 100 meters of category 5

unshielded twisted pair cable or 150 ohm shielded twisted pair cable.

2.8.2 10 Mbps

The TP transmitter operation in 10 Mbps mode is much different from the

100 Mbps transmitter. Even so, the transmitter still consists of a

waveform generator and line driver.

28 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

The purpose of the waveform generator is to shape the output transmit

pulse. The waveform generator consists of a ROM, DAC, clock generator,

and ﬁlter. The DAC generates a stair-stepped representation of the

desired output waveform. The stairstepped DAC output then goes

through a low pass ﬁlter in order to "smooth" the DAC output and remove

any high frequency components. The DAC values are determined from

the ROM output; the ROM outputs are chosen to shape the pulse to the

desired template and are clocked into the DAC at high speed by the clock

generator. In this way, the waveform generator pre-shapes the output

waveform to be transmitted onto the twisted pair cable to meet the pulse

template requirements outlined in IEEE 802.3 Clause 14 and also shown

in Figure 4. The waveshaper replaces and eliminates external ﬁlters on

the TP transmit output.

The line driver converts the shaped and smoothed waveform to a current

output that can drive 100 meters of category 3/4/5 100 Ohm unshielded

twisted pair cable or 150 Ohm shielded twisted pair cable, without any

external ﬁlters. During the idle period, no output signal is transmitted on

the TP outputs (except link pulse).

2.9 Twisted Pair Receiver

2.9.1 Receiver - 100 Mbps

The TP receiver detects input signals from the twisted pair input and

converts it to a digital data bit stream ready for clock and data recovery.

The receiver can reliably detect data from a 100Base-TX compliant

transmitter that has been passed through 0-100 meters of 100-Ohm

category 5 UTP.

The 100 Mbps receiver consists of an adaptive equalizer, baseline

wander correction circuit, comparators, and MLT- 3 decoder. The TP

inputs ﬁrst go to an adaptive equalizer. The adaptive equalizer

compensates for the low pass characteristic of the cable, and it has the

ability to adapt and compensate for 0-100 meters of category 5, 100

Ohm UTP. The baseline wander correction circuit restores the DC

component of the input waveform that was removed by external

transformers. The comparators convert the equalized signal back to

digital levels and are used to qualify the data with the squelch circuit. The

MLT-3 decoder takes the three level MLT-3 digital data from the

Functional Description

29 of 118

April, 2002

comparators and converts it back to normal digital data to be used for

clock and data recovery.

Figure 4

TP Output Voltage Template

B

N

1.0

0.8

0.6

0.4

0.2

P

H

I

O

D

E

C

Q

R

0.0

- 0.2

- 0.4

- 0.6

- 0.8

- 1.0

A

M

J

F

S

U

L K

W

V

T

G

0

10

20

30

40

50

60

70

80

90

100

110

Time (ns)

Internal MAU

Time (ns)

Internal MAU Voltage (V)

Reference

Voltage (V)

Reference

A

B

C

D

E

F

G

H

I

0

1.0

0.4

0.55

0.45

0

M

N

O

P

61

0

15

25

32

39

57

48

67

89

74

73

85

1.0

100

110

111

110

100

110

90

0.4

0.75

0.15

0

Q

R

S

-1.0

0.7

0.6

0

-0.15

-1.0

-0.3

-0.7

T

U

V

J

K

L

-0.55

W

30 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

2.9.2 Receiver - 10 Mbps

The 10 Mbps mode receiver is much simpler than the 100 Mbps mode

receiver and is identical to the 100 Mbps receiver except:

•

The adaptive equalizer is disabled and bypassed.

The baseline wander correction circuit is disabled.

The 10 Mbps receiver is able to detect input signals from the twisted

pair cable that are within the template speciﬁed in IEEE 802.3 Clause

14 and shown in Figure 5.

•

The output of the squelch comparator is used for squelch, link pulse

detect, SOI detect, reverse polarity detect.

The data comparator is a zero crossing comparator whose output is

used for clock and data recovery.

2.9.3 Squelch - 100 Mbps

The squelch block determines whether the input contains valid data. The

100 Mbps TX squelch is one of the criteria used to determine link

integrity. The squelch comparators compare the TX inputs against ﬁxed

positive and negative thresholds, called squelch levels.

The output from the squelch comparator goes to a digital squelch circuit,

which determines whether the receive input data on that channel is valid.

If the data is invalid, the receiver is in the squelched state. If the input

voltage exceeds the squelch levels at least four times with alternating

polarity within a 10 us interval, the data is considered to be valid by the

squelch circuit and the receiver now enters into the unsquelch state.

Functional Description

31 of 118

April, 2002

Figure 5

TP Input Voltage Template - 10 Mbps

a. Short Bit

3.1 V

Slope 0.5 V/ns

585 mV

585 mV sin (π t/PW)

0

PW

b. Long Bit

3.1 V

Slope 0.5 V/ns

585 mV

585 mV sin (π t/PW)

585 mV sin [2 π (t − PW2)/PW]

PW/4 3PW/4

0

PW

In the unsquelch state, the receive threshold level is reduced by

approximately 30% for noise immunity reasons and is called the

unsquelch level. When the receiver is in the unsquelch state the input

signal is considered valid.

The device stays in the unsquelch state until loss of data is detected.

Loss of data is detected if no alternating polarity unsquelch transitions

are detected during any 10 us interval. When the loss of data is detected,

the receive squelch level is re-established.

2.9.4 Squelch - 10 Mbps

The TP squelch algorithm for 10 Mbps mode is identical to the 100 Mbps

mode, except:

•

The 10 Mbps squelch algorithm is not used for link integrity, but to

sense the beginning of a packet.

32 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

•

The receiver goes into the unsquelch state if the input voltage

exceeds the squelch levels for three bit times with alternating polarity

within a 50-250 ns interval.

•

The receiver goes into the squelch state when SOI is detected.

Unsquelch detection has no affect on link integrity, link pulses are

used for that in 10 Mbps mode.

•

Start of packet is determined when the receiver goes into the

unsquelch state and CRS is asserted.

The receiver meets the squelch requirements deﬁned in IEEE 802.3

Clause 14.

2.9.5 Receive Level Adjust

The receiver squelch and unsquelch levels can be lowered by 4.5 dB by

setting the receive level adjust bit in the MI serial port Channel

Conﬁguration register. By setting this bit, the device can support cable

lengths exceeding 100 meters.

2.10 Fiber Interface

2.10.1 General

The Fiber Interface implements the 100BaseFX function deﬁned in IEEE

802.3.

The Fiber Interface consists of three signals: (1) a differential PECL data

output (FXOP/FXON), (2) a differential PECL data input (FXIP/FXIN),

and (3) a PECL signal detect (SD/FXEN).

The Fiber Interface section consists of four blocks: (1) transmitter, (2)

receiver, (3) signal detect, and (4) far end fault.

The Fiber Interface can be independently selected for each channel with

the SD/FXEN_[3:0] pins.

The Fiber Interface is disabled in 10Mbps mode. AutoNegotiation and the

scrambler/descrambler are disabled when the Fiber Interface is enabled.

The Fiber Interface meets all IEEE 802.3 requirements.

Functional Description

33 of 118

April, 2002

2.10.2 Transmitter

The FX transmitter converts data from the 4B5B encoder into binary

NRZI data and outputs the data onto the FXOP/FXON pins for each

channel. The output driver is a differential current source that will drive a

100-ohm load to ECL levels. The FXOP/FXON pins can directly drive an

external ﬁber optic transceiver. The FX transmitter meets all the

requirements deﬁned in IEEE 802.3.

The FX transmit output current level is derived from an internal reference

voltage and the external resistor on REXT pin.

2.10.3 Receiver

The FX receiver (1) converts the differential ECL inputs on the

FXIP/FXIN pins for each channel to a digital bit stream, (2) validates the

data on FXIP/FXIN with the SD/ FXEN input pin for each channel, and

(3) enable/disables the Fiber Interface with the SD/FXEN pin for each

channel. The FX receiver meets all requirements deﬁned in IEEE 802.3.

The input to the FXIP/FXIN pins can be directly driven from a ﬁber optic

transceiver and ﬁrst goes to a comparator. The comparator compares the

input waveform against the internal ECL threshold levels to produce a

low jitter serial bit stream with internal logic levels. The data from the

comparator output is then passed to the clock and data recovery block

provided the signal detect input, SD/FXEN, is asserted. The signal detect

function is described in the next section.

2.10.4 Signal Detect

The FX receiver has a signal detect input pin, SD/FXEN, for each

channel which indicates whether the incoming data on FXIP/FXIN is valid

or not for that channel. The SD/FXEN pin can be driven directly from an

external ﬁber optic transceiver and meets all requirements deﬁned in the

IEEE 802.3 speciﬁcations.

The SD/FXEN input goes directly to a comparator. The comparator

compares the input waveform against the internal ECL threshold level to

produce a digital signal with internal logic levels. The output of the signal

detect comparator then goes to the link integrity and squelch blocks. If

the signal detect input is asserted, the channel is placed in the Link Pass

state and the input data on FXIP/FXIN is determined to be valid. If the

34 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

signal detect input is deasserted, the channel is placed in the Link Fail

state and the input data on FXIP/FXIN is determined to be invalid.

The SD_THR pin adjusts the ECL trip point of the SD/ FXEN input. When

the SD_THR pin is tied to a voltage between GND and GND+0.45V, the

trip point of the SD ECL input buffer is internally set to VCC-1.3V. When

SD_THR pin is set to a voltage greater than GND+0.85v, the trip point

of the SD SD/FXEN ECL input buffer is set to the voltage that is applied

to the SD_THR pin. The trip level for the SD/FXEN input buffer must be

set to VCC- 1.3V. Having external control of the SD/FXEN buffer trip level

with the SD_THR pin allows this trip level to be referenced to an external

supply which facilitates connection to both 3.3V and 5V external ﬁber

optic transceiver. If the device is to be connected to a 3.3V external ﬁber

optic transceiver, then SD_THR should be tied to GND. If the device is

to be connected to a 5V external ﬁber optic transceiver, then SD_THR

needs to be tied to VCC-1.3V, and this can be done so with an external

resistor divider. Refer to Section 4, “Application Information,” page 70, for

more details on connections to external ﬁber optic transceivers.

2.10.5 Fiber Interface Disable

The Fiber Interface will be disabled if the SD/FXEN pin is tied to GND.

Disabling the Fiber Interface automatically enables the TP interface.

2.10.6 Far End Fault

Each channel has the Far End Fault capability, referred to as FEF, and

deﬁned in IEEE 802.3 speciﬁcations. FEF is a method by which the Fiber

Interface can signal a fault to a remote device by transmitting an idle

pattern consisting of 84 ‘1’s followed by a single ‘0’ repeatedly (idle

period normally has all 1’s). FEF was speciﬁed in IEEE 802.3 because

FX lacks the AutoNegotiation capability to signal a remote fault to

another station.

FEF can only be made operational only when the Fiber Interface is

enabled. In the device default state with the Fiber Interface enabled, FEF

is disabled, but it can be enabled by setting the FEF select bit in the MI

serial port Global Conﬁguration register. When FEF is enabled, (1) a ‘0’

is transmitted after each group of 84 ‘1’s repeatedly during idle if the

SD/FXEN pin is deasserted, and (2) if an FEF stream is detected by the

receiver for 3 consecutive intervals, the remote fault bit is set in the MI

serial port Status register and the LED0 output pin is asserted.

Functional Description

35 of 118

April, 2002

2.11 Collision

2.11.1 100 Mbps

Collision occurs whenever transmit and receive occur simultaneously

while the device is in Half Duplex. Collision is sensed whenever there is

simultaneous transmission (packet transmission on TPOP/N) and

reception (non-idle symbols detected on receive input). When collision is

detected:

•

The COL output is asserted.

TP data continues to be transmitted on twisted pair outputs.

TP data continues to be received on twisted pair inputs.

Internal CRS loopback is disabled.

Once collision starts, CRS is asserted and stays asserted until the

receive and transmit packets that caused the collision are terminated.

The collision function is disabled if the device is in the Full Duplex mode,

is in the Link Fail state, or if the device is in the diagnostic loopback

mode.

2.11.2 10 Mbps

Collision in 10 Mbps mode is identical to the 100 Mbps mode, except:

•

Reception is determined by the 10 Mbps squelch criteria.

RXD[3:0] outputs are forced to all 0's.

Collision is asserted when the SQE test is performed.

Collision is asserted when the jabber condition has been detected.

2.11.3 Collision Test

The controller interface collision signal, COL, can be tested by setting the

collision test register bit in the MI serial port Control register. When this

bit is set, TXEN is looped back onto COL and the TP outputs are

disabled.

36 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

2.11.4 Collision Indication

Collision can be programmed to appear on the LED2 pin by appropriately

setting the LED deﬁnition bits in the MI serial port Global Conﬁguration

register. Section 2.23, “LED Drivers,” page 48, describes the

programmable LED deﬁnition bit settings. When the LED2 pin is

programmed to be a collision detect output, the pin is asserted low for

100 ms every time a collision occurs.

2.12 Start of Packet

2.12.1 100 Mbps

Start of packet for 100 Mbps mode is indicated by a unique Start of

Stream Delimiter (SSD). The SSD pattern consists of the two /J/K/ 5B

symbols inserted at the beginning of the packet in place of the ﬁrst two

preamble symbols, as deﬁned in IEEE 802.3 Clause 24 and shown in

Table 3 and Figure 2.

The transmit SSD is generated by the 4B5B encoder and the /J/K/

symbols are inserted by the 4B5B encoder at the beginning of the

transmit data packet in place of the ﬁrst two 5B symbols of the preamble,

as shown in Figure 2.

The receive pattern is detected by the 4B5B decoder by examining

groups of 10 consecutive code bits (two 5B words) from the descrambler.

Between packets, the receiver will be detecting the idle pattern, which is

5B /I/ symbols. While in the idle state, CRS and RXDV are deasserted.

If the receiver is in the idle state and 10 consecutive code bits from the

receiver consist of the /J/K/ symbols, the start of packet is detected, data

reception is begun, CRS and RXDV are asserted, and /5/5/ symbols are

substituted in place of the /J/K/ symbols.

If the receiver is in the idle state and 10 consecutive code bits from the

receiver consist of a pattern that is neither /I/ I/ nor /J/K/ symbols but

contains at least 2 non-contiguous 0's, then activity is detected but the

start of packet is considered to be faulty and a False Carrier Indication

(also referred to as bad SSD) is signaled to the controller interface. When

False Carrier is detected CRS is asserted, RXDV remains deasserted,

RXD[3:0]=1110 while RXER is asserted, and the bad SSD bit is set in

the MI serial port Channel Status Output register. Once a False Carrier

Functional Description

37 of 118

April, 2002

Event is detected, the idle pattern (two /I/I/ symbols) must be detected

before any new SSD’s can be sensed.

If the receiver is in the idle state and 10 consecutive code bits from the

receiver consist of a pattern that is neither /I/ I/ nor /J/K/ symbols but

does not contain at least 2 non contiguous 0's, the data is ignored and

the receiver stays in the idle state.

2.12.2 10 Mbps

Since the idle period in 10 Mbps mode is deﬁned to be no data on the

TP inputs, then the start of packet for 10 Mbps mode is detected when

valid data is detected by the TP squelch circuit. When start of packet is

detected, CRS is asserted as described in Section 2.2, “Controller

Interface,” page 16. Refer to Section 2.9.4, “Squelch - 10 Mbps,” page 32,

for the algorithm for valid data detection.

2.13 End of Packet

2.13.1 100 Mbps

End of packet for 100 Mbps mode is indicated by an End of Stream

Delimiter (referred to as ESD). The ESD pattern consists of the two /T/R/

4B5B symbols inserted after the end of the packet, as deﬁned in IEEE

802.3 Clause 24 and shown in Table 3 and Figure 2.

The transmit ESD is generated by the 4B5B encoder and the /T/R/

symbols are inserted by the 4B5B encoder after the end of the transmit

data packet, as shown in Figure 2.

The receive ESD pattern is detected by the 4B5B decoder by examining

groups of 10 consecutive code bits (two 5B words) from the descrambler

during valid packet reception to determine whether there is an ESD.

If the 10 consecutive code bits from the receiver during valid packet

reception consist of the /T/R/ symbols, the end of packet is detected,

data reception is terminated, CRS and RXDV are deasserted, and /I/I/

symbols are substituted in place of the /T/R/ symbols.

If 10 consecutive code bits from the receiver during valid packet

reception do not consist of /T/R/ symbols, but consist of /I/I/ symbols

instead, the packet is considered to have been terminated prematurely

38 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

and abnormally. When this premature end of packet condition is

detected, RXER remains asserted for the nibble associated with the ﬁrst

/I/ symbol detected and then RXER and CRS and RXDV are all

deasserted. Premature end of packet condition is also indicated by

setting the ESD error bit in the MI serial port Channel Status Output

register.

2.13.2 10 Mbps

The end of packet for 10 Mbps mode is indicated with the SOI (Start of

Idle) pulse. The SOI pulse is a positive double wide pulse containing a

Manchester code violation inserted at the end of every packet.

The transmit SOI pulse is generated by the TP transmitter and inserted

at the end of the data packet after TXEN is deasserted. The transmitted

SOI output pulse at the TP output is shaped by the transmit waveshaper

to meet the pulse template requirements speciﬁed in IEEE 802.3 Clause

14 and shown in Figure 6.

The receive SOI pulse is detected by the TP receiver by sensing missing

data transitions. Once the SOI pulse is detected, data reception is ended

and CRS and RXDV are deasserted.

Figure 6

SOI Output Voltage Template - 10 Mbps

0 BT

4.5 BT

3.1 V

0.5 V/ns

0.25 BT

2.25 BT

6.0 BT

585 mV

+50 mV

−50 mV

585 mV sin (2

π

(t/1 BT))

45.0 BT

0 ≤ t ≤ 0.25 BT and

2.25 ≤ t ≤ 2.5 BT

−3.1 V

2.5 BT 4.5 BT

Functional Description

39 of 118

April, 2002

Figure 7

Link Pulse Output Voltage Template - 10 Mbps

1.3 BT

0 BT

3.1 V

0.5 V/ns

0.5 BT

585 mV

0.6 BT

2.0 BT

300 mV

4.0 BT

+50 mV

−50 mV

200 mV

−50 mV

42.0 BT

4.0 BT

0.25 BT

−3.1 V

0.85 BT 2.0 BT

2.14 Link Integrity and AutoNegotiation

2.14.1 General

The L84225 can be conﬁgured to implement either the standard link

integrity algorithms or the AutoNegotiation algorithm.

The standard link integrity algorithms are used solely to establish an

active link to and from a remote device. There are different standard link

integrity algorithms for 10 and 100 Mbps modes. The AutoNegotiation

algorithm is used for two purposes:

•

To automatically conﬁgure the device for either 10/100 Mbps and

Half/Full Duplex modes

To establish an active link to and from a remote device

The standard link integrity and AutoNegotiation algorithms are described

below.

40 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

2.14.2 10Base-T Link Integrity Algorithm

The L84225 uses the same 10Base-T link integrity algorithm that is

deﬁned in IEEE 802.3 clause 14. This algorithm uses normal link pulses,

referred to as NLP’s and transmitted during idle periods, to determine if

a device has successfully established a link with a remote device (called

Link Pass state). The transmit link pulse meets the template deﬁned in

IEEE 802.3 Clause 14 and shown in Figure 7. Refer to IEEE 802.3

Clause 14 for more details if needed.

2.14.3 100Base-TX Link Integrity Algorithm

Since 100Base-TX is deﬁned to have an active idle signal, then there is

no need to have separate link pulses like those deﬁned for 10Base-T.

The L84225 uses the squelch criteria and descrambler synchronization

algorithm on the input data to determine if the device has successfully

established a link with a remote device (called Link Pass state). Refer to

IEEE 802.3 for details on both algorithms.

2.14.4 AutoNegotiation Algorithm

As stated previously, the AutoNegotiation algorithm is used for two

purposes:

•

To automatically conﬁgure the device for either 10/100 Mbps and

Half/Full Duplex modes

To establish an active link to and from a remote device

The AutoNegotiation algorithm is the same algorithm that is deﬁned in

IEEE 802.3 Clause 28. AutoNegotiation uses a burst of link pulses, called

fast link pulses and referred to as FLP’s, to pass up to 16 bits of signaling

back and forth between the L84225 and a remote device. The transmit

FLP pulses meet the template speciﬁed in IEEE 802.3 and shown in

Figure 7. A timing diagram contrasting NLP’s and FLP’s is shown in

Figure 8.

Functional Description

41 of 118

April, 2002

Figure 8

NLP vs. FLP Link Pulse

a. Normal Link Pulse (NLP)

TX_DI±

b. Fast Link Pulse (FLP)

TX_DI±

D0

D1

D2

D3

D14 D15

Clock Clock Clock Clock Clock Clock Clock

Data Data Data Data Data Data

The AutoNegotiation algorithm is initiated by any of the following events:

•

Powerup

Device Reset

AutoNegotiation Reset

Entering the Link Fail state

Once a negotiation has been initiated, the L84225 ﬁrst determines if the

remote device has AutoNegotiation capability. If the device is not

AutoNegotiation capable and is just transmitting either a 10Base-T or

100Base-TX signal, the L84225 will sense that and place itself in the

correct mode. If the L84225 detects FLP’s from the remote device, then

the remote device is determined to have AutoNegotiation capability and

the device then uses the contents of the MI serial port AutoNegotiation

Advertisement register and FLP’s to advertise it’s capabilities to a remote

device. The remote device does the same, and the capabilities read back

from the remote device are stored in the MI serial port AutoNegotiation

Remote End Capability register. The L84225 negotiation algorithm then

matches it’s capabilities to the remote devices capabilities and

determines to what mode the device should be conﬁgured according to

the priority resolution algorithm deﬁned in IEEE 802.3 Clause 28. Once

the negotiation process is completed, the L84225 then conﬁgures itself

for either 10 or 100 Mbps mode and either Full or Half Duplex modes

(depending on the outcome of the negotiation process), and it switches

42 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

to either the 100Base-TX or 10Base-T link integrity algorithms

(depending on which mode was enabled by AutoNegotiation). Refer to

IEEE 802.3 Clause 28 for more details.

2.14.5 AutoNegotiation Outcome Indication

The outcome or result of the AutoNegotiation process is stored in the

speed detect and duplex detect bits in the MI serial port Status Output

register.

2.14.6 AutoNegotiation Status

The status of the AutoNegotiation process can be monitored by reading

the AutoNegotiation Acknowledgement Bit in the MI serial port Status

register.

2.14.7 AutoNegotiation Enable

The AutoNegotiation algorithm can be enabled (or restarted) by setting

the AutoNegotiation enable bit in the MI serial port Control register or by

asserting the ANEG pin. The AutoNegotiation enable bit and ANEG pin

both have to be high to enable AutoNegotiation. When the

AutoNegotiation algorithm is enabled, the device halts all transmissions

including link pulses for 1200-1500 ms, enters the Link Fail state, and

restarts the negotiation process. When the AutoNegotiation algorithm is

disabled, the selection of 100 Mbps or 10 Mbps mode is determined by

the speed select bit in the MI serial port Control register, and the

selection of Half or Full Duplex is determined by the duplex select bit in

the MI serial port Control register.

2.14.8 AutoNegotiation Reset

The AutoNegotiation algorithm can be initiated at any time by setting the

AutoNegotiation reset bit in the MI serial port Control register.

2.14.9 Link Indication

Receive link detect activity can be monitored through the link detect bit

in the MI serial port Status and Status Output registers or it can also be

programmed to appear on LED status pins by appropriately setting the

programmable LED select bits in the MI serial port Conﬁguration 2

register as shown in Table 4. Whenever the LED Status pins are

Functional Description

43 of 118

April, 2002

programmed to be a link detect output, these pins are asserted low

whenever the device is in the Link Pass state.

2.14.10 Link Disable

The link integrity function can be disabled by setting the link disable bit

in the MI serial port Conﬁguration 1 register. When the link integrity

function is disabled, the device is forced into the Link Pass state,

conﬁgures itself for Half/Full Duplex based on the value of the duplex bit

in the MI serial port Control register, conﬁgures itself for 100/ 10 Mbps

operation based on the values of the speed bit in the MI serial port

Control register, and continues to transmit NLP’s or TX idle patterns,

depending on whether the device is in 10 or 100 Mbps mode.

2.15 Jabber

2.15.1 100 Mbps

The jabber function is disabled in the 100 Mbps mode.

2.15.2 10 Mbps

A jabber condition occurs when the transmit packet exceeds a

predetermined length. When jabber is detected, the TP transmit outputs

are forced to the idle state, collision is asserted, and jabber register bits

in the MI serial port Status and Channel Status Output registers are set.

2.16 Receive Polarity Correction

2.16.1 100 Mbps

No polarity detection or correction is needed in 100 Mbps mode.

2.16.2 10 Mbps

The polarity of the signal on the TP receive input is continuously

monitored. If one SOI pulse indicates incorrect polarity on the TP receive

input, the polarity is internally determined to be incorrect, and the reverse

polarity bit is set in the MI serial port Channel Status Output register.

The L84225 will automatically correct for the reverse polarity condition if

the autopolarity feature is not disabled.

44 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

2.17 Full Duplex Mode

2.17.1 100 Mbps

Full Duplex mode allows transmission and reception to occur

simultaneously. When Full Duplex mode is enabled, collision is disabled,

and internal TXEN to CRS loopback is disabled.

The device can be either forced into Half or Full Duplex mode, or the

device can detect either Half or Full Duplex capability from a remote

device and automatically place itself in the correct mode.

Each channel can be forced into the Full or Half Duplex modes by either

setting the duplex bit in the MI serial port Control register or asserting

the DPLX pin for the corresponding channel with AutoNegotiation

disabled.

The device can automatically conﬁgure itself for Full or Half Duplex

modes by using the AutoNegotiation algorithm to advertise and detect

Full and Half Duplex capabilities to and from a remote terminal. For

detailed information, refer to Section 2.14, “Link Integrity and

AutoNegotiation,” page 40.

2.17.2 10 Mbps

Full Duplex in 10 Mbps mode is identical to the 100 Mbps mode.

2.17.3 Full Duplex Indication

Full Duplex detect activity can be monitored through the duplex detect bit

in the MI serial port Channel Status Output register.

Full Duplex detect activity also appears on the LED1 pin by default. The

LED outputs can be programmed to indicate four speciﬁc sets of events,

by appropriately setting the LED deﬁnition bits in the MI serial port Global

Conﬁguration register. Section 2.23, “LED Drivers,” page 48, describes

the programmable LED deﬁnition bit settings. Note that Full Duplex

detection appears on the LED1 pin in each of the four sets of events.

The LED1 pin is asserted low when the device is conﬁgured for Full

Duplex operation.

Functional Description

45 of 118

April, 2002

2.18 10/100 MBPS Selection

2.18.1 General

The device can be forced into either the 100 or 10 Mbps mode, or the

device can detect 100 or 10 Mbps capability from a remote device and

automatically place itself in the correct mode.

The device can be forced into either the 100 or 10 Mbps mode by either

setting the speed select bit in the MI serial port Control register or by

setting the SPEED pin with AutoNegotiation disabled. Both the speed

select bit and SPEED pin need to be set to the same speed (10 or 100)

for the device to be properly conﬁgured. The speed select bit and SPEED

pin are ignored if AutoNegotiation is enabled.

The device can automatically conﬁgure itself for 100 or 10 Mbps mode

by using the AutoNegotiation algorithm to advertise and detect 100 and

10 Mbps capabilities to and from a remote device. Refer to Section 2.14,

“Link Integrity and AutoNegotiation,” page 40, for more details on

AutoNegotiation.

2.18.2 10/100 MBPS Indication

The device speed (100/10 Mbps) can be monitored through the speed

bit in the MI serial port Channel Status Output register.

The device speed can also be programmed to appear on the LED0 pin,

by appropriately setting the LED deﬁnition bits in the MI serial port Global

Conﬁguration register. Section 2.23, “LED Drivers,” page 48, describes

the programmable LED deﬁnition bit settings. When the LED0 pin is

programmed to be a speed detect output, the pin is asserted low when

the device is conﬁgured for 100 Mbps operation.

2.19 Loopback

2.19.1 Internal CRS Loopback

TXEN is internally looped back onto CRS during every transmit packet.

This internal CRS loopback is disabled during collision, in Full Duplex

mode, in Link Fail State, and in RMII mode. In 10 Mbps mode, internal

CRS loopback is also disabled when jabber is detected.

46 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

The internal CRS loopback can be disabled by setting the TXEN to CRS

loopback disable bit in the MI serial port Channel Conﬁguration register.

When this bit is set, TXEN is no longer looped back to CRS.

2.19.2 Diagnostic Loopback

A diagnostic loopback mode can also be selected by setting the loopback

bit in the MI serial port Control register. When diagnostic loopback is

enabled, TXD[3:0] data is looped back onto RXD[3:0], TXEN is looped

back onto CRS, RXDV operates normally, the TP receive and transmit

paths are disabled, the transmit link pulses are halted, and the Half/Full

Duplex modes do not change. Diagnostic loopback mode can not be

enabled when the FBI interface is selected.

2.20 Reset

The L84225 is reset when either:

1. VDD is applied to the device,

2. the reset bit is set in the MI serial port Control register, or

3. the RESET pin is asserted active low.

When the reset is initiated by either (1) or (2), an internal power-on reset

pulse is generated which resets all internal circuits, forces the MI serial

port bits to their default values, and latches in new values for the MI

address. After the power-on reset pulse has ﬁnished, the reset bit in the

MI serial port Control register is cleared and the device is ready for

normal operation. The device is guaranteed to be ready for normal

operation 50 ms after the reset was initiated.

When the reset is initiated by (3), the identical procedure takes place as

in (1) and (2), except the device stays in reset until the RESET pin is

deasserted high.

2.21 Powerdown

The L84225 can be powered down by setting the powerdown bit in the

MI serial port Control register. In powerdown mode, the TP outputs are

in high impedance state, all functions are disabled except the MI serial

port, and the power consumption is reduced to a minimum. The device

will be ready for normal operation 50 ms after powerdown is deasserted.

Functional Description

47 of 118

April, 2002

2.22 Clock

The L84225 requires a 25 MHz reference frequency for internal signal

generation in MII mode, and 50 MHz in RMII mode. This reference

frequency must be applied to the CLKIN pin.

2.23 LED Drivers

The LED[3:0] outputs can drive LEDs tied to either VDD or GND. The

LED deﬁnitions assume that the LED outputs are active low. If the LED

Anodes are tied to the positive power supply (through limiting resistors),

the LED will indicate the event as shown in Table 4. If the LED Cathodes

are tied to ground and the Anodes to the L84225 Driver output, they will

indicate the respective complementary events.

The LED[3:0] outputs can also drive other digital inputs.

Table 4

LED Function Deﬁnition

LEDDEF

LED3

LED2

LED1

LED0

1

0

LINK + ACT

LINK 100

COL

ACT

FDX

10/100

LINK10

Notes:

When the FX interface is enabled, LED0 becomes FEF. Default = 000

when pin LEDDEF = 0

Bits 16. [13:11] forced to 001 when pin LEDDEF = 1

48 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 5

Symbol

LED Event Deﬁnition

Deﬁnition

ACT

Activity Occurred, Stretch Pulse to 100 ms

Collision Occurred, Stretch Pulse to 100 ms

100 Mb Link Detected

COL

LINK100

LINK10

LINK

10 Mb Link Detected

100 Mb or 10 Mb Link Detected

LINK+ACT

LED on if Link Detected (10 or 100). LED Blinks if Activity

Determined, Stretch Pulse to 100 ms

FDX

Full Duplex Mode Detected with Link Pass

10/100

10 Mb Mode Enabled (High) or 100 Mb Mode Enabled (Low)

with Link Pass

2.24 Repeater Mode

The L84225 has one predeﬁned repeater mode which can be enabled

by asserting the REPEATER pin. When this mode is enabled, the device

operation is altered as follows:

•

TXEN to CRS loopback is disabled.

2.25 MI Serial Port

2.25.1 Signal Description

The MI serial port has ﬁve pins, MDC, MDIO, and PHYAD[4:2]. MDC is

the serial shift clock input. MDIO is a bidirectional data I/O pin.

PHYAD[4:2] are physical address pins.

Pins PHYAD[4:2] set the three most signiﬁcant bits of the PHY address.

The two least signiﬁcant bits of the PHY address are set internally to

match the channel number, as shown in Table 6.

Functional Description

49 of 118

April, 2002

Table 6

PHYAD[1:0] Settings

PHYAD1

PHYAD0

Channel 3

Channel 2

Channel 1

Channel 0

1

0

1

0

1

0

2.25.2 Timing

Figure 9 shows a timing diagram for a MI serial port cycle.

50 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

The MI serial port is idle when at least 32 continuous 1's are detected

on MDIO and remains idle as long as continuous 1's are detected.

During idle, MDIO is in the high impedance state. When the MI serial port

is in the idle state, a 01 pattern on the MDIO pin initiates a serial shift

cycle. Data on MDIO is then shifted in on the next 14 rising edges of

MDC (MDIO is high impedance). If the register access mode is not

enabled, on the next 16 rising edges of MDC, data is either shifted in or

out on MDIO, depending on whether a write or read cycle was selected

with the bits READ and WRITE. After the 32 MDC cycles have been

completed, one complete register has been read/written, the serial shift

process is halted, data is latched into the device, and MDIO goes into

high impedance state. Another serial shift cycle cannot be initiated until

the idle condition (at least 32 continuous 1's) is detected.

2.25.3 Multiple Register Access

Multiple registers can be accessed on a single MI serial port access

cycle with the multiple register access feature. The multiple register

access feature can be enabled by setting the multiple register access

enable bit in the Global Conﬁguration Register for all channels.

When multiple register access is enabled, all registers can be accessed

on a single MI serial port access cycle by setting the register address to

11111 during the ﬁrst 16 MDC clock cycles. There is no actual register

residing in register address location 11111.

When the register address is set to 11111, all eleven registers are

accessed for all four channels on the 704 rising edges of MDC (4 x 11

x 16) that occur after the ﬁrst 16 MDC clock cycles of the MI serial port

access cycle. The registers are accessed in numerical order from 0 to

20 for each channel and from channel 0 to 3. After all 720 MDC clocks

have been completed, all the registers have been read/written, and the

serial shift process is halted, data is latched into the device, and MDIO

goes into high impedance state. Another serial shift cycle cannot be

initiated until the idle condition (at least 32 continuous 1's) is detected.

52 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

2.25.4 Bit Types

Since the serial port is bidirectional, there are many types of bits. The bit

type deﬁnitions are summarized in Table 7.

Table 7

Sym.

MI Register Bit Type Deﬁnition

Deﬁnition

Name

Write Cycle

Read Cycle

W

R

Write

Input

No Operation, Hi Z

Output

Read

No Operation, Hi Z

Input

R/W

Read/Write

Output

R/WSC Read/Write

Self Clearing

Input. Clears Itself After

Operation Completed

Output

R/LL

R/LH

R/LT

Read/Latching

Low

No Operation, Hi Z

Output. When bit goes low, bit latched.

When bit is read, bit updated.

Read/Latching

High

Output. when bit goes high, bit latched.

When bit is read, bit updated.

Read/Latching on

Transition

Output. When bit transitions, bit latched

and interrupt set. When bit is read, inter-

rupt cleared and bit updated.

Write bits (W) are inputs during a write cycle and are high impedance

during a read cycle. Read bits (R) are outputs during a read cycle and

high impedance during a write cycle. Read/Write bits (R/W) are actually

write bits that can be read out during a read cycle. R/WSC bits are R/W

bits that are self-clearing after a set period of time or after a speciﬁc

event has completed. R/LL bits are read bits that latch themselves when

they go low, and they stay latched low until read. After they are read, they

are reset high. R/LH bits are the same as R/LL bits, except that they latch

high. R/LT are read bits that latch themselves whenever they make a

transition or change value, and they stay latched until they are read. After

R/LT bits are read, they are updated to their current value. The R/LT bits

can also be programmed to assert the interrupt function as described in

the Interrupt section.

Functional Description

53 of 118

April, 2002

2.25.5 Frame Structure

The structure of the serial port frame is shown in Table 8 and a timing

diagram is shown in Figure 9. Each serial port access cycle consists of

32 bits (or 720 bits if multiple register access is enabled and

REGAD[4:0]=11111), exclusive of idle. The ﬁrst 16 bits of the serial port

cycle are always write bits and are used for addressing. The last 16/704

bits are from one/all of the 4 x 11 data registers.

The ﬁrst 2 bits in Table 8 and Figure 9 are start bits and need to be

written as a 01 for the serial port cycle to continue. The next 2 bits are

read and write bits that determine whether the accessed data register

bits will be read or write. The next 5 bits are device addresses. The 3

most signiﬁcant bits must match the values on pins PHYAD[4:2] and the

2 least signiﬁcant bits select one of four channels for access. The next 5

bits are register address select bits, which select one of the eleven

registers for access. The next 2 bits are turnaround bits which are not an

actual register bits but extra time to switch MDIO from write to read if

necessary. The ﬁnal 16 bits of the MI serial port cycle (or 704 bits if

multiple register access is enabled and REGAD[4:0]=11111) come from

the speciﬁc data register designated by the register address bits

REGAD[4:0].

2.25.6 Register Structure

The L84225 has eleven 16 bit registers for each channel. All eleven

registers are available for setting conﬁguration inputs and reading status

outputs. A map of the registers is shown in Table 9. The eleven registers

consist of six registers that are deﬁned by IEEE 802.3 speciﬁcations

(Registers 0-5) and ﬁve registers that are unique to the L84225

(Registers 16-20).

The structure and bit deﬁnition of the Control Register is shown in

Table 10. This register stores various conﬁguration inputs and its bit

deﬁnition complies with the IEEE 802.3 speciﬁcations.

The structure and bit deﬁnition of the Status Register is shown in

Table 11. This register contains device capabilities and status output

information and its bit deﬁnition complies with the IEEE 802.3

speciﬁcations.

The structure and bit deﬁnition of the PHY ID Register 1 and PHY ID

Register 2 is shown in Table 12 and Table 13, respectively. These

54 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

registers contain an identiﬁcation code unique to the L84225 and their bit

deﬁnition complies with the IEEE 802.3 speciﬁcations.

The structure and bit deﬁnition of the Auto Negotiation Advertisement

and Auto Negotiation Remote End Capability registers is shown in

Table 14 and Table 15, respectively. These registers are used by the Auto

Negotiation algorithm and their bit deﬁnition complies with the IEEE

802.3 speciﬁcations.

The Global Conﬁguration Register, shown in Table 16, stores various

conﬁguration inputs and is common for all four channels. This register is

reserved for factory use only.

The Channel Conﬁguration Register, shown in Table 17, stores various

conﬁguration inputs unique to each channel. This register is reserved for

factory use only.

The structure and bit deﬁnition of the Channel Status Output Register is

shown in Table 18. This register contains output status information from

each channel.

The structure and bit deﬁnition of the Global Interrupt Mask Register is

shown in Table 19. This register is common for all four channels. Bit 7 is

the interrupt indication. The 7 least signiﬁcant bits are the Mask bits for

the R/LT status bits in the Channel Status Output Register.

Register 20 in Table 20 is reserved for factory use only. All bits must be

set to the pre-set default states shown for normal operation.

2.25.7 Invalid Registers

The registers in locations 6-15 and 21-31 are not implemented on the

device and are therefore unused. When an unused register is read, the

value returned can be conﬁgured to be either all 0s or all 1s by

appropriately pinstrapping the REGDEF pin.

Functional Description

55 of 118

April, 2002

Figure 10

MDIO Interrupt Pulse

Internal

Interrupt

MDC

MDIO

MDIO High-Z

Pulled High Externally

Interrupt

Pulse

MDIO High-Z

Pulled High Externally

Internal

Interrupt

MDC

B1

B0

MDIO

Last Two Bits

of Read Cycle

Interrupt

Pulse

MDIO High-Z

Pulled High Externally

MDIO High-Z

Pulled High Externally

56 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

3 Register Description

Table 8

MI Serial Port Structure

<Idle>

IDLE

<Data>

D[15:0]

ST[1:0]

READ

WRITE

PHYAD[4:0]

REGAD[4:0]

TA[1:0]

MI Registers - Address and Default Value

REGAD

Name

Default (Hex Code)

00000

00001

00010

00011

00100

00101

10000

10001

10010

10011

10100

Control Register

3000

Status Register

7809

PHY ID 1 Register

0016

PHY ID 2 Register

F840

Auto Negotiation Advertisement Register

01E1

Auto Negotiation Remote Capability Register

0000

Reserved

0008

Reserved

0002

0340/0240/ 0140/0040

007F

Channel Status Output Register

Reserved

0000

Symbol

Name

Deﬁnition

R/W

IDLE

Idle Pattern

These bits are an idle pattern. Device will not initiate an MI

cycle until it detects at least 32 1's.

W

ST[1:0]

Start Bits

When ST[1:0]=01, a MI serial port access cycle starts.

1 = Read Cycle

W

READ

Read Select

Write Select

WRITE

1 = Write Cycle

PHYAD[4:0]

PhysicalDevice When PHYAD[4:2] bits match the PHYAD[4:2] pins, the MI

Address

serial port is selected for operation. PHYAD[1:0] is used for

channel selection:

PHYAD [1:0]=11 For Channel 3

PHYAD [1:0]=10 For Channel 2

PHYAD [1:0]=01 For Channel 1

PHYAD [1:0]=00 For Channel 0

REGAD4[4:0] Register

Address

If REGAD[4:0]=00000-11100, these bits determine the

speciﬁc register from which D[15:0] is read/written. If mul-

tiple register access is enabled and REGAD[4:0]=11111,

all registers are read/written in a single cycle.

W

Register Description

57 of 118

April, 2002

Symbol

Name

Deﬁnition

R/W

TA[1:0]

Turnaround

Time

These bits provide some turnaround time for MDIO

When READ=1, TA[1:0]=Z0

R/W

When WRITE=1, TA[1:0]=ZZ

D[15:0]+

Data

These 16 bits contain data to/from one of the eleven regis- R or

ters selected by register address bits REGAD[4:0].

W

58 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 10

Register 0 - Control Register Deﬁnition

0.15

RST

0.14

LPBK

R/W

0.13

SPEED

R/W

0.12

ANEG_EN

R/W

0.11

PDN

R/W

0.10

MII_DIS

R/W

0.9

0.8

DPLX

R/W

ANEG_RST

R/WSC

0.7

0.6

0

0.5

0

0.4

0

0.3

0

0.2

0

0.1

0

0.0

0

COLTST

R/WSC

R

Bit

Symbol

Name

Deﬁnition

R/W Def.

0.15

RST

Reset

1 = Reset, Bit Self Clearing after Reset Complete R/W

0

1

0 = Normal SC

SC

0.14

0.13

LPBK

SPEED

Loopback

Enable

1 = Loopback Mode Enabled

0 = Normal

R/W

Speed

Select

1 = 100 Mbps Selected (100BaseTX)

0 = 10 Mbps Selected (10BaseT)

Note: Can be overridden with SPEED pin

R/W

0.12

ANEG_EN

AutoNegoti- 1 = AutoNegotiation Enabled

ation Enable 0 = AutoNegotiation Disabled

1

Note: Can be overridden with ANEG pin

0.11

0.10

0.9

PDN

Powerdown 1 = Powerdown

Enable 0 = Normal

R/W

0

1

0

MII_DIS

MII Interface 1 = MII Interface Disabled

Disable 0 = Normal

ANEG_RST AutoNegoti- 1 = Restart AutoNegotiation Process, Bit Self

ation Reset Clearing After Reset Complete

0 = Normal

R/W

SC

0.8

0.7

DPLX

Duplex

Mode Select 0 = Half Duplex

Note: Can be overridden with DPLX pin

1 = Full Duplex

R/W

0

COLTST

Collision

1 = Collision Test Enabled

R/W

0

Test Enable 0 = Normal

0.6 thru

0.0

Reserved

60 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 11

Register 1 - Status Register Deﬁnition

1.15

CAP_T4

R

1.14

CAP_TXF

R

1.13

CAP_TXH

R

1.12

CAP_TF

R

1.11

CAP_TH

R

1.10

0

1.9

0

1.8

0

R

1.7

0

1.6

1.5

1.4

1.3

1.2

1.1

JAB

R/LH

1.0

EXREG

R

CAP_SUPR ANEG_ACK REM_FLT CAP_ANEG

LINK

R/LL

R

R/LH

R

Bit

Symbol

Name

Deﬁnition

R/W Def.

1.15

CAP_T4

100Base-T4

Capable

0 = Not Capable of 100Base-T4 Operation

R

0

1

0

1.14

1.13

1.12

1.11

CAP_TXF

100Base-TX Full 1 = Capable Of 100Base-TX Full Duplex

Duplex Capable

CAP_TXH 100Base-TX Half 1 = Capable Of 100Base-TX Half Duplex

Duplex Capable

CAP_TF

10Base-T Full

Duplex Capable

1 = Capable Of 10Base-T Full Duplex

1 = Capable Of 10Base-T Half Duplex

Reserved

CAP_TH

10Base-T Half

Duplex Capable

1.10

thru

1.7

1.6

1.5

1.4

CAP_SUPR MI Preamble

Suppression

0 = Not Capable of Accepting MI Frames

with MI Preamble Suppressed

R

0

Capable

ANEG_ACK AutoNegotiation

1 = AutoNegotiation Acknowledgement Pro-

Acknowledgment cess Complete

0 = AutoNegotiation Not Complete

REM_FLT

Remote Fault

Detect

1 = Remote Fault Detected. This bit is set R/LH

when Remote Fault Bit 5.13 is set.

0 = No Remote Fault

1.3

1.2

CAP_ANEG AutoNegotiation

Capable

1 = Capable of AutoNegotiation

R

1

0

LINK

Link Status

1 = Link Detected (Same as Bit 18.6

Inverted)

R/LL

0 = Link Not Detected

Register Description

61 of 118

April, 2002

Bit

Symbol

Name

Deﬁnition

R/W Def.

1.1

JAB

Jabber Detect

1 = Jabber Detect

0 = Normal

R/LH

R

0

1

1.0

EXREG

Extended Regis- 1 = Extended Registers Exist

ter Capable

Note: 1.15 Bit is Shifted First

Table 12

Register 2 - PHY ID Register 1 Deﬁnition

2.15

OUI3

R

2.14

OUI4

R

2.13

OUI5

R

2.12

OUI6

R

2.11

OUI7

R

2.10

OUI8

R

2.9

OUI9

R

2.8

OUI10

R

2.7

OUI11

R

2.6

OUI12

R

2.5

OUI13

R

2.4

OUI14

R

2.3

OUI15

R

2.2

OUI16

R

2.1

OUI17

R

2.0

OUI18

R

Bit

Symbol Name

Deﬁnition

OUI = 00-A0-7D

R/W Def.

2.15

2.14

2.13

2.12

2.11

2.10

2.9

2.8

2.7

2.6

2.5

OUI3

OUI4

CompanyID, Bits 3-18

R

0

1

0

1

0

OUI5

OUI6

OUI7

OUI8

OUI9

OUI10

OUI11

OUI12

OUI13

OUI14

OUI15

OUI16

OUI17

OUI18

2.4

2.3

2.2

2.1

2.0

Note: 2.15 Bit is Shifted First

62 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 13

Register 3 - PHY ID Register 2 Deﬁnition

3.15

OUI19

R

3.14

OUI20

R

3.13

OUI21

R

3.12

OUI22

R

3.11

OUI23

R

3.10

OUI24

R

3.9

PART5

R

3.8

PART4

R

3.7

PART3

R

3.6

PART2

R

3.5

PART1

R

3.4

PART0

R

3.3

REV3

R

3.2

REV2

R

3.1

REV1

R

3.0

REV0

R

Bit

Symbol Name

Deﬁnition

OUI = 00-A0-7D

R/W

Def.

3.15

3.14

3.13

3.12

3.11

3.10

OUI19

OUI20

OUI21

OUI22

OUI23

OUI24

Company ID, Bits 3-18

R

1

0

3.9

3.8

3.7

3.6

3.5

3.4

PART5

PART4

PART3

PART2

PART1

PART0

Manufacturer's Part Number

04

R

0

1

0

3.3

3.2

3.1

3.0

REV3

REV2

REV1

REV0

Manufacturer's Revision Number

Note: 3.15 Bit is Shifted First

–

Register Description

63 of 118

April, 2002

Table 14

Register 4 - AutoNegotiation Advertisement Register Deﬁnition

4.15

NP

4.14

ACK

R

4.13

RF

4.12

0

4.11

0

4.10

PAUSE

R/W

4.9

T4

4.8

TX_FDX

R/W

4.7

TX_HDX

R/W

4.6

10_FDX

R/W

4.5

0

4.4

0

4.3

0

4.2

0

4.1

0

4.0

CSMA

R/W

Bit

Symbol Name

Deﬁnition

R/W Def.

4.15

4.14

NP

Next Page Enable 0 = No Next Page

R/W

R

0

ACK

Acknowledge

1 = AutoNegotiation Word Recognized

0 = Not Recognized

4.13

RF

Remote Fault

1 = AutoNegotiation Remote Fault Detected R/W

0 = No Remote Fault

0

4.12 thru

4.11

Reserved

R/W

4.10

PAUSE PAUSE Frame

Capable

1 = Capable of Transmitting and Receiving

Pause Frames

R/W

0 = Not Capable

4.9

4.8

4.7

4.6

4.5

T4

100Base-T4

Capable

1 = Capable Of 100Base-T4

0 = Not Capable

R/W

0

1

0

1

TX_FDX 100Base-TX Full

Duplex Capable

1 = Capable of 100Base-TX Full Duplex

0 = Not Capable

TX_HDX 100Base-TX Half

Duplex Capable

1 = Capable Of 100Base-TX Half Duplex

0 = Not Capable

10_FDX 10Base-TX Full

Duplex Capable

1 = Capable Of 10Base-TX Full Duplex

0 = Not Capable

10_HDX 10Base-TX Half

Duplex Capable

1 = Capable Of 10Base-TX Half Duplex

0 = Not Capable

4.4 thru

4.1

Reserved

4.0

CSMA CSMA 802.3

Capable

1 = Capable of 802.3 CSMA Operation

0 = Not Capable

Note: 4.15 Bit is Shifted First

64 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 15

Register 5 - AutoNegotiation Remote Capability Deﬁntion

5.15

NP

R

5.14

ACK

R

5.13

RF

R

5.12

0

5.11

0

5.10

PAUSE

R

5.9

T4

R

5.8

TX_FDX

R

5.7

TX_HDX

R

5.6

10_FDX

R

5.5

0

5.4

0

5.3

0

5.2

0

5.1

0

5.0

CSMA

R

Bit

Symbol Name

Deﬁnition

R/W Def.

5.15

NP

ACK

RF

Next Page Enable 1 = Next Page Exists

0 = No Next Page

R

0

5.14

5.13

Acknowledge

1 = Received AutoNeg. Word Recognized

0 = Not Recognized

Remote Fault

Enable

1 = AutoNegotiation Remote Fault Detected

0 = No Remote Fault

5.12 thru

5.11

Reserved

5.10

PAUSE PAUSE Frame

Capable

1 = Capable of Transmitting and Receiving

Pause Frames

0 = Not Capable

5.9

5.8

5.7

5.6

5.5

T4

100Base-T4

Capable

1 = Capable Of 100Base-T4

0 = Not Capable

R

0

1

0

TX_FDX 100Base-TX Full

Duplex Capable

1 = Capable of 100BaseTx Full Duplex

0 = Not Capable

TX_HDX 100Base-TX Half

Duplex Capable

1 = Capable Of 100BaseTx Half Duplex

0 = Not Capable

10_FDX 10Base-TX Full

Duplex Capable

1 = Capable Of 10BaseTx Full Duplex

0 = Not Capable

10_HDX 10Base-TX Half

Duplex Capable

1 = Capable Of 10BaseTx Half Duplex

0 = Not Capable

5.4 thru

5.1

Reserved

5.0

CSMA CSMA 802.3

Capable

1 = Capable of 802.3 CSMA Operation

0 = Not Capable

Note: 5.15 Bit is Shifted First

Register Description

65 of 118

April, 2002

Table 16

Register 16 - Reserved

16.15

0

16.14

0

16.13

0

16.12

0

16.11

0

16.10

0

16.9

0

16.8

0

R/W

16.7

0

16.6

1

16.5

0

16.4

0

16.3

1

16.2

0

16.1

0

16.0

0

R/W

Bit

Symbol Name Deﬁnition

R/W

Def.

16.15 thru

16.0

—

Reserved for factory use. Must be written with

default values speciﬁed above for normal operation

—

66 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 17

Register 17 - Reserved

17.15

0

17.14

0

17.13

0

17.12

0

17.11

0

17.10

0

17.9

0

17.8

0

R/W

17.7

0

17.6

0

17.5

0

17.4

0

17.3

0

17.2

0

17.1

1

17.0

0

R/W

Bit

Symbol Name Deﬁnition

R/W

Def.

17.15 thru

17.0

—

Reserved for factory use. Must be written with

default values speciﬁed above for normal operation

—

Register Description

67 of 118

April, 2002

Table 18

Register 18 - Channel Status Output Register Deﬁnition

18.15

RPOL

R

18.14

DSYN_TO

R

18.13

18.12

18.11

R

18.10

R

18.9

CHAD1

R

18.8

CHAD0

R

18.7

R

18.6

18.5

18.4

18.3

CWRD

R/LT

18.2

SSD

R/LT

18.1

ESD

R/LT

18.0

JAB

R/LT

LINK_FAIL SPD_DET DPLX_DET

R/LT

Bit

Symbol

Name

Deﬁnition

R/W

Default

18.15

RPOL

Reversed

Polarity Detect

1 = Reversed Polarity Detect

0 = Normal

R

0

18.14

DSYN_TO

Loss of Syn-

chronization

Detect

1 = Descrambler Has Lost

Synchronization

0 = Normal

0

18.13

thru

18.10

Reserved

R

18.9

18.8

CHAD1

CHAD0

Channel

Address

11 = Accessing Channel 3

10 = Accessing Channel 2

01 = Accessing Channel 1

00 = Accessing Channel 0

11/10/

01/00

18.7

18.6

Reserved

R

0

1

LINK_FAIL

SPD_DET

DPLX_DET

CWRD

Link Fail Detect 1 = Link Not Detected

0 = Normal

R/LT

18.5

18.4

18.3

100/10 Speed

Detect

1 = Device in 100BaseTx Mode

0 = Device in 10 BaseT Mode

R/LT

0

Duplex Detect

1 = Device in Full Duplex Mode

0 = Device in Half Duplex Mode

Codeword

Error

1 = Invalid 4B5B Code Detected On

Receive Data

0 = Normal

18.2

SSD

Start of Stream

Error

1 = No Start of Stream Delimiter

Detected On Receive Data

0 = Normal

R/LT

0

68 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Bit

Symbol

Name

Deﬁnition

R/W

Default

18.1

ESD

End of Stream

Error

1 = No End of Stream Delimiter

Detected On Receive Data

0 = Normal

R/LT

0

18.0

JAB

Jabber Detect

1 = Jabber Detected

0 = Normal

R/LT

0

Note: 18.15 Bit Is Shifted First

Register 19 - Reserved

Table 19

19.15

0

19.14

0

19.13

0

19.12

0

19.11

0

19.10

0

19.9

19.8

0

R/W

19.7

0

19.6

1

19.5

1

19.4

1

19.3

1

19.2

1

19.1

1

19.0

1

R/W

Bit

Symbol Name Deﬁnition

R/W

Def.

19.15 thru

19.0

—

Reserved for factory use. Must be written with

default values speciﬁed above for normal operation

—

Register Description

69 of 118

April, 2002

Table 20

Register 20 - Reserved

20.15

0

20.14

0

20.13

0

20.12

0

20.11

0

20.10

0

20.9

0

20.8

0

R/W

20.7

0

20.6

0

20.5

0

20.4

0

20.3

0

20.2

0

20.1

0

20.0

0

R/W

Bit

Symbol Name Deﬁnition

R/W

Def.

20.15 thru

20.0

—

Reserved for factory use. Must be written with

default values speciﬁed above for normal operation

—

Note: 20.15 Bit Is Shifted First

4 Application Information

4.1 Example Schematics

A typical example of the L84225 used for a switching hub application in

twisted pair mode is shown in Figure 11; an example of the L84225 used

in ﬁber mode is shown in Figure 12.

4.2 TP Interface

4.2.1 Transmit Interface

The interface between the TP outputs on TPOP/N and the twisted pair

cable is typically transformer coupled and terminated with the two

resistors as shown in Figure 11.

The transformer for the transmitter is recommended to have a winding

ratio of 1:1 with the center tap of the primary winding tied to VDD, as

shown in Figure 11. The speciﬁcations for such a transformer are shown

in Table 21. Sources for quad transformers compatible with the L84225

are listed in Table 22. Note that both “Stacked” and “Non-Stacked” pinout

types are listed. The Stacked and Non-Stacked designation refers to the

70 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

type of RJ-45 connector used on the secondary side (line side) of the

transformer. The pinout of these types differ slightly so that traces to the

magnetics may be kept as short and direct as possible.

The "non-stacked" RJ-45 (also referred to as harmonica) is a traditional

horizontally oriented connector consisting of four RJ-45 jacks in a single

in-line assembly.

The newer "stacked" connector consists of a two-over-two conﬁguration

so that four RJ-45 jacks are located in the footprint area of two side-by-

side connectors. This is a signiﬁcant improvement for higher density

multi-port applications and smaller system form-factors.

The L84225 pin-out has been optimized for connection to transformers

and connectors designed for the higher density stacked conﬁguration.

The Quad Transceiver also operates with non-stacked connectors using

either transformers that map the pin-out to the non-stacked conﬁguration,

or using trace "crossovers" on the PCB layout.

The transformers listed with "non-stacked" pinouts use crossover

connections inside the part to map the stacked pinout of the L84225 to

non-stacked RJ-45 connectors. Crossovers internal to the transformer

are not made in a controlled impedance environment, so this can impact,

somewhat, the cross-talk performance of the system.

For best cross-talk and system performance, it is suggested that stacked

connector and transformer conﬁgurations be used. Alternately, non-

stacked connectors may be used with stacked transformer types and the

crossover wiring can be put on the pc board using a ground plane to

reduce impedance mismatch.

The transmit output needs to be terminated with two external termination

resistors in order to meet the output impedance and return loss

requirements of IEEE 802.3. It is recommended that these two external

resistors be connected from VDD to each of the TPOP/N outputs, and

their value should be chosen to provide the correct termination

impedance when looking back through the transformer from the twisted

pair cable, as shown in Figure 11. The value of these two external

termination resistors depends on the type of cable driven by the device.

Refer to the Cable Selection Section for more details on choosing the

value of these resistors.

Application Information

71 of 118

April, 2002

To minimize common mode output noise and to aid in meeting radiated

emissions requirements, it may be necessary to add a common mode

choke on the transmit outputs as well as add common mode bundle

termination. The transformers listed in Table 22 all contain common

mode chokes on both the transmit and receive sides, as shown in

Figure 11. Common mode bundle termination is achieved by tying the

unused pairs in the RJ45 to chassis ground through 75 ohm resistors

and a 0.01 uF capacitor, as shown in Figure 11.

To minimize noise pickup into the transmit path in a system or on a PCB,

the loading on TPOP/N should be minimized and both outputs should

always be loaded equally.

Table 21

TP Transformer Speciﬁcation

Speciﬁcation

Parameter

Transmit

Receive

Turns Ratio

1:1 CT

350

0.2

1:1

350

0.2

15

Inductance, (uH Min)

Leakage Inductance, (uH)

Capacitance (pF Max)

DC Resistance (Ohms Max)

15

0.4

72 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Figure 11

Typical Switching Hub Port Schematic Using the L84225 in Twisted Pair

Mode

19

50 50

TXCLK_3 VDD

TXD3_3

TXD2_3

TXD1_3

TXD0_3

TXEN_3

TXER_3

COL_3

RXCLK_3

RXD3_3

RXD2_3

RXD1_3

RXD0_3

CRS_3

1%

1:1

L84302

TPOP_3

TPON_3

16 MII

or

6 RMII

1

2

RJ45

QUAD

4

5

7

8

3

6

Switch

Fabric

100/10 MB

Ethernet

Controller

25

TPIP_3

TPIN_3

0.01

RXDV_3

RXER_3

25

75

L84225

TXCLK_0

TXD3_0

TXD2_0

TXD1_0

TXD0_0

TXEN_0

TXER_0

COL_0

RXCLK_0

RXD3_0

RXD2_0

RXD1_0

RXD0_0

CRS_0

0.01

16 MII

or

6 RMII

50 50

1%

1:1

TPOP_0

TPON_0

1

2

RXDV_0

RXER_0

RJ45

4

5

7

8

3

6

MDIO, MDC

25

TPIP_0

TPIN_0

0.01

16

LED[3:0]_[3:0]

25

REGDEF

DPLX[3:0]

SPEED[3:0]

ANEG

REPEATER

RMII_EN

75

REXT

10 K

0.01

PINSTRAP

AD_REV

LEDDEF

4

SD_[3:0]/

FXEN_[3:0]

System Reset

System Clock

RESET

CLKIN

SD_THR

GND

18

Application Information

73 of 118

April, 2002

Figure 12

Typical Switching Hub Port Schematic Using the L84225 in FX Mode with

3.3 V Transceivers

19

GEN

70

GEN

70

VDD

TXCLK_3

TXD3_3

TXD2_3

TXD1_3

TXD0_3

TXEN_3

TXER_3

COL_3

RXCLK_3

RXD3_3

RXD2_3

RXD1_3

RXD0_3

CRS_3

VDD

TD

FXOP_3

FXON_3

TDB

GEN

127

GEN

127

GEN

173

GEN

173

16

RD

RDB

FXIP_3

FXIN_3

3.3 V

Optic

Transceiver

QUAD

Switch

Fabric

GEN

83

GEN

83

RXDV_3

RXER_3

100/10 MB

Ethernet

Controller

GEN

127

L84225

SD

GEN

83

TXCLK_0

TXD3_0

TXD2_0

TXD1_0

TXD0_0

TXEN_0

TXER_0

COL_0

16

RXCLK_0

RXD3_0

RXD2_0

RXD1_0

RXD0_0

CRS_0

GEN

70

VDD

TD

FXOP_0

FXON_0

TDB

RXDV_0

RXER_0

GEN

127

GEN

127

GEN

173

GEN

173

2

RD

MDIO/MDC

RDB

FXIP_0

FXIN_0

3.3 V

Optic

Transceiver

16

LED[3:0]_[3:0]

GEN

83

GEN

83

GEN

REGDEF

DPLX[3:0]

SPEED[3:0]

ANEG

REPEATER

RMII_EN

127

SD

SD_0

GEN

83

PINSTRAP

AD_REV

LEDDEF

REXT

10 K

SD_THR

System Reset

System Clock

RESET

CLKIN

GND

18

74 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Table 22

Vendor

TP Transformer Sources

Part Number

Pin Out Type

Pulse

bel

H1062

Stacked

S558-5999B47

6931-30

Stacked

nano pulse

Valor

Stacked

ST6179

Stacked

Halo

TG110-S453NX

H1053

Stacked

Pulse

bel

Non-Stacked

S558-5999-J5

6949-30

nano pulse

Valor

ST6403P

Halo

TG110-S456NX

4.2.2 Receive Interface

Receive data is typically transformer coupled into the receive inputs on

TPIP/N and terminated with an external resistor as shown in Figure 11.

The transformer for the receiver is recommended to have a winding

ration of 1:1, as shown in Figure 11. The speciﬁcations for such a

transformer are shown in Table 21. Sources for the transformer are listed

in Table 22.

The receive input needs to be terminated with the correct termination

impedance to meet the input impedance and return loss requirements of

IEEE 802.3. In addition, the receive TP inputs need to be attenuated. It

is recommended that both the termination and attenuation be

accomplished by placing four external resistors in series across the

TPIP/N inputs as shown in Figure 11. The resistors should be

25%/25%/25%/25% of the total series resistance, and the total series

resistance should be equal to the characteristic impedance of the cable

(100 ohms for UTP, 150 Ohms for STP). For 100 Ohm twisted pair, the

resistor string values should be 25 Ohms each (1%). It is also

recommended that a 0.1uF capacitor be placed between the center of

Application Information

75 of 118

April, 2002

the series resistor string and Vcc in order to provide an AC ground for

attenuating common mode signal at the input. This capacitor is also

shown in Figure 11.

To minimize common mode input noise and to aid in meeting

susceptibility requirements, it may be necessary to add a common mode

choke on the receive input as well as add common mode bundle

termination. The transformers listed in Table 22 contain common mode

chokes on both the transmit and receive sides, as shown in Figure 11.

Common mode bundle termination is achieved by tying the receive

secondary center tap and the unused pairs in the RJ45 to chassis ground

through 75 ohm resistors and a 0.01 uF capacitor, as shown in Figure 11.

In order to minimize noise pickup into the receive path in a system or on

a PCB, the loading on TPIP/N should be minimized and both inputs

should be loaded equally.

4.3 TP Transmit Output Current Set

The TPOP/N output current level is set by an external resistor tied

between REXT and GND. This output current is determined by the

following equation where R is the value of REXT:

I

= (10K/R) I

ref

out

Where I

= 40 mA (100 Mbps, UTP)

ref

= 32.6 mA (100 Mbps, STP)

= 100 mA (10 Mbps, UTP)

= 81.6 mA (10 Mbps, STP)

For 100 Ohm UTP, REXT should be typically set to 10K ohms and REXT

should be a 1% resistor in order to meet IEEE 802.3 speciﬁed levels.

Once REXT is set for the 100 Mbps and UTP modes as shown by the

equation above, Iref is then automatically changed inside the device

when the 10 Mbps mode or UTP120/STP150 modes are selected as

described in Section 5.3, “Twisted Pair Characteristics, Transmit,”

page 89.

Keep resistor REXT as close to pins REXT and GND as possible in order

to reduce noise pickup into the transmitter.

Since the TP output is a current source, capacitive and inductive loading

can reduce the output voltage level from the ideal. Thus, in an actual

76 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

application, it might be necessary to adjust the value of the output current

to compensate for external loading. The TP output level can be adjusted

by changing the value of the external resistor tied to RXT.

4.4 Transmitter Droop

The IEEE 802.3 speciﬁcation has a transmitter output droop requirement

for 100BaseTX. Since the L84225 TP output is a current source, it has

no perceptible droop by itself. However, the open circuit inductance of the

transformer added to the device transmitter output as shown in Figure 11

will cause droop to appear at the transmit interface to the TP wire. If the

transformer connected to the L84225 outputs meets the requirements in

Table 21, the transmit interface to the TP cable will meet the IEEE 802.3

droop requirements.

4.5 Fiber Interface

4.5.1 General

The L84225 uses a PECL-type driver/receiver to achieve a throughput of

100 Mbps across a differential ﬁber interface. The interface comprises

four signals: FXOP/ FXON (output) and FXIP/FXIN (input).

Some Fiber transceivers modules that will work with the L84225 are

shown in Table 23. The Siemens Fiber Transceiver V23809-C8-C10

operates at 3.3V for use with the L84225. 5V Fiber modules such as the

HP HFBR-5103 will also operate with the proper termination network

described later.

Table 23

Vendor

Fiber Transceiver Modules

3.3V

5V

Siemens¹

HP

V23809-C8-C10

Available Soon

Contact Supplier

V23809-C8-C10

HFBR-5103

269040-1

Amp

1. Siemens part operates at both 3.3V and 5V supply values.

The L84225 ﬁber interface is enabled for each channel independently if

a valid PECL Fiber signal is tied to the SD_[3:0]/FXEN_[3:0] pins; the

Application Information

77 of 118

April, 2002

ﬁber interface is disabled (and the TP interface enabled) by connecting

the SD_[3:0]/FXEN_[3:0] pins to GND for that channel.

AutoNegotiation and the scrambler/descrambler are disabled when the

ﬁber interface is enabled.

The voltage applied to the SD_THR pin sets the input reference level of

the ﬁber interface for the single ended Signal Detect inputs only. If a 3.3

V ﬁber transceiver is used with the L84225, this pin should be tied to

GND. If a 5 V ﬁber transceiver is used, this pin needs to be tied to

VCC(3.3V)-1.3 V (about 2V), but referenced to the 5V supply of the ﬁber

transceiver. An easy way to do this is with a 15K:10K voltage divider from

the 5 V supply to ground, with the center point of the divider connected

to SD_THR, as shown in Figure 14.

4.5.2 Operation with 3.3V Fiber Transceivers

Termination on the differential outputs of the ﬁber transceiver module

must be observed for proper impedance matching, which is normally the

equivalent of 50 Ohms single ended. The terminating resistor values are

shown in Figure 13 for FXOP/FXON (outputs), FXIP/ FXIN (inputs) and

SD_[3:0]/FXEN_[3:0] (inputs) for use with 3.3V ﬁber modules. The

calculated termination resistors on FXOP/FXON are a pull-up of 69.8

Ohms to 3.3V and a pulldown of 174 Ohms to ground.

The termination network at the ﬁber inputs (FXIP/FXIN and

SD_[3:0]/FXEN_[3:0]) of the L84225 is speciﬁed by the ﬁber module

manufacturer and will normally be a pull-up of 127 Ohms to 3.3V and a

pulldown of 82.5 Ohms to GND, as shown in Figure 13. Note that the

Input and Output termination resistor values are different since the output

driver of the Fiber module and the L84225 have a different structure. The

interface network for 3.3V ﬁber transceiver modules is shown in

Figure 13.

78 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Figure 13

FX Interface to 3.3V Fiber Modules

3.3V

69.8

VDD = 3.3V

TD

TD-

FXOP

FXON

3.3 V

Fiber

127

174

L84220

Transceiver

10/100 TX/FX

Transceiver

RD

RD-

SD

FXIP

127

FXIN

82.5

SD/FXEN

SD_THR

82.5

4.5.3 Operation with 5V Fiber Transceivers

It is also possible to use the L84225 with 5V ﬁber modules by changing

the resistive termination network slightly.

Since the L84225 FXOP/FXON Outputs are 5V tolerant, the output

termination resistors should be a pull-up of 61.9 Ohms to the 5V supply,

and a pulldown of 261 Ohms to GND, as shown in Figure 14. This

provides an Output High Voltage of 4.05V, and a low of about 3.3V to the

ﬁber module.

The termination network on the FXIP/FXIN inputs of the L84225 must be

modiﬁed for operation with 5V modules by adding a third resistor as a

“tap” on the pulldown leg, as shown in Figure 14. This divides down the

voltage seen at the input of the L84225 so that it does not exceed the

range of the input buffer. The pull-up resistor recommended by the 5V

module supplier generally remains the same - usually about 82.5 Ohms

to the 5V supply. The normally recommended 125-Ohm pulldown resistor

must be split into two. The values of this new pair should be 52.3 Ohms

connected to the pull-up resistor and 73.2 Ohms connected from the

Application Information

79 of 118

April, 2002

52.3-Ohm resistor to ground, providing a voltage divider function at the

junction of the pair. The junction of these two resistors should be

connected to the FXIP/FXIN and SD_[3:0]/FXEN_[3:0] inputs of the

L84225. This will provide a High PECL logic level of 2.36V and a low of

1.92V, which is sufﬁcient for operation of the L84225. An interface

suitable for operation with 5V ﬁber transceiver modules is shown below

in Figure 14.

Figure 14

FX Interface to 5V Fiber Modules

VDD=5V

3.3V

61.9

VDD = 3.3V

VDD = 5V

TD

TD-

FXOP

FXON

5V

82.5

Fiber

261

L84220

Transceiver

10/100 TX/FX

Transceiver

RD

RD-

52.3

73.2

82.5

FXIP

SD

FXIN

SD/FXEN

SD_THR

52.3

73.2

15K

10K

4.6 MII Controller Interface

4.6.1 General

The MII controller interface allows the L84225 to connect to any external

Ethernet controller without any glue logic, provided that the external

Ethernet controller has an MII interface that complies with IEEE 802.3 as

shown in Figure 11 and Figure 12.

80 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

The L84225 also offers RMII (Reduced MII) interface as a selectable

option for use with controllers (MACs) supporting RMII operation. By

holding the RMII_EN pin high, the RMII interface is enabled, cutting the

required interface signals from 16 to 6. This is a signiﬁcant savings in

board interconnect for high port count systems.

For normal MII operation, the RMII_EN pin should be tied to GND. Refer

to the RMII description in Section 2 for details of the interface operation.

4.6.2 Clocks

Standard Ethernet controllers with an MII use TXCLK to clock data in on

inputs TXD[3:0]. TXCLK is speciﬁed in IEEE 802.3 and on the L84225

to be an output. The L84225 requires a 25 MHz reference frequency in

MII mode, and 50 MHz in RMII mode. This reference frequency must be

applied to the CLKIN pin. CLKIN generates TXCLK inside the L84225;

thus, data can be clocked into the L84225 on the rising edge of output

clock TXCLK or on the rising edge of input clock CLKIN.

If a nonstandard controller is used to interface to the L84225, or in

Repeater Applications, there may be a need to clock TXD[3:0] into the

L84225 on the rising edge CLKIN. Where CLKIN is used as the input

clock, TXCLK can be left open or used for another purpose.

4.6.3 MII Disable

The MII outputs can be placed in the high impedance state and inputs

disabled by setting the MII disable bit in the MI serial port Control

register. When this bit is set to the disable state, the TP and FX outputs

are both disabled and transmission is inhibited. The default value of this

bit when the device powers up or is reset is dependent on the device

address. If the device address latched into PHYAD[4:0] at reset is 11111,

it is assumed that the device is being used in applications where there

maybe more than one device sharing the MII bus, like external PHYs or

adapter cards, so the device powers up with the MII interface disabled.

If the device address latched into PHYAD[4:0] at reset is not 11111, it is

assumed that the device is being used in an application where it is the

only device on the MII bus, like hubs, so the device powers up with the

MII interface enabled.

Application Information

81 of 118

April, 2002

4.7 FBI Controller Interface

The FBI (Five Bit Interface) controller interface has the same

characteristics of the MII except that the data path is ﬁve bits wide,

instead of 4 bits wide per the MII. The ﬁve-bit-wide data path is

automatically enabled when the 4B5B encoder is bypassed. Because of

this encoder/ decoder bypass, the FBI is used primarily for repeaters or

other applications where the PHY encoding/decoding function is not

needed. For more details about the FBI, see the Non-MII Based

Repeaters Section.

4.8 Repeater Applications

4.8.1 MII Based Repeaters

The L84225 can be used as the physical interface for MII based

repeaters by using the standard MII/RMII as the interface to the repeater

core.

For most repeaters, it is necessary to disable the internal CRS loopback.

This can be done by asserting the repeater input of the chip.

For some particular types of repeaters, it may be desirable to either

enable or disable AutoNegotiation, force Half Duplex operation, and

enable either 100 Mbps or 10 Mbps operation. All of these modes can

be conﬁgured by either asserting the appropriate hardware pins or by

setting the appropriate bits in the MI serial port Control register.

4.8.2 Clocks

Normally, transmit data sent over the MII/RMII/FBI is clocked into the

L84225 by the rising edge of the output clock TXCLK. It may be desirable

or necessary in some repeater applications to clock in transmit data from

a master clock from the repeater core. This would require that transmit

data be clocked in on the edge of an input clock. An input clock is

available for clocking in data on TXD by the rising edge on the CLKIN

pin. Notice from the timing diagrams that CLKIN generates TXCLK, and

TXD data is clocked in on TXCLK edges. This means that TXD data is

also clocked in on the CLKIN edge as well. Thus, an external clock

driving the CLKIN input can also be used as the clock for TXD.

82 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

4.9 Serial Port

4.9.1 General

The L84225 has an MI serial port to set all of the devices' conﬁguration

inputs and read out the status outputs. Any external device that has an

IEEE 802.3 compliant MI interface can connect directly to the L84225

without any glue logic, as shown in Figure 11 and Figure 12.

As described earlier, the MI serial port consists of ﬁve lines: MDC, MDIO,

and PHYAD[4:2]. However, only 2 lines, MDC and MDIO, are needed to

shift data in and out.

PHYAD[4:2] deﬁne the three most signiﬁcant bits of the PHY address, as

described in Section 4.9.3, “Serial Port Addressing,” page 83.

4.9.2 Polling vs. Interrupt

The status output bits can be monitored by either polling the serial port

or with the interrupt output.

If polling is used, the registers can be read at regular intervals and the

status bits can be checked against their previous values to determine any

changes. To make polling simpler, all the registers can be accessed in a

single read or write cycle by setting the register address bits REGAD[4:0]

to 11111 and adding enough clocks to read out all the bits, provided the

multiple register access feature has been enabled.

4.9.3 Serial Port Addressing

The device address for the MI serial port is selected by connecting the

PHYAD[4:2] pins to the desired value. The PHYAD[1:0] addresses are

internally hardwired for each channel as shown in both Table 6 and

Table 8.

4.10 Unmanaged Port Conﬁguration

The L84225 has conﬁguration inputs which can “over-ride” the default

conﬁguration state obtained on POWER-UP or RESET of the device.

Use of these pins ANEG, SPEED_[3:0], and DPLX_[3:0] allow selection

of Global AutoNegotiation, Individual Port Speed (10/100), and Individual

Port Duplex (Full/Half), by properly strapping these pins to VDD or VSS

Application Information

83 of 118

April, 2002

as shown in Table 24. Note that these pins should not ﬂoat, but must be

connected either High or Low for proper operation.

In order to obtain the “Default Mode of Operation”, i.e.: Auto-negotiation

enabled, 100MBs, and Half Duplex; the ANEG, SPEED_[3:0], and

DPLX_[3:0] pins should be set to 1,1,0 respectively.

Table 24

Hardware Conﬁguration

Auto-Negotiate Speed

Conﬁguration

State

Duplex

Advertise 10/100 Advertise Full/Half

Normal

Enabled

(POC/RESET)

Conﬁg Pins

ANEG=1

SPEED_[3:0]=1

10MBs

DPLX_[3:0]=0

Full

Complement State Disabled

Conﬁg Pins ANEG=0

SPEED_[3:0]=0

DPLX_[3:0]=1

4.11 Long Cable

IEEE 802.3 speciﬁes that 10BaseT and 100BaseTX operate over twisted

pair cable lengths from 0 to 100 meters. The squelch levels can be

reduced by 4.5 dB if the receive level adjust bit is appropriately set in the

MI serial port Channel Conﬁguration register, which will allow the L84225

to operate with up to 150 meters of twisted pair cable. The equalizer is

already designed to accommodate between 0 to 150 meters of cable.

4.12 Clock

The L84225 requires a 25 MHz reference frequency for internal signal

generation in MII mode, and 50 MHz in RMII mode. The appropriate

reference frequency must be applied to the CLKIN pin.

4.13 LED Drivers

The LED[3:0] outputs can all drive LED’s tied to VDD as shown in

Figure 11 and Figure 12. In addition, the LED[3:0] outputs can drive

LEDs tied to GND as well. The LED deﬁnitions assume that the LED

84 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

outputs are tied to VDD, active low signals (otherwise the LED outputs

will indicate their respective opposite events.)

The LEDDEF pin determines the default settings for LED[3:0]. If LEDDEF

= 0, the default functions for LED[3:0] are Link 100, Activity, Full Duplex,

and Link 10, respectively. If LEDDEF = 1, the LED functions for LED[3:0]

are forced to LINK + ACTIVITY, Collision, Full Duplex and 10/100 Mbps

operation, respectively. Table 4 deﬁnes the LED functions. Table 5

deﬁnes the LED events.

The LED[3:0] outputs can also drive other digital inputs. Thus, LED[3:0]

can also be used as digital outputs whose function can be user deﬁned

and controlled through the MI serial port.

4.14 5V Compatible I/O Operation

The input and output pins of the L84225 are tolerant of signal levels up

to a maximum of 5.5V (including overshoot etc.). This allows the

transceiver to be operated with 5V controllers that have TTL I/O

characteristics (0.8 to 2.0V Input levels) without the use of levelshifters

or other interfaces.

Controllers and other system components may be operated with 5V

supplies and all inter-chip signals may be connected directly to the

L84225. All required external logic levels must retain TTL compatibility

since the L84225 outputs are not guaranteed to achieve higher than 2.3V

with a load of 10ma. However, the inputs of the L84225 will tolerate TTL

or CMOS logic levels being driven into the device.

This should make replacement of the Physical Layer transceivers in

existing designs quite simple since any 5V devices do not need to be

changed.

4.15 Power Supply Decoupling

There are 18 VDDs and 19 GNDs on the L84225.

All VDDs on each individual side should be connected together

(grouped) and tied to a power plane, as close as possible to the L84225

supply pins. If the VDDs vary in potential by even a small amount, noise

and latchup can result. The L84225 VDD pins should be kept to within

50 mV of each other.

Application Information

85 of 118

April, 2002

All GNDs should be connected as close as possible to the device with a

large ground plane. If the GNDs vary in potential by even a small

amount, noise and latchup can result. The GND pins should be kept to

within 50 mV of each other.

A 0.01-0.1uF decoupling capacitor should be connected between the

VDD group and GND on each of the 4 sides of the L84225 as close as

possible to the device pins, preferably within 0.5 in. The value should be

chosen depending on whether the noise from VDD-GND is high or low

frequency. A conservative approach would be to use two decoupling

capacitors on each side, one 0.1uf for low frequencies, and one 0.001 uf

for high frequency noise on the power supply.

The VDD connection to the transmit transformer center tap shown in

Figure 11 and Figure 12 must be well decoupled in order to minimize

common mode noise injection from the supply into the twisted pair cable.

It is recommended that a 0.01 uF decoupling capacitor be placed

between the transformer center tap VDD connection and the L84225

GND plane. This decoupling capacitor should be physically placed as

close as possible to the transformer center tap, preferably within 0.5 in.

The PCB layout and power supply decoupling discussed above should

provide sufﬁcient decoupling to achieve the following when measured at

the device:

1. the resultant AC noise voltage measured across each VDD/GND set

should be less than 100 mVpp,

2. all VDDs should be within 50 mVpp of each other, and

3. all GNDs should be within 50 mVpp of each other.

86 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

5 Speciﬁcations

5.1 Absolute Maximum Ratings

Absolute maximum ratings are limits beyond which may cause

permanent damage to the device or affect device reliability. All voltages

are speciﬁed with respect to GND, unless otherwise speciﬁed.

•

V

Supply Voltage

-0.3 V to +4.0 V

-0.3 V to 5.5 V

3.0 Watt @ 70 C

-65 to +150 C

-10 to +80 C

DD

All Inputs and Outputs

Package Power Dissipation

Storage Temperature

Temperature Under Bias

Lead Temperature (Soldering, 10 Sec) 260 C

Body Temperature (Soldering, 30 Sec) 220 C

Note that all inputs and outputs are 5V tolerant.

Speciﬁcations

87 of 118

April, 2002

5.2 DC Electrical Characteristics

Unless otherwise noted, all test conditions are as follows:

1. T = 0 to +70 C

A

2. V = 3.3 V 5%

DD

3. 25 MHz 0.01%

4. REXT = 10K 1%,no load

Limit

Sym. Parameter

Min

Typ

Max

Unit

Conditions

V_IL

V_IH

I_IL

Input Low Voltage

0.8

Volt

uA

Input High Voltage

Input Low Current

2

1

VIN = GND

All Except RESET

10

50

1

uA

VIN = GND RESET

VIN = VDD

I_IH

Input High Current

V_OLOutput Low

Voltage

0.4

1

Volt

IOL = -4 mA, Except LED[3:0]

IOL = -20 mA, LED[3:0]

V_OHOutput High

Voltage

VDD -1.0

IOH = 4 mA

All Except LED[3:0]

VDD -1.0

2.4

Volt

pF

IOH = 10 mA, LED[3:0]

IOH = 10 uA

C_IN

I_DD

Input Capacitance

5

VDD Supply

Current

450

700

mA

Transmitting 100%, 100 Mbps

Transmitting 100%, 10 Mbps

I_GNDGND Supply

Current

Transmitting 100%, 100 Mbps,

Note 1

700

200

mA

uA

Transmitting 100%, 10 Mbps,

Note 1

Powerdown

Note 1. IGND includes current ﬂowing into GND from the external

resistors and transformer on TPOP/TPON, as shown in Figure 11.

88 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

5.3 Twisted Pair Characteristics, Transmit

Unless otherwise noted, all test conditions are as follows:

1. T = 0 to +70 C

A

2. V = 3.3 V 5%

DD

3. 25 MHz 0.01%

4. REXT = 10K 1%,no load

5. TPOP/N loading shown in Figure 11, or equivalent

Limit

Sym. Parameter

T_OVTP Differential Output

Min

Typ

Max

Unit

Conditions

0.950 1.000 1.050

V pk

100 Mbps, UTP Mode, 100

Ohm load

Voltage

1.165 1.225 1.285

V pk

%

100 Mbps, STP Mode, 150

Ohm load

2.2

2.5

2.8

10 Mbps, UTP Mode, 100 Ohm

load

2.694 3.062 3.429

10 Mbps, STP Mode, 150 Ohm

load

T_OVSTP Differential Output

Voltage Symmetry

98

102

100 Mbps, ratio of positive and

negative amplitude peaks on

TPOP/N

T_ORFTP Differential Output

Rise And Fall Time

3.0

5.0

0.5

ns

100 Mbps

T_ORFSTP Differential Output

Rise And Fall Time

Symmetry

100 Mbps, difference between

rise and fall times on TPOP/N

T_ODCTP Differential Output

Duty Cycle Distortion

0.25

ns

100 Mbps, output data=0101...

NRZI Pattern Unscrambled,

measure at 50% Points

T_OJ

TP Differential Output

Jitter

0.7

5.0

ns

%

100 Mbps, Output Data=Scram-

bled /H/

T_OO

TP Differential Output

Overshoot

100 Mbps

10 Mbps

T_OVTTP Differential Output

Voltage Template

See Figure 4

See Figure 6

T_SOI

TP Differential Output

SOI Voltage Template

Speciﬁcations

89 of 118

April, 2002

Limit

Sym. Parameter

Min

Typ

Max

Unit

Conditions

T_LPT

T_OIV

T_OIA

TP Differential Output

Link Pulse Voltage

Template

See Figure 7

10 Mbps, NLP and FLP

TP Differential Output

Idle Voltage

50

42

mV

10 Mbps, Measured on Sec-

ondary Side of Xfmr in

Figure 11

TP Output Current

38

40

mA pk 100 Mbps, UTP with

TLVL[3:0]=1000

31.06 32.66 34.26 mA pk 100 Mbps, STP with

TLVL[3:0]=1000

88

100

112

mA pk 10 Mbps, UTP with

TLVL[3:0]=1000

71.86 81.64 91.44 mA pk 10 Mbps, STP with

TLVL[3:0]=1000

T_OIR

TP Output Current

Adjustment Range

0.80

1.2

Adjustable with REXT, Relative

to TOIA with REXT=10K

0.86

1.16

Adjustable with TLVL[3:0]. See

Section 4.3, “TP Transmit Out-

put Current Set.” Relative to

Value at TLVL[3:0]=1000.

T_ORATP Output Current

TLVL Step Accuracy

50

%

Relative to Ideal Values in Table

2. Values Relative to Output

with TLVL[3:0]=1000.

T_OR

T_OC

TP Output Resistance

10K

15

Ohm

pF

TP Output

Capacitance

90 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

5.4 Twisted Pair Characteristics, Receive

Unless otherwise noted, all test conditions are as follows:

1. T = 0 to +70 C

A

2. V = 3.3 V 5%

DD

3. 25 MHz 0.01%

4. REXT = 10K 1%,no load

5. 62.5/10 MHz Square Wave on TP inputs in 100/10 Mbps

Limit

Sym. Parameter

R_STTP Input Squelch

Min

Typ

Max

Unit

Conditions

166

310

60

500

540

200

378

300

324

180

227

mV pk 100 Mbps, RLVL=0

mV pk 10 Mbps, RLVL=0

mV pk 100 Mbps, RLVL=1

mV pk 10 Mbps, RLVL=1

mV pk 100 Mbps, RLVL=0

mV pk 10 Mbps, RLVL=0

mV pk 100 Mbps, RLVL=1

mV pk 10 Mbps, RLVL=1

Threshold

217

100

186

60

R_UT

TP Input Unsquelch

Threshold

130

R_OCVTP Input Open Circuit

Voltage

V_DD- 2.4

0.2

Volt

Voltage on either

TPIP or TPIN with

respect to GND

R_CMRTP Input Common Mode

Voltage Range

R_OCV

0.25

Voltage on either

TPIP or TPIP with

respect to GND

R_DR

TP Input Differential Volt-

age Range

V_DD

R_IR

R_IC

TP Input Resistance

TP Input Capacitance

5K

ohm

pF

10

Speciﬁcations

91 of 118

April, 2002

5.5 Fiber Interface Characteristics, Transmit and Receive

Unless otherwise noted, all test conditions are as follows:

1. T = 0 to +70 C

A

2. V = 3.3 V 5%

DD

3. 25 MHz 0.01%

4. REXT = 10K 1%,no load

5. FXOP/N loading shown in Figure 12 or equivalent

Limit

Sym.

Parameter

Min

Typ

Max

Unit Conditions

F_OVH

Fiber Output Level,

High

V_DD

1.020

-

V_DD

0.880

-

V

Single ended FXOP/N rela-

tive to GND

F_OVL

F_DIV

F_CMR

F_SDIH

Fiber Output Level,

Low

V_DD

1.810

-

V_DD

1.620

-

Single ended FXOP/N rela-

tive to GND

Fiber Differential

Input Voltage

0.150

FXIP/N

Fiber Input Common

Mode Voltage Range

1.35

V_DD-0.8

FXIP/N

SD/FXEN Input High V_{SD_THR}

Voltage

This spec applies when

device is connected to 5 V

external ﬁber optic trans-

ceivers. V_{SD_THR}is the

-50 mV

voltage applied to the

SD_THR pin and is spec’ed

by F_SDTHR

.

VCC -

1.165

V

This spec applies when

device is connected to 3.3V

external ﬁber optic trans-

ceivers. SD_THR is tied to

GND.

92 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Limit

Typ

Sym.

Parameter

Min

Max

Unit Conditions

V This spec applies when

F_SDIL

SD/FXEN Input Low

Voltage

V_{SD_THR}

+50 mV

device is connected to 5V

external ﬁber optic trans-

ceivers. V_{SD_THR}is the

voltage applied to the

SD_THR pin and is spec’ed

by FSDTHR.

VCC-

1.475

This spec applies when

device is connected to 3.3V

external ﬁber optic trans-

ceivers. SD_THR is tied to

GND.

F_SDTHRSD_THR Input

Voltage

VCC

–1.3 V

–10%

VCC

1.3 V

VCC

–1.3 V

+10%

V

This spec applies when

device is connected to 5V

external ﬁber optic trans-

ceivers. When interfacing to

3.3V ﬁber optic transceiv-

ers, SD_THR is tied to

GND.

F_DIS

Fiber Interface Dis-

able Voltage,

SD/FXEN Pin

0.45

0.85

V

For disabling ﬁber interface

F_LVL

Internal/External

Signal Detect Level

Select, SD_THR Pin

For selecting interface to

either 3.3V or 5 V external

ﬁber transceivers

5.6 AC Test Timing Conditions

Unless otherwise noted, all test conditions are as follows:

1. T = 0 to +70 C

A

2. V = 3.3 V 5%

DD

3. 25 MHz 0.01%

4. REXT = 10K 1%,no load

5. Input conditions:

All inputs:

tr,tf <= 10 ns, 20-80%

6. Output Loading

TPOP/N:

Same as Figure 11 or equivalent, 10 pF

REGDEF:

All other digital outputs:

1K pullup, 50 pF

25 pF

Speciﬁcations

93 of 118

April, 2002

7. Measurement Points:

TPOP/N, TPIP/N:

0V during data, 0.3V at start/end of packet

1.4 V

All other inputs and outputs:

5.7 Clock Timing Characteristics

Refer to Figure 15 for Timing Diagram

Limit

Sym. Parameter

Min

Typ

Max

Unit Conditions

t₁

t₂

t₃

t₄

CLKIN Period

39.996

40

20

40.004

20.002

ns

MII

19.996

RMII

CLKIN High Time

CLKIN Low Time

CLKIN to TXCLK Delay

16

7

MII

RMII

16

7

MII

RMII

10

20

100 Mbps, MII

10 Mbps, MII

Figure 15

Output Timing

t₁

t₂

t₃

OSCIN

t₄

TXCLK

(100 MB)

t₄

TXCLK

(10 MB)

94 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

5.8 Transmit Timing Characteristics

Refer to Figure 16 and Figure 17 for Timing Diagram

Limit

Typ

Sym. Parameter

Min

Max

Unit

Conditions

t₁₁

t₁₂

t₁₃

TXCLK Period

39.996

399.96

16

40

400

20

40.004

400.04

24

ns

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

TXCLK Low Time

TXCLK High Time

160

200

20

240

24

16

160

200

240

10

t₁₄

t₁₅

TXCLK Rise/Fall Time

TXEN Setup Time

15

4

MII

RMII

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

TXEN Hold Time

0

MII

2

MII

CRS During Transmit Assert

Time

40

100 Mbps, MII and FBI

400

160

900

10 Mbps, MII and FBI

CRS During Transmit Deas-

sert Time

100 Mbps

10 Mbps

MII

TXD Setup Time

15

4

RMII

TXD Hold Time

0

ns

MII

2

RMII

t₂₁

t₂₂

TXER Setup Time

TXER Hold Time

15

0

ns

MII

2

RMII

t₂₃

Transmit Propagation Delay

Transmit Output Jitter

60

140

600

0.7

ns

100 Mbps, MII

100 Mbps, FBI

10 Mbps

t₂₄

ns pk-pk 100 Mbps

ns pk-pk 10 Mbps

5.5

t₂₅

Transmit SOI Pulse Width

To 0.3V

250

ns

10 Mbps

Speciﬁcations

95 of 118

April, 2002

Limit

Typ

Sym. Parameter

Min

Max

Unit

Conditions

t₂₆

t₂₇

t₂₈

Transmit SOI Pulse Width to

40 mV

4500

ns

10 Mbps

LEDn Delay Time

25

ms

LEDn Programmed

For Activity

LEDn Pulse Width

80

105

LEDn Programmed

For Activity

Figure 16

Transmit Timing - 100 Mbps

MII 100 Mbps

t

11

TXCLK

TXEN

t

13

t

14

15

16

t

12

t

14

t

18

17

CRS

t

20

t

19

TXD[3:0]

N0

N1

t

N2

N3

t

21

22

TXER

t

24

23

TPO

±

IDLE

/J/K/

DATA

/T/R/

IDLE

t

27

t

28

LEDn

RMII 100 Mbps

Same as MII 100 Mbps except:

1. Data Input on TXD[1:0]; TXD[3:2] Not Used.

2. All Timing Referenced to CLKIN instead of TXCLK

FBI 100 Mbps

Same as MII 100 Mbps except:

1. TXER Converted to TXD4.

2. RXER Converted to RXDA

96 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Figure 17

Transmit Timing - 10 Mbps

MII 10 Mbps

t

11

TXCLK

TXEN

t

13

14

t

15

16

12

t

14

t

18

17

CRS

t

20

t

19

TXD[3:0]

N0

N1

N2

N3

t

26

t

24

t

25

23

PREAMBLE

TP0

±

DATA

SOI

t

27

t

28

LEDn

RMII 10 Mbps

Same as MII 10 Mbps except:

1. Data Input on TXD[1:0]; TXD[3:2] Not Used.

2. All Timing Referenced to CLKIN instead of TXCLK.

3. Each data Di-Bit on TXD[1:0] is present for 10 consecutive CLKIN cycles.

Speciﬁcations

97 of 118

April, 2002

5.9 Receive Timing Characteristics

Refer to Figure 18 through Figure 24 for Timing Diagrams

Limit

Typ

Sym. Parameter

t₃₁Start of Packet to CRS

Min

Max

Unit

Conditions

200

700

240

280

600

ns

100 Mbps, MII

100 Mbps, RMII

10 Mbps

Assert Delay

t₃₂

End of Packet to CRS

Deassert Delay

130

100 Mbps, MII

100 Mbps RMII

10 Mbps, MII. Relative to Start

of SOI Pulse

1000

ns

10 Mbps, RMII. Relative to

Start of SOI Pulse

t₃₃

Start of Packet to

RXDV Assert Delay

240

3600

280

ns

100 Mbps

10 Mbps

t₃₄

End of Packet to

RXDV Deassert Delay

100 Mbps, MII

100 Mbps, RMII

360

1000

10 Mbps, MII. Relative to Start

of SOI Pulse

2800

ns

10 Mbps, RMII. Relative to

Start of SOI Pulse

t₃₇

RXCLK to RXDV RXD,

RXER Delay

-8

-4

8

ns

100 Mbps, MII

100 Mbps and 10 Mbps, RMII

10 Mbps, MII

100 Mbps

2

-80

18

80

t₃₈

t₃₉

t₄₀

RXCLK High Time

RXCLK Low Time

20

200

20

22

180

18

600

22

10 Mbps

100 Mbps

180

125

200

600

200

10 Mbps

SOI Pulse Minimum

Width Required for

Idle Detection

10 Mbps

Measured TPIP/N from last

zero cross to 0.3 V point.

t₄₁

Receive Input Jitter

2.0

ns pk-pk 100 Mbps

13.5 ns pk-pk 10 Mbps

25 ms LEDn Programmed for Activity

t₄₃

LEDn Delay Time

98 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Limit

Typ

Sym. Parameter

t₄₄LEDn Pulse Width

t₄₅

Min

Max

Unit

Conditions

60

105

10

ms

ns

LEDn Programmed for Activity

RXCLK, RXD, CRS,

RXDV, RXER Output

Rise and Fall Times

Figure 18

Receive Timing, Start of Packet - 100 Mbps, MII & FBI

MII 100 Mbps

TPI

±

IDLE

J

K

DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA

DATA DATA DATA DATA DATA

t

41

t

31

CRS

t

39

t

38

RXCLK

RXDV

TX

RX

t

37

t

33

t

37

RXD[3:0]

PREAMBLE PREAMBLE PREAMBLE PREAMBLE PREAMBLE

t

37

RXER

t

44

43

PLEDn

FBI 100 Mbps

Same as MII 100 Mbps except:

1. RXER Converted to RXD4.

2. TXER Converted to TXD4.

Speciﬁcations

99 of 118

April, 2002

Figure 19

Receive Timing, Start of Packet - 100 Mbps, RMII

RMII 100 Mbps

TPI

±

IDLE

J

K

DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA

DATA DATA DATA DATA DATA

t

41

t

31

CRS

t

39

t

38

CLKIN

RXDV

TX

RX

t

37

t

33

t

37

RXD[1:0]

PREAMBLE PREAMBLE PREAMBLE PREAMBLE PREAMBLE

t

37

t

37

RXER

100 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Figure 20

Receive Timing, End of Packet - 100 Mbps

MII 100 Mbps

DATA

T

R

I

TPI

±

t

32

CRS

t

39

t

38

RXCLK

RX

34

RX

TX

t

37

t

RXDV

RXD[3:0]

DATA

RMII 100 Mbps

TPI

±

DATA

T

R

I

t

32

34

CRS

t

39

37

t

38

37

CLKIN

RX

TX

RXD[1:0]

DATA

Speciﬁcations

101 of 118

April, 2002

Figure 21

Receive Timing, Start of Packet - 10 Mbps, MII

MII 10 Mbps

t

41

DATA

TPI

±

t

31

CRS

t

39

t

38

RXCLK

TX

RX

t

37

t

33

RXDV

RXD[3:0]

RXER

t

37

PREAMBLE PREAMBLE

DATA

t

43

44

LEDn

102 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Figure 22

Receive Timing, Start of Packet - 10 Mbps, RMII

RMII 10 Mbps

t

41

DATA

TPI

±

t

31

CRS

t

39

t

38

CLKIN

TX

RX

t

37

33

PREAMBLE PREAMBLE

DATA DATA

DATA

RXD[1:0]

RXER

Note 1

t

43

44

LEDn

Note 1. Each Di-Bit is present on RXD[1:0] for 10 consecutive CLKIN cycles.

Speciﬁcations

103 of 118

April, 2002

Figure 23

Receive Timing, End of Packet - 10 Mbps, MII

MII 10 Mbps

t

41

SOI

DATA

TPI

±

DATA

DATA DATA DATA

t

40

t

32

CRS

t

39

t

38

RXCLK

RX

TX

t

37

t

34

RXDV

RXD[3:0]

DATA

Figure 24

Receive Timing, End of Packet - 10 Mbps, RMII

RMII 10 Mbps

t

41

SOI

DATA

TPI

±

DATA

DATA DATA DATA

t

40

t

32

CRS

t

34

t

37

t

39

t

38

CLKIN

RX

TX

RXD[3:0]

DATA

104 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

5.10 Collision Timing Characteristics

Refer to Figure 25, Figure 26, and Figure 27 for Timing Diagrams

Limit

Typ

Sym. Parameter

Min

Max

Unit Conditions

t₅₁

t₅₂

t₅₃

t₅₄

Rcv Packet Start to COL

Assert Time

200

700

240

300

200

700

240

300

25

ns

ms

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

100 Mbps

10 Mbps

Rcv Packet Stop to COL Deas-

sert Time

130

Mt Packet Start to COL Assert

Time

Xmt Packet Stop to COL Deas-

sert Time

t₅₅

t₅₆

LEDn Delay Time

LEDn Pulse Time

LEDn programmed for

collision

80

105

ms

LEDn programmed for

collision

t₅₇

t₅₈

Collision Test Assert Time

Collision Test Deassert Time

5120

40

ns

800

10

10 Mbps

t₆₀

COL Rise and Fall Time

Speciﬁcations

105 of 118

April, 2002

Figure 25

Collision Timing, Receive

MII 100 Mbps

t

41

SOI

DATA

TPI

±

DATA

DATA DATA DATA

t

40

t

32

CRS

t

39

t

38

RXCLK

RX

TX

t

37

t

34

RXDV

RXD[3:0]

DATA

FBI 100 Mbps

Same as MII 100 Mbps

MII 100 Mbps

TPO

TPI

±

t

52

51

COL

t

56

55

LEDn

106 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Figure 26

Collision Timing, Transmit

MII 100 Mbps

TPO

±

I

DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA

I

J

K

DATA DATA DATA DATA

T

R

I

TPI

t

52

51

COL

t

56

55

LEDn

FBI 100 Mbps

Same as MII 100 Mbps

MII 100 Mbps

TPO

±

TPI

t

52

51

COL

t

56

55

LEDn

Figure 27

Collision Test Timing

MII 100 MB

TXEN

COL

t

58

57

Speciﬁcations

107 of 118

April, 2002

5.11 Link Pulse Timing Characteristics

Refer to Figure 28 and Figure 29 for Timing Diagrams

Limit

Typ

Sym. Parameter

Min

Max

Unit

Conditions

t₆₁

t₆₂

t₆₃

NLP Transmit Link Pulse Width

See Figure 8

ns

ms

ns

NLP Transmit Link Pulse Period

8

24

NLP Receive Link Pulse Width

Required For Detection

50

t₆₄

t₆₅

t₆₆

NLP Receive Link Pulse Mini-

mum Period Required For

Detection

6

7

ms

link_test_min

NLP Receive Link Pulse Maxi-

mum Period Required For

Detection

50

150

link_test_max

link_loss

NLP Receive Link Pulses

Required To Exit Link Fail State

3

Link

Pulses

lc_max

t₆₇

t₆₈

FLP Transmit Link Pulse Width

100

150

ns

FLP Transmit Clock Pulse To

Data Pulse Period

55.5 62.5 69.5

µs

interval_timer

t₆₉

t₇₀

t₇₁

t₇₂

FLP Transmit Clock Pulse To

Clock Pulse Period

111

8

125

139

22

µs

ms

ns

FLP Transmit Link Pulse Burst

Period

transmit_link_burst_timer

FLP Receive Link Pulse Width

Required For Detection

50

5

FLP Receive Link Pulse Minimum

Period Required For Clock Pulse

Detection

25

185

47

µs

ﬂp_test_min_timer

t₇₃

t₇₄

t₇₅

t₇₆

FLP Receive Link Pulse Maxi-

mum Period Required For Clock

Pulse Detection

165

15

µs

ﬂp_test_max_timer

FLP Receive Link Pulse Minimum

Period Required For Data Pulse

Detection

data_detect_min_timer

data_detect_max_timer

FLP Receive Link Pulse Maxi-

mum Period Required For Data

Pulse Detection

78

100

17

FLP Receive Link Pulses

Required To Detect Valid FLP

Burst

17

Link

Pulses

108 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

Limit

Typ

Sym. Parameter

Min

Max

Unit

Conditions

t₇₇

t₇₈

t₇₉

FLP Receive Link Pulse Burst

Minimum Period Required For

Detection

5

7

ms

nlp_test_min_timer

FLP Receive Link Pulse Burst

Maximum Period Required For

Detection

50

3

150

3

ms

nlp_test_max_timer

FLP Receive Link Pulses Bursts

Required To Detect AutoNegotia-

tion Capability

3

Link

Pulse

Bursts

t₈₀

t₈₁

t₈₂

FLP Receive Acknowledge Fail

Period

1200

750

1500

1000

ms

FLP Transmit Renegotiate Link

Fail Period

break_link_timer

NLP Receive Link Pulse Maxi-

mum Period Required For

Detection After FLP Negotiation

Has Completed

link_fail_inhibit_timer

Figure 28

NLP Link Pulse Timing

a. Transmit NLP

TPO±

t

61

t

62

b. Receive NLP

TPI±

t

63

t

64

t

66

65

PLEDn

Speciﬁcations

109 of 118

April, 2002

Figure 29

FLP Link Pulse Timing

a. Transmit FLP and Transmit FLP Burst

CLK

DATA

CLK

DATA

CLK

DATA

TPO±

t

67

t

68

t

69

t₇₀

b. Receive FLP

CLK

DATA

CLK

DATA

TPI±

31.25 62.50

93.75

125.00

156.25

t

71

t

72

t

73

t

74

t

75

c. Receive FLP Burst

TPI±

t

78

79

77

LEDn

110 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

5.12 Jabber Timing Characteristics

Refer to Figure 30 for Timing Diagram

Limit

Typ

Sym. Parameter

t₉₁Jabber Activation Delay Time

t₉₂Jabber Deactivation Delay Time

Min

Max

Unit

Conditions

50

100

750

ms

10 Mbps

250

Figure 30

Jabber Timing

MII 100 Mbps

Not applicable

FBI 100 Mbps

MII 10 Mbps

TXEN

Not applicable

t

91

TPO

±

t

92

COL

CRS

Speciﬁcations

111 of 118

April, 2002

5.13 LED Driver Timing Characteristics

Refer to Figure 31 for Timing Diagram

Limit

Sym. Parameter

Min

Typ

Max

Unit

Conditions

t96

t97

LED[3:0] On Time

LED[3:0] Off Time

80

105

ms

LED[3:0] Programmed to Blink

Figure 31

LED Driver Timing

t

96

97

LED[5:0]

112 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

5.14 MI Serial Port Timing Characteristics

Refer to Figure 32 for Timing Diagram

Limit

Sym. Parameter

Min

Typ

Max

Unit

Conditions

t₁₀₁

t₁₀₂

t₁₀₃

t₁₀₄

t₁₀₅

t₁₀₆

t₁₀₇

t₁₀₈

MDC High Time

20

10

ns

MDC Low Time

MDIO Setup Time

Write Bits

MDIO Hold Time

Write Bits

MDC To MDIO Delay

MDIO Hi-Z To Active Delay

MDIO Active To HI-Z Delay

Frame Delimiter (Idle)

20

Read Bits

Write-Read Bit Transition

Read-Write Bit Transition

32

Clocks # of Consecutive MDC Clocks

with MDIO=1

t₁₁₀

t₁₁₁

MDC To MDIO Interrupt

Pulse Assert Delay

100

ns

MDC To MDIO Interrupt

Pulse Deassert Delay

ns

Figure 32

MI Serial Port Timing

t₁₀₂

t₁₀₁

14

MDC

0

1

13

15

16

17

30

31

t₁₀₄

t₁₀₃

ST1

t₁₀₅

t₁₀₇

t₁₀₆

MDIO

(READ)

ST0

t₁₀₄

REGAD0

TA0

D15

D14

D0

TA1

t₁₀₃

ST1

MDIO

(WRITE)

ST0

TA1

TA0

D15

D1

D0

Speciﬁcations

113 of 118

April, 2002

6 Ordering Information

L

84225

/ Z

Manufacturer

Part Type

Product Rev.

Quad 100 Base-TX/FX10 Base-T

Physical Layer Device (PHY)

7 Revision History

March 2, 1999:

•

MD400183/– has been changed to MD400183/A

Global: References to JAM have been changed to AD_REV, and

MDINT has been changed to REGDEF.

page 7

•

Pin #98, Row has been completely changed.

page 8

•

Pin #110, I/O, “I Pulldown” has been changed to “I.”

page 9

•

Pin #101, Pin Name RMII_EN has been changed to RMII_EN.

page 12, Figure 1

•

References to JAM and MDINT have been changed to AD_REV and

REGDEF, respectively.

page 55, Section 2.25.7, “Invalid Registers”

Section 2.25.7, “Invalid Registers,” is new.

•

114 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

page 57, Table 8. MI Serial Port Structure

•

Symbol REGAD4[4:0] Deﬁnition, “copy, ...If REGDEF pin asserted

and...” has been deleted.

page 59, Table 9. MI Serial Port Register Map

•

Bit x.7, 18 Channel Status Output, INT has been changed to 0.

Bit x.10, 4 AutoNegot. Advertisement, 0 has been changed to

PAUSE.

•

Bit x.10, 5 AutoNegot. Remote Capability, 0 has been changed to

PAUSE.

page 64, Table 14 Register 4 - AutoNegotiation Advertisement Register

Deﬁnition

•

Bit 4.10 has been changed from 0 to PAUSE.

Row 4.10 has been added.

page 65, Table 15 Register 5 - AutoNegotiation Remote Capability

Deﬁnition

•

Bit 5.10 has been changed from 0 to PAUSE.

Row 5.10 has been added.

page 68, Table 18 Register 18 - Channel Status Output Register

Deﬁnition

•

Bit 18.7, is now blank.

Row Bit 18.7, Symbol is now blank, Name is now blank, Deﬁnition

has been changed to Reserved.

page 73, Figure 11. Typical Switching Hub Port Schematic Using the

L84225 in Twisted Pair Mode

•

References to JAM and MDINT have been changed to AD_REV and

REGDEF, respectively.

page 74, Figure 12. Typical Switching Hub Port Schematic Using the

L84225 in FX Mode with 3.3V Transceivers

•

References to JAM and MDINT have been changed to AD_REV and

REGDEF, respectively.

Revision History

115 of 118

April, 2002

page 105, Section 5.10, “Collision Timing Characteristics”

•

Any references to Jam have been deleted.

Row t has been deleted.

59

page 109, Jam Timing ﬁgure

Jam Timing ﬁgure has been deleted.

page 109, Figure 28. NLP Link Pulse Timing

Figure 28. NLP Link Pulse Timing is new.

April, 2002:

•

MD400183/A has been changed to MD400183/B

Document has been reformatted with a standard LSI template.

Tables and Figures have been renumbered to make a continuous

numeric sequence. All internal cross-references to tables and ﬁgures

have been updated.

•

All references to SEEQ have been removed.

All “84225” were changed to “L84225.”

In Section 2.25.6, “Register Structure,” page 54, descriptions of

Global Conﬁguration and Channel Conﬁguration registers were

updated to note that these registers are now reserved.

116 of 118

April, 2002

L84225 Quad 100BaseTX/FX/10BaseT Phys. Layer Device - Technical Manual

8 Surface Mount Packages

Figure 33

160-Pin PQFP

31.20 ± 0.30

28.00 ± 0.20

0.18 ± 0.05

L84225

0.10 MAX

See Detail A

#160

#1

0.25 min.

1.325

Ref.

3.40 ± 0.20

0.30 ± 0.10

0.65 Ref.

4.10 Max.

0 − 8 ˚

Detail A

1. All Dimensions are in millimeters

0.88 ± 0.15

Important:

This drawing may not be the latest version.

Surface Mount Packages

117 of 118

April, 2002

Headquarters

LSI Logic Corporation

North American Headquarters

Milpitas CA

LSI Logic Europe Ltd

European Headquarters

Bracknell England

LSI Logic K.K.

Headquarters

Tokyo Japan

Tel: 408.433.8000

Fax: 408.433.8989

Tel: 44.1344.426544

Fax: 44.1344.481039

Tel: 81.3.5463.7821

Fax: 81.3.5463.7820

Visit us at our web site: http://www.lsilogic.com

ISO 9000 Certified

The LSI Logic logo design is a registered trademark of LSI

Logic Corporation. All other brand and product names may

be trademarks of their respective companies.

LSI Logic Corporation reserves the right to make changes

to any products and services herein at any time without

notice. LSI Logic does not assume any responsibility or lia-

bility arising out of the application or use of any product or

service described herein, except as expressly agreed to in

writing by LSI Logic; nor does the purchase, lease, or use

of a product or service from LSI Logic convey a license

under any patent rights, copyrights, trademark rights, or any

other of the intellectual property rights of LSI Logic or of

third parties.

Doc. No. MD400183/B

April, 2002

Surface Mount Packages


型号：	L84225
厂家：	ETC
描述：	L84225 100BaseTX/FX/10BaseT Physical Layer Device technical manual 4/02 L84225 100BaseTX的/ FX /的10BaseT物理层设备技术手册4/02
文件：	总118页 (文件大小：829K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L84225 [ETC]

相关型号：

L84302

L8446-04

L8446-06

L8446-07

L8446-41

L8446-42

L8446-61

L8446-62

L8446-71

L8446-72

L845/3GDT

L845/3IDT