LA78610A [ETC]
; - 12号的铝制车身绘( RAL 7032 )型号: | LA78610A |
厂家: | ETC |
描述: |
|
文件: | 总12页 (文件大小:285K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
10 MHz, 4-Quadrant
Multiplier/Divider
a
AD734
FEATURES
High Accuracy
0.1% Typical Error
High Speed
CO NNECTIO N D IAGRAM
14-P in D IP
(Q P ackage & N P ackage)
10 MHz Full-Pow er Bandw idth
450 V/ s Slew Rate
200 ns Settling to 0.1% at Full Pow er
Low Distortion
–80 dBc from Any Input
Third-Order IMD Typically –75 dBc at 10 MHz
Low Noise
94 dB SNR, 10 Hz to 20 kHz
70 dB SNR, 10 Hz to 10 MHz
Direct Division Mode
2 MHz BW at Gain of 100
X1
X2
U0
U1
VP POSITIVE SUPPLY
1
2
3
4
5
6
7
14
13
12
11
10
9
X INPUT
DD DENOMINATOR DISABLE
W OUTPUT
AD734
TOP VIEW
(Not to Scale)
DENOMINATOR
INTERFACE
Z1
Z INPUT
Z2
U2
Y1
ER REFERENCE VOLTAGE
VN NEGATIVE SUPPLY
Y INPUT
Y2
8
APPLICATIONS
High Perform ance Replacem ent for AD534
Multiply, Divide, Square, Square Root
Modulator, Dem odulator
Wideband Gain Control, RMS-DC Conversion
Voltage-Controlled Am plifiers, Oscillators, and Filters
Dem odulator w ith 40 MHz Input Bandw idth
demodulator with input frequencies as high as 40 MHz as long
as the desired output frequency is less than 10 MHz.
T he AD734AQ and AD734BQ are specified for the industrial
temperature range of –40°C to +85°C and come in a 14-pin
ceramic DIP. T he AD734SQ/883B, available processed to MIL-
ST D-883B for the military range of –55°C to +125°C, is
available in a 14-pin ceramic DIP.
P RO D UCT D ESCRIP TIO N
T he AD734 is an accurate high speed, four-quadrant analog
multiplier that is pin-compatible with the industry-standard
AD534 and provides the transfer function W = XY/U. T he
AD734 provides a low-impedance voltage output with a full-
power (20 V pk-pk) bandwidth of 10 MHz. T otal static error
(scaling, offsets, and nonlinearities combined) is 0.1% of full
scale. Distortion is typically less than –80 dBc and guaranteed.
T he low capacitance X, Y and Z inputs are fully differential. In
most applications, no external components are required to
define the function.
P RO D UCT H IGH LIGH TS
T he AD734 embodies more than two decades of experience in
the design and manufacture of analog multipliers, to provide:
1. A new output amplifier design with more than twenty times
the slew-rate of the AD534 (450 V/µs versus 20 V/µs) for a
full power (20 V pk-pk) bandwidth of 10 MHz.
2. Very low distortion, even at full power, through the use of
circuit and trimming techniques that virtually eliminate all of
the spurious nonlinearities found in earlier designs.
T he internal scaling (denominator) voltage U is 10 V, derived
from a buried-Zener voltage reference. A new feature provides
the option of substituting an external denominator voltage,
allowing the use of the AD734 as a two-quadrant divider with a
1000:1 denominator range and a signal bandwidth that remains
10 MHz to a gain of 20 dB, 2 MHz at a gain of 40 dB and
200 kHz at a gain of 60 dB, for a gain-bandwidth product of
200 MHz.
3. Direct control of the denominator, resulting in higher
multiplier accuracy and a gain-bandwidth product at small
denominator values that is typically 200 times greater than
that of the AD534 in divider modes.
4. Very clean transient response, achieved through the use of a
novel input stage design and wide-band output amplifier,
which also ensure that distortion remains low even at high
frequencies.
T he advanced performance of the AD734 is achieved by a
combination of new circuit techniques, the use of a high speed
complementary bipolar process and a novel approach to laser-
trimming based on ac signals rather than the customary dc
methods. T he wide bandwidth (>40 MHz) of the AD734’s
input stages and the 200 MHz gain-bandwidth product of the
multiplier core allow the AD734 to be used as a low distortion
5. Superior noise performance by careful choice of device
geometries and operating conditions, which provide a
guaranteed 88 dB of dynamic range in a 20 kHz bandwidth.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(T = +25؇C, +V = VP = +15 V, –V = VN = –15 V, R ≥ 2 k⍀)
AD734–SPECIFICATIONS
TRANSFER FUNCTIO N
A
S
S
L
X − X Y −Y
(
2 )(
)
1
1
2
W = AO
− Z − Z
(
)
1
2
U −U
(
)
1
2
A
B
S
P aram eter
Conditions
Min Typ Max
Min Typ Max
Min Typ Max
Units
MULT IPLIER PERFORMANCE
T ransfer Function
W = XY/10
0.1 0.4
1
W = XY/10
0.1 0.25
0.6
W = XY/10
0.1 0.4
1.25
T otal Static Error1
Over T MIN to T MAX
vs. T emperature
–10 V ≤ X, Y ≤ 10 V
%
%
T MIN to T MAX
0.004
0.003
0.004
%/°C
%/V
%
vs. Either Supply
Peak Nonlinearity
±VS = 14 V to 16 V
–10 V ≤ X ≤ +10 V, Y = +10 V
–10 V ≤ Y ≤ +10 V, X = +10 V
X = 7 V rms, Y = +10 V, f ≤ 5 kHz
T MIN to T MAX
Y = 7 V rms, X = +10 V, f ≤ 5 kHz
T MIN to T MAX
X = 7 V rms, Y = nulled, f ≤ 5 kHz
Y = 7 V rms, X = nulled, f ≤ 5 kHz
X = Y = 0
0.01 0.05
0.05
0.025
0.01 0.05
0.05
0.025
0.01 0.05
0.05
0.025
%
T HD2
–58
–55
–60
–57
–66
–63
–80
–74
–58
–55
–60
–57
dBc
dBc
dBc
dBc
dBc
dBc
Feedthrough
–85 –60
–85 –66
–85 –70
–85 –76
–85 –60
–85 –66
Noise (RT O)
Spectral Density
T otal Output Noise
100 Hz to 1 MHz
10 Hz to 20 kHz
T MIN to T MAX
1.0
–94 –88
–85
1.0
–94 –88
–85
1.0
–94 –88
–85
µV/√Hz
dBc
dBc
DIVIDER PERFORMANCE (Y = 10 V)
T ransfer Function
Gain Error
W = XY/U
1
W = XY/U
1
W = XY/U
1
Y = 10 V, U = 100 mV to 10 V
%
V
%
%
ns
X Input Clipping Level
Y ≤ 10 V
1.25 × U
0.3
1.25 × U
0.15
1.25 × U
U Input Scaling Error3
0.3
1
T MIN to T MAX
U = 1 V to 10 V Step, X = 1 V
0.8
0.65
(Output to 1%)
100
100
100
INPUT INT ERFACES (X, Y, & Z)
3 dB Bandwidth
Operating Range
40
±12.5
15
40
±12.5
5
40
±12.5
15
MHz
V
Differential or Common Mode
T MIN to T MAX
X Input Offset Voltage
mV
mV
mV
mV
mV
mV
dB
dB
dB
nA
nA
kΩ
25
10
12
20
15
5
6
10
50
25
10
12
20
Y Input Offset Voltage
Z Input Offset Voltage
T MIN to T MAX
T MIN to T MAX
f ≤ 1 kHz
T MIN to T MAX
f = 5 kHz
50
90
Z Input PSRR (Either Supply)
54
50
70
70
66
56
70
70
54
50
70
70
CMRR
85
50
85
50
85
50
Input Bias Current (X, Y, Z Inputs)
300
400
150
300
300
500
T MIN to T MAX
Differential
Differential
Input Resistance
Input Capacitance
50
2
50
2
50
2
pF
DENOMINAT OR INT ERFACES (U0, U1, & U2)
Operating Range
Denominator Range
VN to VP-3
1000:1
28
VN to VP-3
1000:1
28
VN to VP-3
1000:1
28
V
Interface Resistor
U1 to U2
kΩ
OUT PUT AMPLIFIER (W)
Output Voltage Swing
Open-Loop Voltage Gain
Dynamic Response
3 dB Bandwidth
Slew Rate
T MIN to T MAX
±12
±12
±12
V
dB
X = Y = 0, Input to Z
From X or Y Input, CL ≤ 20 pF
W ≤ 7 V rms
72
72
72
8
10
450
8
10
450
8
10
450
MHz
V/µs
Settling T ime
T o 1%
T o 0.1%
Short-Circuit Current
+20 V or –20 V Output Step
T MIN to T MAX
125
200
50
125
200
50
125
200
50
ns
ns
mA
20
80
20
80
20
80
POWER SUPPLIES, ±VS
Operating Supply Range
Quiescent Current
±8
6
±16.5 ±8
12
±16.5 ±8
12
±16.5
12
V
mA
T MIN to T MAX
9
6
9
6
9
NOT ES
1Figures given are percent of full scale (e.g., 0.01% = 1 mV).
2dBc refers to deciBels relative to the full-scale input (carrier) level of 7 V rms.
3See Figure 10 for test circuit.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. B
AD734
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2
Tem perature
Range
P ackage
D escription O ption
P ackage
Model
for T J max = 175°C . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
X, Y and Z Input Voltages . . . . . . . . . . . . . . . . . . . . VN to VP
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage T emperature Range
Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
AD734A, B (Industrial) . . . . . . . . . . . . . . . –40°C to +85°C
AD734S (Military) . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead T emperature Range (soldering 60 sec) . . . . . . . . +300°C
T ransistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
AD734AN
AD734BN
AD734AQ
AD734BQ
AD734SQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Plastic DIP
Plastic DIP
Cerdip
N-14
N-14
Q-14
Q-14
Q-14
Q-14
Cerdip
–55°C to +125°C Cerdip
AD734SQ/883B –55°C to +125°C Cerdip
AD734SCHIPS –55°C to +125°C Chip
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied.
214-Pin Ceramic DIP: θJA = 110°C/W.
CH IP D IMENSIO NS & BO ND ING D IAGRAM
D imensions shown in inches and (mm).
(Contact factory for latest dimensions.)
REV. B
–3–
AD734
ac-coupled and the other is grounded, the residual offset voltage
is typically less than 5 mV, which corresponds to a bias current
of only 100 nA. T his low bias current ensures that mismatches
in the sources resistances at a pair of inputs does not cause an
offset error. T hese currents remain low over the full temperature
range and supply voltages.
X = X – X
1
X1
X2
2
HIGH-ACCURACY
TRANSLINER
MULTIPLIER CORE
XIF
DD
XY/U – Z
U
XZ
U
DENOMINATOR
CONTROL
∑
WIF
W
U 0
U1
A
∞
ER
O
T he common-mode range of the X, Y and Z inputs does not
fully extend to the supply rails. Nevertheless, it is often possible
to operate the AD734 with one terminal of an input pair con-
nected to either the positive or negative supply, unlike previous
multipliers. T he common-mode resistance is several megohms.
Ru
AD734
U 2
Y1
Z1
Z2
ZIF
YIF
Y2
Z = Z – Z
Y = Y – Y
1
2
1
2
T he full-scale output of ±10 V can be delivered to a load resis-
tance of 1 kΩ (although the specifications apply to the standard
multiplier load condition of 2 kΩ). T he output amplifier is
stable driving capacitive loads of at least 100 pF, when a slight
increase in bandwidth results from the peaking caused by this
capacitance. T he 450 V/µs slew rate of the AD734’s output am-
plifier ensures that the bandwidth of 10 MHz can be maintained
up to the full output of 20 V pk-pk. Operation at reduced supply
voltages is possible, down to ±8 V, with reduced signal levels.
Figure 1. AD734 Block Diagram
FUNCTIO NAL D ESCRIP TIO N
Figure 1 is a simplified block diagram of the AD734. Operation
is similar to that of the industry-standard AD534 and in many
applications these parts are pin-compatible. T he main functional
difference is the provision for direct control of the denominator
voltage, U, explained fully on the following page. Internal sig-
nals are actually in the form of currents, but the function of the
AD734 can be understood using voltages throughout, as shown
in this figure. Pins are named using upper-case characters (such
as X1, Z2) while the voltages on these pins are denoted by sub-
scripted variables (for example, X1, Z2).
Available Tr ansfer Functions
The uncommitted (open-loop) transfer function of the AD734 is
X − X Y −Y
(
2 )(
)
1
1
2
W = AO
− Z − Z
(
)
1
2
,
(1)
U
T he AD734’s differential X, Y and Z inputs are handled by
wideband interfaces that have low offset, low bias current and
low distortion. T he AD734 responds to the difference signals
X = X1 – X2, Y = Y1 – Y2 and Z = Z1 – Z2, and rejects
common-mode voltages on these inputs. T he X, Y and Z
interfaces provide a nominal full-scale (FS) voltage of ±10 V,
but, due to the special design of the input stages, the linear
range of the differential input can be as large as ±17 V. Also
unlike previous designs, the response on these inputs is not
clipped abruptly above ±15 V, but drops to a slope of one half.
where AO is the open-loop gain of the output op-amp, typically
72 dB. When a negative feedback path is provided, the circuit
will force the quantity inside the brackets essentially to zero,
resulting in the equation
(X1 – X2)(Y1 – Y2) = U (Z1 – Z2)
(2)
T his is the most useful generalized transfer function for the
AD734; it expresses a balance between the product XY and the
product UZ. T he absence of the output, W, in this equation
only reflects the fact that we have not yet specified which of the
inputs is to be connected to the op amp output.
T he bipolar input signals X and Y are multiplied in a translinear
core of novel design to generate the product XY/U. T he denom-
inator voltage, U, is internally set to an accurate, temperature-
stable value of 10 V, derived from a buried-Zener reference. An
uncalibrated fraction of the denominator voltage U appears
between the voltage reference pin (ER) and the negative supply
pin (VN), for use in certain applications where a temperature-
compensated voltage reference is desirable. T he internal denom-
inator, U, can be disabled, by connecting the denominator
disable Pin 13 (DD) to the positive supply pin (VP); the denom-
inator can then be replaced by a fixed or variable external volt-
age ranging from 10 mV to more than 10 V.
Most of the functions of the AD734 (including division, unlike
the AD534 in this respect) are realized with Z1 connected to W.
So, substituting W in place of Z1 in the above equation results in
an output.
X − X Y −Y
(
2 )(
)
+ Z2 .
1
1
2
W =
(3)
U
T he free input Z2 can be used to sum another signal to the
output; in the absence of a product signal, W simply follows the
voltage at Z2 with the full 10 MHz bandwidth. When not
needed for summation, Z2 should be connected to the ground
associated with the load circuit. We can show the allowable
polarities in the following shorthand form:
T he high-gain output op-amp nulls the difference between
XY/U and an additional signal Z, to generate the final output
W. T he actual transfer function can take on several forms, de-
pending on the connections used. T he AD734 can perform all
of the functions supported by the AD534, and new functions
using the direct-division mode provided by the U-interface.
±X ±Y
(
)(
)
+ ± Z.
±W =
(
)
(4)
+U
(
)
Each input pair (X1 and X2, Y1 and Y2, Z1 and Z2) has a
differential input resistance of 50 kΩ; this is formed by “real”
resistors (not a small-signal approximation) and is subject to a
tolerance of ±20%. T he common-mode input resistance is
several megohms and the parasitic capacitance is about 2 pF.
In the recommended direct divider mode, the Y input is set to a
fixed voltage (typically 10 V) and U is varied directly; it may
have any value from 10 mV to 10 V. T he magnitude of the ratio
X/U cannot exceed 1.25; for example, the peak X-input for U
= 1 V is ±1.25 V. Above this level, clipping occurs at the
positive and negative extremities of the X-input. Alternatively,
T he bias currents associated with these inputs are nulled by
laser-trimming, such that when one input of a pair is optionally
–4–
REV. B
AD734
the AD734 can be operated using the standard (AD534) divider
connections (Figure 8), when the negative feedback path is
established via the Y2 input. Substituting W for Y2 in Equation
(2), we get
After temperature-correction (block T C), the reference voltage
is applied to transistor Qd and trimmed resistor Rd, which
generate the required reference current. T ransistor Qu and
resistor Ru are not involved in setting up the internal denominator,
and their associated control pins U0, U1 and U2 will normally
be grounded. T he reference voltage is also made available, via
the 100 kΩ resistor Rr, at Pin 9 (ER); the purpose of Qr is
explained below.
Z − Z
(
)
+Y1.
2
1
W = U
(5)
X − X
(
)
1
2
In this case, note that the variable X is now the denominator,
When the control pin DD (denominator disable) is connected to
VP, the internal source of Iu is shut off, and the collector cur-
rent of Qu must provide the denominator current. T he resistor
Ru is laser-trimmed such that the multiplier denominator is
exactly equal to the voltage across it (that is, across pins U1 and
U2). Note that this trimming only sets up the correct internal
ratio; the absolute value of Ru (nominally 28 kΩ) has a
tolerance of ±20%. Also, the alpha of Qu, (typically 0.995)
which might be seen as a source of scaling error, is canceled by
the alpha of other transistors in the complete circuit.
and the above restriction (X/U ≤ 1.25) on the magnitude of the
X input does not apply. However, X must be positive in order
for the feedback polarity to be correct. Y1 can be used for
summing purposes or connected to the load ground if not
needed. T he shorthand form in this case is
±Z
(
(
)
+ ±Y .
±W = +U
(
)
(
)
(
)
(6)
+X
)
In some cases, feedback may be connected to two of the avail-
able inputs. T his is true for the square-rooting connections (Fig-
ure 9), where W is connected to both X1 and Y2. Setting X1 =
W and Y2 = W in Equation (2), and anticipating the possibility
of again providing a summing input, so setting X2 = S and Y1 =
S, we find, in shorthand form
In the simplest scheme (Figure 3), an externally-provided
control voltage, VG, is applied directly to U0 and U2 and the
resulting voltage across Ru is therefore reduced by one VBE. For
example, when VG = 2 V, the actual value of U will be about
1.3 V. T his error will not be important in some closed-loop
applications, such as automatic gain control (AGC), but clearly
is not acceptable where the denominator value must be well-
defined. When it is required to set up an accurate, fixed value of
U, the on-chip reference may be used. T he transistor Qr is
provided to cancel the VBE of Qu, and is biased by an external
resistor, R2, as shown in Figure 4. R1 is chosen to set the de-
sired value of U and consists of a fixed and adjustable resistor.
(7)
±W = +U +Z + ±S .
)(
(
)
(
)
(
)
T his is seen more generally to be the geometric-mean function,
since both U and Z can be variable; operation is restricted to
one quadrant. Feedback may also be taken to the U-interface.
Full details of the operation in these modes is provided in the
appropriate section of this data sheet.
D ir ect D enom inator Contr ol
+VS
14
13
VP
DD
A valuable new feature of the AD734 is the provision to replace
the internal denominator voltage, U, with any value from
+10 mV to +10 V. T his can be used (1) to simply alter the
multiplier scaling, thus improve accuracy and achieve reduced
noise levels when operating with small input signals; (2) to
implement an accurate two-quadrant divider, with a 1000:1 gain
range and an asymptotic gain-bandwidth product of 200 MHz;
(3) to achieve certain other special functions, such as AGC or
rms.
AD734
Iu
60µA
~
U0
U1
Qu
3
4
Rr
100k
ER
VN
NC
V
9
8
NC
G
Qr
Ru
28k
U2
–VS
5
Figure 2 shows the internal circuitry associated with denomina-
tor control. Note first that the denominator is actually propor-
tional to a current, Iu, having a nominal value of 356 µA for
U = 10 V, whereas the primary reference is a voltage, generated
by a buried-Zener circuit and laser-trimmed to have a very low
temperature coefficient. T his voltage is nominally 8 V with a
tolerance of ±10%.
Figure 3. Low-Accuracy Denom inator Control
+V
R2
14
13
VP
DD
S
Iu
AD734
U0
U1
3
4
Qu
Rr
100k
Iu NOMINALLY
ER
VN
14
356µA for
U = 10V
VP
LINK TO
9
8
Qr
AD734
Ru
28k
DISABLE
NOM
8V
R1
U2
–V
5
13
9
NC
DD
S
Rr
100k
3
4
U0
U1
Qd
Qu
TC
ER
VN
Rd
NOM
22.5k
Ru
28k
Qr
NOM
8V
Figure 4. Connections for a Fixed Denom inator
5
8
U2
T able I shows useful values of the external components for set-
ting up nonstandard denominator values.
NEGATIVE SUPPLY
Figure 2. Denom inator Control Circuitry
REV. B
–5–
AD734
+15V
Table I. Com ponent Values for Setting Up Nonstandard
D enom inator Values
AD734
1
2
3
4
5
6
7
14
13
12
11
X1
X2
U0
U1
U2
VP
X – INPUT
0.1µF
±10V FS
DD
W
NC
D enom inator
R1 (Fixed)
R1 (Variable)
R2
(Y – Y )
(X – X )
1
2
1
2
+ Z
W =
2
10V
LOAD
5 V
3 V
2 V
1 V
34.8 kΩ
64.9 kΩ
86.6 kΩ
174 kΩ
20 kΩ
20 kΩ
50 kΩ
100 kΩ
120 kΩ
220 kΩ
300 kΩ
620 kΩ
Z1
L
GROUND
Z2 10
Z
2
OPTIONAL
L
9
8
ER
VN
NC
Y1
Y2
SUMMING INPUT
Y – INPUT
±10V FS
0.1µF
±10V FS
–15V
T he denominator can also be current controlled, by grounding
Pin 3 (U0) and withdrawing a current of Iu from Pin 4 (U1).
T he nominal scaling relationship is U = 28 × Iu, where u is
expressed in volts and Iu is expressed in milliamps. Note,
however, that while the linearity of this relationship is very good,
it is subject to a scale tolerance of ±20%. Note that the common
mode range on Pins 3 through 5 actually extends from 4 V to
36 V below VP, so it is not necessary to restrict the connection
of U0 to ground if it should be desirable to use some other
voltage.
Figure 5. Basic Multiplier Circuit
of 32 Hz. When a tighter control of this frequency is needed, or
when the HP corner is above about 100 kHz, an external resis-
tor should be added across the pair of input nodes.
At least one of the two inputs of any pair must be provided with
a dc path (usually to ground). T he careful selection of ground
returns is important in realizing the full accuracy of the AD734.
T he Z2 pin will normally be connected to the load ground,
which may be remote, in some cases. It may also be used as an
optional summing input (see Equations (3) and (4), above)
having a nominal FS input of ±10 V and the full 10 MHz
bandwidth.
T he output ER may also be buffered, re-scaled and used as a
general-purpose reference voltage. It is generated with respect to
the negative supply line Pin 8 (VN), but this is acceptable when
driving one of the signal interfaces. An example is shown in Fig-
ure 12, where a fixed numerator of 10 V is generated for a di-
vider application. T here, Y2 is tied to VN but Y1 is 10 V above
this; therefore the common-mode voltage at this interface is still
5 V above VN, which satisfies the internal biasing requirements
(see Specifications T able).
In applications where high absolute accuracy is essential, the
scaling error caused by the finite resistance of the signal
source(s) may be troublesome; for example, a 50 Ω source
resistance at just one input will introduce a gain error of –0.1%;
if both the X- and Y-inputs are driven from 50 Ω sources, the
scaling error in the product will be –0.2%. Provided the source
resistance(s) are known, this gain error can be completely
compensated by including the appropriate resistance (50 Ω or
100 Ω, respectively, in the above cases) between the output W
(Pin 12) and the Z1 feedback input (Pin 11). If Rx is the total
source resistance associated with the X1 and X2 inputs, and Ry
is the total source resistance associated with the Y1 and Y2
inputs, and neither Rx nor Ry exceeds 1 kΩ, a resistance of
Rx+Ry in series with pin Z1 will provide the required gain
restoration.
O P ERATIO N AS A MULTIP LIER
All of the connection schemes used in this section are essentially
identical to those used for the AD534, with which the AD734 is
pin-compatible. T he only precaution to be noted in this regard
is that in the AD534, Pins 3, 5, 9, and 13 are not internally
connected and Pin 4 has a slightly different purpose. In many
cases, an AD734 can be directly substituted for an AD534 with
immediate benefits in static accuracy, distortion, feedthrough,
and speed. Where Pin 4 was used in an AD534 application to
achieve a reduced denominator voltage, this function can now be
much more precisely implemented with the AD734 using alter-
native connections (see Direct Denominator Control, page 5).
Pins 9 (ER) and 13 (DD) should be left unconnected in this
application. T he U-inputs (Pins 3, 4 and 5) are shown
connected to ground; they may alternatively be connected to
VN, if desired. In applications where Pin 2 (X2) happens to be
driven with a high-amplitude, high-frequency signal, the
capacitive coupling to the denominator control circuitry via an
ungrounded Pin 3 can cause high-frequency distortion. However,
the AD734 can be operated without modification in an AD534
socket, and these three pins left unconnected, with the above
Operation from supplies down to ±8 V is possible. T he supply
current is essentially independent of voltage. As is true of all
high speed circuits, careful power-supply decoupling is impor-
tant in maintaining stability under all conditions of use. T he
decoupling capacitors should always be connected to the load
ground, since the load current circulates in these capacitors at
high frequencies. Note the use of the special symbol (a triangle
with the letter ‘L’ inside it) to denote the load ground.
caution noted.
+15V
AD734
0.1µF
Standar d Multiplier Connections
1
2
3
4
5
6
7
14
13
12
11
X1
VP
X – INPUT
Figure 5 shows the basic connections for multiplication. T he X
and Y inputs are shown as optionally having their negative
nodes grounded, but they are fully differential, and in many
applications the grounded inputs may be reversed (to facilitate
interfacing with signals of a particular polarity, while achieving
some desired output polarity) or both may be driven.
L
±10V FS
DD
NC
NC
X2
U0
U1
U2
(Y – Y )
(X – X )
1
2
1
2
W
1
1
50k
I
=
W
R
10V
S
R
Z1
S
Z2 10
9
8
ER
VN
Y1
Y2
Y – INPUT
±10V FS
0.1µF
I
±10mA MAX FS
W
T he AD734 has an input resistance of 50 kΩ ± 20% at the X, Y,
and Z interfaces, which allows ac-coupling to be achieved with
moderately good control of the high-pass (HP) corner
±10V MAXIMUM
LOAD VOLTAGE
L
–15V
L
frequency; a capacitor of 0.1 µF provides a HP corner frequency
Figure 6. Conversion of Output to a Current
–6–
REV. B
AD734
+15V
NC
Cur r ent O utput
R2
1.6k
AD734
0.1µF
It may occasionally be desirable to convert the output voltage to
a current. In correlation applications, for example, multiplica-
tion is followed by integration; if the output is in the form of a
current, a simple grounded capacitor can perform this function.
Figure 6 shows how this can be achieved. T he op amp forces
the voltage across Z1 and Z2, and thus across the resistor RS, to
be the product XY/U. Note that the input resistance of the
Z interface is in shunt with RS, which must be calculated
accordingly.
1
2
3
4
5
6
7
14
13
12
11
X1
VP
L
R1
DD
X2
U0
U1
U2
1.6k
R3
W
13k
E2cos2ωt /10V
Esinωt
Z1
R4
4.32k
Z2 10
9
ER
NC
Y1
Y2
0.1µF
C
L
8
VN
L
–15V
T he smallest FS current is simply ±10 V/50 kΩ, or ±200 µA,
with a tolerance of about 20%. T o guarantee a 1% conversion
tolerance without adjustment, RS must be less than 2.5 kΩ. T he
maximum full scale output current should be limited to about
±10 mA (thus, RS = 1 kΩ). T his concept can be applied to all
connection modes, with the appropriate choice of terminals.
Figure 7. Frequency Doubler
O P ERATIO N AS A D IVID ER
T he AD734 supports two methods for performing analog
division. T he first is based on the use of a multiplier in a feed-
back loop. T his is the standard mode recommended for multi-
pliers having a fixed scaling voltage, such as the AD534, and
will be described in this Section. T he second uses the AD734’s
unique capability for externally varying the scaling (denominator)
voltage directly, and will be described in the next section.
Squar ing and Fr equency-D oubling
Squaring of an input signal, E, is achieved simply by connecting
the X and Y inputs in parallel; the phasing can be chosen to
produce an output of E2/U or –E2/U as desired. T he input may
have either polarity, but the basic output will either always be
positive or negative; as for multiplication, the Z2 input may be
used to add a further signal to the output.
Feedback D ivider Connections
Figure 8 shows the connections for the standard (AD534)
divider mode. Feedback from the output, W, is now taken to the
Y2 (inverting) input, which, provided that the X-input is posi-
tive, establishes a negative feedback path. Y1 should normally
be connected to the ground associated with the load circuit, but
may optionally be used to sum a further signal to the output. If
desired, the polarity of the Y-input connections can be reversed,
with W connected to Y1 and Y2 used as the optional sum-
mation input. In this case, either the polarity of the X-input
connections must be reversed, or the X-input voltage must be
negative.
When the input is a sinewave, a squarer behaves as a frequency-
doubler, since
(Esinwt)2 = E2 (1 – cos2wt)/2
(8)
Equation (8) shows a dc term at the output which will vary
strongly with the amplitude of the input, E. T his dc term can be
avoided using the connection shown in Figure 7, where an
RC-network is used to generate two signals whose product has
no dc term. T he output is
E
π
E
π
1
W = 4
sin wt +
sin wt −
+15V
(9)
4
4
10 V
AD734
2
2
0.1µF
X INPUT
+0.1V TO
+10V
1
2
3
4
5
6
7
14
13
12
11
X1
X2
U0
U1
U2
VP
L
for w = 1/CR1, which is just
W = E2(cos2wt)/( 10 V)
DD
NC
NC
(Z – Z )
2
1
(10)
W
+Y1
W = 10
(X – X )
1
2
Z1
which has no dc component. T o restore the output to ±10 V
when E = 10 V, a feedback attenuator with an approximate ratio
of 4 is used between W and Z1; this technique can be used
wherever it is desired to achieve a higher overall gain in the
transfer function.
Z INPUT
±10V FS
Z2 10
Y
1
9
8
ER
VN
Y1
Y2
0.1µF
L
OPTIONAL
SUMMING
INPUT
L
–15V
±10V FS
In fact, the values of R3 and R4 include additional compensa-
tion for the effects of the 50 kΩ input resistance of all three
interfaces; R2 is included for a similar reason. T hese resistor
values should not be altered without careful calculation of the
consequences; with the values shown, the center frequency fO is
100 kHz for C = 1 nF. T he amplitude of the output is only a
weak function of frequency: the output amplitude will be 0.5%
too low at f = 0.9f0 and f = 1.1f0. T he cross-connection is
simply to produce the cosine output with the sign shown in
Equation (10); however, the sign in this case will rarely be
important.
Figure 8. Standard (AD534) Divider Connection
T he numerator input, which is differential and can have either
polarity, is applied to pins Z1 and Z2. As with all dividers based
on feedback, the bandwidth is directly proportional to the
denominator, being 10 MHz for X = 10 V and reducing to
100 kHz for X = 100 mV. T his reduction in bandwidth, and the
increase in output noise (which is inversely proportional to the
denominator voltage) preclude operation much below a denomi-
nator of 100 mV. Division using direct control of the denominator
(Figure 10) does not have these shortcomings.
REV. B
–7–
AD734
+15V
0.1µF
T his connection scheme may also be viewed as a variable-gain
element, whose output, in response to a signal at the X input, is
controllable by both the Y input (for attenuation, using Y less
than U) and the U input (for amplification, using U less than
Y). T he ac performance is shown in Figure 11; for these results,
Y was maintained at a constant 10 V. At U = 10 V, the gain is
unity and the circuit bandwidth is a full 10 MHz. At U = 1 V,
the gain is 20 dB and the bandwidth is essentially unaltered. At
U = 100 mV, the gain is 40 dB and the bandwidth is 2 MHz.
Finally, at U = 10 mV, the gain is 60 dB and the bandwidth is
250 kHz, corresponding to a 250 MHz gain-bandwidth product.
AD734
1
2
3
4
5
6
7
14
13
12
11
X1
VP
L
DD
NC
X2
U0
U1
U2
W = (10V) (Z – Z ) + S
2
1
D
W
Z1
Z INPUT
+10mV TO
+10V
S
OPTIONAL
SUMMING
INPUT
L
Z2 10
9
8
ER
VN
NC
Y1
Y2
0.1µF
±10V FS
L
–15V
70
Figure 9. Connection for Square Rooting
Connections for Squar e-Rooting
U = 10mV
60
T he AD734 may be used to generate an output proportional to
the square-root of an input using the connections shown in
Figure 9. Feedback is now via both the X and Y inputs, and is
always negative because of the reversed-polarity between these
two inputs. T he Z input must have the polarity shown, but
because it is applied to a differential port, either polarity of
input can be accepted with reversal of Z1 and Z2, if necessary.
T he diode D, which can be any small-signal type (lN4148 being
suitable) is included to prevent a latching condition which could
occur if the input momentarily was of the incorrect polarity of
the input, the output will be always negative.
50
U = 100mV
40
30
U = 1V
20
10
U = 10V
0
10k
100k
FREQUENCY – Hz
1M
10M
Note that the loading on the output side of the diode will be
provided by the 25 kΩ of input resistance at X1 and Y2, and by
the user’s load. In high speed applications it may be beneficial
to include further loading at the output (to 1 kΩ minimum) to
speed up response time. As in previous applications, a further
signal, shown here as S, may be summed to the output; if this
option is not used, this node should be connected to the load
ground.
Figure 11. Three-Variable Multiplier/Divider Perform ance
T he 2 MΩ resistor is included to improve the accuracy of the
gain for small denominator voltages. At high gains, the X input
offset voltage can cause a significant output offset voltage. T o
eliminate this problem, a low-pass feedback path can be used
from W to X2; see Figure 13 for details.
D IVISIO N BY D IRECT D ENO MINATO R CO NTRO L
T he AD734 may be used as an analog divider by directly vary-
ing the denominator voltage. In addition to providing much
higher accuracy and bandwidth, this mode also provides greater
flexibility, because all inputs remain available. Figure 10 shows
the connections for the general case of a three-input multiplier
divider, providing the function
Where a numerator of 10 V is needed, to implement a two-
quadrant divider with fixed scaling, the connections shown in
Figure 12 may be used. T he reference voltage output appearing
between Pin 9 (ER) and Pin 8 (VN) is amplified and buffered
by the second op amp, to impose 10 V across the Y1/Y2 input.
Note that Y2 is connected to the negative supply in this applica-
tion. T his is permissible because the common-mode voltage is
still high enough to meet the internal requirements. T he transfer
function is
X − X Y −Y
(
2 )(
)
+ Z2,
1
1
2
W =
(11)
U −U
(
)
1
2
where the X, Y, and Z signals may all be positive or negative,
but the difference U = U1 – U2 must be positive and in the
range +10 mV to +10 V. If a negative denominator voltage must
be used, simply ground the noninverting input of the op amp.
As previously noted, the X input must have a magnitude of less
than 1.25U.
X1 − X2
W = 10 V
+ Z2 .
(12)
U1 −U2
The ac performance of this circuit remains as shown in Figure 11.
+15V
AD734
1
2
3
4
5
6
7
+15V
14
13
12
11
X1
X2
U0
U1
U2
VP
AD734
X – INPUT
0.1µF
DD
(X – X )
10V
1
2
1
2
3
4
5
6
7
14
13
12
11
X1
X2
U0
U1
U2
VP
W =
+ Z
2
U
1
X – INPUT
0.1µF
W =
U
– U
W
1
2
DD
(Y – Y )
(X – X )
1
2
1
2
+ Z
LOAD
U – INPUT
U
1
2
2MΩ
Z1
U
– U
L
W
1
2
GROUND
LOAD
GROUND
U
2
Z2 10
Z
2
U – INPUT
2MΩ
Z1
L
OPTIONAL
SUMMING
INPUT
L
9
8
ER
VN
Y1
Y2
U
2
Z2 10
Z
2
0.1µF
OPTIONAL
SUMMING INPUT
±10V FS
L
9
8
ER
VN
NC
Y1
Y2
±10V FS
0.1µF
100k
Y – INPUT
–15V
200k
SCALE
ADJUST
–15V
OP AMP = AD712 DUAL
Figure 10. Three-Variable Multiplier/Divider Using Direct
Denom inator Control
Figure 12. Two-Quadrant Divider with Fixed 10 V Scaling
REV. B
–8–
AD734
T he output amplitude tracks EC over the range +1 V to slightly
more than +10 V.
A P RECISIO N AGC LO O P
T he variable denominator of the AD734 and its high gain-
bandwidth product make it an excellent choice for precise
automatic gain control (AGC) applications. Figure 13 shows a
suggested method. T he input signal, EIN, which may have a
peak amplitude of from 10 mV to 10 V at any frequency from
100 Hz to 10 MHz, is applied to the X input, and a fixed posi-
tive voltage EC to the Y input. Op amp A2 and capacitor C2
form an integrator having a current summing node at its invert-
ing input. (T he AD712 dual op amp is a suitable choice for this
application.) In the absence of an input, the current in D2 and
R2 causes the integrator output to ramp negative, clamped by
diode D3, which is included to reduce the time required for the
loop to establish a stable, calibrated, output level once the
circuit has received an input signal. With no input to the
denominator (U0 and U2), the gain of the AD734 is very high
(about 70 dB), and thus even a small input causes a substantial
output.
+2
+1
100kHZ
0
–1
1MHZ
100HZ
–2
10mV
100mV
1V
10V
INPUT AMPLITUDE – Volts
R3
1MΩ
Figure 14. AGC Am plifier Output Error vs. Input Voltage
C1
1µF
A1
+15V
AD734
WID EBAND RMS-D C CO NVERTER
USING U INTERFACE
T he AD734 is well suited to such applications as implicit RMS-
DC conversion, where the AD734 implements the function
1
2
3
4
5
6
7
14
13
12
X1
X2
U0
U1
U2
VP
E
IN
0.1µF
D1
DD
W
1N914
E
OUT
D3
1N914
C2
1µF
C1
1µF
Z1 11
Z2 10
NC
A2
L
2
avg VIN
[
]
L
0.1µF
9
8
ER
VN
(13)
E
C
VRMS =
Y1
Y2
VRMS
+1V TO
+10V
D2
1N914
–15V
OP AMP = AD712 DUAL
using its direct divide mode. Figure 15 shows the circuit.
R2
1MΩ
R1
1MΩ
+15V
0.1µF
AD734
V
1
2
3
4
5
6
7
14
13
12
X1
VP
IN
1/2
AD708
L
Figure 13. Precision AGC Loop
U2b
R1
3.32kΩ
DD
X2
L
V
O
Diode D1 and C1 form a peak detector, which rectifies the out-
put and causes the integrator to ramp positive. When the cur-
rent in R1 balances the current in R2, the integrator output
holds the denominator output at a constant value. T his occurs
when there is sufficient gain to raise the amplitude of EIN to that
required to establish an output amplitude of EC over the range
of +1 V to +10 V. T he X input of the AD734, which has finite
offset voltage, could be troublesome at the output at high gains.
T he output offset is reduced to that of the X input (one or two
millivolts) by the offset loop comprising R3, C3, and buffer A1.
T he low pass corner frequency of 0.16 Hz is transformed to a
high-pass corner that is multiplied by the gain (for example,
160 Hz at a gain of 1000).
W
U0 U1
1/2
U2a
AD708
Z1 11
Z2 10
C1
47µF
C2
1µF
U1
2
V
=
V
U2
L
O
IN
L
L
L
9
8
ER
VN
Y1
Y2
0.1µF
L
–15V
Figure 15. A 2-Chip, Wideband RMS-DC Converter
In this application, the AD734 and an AD708 dual op amp
serve as a 2-chip RMS-DC converter with a 10 MHz bandwidth.
Figure 16 shows the circuit’s performance for square-, sine-,
and triangle-wave inputs. T he circuit accepts signals as high as
10 V p-p with a crest factor of 1 or 1 V p-p with a crest factor of
10. T he circuit’s response is flat to 10 MHz with an input of
10 V, flat to almost 5 MHz for an input of 1 V, and to almost
1 MHz for inputs of 100 mV. For accurate measurements of
input levels below 100 mV, the AD734’s output offset (Z inter-
face) voltage, which contributes a dc error, must be trimmed out.
In applications not requiring operation down to low frequencies,
amplifier A1 can he eliminated, but the AD734’s input
resistance of 50 kΩ between X1 and X2 will reduce the time
constant and increase the input offset. Using a non-polar 20 µF
tantalum capacitor for C1 will result in the same unity-gain
high-pass corner; in this case, the offset gain increases to 20, still
very acceptable.
In Figure 15’s circuit, the AD734 squares the input signal, and
its output (VIN2) is averaged by a low-pass filter that consists of
R1 and C1 and has a corner frequency of 1 Hz. Because of the
implicit feedback loop, this value is both the output value, VRMS
and the denominator in Equation (13). U2a and U2b, an
AD708 dual dc precision op amp, serve as unity-gain buffers,
supplying both the output voltage and driving the U interface.
Figure 14 shows the error in the output for sinusoidal inputs at
100 Hz, 100 kHz, and 1 MHz, with EC set to +10 V. T he out-
put error for any frequency between 300 Hz and 300 kHz is
similar to that for 100 kHz. At low signal frequencies and low
input amplitudes, the dynamics of the control loop determine
the gain error and distortion; at high frequencies, the 200 MHz
gain-bandwidth product of the AD734 limit the available gain.
,
REV. B
–9–
AD734
100
If the two X1 inputs are at frequencies f1 and f2 and the
frequency at the Y1 input is f0, then the two-tone third-order
intermodulation products should appear at frequencies 2f1 – f2 ±
f0 and 2f2 – f1 ± f0. Figures 18 and 19 show the output spectra of
the AD734 with f1 = 9.95 MHz, f2 = 10.05 MHz, and f0 =
9.00 MHz for a signal level of f1 & f2 of 6 dBm and f0 of
+24 dBm in Figure 18 and f1 & f2 of 0 dBm and f0 of +24 dBm
in Figure 19. T his performance is without external trimming of
the AD734’s X and Y input-offset voltages.
10
1
100m
10m
1m
T he possible T wo T one Intermodulation Products are at 2 ×
9.95 MHz – 10.05 MHz ± 9.00 MHz and 2 × 10.05 –
9.95 MHz ± 9.00 MHz; of these only the third-order products
at 0.850 MHz and 1.150 MHz are within the 10 MHz band-
width of the AD734; the desired output signals are at
0.950 MHz and 1.050 MHz. Note that the difference (Figure
18) between the desired outputs and third-order products is
approximately 78 dB, which corresponds to a computed
third-order intercept point of +46 dBm.
SQUARE WAVE
SINE WAVE
TRI-WAVE
100µ
10k
100k
1M
10M
INPUT FREQUENCY – Hz
Figure 16. RMS-DC Converter Perform ance
LO W D ISTO RTIO N MIXER
T he AD734’s low noise and distortion make it especially
suitable for use as a mixer, modulator, or demodulator.
Although the AD734’s –3 dB bandwidth is typically 10 MHz
and is established by the output amplifier, the bandwidth of its
X and Y interfaces and the multiplier core are typically in excess
of 40 MHz. T hus, provided that the desired output signal is less
than 10 MHz, as would typically be the case in demodulation,
the AD734 can be used with both its X and Y input signals as
high as 40 MHz. One test of mixer performance is to linearly
combine two closely spaced, equal-amplitude sinusoidal signals
and then mix them with a third signal to determine the mixer’s
2-tone T hird-Order Intermodulation Products.
+15V
AD734
HP3326A
COMBINE
A + B
0.1µF
1
2
3
4
5
6
7
14
13
12
11
X1
VP
AD707
DD
X2
U0
U1
U2
Figure 18. AD734 Third-Order Interm odulation Perform ance
for f1 = 9.95 MHz, f2 = 10.05 MHz, and f0 = 9.00 MHz and for
Signal Levels of f1 & f2 of 6 dBm and f0 of +24 dBm . All Dis-
played Signal Levels Are Attenuated 20 dB by the 10X Probe
Used to Measure the Mixer’s Output
HP3585A
WITH 10X PROBE
dBm REF TO 50Ω
DATEL
DVC-8500
W
2kΩ
Z1
Z2 10
HP3326A
HIGH VOLTAGE
OPTION
9
8
ER
VN
Y1
Y2
0.1µF
–15V
Figure 17. AD734 Mixer Test Circuit
Figure 17 shows a test circuit for measuring the AD734’s perfor-
mance in this regard. In this test, two signals, at 10.05 MHz and
9.95 MHz are summed and applied to the AD734’s X interface.
A second 9 MHz signal is applied to the AD734’s Y interface.
T he voltage at the U interface is set to 2 V to use the full
dynamic range of the AD734. T hat is, by connecting the W and
Z1 pins together, grounding the Y2 and X2 pins, and setting
U = 2 V, the overall transfer function is
X1Y1
W =
(14)
2 V
and W can be as high as 20 V p-p when X1 = 2 V p-p and Y1 =
10 V p-p. T he 2 V p-p signal level corresponds to +10 dBm into
a 50 Ω input termination resistor connected from X1 or Y1 to
ground.
Figure 19. AD734 Third-Order Interm odulation Perform ance
for f1 = 9.95 MHz, f2 = 10.05 MHz, and f0 = 9.00 MHz and for
Signal Levels of f1 & f2 of 0 dBm and f0 of +24 dBm . All Dis-
played Signal Levels Are Attenuated 20 dB by the 10X Probe
Used to Measure the Mixer’s Output
–10–
REV. B
Typical Characteristics–AD734
V
= ±15V
S
X = 1.4V RMS
Y = 10V
V
R
C
= ±15V
V = ±15V
S
S
0.3
0.2
0.06
0.04
0.02
0
= 2kΩ
R
= 2kΩ
LOAD
LOAD
LOAD
LOAD
R
= 500Ω
LOAD
LOAD
= 20pF
C
= 20pF
C
= 20pF
0.1
0.1
0.05
0
0
–0.1
–0.2
–0.3
–0.4
–0.02
–0.04
–0.06
–0.08
–0.05
–0.1
100k
1M
FREQUENCY – Hz
10M
–2V
0
2V
–2V
0
2V
SIGNAL AMPLITUDE
SIGNAL AMPLITUDE
Figure 20. Differential Gain at
Figure 21. Differential Phase at
Figure 22. Gain Flatness, 300 kHz to
3.58 MHz and RL = 2 kΩ
3.58 MHz and RL = 2 kΩ
10 MHz, RL = 500 Ω
0
100
100
80
INPUT SIGNAL = 7V RMS
–40
Y INPUT, X = 10V
80
Y INPUT, X NULLED
–60
60
60
VN
X INPUT, Y NULLED
–80
X INPUT, Y = 10V
40
VP
40
COMMON-MODE
20
–100
20
0
SIGNAL = 7V RMS
0
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
Figure 25. Feedthrough vs. Frequency
Figure 23. CMRR vs. Frequency
Figure 24. PSRR vs. Frequency
0
0
0
FREQUENCY = 1MHz
VP = 15V
VN = –15V
TEST INPUT = 1V RMS
U = 2V
OTHER INPUT = 2V DC
–20
TEST INPUT = 7V RMS
OTHER INPUT = 10V DC
–20
–20
R
= 2kΩ
R
= ≥ 2kΩ
LOAD
LOAD
–40
–60
–40
–40
–60
–80
X INPUT. Y = 10V DC
X INPUT
X INPUT
–60
Y INPUT
Y INPUT
Y INPUT. X = 10V DC
–80
–80
–100
–10dBm
10dBm
30dBm
70.7mV RMS
707mV RMS
7V RMS
1k
10k
100k
FREQUENCY – Hz
1M
10M
1k
10k
100k
FREQUENCY – Hz
1M
10M
SIGNAL LEVEL
Figure 27. THD vs. Frequency,
U = 10 V
Figure 28. THD vs. Signal Level,
f = 1 MHz
Figure 26. THD vs. Frequency,
U = 2 V
REV. B
–11–
AD734–Typical Characteristics
5
V
= ±15V
S
4
3
X = 1.4V rms
Y = 10V
R
0
–30
= 500Ω
LOAD
LOAD
C
= 20pF, 47pF,
100pF
2
INCREASING
C
1
–60
LOAD
V
= ±15V
S
X = 1.4V rms
Y = 10V
0
–90
–1
–2
–3
–4
–5
–120
–150
–180
R
C
= 500Ω
LOAD
LOAD
= 20pF, 47pF, 100pF
INCREASING
C
LOAD
100k
1M
10M
100k
1M
FREQUENCY – Hz
10M
FREQUENCY – Hz
Figure 31. Pulse Response vs.
LOAD, CLOAD = 0 pF, 47 pF,
100 pF, 200 pF
C
Figure 29. Gain vs. Frequency vs.
CLOAD
Figure 30. Phase vs. Frequency
vs. CLOAD
0
20
15
10
–10
U = 5V
U = 2V
U = 10V
U = 1V
5
0
–5
–20
X
Y
FREQ =
FREQ –1MHz
–10
–15
–20
1
1
(
E.G., Y – X = 1MHz
1 1
FOR ALL CURVES)
–30
10 20 30 40 50 60 70 80 90 100
8
9
10 11 12 13 14 15 16 17 18
Y
FREQUENCY – MHz
1
SUPPLY VOLTAGE – ±V
S
Figure 33. Output Am plitude vs. Input
Frequency, When Used as Dem odulator
Figure 32. Output Swing vs. Supply
Voltage
20
15
10
5
8
60
INPUT OFFSET VOLTAGE
DRIFT WILL TYPICALLY BE
WITHIN SHADED AREA
INPUT OFFSET VOLTAGE
DRIFT WILL TYPICALLY BE
WITHIN SHADED AREA
INPUT OFFSET VOLTAGE
DRIFT WILL TYPICALLY BE
WITHIN SHADED AREA
6
4
40
20
2
0
0
0
–20
–40
–60
–5
–10
–15
–2
–4
–6
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE – °C
TEMPERATURE – °C
TEMPERATURE – °C
Figure 34. VOS Drift, X Input
Figure 36. VOS Drift, Y Input
Figure 35. VOS Drift, Z Input
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
14-P in P lastic D IP (N) P ackage
14-P in Ceram ic D IP (Q) P ackage
14
1
8
0.280 (7.11)
0.240 (6.10)
PIN 1
7
0.325 (8.25)
0.300 (7.62)
0.795 (20.19)
0.725 (18.42)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210
(5.33)
MAX
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
0.160 (4.06)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
–12–
REV. B
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