LA9239T [ETC]
;
ETC 
Ordering number : ENN7131
Monolithic Linear IC
LA9239T
48× CD-ROM Digital Servo RF IC
Overview
Features
The LA9239T is a CD-ROM digital servo RF IC that
supports high-speed CD-ROM drive replay of up to 48×. It
also supports RW disks by featuring an on-chip servo
VCA and gain switch.
The LA9239T is an IC that features on-chip functions for
improved playability and an RF equalizer, resulting in
superior performance and a reduced need for external
components.
Functions
• RF amplifier (with AGC)
Package Dimensions
unit: mm
• RF gain amplifier (supporting CD-RW disk replay)
• RF equalizer (7 modes)
• RF hold function
3253-TSSOP36
[LA9239T]
9.95
• PH/BH detection
36
19
• 3T extraction circuit
• FE amplifier (built-in balance adjustment VCA)
• TE amplifier (built-in balance adjustment VCA)
• servo signal VCA circuit
• APC circuit (with laser power-up function)
• sleep function
1
18
0.15
(0.5)
0.725
0.22
SANYO: TSSOP36
Specifications
Maximum Ratings at Ta = 25°C, Pins 4 and 31 = GND
Parameter
Maximum power supply voltage
Allowable power dissipation
Operating temperature
Symbol
Conditions
Ratings
Unit
V
V
CC max
Pd max
Topr
7
300
mW
°C
–25 to +70
–40 to +150
Storage temperature
Tstg
°C
Operating Conditions at Ta = 25°C
Parameter
Symbol
VCC
Conditions
Ratings
5
Unit
V
Recommended power supply voltage
Allowable operating voltage range
VCC op
4.5 to 5.5
V
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
11502RM (OT) No. 7131-1/9
LA9239T
Operating Characteristics at Ta = 25°C, V (Pins 23, 34) = 5 V, GND (Pins 4, 31) = 0 V
CC
Ratings
typ
30
Parameter
Current drain
Symbol
Conditions
Unit
min
18
max
42
ICC
ICCS
Vref
No signal
mA
mA
V
Current drain (during sleep)
Reference voltage
Preamplifier offset
RF no-signal voltage
RF gain max
No signal, EQS = 0 V
2
2.3
6
10
2.7
2.5
0
RFAOost Difference with VR in RFA0
–120
1.5
+120
2.3
mV
V
RFSM
RFG1
RFG2
FIN1, FIN2 = VR
GHS = 0 V
1.8
21
19
23
dB
dB
dB
RF gain min
GHS = 0 V
4
6
8
RF gain UP
RFGUP GHS = 5 V
RFSM difference when FIN1, 2: 350 mVp-p,
12.5
14
15.5
RFEQ normal
RFEQ CAV1
RFEQ CAV2
RFEQ CAV3
RFEQ CAV4
RFEQ CAV5
RFEQ CAV6
RFEQN f = 1 MHz and 350 mVp-p, f = 100 kHz,
EQS = 5 V, BHC = 2.45 V, PHC = 2.8 V
1.5
1
3.5
3
5.5
5
dB
dB
dB
dB
dB
dB
dB
RFSM difference when FIN1, 2: 350 mVp-p,
RFEQ1 f = 2.4 MHz and 350 mVp-p, f = 100 kHz,
EQS = 4.1 V, BHC = 2.45 V, PHC = 2.8 V
RFSM difference when FIN1, 2: 350 mVp-p,
RFEQ2 f = 4.4 MHz and 350 mVp-p, f = 100 kHz,
EQS = 3.4 V, BHC = 2.45 V, PHC = 2.8 V
1
3
5
RFSM difference when FIN1, 2: 350 mVp-p,
RFEQ3 f = 6 MHz and 350 mVp-p, f = 100 kHz,
EQS = 2.8 V, BHC = 2.45 V, PHC = 2.8 V
1
3
5
RFSM difference when FIN1, 2: 350 mVp-p,
RFEQ4 f = 8 MHz and 350 mVp-p, f = 100 kHz,
EQS = 2.2 V, BHC = 2.45 V, PHC = 2.8 V
1
3
5
RFSM difference when FIN1, 2: 350 mVp-p,
RFEQ5 f = 12 MHz and 350 mVp-p, f = 100 kHz,
EQS = 1.6 V, BHC = 2.45 V, PHC = 2.8 V
1
3
5
RFSM difference when FIN1, 2: 350 mVp-p,
RFEQ6 f = 30 MHz and 350 mVp-p, f = 100 kHz,
EQS = 0.9 V, BHC = 2.45 V, PHC = 2.8 V
0.5
2.5
4.5
RF hold
RFHLD FIN1, 2: 700 mVp-p, f = 100 kHz, RHLD = 5 V
–13.5
2.7
–20
1.3
7
–11
3.3
–16.5
1.6
9
–8.5
3.9
–13
1.9
11
dB
V
PH
PH
3TON
BH
RFSM = 1.7 Vp-p
3T extraction
BH
Difference with RFSM for 3TON = 5 V, PH
RFSM = 1.7 Vp-p
dB
V
BH band switch
REFL offset
REFL gain 1
REFL gain 2
FE offset
BHH
f = 100 kHz, RHH = 5 V
dB
mV
dB
dB
mV
dB
dB
dB
dB
mV
dB
dB
dB
dB
mV
dB
dB
kHz
kHz
mV
mV
V
REFLost Difference with VR for REFL
REFL1 FIN1 = Vin, FIN2 = VR, SGC = 2 V
REFL2 FIN1 = Vin, FIN2 = VR, SGC = 3 V
–120
9
0
+120
13
11
14.5
–120
5
16.5
0
18.5
+120
9
FEost
FEG1
FEG2
FBAL1
FBAL2
TEost
TEG1
TEG2
TBAL1
TBAL2
TSost
TSG1
TSG2
TSHL
TSHH
LDSL
LDSH
LDD
Difference with VR for FE
FE gain 1
FIN1 = Vin, FIN2 = VR, SGC = 2 V, FBAL = VR
FIN1 = Vin, FIN2 = VR, SGC = 3 V, FBAL = VR
FIN1 = Vin, FIN2 = VR, SGC = VR, FBAL = 2 V
FIN1 = Vin, FIN2 = VR, SGC = VR, FBAL = 3 V
Difference with VR for TE
7
FE gain 2
10
12
14
FE balance 1
FE balance 2
TE offset
10.5
7.5
–120
13.5
19
12.5
9.5
0
14.5
11.5
+120
17.5
23
TE gain 1
E = Vin, F = VR, SGC = 2 V, TBAL = VR
E = Vin, F = VR, SGC = 3 V, TBAL = VR
E = Vin, F = VR, SGC = VR, TBAL = 2 V
E = Vin, F = VR, SGC = VR, TBAL = 3 V
Difference with VR for TS
15.5
21
TE gain 2
TE balance 1
TE balance 2
TS offset
20
22
24
16
18
20
–120
13
0
+120
17
TS gain 1
GHS = 0 V, TBAL = VR
15
TS gain 2
GHS = 5 V, TBAL = VR
25
27
29
TS band 1
TE-TE- = 82 P, TSH = 0 V
16
20
24
TS band 2
TE-TE- = 82 P, TSH = 5 V
240
175
215
4
300
190
230
4.3
360
205
245
5
APC reference voltage 1
APC reference voltage 2
APC off voltage
LSD voltage for LDD = 3 V, LDON = 0 V
LSD voltage for LDD = 3 V, LDON = 5 V
LDON = VR
No. 7131-2/9
LA9239T
Explanation of Operation
(1) RF amplifier
The RF signal is generated by inputting (A+C) from FIN2 (pin 8) and (B+D) from FIN1 (pin 7) and adding the two.
The EFM signal is output from the RFSM (pin 33) via the preamplifier, gain switch, RFAGC circuit, and 3T
compensation circuit. The RFSUM output D range is 1 to 4 V. 3T compensation can be done according to the band
through the EQS (pin 18) control pin.
The gain switch enables replay of CD and CD-RW disks, and when GHS (pin 16) level is made Hi (CD-RW mode), a
gain of 14 dB can be obtained. In the CD mode, the gain is 0 dB.
The on-chip AGC circuit has a variable range of ±6 dB. The peak level controls the RFAGC level, and the bottom
level controls the DC level of RF. The respective frequency response characteristics can be changed with the external
capacitors connected to PHC (pin 2) and BHC (pin 1).
The response frequency is proportional to the capacitance of the PHC and BHC capacitors.
When a defect is detected in the DSP, AGC control can be changed to the hold status (by making RHLD (pin 32) Hi)
to prevent the RF signal from becoming unstable.
(2) Focus error amplifier
The focus error signal is generated by inputting (A+C) to FIN2 (pin 8) and (B+D) to FIN1 (pin 7), passing these
signals through the focus balance adjustment VCA, and extracting the difference between the two ((B+D)–(A+C)).
The FE signal is gain controlled by FE-VCA and output to FE (pin 28). The FE signal gain can be set with the resistor
connected between FE and FE- (pin 29).
The focus balance adjustment VCA is controlled by FBAL (pin 21), and FE-VCA is controlled by SGC (pin 19). A
gain of +12 dB for the FE signal gain is obtained in the RW mode by making the GS level Hi.
Note: The polarity of the FE output in relation to the FIN1 input is common-mode output.
(3) Tracking error amplifier
The tracking error signal is generated through input to E (pin 9) and F (pin 10), passing the signals through the
tracking balance adjustment VCA, and detecting their difference. The TE signal is gain controlled at TE-VCA and
output from TE (pin 26). The TE signal gain can be set with the resistor connected between TE and TE- (pin 27). The
tracking balance adjustment VCA is controlled by TBAL (pin 20), and TE-VCA is controlled by SGC (pin 19).
The TE signal for the TES comparator is output from TS (pin 23). The TS signal level must meet the TES comparator
level in the DSP. Setting of this level is performed with the pickup output and the resistor between the E and F inputs.
In the RW mode, a gain of +12 dB for TE and TS signal gain is obtained by making the GHS (pin 16) level Hi (same
as for RF). An on-chip band switch is also provided to support high-speed seek for the TS signal, which is controlled
with TSH (pin 22). The band can be set with the capacitance between TSS (pin 25) and TS.
Note: The polarity of the TE output in relation to the E input is inverted output, and the polarity of the TS output in
relation to the E input is also inverted output.
(4) APC (auto laser power control)
The APC controls the pickup laser power. Since CD-RW disks are also supported, a laser power-up (+20%) function
is also provided. Laser ON/OFF and laser power-up control are performed with LDON (pin 15).
(5) REFL detection (reflected light detection) and focus detection
The reflected light amount signal from the disk is added to the FIN1 and FIN2 inputs (A+B+C+D) and fetched. It is
then gain controlled at REFL-VCA and output from REFL (pin 30) to the DSP. This output signal is used to control
SGC (pin 19) to secure the D range of the servo signal in relation to disk irregularities. The amount of light is judged
by the DSP and SGC control is performed. REFL-VCA is controlled by SGC. During RW replay, the REFL gain is
increased by 12 dB (GHS = Hi).
The REFL signal is also used as a signal for focus detection.
Note: The polarity of the REFL output in relation to the FIN1 input is common-mode output.
No. 7131-3/9
LA9239T
(6) BH (RF bottom hold signal)
The HFL (mirror) detection signal is generated at BH (pin 35), and HFL (mirror) is detected in the DSP. The DSP
detects the track jump direction using the phase difference with TES. Moreover, this BH circuit has a band switching
function that can be controlled with BHH (pin 17). (BHH = Hi for wide band)
(7) PH (RF peak hold signal)
The RF peak hold signal used for defect detection is output from PH. The DSP performs defect detection judgments
based on this signal. Since the EFM signal level is not necessarily stable due to the influence of the disk's reflection
factor, consideration must be paid to using as reference the PH signal level measured when there are no scratches, for
defect judgment. Moreover, the PH circuit performs constant settings during PH demodulation according to the speed.
This is controlled along with the RF equalizer by the EQS (pin 18) control pin.
The system is designed so that, during focus balance adjustment, the peak and bottom levels of the 3T component are
detected and output as the error signal. During focus balance adjustment, 3T is extracted and output from PH and BH
by setting 3TON (pin 6) to Hi.
(8) Sleep
The sleep status can be selected in order to reduce the current drain of the IC.
(Sleep is selected with EQS (pin 18) = GND.)
Usage Note
The level of the signals input to FIN1 (pin 7), FIN2 (pin 8), E (pin 9), and F (pin 10) must be set so that it is higher than
the reference voltage (VREF).
Relationships between control pin voltages and operation modes
1. 3TON (pin 6)
Extracts 3T and performs focus balance adjustment.
Mode
3TON
3TOFF
Min
3.0 V
0 V
Max
5.0 V
2.0 V
Extraction Frequency
10 MHz
—
2. LDON (pin 15)
Laser ON and laser power-up (20%) switch control
Mode
PUPH
Min
3.5 V
2.0 V
0 V
Max
5.0 V
3.0 V
1.5 V
Laser
ON
Power Up
Hi
LDOF
OFF
ON
Low
LDON+PUPL
Low
3. GHS (pin 16)
RF and TS gain-up (+14 dB) switch control
Mode
Min
3.0 V
0 V
Max
5.0 V
2.0 V
Gain Up
Hi
RW support
CD support
Low
4. BHH (pin 17)
Reduces the time constant during bottom hold when the access speed is slow.
Mode
Min
3.0 V
0 V
Max
5.0 V
2.0 V
Band (fc)
450 kHz
80 kHz
Hi (during normal operation)
Low (when access speed is slow)
No. 7131-4/9
LA9239T
5. TSH (pin 22)
TS filter setting pin for TES signal
TSH
Min
3.0 V
0 V
Max
5.0 V
2.0 V
TS Band
300 kHz
Hi (during seek)
Low (other than seek)
20 kHz (between pins 24 and 25: 80P)
6. EQS (pin 18)
RF equalizer, PH detection time constant control (7 modes), and sleep switch control
PH time constant switching is done according to the equalizer switch.
Mode
Normal
CAV1
CAV2
CAV3
CAV4
CAV5
CAV6
Sleep
Min
Max
5.0 V
4.3 V
3.6 V
3.0 V
2.4 V
1.8 V
1.2 V
0.5 V
+2 dB Boost Frequency
Approx. 1.0 MHz
Approx. 2.4 MHz
Approx. 4.3 MHz
Approx. 6.0 MHz
Approx. 8.0 MHz
Approx. 11 MHz
Approx. 30 MHz
—
11T Frequency
Approx. 200 kHz
Approx. 2.4 MHz
Approx. 3.5 MHz
Approx. 3.9 MHz
Approx. 4.7 MHz
Approx. 5.9 MHz
Approx. 9.4 MHz
—
4.5 V
3.9 V
3.2 V
2.6 V
2.0 V
1.4 V
0.8 V
0 V
7. RHLD (pin 32)
RHLD
Min
3.0 V
0 V
Max
5.0 V
2.0 V
Hi (during defect detection)
Low (during normal operation)
No. 7131-5/9
LA9239T
Pin Description
Pin No.
Pin Name
BHC
Description
1
2
3
4
5
6
Bottom hold capacitor connection pin for RF AGC detection
Peak hold capacitor connection pin for RF AGC detection
RF preamplifier output pin
PHC
RFAO
GND1
RFA–
3TON
RF signal GND pin
RF preamplifier minus input pin
3T extraction circuit control pin
Pickup voltage output connection pin. The RF signal and mirror signal are generated by adding FIN1 to
FIN2, and the FE signal is generated by subtracting FIN1 from FIN2.
7
FIN1
8
FIN2
E
Pickup voltage output connection pin
Pickup voltage output connection pin. The TE signal is generated by subtracting E from F.
Pickup voltage output connection pin
Reference voltage bus capacitor connection pin
Reference voltage output pin
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
F
REFI
VREF
LDD
LDS
LDON
GHS
BHH
EQS
SGC
TBAL
FBAL
TSH
VCC2
TS
APC circuit output pin
APC circuit input pin
Laser ON/OFF, laser power-up control pin
RF, TS signal gain switch pin (0 dB/+14 dB)
BH response switch pin
RF equalizer, PH detection control pin
Servo gain control pin (FE, TE, REFL signals)
TE balance adjustment pin
FE balance adjustment pin
TS signal band control pin
Servo signal VCC pin
TS signal (TES signal source) output pin (→ DSP)
TS signal band setting pin
TSS
TE
TE signal output pin (→ DSP)
TE–
TE signal gain setting pin
FE
FE signal output pin (→ DSP)
FE–
Servo signal GND pin
REFL
GND2
RHLD
RFSM
VCC1
BH
Reflection signal output pin (→ DSP)
Servo signal GND pin
RF hold control pin
EFM signal output pin (→ DSP)
RF signal VCC pin
RF bottom hold signal output pin (→ DSP)
RF peak hold signal output pin (→ DSP)
PH
No. 7131-6/9
LA9239T
Block Diagram
BHC
PH
BH
REF
REF
1
2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RFAGC
RFAGC
PHC
RFA0
GND1
RFA--
5V
1
V
CC
3
V
CC
RFSM
RHLD
GND2
-- +
4
REF
--
+
REF
5
3TON
FIN1
6
REFL-VCA
REFL
FE--
FE
7
BAL
+GUP
FIN2
E
8
F.-VCA
T.-VCA
--
+
9
BAL
FE AMP
TE AMP
+GUP
F
TE--
TE
10
11
12
13
14
15
16
17
18
REFI
--
+
DSP
REF
TSS
TS
VREF
LDD
V
CC
--
+
5V
2
V
LDS
CC
APC
TS AMP
REF
V
CC
LDON
TSH
GHS
BHH
EQS
FBAL
TBAL
SGC
No. 7131-7/9
LA9239T
Test Circuit
PH
BH
BHC
REF
REF
1
2
BH
36 PH
35 BH
0.1µF
PHC
0.1µF
PH-CONTROL
7_MODE
3TFIL.
PH
EQ-CONTROL
5V
V
1
CC
RFA0
GND1
RFA--
3
34
+
V
CC
-- +
--
+
4
33 RFSM
32 RHLD
--
+
REF
REF
REF
7_MODE
--
+
+
5
GND2
31
3TON
FIN1
6
100kΩ
0.1µF
100kΩ
+
--
+
--
--
+
7
30 REFL
REF
FE--
29
FIN2
E
REF
REF
REF
8
0.1µF
+
--
FE
28
--
+
--
9
+
56kΩ
0.1µF
F
TE--
27
10
11
12
56kΩ
+
--
REF
REF
REFI
TE
26
--
+
0.1µF
V
CC
0.1µF
VREF
TSS
25
+
--
--
--
+
TS
24
LDD 13
LDS 14
LDON 15
GHS 16
BHH 17
EQS 18
--
+
5V
V
2
CC
REF
23
V
CC
+
V
CC
REF
22 TSH
REF
21 FBAL
20 TBAL
19 SGC
No. 7131-8/9
LA9239T
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of January, 2002. Specifications and information herein are subject
to change without notice.
PS No. 7131-9/9
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