LC00A [ETC]
具体型号：SN54LVC00A, SN74LVC00A; 具体型号： SN54LVC00A ， SN74LVC00A
| 型号： | LC00A |
| 厂家： | 
ETC |
| 描述： | 具体型号：SN54LVC00A, SN74LVC00A |
| 文件： | 总8页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279G – JANUARY 1993 – REVISED JUNE 1998
SN54LVC00A . . . J OR W PACKAGE
SN74LVC00A . . . D, DB, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
2Y
GND
= 3.3 V, T = 25°C
CC
A
8
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
SN54LVC00A . . . FK PACKAGE
(TOP VIEW)
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and DIPs (J)
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
2A
4
5
6
7
8
17
16
description
NC
2B
15 NC
14
9 10 11 12 13
3B
The SN54LVC00A quadruple 2-input positive-
NAND gate is designed for 2.7-V to 3.6-V V
CC
operation and the SN74LVC00A quadruple
2-inputpositive-NANDgateisdesignedfor1.65-V
to 3.6-V V
operation.
CC
NC – No internal connection
The ’LVC00A devices perform the Boolean
function Y = A • B or Y = A + B in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN54LVC00A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVC00A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279G – JANUARY 1993 – REVISED JUNE 1998
†
logic symbol
1
1A
1B
2A
2B
3A
3B
4A
4B
&
3
6
2
1Y
2Y
3Y
4Y
4
5
9
8
10
12
13
11
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, PW, and W packages.
logic diagram, each gate (positive logic)
A
B
Y
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279G – JANUARY 1993 – REVISED JUNE 1998
recommended operating conditions (see Note 4)
SN54LVC00A
SN74LVC00A
UNIT
MIN
2
MAX
MIN
MAX
Operating
3.6
1.65
1.5
3.6
V
V
Supply voltage
V
CC
Data retention only
1.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65×V
1.7
CC
High-level input voltage
V
V
IH
2
2
0.35×V
0.7
CC
V
IL
Low-level input voltage
0.8
5.5
0.8
V
V
Input voltage
0
0
0
0
5.5
V
V
I
Output voltage
V
V
O
CC
CC
–4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–8
I
High-level output current
mA
OH
OL
–12
–24
–12
–24
4
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
8
I
Low-level output current
mA
12
24
12
24
85
T
A
Operating free-air temperature
–55
125
–40
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279G – JANUARY 1993 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC00A
SN74LVC00A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
†
†
MIN TYP
MAX
MIN TYP
V –0.2
CC
MAX
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
I
= –100 µA
OH
V
–0.2
CC
I
I
= –4 mA
= –8 mA
1.2
OH
V
OH
2.3 V
1.7
2.2
2.4
2.2
V
OH
2.7 V
2.2
I
I
I
= –12 mA
= –24 mA
= 100 µA
OH
OH
OL
3 V
2.4
2.2
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
0.2
0.2
I
I
I
I
= 4 mA
= 8 mA
= 12 mA
= 24 mA
0.45
0.7
0.4
0.55
±5
OL
OL
OL
OL
V
OL
V
2.3 V
2.7 V
0.4
0.55
±5
3 V
I
I
V = 5.5 V or GND
3.6 V
µA
µA
I
I
V = V
or GND,
I = 0
O
3.6 V
10
10
CC
I
CC
One input at V
– 0.6 V,
or GND
CC
Other inputs at V
∆I
CC
2.7 V to 3.6 V
3.3 V
500
500
µA
CC
or GND
C
V = V
5
5
pF
i
I
CC
= 3.3 V, T = 25°C.
†
All typical values are at V
CC
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC00A
FROM
(INPUT)
TO
(OUTPUT)
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
pd
A or B
5.1
1
4.3
ns
Y
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC00A
FROM
(INPUT)
TO
(OUTPUT)
V = 1.8 V
CC
± 0.15 V
V = 2.5 V
CC
± 0.2 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
4.3
1
‡
‡
‡
‡
t
A or B
5.1
1
ns
ns
Y
pd
§
t
sk(o)
‡
§
This information was not available at the time of publication.
Skew between any two outputs of the same package switching in the same direction
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279G – JANUARY 1993 – REVISED JUNE 1998
operating characteristics, T = 25°C
A
V
= 1.8 V
± 0.15 V
V
= 2.5 V
V
= 3.3 V
CC
CC
± 0.2 V
CC
± 0.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
†
†
C
Power dissipation capacitance per gate
f = 10 MHz
9.5
pF
pd
†
This information was not available at the time of publication.
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1k Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
Open
L
PLZ PZL
1k Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279G – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC00A, SN74LVC00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS279G – JANUARY 1993 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
6 V
Open
GND
S1
TEST
S1
500 Ω
From Output
Under Test
t
pd
Open
6 V
t
/t
PLZ PZL
/t
C
= 50 pF
t
GND
L
PHZ PZH
500 Ω
(see Note A)
t
w
LOAD CIRCUIT
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Data
Input
2.7 V
0 V
1.5 V
1.5 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
(see Note B)
OL
OH
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 3. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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