LH28F320BJB-PTTL90 [ETC]
Flash ROM ; 闪存可编程性
| 型号： | LH28F320BJB-PTTL90 |
| 厂家： | 
ETC |
| 描述： | Flash ROM
|
| 文件： | 总47页 (文件大小：683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Date
ꢀ
Oct. 18. 2000
32M (x8/x16) Flash Memory
LH28F320BJB-PTTL90
LHF32J10
●Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.
●When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands high reliability, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
•Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative of the
company.
Rev. 1.27
LHF32J10
CONTENTS
PAGE
1
PAGE
1 INTRODUCTION..............................................................3
1.1 Features ........................................................................3
1.2 Product Overview.........................................................3
1.3 Product Description......................................................4
1.3.1 Package Pinout .......................................................4
1.3.2 Block Organization.................................................4
5 DESIGN CONSIDERATIONS ....................................... 27
5.1 Three-Line Output Control ........................................ 27
5.2 RY/BY# and WSM Polling ....................................... 27
5.3 Power Supply Decoupling ......................................... 27
5.4 V
Trace on Printed Circuit Boards ..................... 27
CCW
5.5 V , V
, RP# Transitions .................................... 27
CC
CCW
5.6 Power-Up/Down Protection....................................... 28
5.7 Power Dissipation...................................................... 28
5.8 Data Protection Method............................................. 28
2 PRINCIPLES OF OPERATION........................................8
2.1 Data Protection.............................................................8
3 BUS OPERATION ............................................................9
3.1 Read..............................................................................9
3.2 Output Disable..............................................................9
3.3 Standby.........................................................................9
3.4 Reset.............................................................................9
3.5 Read Identifier Codes.................................................10
3.6 OTP(One Time Program) Block ................................10
3.7 Write...........................................................................11
6 ELECTRICAL SPECIFICATIONS ................................ 29
6.1 Absolute Maximum Ratings ...................................... 29
6.2 Operating Conditions................................................. 29
6.2.1 Capacitance.......................................................... 29
6.2.2 AC Input/Output Test Conditions ........................ 30
6.2.3 DC Characteristics ............................................... 31
6.2.4 AC Characteristics - Read-Only Operations........ 33
6.2.5 AC Characteristics - Write Operations ................ 36
6.2.6 Alternative CE#-Controlled Writes...................... 38
6.2.7 Reset Operations .................................................. 40
6.2.8 Block Erase, Full Chip Erase, Word/Byte Write and
Lock-Bit Configuration Performance ................. 41
4 COMMAND DEFINITIONS...........................................11
4.1 Read Array Command................................................13
4.2 Read Identifier Codes Command ...............................13
4.3 Read Status Register Command.................................13
4.4 Clear Status Register Command.................................13
4.5 Block Erase Command...............................................14
4.6 Full Chip Erase Command .........................................14
4.7 Word/Byte Write Command.......................................14
4.8 Block Erase Suspend Command ................................15
4.9 Word/Byte Write Suspend Command ........................15
4.10 Set Block and Permanent Lock-Bit Command.........16
4.11 Clear Block Lock-Bits Command ............................16
4.12 OTP Program Command..........................................17
4.13 Block Locking by the WP# ......................................17
Rev. 1.27
LHF32J10
2
LH28F320BJB-PTTL90
32M-BIT ( 2Mbit ×16 / 4Mbit ×8 )
Boot Block Flash MEMORY
● Low Voltage Operation
● Enhanced Automated Suspend Options
V
=V
=2.7V-3.6V Single Voltage
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
CC
CCW
● OTP(One Time Program) Block
3963 word + 4 word Program only array
● Enhanced Data Protection Features
● User-Configurable ×8 or ×16 Operation
● High-Performance Read Access Time
Absolute Protection with V
≤V
CCW
CCWLK
Block Erase, Full Chip Erase, Word/Byte Write and
Lock-Bit Configuration Lockout during Power
Transitions
90ns(V =2.7V-3.6V)
CC
Block Locking with Command and WP#
Permanent Locking
● Operating Temperature
0°C to +70°C
● Automated Block Erase, Full Chip Erase,
Word/Byte Write and Lock-Bit Configuration
● Low Power Management
Command User Interface (CUI)
Typ. 4µA (V =3.0V) Standby Current
CC
Status Register (SR)
Automatic Power Savings Mode Decreases I
Static Mode
in
CCR
Typ. 120µA (V =3.0V, T =+25°C, f=32kHz)
Read Current
● SRAM-Compatible Write Interface
CC
A
● Chip-Size Packaging
● Optimized Array Blocking Architecture
Two 4K-word (8K-byte) Boot Blocks
Six 4K-word (8K-byte) Parameter Blocks
Sixty-three 32K-word (64K-byte) Main Blocks
Top Boot Location
60-Ball CSP
TM*
● ETOX
Nonvolatile Flash Technology
● CMOS Process (P-type silicon substrate)
● Not designed or rated as radiation hardened
● Extended Cycling Capability
Minimum 100,000 Block Erase Cycles
SHARP’s LH28F320BJB-PTTL90 Flash memory is a high-density, low-cost, nonvolatile, read/write storage solution for a
wide range of applications.
LH28F320BJB-PTTL90 can operate at V =2.7V-3.6V and V
capability realize battery life and suits for cellular phone application.
=2.7V-3.6V or 11.7V-12.3V. Its low voltage operation
CC
CCW
Its Boot, Parameter and Main-blocked architecture, low voltage and extended cycling provide for highly flexible component
suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code
+ data storage applications.
For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to
DRAM, the LH28F320BJB-PTTL90 offers four levels of protection: absolute protection with V
≤V
, selective
CCW
CCWLK
hardware block locking or flexible software block locking. These alternatives give designers ultimate control of their code
security needs.
TM*
The LH28F320BJB-PTTL90 is manufactured on SHARP’s 0.25µm ETOX
package: the 60-ball CSP, ideal for board constrained applications.
process technology. It come in chip-size
*ETOX is a trademark of Intel Corporation.
Rev. 1.27
LHF32J10
3
A block erase operation erases one of the device’s 32K-
1 INTRODUCTION
word/64K-byte blocks typically within 1.2s (3V V , 3V
CC
V
V
), 4K-word/8K-byte blocks typically within 0.6s (3V
This
datasheet
contains
LH28F320BJB-PTTL90
CCW
CC
, 3V V
) independent of other blocks. Each block
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
CCW
can be independently erased minimum 100,000 times.
Block erase suspend mode allows system software to
suspend block erase to read or write data from any other
block.
1.1 Features
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
Key enhancements of LH28F320BJB-PTTL90 boot block
Flash memory are:
within 33µs (3V V , 3V V
), 64K-byte blocks
CC
CCW
typically within 31µs (3V V , 3V V
), 4K-word
CC
CCW
blocks typically within 36µs (3V V , 3V V
), 8K-
CC
CCW
•Single low voltage operation
•Low power consumption
•Enhanced Suspend Capabilities
•Boot Block Architecture
byte blocks typically within 32µs (3V V , 3V V
).
CC
CCW
Word/byte write suspend mode enables the system to read
data or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits,
seventy-one block lock-bits, a permanent lock-bit and
WP# pin, to lock and unlock blocks. Block lock-bits gate
block erase, full chip erase and word/byte write
operations, while the permanent lock-bit gates block lock-
bit modification and locked block alternation. Lock-bit
configuration operations (Set Block Lock-Bit, Set
Permanent Lock-Bit and Clear Block Lock-Bits
commands) set and cleared lock-bits.
Please note following:
•V
has been lowered to 1.0V to support 2.7V-
CCWLK
3.6V block erase, full chip erase, word/byte write and
lock-bit configuration operations. The V voltage
CCW
transitions to GND is recommended for designs that
switch V off during read operation.
CCW
1.2 Product Overview
The status register indicates when the WSM’s block erase,
full chip erase, word/byte write or lock-bit configuration
operation is finished.
The LH28F320BJB-PTTL90 is a high-performance 32M-
bit Boot Block Flash memory organized as 2M-word of 16
bits or 4M-byte of 8 bits. The 2M-word/4M-byte of data is
arranged in two 4K-word/8K-byte boot blocks, six 4K-
word/8K-byte parameter blocks and sixty-three 32K-
word/64K-byte main blocks which are individually
erasable, lockable and unlockable in-system. The memory
map is shown in Figure 3.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase, full chip erase,
word/byte write or lock-bit configuration. RY/BY#-high Z
indicates that the WSM is ready for a new command,
block erase is suspended (and word/byte write is
inactive), word/byte write is suspended, or the device is in
reset mode.
The dedicated V
pin gives complete data protection
CCW
when V
≤V
.
CCW
CCWLK
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase, full chip erase,
word/byte write and lock-bit configuration operations.
Rev. 1.27
LHF32J10
4
The access time is 90ns (t
temperature range (0°C to +70°C) and V supply voltage
range of 2.7V-3.6V.
) over the operating
1.3 Product Description
1.3.1 Package Pinout
AVQV
CC
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
LH28F320BJB-PTTL90 Boot Block Flash memory is
available in 60-ball CSP package (see Figure 2).
(addresses not switching). In APS mode, the typical I
CCR
current is 4µA (CMOS) at 3.0V V
.
CC
1.3.2 Block Organization
When CE# and RP# pins are at V , the I
CMOS
CC
CC
This product features an asymmetrically-blocked
architecture providing system memory integration. Each
erase block can be erased independently of the others up to
100,000 times. For the address locations of the blocks, see
the memory map in Figure 3.
standby mode is enabled. When the RP# pin is at GND,
reset mode is enabled which minimizes power
consumption and provides write protection. A reset time
(t
) is required from RP# switching high until outputs
PHQV
are valid. Likewise, the device has a wake time (t
)
PHEL
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
Boot Blocks: The boot block is intended to replace a
dedicated boot PROM in
a
microprocessor or
microcontroller-based system. This boot block 4K words
(4,096words) features hardware controllable write-
protection to protect the crucial microprocessor boot code
from accidental modification. The protection of the boot
Please do not execute reprogramming "0" for the bit which
has already been programed "0". Overwrite operation may
generate unerasable bit. In case of reprogramming "0" to
the data which has been programed "1".
block is controlled using a combination of the V
WP# pins and block lock-bit.
, RP#,
CCW
·Program "0" for the bit in which you want to change
data from "1" to "0".
Parameter Blocks: The boot block architecture includes
parameter blocks to facilitate storage of frequently update
small parameters that would normally require an
EEPROM. By using software techniques, the word-rewrite
functionality of EEPROMs can be emulated. Each boot
block component contains six parameter blocks of 4K
words (4,096 words) each. The protection of the parameter
·Program "1" for the bit which has already been
programmed "0".
For example, changing data from "10111101" to
"10111100" requires "11111110" programming.
block is controlled using a combination of the V
and block lock-bit.
, RP#
CCW
Main Blocks: The reminder is divided into main blocks for
data or code storage. Each 32M-bit device contains sixty-
three 32K words (32,768 words) blocks. The protection of
the main block is controlled using a combination of the
V
, RP# and block lock-bit.
CCW
Rev. 1.27
LHF32J10
5
DQ -DQ
0
15
Output
Buffer
Input
Buffer
V
I/O
Logic
CC
Identifier
Register
BYTE#
CE#
WE#
OE#
RP#
WP#
Command
User
Interface
Status
Register
Data
Comparator
RY/BY#
Y
Input
Buffer
Y-Gating
Write
State
Machine
A
-A
Decoder
-1 20
V
CCW
Program/Erase
Voltage Switch
32K-Word
V
Address
Latch
CC
X
(64K-Byte)
Main Blocks
×63
Decoder
GND
Address
Counter
Figure 1. Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
A14
A15
A12
A9
A
B
C
D
E
A13
A16
NC
NC
NC
GND BYTE#
NC
NC
NC
A10
A20
A11
A8
DQ15/A-1 DQ14
DQ7
DQ13
DQ4
DQ3
DQ9
DQ0
CE#
DQ6
DQ12
DQ10
DQ5
VCC
60-BALL CSP
RP# RY/BY#
WE#
WP#
A17
A5
PINOUT
11mm x 8mm
TOP VIEW
VCCW
A18
A6
A19
A7
A4
A1
DQ11
DQ2
DQ8
GND
DQ1
OE#
A0
F
G
H
A2
A3
NC
NC
NC
NC
NC
NC
Figure 2. CSP 60-Ball Pinout
Rev. 1.27
LHF32J10
6
Table 1. Pin Descriptions
Symbol
Type
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A
-1
INPUT
A : Lower address input while BYTE# is V . A pin changes DQ pin while BYTE# is V .
-1
IL
-1
15
IH
A -A
0
20
A -A : Main Block Address.
15 20
A -A : Boot and Parameter Block Address.
12 20
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data
during memory array, status register and identifier code read cycles. Data pins float to high-
INPUT/
OUTPUT
DQ -DQ
impedance when the chip is deselected or outputs are disabled. Data is internally latched during a
write cycle. DQ -DQ pins are not used while byte mode (BYTE#=V ). Then, DQ pin
0
15
8
15
IL
15
changes A address input.
-1
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
CE#
RP#
INPUT
INPUT
RESET: Resets the device internal automation. RP#-high enables normal operation. When driven
low, RP# inhibits write operations which provides data protection during power transitions. Exit
from reset mode sets the device to read array mode. RP# must be V during power-up.
IL
OE#
INPUT
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
the rising edge of the WE# pulse.
WE#
WRITE PROTECT: When WP# is V , boot blocks cannot be written or erased. When WP# is
IL
WP#
INPUT
INPUT
V , locked boot blocks can not be written or erased. WP# is not affected parameter and main
blocks.
IH
BYTE ENABLE: BYTE# V places device in byte mode (×8). All data is then input or output on
IL
BYTE#
DQ , and DQ
input buffer.
float. BYTE# V places the device in word mode (×16), and turns off the A
0-7
8-15
IH
-1
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an
internal operation (block erase, full chip erase, word/byte write or lock-bit configuration).
RY/BY#-high Z indicates that the WSM is ready for new commands, block erase is suspended,
and word/byte write is inactive, word/byte write is suspended, or the device is in reset mode.
OPEN
DRAIN
OUTPUT
RY/BY#
BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE OR LOCK-BIT
CONFIGURATION POWER SUPPLY: For erasing array blocks, writing words/bytes or
configuring lock-bits. With V
chip erase, word/byte write and lock-bit configuration with an invalid V
Characteristics) produce spurious results and should not be attempted. Applying 12V±0.3V to
≤V
, memory contents cannot be altered. Block erase, full
CCW
CCWLK
V
SUPPLY
(see 6.2.3 DC
CCW
CCW
V
during erase/write can only be done for a maximum of 1000 cycles on each block. V
CCW
CCW
may be connected to 12V±0.3V for a total of 80 hours maximum.
DEVICE POWER SUPPLY: Do not float any power pins. With V ≤V
, all write attempts to
CC
LKO
V
SUPPLY
the flash memory are inhibited. Device operations at invalid V voltage (see 6.2.3 DC
CC
CC
Characteristics) produce spurious results and should not be attempted.
GND
NC
SUPPLY GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 1.27
LHF32J10
Top Boot
7
[A20-A0]
[A20-A-1]
1FFFFF
1FF000
1FEFFF
1FE000
1FDFFF
3FFFFF
3FE000
3FDFFF
3FC000
3FBFFF
4KW/8KB Boot Block
4KW/8KB Boot Block
0
1
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
1FD000
1FCFFF
1FC000
1FBFFF
1FB000
1FAFFF
1FA000
1F9FFF
3FA000
3F9FFF
3F8000
3F7FFF
3F6000
3F5FFF
3F4000
3F3FFF
[A20-A0]
[A20-A-1]
1F9000
1F8FFF
3F2000
3F1FFF
0FFFFF
1FFFFF
32KW/64KB Main Block 31
32KW/64KB Main Block 32
0F8000
0F7FFF
0F0000
0EFFFF
0E8000
0E7FFF
0E0000
0DFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1F8000
1F7FFF
1F0000
1EFFFF
1E8000
1E7FFF
1E0000
1DFFFF
3F0000
3EFFFF
3E0000
3DFFFF
3D0000
3CFFFF
3C0000
3BFFFF
32KW/64KB Main Block
32KW/64KB Main Block
33
34
32KW/64KB Main Block 35
32KW/64KB Main Block 36
0D8000
0D7FFF
1B0000
1AFFFF
1D8000
1D7FFF
3B0000
3AFFFF
0D0000
0CFFFF
1A0000
19FFFF
1D0000
1CFFFF
1C8000
1C7FFF
1C0000
1BFFFF
1B8000
1B7FFF
1B0000
1AFFFF
1A8000
1A7FFF
3A0000
39FFFF
390000
38FFFF
380000
37FFFF
370000
36FFFF
360000
35FFFF
350000
34FFFF
32KW/64KB Main Block 37
32KW/64KB Main Block 38
32KW/64KB Main Block 39
32KW/64KB Main Block 40
32KW/64KB Main Block 41
32KW/64KB Main Block 42
32KW/64KB Main Block 43
32KW/64KB Main Block 44
32KW/64KB Main Block 45
32KW/64KB Main Block 46
32KW/64KB Main Block 47
32KW/64KB Main Block 48
32KW/64KB Main Block 49
32KW/64KB Main Block 50
32KW/64KB Main Block 51
32KW/64KB Main Block 52
32KW/64KB Main Block 53
32KW/64KB Main Block 54
32KW/64KB Main Block 55
32KW/64KB Main Block 56
32KW/64KB Main Block 57
32KW/64KB Main Block 58
32KW/64KB Main Block 59
32KW/64KB Main Block 60
0C8000
0C7FFF
0C0000
0BFFFF
0B8000
0B7FFF
0B0000
0AFFFF
0A8000
0A7FFF
0A0000
09FFFF
098000
097FFF
090000
08FFFF
088000
087FFF
080000
07FFFF
078000
077FFF
070000
06FFFF
068000
067FFF
060000
05FFFF
058000
057FFF
050000
04FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
32KW/64KB Main Block 10
32KW/64KB Main Block 11
32KW/64KB Main Block 12
32KW/64KB Main Block 13
32KW/64KB Main Block 14
32KW/64KB Main Block 15
32KW/64KB Main Block 16
32KW/64KB Main Block 17
32KW/64KB Main Block 18
32KW/64KB Main Block 19
32KW/64KB Main Block 20
32KW/64KB Main Block 21
32KW/64KB Main Block 22
32KW/64KB Main Block 23
32KW/64KB Main Block 24
32KW/64KB Main Block 25
32KW/64KB Main Block 26
32KW/64KB Main Block 27
32KW/64KB Main Block 28
32KW/64KB Main Block 29
32KW/64KB Main Block 30
1A0000
19FFFF
198000
197FFF
190000
18FFFF
188000
187FFF
180000
17FFFF
178000
177FFF
170000
16FFFF
168000
167FFF
160000
15FFFF
158000
157FFF
150000
14FFFF
148000
147FFF
140000
13FFFF
138000
137FFF
340000
33FFFF
330000
32FFFF
320000
31FFFF
310000
30FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
300000
2FFFFF
2F0000
2EFFFF
2E0000
2DFFFF
2D0000
2CFFFF
0C0000
0BFFFF
2C0000
2BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
2B0000
2AFFFF
2A0000
29FFFF
290000
28FFFF
280000
27FFFF
270000
26FFFF
260000
25FFFF
250000
24FFFF
240000
23FFFF
230000
22FFFF
220000
21FFFF
210000
20FFFF
200000
048000
047FFF
040000
03FFFF
038000
037FFF
030000
02FFFF
028000
027FFF
020000
01FFFF
018000
017FFF
130000
12FFFF
128000
127FFF
120000
11FFFF
118000
117FFF
010000
00FFFF
110000
10FFFF
32KW/64KB Main Block
32KW/64KB Main Block
61
62
008000
007FFF
108000
107FFF
000000
100000
Figure 3. Memory Map
Rev. 1.27
LHF32J10
8
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
2 PRINCIPLES OF OPERATION
The LH28F320BJB-PTTL90 flash memory includes an
on-chip WSM to manage block erase, full chip erase,
word/byte write and lock-bit configuration functions. It
allows for: fixed power supplies during block erase, full
chip erase, word/byte write and lock-bit configuration, and
minimal processor overhead with RAM-like interface
timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
2.1 Data Protection
When V
≤V
, memory contents cannot be
CCW
CCWLK
Status register and identifier codes can be accessed
altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
through the CUI independent of the V
voltage. High
CCW
voltage on V
enables successful block erase, full chip
CCW
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents−block
erase, full chip erase, word/byte write, lock-bit
configuration, status and identifier codes−are accessed via
the CUI and verified through the status register.
even when high voltage is applied to V
. All write
CCW
functions are disabled when V
is below the write
CC
lockout voltage V
or when RP# is at V . The device’s
LKO
IL
block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and word/byte write operations.
Refer to Table 5 for write protection alternatives.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Rev. 1.27
LHF32J10
9
3 BUS OPERATION
3.4 Reset
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
RP# at V initiates the reset mode.
IL
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
3.1 Read
100ns. Time t
is required after return from reset
PHQV
mode until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
Information can be read from any block, identifier codes
or status register independent of the V
can be at V .
voltage. RP#
CCW
IH
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from reset mode, the device automatically
resets to read array mode. Six control pins dictate the data
flow in and out of the component: CE#, OE#, BYTE#,
WE#, RP# and WP#. CE# and OE# must be driven active
to obtain data at the outputs. CE# is the device selection
control, and when active enables the selected memory
device. OE# is the data output (DQ -DQ ) control and
During block erase, full chip erase, word/byte write or
lock-bit configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset operation
is complete. Memory contents being altered are no longer
valid; the data may be partially erased or written. Time
t
is required after RP# goes to logic-high (V )
PHWL
IH
before another command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase, full chip erase, word/byte write or
lock-bit configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization may not
occur because the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal
that resets the system CPU.
0
15
when active drives the selected memory data onto the I/O
bus. BYTE# is the device I/O interface mode control.
WE# must be at V , RP# must be at V , and BYTE#
IH
IH
and WP# must be at V or V . Figure 16, 17 illustrates
IL
IH
read cycle.
3.2 Output Disable
With OE# at a logic-high level (V ), the device outputs
IH
are disabled. Output pins (DQ -DQ ) are placed in a
0
15
high-impedance state.
3.3 Standby
CE# at a logic-high level (V ) places the device in
IH
standby mode which substantially reduces device power
consumption. DQ -DQ outputs are placed in a high-
0
15
impedance state independent of OE#. If deselected during
block erase, full chip erase, word/byte write or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation completes.
Rev. 1.27
LHF32J10
10
3.5 Read Identifier Codes
3.6 OTP(One Time Program) Block
The read identifier codes operation outputs the
manufacturer code, device code, block lock configuration
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes, the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit setting.
The OTP block is a special block that can not be erased.
The block is divided into two parts. One is a factory
program area where a unique number can be written
according to customer requirements in SHARP factory.
This factory program area is "READ ONLY" (Already
locked). The other is a customer program area that can be
used by customers. This customer program area can be
locked. After locking, this customer program area is
protected permanently.
Top Boot
The OTP block is read in Configuration Read Mode by
writing Read Identifier Codes command(90H). To return
to Read Array Mode, write Read Array command(FFH).
[A20-A0]
1FFFFF
[A20-A-1]
3FFFFF
Reserved for Future Implementation
1FF003
1FF002
1FF001
1FF000
1FEFFF
3FE006
3FE005
3FE004
3FE003
3FE000
3FDFFF
The OTP block is programmed by writing OTP Program
command(C0H). First write OTP Program command and
then write data with address to the device (See Figure 5).
If OTP program is failed, SR.4(WORD/BYTE WRITE
AND SET LOCK-BIT STATUS) bit is set to "1". And if
this OTP block is locked, SR.1(DEVICE PROTECT
STATUS) bit is set to "1" too.
Boot Block 0 Lock Configuration Code
Reserved for Future Implementation
Boot Block 0
Reserved for Future Implementation
1FE003
1FE002
1FE001
1FE000
1FDFFF
3FC006
3FC005
Boot Block 1 Lock Configuration Code
Reserved for Future Implementation
3FC004
3FC003
3FC000
3FBFFF
The OTP block is also locked by writing OTP Program
command(C0H). First write OTP Program command and
then write data "FFFDH" with address "80H" to the
device. Address "80H" of OTP block is OTP lock
information. Bit 0 of address "80H" means factory
program area lock status("1" is "NOT LOCKED", "0" is
"LOCKED"). Bit 1 of address "80H" means customer
program area lock status. The OTP lock information can
not be cleared, after once it is set.
Boot Block 1
Reserved for Future Implementation
1FD003
1FD002
1FD001
1FD000
1FCFFF
1F9000
1F8FFF
3FA006
3FA005
3FA004
Parameter Block 0 Lock Configuration Code
3FA003
3FA000
3F9FFF
3F2000
3F1FFF
Reserved for Future Implementation
Parameter Block 0
(Parameter Blocks 1 through 4)
Reserved for Future Implementation
1F8003
1F8002
1F8001
1F8000
3F0006
3F0005
3F0004
3F0003
3F0000
3EFFFF
[A20-A-1]
[A20-A0]
Parameter Block 5 Lock Configuration Code
001FFF
Reserved for Future Implementation
Parameter Block 5
000FFF
1F7FFF
Reserved for Future Implementation
Main Block 0 Lock Configuration Code
Customer Program Area
1F0003
1F0002
1F0001
1F0000
1EFFFF
008000
007FFF
001000
000FFF
000080
3E0006
3E0005
3E0004
3E0003
3E0000
3DFFFF
010000
00FFFF
002000
001FFF
000100
Reserved for Future Implementation
Main Block 0
000085
000084
000081
000080
00010A
000109
000102
000100
(Main Blocks 1 through 61)
Reserved for Future Implementation
OTP Block
Factory Program Area
OTP Lock
Customer Program Area Lock
Factory Program Area Lock
00007F
000004
0000FF
000008
Reserved for Future Implementation
Figure 5. OTP Block Address Map
000007
000003
000002
000001
000000
Permanent Lock Configuration Code
Main Block 62 Lock Configuration Code
Device Code
000006
000005
000004
000003
000002
000001
000000
Manufacturer Code
Main Block 62
Figure 4. Device Identifier Code Memory Map
Rev. 1.27
LHF32J10
11
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 18 and 19 illustrate WE# and CE# controlled write
operations.
3.7 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V =2.7V-3.6V and
CC
V
=V
, the CUI additionally controls block
CCW
CCWH1/2
erase, full chip erase, word/byte write and lock-bit
configuration.
4 COMMAND DEFINITIONS
The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and an address within the device. The Word/Byte Write
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
device (Permanent Lock) or block within the device
(Block Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address within the
device.
When the V
voltage ≤V
, read operations from
CCW
CCWLK
the status register, identifier codes, or blocks are enabled.
Placing V on V enables successful block
CCWH1/2
CCW
erase, full chip erase, word/byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these commands.
(1,2)
Table 2.1. Bus Operations (BYTE#=V )
IH
(3)
Mode
Notes
8
RP#
CE#
OE#
WE#
Address
V
DQ
D
RY/BY#
CCW
X
0-15
Read
V
V
V
V
X
X
X
X
X
X
X
IH
IL
IL
IH
OUT
Output Disable
Standby
V
V
V
V
X
X
X
High Z
IH
IL
IH
IH
V
V
X
X
X
X
High Z
High Z
IH
IH
Reset
4
8
V
X
High Z
High Z
X
IL
See
Figure 4, 5
Read Identifier Codes
Write
V
V
V
V
X
X
Note 5
IH
IL
IL
IH
6,7,8
V
V
V
V
X
D
IH
IL
IH
IL
IN
(1,2)
Table 2.2. Bus Operations (BYTE#=V )
IL
(3)
Mode
Read
Notes
8
RP#
CE#
OE#
WE#
Address
V
DQ
RY/BY#
CCW
X
0-7
V
V
V
V
X
X
X
X
D
X
X
IH
IL
IL
IH
OUT
Output Disable
Standby
V
V
V
V
X
X
X
High Z
High Z
High Z
IH
IL
IH
IH
V
V
X
X
X
X
X
IH
IH
Reset
4
8
V
X
High Z
IL
See
Figure 4, 5
Read Identifier Codes
V
V
V
V
X
X
Note 5
High Z
X
IH
IL
IL
IH
Write
6,7,8
V
V
V
V
X
D
IH
IL
IH
IL
IN
NOTES:
1. Refer to DC Characteristics. When V
≤V
, memory contents can be read, but not altered.
CCW
CCWLK
2. X can be V or V for control pins and addresses, and V
or V
for V
. See DC Characteristics for
IL
IH
CCWLK
CCWH1/2
CCW
V
voltages.
CCWLK
3. RY/BY# is V when the WSM is executing internal block erase, full chip erase, word/byte write or lock-bit configuration
OL
algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive),
word/byte write suspend mode or reset mode.
4. RP# at GND±0.2V ensures the lowest power consumption.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed
when V
=V
and V =2.7V-3.6V.
CCW
CCWH1/2 CC
7. Refer to Table 3 for valid D during a write operation.
IN
8. Never hold OE# low and WE# low at the same timing.
Rev. 1.27
LHF32J10
12
(10)
Table 3. Command Definitions
Bus Cycles
First Bus Cycle
Second Bus Cycle
(1)
(2)
(3)
(1)
(2)
(3)
Command
Read Array/Reset
Req’d.
Notes
4
Oper
Addr
Data
Oper
Addr
Data
1
≥2
2
Write
Write
Write
Write
Write
Write
X
X
X
X
X
X
FFH
90H
70H
50H
20H
30H
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Read
Read
IA
X
ID
SRD
1
2
5
Write
Write
BA
X
D0H
D0H
Full Chip Erase
2
40H or
10H
Word/Byte Write
2
1
1
5,6
5
Write
Write
Write
X
X
X
Write
WA
WD
Block Erase and Word/Byte
Write Suspend
B0H
D0H
Block Erase and Word/Byte
Write Resume
5
Set Block Lock-Bit
Clear Block Lock-Bits
Set Permanent Lock-Bit
OTP Program
2
2
2
2
8
7,8
9
Write
Write
Write
Write
X
X
X
X
60H
60H
60H
C0H
Write
Write
Write
Write
BA
X
01H
D0H
F1H
OD
X
OA
NOTES:
1. BUS operations are defined in Table 2.1 and Table 2.2.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased.
WA=Address of memory location to be written.
OA=Address of OTP block to be written: see Figure 5.
3. ID=Data read from identifier codes.
SRD=Data read from status register. See Table 6 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
OD=Data to be written at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and
permanent lock configuration codes. See Section 4.2 for read identifier code data.
5. If WP# is V , boot blocks are locked without block lock-bits state. If WP# is V , boot blocks are locked by block lock-
IL
IH
bits. The parameter and main blocks are locked by block lock-bits without WP# state.
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
9. Once the permanent lock-bit is set, permanent lock-bit reset is unable.
10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 1.27
LHF32J10
13
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This
operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase, full chip erase, word/byte write or
lock-bit configuration the device will not recognize the
Read Array command until the WSM completes its
operation unless the WSM is suspended via an Erase
Suspend or Word/Byte Write Suspend command. The
Read Array command functions independently of the
The status register may be read to determine when a block
erase, full chip erase, word/byte write or lock-bit
configuration is complete and whether the operation
completed successfully. It may be read at any time by
writing the Read Status Register command. After writing
this command, all subsequent read operations output data
from the status register until another valid command is
written. The status register contents are latched on the
falling edge of OE# or CE#, whichever occurs. OE# or
CE# must toggle to V before further reads to update the
IH
status register latch. The Read Status Register command
V
voltage and RP# can be V .
functions independently of the V
voltage. RP# can be
CCW
IH
CCW
V .
IH
4.2 Read Identifier Codes Command
4.4 Clear Status Register Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer, device, block lock configuration
and permanent lock configuration codes (see Table 4 for
identifier code values). To terminate the operation, write
another valid command. Like the Read Array command,
the Read Identifier Codes command functions
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 6). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
independently of the V
voltage and RP# can be V .
CCW
IH
Following the Read Identifier Codes command, the
following information can be read:
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
Table 4. Identifier Codes
(2)
(3)
the applied V
command is not functional during block erase or
word/byte write suspend modes.
Voltage. RP# can be V . This
Address
Data
CCW IH
Code
[A -A ] [DQ -DQ ]
20
0
7
0
Manufacture Code
Device Code
00000H
B0H
00001H
E2H
(1)
Block Lock Configuration
•Block is Unlocked
BA +2
DQ =0
0
•Block is Locked
DQ =1
0
•Reserved for Future Use
DQ
1-7
Permanent Lock Configuration 00003H
•Device is Unlocked
DQ =0
0
•Device is Locked
DQ =1
0
•Reserved for Future Use
DQ
1-7
NOTE:
1. BA selects the specific block lock configuration code
to be read. See Figure 4 for the device identifier code
memory map.
2. A don’t care in byte mode.
-1
3. DQ -DQ outputs 00H in word mode.
15
8
Rev. 1.27
LHF32J10
14
status register mode until a new command is issued. If
error is detected on a block during full chip erase
operation, WSM stops erasing. Full chip erase operation
start from lower address block, finish the higher address
block. Full chip erase can not be suspended.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH/FFH). Block preconditioning, erase, and verify
are handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status register
data when read (see Figure 6). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Full Chip Erase command sequence
will result in both status register bits SR.4 and SR.5 being
set to "1". Also, reliable full chip erasure can only occur
when V =2.7V-3.6V and V
=V
. In the
CC
CCW
CCWH1/2
absence of this high voltage, block contents are protected
against erasure. If full chip erase is attempted while
V
≤V
, SR.3 and SR.5 will be set to "1".
CCW
CCWLK
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
Successful full chip erase requires for boot blocks that
WP# is V and the corresponding block lock-bit be
IH
cleared. In parameter and main blocks case, it must be
cleared the corresponding block lock-bit. If all blocks are
locked, SR.1 and SR.5 will be set to "1".
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
4.7 Word/Byte Write Command
Word/Byte write is executed by a two-cycle command
sequence. Word/Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 8). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
V
=2.7V-3.6V and V
=V
. In the absence of
CC
CCW
CCWH1/2
this high voltage, block contents are protected against
erasure. If block erase is attempted while V ≤V
,
CCWLK
CCW
SR.3 and SR.5 will be set to "1". Successful block erase
requires for boot blocks that WP# is V and the
IH
corresponding block lock-bit be cleared. In parameter and
main blocks case, it must be cleared the corresponding
block lock-bit. If block erase is attempted when the
excepting above conditions, SR.1 and SR.5 will be set to
"1".
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
4.6 Full Chip Erase Command
This command followed by a confirm command erases all
of the unlocked blocks. A full chip erase setup (30H) is
first written, followed by a full chip erase confirm (D0H).
After a confirm command is written, device erases the all
unlocked blocks block by block. This command sequence
requires appropriate sequencing. Block preconditioning,
erase and verify are handled internally by the WSM
(invisible to the system). After the two-cycle full chip
erase sequence is written, the device automatically outputs
status register data when read (see Figure 7). The CPU can
detect full chip erase completion by analyzing the output
data of the RY/BY# pin or status register bit SR.7.
Reliable word/byte writes can only occur when
V
=2.7V-3.6V and V
=V
. In the absence of
CC
CCW
CCWH1/2
this high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V
≤V
, status register bits SR.3 and SR.4 will be
CCW
CCWLK
set to "1". Successful word/byte write requires for boot
blocks that WP# is V and the corresponding block lock-
IH
bit be cleared. In parameter and main blocks case, it must
be cleared the corresponding block lock-bit. If word/byte
write is attempted when the excepting above conditions,
SR.1 and SR.4 will be set to "1".
When the full chip erase is complete, status register bit
SR.5 should be checked. If erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
Rev. 1.27
LHF32J10
15
4.8 Block Erase Suspend Command
4.9 Word/Byte Write Suspend Command
The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block erase process starts,
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1").
RY/BY# will also transition to High Z. Specification
The Word/Byte Write Suspend command allows
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts, writing the Word/Byte Write Suspend command
requests that the WSM suspend the Word/Byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to "1"). RY/BY# will also transition to
t
defines the block erase suspend latency.
High Z. Specification t
suspend latency.
defines the word/byte write
WHRZ2
WHRZ1
When Block Erase Suspend command write to the CUI, if
block erase was finished, the device places read array
mode. Therefore, after Block Erase Suspend command
write to the CUI, Read Status Register command (70H)
has to write to CUI, then status register bit SR.6 should be
checked for places the device in suspend mode.
When Word/Byte Write Suspend command write to the
CUI, if word/byte write was finished, the device places
read array mode. Therefore, after Word/Byte Write
Suspend command write to the CUI, Read Status Register
command (70H) has to write to CUI, then status register
bit SR.2 should be checked for places the device in
suspend mode.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.9), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended, status register bit SR.7 will return to "0"
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte Write
Resume command is written to the flash memory, the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear and
and the RY/BY# output will transition to V . However,
OL
SR.6 will remain "1" to indicate block erase suspend
status.
RY/BY# will return to V . After the Word/Byte Write
OL
Resume command is written, the device automatically
outputs status register data when read (see Figure 10).
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
V
must remain at V
(the same V
level
CCW
CCWH1/2
CCW
used for word/byte write) while in word/byte write
suspend mode. RP# must also remain at V . WP# must
IH
also remain at V or V (the same WP# level used for
IL
IH
automatically clear and RY/BY# will return to V . After
word/byte write).
OL
the Erase Resume command is written, the device
automatically outputs status register data when read (see
If the time between writing the Word/Byte Write Resume
command and writing the Word/Byte Write Suspend
command is short and both commands are written
repeatedly, a longer time is required than standard
word/byte write until the completion of the operation.
Figure 9). V
must remain at V
(the same
CCW
CCWH1/2
V
level used for block erase) while block erase is
CCW
suspended. RP# must also remain at V . WP# must also
IH
remain at V or V (the same WP# level used for block
IL
IH
erase). Block erase cannot resume until word/byte write
operations initiated during block erase suspend have
completed.
If the time between writing the Block Erase Resume
command and writing the Block Erase Suspend command
is shorter than t
and both commands are written
ERES
repeatedly, a longer time is required than standard block
erase until the completion of the operation.
Rev. 1.27
LHF32J10
16
4.10 Set Block and Permanent Lock-Bit
Commands
4.11 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear
Block Lock-Bits command. With the permanent lock-bit
not set, block lock-bits can be cleared using only the Clear
Block Lock-Bits command. If the permanent lock-bit is
set, block lock-bits cannot cleared. See Table 5 for a
summary of hardware and software write protection
options.
A flexible block locking and unlocking scheme is enabled
via a combination of block lock-bits, a permanent lock-bit
and WP# pin. The block lock-bits and WP# pin gates
program and erase operations while the permanent lock-bit
gates block-lock bit modification. With the permanent
lock-bit not set, individual block lock-bits can be set using
the Set Block Lock-Bit command. The Set Permanent
Lock-Bit command, sets the permanent lock-bit. After the
permanent lock-bit is set, block lock-bits and locked block
contents cannot altered. See Table 5 for a summary of
hardware and software write protection options.
Clear block lock-bits operation is executed by a two-cycle
command sequence. A clear block lock-bits setup is first
written. After the command is written, the device
automatically outputs status register data when read (see
Figure 12). The CPU can detect completion of the clear
block lock-bits event by analyzing the RY/BY# Pin output
or status register bit SR.7.
Set block lock-bit and permanent lock-bit are executed by
a two-cycle command sequence. The set block or
permanent lock-bit setup along with appropriate block or
device address is written followed by either the set block
lock-bit confirm (and an address within the block to be
locked) or the set permanent lock-bit confirm (and any
device address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read (see
Figure 11). The CPU can detect the completion of the set
lock-bit event by analyzing the RY/BY# pin output or
status register bit SR.7.
When the operation is complete, status register bit SR.5
should be checked. If a clear block lock-bit error is
detected, the status register should be cleared. The CUI
will remain in read status register mode until another
command is issued.
This two-step sequence of set-up followed by execution
ensures that block lock-bits are not accidentally cleared.
An invalid Clear Block Lock-Bits command sequence will
result in status register bits SR.4 and SR.5 being set to "1".
Also, a reliable clear block lock-bits operation can only
When the set lock-bit operation is complete, status register
bit SR.4 should be checked. If an error is detected, the
status register should be cleared. The CUI will remain in
read status register mode until a new command is issued.
occur when V =2.7V-3.6V and V
clear block lock-bits operation is attempted while
=V
. If a
CC
CCW
CCWH1/2
V
≤V , SR.3 and SR.5 will be set to "1". In the
CCW
CCWLK
absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block
lock-bits operation requires that the permanent lock-bit is
not set. If it is attempted with the permanent lock-bit set,
SR.1 and SR.5 will be set to "1" and the operation will
fail.
This two-step sequence of set-up followed by execution
ensures that lock-bits are not accidentally set. An invalid
Set Block or Permanent Lock-Bit command will result in
status register bits SR.4 and SR.5 being set to "1". Also,
reliable operations occur only when V =2.7V-3.6V and
CC
V
=V
. In the absence of this high voltage,
CCW
CCWH1/2
If a clear block lock-bits operation is aborted due to V
lock-bit contents are protected against alteration.
CCW
or V
transitioning out of valid range or RP# active
CC
transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
values. Once the permanent lock-bit is set, it cannot be
cleared.
A successful set block lock-bit operation requires that the
permanent lock-bit be cleared. If it is attempted with the
permanent lock-bit set, SR.1 and SR.4 will be set to "1"
and the operation will fail.
Rev. 1.27
LHF32J10
17
programs. If OTP program is attempted while
≤V , status register bits SR.3 and SR.4 is set
4.12 OTP Program Command
V
CCW
CCWLK
OTP program is executed by a two-cycle command
sequence. OTP program command(C0H) is written,
followed by a second write cycle that specifies the address
and data (latched on the rising edge of WE#). The WSM
then takes over, controlling the OTP program and program
verify algorithms internally. After the OTP program
command sequence is completed, the device automatically
outputs status register data when read (see Figure 13). The
CPU can detect the completion of the OTP program by
analyzing the output data of the RY/BY# pin or status
register bit SR.7.
to "1". If OTP write is attempted when the OTP Lock-bit
is set, SR.1 and SR.4 is set to "1".
4.13 Block Locking by the WP#
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
The lockable two boot blocks are locked when WP#=V ;
IL
any program or erase operation to a locked block will
result in an error, which will be reflected in the status
register. For top configuration, the top two boot blocks are
lockable. For the bottom configuration, the bottom two
When OTP program is completed, status register bit SR.4
should be checked. If OTP program error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully
program to "0"s. The CUI remains in read status register
mode until it receives other commands.
boot blocks are lockable. If WP# is V and block lock-
IH
bit is not set, boot block can be programmed or erased
normally (Unless V
only two boot blocks, other blocks are not affected.
is below V
). WP# is valid
CCW
CCWLK
Reliable OTP program can be executed only when
V
=2.7V-3.6V and V
=V
. In the absence of
CC
CCW
CCWH1/2
this voltage, memory contents are protected against OTP
Table 5. Write Protection Alternatives
Permanent Block
Lock-Bit Lock-bit
Operation
V
RP#
X
WP#
Effect
CCW
Block Erase ≤V
X
X
X
X
X
0
X
X
All Blocks Locked.
CCWLK
CCWLK
or
>V
V
All Blocks Locked.
IL
Word/Byte
Write
V
V
2 Boot Blocks Locked.
IH
IL
V
Block Erase and Word/Byte Write Enabled.
Block Erase and Word/Byte Write Disabled.
Block Erase and Word/Byte Write Disabled.
All Blocks Locked.
IH
1
V
IL
V
IH
Full Chip ≤V
X
X
X
X
X
X
X
X
X
CCWLK
Erase
>V
V
All Blocks Locked.
CCWLK
IL
V
V
All Unlocked Blocks are Erased.
2 Boot Blocks and Locked Blocks are NOT Erased.
IH
IL
V
All Unlocked Blocks are Erased,
Locked Blocks are NOT Erased.
IH
Set Block ≤V
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Set Block Lock-Bit Disabled.
Set Block Lock-Bit Disabled.
Set Block Lock-Bit Enabled.
CCWLK
Lock-Bit
>V
V
CCWLK
IL
V
IH
1
Set Block Lock-Bit Disabled.
Clear Block Lock-Bits Disabled.
Clear Block Lock-Bits Disabled.
Clear Block Lock-Bits Enabled.
Clear Block Lock-Bits Disabled.
Set Permanent Lock-Bit Disabled.
Set Permanent Lock-Bit Disabled.
Set Permanent Lock-Bit Enabled.
Clear Block ≤V
X
X
X
0
CCWLK
Lock-Bits >V
V
CCWLK
IL
V
IH
1
Set
≤V
X
X
X
X
CCWLK
Permanent >V
Lock-Bit
V
CCWLK
IL
V
IH
Rev. 1.27
LHF32J10
18
Table 6. Status Register Definition
WSMS
7
BESS
6
ECBLBS
5
WBWSLBS
VCCWS
WBWSS
2
DPS
1
R
0
4
3
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
Check RY/BY# or SR.7 to determine block erase, full chip
1 = Ready
0 = Busy
erase, word/byte write or lock-bit configuration completion.
SR.6-0 are invalid while SR.7="0".
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS (ECBLBS)
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase or lock-bit configuration attempt, an improper
1 = Error in Block Erase, Full Chip Erase or Clear Block command sequence was entered.
Lock-Bits
0 = Successful Block Erase, Full Chip Erase or Clear
Block Lock-Bits
SR.4 = WORD/BYTE WRITE AND SET LOCK-BIT
STATUS (WBWSLBS)
1 = Error in Word/Byte Write or Set Block/Permanent
Lock-Bit
SR.3 does not provide a continuous indication of V
CCW
level. The WSM interrogates and indicates the V
level
CCW
only after Block Erase, Full Chip Erase, Word/Byte Write or
0 = Successful Word/Byte Write or Set Block/Permanent Lock-Bit Configuration command sequences. SR.3 is not
Lock-Bit guaranteed to reports accurate feedback only when
≠V
V
.
CCWH1/2
CCW
SR.3 = V
STATUS (VCCWS)
Low Detect, Operation Abort
OK
CCW
CCW
CCW
1 = V
0 = V
SR.1 does not provide a continuous indication of permanent
and block lock-bit and WP# values. The WSM interrogates
the permanent lock-bit, block lock-bit and WP# only after
Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit
Configuration command sequences. It informs the system,
depending on the attempted operation, if the block lock-bit is
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
set, permanent lock-bit is set and/or WP# is V . Reading
IL
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Lock-Bit, Permanent Lock-Bit and/or WP#
Lock Detected, Operation Abort
the block lock and permanent lock configuration codes after
writing the Read Identifier Codes command indicates
permanent and block lock-bit status.
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.0 is reserved for future use and should be masked out
when polling the status register.
Rev. 1.27
LHF32J10
19
Start
Bus
Operation
Comments
Command
Data=70H
Addr=X
Read Status
Register
Write
Read
Write 70H
Status Register Data
Read Status
Register
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=20H
Addr=X
Write
Write
Erase Setup
Data=D0H
Erase
Confirm
Write 20H
Addr=Within Block to be Erased
Write D0H,
Block Address
Status Register Data
Read
Read Status
Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
Suspend Block
Erase Loop
No
0
Repeat for subsequent block erasures.
Suspend
Block Erase
SR.7=
1
Yes
Full status check can be done after each block erase or after a sequence of
block erasures.
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Comments
Command
Check SR.3
1=V Error Detect
Standby
1
CCW
V
Range Error
SR.3=
CCW
Check SR.1
Standby
Standby
Standby
0
1=Device Protect Detect
Check SR.4,5
1
Device Protect Error
Both 1=Command Sequence Error
SR.1=
Check SR.5
0
1=Block Erase Error
1
Command Sequence
Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases
where multiple blocks are erased before full status is checked.
SR.4,5=
If error is detected, clear the Status Register before attempting retry or other error recovery.
0
1
SR.5=
Block Erase Error
0
Block Erase Successful
Figure 6. Automated Block Erase Flowchart
Rev. 1.27
LHF32J10
20
Start
Bus
Comments
Command
Operation
Data=70H
Addr=X
Read Status
Register
Write 70H
Write
Read
Read Status
Register
Status Register Data
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=30H
Addr=X
Full Chip Erase
Setup
Write
Write
Read
Write 30H
Write D0H
Data=D0H
Addr=X
Full Chip Erase
Confirm
Status Register Data
Check SR.7
Read Status
Register
Standby
1=WSM Ready
0=WSM Busy
Full status check can be done after each full chip erase.
0
SR.7=
1
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Full Chip Erase
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Comments
Command
Check SR.3
1=V Error Detect
Standby
1
CCW
V
Range Error
SR.3=
CCW
Check SR.1
0
Standby
1=Device Protect Detect
(All Blocks are locked)
1
Check SR.4,5
Device Protect Error
SR.1=
Standby
Standby
Both 1=Command Sequence Error
0
Check SR.5
1=Full Chip Erase Error
1
Command Sequence
Error
SR.4,5=
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register Command in cases
where multiple blocks are erased before full status is checked.
0
If error is detected, clear the Status Register before attempting retry or other error recovery.
1
SR.5=
Full Chip Erase Error
0
Full Chip Erase
Successful
Figure 7. Automated Full Chip Erase Flowchart
Rev. 1.27
LHF32J10
21
Bus
Operation
Start
Command
Comments
Data=70H
Addr=X
Read Status
Register
Write
Read
Write 70H
Status Register Data
Read Status
Register
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=40H or 10H
Addr=X
Write
Write
Setup Word/Byte Write
Word/Byte Write
Data=Data to Be Written
Write 40H or 10H
Addr=Location to Be Written
Write Word/Byte
Data and Address
Read
Status Register Data
Read
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
Suspend Word/Byte
Write Loop
No
Suspend
Word/Byte
Write
0
Repeat for subsequent word/byte writes.
SR.7=
1
Yes
SR full status check can be done after each word/byte write, or after a sequence of
word/byte writes.
Write FFH after the last word/byte write operation to place device in read array mode.
Full Status
Check if Desired
Word/Byte Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Comments
Command
Check SR.3
1=V Error Detect
Standby
1
CCW
SR.3=
V
Range Error
CCW
Check SR.1
Standby
Standby
0
1=Device Protect Detect
Check SR.4
1
SR.1=
Device Protect Error
1=Data Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases
where multiple locations are written before full status is checked.
0
If error is detected, clear the Status Register before attempting retry or other error recovery.
1
Word/Byte Write Error
SR.4=
0
Word/Byte Write Successful
Figure 8. Automated Word/Byte Write Flowchart
Rev. 1.27
LHF32J10
22
Start
Bus
Operation
Command
Comments
Data=B0H
Addr=X
Erase
Suspend
Write
Read
Write B0H
Status Register Data
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
0
Check SR.6
SR.7=
1
Standby
Write
1=Block Erase Suspended
0=Block Erase Completed
Data=D0H
Addr=X
Erase
Resume
0
SR.6=
1
Block Erase Completed
Read or
Word/Byte
Write ?
Word/Byte Write
Read
Word/Byte Write Loop
Read Array Data
No
Done?
Yes
Write D0H
Write FFH
Block Erase Resumed
Read Array Data
Figure 9. Block Erase Suspend/Resume Flowchart
Rev. 1.27
LHF32J10
23
Start
Bus
Operation
Command
Comments
Data=B0H
Addr=X
Word/Byte Write
Suspend
Write
Read
Write B0H
Status Register Data
Addr=X
Read
Status Register
Check SR.7
Standby
Standby
1=WSM Ready
0=WSM Busy
0
0
Check SR.2
SR.7=
1
1=Word/Byte Write Suspended
0=Word/Byte Write Completed
Data=FFH
Addr=X
Read Array
Write
Read
Write
Word/Byte Write Completed
SR.2=
1
Read Array locations other
than that being written.
Data=D0H
Addr=X
Word/Byte Write
Resume
Write FFH
Read Array Data
Done
No
Reading
Yes
Write D0H
Write FFH
Word/Byte Write Resumed
Read Array Data
Figure 10. Word/Byte Write Suspend/Resume Flowchart
Rev. 1.27
LHF32J10
24
Start
Bus
Operation
Command
Comments
Data=70H
Addr=X
Read Status
Register
Write
Read
Write 70H
Status Register Data
Read Status
Register
Check SR.7
Standby
Write
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Set
Data=60H
Addr=X
Block/Permanent
Lock-Bit Setup
Write 60H
Data=01H(Block),
Set
F1H(Permanent)
Write
Block or Permanent
Lock-Bit Confirm
Addr=Block Address(Block),
Device Address(Permanent)
Write 01H/F1H,
Block/Device Address
Read
Status Register
Status Register Data
Read
Check SR.7
Standby
0
1=WSM Ready
0=WSM Busy
SR.7=
1
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation or after a sequence of
lock-bit set operations.
Full Status
Check if Desired
Write FFH after the last lock-bit set operation to place device in read array mode.
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Command
Comments
Check SR.3
1=V Error Detect
Standby
1
CCW
SR.3=
V
Range Error
CCW
Check SR.1
0
1=Device Protect Detect
Standby
Permanent Lock-Bit is Set
(Set Block Lock-Bit Operation)
1
Device Protect Error
SR.1=
Check SR.4,5
Standby
Standby
0
Both 1=Command Sequence Error
Check SR.4
1
Command Sequence
Error
SR.4,5=
1=Set Lock-Bit Error
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases
where multiple lock-bits are set before full status is checked.
If error is detected, clear the Status Register before attempting retry or other error recovery.
1
SR.4=
Set Lock-Bit Error
0
Set Lock-Bit Successful
Figure 11. Set Block and Permanent Lock-Bit Flowchart
Rev. 1.27
LHF32J10
25
Start
Bus
Operation
Command
Comments
Data=70H
Addr=X
Read Status
Register
Write
Read
Write 70H
Status Register Data
Read Status
Register
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=60H
Addr=X
Clear Block
Lock-Bits Setup
Write
Write
Data=D0H
Addr=X
Write 60H
Write D0H
Clear Block
Lock-Bits Confirm
Status Register Data
Read
Read
Status Register
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
Write FFH after the Clear Block Lock-Bits operation to place device in read array mode.
SR.7=
1
Full Status
Check if Desired
Clear Block Lock-Bits
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Comments
Command
Check SR.3
1=V Error Detect
Standby
1
CCW
V
Range Error
SR.3=
CCW
Check SR.1
0
Standby
1=Device Protect Detect
Permanent Lock-Bit is Set
1
SR.1=
Device Protect Error
Check SR.4,5
Standby
Standby
Both 1=Command Sequence Error
0
Check SR.5
1
Command Sequence
Error
1=Clear Block Lock-Bits Error
SR.4,5=
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command.
If error is detected, clear the Status Register before attempting retry or other error recovery.
0
1
Clear Block Lock-Bits
Error
SR.5=
0
Clear Block Lock-Bits
Successful
Figure 12. Clear Block Lock-Bits Flowchart
Rev. 1.27
LHF32J10
26
Bus
Operation
Start
Command
Comments
Data=70H
Addr=X
Read Status
Register
Write
Read
Write 70H
Status Register Data
Read Status
Register
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
0
SR.7=
1
Data=C0H
Addr=X
Write
Write
Setup OTP Program
OTP Program
Data=Data to Be Written
Write C0H
Addr=Location to Be Written
Write Data and Address
Read
Status Register Data
Read
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
Standby
0
Repeat for subsequent OTP programs.
SR.7=
1
SR full status check can be done after each OTP program, or after a sequence of
OTP programs.
Write FFH after the last OTP program operation to place device in read array mode.
Full Status
Check if Desired
OTP Program
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Comments
Command
Check SR.3
1=V Error Detect
Standby
1
CCW
SR.3=
V
Range Error
CCW
Check SR.1
Standby
Standby
0
1=Device Protect Detect
Check SR.4
1
SR.1=
Device Protect Error
OTP Program Error
1=Data Write Error
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases
where multiple locations are written before full status is checked.
0
If error is detected, clear the Status Register before attempting retry or other error recovery.
1
SR.4=
0
OTP Program Successful
Figure 13. Automated OTP Program Flowchart
Rev. 1.27
LHF32J10
27
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
connected between its V
and GND and between its
CC
V
and GND. These high-frequency, low inductance
CCW
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
supply connection between V
and GND. The bulk
CC
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.4 V
Trace on Printed Circuit Boards
CCW
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
5.2 RY/BY# and WSM Polling
attention to the V
Power supply trace. The V
pin
CCW
CCW
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
RY/BY# is an open drain output that should be connected
to V by a pull up resistor to provides a hardware method
CC
considerations given to the V
power bus. Adequate
of detecting block erase, full chip erase, word/byte write
and lock-bit configuration completion. It transitions low
after block erase, full chip erase, word/byte write or lock-
CC
V
supply traces and decoupling will decrease V
CCW
CCW
voltage spikes and overshoots.
bit configuration commands and returns to V
(while
OH
RY/BY# is pull up) when the WSM has finished executing
the internal algorithm.
5.5 V , V
, RP# Transitions
CC CCW
Block erase, full chip erase, word/byte write and lock-bit
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or reset modes.
configuration are not guaranteed if V falls outside of a
CCW
valid V
range, V falls outside of a valid 2.7V-
CCWH1/2
CC
3.6V range, or RP#≠V . If V
error is detected, status
IH
CCW
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP# transitions
to V during block erase, full chip erase, word/byte write
IL
or lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation will
abort and the device will enter reset mode. The aborted
operation may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP# transitions
to V clear the status register.
IL
The CUI latches commands issued by system software and
is not altered by V
or CE# transitions or WSM
CCW
actions. Its state is read array mode upon power-up, after
exit from reset mode or after V transitions below V
.
LKO
CC
Rev. 1.27
LHF32J10
28
5.6 Power-Up/Down Protection
5.8 Data Protection Method
The device is designed to offer protection against
accidental block erase, full chip erase, word/byte write or
lock-bit configuration during power transitions. Upon
power-up, the device is indifferent as to which power
Noises having a level exceeding the limit specified in the
specification may be generated under specific operating
conditions on some systems. Such noises, when induced
onto WE# signal or power supply, may be interpreted as
false commands, causing undesired memory updating. To
protect the data stored in the flash memory against
unwanted overwriting, systems operating with the flash
memory should have the following write protect designs,
as appropriate:
supply (V
or V ) powers-up first. Internal circuitry
CCW
CC
resets the CUI to read array mode at power-up.
A system designer must guard against spurious writes for
V
voltages above V
when V
is active. Since
CC
LKO
CCW
both WE# and CE# must be low for a command write,
driving either to V will inhibit writes. The CUI’s two-
1) Protecting data in specific block
IH
step command sequence architecture provides added level
of protection against data alteration.
When a lock bit is set, the corresponding block (includes
the 2 boot blocks) is protected against overwriting. By
setting a WP# to low, only the 2 boot blocks can be
protected against overwriting. By using this feature, the
flash memory space can be divided into the program
section (locked section) and data section (unlocked
section). The permanent lock bit can be used to prevent
false block bit setting. For further information on
setting/resetting lock-bit, refer to the specification. (See
chapter 4.10 and 4.11.)
In-system block lock and unlock capability prevents
inadvertent data alteration. The device is disabled while
RP#=V regardless of its control inputs state.
IL
5.7 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
2) Data protection through V
CCW
When the level of V
is lower than V
(lockout
CCW
CCWLK
voltage), write operation on the flash memory is disabled.
All blocks are locked and the data in the blocks are
completely write protected. For the lockout voltage, refer
to the specification. (See chapter 6.2.3.)
3) Data protection through RP#
When the RP# is kept low during read mode, the flash
memory will be reset mode, then write protecting all
blocks. When the RP# is kept low during power up and
power down sequence such as voltage transition, write
operation on the flash memory is disabled, write
protecting all blocks. For the details of RP# control, refer
to the specification. (See chapter 5.6 and 6.2.7.)
Rev. 1.27
LHF32J10
29
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase,
Full Chip Erase, Word/Byte Write
and Lock-Bit Configuration................0°C to +70°C
NOTES:
(1)
1. Operating temperature is for commercial temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
Storage Temperature
During under Bias............................... -10°C to +80°C
During non Bias ................................ -65°C to +125°C
and -0.2V on V and V
pins. During transitions,
CC
CCW
this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins are
Voltage On Any Pin
(2)
(except V and V
) ........... -0.5V to V +0.5V
CC
CC
CCW
V
V
+0.5V which, during transitions, may overshoot to
+2.0V for periods <20ns.
CC
CC
(2)
V
V
Supply Voltage................................ -0.2V to +4.6V
CC
3. Maximum DC voltage on V
may overshoot to
CCW
+13.0V for periods <20ns. Applying 12V±0.3V to
during erase/write can only be done for a
(2,3)
Supply Voltage.........................-0.2V to +13.0V
CCW
V
CCW
maximum of 1000 cycles on each block. V
may be
(4)
CCW
Output Short Circuit Current................................100mA
connected to 12V±0.3V for a total of 80 hours
maximum.
4. Output shorted for no more than one second. No more
than one output shorted at a time.
6.2 Operating Conditions
Temperature and V Operating Conditions
CC
Symbol
Parameter
Min.
Max.
+70
3.6
Unit
°C
Test Condition
T
Operating Temperature
0
Ambient Temperature
A
V
V
Supply Voltage (2.7V-3.6V)
2.7
V
CC
CC
(1)
6.2.1 CAPACITANCE
T =+25°C, f=1MHz
A
Symbol
Parameter
Typ.
Max.
Unit
Condition
C
C
Input Capacitance
Output Capacitance
7
9
10
12
pF
pF
V =0.0V
IN
IN
V
=0.0V
OUT
OUT
NOTE:
1. Sampled, not 100% tested.
Rev. 1.27
LHF32J10
30
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
1.35
1.35
INPUT
TEST POINTS
OUTPUT
0.0
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for V =2.7V-3.6V
CC
Test Configuration Capacitance Loading Value
Test Configuration
=2.7V-3.6V
C (pF)
L
1.3V
V
50
CC
1N914
RL=3.3kΩ
DEVICE
UNDER
TEST
OUT
CL Includes Jig
Capacitance
CL
Figure 15. Transient Equivalent Testing Load Circuit
Rev. 1.27
LHF32J10
31
6.2.3 DC CHARACTERISTICS
DC Characteristics
V
=2.7V-3.6V
Test
CC
Sym.
Parameter
Input Load Current
Notes
1
Typ.
Max.
Unit
µA
Conditions
I
I
I
I
I
I
I
V
=V Max.
LI
CC CC
±0.5
V =V or GND
IN
CC
Output Leakage Current
1
1,3
1,5
1
V
V
=V Max.
LO
CC
CC
±0.5
20
µA
µA
µA
µA
mA
=V or GND
OUT
CC
V
V
V
V
V
Standby Current
V
=V Max.
CCS
CCAS
CCD
CCR
CCW
CC
CC
CC
CC
CC
CC CC
4
4
CE#=RP#=V ±0.2V
CC
Auto Power-Save Current
Reset Power-Down Current
Read Current
V
=V Max.
CC CC
20
CE#=GND±0.2V
RP#=GND±0.2V
4
20
I
(RY/BY#)=0mA
OUT
1
V
=V Max., CE#=GND
CC CC
15
30
f=5MHz, I
=0mA
OUT
Word/Byte Write or Set Lock-
1,6
5
5
4
4
17
12
17
12
mA
mA
mA
mA
V
V
V
V
=2.7V-3.6V
CCW
CCW
CCW
CCW
Bit Current
Block Erase, Full Chip Erase or
=11.7V-12.3V
=2.7V-3.6V
I
V
1,6
CCE
CC
Clear Block Lock-Bits Current
=11.7V-12.3V
I
I
V
Word/Byte Write or
1,2
1
CCWS
CCES
CC
1
6
mA
CE#=V
IH
Block Erase Suspend Current
I
V
Standby or Read Current
±2
10
±15
200
µA
µA
V
V
V
≤V
CCWS
CCW
CCW
CCW
CC
I
I
>V
CCWR
CCW
CC
V
Auto Power-Save Current
1,5
=V Max.
CCWAS
CC
CC
0.1
5
µA
CE#=GND±0.2V
I
I
V
V
Reset Power-Down Current
1
0.1
12
5
µA
mA
mA
mA
mA
RP#=GND±0.2V
CCWD
CCWW
CCW
Word/Byte Write or Set Lock-
1,6
40
30
25
20
V
V
V
V
=2.7V-3.6V
CCW
CCW
CCW
CCW
CCW
Bit Current
Block Erase, Full Chip Erase
=11.7V-12.3V
=2.7V-3.6V
I
V
1,6
1
8
CCWE
CCW
or Clear Block Lock-Bits Current
V Word/Byte Write or
CCW
Block Erase Suspend Current
=11.7V-12.3V
I
I
CCWWS
CCWES
10
200
µA
V
=V
CCW
CCWH1/2
Rev. 1.27
LHF32J10
32
DC Characteristics (Continued)
V
=2.7V-3.6V
Max.
CC
Sym.
Parameter
Input Low Voltage
Notes
Min.
-0.5
Unit
V
Test Conditions
V
V
6
6
0.4
IL
Input High Voltage
Output Low Voltage
Output High Voltage
V
-0.4
V
+0.5
IH
CC
CC
V
V
V
V
V
V
V
V
3,6
6
V
I
=V Min.
OL
CC
CC
0.4
=2.0mA
OL
V
-0.4
V
I
=V Min.
OH
CC
CC
CC
=-100µA
OH
V
Lockout during Normal
4,6
CCWLK
CCWH1
CCW
1.0
3.6
Operations
V
during Block Erase, Full Chip
CCW
Erase, Word/Byte Write or Lock-Bit
Configuration Operations
2.7
V
V
V
V
during Block Erase, Full Chip
7
CCWH2
LKO
CCW
Erase, Word/Byte Write or Lock-Bit
Configuration Operations
11.7
2.0
12.3
V
V
V
Lockout Voltage
CC
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal V voltage and T =+25°C.
CC
A
2. I
and I
are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the
CCWS
CCES
device’s current draw is the sum of I
3. Includes RY/BY#.
or I
and I
or I
, respectively.
CCWS
CCES
CCR
CCW
4. Block erases, full chip erase, word/byte writes and lock-bit configurations are inhibited when V
≤V
, and not
CCW
CCWLK
guaranteed in the range between V
(max.) and V
(min.), between V
(max.) and V
(min.) and
CCWLK
CCWH1
CCWH1
CCWH2
above V
(max.).
CCWH2
5. The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more
than 300ns while read mode.
6. Sampled, not 100% tested.
7. Applying 12V±0.3V to V
during erase/write can only be done for a maximum of 1000 cycles on each block. V
CCW
CCW
may be connected to 12V±0.3V for a total of 80 hours maximum.
Rev. 1.27
LHF32J10
33
(1)
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS
V
=2.7V-3.6V, T =0°C to +70°C
A
CC
Sym.
Parameter
Notes
2
Min.
90
Max.
Unit
ns
t
t
t
t
t
t
t
t
t
Read Cycle Time
AVAV
AVQV
ELQV
PHQV
GLQV
ELQX
EHQZ
GLQX
GHQZ
Address to Output Delay
CE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
CE# to Output in Low Z
90
90
ns
ns
600
40
ns
2
3
3
3
3
ns
0
0
ns
CE# High to Output in High Z
OE# to Output in Low Z
40
15
ns
ns
OE# High to Output in High Z
ns
Output Hold from Address, CE# or OE# Change, Whichever
Occurs First
t
3
0
ns
OH
t
t
t
BYTE# to Output Delay
3
3
90
25
5
ns
ns
ns
FVQV
FLQZ
ELFV
BYTE# Low to Output in High Z
CE# to BYTE# High or Low
3,4
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t
3. Sampled, not 100% tested.
-t
after the falling edge of CE# without impact on t
.
ELQV
ELQV GLQV
4. If BYTE# transfer during reading cycle, exist the regulations separately.
Rev. 1.27
LHF32J10
34
Device
Address Selection
Standby
Data Valid
VIH
ADDRESSES(A)
VIL
Address Stable
tAVAV
VIH
CE#(E)
VIL
tEHQZ
VIH
OE#(G)
VIL
tGHQZ
VIH
WE#(W)
VIL
tGLQV
tELQV
tGLQX
tELQX
tOH
VOH
DATA(D/Q)
HIGH Z
HIGH Z
Valid Output
(DQ -DQ
)
0
15
VOL
tAVQV
V
CC
tPHQV
VIH
RP#(P)
VIL
Figure 16. AC Waveform for Read Operations
Rev. 1.27
LHF32J10
35
Device
Address Selection
Standby
Data Valid
VIH
ADDRESSES(A)
Address Stable
VIL
tAVAV
VIH
CE#(E)
VIL
tELQV
tEHQZ
tAVQV
VIH
OE#(G)
VIL
tGLQV
tGHQZ
tFVQV
VIH
BYTE#(F)
VIL
tOH
tGLQX
tELFV
VOH
DATA(D/Q)
(DQ -DQ )
HIGH Z
HIGH Z
HIGH Z
Valid
Output
Data Output
0
7
tELQX
VOL
tFLQZ
VOH
DATA(D/Q)
(DQ -DQ
HIGH Z
Data
Output
)
15
8
VOL
Figure 17. BYTE# timing Waveform
Rev. 1.27
LHF32J10
36
(1)
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
V
=2.7V-3.6V, T =0°C to +70°C
A
CC
Sym.
Parameter
Notes
Min.
90
1
Max.
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
AVAV
PHWL
ELWL
WLWH
SHWH
VPWH
AVWH
DVWH
WHDX
WHAX
WHEH
WHWL
WHRL
WHGL
QVVL
QVSL
RP# High Recovery to WE# Going Low
CE# Setup to WE# Going Low
WE# Pulse Width
2
10
50
100
100
50
50
0
WP#V Setup to WE# Going High
2
2
3
3
IH
V
Setup to WE# Going High
CCW
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
0
10
30
WE# Pulse Width High
WE# High to RY/BY# Going Low or SR.7 Going "0"
Write Recovery before Read
100
0
0
V
Hold from Valid SRD, RY/BY# High Z
2,4
2,4
5
CCW
WP# V Hold from Valid SRD, RY/BY# High Z
0
IH
BYTE# Setup to WE# Going High
BYTE# Hold from WE# High
50
90
FVWH
WHFV
5
NOTES:
1. Read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are
the same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A and D for block erase, full chip erase, word/byte write or lock-bit configuration.
IN
IN
4. V
should be held at V
until determination of block erase, full chip erase, word/byte write or lock-bit
CCW
CCWH1/2
configuration success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.27
LHF32J10
37
1
2
3
4
5
6
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
AIN
AIN
ADDRESSES(A)
CE#(E)
tWHAX
tAVAV
tAVWH
tELWL
tWHEH
tWHGL
OE#(G)
tWHQV1,2,3,4
tWHWL
WE#(W)
tWLWH
tDVWH
tWHDX
High Z
Valid
SRD
DIN
DIN
DIN
DATA(D/Q)
BYTE#(F)
tPHWL
tFVWH
tWHFV
tWHRL
High Z
("1")
RY/BY#(R)
(SR.7)
VOL
("0")
tQVSL
tSHWH
VIH
VIL
VIH
VIL
WP#(S)
RP#(P)
tVPWH
tQVVL
VCCWH1/2
VCCWLK
VIL
V
CCW
(V)
NOTES:
1. VCC power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 18. AC Waveform for WE#-Controlled Write Operations
Rev. 1.27
LHF32J10
38
(1)
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES
V
=2.7V-3.6V, T =0°C to +70°C
A
CC
Sym.
Parameter
Notes
Min.
90
1
Max.
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
AVAV
PHEL
WLEL
ELEH
SHEH
VPEH
AVEH
DVEH
EHDX
EHAX
EHWH
EHEL
EHRL
EHGL
QVVL
QVSL
FVEH
EHFV
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
2
0
65
100
100
50
50
0
WP#V Setup to CE# Going High
2
2
3
3
IH
V
Setup to CE# Going High
CCW
Address Setup to CE# Going High
Data Setup to CE# Going High
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
0
0
25
CE# High to RY/BY# Going Low or SR.7 Going "0"
Write Recovery before Read
100
0
0
V
Hold from Valid SRD, RY/BY# High Z
2,4
2,4
5
CCW
WP# V Hold from Valid SRD, RY/BY# High Z
0
IH
BYTE# Setup to CE# Going High
BYTE# Hold from CE# High
50
90
5
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A and D for block erase, full chip erase, word/byte write or lock-bit configuration.
IN
IN
4. V
should be held at V
until determination of block erase, full chip erase, word/byte write or lock-bit
CCW
CCWH1/2
configuration success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.27
LHF32J10
39
1
2
3
4
5
6
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
AIN
AIN
ADDRESSES(A)
CE#(E)
tEHAX
tAVEH
tAVAV
tEHEL
tELEH
tDVEH
tEHGL
OE#(G)
WE#(W)
tEHQV1,2,3,4
tEHWH
tEHDX
tWLEL
High Z
Valid
SRD
DIN
DIN
DIN
DATA(D/Q)
BYTE#(F)
tPHEL
tFVEH
tEHFV
tEHRL
High Z
("1")
RY/BY#(R)
(SR.7)
VOL
("0")
tQVSL
tSHEH
VIH
VIL
VIH
VIL
WP#(S)
RP#(P)
tVPEH
tQVVL
VCCWH1/2
VCCWLK
VIL
V
CCW
(V)
NOTES:
1. VCC power-up and standby.
2. Write each setup command.
3. Write each confirm command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 19. AC Waveform for CE#-Controlled Write Operations
Rev. 1.27
LHF32J10
40
6.2.7 RESET OPERATIONS
High Z
("1")
VOL
("0")
RY/BY#(R)
(SR.7)
VIH
VIL
RP#(P)
tPLPH
(A)Reset During Read Array Mode
High Z
("1")
VOL
("0")
RY/BY#(R)
(SR.7)
tPLRZ
VIH
VIL
RP#(P)
tPLPH
(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration
2.7V
VIL
VCC
t2VPH
VIH
VIL
RP#(P)
(C)RP# rising Timing
Figure 20. AC Waveform for Reset Operation
Reset AC Specifications
Sym.
Parameter
Notes
2
Min.
100
Max.
30
Unit
ns
t
t
t
RP# Pulse Low Time
PLPH
RP# Low to Reset during Block Erase, Full Chip Erase,
Word/Byte Write or Lock-Bit Configuration
1,2
2,3
µs
ns
PLRZ
V
2.7V to RP# High
100
2VPH
CC
NOTES:
1. If RP# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing,
the reset will complete within 100ns.
2. A reset time, t
, is required from the later of RY/BY#(SR.7) going High Z("1") or RP# going high until outputs are
PHQV
valid. Refer to AC Characteristics - Read-Only Operations for t
3. When the device power-up, holding RP# low minimum 100ns is required after V has been in predefined range and also
.
PHQV
CC
has been in stable there.
Rev. 1.27
LHF32J10
41
6.2.8 BLOCK ERASE, FULL CHIP ERASE, WORD/BYTE WRITE AND LOCK-BIT
(3)
CONFIGURATION PERFORMANCE
V
=2.7V-3.6V, T =0°C to +70°C
A
CC
V
=2.7V-3.6V
V
=11.7V-12.3V
CCW
CCW
(1)
(1)
Sym.
Parameter
Word Write Time
Notes Min. Typ.
Max.
200
200
200
200
4
Min. Typ.
Max. Unit
t
t
32K word Block
4K word Block
64K byte Block
8K byte Block
32K word Block
4K word Block
64K byte Block
8K byte Block
2
2
2
2
2
2
2
2
33
36
31
32
20
27
µs
µs
µs
µs
s
WHQV1
EHQV1
Byte Write Time
19
26
Block Write Time
(In word mode)
Block Write Time
(In byte mode)
1.1
0.15
2.2
0.66
0.12
1.4
0.25
0.5
7
s
s
0.3
1
s
t
t
32K word Block
64K byte Block
WHQV2
EHQV2
Block Erase Time
2
1.2
6
0.9
s
4K word Block
8K byte Block
2
2
2
0.6
84
56
5
0.5
64
42
s
s
Full Chip Erase Time
Set Lock-Bit Time
420
200
t
t
WHQV3
EHQV3
µs
t
t
WHQV4
EHQV4
Clear Block Lock-Bits Time
2
4
4
1
6
5
0.69
6
s
t
t
Word/Byte Write Suspend Latency Time to
Read
WHRZ1
EHRZ1
15
30
15
30
µs
µs
t
t
Block Erase Suspend Latency Time to
Read
WHRZ2
EHRZ2
16
16
Latency Time from Block Erase Resume
Command to Block Erase Suspend
Command
t
5
600
600
µs
ERES
NOTES:
1. Typical values measured at T =+25°C and V =3.0V, V =3.0V or 12.0V. Assumes corresponding lock-bits are not
CCW
A
CC
set. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. A latency time is required from issuing suspend command(WE# or CE# going high) until RY/BY# going High Z or SR.7
going "1".
5. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter
than t
and both commands are written repeatedly, a longer time is required than standard block erase until the
ERES
completion of the operation.
Rev. 1.27
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
*1
tVR
tR
t2VPH
tPHQV
VIH
(P)
RP#
(RST#)
VIL
VCCWH1/2
(VPPH1/2)
*2
(V)
VCCW
(VPP)
GND
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tR
tF
tELQV
VIH
VIL
VIH
VIL
VIH
VIL
VIH
(E)
CE#
(W)
WE#
tR
tF
tGLQV
(G)
OE#
(S)
WP#
VIL
VOH
High Z
Valid
Output
DATA
(D/Q)
V
OL
*1 t5VPH for the device in 5V operations.
*2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP)
to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications t , t , t in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
VR
R
F
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
1
Min.
0.5
Max.
Unit
t
t
t
V
Rise Time
CC
30000
µs/V
µs/V
µs/V
VR
Input Signal Rise Time
Input Signal Fall Time
1, 2
1, 2
1
1
R
F
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
t (Max.) and t (Max.) for RP# (RST#) are 50µs/V.
R
F
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below V (Min.) or above V (Max.) on address, data, reset, and control signals,
IH
IL
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
Input Signal
VIH (Min.)
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for V (Min.) and V (Max.).
IH
IL
Rev. 1.10
iv
(1)
A-2 RELATED DOCUMENT INFORMATION
Document No.
Document Name
AP-001-SD-E
AP-006-PT-E
AP-007-SW-E
Flash Memory Family Software Drivers
Data Protection Method of SHARP Flash Memory
RP#, V Electric Potential Switching Circuit
PP
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
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