LH28F640BFB-PBTL60_技术文档

Date

Jan. 21. 2003

64M (x16) Flash Memory

LH28F640BFB-PBTL60

LHF64FB7

• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,

full or in part, of this material is prohibited without the express written permission of the company.

• When using the products covered herein, please observe the conditions written herein and the precautions outlined in

the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly

adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following application areas. When using the

products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure

to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph

(3).

• Office electronics

• Instrumentation and measuring equipment

• Machine tools

• Audiovisual equipment

• Home appliance

• Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment which demands high

reliability, should first contact a sales representative of the company and then accept responsibility for

incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring

reliability and safety of the equipment and the overall system.

• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment

• Mainframe computers

• Traffic control systems

• Gas leak detectors and automatic cutoff devices

• Rescue and security equipment

• Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands extremely high performance

in terms of functionality, reliability, or accuracy.

• Aerospace equipment

• Communications equipment for trunk lines

• Control equipment for the nuclear power industry

• Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales

representative of the company.

• Please direct all queries regarding the products covered herein to a sales representative of the company.

Rev. 2.44

LHF64FB7

1

CONTENTS

PAGE

0.8mm pitch 60-Ball CSP Pinout ............................... 3

Pin Descriptions.......................................................... 4

PAGE

Extended Status Register Definition......................... 15

Partition Configuration Register Definition.............. 16

Partition Configuration ............................................. 16

1 Electrical Specifications......................................... 17

1.1 Absolute Maximum Ratings ........................... 17

1.2 Operating Conditions...................................... 17

1.2.1 Capacitance.............................................. 18

1.2.2 AC Input/Output Test Conditions ............ 18

1.2.3 DC Characteristics ................................... 19

Simultaneous Operation Modes

Allowed with Four Planes .................................. 5

Memory Map.............................................................. 6

Identifier Codes and OTP Address

for Read Operation ............................................. 7

Identifier Codes and OTP Address for

Read Operation on Partition Configuration........ 7

OTP Block Address Map for OTP Program............... 8

Bus Operation............................................................. 9

Command Definitions .............................................. 10

Functions of Block Lock and Block Lock-Down..... 12

1.2.4 AC Characteristics

- Read-Only Operations......................... 21

1.2.5 AC Characteristics

- Write Operations ................................. 26

Block Locking State Transitions upon

Command Write................................................ 12

1.2.6 Reset Operations ...................................... 28

Block Locking State Transitions upon

1.2.7 Block Erase, Full Chip Erase,

(Page Buffer) Program and

WP# Transition................................................. 13

OTP Program Performance.................... 29

Status Register Definition......................................... 14

2 Related Document Information.............................. 30

Rev. 2.44

LHF64FB7

2

LH28F640BFB-PBTL60

64Mbit (4Mbit×16)

Page Mode Dual Work Flash MEMORY

64M density with 16Bit I/O Interface

Flexible Blocking Architecture

• Eight 4K-word Parameter Blocks

• One-hundred and twenty-seven 32K-word Main

Blocks

High Performance Reads

• 60/25ns 8-Word Page Mode

• Bottom Parameter Location

Configurative 4-Plane Dual Work

• Flexible Partitioning

• Read operations during Block Erase or (Page Buffer)

Program

Enhanced Data Protection Features

• Individual Block Lock and Block Lock-Down with

Zero-Latency

• All blocks are locked at power-up or device reset.

• Absolute Protection with V_PP≤V_PPLK

• Status Register for Each Partition

Low Power Operation

• 2.7V Read and Write Operations

• V_CCQfor Input/Output Power Supply Isolation

• Block Erase, Full Chip Erase, (Page Buffer) Word

Program Lockout during Power Transitions

• Automatic Power Savings Mode Reduces I_CCR

in Static Mode

Automated Erase/Program Algorithms

• 3.0V Low-Power 11µs/Word (Typ.)

Programming

• 12V No Glue Logic 9µs/Word (Typ.)

Production Programming and 0.5s Erase (Typ.)

Enhanced Code + Data Storage

• 5µs Typical Erase/Program Suspends

OTP (One Time Program) Block

• 4-Word Factory-Programmed Area

• 4-Word User-Programmable Area

Cross-Compatible Command Support

• Basic Command Set

• Common Flash Interface (CFI)

High Performance Program with Page Buffer

• 16-Word Page Buffer

• 5µs/Word (Typ.) at 12V V_PP

Extended Cycling Capability

• Minimum 100,000 Block Erase Cycles

0.8mm pitch 60-Ball CSP

Operating Temperature 0°C to +70°C

ETOX^TM*Flash Technology

CMOS Process (P-type silicon substrate)

Not designed or rated as radiation hardened

The product, which is 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low

power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can

operate at V_CC=2.7V-3.6V and V_PP=1.65V-3.6V or 11.7V-12.3V. Its low voltage operation capability greatly extends

battery life for portable applications.

The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus

eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual

work operation.

The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main

Blocks that provide maximum flexibility for safe nonvolatile code and data storage.

Fast program capability is provided through the use of high speed Page Buffer Program.

Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.

* ETOX is a trademark of Intel Corporation.

Rev. 2.44

LHF64FB7

3

60-BALL CSP

PINOUT

11mm x 8mm

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

NC NC NC

A

14

A

13

10

20

A

15

A

16 GND VCCQ NC NC NC

A

11

A

A12 DQ15 DQ14 DQ7

A

8

A

9

DQ6 DQ5 DQ13

WE# RST#

WP#

A

21 DQ12 VCC DQ4

19 DQ¹⁰DQ11 DQ3

V

PP

A

F

A

17

A

18

A7

A4

A1

DQ1 DQ2 DQ9

OE# DQ8 DQ0

G

H

A

5

2

A

6

3

NC NC NC

A

0

GND CE# NC NC NC

Figure 1. 0.8mm pitch 60-Ball CSP Pinout

Rev. 2.44

LHF64FB7

4

Table 1. Pin Descriptions

Symbol

A₀-A₂₁

Type

Name and Function

ADDRESS INPUTS: Inputs for addresses. 64M: A₀-A₂₁

INPUT

DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User

Interface) write cycles, outputs data during memory array, status register, query code,

identifier code and partition configuration register code reads. Data pins float to high-

impedance (High Z) when the chip or outputs are deselected. Data is internally latched

during an erase or program cycle.

INPUT/

OUTPUT

DQ₀-DQ₁₅

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense

amplifiers. CE#-high (V_IH) deselects the device and reduces power consumption to

standby levels.

CE#

INPUT

RESET: When low (V_IL), RST# resets internal automation and inhibits write operations

which provides data protection. RST#-high (V_IH) enables normal operation. After

power-up or reset mode, the device is automatically set to read array mode. RST# must

be low during power-up/down.

RST#

OE#

INPUT

OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the rising edge of CE# or WE# (whichever goes high first).

WE#

WRITE PROTECT: When WP# is V_IL, locked-down blocks cannot be unlocked. Erase

WP#

INPUT

or program operation can be executed to the blocks which are not locked and not locked-

down. When WP# is V_IH, lock-down is disabled.

MONITORING POWER SUPPLY VOLTAGE: V_PPis not used for power supply pin.

With V_PP≤V_PPLK, block erase, full chip erase, (page buffer) program or OTP program

cannot be executed and should not be attempted.

Applying 12V 0.3V to V_PPprovides fast erasing or fast programming mode. In this

mode, V_PPis power supply pin. Applying 12V 0.3V to V_PPduring erase/program can

only be done for a maximum of 1,000 cycles on each block. V_PPmay be connected to

V_PP

INPUT

12V 0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits

may reduce block cycling capability or cause permanent damage.

DEVICE POWER SUPPLY (2.7V-3.6V): With V_CC≤V_LKO, all write attempts to the

flash memory are inhibited. Device operations at invalid V_CCvoltage (see DC

Characteristics) produce spurious results and should not be attempted.

V_CC

SUPPLY

INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output

pins.

V_CCQ

SUPPLY

GND

NC

GROUND: Do not float any ground pins.

NO CONNECT: Lead is not internally connected; it may be driven or floated.

Rev. 2.44

LHF64FB7

5

Table 2. Simultaneous Operation Modes Allowed with Four Planes^{(1, 2)}

THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:

Page

IF ONE

PARTITION IS:

Block

Erase

Suspend

Read Read

Word

OTP

Block FullChip Program

Buffer

Array ID/OTP Status Query Program

Program Erase

Erase Suspend

Program

Read Array

Read ID/OTP

Read Status

X

Read Query

Word Program

Page Buffer

Program

X

OTP Program

Block Erase

X

Full Chip Erase

Program

Suspend

X

Block Erase

Suspend

X

NOTES:

1. "X" denotes the operation available.

2. Configurative Partition Dual Work Restrictions:

Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each

partition. Only one partition can be erased or programmed at a time - no command queuing.

Commands must be written to an address within the block targeted by that command.

Rev. 2.44

LHF64FB7

6

BLOCK NUMBER ADDRESS RANGE

1F8000H - 1FFFFFH

1F0000H - 1F7FFFH

1E8000H - 1EFFFFH

1E0000H - 1E7FFFH

1D8000H - 1DFFFFH

1D0000H - 1D7FFFH

1C8000H - 1CFFFFH

1C0000H - 1C7FFFH

1B8000H - 1BFFFFH

1B0000H - 1B7FFFH

1A8000H - 1AFFFFH

1A0000H - 1A7FFFH

198000H - 19FFFFH

190000H - 197FFFH

188000H - 18FFFFH

180000H - 187FFFH

178000H - 17FFFFH

170000H - 177FFFH

168000H - 16FFFFH

160000H - 167FFFH

158000H - 15FFFFH

150000H - 157FFFH

148000H - 14FFFFH

140000H - 147FFFH

138000H - 13FFFFH

130000H - 137FFFH

128000H - 12FFFFH

120000H - 127FFFH

118000H - 11FFFFH

110000H - 117FFFH

108000H - 10FFFFH

100000H - 107FFFH

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

32K-WORD

BLOCK NUMBER ADDRESS RANGE

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

3F8000H - 3FFFFFH

3F0000H - 3F7FFFH

3E8000H - 3EFFFFH

3E0000H - 3E7FFFH

3D8000H - 3DFFFFH

3D0000H - 3D7FFFH

3C8000H - 3CFFFFH

3C0000H - 3C7FFFH

3B8000H - 3BFFFFH

3B0000H - 3B7FFFH

3A8000H - 3AFFFFH

3A0000H - 3A7FFFH

398000H - 39FFFFH

390000H - 397FFFH

388000H - 38FFFFH

380000H - 387FFFH

378000H - 37FFFFH

370000H - 377FFFH

368000H - 36FFFFH

360000H - 367FFFH

358000H - 35FFFFH

350000H - 357FFFH

348000H - 34FFFFH

340000H - 347FFFH

338000H - 33FFFFH

330000H - 337FFFH

328000H - 32FFFFH

320000H - 327FFFH

318000H - 31FFFFH

310000H - 317FFFH

308000H - 30FFFFH

300000H - 307FFFH

32K-WORD

0F8000H - 0FFFFFH

0F0000H - 0F7FFFH

0E8000H - 0EFFFFH

0E0000H - 0E7FFFH

0D8000H - 0DFFFFH

0D0000H - 0D7FFFH

0C8000H - 0CFFFFH

0C0000H - 0C7FFFH

0B8000H - 0BFFFFH

0B0000H - 0B7FFFH

0A8000H - 0AFFFFH

0A0000H - 0A7FFFH

098000H - 09FFFFH

090000H - 097FFFH

088000H - 08FFFFH

080000H - 087FFFH

078000H - 07FFFFH

070000H - 077FFFH

068000H - 06FFFFH

060000H - 067FFFH

058000H - 05FFFFH

050000H - 057FFFH

048000H - 04FFFFH

040000H - 047FFFH

038000H - 03FFFFH

030000H - 037FFFH

028000H - 02FFFFH

020000H - 027FFFH

018000H - 01FFFFH

010000H - 017FFFH

008000H - 00FFFFH

007000H - 007FFFH

006000H - 006FFFH

005000H - 005FFFH

004000H - 004FFFH

003000H - 003FFFH

002000H - 002FFFH

001000H - 001FFFH

000000H - 000FFFH

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32K-WORD

4K-WORD

2F8000H - 2FFFFFH

2F0000H - 2F7FFFH

2E8000H - 2EFFFFH

2E0000H - 2E7FFFH

2D8000H - 2DFFFFH

2D0000H - 2D7FFFH

2C8000H - 2CFFFFH

2C0000H - 2C7FFFH

2B8000H - 2BFFFFH

2B0000H - 2B7FFFH

2A8000H - 2AFFFFH

2A0000H - 2A7FFFH

298000H - 29FFFFH

290000H - 297FFFH

288000H - 28FFFFH

280000H - 287FFFH

278000H - 27FFFFH

270000H - 277FFFH

268000H - 26FFFFH

260000H - 267FFFH

258000H - 25FFFFH

250000H - 257FFFH

248000H - 24FFFFH

240000H - 247FFFH

238000H - 23FFFFH

230000H - 237FFFH

228000H - 22FFFFH

220000H - 227FFFH

218000H - 21FFFFH

210000H - 217FFFH

208000H - 20FFFFH

200000H - 207FFFH

32K-WORD

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

8

7

6

5

4

3

2

1

0

Figure 2. Memory Map (Bottom Parameter)

Rev. 2.44

LHF64FB7

7

Table 3. Identifier Codes and OTP Address for Read Operation

Address

Data

[DQ₁₅-DQ₀]

Code

Notes

[A₁₅-A₀]

Manufacturer Code

Device Code

Manufacturer Code

0000H

0001H

00B0H

00B1H

DQ₀= 0

1

1, 2

3

Bottom Parameter Device Code

Block is Unlocked

Block Lock Configuration

Code

Block

Address

+ 2

Block is Locked

DQ₀= 1

DQ₁= 0

DQ₁= 1

3

Block is not Locked-Down

Block is Locked-Down

3

Device Configuration Code

OTP

Partition Configuration Register

0006H

0080H

PCRC

OTP-LK

OTP

1, 4

1, 5

1, 6

OTP Lock

OTP

0081-0088H

NOTES:

1. The address A₂₁-A₁₆are shown in below table for reading the manufacturer code, device code,

device configuration code and OTP data.

2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address).

3. Block Address = The beginning location of a block address within the partition to which

the Read Identifier Codes/OTP command (90H) has been written.

DQ₁₅-DQ₂are reserved for future implementation.

4. PCRC=Partition Configuration Register Code.

5. OTP-LK=OTP Block Lock configuration.

6. OTP=OTP Block data.

Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration⁽¹⁾(64M-bit device)

Partition Configuration Register ⁽²⁾

Address (64M-bit device)

[A₂₁-A₁₆]

PCR.10

PCR.9

PCR.8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

00H

00H or 10H

00H or 20H

00H or 30H

00H or 10H or 20H

00H or 20H or 30H

00H or 10H or 30H

00H or 10H or 20H or 30H

NOTES:

1. The address to read the identifier codes or OTP data is dependent on the partition which is selected

when writing the Read Identifier Codes/OTP command (90H).

2. Refer to Table 12 for the partition configuration register.

Rev. 2.44

LHF64FB7

8

[A²¹-A ]

0

000088H

Customer Programmable Area

Factory Programmed Area

000085H

000084H

000081H

000080H

Reserved for Future Implementation

(DQ15-DQ2)

Customer Programmable Area Lock Bit (DQ

Factory Programmed Area Lock Bit (DQ

1

)

0

)

Figure 3. OTP Block Address Map for OTP Program

(The area outside 80H~88H cannot be used.)

Rev. 2.44

LHF64FB7

9

Table 5. Bus Operation^{(1, 2)}

Mode

Read Array

Output Disable

Standby

Notes RST#

CE#

V_IL

V_IH

X

OE#

V_IL

V_IH

X

WE#

V_IH

X

Address

V_PP

X

DQ_0-15

D_OUT

6

V_IH

V_IL

X

High Z

X

Reset

3

6

X

See

Table 3 and

Table 4

See

Table 3 and

Table 4

Read Identifier

Codes/OTP

V_IH

V_IL

V_IH

X

See

Appendix

See

Appendix

V_IH

V_IL

V_IH

V_IL

Read Query

6,7

X

Write

4,5,6

X

D_IN

NOTES:

1. Refer to DC Characteristics. When V_PP≤V_PPLK, memory contents can be read, but cannot be altered.

2. X can be V_ILor V_IHfor control pins and addresses, and V_PPLKor V_PPH1/2for V_PP. See DC Characteristics for V_PPLK

and V_PPH1/2voltages.

3. RST# at GND 0.2V ensures the lowest power consumption.

4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed

when V_PP=V_PPH1/2and V_CC=2.7V-3.6V.

5. Refer to Table 6 for valid D_INduring a write operation.

6. Never hold OE# low and WE# low at the same timing.

7. Refer to Appendix of LH28F640BF series for more information about query code.

Rev. 2.44

LHF64FB7

10

Table 6. Command Definitions⁽¹¹⁾

First Bus Cycle

Bus

Second Bus Cycle

Command

Cycles Notes

Req’d

Oper⁽¹⁾

Addr⁽²⁾

Oper⁽¹⁾

Addr⁽²⁾

Data⁽³⁾

Data

Read Array

1

Write

PA

BA

X

FFH

90H

98H

70H

50H

20H

30H

Read Identifier Codes/OTP

Read Query

≥ 2

2

4

Read

IA or OA ID or OD

QA

PA

QD

Read Status Register

Clear Status Register

Block Erase

SRD

1

2

5

Write

BA

X

D0H

Full Chip Erase

Program

2

5,9

40H or

10H

2

≥ 4

1

5,6

5,7

8,9

Write

WA

PA

Write

WA

WD

N-1

Page Buffer Program

E8H

Block Erase and (Page Buffer)

Program Suspend

B0H

Block Erase and (Page Buffer)

Program Resume

1

8,9

Write

PA

D0H

Set Block Lock Bit

2

Write

BA

60H

C0H

60H

Write

BA

01H

D0H

2FH

OD

Clear Block Lock Bit

Set Block Lock-down Bit

OTP Program

10

9

BA

OA

Set Partition Configuration Register

PCRC

04H

NOTES:

1. Bus operations are defined in Table 5.

2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second

bus cycle.

X=Any valid address within the device.

PA=Address within the selected partition.

IA=Identifier codes address (See Table 3 and Table 4).

QA=Query codes address. Refer to Appendix of LH28F640BF series for details.

BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.

WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.

OA=Address of OTP block to be read or programmed (See Figure 3).

PCRC=Partition configuration register code presented on the address A₀-A₁₅.

3. ID=Data read from identifier codes. (See Table 3 and Table 4).

QD=Data read from query database. Refer to Appendix of LH28F640BF series for details.

SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.

WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever

goes high first) during command write cycles.

OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first)

during command write cycles.

N-1=N is the number of the words to be loaded into a page buffer.

4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock

configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4).

The Read Query command is available for reading CFI (Common Flash Interface) information.

5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked

block can be erased or programmed when RST# is V_IH.

6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.

7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any

valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of

Rev. 2.44

LHF64FB7

11

LH28F640BF series for details.

8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the

suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.

9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while

the block erase operation is being suspended.

10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is V_IL. When

WP# is V_IH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.

11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be

used.

Rev. 2.44

LHF64FB7

12

Table 7. Functions of Block Lock⁽⁵⁾and Block Lock-Down

Current State

Erase/Program Allowed ⁽²⁾

(1)

State

[000]

WP#

State Name

Unlocked

DQ₁

DQ₀

0

1

Yes

No

[001]⁽³⁾

[011]

Locked

0

1

0

1

0

1

Locked-down

Unlocked

Locked

No

Yes

No

[100]

[101]⁽³⁾

[110]⁽⁴⁾

[111]

1

0

1

Lock-down Disable

Yes

No

NOTES:

1. DQ₀=1: a block is locked; DQ₀=0: a block is unlocked.

DQ₁=1: a block is locked-down; DQ₁=0: a block is not locked-down.

2. Erase and program are general terms, respectively, to express: block erase, full chip erase and

(page buffer) program operations.

3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,

[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.

4. When WP# is driven to V_ILin [110] state, the state changes to [011] and the blocks are

automatically locked.

5. OTP (One Time Program) block has the lock function which is different from those described

above.

Table 8. Block Locking State Transitions upon Command Write⁽⁴⁾

Current State

DQ₁DQ₀

Result after Lock Command Written (Next State)

Set Lock⁽¹⁾

Clear Lock⁽¹⁾

No Change

[000]

Set Lock-down⁽¹⁾

State WP#

[011]⁽²⁾

[011]

[000]

[001]

0

1

[001]

No Change⁽³⁾

No Change

[101]

[011]

[100]

0

1

0

1

0

No Change

[111]⁽²⁾

[111]

[101]

[110]

1

0

1

0

No Change

[111]

[100]

[111]⁽²⁾

No Change

[111]

1

No Change

[110]

No Change

NOTES:

1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit

command and "Set Lock-down" means Set Block Lock-Down Bit command.

2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ₀=0), the

corresponding block is locked-down and automatically locked at the same time.

3. "No Change" means that the state remains unchanged after the command written.

4. In this state transitions table, assumes that WP# is not changed and fixed V_ILor V_IH.

Rev. 2.44

LHF64FB7

13

Table 9. Block Locking State Transitions upon WP# Transition⁽⁴⁾

Current State

Result after WP# Transition (Next State)

Previous State

WP#=0→1⁽¹⁾

WP#=1→0⁽¹⁾

DQ₁

DQ₀

State

WP#

-

[000]

[001]

0

1

[100]

[101]

[110]

-

[110]⁽²⁾

[011]

0

1

Other than [110]⁽²⁾

[111]

-

[100]

[101]

[110]

1

0

1

0

1

0

-

[000]

[001]

[011]⁽³⁾

[011]

-

[111]

1

-

NOTES:

1. "WP#=0→1" means that WP# is driven to V_IHand "WP#=1→0" means that WP# is driven to

V_IL.

2. State transition from the current state [011] to the next state depends on the previous state.

3. When WP# is driven to V_ILin [110] state, the state changes to [011] and the blocks are

automatically locked.

4. In this state transitions table, assumes that lock configuration commands are not written in

previous, current and next state.

Rev. 2.44

LHF64FB7

14

Table 10. Status Register Definition

R

15

R

14

R

11

R

10

R

9

R

8

13

BEFCES

5

12

PBPOPS

4

WSMS

7

BESS

6

VPPS

3

PBPSS

2

DPS

1

R

0

SR.15 - SR.8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

NOTES:

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

Status Register indicates the status of the partition, not WSM

(Write State Machine). Even if the SR.7 is "1", the WSM may

be occupied by the other partition when the device is set to 2,

3 or 4 partitions configuration.

1 = Ready

0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)

1 = Block Erase Suspended

Check SR.7 to determine block erase, full chip erase, (page

buffer) program or OTP program completion. SR.6 - SR.1 are

invalid while SR.7="0".

0 = Block Erase in Progress/Completed

SR.5 = BLOCK ERASE AND FULL CHIP ERASE

STATUS (BEFCES)

If both SR.5 and SR.4 are "1"s after a block erase, full chip

erase, (page buffer) program, set/clear block lock bit, set

block lock-down bit, set partition configuration register

attempt, an improper command sequence was entered.

1 = Error in Block Erase or Full Chip Erase

0 = Successful Block Erase or Full Chip Erase

SR.4 = (PAGE BUFFER) PROGRAM AND

OTP PROGRAM STATUS (PBPOPS)

SR.3 does not provide a continuous indication of V_PPlevel.

The WSM interrogates and indicates the V_PPlevel only after

Block Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. SR.3 is not guaranteed to

1 = Error in (Page Buffer) Program or OTP Program

0 = Successful (Page Buffer) Program or OTP Program

report accurate feedback when V_PP≠V_PPH1, V_PPH2or V_PPLK

.

SR.3 = V_PPSTATUS (VPPS)

1 = V_PPLOW Detect, Operation Abort

0 = V_PPOK

SR.1 does not provide a continuous indication of block lock

bit. The WSM interrogates the block lock bit only after Block

Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. It informs the system,

depending on the attempted operation, if the block lock bit is

set. Reading the block lock configuration codes after writing

the Read Identifier Codes/OTP command indicates block

lock bit status.

SR.2 = (PAGE BUFFER) PROGRAM SUSPEND

STATUS (PBPSS)

1 = (Page Buffer) Program Suspended

0 = (Page Buffer) Program in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Erase or Program Attempted on a

Locked Block, Operation Abort

0 = Unlocked

SR.15 - SR.8 and SR.0 are reserved for future use and should

be masked out when polling the status register.

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

Rev. 2.44

LHF64FB7

15

Table 11. Extended Status Register Definition

R

15

R

14

R

13

R

12

R

11

R

10

R

9

R

8

SMS

7

R

1

R

0

6

5

4

3

2

XSR.15-8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

NOTES:

After issue a Page Buffer Program command (E8H),

XSR.7="1" indicates that the entered command is accepted.

If XSR.7 is "0", the command is not accepted and a next Page

Buffer Program command (E8H) should be issued again to

check if page buffer is available or not.

XSR.7 = STATE MACHINE STATUS (SMS)

1 = Page Buffer Program available

0 = Page Buffer Program not available

XSR.15-8 and XSR.6-0 are reserved for future use and

should be masked out when polling the extended status

register.

XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

Rev. 2.44

LHF64FB7

16

Table 12. Partition Configuration Register Definition

R

15

R

14

R

13

R

12

R

11

R

PC2

10

R

PC1

9

PC0

8

R

7

6

5

4

3

2

1

0

PCR.15-11 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

111 = There are four partitions in this configuration.

Each plane corresponds to each partition respec-

tively. Dual work operation is available between any

two partitions.

PCR.10-8 = PARTITION CONFIGURATION (PC2-0)

000 = No partitioning. Dual Work is not allowed.

001 = Plane1-3 are merged into one partition.

(default in a bottom parameter device)

PCR.7-0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

010 = Plane 0-1 and Plane2-3 are merged into one

partition respectively.

100 = Plane 0-2 are merged into one partition.

(default in a top parameter device)

NOTES:

After power-up or device reset, PCR10-8 (PC2-0) is set to

011 = Plane 2-3 are merged into one partition. There are "001" in a bottom parameter device and "100" in a top

three partitions in this configuration. Dual work parameter device.

operation is available between any two partitions.

110 = Plane 0-1 are merged into one partition. There are

See Figure 4 for the detail on partition configuration.

three partitions in this configuration. Dual work

operation is available between any two partitions.

101 = Plane 1-2 are merged into one partition. There are

PCR.15-11 and PCR.7-0 are reserved for future use and

should be masked out when checking the partition

three partitions in this configuration. Dual work

operation is available between any two partitions.

configuration register.

PC2 PC1PC0

PARTITIONING FOR DUAL WORK

PARTITION0

PC2 PC1PC0

PARTITIONING FOR DUAL WORK

PARTITION2

PARTITION0

PARTITION1

0

1

0

1

0

1

0

1

0

1

0

1

0

PARTITION1

PARTITION0

PARTITION2 PARTITION1

PARTITION0

PARTITION1

PARTITION2 PARTITION1 PARTITION0

PARTITION0

PARTITION3 PARTITION2 PARTITION1

PARTITION1

PARTITION0

Figure 4. Partition Configuration

Rev. 2.44

LHF64FB7

17

*WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent

damage. These are stress ratings only. Operation

beyond the "Operating Conditions" is not

recommended and extended exposure beyond

the "Operating Conditions" may affect device

reliability.

1 Electrical Specifications

*

1.1 Absolute Maximum Ratings

Operating Temperature

During Read, Erase and Program ......0°C to +70°C ⁽¹⁾

NOTES:

1. Operating temperature is for commercial temperature

product defined by this specification.

2. All specified voltages are with respect to GND.

Minimum DC voltage is -0.5V on input/output pins

and -0.2V on V_CCand V_PPpins. During transitions,

this level may undershoot to -2.0V for periods <20ns.

Maximum DC voltage on input/output pins is

Storage Temperature

During under Bias............................... -10°C to +80°C

During non Bias................................ -65°C to +125°C

Voltage On Any Pin

(except V_CCand V_PP).............. -0.5V to V_CC+0.5V ⁽²⁾

V

_CC+0.5V which, during transitions, may overshoot to

V_CC+2.0V for periods <20ns.

3. Maximum DC voltage on V_PPmay overshoot to

+13.0V for periods <20ns.

4. V_PPerase/program voltage is normally 2.7V-3.6V.

Applying 11.7V-12.3V to V_PPduring erase/program

can be done for a maximum of 1,000 cycles on the

main blocks and 1,000 cycles on the parameter blocks.

V_CCand V_CCQSupply Voltage .......... -0.2V to +3.9V ⁽²⁾

V_PPSupply Voltage .................... -0.2V to +12.6V ^{(2, 3, 4)}

Output Short Circuit Current...........................100mA ⁽⁵⁾

V

_PPmay be connected to 11.7V-12.3V for a total of 80

hours maximum.

5. Output shorted for no more than one second. No more

than one output shorted at a time.

1.2 Operating Conditions

Parameter

Symbol

T_A

Min.

0

Typ.

+25

3.0

12

Max.

+70

3.6

Unit

°C

Notes

Operating Temperature

V_CCSupply Voltage

V_CC

2.7

V

1

I/O Supply Voltage

V_CCQ

V_PPH1

V_PPH2

2.7

3.6

V

V_PPVoltage when Used as a Logic Control

V_PPSupply Voltage

1.65

3.6

V

1

11.7

12.3

V

1, 2

Main Block Erase Cycling: V_PP=V_PPH1

Parameter Block Erase Cycling: V_PP=V_PPH1

Main Block Erase Cycling: V_PP=V_PPH2, 80 hrs.

Parameter Block Erase Cycling: V_PP=V_PPH2, 80 hrs.

Maximum V_PPhours at V_PPH2

NOTES:

100,000

Cycles

Hours

1,000

80

1. See DC Characteristics tables for voltage range-specific specification.

2. Applying V_PP=11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks

and 1,000 cycles on the parameter blocks. A permanent connection to V_PP=11.7V-12.3V is not allowed and can cause

damage to the device.

Rev. 2.44

LHF64FB7

18

1.2.1 Capacitance⁽¹⁾(T_A=+25°C, f=1MHz)

Parameter

Symbol

C_IN

Condition

V_IN=0.0V

Min.

Typ.

Max.

7

Unit

pF

Input Capacitance

4

6

Output Capacitance

C_OUT

V_OUT=0.0V

10

pF

NOTE:

1. Sampled, not 100% tested.

1.2.2 AC Input/Output Test Conditions

V_CCQ

INPUT

V_CCQ/2

TEST POINTS

V_CCQ/2 OUTPUT

0.0

AC test inputs are driven at V_CCQ(min) for a Logic "1" and 0.0V for a Logic "0".

Input timing begins, and output timing ends at V_CCQ/2. Input rise and fall times (10% to 90%) < 5ns.

Worst case speed conditions are when V_CC=V_CC(min).

Figure 5. Transient Input/Output Reference Waveform for V_CC=2.7V-3.6V

Table 13. Configuration Capacitance Loading Value

C_L(pF)

Test Configuration

_CC=2.7V-3.6V

V

30pF, 50pF, 70pF

Figure 6. Transient Equivalent Testing Load Circuit

Rev. 2.44

LHF64FB7

19

1.2.3 DC Characteristics

V_CC=2.7V-3.6V

Notes Min.

Symbol

I_LI

Parameter

Typ.

Max.

+1.0

Unit

Test Conditions

_CC=V_CCMax.,

V

Input Load Current

1

-1.0

µA

V_CCQ=V_CCQMax.,

V_IN/V_OUT=V_CCQor

GND

I_LO

Output Leakage Current

1

-1.0

+1.0

µA

V_CC=V_CCMax.,

CE#=RST#=

V_CCQ0.2V,

I_CCS

V_CCStandby Current

1

4

20

WP#=V_CCQor GND

V_CC=V_CCMax.,

I_CCAS

I_CCD

V_CCAutomatic Power Savings Current

1,4

1

4

20

25

µA

mA

CE#=GND 0.2V,

WP#=V_CCQor GND

V_CCReset Power-Down Current

Average V_CCRead

Current

Normal Mode

RST#=GND 0.2V

1,7

15

V_CC=V_CCMax.,

CE#=V_IL,

OE#=V_IH,

f=5MHz

I_CCR

Average V_CCRead

8 Word Read

1,7

5

10

mA

Current

Page Mode

V_PP=V_PPH1

V_PP=V_PPH2

V_PP=V_PPH1

V_PP=V_PPH2

1,5,7

20

10

4

60

20

30

10

mA

I_CCW

V_CC(Page Buffer) Program Current

V_CCBlock Erase, Full Chip

Erase Current

I_CCE

I_CCWS

I_CCES

I_PPS

I_PPR

V_CC(Page Buffer) Program or

Block Erase Suspend Current

CE#=V_IH

1,2,7

1,6,7

10

2

200

5

µA

V_PPStandby or Read Current

V_PP≤V_CC

V_PP=V_PPH1

V_PP=V_PPH2

V_PP=V_PPH1

V_PP=V_PPH2

V_PP=V_PPH1

V_PP=V_PPH2

V_PP=V_PPH1

V_PP=V_PPH2

1,5,6,7

1,6,7

2

10

2

5

30

5

µA

mA

µA

mA

µA

I_PPW

V_PP(Page Buffer) Program Current

V_PPBlock Erase, Full Chip

Erase Current

I_PPE

5

15

5

2

V_PP(Page Buffer) Program

Suspend Current

I_PPWS

1,6,7

10

2

200

5

1,6,7

I_PPES

V_PPBlock Erase Suspend Current

1,6,7

10

200

Rev. 2.44

LHF64FB7

20

DC Characteristics (Continued)

V

_CC=2.7V-3.6V

Symbol

V_IL

Parameter

Input Low Voltage

Notes Min.

Typ.

Max.

0.4

Unit

V

Test Conditions

5

-0.4

2.4

V_CCQ

+ 0.4

V_IH

Input High Voltage

V

V_CC=V_CCMin.,

_CCQ=V_CCQMin.,

_OL=100µA

V_OL

V

Output Low Voltage

5

0.2

V

I

V

_CC=V_CCMin.,

_CCQ=V_CCQMin.,

V_CCQ

-0.2

V_OH

Output High Voltage

V

I_OH=-100µA

V_PPLockout during Normal

Operations

V_PPLK

3,5,6

6

0.4

3.6

V

V_PPduring Block Erase, Full Chip

Erase, (Page Buffer) Program or OTP

Program Operations

V_PPH1

1.65

3.0

12

V_PPduring Block Erase, Full Chip

Erase, (Page Buffer) Program or OTP

Program Operations

V_PPH2

6

11.7

1.5

12.3

V

V_LKO

V_CCLockout Voltage

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V_CC=3.0V and T_A=+25°C

unless V_CCis specified.

2. I_CCWSand I_CCESare specified with the device de-selected. If read or (page buffer) program is executed while in block

erase suspend mode, the device’s current draw is the sum of I_CCESand I_CCRor I_CCW. If read is executed while in (page

buffer) program suspend mode, the device’s current draw is the sum of I_CCWSand I_CCR

.

3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when V_PP≤V_PPLK, and not guaranteed

in the range between V_PPLK(max.) and V_PPH1(min.), between V_PPH1(max.) and V_PPH2(min.) and above V_PPH2(max.).

4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle

completion. Standard address access timings (t_{AV QV}) provide new data when addresses are changed.

5. Sampled, not 100% tested.

6. V_PPis not used for power supply pin. With V_PP≤V_PPLK, block erase, full chip erase, (page buffer) program and OTP

program cannot be executed and should not be attempted.

Applying 12V 0.3V to V_PPprovides fast erasing or fast programming mode. In this mode, V_PPis power supply pin and

supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths

and layout considerations given to the V_CCpower bus.

Applying 12V 0.3V to V_PPduring erase/program can only be done for a maximum of 1,000 cycles on each block. V_PP

may be connected to 12V 0.3V for a total of 80 hours maximum.

7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.

Rev. 2.44

LHF64FB7

21

(1)

1.2.4 AC Characteristics - Read-Only Operations

V

_CC=2.7V-3.6V, T_A=0°C to +70°C, C_L=30pF

Symbol

t_AVAV

Parameter

Notes Min.

60

Max. Unit

ns

Read Cycle Time

t_{AVQ V}

t_ELQV

t_APA

Address to Output Delay

CE# to Output Delay

60

ns

3

2

Page Address Access Time

25

t_GLQV

t_PHQV

t_EHQZ, t_GHQZ

t_ELQX

t_GLQX

t_OH

OE# to Output Delay

20

RST# High to Output Delay

150

20

CE# or OE# to Output in High Z, Whichever Occurs First

CE# to Output in Low Z

2

0

OE# to Output in Low Z

Output Hold from First Occurring Address, CE# or OE# change

Address Setup to CE#, OE# Going Low

for Reading Status Register

t

_AVEL, t_AVGL

4, 6

10

ns

Address Hold from CE#, OE# Going Low

for Reading Status Register

t

_ELAX, t_GLAX

_EHEL, t_GHGL

5, 6

6

30

15

ns

CE#, OE# Pulse Width High for Reading Status Register

NOTES: Refer to NOTE 1 through NOTE 6 on next page.

V_CC=2.7V-3.6V, T_A=0°C to +70°C, C_L=50pF

Parameter

Symbol

t_AVAV

Notes Min.

65

Max. Unit

ns

Read Cycle Time

t_{AVQ V}

t_ELQV

t_APA

Address to Output Delay

CE# to Output Delay

65

ns

3

2

Page Address Access Time

OE# to Output Delay

25

t_GLQV

t_PHQV

t_EHQZ, t_GHQZ

t_ELQX

t_GLQX

t_OH

20

RST# High to Output Delay

150

20

CE# or OE# to Output in High Z, Whichever Occurs First

CE# to Output in Low Z

2

0

OE# to Output in Low Z

Output Hold from First Occurring Address, CE# or OE# change

Address Setup to CE#, OE# Going Low

for Reading Status Register

t

_AVEL, t_AVGL

4, 6

10

ns

Address Hold from CE#, OE# Going Low

for Reading Status Register

t

_ELAX, t_GLAX

_EHEL, t_GHGL

5, 6

6

30

15

ns

CE#, OE# Pulse Width High for Reading Status Register

NOTES: Refer to NOTE 1 through NOTE 6 on next page.

Rev. 2.44

LHF64FB7

22

V

_CC=2.7V-3.6V, T_A=0°C to +70°C, C_L=70pF

Symbol

t_AVAV

Parameter

Notes Min.

70

Max. Unit

ns

Read Cycle Time

t_{AVQ V}

t_ELQV

t_APA

Address to Output Delay

CE# to Output Delay

70

ns

3

2

Page Address Access Time

30

t_GLQV

t_PHQV

t_EHQZ, t_GHQZ

t_ELQX

t_GLQX

t_OH

OE# to Output Delay

25

RST# High to Output Delay

150

25

CE# or OE# to Output in High Z, Whichever Occurs First

CE# to Output in Low Z

2

0

OE# to Output in Low Z

Output Hold from First Occurring Address, CE# or OE# change

Address Setup to CE#, OE# Going Low

for Reading Status Register

t_AVEL, t_AVGL

t_ELAX, t_GLAX

4, 6

10

ns

Address Hold from CE#, OE# Going Low

for Reading Status Register

5, 6

6

30

15

ns

t

_EHEL, t_GHGL

CE#, OE# Pulse Width High for Reading Status Register

NOTES:

1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.

2. Sampled, not 100% tested.

3. OE# may be delayed up to t_ELQVt_GLQVafter the falling edge of CE# without impact to t_ELQV

.

4. Address setup time (t_AVEL, t_AVGL) is defined from the falling edge of CE# or OE# (whichever goes low last).

5. Address hold time (t_ELAX, t_GLAX) is defined from the falling edge of CE# or OE# (whichever goes low last).

6. Specifications t

operations.

, t_{AV GL}, t_ELAX, t_GLAXand t_EHEL, t_GHGLfor read operations apply to only status register read

AVEL

Rev. 2.44

LHF64FB7

23

(A) ^V

IH

VALID

A

21-0 (A)

20-0

ADDRESS

t_AVAV

V_IL

t_EHQZ

t_GHQZ

t_AVQV

t_EHEL

V_IH

V_IL

(E)

CE#

t_AVEL

t_ELAX

t_AVGL

t_GHGL

t_GLAX

OE# (G) ^V

IH

V_IL

t_ELQV

V_IH

V_IL

(W)

WE#

t_GLQV

t_GLQX

t_ELQX

t_OH

V_OH

High Z

VALID

DQ_15-0

(D/Q)

OUTPUT

V_OL

t_PHQV

V_IH

V_IL

(P)

RST#

Figure 7. AC Waveform for Single Asynchronous Read Operations

from Status Register, Identifier Codes, OTP Block or Query Code

Rev. 2.44

LHF64FB7

24

V_IH

V_IL

VALID

A

A21-3 (A(A))

20-3

ADDRESS

t_AVAV

t_AVQV

A_2-0(A) ^V

IH

VALID

ADDRESS

VALID

ADDRESS

V_IL

V_IH

V_IL

(E)

CE#

t_ELQV

t_EHQZ

t_GHQZ

OE# (G) ^V

IH

V_IL

WE# (W) ^V

IH

t_GLQV

V_IL

t_GLQX

t_APA

t_OH

t_ELQX

V_OH

V_OL

High Z

VALID

DQ_15-0

(D/Q)

OUTPUT OUTPUT

OUTPUT

t_PHQV

V_IH

V_IL

(P)

RST#

Figure 8. AC Waveform for Asynchronous 4-Word Page Mode

Read Operations from Main Blocks or Parameter Blocks

Rev. 2.44

LHF64FB7

25

V_IH

V_IL

VALID

A

A21-3 (A(A))

20-3

ADDRESS

t_AVAV

t_AVQV

A_2-0(A) ^V

IH

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS ADDRESS ADDRESS ADDRESS

V_IL

V_IH

V_IL

(E)

CE#

t_EHQZ

t_GHQZ

t_ELQV

OE# (G) ^V

IH

V_IL

WE# (W) ^V

IH

t_GLQV

V_IL

t_GLQX

t_APA

t_OH

t_ELQX

V_OH

V_OL

High Z

t_PHQV

VALID VALID VALID

VALID

VALID VALID VALID

VALID

DQ_15-0

(D/Q)

OUTPUT

V_IH

V_IL

(P)

RST#

Figure 9. AC Waveform for Asynchronous 8-Word Page Mode

Read Operations from Main Blocks or Parameter Blocks

Rev. 2.44

LHF64FB7

26

(1), (2)

1.2.5 AC Characteristics - Write Operations

V_CC=2.7V-3.6V, T_A=0°C to +70°C

Symbol

Parameter

Notes

Min.

60

Max.

Unit

ns

t_AVAV

Write Cycle Time

65

70

t_PHWL(t_PHEL

)

RST# High Recovery to WE# (CE#) Going Low

CE# (WE#) Setup to WE# (CE#) Going Low

3

150

t_ELWL(t_WLEL

)

0

45

50

55

40

45

50

55

0

ns

t_AVAV=60ns

_AVAV=65ns

t_AVAV=70ns

t

_WLWH(t_ELEH

)

t

WE# (CE#) Pulse Width

4, 9

8

t_DVWH(t_DVEH

)

Data Setup to WE# (CE#) Going High

t_AVAV=60ns

Address Setup to WE# (CE#) Going

High

t

_AVWH(t_AVEH

)

t_AVAV=65ns

t_AVAV=70ns

8, 9

t

_WHEH(t_EHWH

)

CE# (WE#) Hold from WE# (CE#) High

Data Hold from WE# (CE#) High

Address Hold from WE# (CE#) High

WE# (CE#) Pulse Width High

t_WHDX(t_EHDX

_WHAX(t_EHAX

t_WHWL(t_EHEL

t_SHWH(t_SHEH

_VVWH(t_VVEH

t_WHGL(t_EHGL

t_QVSL

)

0

t

)

0

)

5

3

15

0

)

WP# High Setup to WE# (CE#) Going High

V_PPSetup to WE# (CE#) Going High

t

)

200

30

0

)

Write Recovery before Read

WP# High Hold from Valid SRD

V_PPHold from Valid SRD

3, 6

t_QVVL

0

t_AVQV

50

+

t_WHR0(t_EHR0

)

WE# (CE#) High to SR.7 Going "0"

3, 7

ns

NOTES:

1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and

OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only

operations.

2. A write operation can be initiated and terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width (t_WP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of

CE# or WE# (whichever goes high first). Hence, t_WP=t_WLWH=t_ELEH=t_WLEH=t_ELWH

5. Write pulse width high (t_WPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling

edge of CE# or WE# (whichever goes low last). Hence, t_WPH=t_WHWL=t_EHEL=t_WHEL=t_EHWL

.

6. V_PPshould be held at V_PP=V_PPH1/2until determination of block erase, full chip erase, (page buffer) program or OTP

program success (SR.1/3/4/5=0).

7. t_WHR0(t_EHR0) after the Read Query or Read Identifier Codes/OTP command=t_AVQV+100ns.

8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit

configuration.

9. t_WLWH(t_ELEH) and t_AVWH(t_AVEH) values vary depending on the write cycle time (t_AVAV).

Rev. 2.44

LHF64FB7

27

NOTE 1

NOTE 2

NOTE 3

NOTE 4

NOTE 5

AA

(A) ^V

IH

VALID

ADDRESS

VALID

2210-0-0(A)

ADDRESS

V_IL

t_AVWH(t_AVEH

)

t_AVAV

t_WHAX

(t_EHAX

)

V_IH

V_IL

NOTES 5, 6

(E)

CE#

t_ELWL(t_WLEL

)

t_WHEH(t_EHWH

)

t_WHGL(t_EHGL)

NOTES 5, 6

OE# (G) ^V

IH

V_IL

t_PHWL(t_PHEL)

t_WHWL(t_EHEL

)

WE# (W) ^V

IH

V_IL

t_WLWH

(t_ELEH

t_WHQV1,2,3(t_EHQV1,2,3)

)

t_DVWH(t_DVEH

)

t

_WHDX(t_EHDX)

V_IH

V_IL

DQ_15-0

(D/Q)

VALID

SRD

DATA IN

t_WHR0(t_EHR0

)

"1"

"0"

SR.7 (R)

(P) ^V

IH

RST#

V_IL

t_SHWH(t_SHEH

)

t_QVSL

V_IH

V_IL

WP# (S)

t_VVWH(t_VVEH

)

t_QVVL

V_PPH1,2

V

_PP(V) V_PPLK

V_IL

NOTES:

1. V_CCpower-up and standby.

2. Write each first cycle command.

3. Write each second cycle command or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.

Figure 10. AC Waveform for Write Operations

Rev. 2.44

LHF64FB7

28

1.2.6 Reset Operations

tPHQV

VIH

(P)

RST#

V^IL

tPLPH

V_OH

High Z

VALID

OUTPUT

DQ

_15-0(D/Q)

V

OL

(A) Reset during Read Array Mode

SR.7="1"

ABORT

COMPLETE

tPLRH

tPHQV

VIH

VIL

(P)

RST#

tPLPH

V_OH

High Z

VALID

OUTPUT

DQ

_15-0(D/Q)

V

OL

(B) Reset during Erase or Program Mode

V_CC(min)

GND

V_CC

tVHQV

t2VPH

tPHQV

VIH

(P)

RST#

V^IL

V_OH

High Z

VALID

OUTPUT

DQ

_15-0(D/Q)

V

OL

(C) RST# rising timing

Figure 11. AC Waveform for Reset Operations

Reset AC Specifications (V_CC=2.7V-3.6V, T_A=0°C to +70°C)

Symbol

t_PLPH

Parameter

Notes

1, 2, 3

Min.

100

Max.

Unit

RST# Low to Reset during Read

(RST# should be low during power-up.)

ns

t_PLRH

t_2VPH

RST# Low to Reset during Erase or Program

V_CC2.7V to RST# High

1, 3, 4

1, 3, 5

3

22

1

µs

ns

100

t_VHQV

NOTES:

V_CC2.7V to Output Delay

ms

1. A reset time, t_PHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC

Characteristics - Read-Only Operations for t_PHQV

.

2. t_PLPHis <100ns the device may still reset but this is not guaranteed.

3. Sampled, not 100% tested.

4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,

the reset will complete within 100ns.

5. When the device power-up, holding RST# low minimum 100ns is required after V_CChas been in predefined range and

also has been in stable there.

Rev. 2.44

LHF64FB7

29

(3)

1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance

V

_CC=2.7V-3.6V, T_A=0°C to +70°C

Page Buffer

Command is

Used or not

Used

V_PP=V_PPH1

(In System)

V_PP=V_PPH2

(In Manufacturing)

Symbol

Parameter

Notes

Unit

Typ.⁽¹⁾Max.

Min.

(2)

Min.

2

Not Used

Used

0.05

0.03

0.38

0.24

11

0.3

0.04

0.02

0.31

0.17

9

0.12

s

4K-Word Parameter Block

Program Time

t_WPB

0.12

2.4

0.06

1.0

0.5

185

90

Not Used

Used

s

32K-Word Main Block

Program Time

t_WMB

1.0

s

t_WHQV1

t_EHQV1

t_WHOV1

t_EHOV1

t_WHQV2

t_EHQV2

t_WHQV3

t_EHQV3

/

Not Used

Used

200

100

µs

Word Program Time

OTP Program Time

7

5

2

Not Used

36

400

4

27

185

4

µs

4K-Word Parameter Block

Erase Time

-

0.3

0.2

s

32K-Word Main Block

Erase Time

2

4

0.6

80

5

0.5

65

5

s

Full Chip Erase Time

700

10

700

10

t_WHRH1

t_EHRH1

t_WHRH2

t_EHRH2

/

(Page Buffer) Program Suspend

Latency Time to Read

-

µs

/

Block Erase Suspend

Latency Time to Read

4

5

20

5

20

µs

Latency Time from Block Erase

Resume Command to Block

Erase Suspend Command

t_ERES

-

500

NOTES:

1. Typical values measured at V_CC=3.0V, V_PP=3.0V or 12V, and T_A=+25°C. Assumes corresponding lock bits

are not set. Subject to change based on device characterization.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".

5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter

than t_ERESand its sequence is repeated, the block erase operation may not be finished.

Rev. 2.44

LHF64FB7

30

2 Related Document Information⁽¹⁾

Document No.

FUM00701

Document Name

LH28F640BF series Appendix

NOTE:

1. International customers should contact their local SHARP or distribution sales offices.

Rev. 2.44


型号：	LH28F640BFB-PBTL60
厂家：	ETC
描述：	Flash ROM 闪存可编程性闪存
文件：	总38页 (文件大小：935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LH28F640BFB-PBTL60 [ETC]

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