LM4851IBL-1 [ETC]
Amplifier. Other ; 功放。其他\n
| 型号： | LM4851IBL-1 |
| 厂家： | 
ETC |
| 描述： | Amplifier. Other
|
| 文件： | 总16页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
June 2002
LM4851
Integrated Audio Amplifier System
General Description
Features
n Mono 1W (typ) and stereo 100mW (typ) output
The LM4851 is an audio power amplifier system capable of
delivering 1W (typ) of continuous average power into a mono
8Ω bridged-tied load (BTL) with 1% THD+N and 100mW
(typ) per channel of continuous average power into stereo
32Ω BTL loads with 0.5% THD+N, using a 5V power supply.
n SPI programmable 32 step digital volume control
(-40.5dB to +6dB)
n Eight distinct SPI programmable output modes
n micro-SMD surface mount packaging
n “Click and pop” suppression circuitry
n No bootstrap capacitors required
n Thermal shutdown protection
The LM4851 features a 32 step digital volume control and
eight distinct output modes. The digital volume control and
output modes are programmed through a three-wire SPI
serial control interface.
n 0dB power-up volume
n Low shutdown current
Key Specifications
n THD+N at 1kHz, 1W into 8Ω BTL
n THD+N at 1kHz, 100mW into 32Ω BTL
n Single Supply Operation
1% (typ)
0.5% (typ)
3.0 to 5.0V
Applications
n Mobile phones
n PDAs
Typical Application
20040831
FIGURE 1. Typical Audio Amplifier Application Circuit
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2002 National Semiconductor Corporation
DS200408
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Connection Diagrams
18-Bump micro SMD Marking
200408A5
Top View
XY- Date Code
TT - Die Traceability
G - Boomer Family
52 - LM4851IBL-1
20040829
NC = NO CONNECT
Top View
18-Bump micro SMD
200408A7
Top View
Order Number LM4851LQ
See NS Package Number LQA24A for Exposed-DAP LLP
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2
Absolute Maximum Ratings (Note 2)
Thermal Resistance
θJA (typ) - LQA24A
θJC (typ) - LQA24A
θJA (typ) - BLA18AAB
θJC (typ) - BLA18AAB
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
42˚C/W
3.0˚C/W
Supply Voltage
6.0V
−65˚C to +150˚C
2.0kV
48˚C/W (Note 9)
23˚C/W (Note 9)
Storage Temperature
ESD Susceptibility (Note 4)
ESD Machine model (Note 7)
Junction Temperature (TJ)
Solder Information (Note 1)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
100V
Operating Ratings (Note 3)
Temperature Range
150˚C
−40˚C to 85˚C
Supply Voltage VDD
3.0V ≤ VDD ≤ 5.0V
Note 1: See AN-450 ’Surface Mounting and their effects on Product Reliabil-
ity’ for other methods of soldering surface mount devices.
215˚C
220˚C
Electrical Characteristics (Notes 2, 8)
The following specifications apply for VDD= 5.0V, TA= 25˚C unless otherwise specified.
Symbol Parameter Conditions
LM4851
Units
(Limits)
Typical
Limit
(Note 5)
7.5
(Note 6)
Output mode 7
14
mA
mA
VIN = 0V; IO = 0A
IDD
Supply Current
Output modes 1, 2, 3, 4, 5, 6
VIN = 0V; IO = 0A
5.0
9.0
IDD
Shutdown Current
Output mode 0
0.1
5.0
1.0
2
µA
mV
VOS
Output Offset Voltage
VIN = 0V
50
0.8
SPKROUT; RL = 8Ω
W (min)
THD+N = 1%; f = 1kHz
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
ROUT and LOUT; f = 1kHz
POUT = 100mW; RL = 32Ω
SPKROUT; f = 1kHz
PO
Output Power
100
80
0.5
1.0
mW (min)
% (max)
% (max)
%
THD+N
Total Harmonic Distortion Plus
Noise
POUT = 800mW; RL = 8Ω
ROUT and LOUT; f = 20Hz to 20kHz
POUT = 100mW; RL = 32Ω
SPKROUT; f = 20Hz to 20kHz
POUT = 800mW; RL = 8Ω
A-weighted; f = 1kHz
0.3
0.3
%
SNR
Signal to Noise Ratio
90
70
dB
dB
PSRR
Power Supply Rejection Ratio
VRIPPLE = 200mVPP; f = 217Hz
Input floating; Input referred
VRIPPLE = 200mVPP; f = 217Hz
Input terminated into 50Ω; Output referred
62
dB
VIH
Logic High Input Voltage
1.4
5.0
V (min)
V (max)
3
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Electrical Characteristics (Notes 2, 8) (Continued)
The following specifications apply for VDD= 5.0V, TA= 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4851
Units
(Limits)
Typical
Limit
(Note 5)
(Note 6)
VIL
Logic Low Input Voltage
0.4
V (max)
dBdB
Digital Volume Range (RIN and
Input referred minimum gain
Input referred maximum gain
-40.5
+6
LRIN
)
Digital Volume Stepsize
Stepsize Error
1.5
0.5
6
dB
dB
dB
Phone In Volume
BTL gain from
Phone In to SPKROUT
BTL gain from
Phone In Volume
Phone In Input Impedance
RIN and LIN
0
dB
Phone In to ROUT,LOUT
20
50
15
25
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
(min)
37.5
62.5
20
tES
tEH
tEL
Enable Setup Time (ENB)
Enable Hold Time (ENB)
Enable Low Time (ENB)
Data Setup Time (DATA)
Data Hold Time (DATA)
Clock Setup Time (CLK)
Clock Logic High Time (CLK)
Clock Logic Low Time (CLK)
Clock Frequency
20
30
tDS
tDH
tCS
tCH
tCL
tCLK
20
20
20
50
50
DC
10
MHz (max)
Electrical Characteristics (Notes 2, 8)
The following specifications apply for VDD= 3.0V, TA= 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4851
Units
(Limits)
Typical
Limit
(Note 5)
(Note 6)
Output mode 7
6.2
4.0
11
mA
mA
VIN = 0V; IO = 0A
IDD
Supply Current
Output modes 1, 2, 3, 4, 5, 6
VIN = 0V; IO = 0A
7.0
IDD
Shutdown Current
Output mode 0
0.1
5.0
340
2
µA
mV
VOS
Output Offset Voltage
VIN = 0V
50
SPKROUT; RL = 8Ω
THD+N = 1%; f = 1kHz
ROUT and LOUT; RL = 32Ω
THD+N = 0.5%; f = 1kHz
300
mW (min)
PO
Output Power
25
20
mW (min)
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4
Electrical Characteristics (Notes 2, 8) (Continued)
The following specifications apply for VDD= 3.0V, TA= 25˚C unless otherwise specified.
Symbol
Parameter
Conditions
LM4851
Units
(Limits)
Typical
Limit
(Note 5)
(Note 6)
THD+N
Total Harmonic Distortion Plus
Noise
ROUT and LOUT; f = 1kHz
0.5
1.0
% (max)
% (max)
%
POUT = 20mW; RL = 32Ω
SPKROUT; f = 1kHz
POUT = 300mW; RL = 8Ω
ROUT and LOUT; f = 20Hz to 20kHz
POUT = 20mW; RL = 32Ω
0.4
0.3
SPKROUT; f = 20Hz to 20kHz
POUT = 250mW; RL = 8Ω
%
SNR
Signal to Noise Ratio
A-weighted; f = 1kHz
90
70
dB
dB
PSRR
Power Supply Rejection Ratio
VRIPPLE = 200mVPP; f = 217Hz
Input floating; Input referred
VRIPPLE = 200mVPP; f = 217Hz
Input terminated into 50Ω; Output referred
62
dB
VIH
VIL
Logic High Input Voltage
1.4
3.0
0.4
V (min)
V (max)
V (max)
dBdB
Logic Low Input Voltage
Digital Volume Range (RIN and
Input referred minimum gain
Input referred maximum gain
-40.5
+6
LRIN
)
Digital Volume Stepsize
Stepsize Error
1.5
0.5
6
dB
dB
dB
Phone In Volume
BTL gain from
Phone In to SPKROUT
BTL gain from
Phone In Volume
Phone In Input Impedance
RIN and LIN
0
dB
Phone In to ROUT,LOUT
20
50
15
25
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
(min)
37.5
62.5
20
tES
tEH
tEL
Enable Setup Time (ENB)
Enable Hold Time (ENB)
Enable Low Time (ENB)
Data Setup Time (DATA)
Data Hold Time (DATA)
Clock Setup Time (CLK)
Clock Logic High Time (CLK)
Clock Logic Low Time (CLK)
Clock Frequency
20
30
tDS
tDH
tCS
tCH
tCL
tCLK
20
20
20
50
50
DC
10
MHz (max)
Note 2: Absolute Maximum Rating indicate limits beyond which damage to the device may occur.
Note 3: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor.
Note 5: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 6: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 7: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50Ω).
Note 8: All voltages are measured with respect to the ground pin, unless otherwise specified.
2
Note 9: The given θ and θ is for an LM4851 mounted on a demonstration board with a 4 in area of 1oz printed circuit board copper ground plane.
JA
JC
5
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External Components Description
(Refer to Figure 1.)
Components
Functional Description
1.
Cin
This is the input coupling capacitor. It blocks the DC voltage at, and couples the the input signal to, the
amplifier’s input terminals. Ci, also creates a highpass filter with the internal resistor Ri at fc = 1/(2πRiCi).
This is the supply bypass capacitor. It provides power supply filtering.
2.
3.
Cs
CB
This is the BYPASS pin capacitor. It provides half-supply filtering.
Typical Performance Characteristics
THD+N vs Frequency
THD+N vs Frequency
20040863
20040864
THD+N vs Frequency
THD+N vs Frequency
20040865
20040866
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6
Typical Performance Characteristics (Continued)
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Output Power
THD+N vs Output Power
20040867
20040868
THD+N vs Output Power
20040839
20040840
THD+N vs Output Power
20040841
20040842
7
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Typical Performance Characteristics (Continued)
THD+N vs Output Power
THD+N vs Output Power
20040843
20040844
20040874
20040861
Power Supply Rejection Ratio
Power Supply Rejection Ratio
20040845
Power Supply Rejection Ratio
Power Supply Rejection Ratio
20040860
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8
Typical Performance Characteristics (Continued)
Power Supply Rejection Ratio
Power Supply Rejection Ratio
20040862
20040859
Output Power vs Supply Voltage
Output Power vs Supply Voltage
20040846
20040847
Output Power
Output Power vs Supply Voltage
vs Load Resistance
20040849
20040848
9
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Typical Performance Characteristics (Continued)
Output Power
vs Load Resistance
Power Dissipation
vs Output Power
20040869
20040871
Power Dissipation
vs Output Power
Supply Current
vs Supply Voltage
20040872
20040855
Channel Separation
vs Frequency
200408A6
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10
Application Information
SPI pin Description
the data bits are written to the DATA pin with the least
significant bit (LSB) first. All serial data are sampled at the
rising edge of the CLK signal. Once all the data bits have
been sampled, ENB transitions from logic-high to logic-low
to complete the SPI sequence. All 8 bits must be received
before any data latch can occur. Any excess CLK and DATA
transitions will be ignored after the eighth rising clock edge
has occurred. For any data sequence longer than 8 bits, only
the first 8 bits will get loaded into the shift register and the
rest of the bits will be disregarded.
DATA: This is the serial data input pin.
CLK: This is the click input pin.
ENB: This is the SPI enable pin and is active-high.
SPI Operation Description
The serial data bits are organized into a field which contains
8 bits of data defined by TABLE 1. The Data 0 to Data 2 bits
determine the output mode of the LM4851 as shown in
TABLE 2. The Data 3 to Data 7 bits determine the volume
level setting as illustrated by TABLE 3. For each SPI transfer,
TABLE 1. Bit Allocation
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Mode 1
Mode 2
Mode 3
Volume 1
Volume 2
Volume 3
Volume 4
Volume 5
TABLE 2. Output Mode Selection
Output Mode #
Data 2
Data 1
Data 0
SPKROUT
SD
ROUT
SD
SD
P
LOUT
SD
SD
P
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
P
SD
R+L
SD
SD
R
SD
L
R+L+P
R+P
P
SD
R+P
R+P
SD
L+P
L+P
(P= Phone Input R = Rin L = Lin SD = Shutdown Power-Up
Mode = Output Mode 0)
11
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Application Information (Continued)
TABLE 3. Volume Control Settings
Gain (dB)
-40.5
-39.0
-37.5
-36.0
-34.5
-33.0
-31.5
-30.0
-28.5
-27.0
-25.5
-24.0
-22.5
-21.0
-19.5
-18.0
-16.5
-15.0
-13.5
-12.0
-10.5
-9.0
Data 7
Data 6
Data 5
Data 4
Data 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-7.5
-6.0
-4.5
-3.0
-1.5
0.0
1.5
3.0
4.5
6.0
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12
6. ENB must be logic-high at least 20ns (tES ) before the first
rising edge of CLK, and ENB has to remain logic-high at
least 20ns (tEH) after the eighth rising edge of CLK.
Application Information (Continued)
SPI Operational Requirements
1. The data bits are transmitted with the LSB first.
2. The maximum clock rate is 10MHz for the CLK pin.
7. If ENB remains logic-low for more than 10ns before all 8
bits are transmitted then the data latch will be aborted.
8. If ENB is logic-high for more than 8 CLK pulses then only
the first 8 data bits will be latched and activated when ENB
transitions to logic-low.
3. CLK must remain logic-high for at least 50ns (tCH ) after
the rising edge of CLK, and CLK must remain logic-low for at
least 50ns (tCL) after the falling edge of CLK.
9. ENB must remain logic-low for at least 30ns (tEL ) to latch
in the data.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 20ns (tDS) before
the rising edge of CLK. Also, any transition on DATA must
occur at least 20ns (tDH) after the rising edge of CLK and
stabilize before the next rising edge of CLK.
10. Coincidental rising or falling edges of CLK and ENB are
not allowed. If CLK is to be held logic-high after the data
transmission, the falling edge of CLK must occur at least
20ns (tCS) before ENB transitions to logic-high for the next
set of data.
5. ENB should be logic-high only during serial data transmis-
sion.
20040850
FIGURE 2. SPI Timing Diagram
13
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Demonstration Board Layout
200408A1
200408A2
Top Silkscreen
Figure 3.
Top Layer
Figure 4.
200408A4
200408A3
Bottom Layer
Figure 6.
Middle Layer
Figure 5.
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14
Physical Dimensions inches (millimeters) unless otherwise noted
18-Bump micro SMD
Order Number LM4851IBL-1
NS Package Number BLA18AAB
X1 = 1.996 X2 = 2.225 X3 = 0.795
15
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead MOLDED PKG, Leadless Leadframe Package LLP
Order Number LM4851LQ
NS Package Number LQA24A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
Email: support@nsc.com
Email: europe.support@nsc.com
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English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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