LV9001 [ETC]
TLV900x Low-Power, Rail-to-Rail In and Out, 1-MHz Operational Amplifier;
| 型号： | LV9001 |
| 厂家： | 
ETC |
| 描述： | TLV900x Low-Power, Rail-to-Rail In and Out, 1-MHz Operational Amplifier |
| 文件： | 总29页 (文件大小：1339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV9001, TLV9002, TLV9004
SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
TLV900x Low-Power, Rail-to-Rail In and Out, 1-MHz Operational Amplifier
1 Features
3 Description
The TLV900x family includes single- (TLV9001), dual-
(TLV9002) and quad-channel (TLV9004), low-voltage
(1.8 V to 5.5 V) operational amplifiers (op amps) with
rail-to-rail input and output swing capabilities. These
op amps provide a cost-effective solution for space-
constrained applications, such as smoke detectors,
wearable electronics, and small appliances, where
low-voltage operation and high capacitive-load drive
are required. The capacitive-load drive of the
TLV900x family is 500 pF, and the resistive open-
loop output impedance makes it easy to stabilize with
much higher capacitive loads. These op amps are
designed specifically for low-voltage operation (1.8 V
to 5.5 V) with performance specifications similar to
the TLV600x devices.
1
•
Rail-to-Rail Input and Output
Low Input Offset Voltage: ±0.4 mV
Unity-Gain Bandwidth: 1 MHz
Low Broadband Noise: 27 nV/√Hz
Low Input Bias Current: 5 pA
Low Quiescent Current: 60 µA/Ch
Unity-Gain Stable
•
•
•
•
•
•
•
•
•
Internal RFI and EMI Filter
Operational at Supply Voltages as Low as 1.8 V
Easier to Stabilize With Higher Capacitive Load
Due to Resistive Open-Loop Output Impedance
•
Extended Temperature Range: –40°C to +125°C
The robust design of the TLV900x family simplifies
circuit design. The op amps feature unity-gain
stability, an integrated RFI and EMI rejection filter,
and no-phase reversal in overdrive condition.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Smoke Detectors
Motion Detectors
Micro-size packages, such as SOT-553 and WSON,
are offered for all channel variants (single, dual, and
quad), along with industry-standard packages, such
as SOIC, MSOP, SOT-23 and TSSOP packages.
Wearable Devices
Large and Small Appliances
EPOS
Barcode Scanners
Device Information(1)
Sensor Signal Conditioning
Power Modules
PART NUMBER
PACKAGE
BODY SIZE (NOM)
1.60 mm × 2.90 mm
1.25 mm × 2.00 mm
1.65 mm x 1.20 mm
3.91 mm × 4.90 mm
3.91 mm × 4.90 mm
2.00 mm x 2.00 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
4.40 mm × 5.00 mm
SOT-23 (5)
Personal Electronics
Active Filters
SC70 (5)
TLV9001
SOT-553 (5)
SOIC (8)
HVAC: Heating, Ventilating, and Air Conditioning
Motor Control: AC Induction
Low-Side Current Sensing
SOIC (8)
TLV9002
TLV9004
WSON (8)
VSSOP (8)
SOIC (14)
TSSOP (14)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Single-Pole, Low-Pass Filter
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
1 + sR1C1
=
1 +
(
(
RG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9001, TLV9002, TLV9004
SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information: TLV9002 ................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Typical Characteristics.............................................. 9
Detailed Description ............................................ 15
7.1 Overview ................................................................. 15
7.2 Functional Block Diagram ....................................... 15
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
Power Supply Recommendations...................... 21
9.1 Input and ESD Protection ....................................... 21
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 Device and Documentation Support ................. 23
11.1 Documentation Support ........................................ 23
11.2 Related Links ........................................................ 23
11.3 Receiving Notification of Documentation Updates 23
11.4 Community Resources.......................................... 23
11.5 Trademarks........................................................... 23
11.6 Electrostatic Discharge Caution............................ 23
11.7 Glossary................................................................ 23
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2017) to Revision A
Page
•
Changed device status from Advance Information to Production Data ................................................................................. 1
2
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Product Folder Links: TLV9001 TLV9002 TLV9004
TLV9001, TLV9002, TLV9004
www.ti.com
SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
5 Pin Configuration and Functions
TLV9001 DBV and DRL Package
5-Pin SOT-23 and SOT-553
Top View
TLV9001 DCK Package
5-Pin SC70
Top View
OUT
V-
1
2
3
5
4
V+
+IN
V-
1
2
3
5
4
V+
+IN
-IN
-IN
OUT
TLV9001 D Package
8-Pin SOIC
Top View
NC(1)
-IN
+IN
V-
1
8
7
6
5
NC(1)
V+
2
3
4
OUT
NC(1)
NC - No internal connection
Pin Functions: TLV9001
PIN
I/O
DESCRIPTION
NAME
–IN
DBV, DRL
DCK
D
4
3
3
1
2
I
Inverting input
Noninverting input
Output
+IN
OUT
NC
3
I
1
4
6
O
—
—
—
—
2
—
2
1, 5, 8
No internal connection
V–
4
7
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
5
5
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TLV9001, TLV9002, TLV9004
SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
www.ti.com
TLV9002 D, DGK Packages
8-Pin SOIC, VSSOP
Top View
OUT A
1
2
3
4
8
7
6
5
V+
-IN A
+IN A
V-
OUT B
-IN B
+IN B
TLV9002 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
8
7
6
5
V+
OUT A
-IN A
+IN A
V-
1
2
3
4
Exposed
Thermal
Die Pad
on
OUT B
-IN B
+IN B
Underside(1)
(1) Connect thermal pad to V–
Pin Functions: TLV9002
PIN
I/O
DESCRIPTION
NAME
NO.
2
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
6
I
5
I
1
O
O
—
—
7
Output, channel B
4
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
8
4
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TLV9001, TLV9002, TLV9004
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SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
TLV9004 D, PW Packages
14-Pin SOIC, TSSOP
Top View
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
A
D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
B
C
OUT C
Pin Functions: TLV9004
PIN
I/O
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
OUT A
OUT B
OUT C
OUT D
V–
NO.
2
I
I
Inverting input, channel A
3
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
Output, channel A
6
I
5
I
9
I
10
13
12
1
I
I
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
11
4
Output, channel D
Negative (lowest) supply or ground (for single-supply operation)
Positive (highest) supply
V+
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TLV9001, TLV9002, TLV9004
SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
Supply voltage ([V+] – [V–])
6
(V+) + 0.5
(V+) – (V–) + 0.2
10
Common-mode
Voltage(2)
(V–) – 0.5
V
Signal input pins
Differential
V
Current(2)
–10
–55
–65
mA
mA
°C
°C
°C
Output short-circuit(3)
Operating, TA
Junction, TJ
Continuous
150
150
150
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
VS
TA
Supply voltage
1.8
Specified temperature
–40
125
°C
6.4 Thermal Information: TLV9002
TLV9002
THERMAL METRIC(1)
D (SOIC)
8 PINS
147.4
94.3
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
89.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
47.3
ψJB
89
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.
6
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SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
6.5 Electrical Characteristics
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Vs = 5 V
±0.4
±1.6
±2
mV
mV
VOS
Input offset voltage
Vs = 5 V, TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT
PSRR
VOS vs temperature
±0.6
105
μV/°C
dB
Power-supply rejection ratio
VS = 1.8 to 5.5 V, VCM = (V–)
80
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
No phase reversal, rail-to-rail input
(V–) – 0.1
(V+) + 0.1
V
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA
–40°C to 125°C
=
=
=
86
95
77
68
dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V, TA
–40°C to 125°C
dB
dB
dB
CMRR
Common-mode rejection ratio
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V, TA
–40°C to 125°C
63
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+)+ 0.1 V, TA
–40°C to 125°C
=
INPUT BIAS CURRENT
IB
Input bias current
Vs = 5 V
±5
±2
pA
pA
IOS
Input offset current
NOISE
En
Input voltage noise (peak-to-peak)
Input voltage noise density
Input current noise density
ƒ = 0.1 Hz to 10 Hz, Vs = 5 V
ƒ = 1 kHz, Vs = 5 V
4.7
30
27
23
μVPP
nV/√Hz
nV/√Hz
fA/√Hz
en
ƒ = 10 kHz, Vs = 5 V
ƒ = 1 kHz, Vs = 5 V
in
INPUT CAPACITANCE
CID
CIC
Differential
1.5
5
pF
pF
Common-mode
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V, RL = 10
kΩ
104
117
dB
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V, RL = 10
kΩ
100
115
130
dB
dB
dB
AOL
Open-loop voltage gain
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V, RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V, RL = 2
kΩ
FREQUENCY RESPONSE
GBW
φm
Gain-bandwidth product
Vs = 5 V
1
78
MHz
degrees
V/µs
μs
Phase margin
Slew rate
VS = 5.5 V, G = 1
SR
Vs = 5 V
2
To 0.1%, VS = 5 V, 2 V Step , G = +1, CL = 100 pF
To 0.01%, VS = 5 V, 2 V Step , G = +1, CL = 100 pF
VS = 5 V, VIN × gain > VS
2.5
3
tS
Settling time
μs
tOR
Overload recovery time
0.85
μs
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1
kHz, 80 kHz measurement BW
THD+N
OUTPUT
Total harmonic distortion + noise
0.004
%
VS = 5.5 V, RL = 10 kΩ
VS = 5.5 V, RL = 2 kΩ
Vs = 5.5 V
10
35
20
55
mV
mV
mA
Ω
VO
Voltage output swing from supply rails
ISC
ZO
Short-circuit current
±40
1200
Open-loop output impedance
Vs = 5 V, f = 1 MHz
POWER SUPPLY
VS
Specified voltage range
1.8 (±0.9)
5.5 (±2.75)
V
IO = 0 mA, VS = 5.5 V
60
75
85
µA
µA
IQ
Quiescent current per amplifier
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
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SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
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Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25 °C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS /
2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VS = 0 V to 5 V, to 90% IQ level
MIN
TYP
MAX
UNIT
Power-on time
50
µs
8
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SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
6.6 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
40
35
30
25
20
15
10
5
25
20
15
10
5
0
0
-
1200 -900 -600 -300
0
300 600 900 1200 1500 1800
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
D001
Offset Voltage (μV)
D002
Offset Voltage Drift (μV/°C)
VS = 5 V
VS = 5 V, TA = –40°C to 125°C
Figure 1. Offset Voltage Distribution Histogram
Figure 2. Offset Voltage Drift Distribution Histogram
1000
800
2000
1500
1000
500
600
400
200
0
0
-200
-400
-600
-800
-1000
-500
-1000
-1500
-2000
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-4
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
4
D003
D004
Figure 3. Input Offset Voltage vs Temperature
Figure 4. Offset Voltage vs Common-Mode
1000
6
4
IB-
IB+
IOS
800
600
2
400
0
200
-2
-4
-6
-8
-10
0
-200
-400
-600
-800
-1000
-40
-20
0
20
40
60
80
100 120 140
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Temperature (èC)
Supply Voltage (V)
D006
D005
Figure 6. IB and IOS vs Temperature
Figure 5. Offset Voltage vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
160
140
120
100
80
3.5
3
IB-
IB+
IOS
2.5
2
1.5
1
0.5
0
60
-0.5
-1
40
-1.5
-2
20
VS = 5.5 V
VS = 1.8 V
-2.5
0
-3
-2
-1
0
1
2
3
-40
-20
0
20
40
60
80
100 120 140
Common-Mode Voltage (V)
Temperature (èC)
D007
D008
Figure 7. IB and IOS vs Common-Mode Voltage
Figure 8. Open-Loop Gain vs Temperature
100
120
160
140
120
100
80
80
60
40
20
0
100
80
60
40
20
0
60
40
20
Gain
Phase
0
-20
-3
-2
-1 0
Output Voltage (V)
1
2
3
1k
10k
100k
Frequency (Hz)
1M
D010
D009
CL = 10 pF
Figure 10. Open-Loop Gain vs Output Voltage
Figure 9. Open-Loop Gain and Phase vs Frequency
3
2.5
2
80
70
60
50
40
30
20
10
0
Gain = -1
Gain = 1
Gain = 10
Gain = 100
Gain = 1000
1.5
1
125°C
85°C
25°C
-40°C
0.5
0
-0.5
-1
85°C
25°C
-40°C
-1.5
-2
125°C
-10
-20
-2.5
-3
100
1k
10k
100k
1M
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
Frequency (Hz)
D011
D012
CL = 10 pF
Figure 11. Closed-Loop Gain vs Frequency
Figure 12. Output Voltage vs Output Current (Claw)
10
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SBOS833A –OCTOBER 2017–REVISED DECEMBER 2017
Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
120
100
80
60
40
20
0
120
100
80
60
40
20
0
PSRR+
PSRR-
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
100k
1M
Temperature (èC)
Frequency (Hz)
D014
D013
VS = 1.8 V to 5.5 V
Figure 14. DC PSRR vs Temperature
Figure 13. PSRR vs Frequency
160
140
120
100
80
120
100
80
60
40
20
0
60
40
20
VS = 1.8 V
VS = 5.5 V
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
100k
1M
Temperature (èC)
Frequency (Hz)
D016
D015
VCM = (V–) – 0.1 V to
(V+) – 1.4 V
Figure 15. CMRR vs Frequency
Figure 16. DC CMRR vs Temperature
120
100
80
60
40
20
0
Time (1 s/div)
10
100
1k
10k
100k
D017
Frequency (Hz)
D018
Figure 17. 0.1 Hz to 10 Hz Integrated Voltage Noise
Figure 18. Input Voltage Noise Spectral Density
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Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
-50
-60
0
-20
G = +1, RL = 2 kW
G = +1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 10 kW
-70
-40
-80
-60
-90
-80
RL = 2K
RL = 10K
-100
-100
100
1k
10k
0.001
0.01
0.1
1
2
Frequency (Hz)
Amplitude (VRMS)
D019
D020
VS = 5.5 V, VCM = 2.5 V, G = 1, BW = 80 kHz, VOUT = 0.5 VRMS
VS = 5.5 V, VCM = 2.5 V, f = 1 kHz, G = 1, BW = 80 kHz
Figure 19. THD + N vs Frequency
Figure 20. THD + N vs Amplitude
70
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100 120 140
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (èC)
Voltage Supply (V)
D022
D021
Figure 22. Quiescent Current vs Temperature
Figure 21. Quiescent Current vs Supply Voltage
50
2000
45
40
35
30
25
20
15
10
5
1800
1600
1400
1200
1000
800
600
400
200
0
Overshoot (+)
Overshoot (–)
0
1k
10k
100k
Frequency (Hz)
1M
10M
0
200
400 600
Capacitance Load (pF)
800
1000
D023
D024
G = 1, VIN = 100 mVpp
Figure 23. Open-Loop Output Impedance vs Frequency
Figure 24. Small Signal Overshoot vs Capacitive Load
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Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
50
45
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
Overshoot (+)
Overshoot (–)
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400
600
800
1000
Capacitance Load (pF)
D025
D026
G = –1, VIN = 100 mVpp
Figure 25. Small Signal Overshoot vs Capacitive Load
Figure 26. Phase Margin vs Capacitive Load
VOUT
VIN
VOUT
VIN
Time (100 ms/div)
Time (20 ms/div)
D027
D028
G = 1, VIN = 6.5 VPP
G = –10, VIN = 600 mVPP
Figure 27. No Phase Reversal
Figure 28. Overload Recovery
VOUT
VIN
VOUT
VIN
Time (10 ms/div)
Time (10 ms/div)
D029
D030
G = 1, VIN = 100 mVPP , CL = 10 pF
G = 1, VIN = 4 VPP , CL = 10 pF
Figure 29. Small-Signal Step Response
Figure 30. Large-Signal Step Response
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Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Time (1 ms/div)
Time (1 μs/div)
D032
D031
G = 1, CL = 100 pF, 2-V step
G = 1, CL = 100 pF, 2-V step
Figure 32. Large-Signal Settling Time (Positive)
Figure 31. Large-Signal Settling Time (Negative)
80
60
6
5
4
3
2
1
0
VS = 5.5 V
VS = 1.8 V
40
20
0
-20
-40
-60
-80
Sinking
Sourcing
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D034
D033
Figure 34. Maximum Output Voltage vs Frequency
Figure 33. Short-Circuit Current vs Temperature
140
120
100
80
0
-20
-40
-60
60
-80
40
-100
-120
-140
20
0
10M
100M
Frequency (Hz)
1G
10G
1k
10k
100k
Frequency (Hz)
1M
10M
D035
D036
Figure 35. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
Figure 36. Channel Separation
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7 Detailed Description
7.1 Overview
The TLV900x series is a family of low-power, rail-to-rail input and output op amps. These devices operate from
1.8 V to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The
input common-mode voltage range includes both rails and allows the TLV900x series to be used in virtually any
single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in
low-supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).
7.2 Functional Block Diagram
V+
Reference
Current
VIN+
VIN–
VBIAS1
Class AB
Control
Circuitry
VO
VBIAS2
V–
(Ground)
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7.3 Feature Description
7.3.1 Operating Voltage
The TLV900x series of op amps are ensured for operation from 1.8 V to 5.5 V. In addition, many specifications
apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or temperature are
illustrated in the section.
7.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV900x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage: an
N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block
Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV
above the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative
supply to approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in
which both pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus, the
transition region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to
(V+) – 1 V to (V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift,
and THD can degrade compared to device operation outside this region.
7.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV900x series delivers a robust output drive
capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
7.3.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV900x series is approximately 850 ns.
7.4 Device Functional Modes
The TLV900x family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV900x is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed for
portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected
to any point between V+ and V–. The input common-mode voltage range includes both rails, and allows the
TLV900x to be used in any single-supply application.
8.2 Typical Application
8.2.1 TLV900x Low-Side, Current Sensing Application
Figure 37 shows the TLV900x configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5V
+
TLV9002
VOUT
Þ
+
RSHUNT
0.1 Ω
VSHUNT
RF
57.6 kΩ
Þ
RG
1.2 kΩ
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Figure 37. TLV900x in a Low-Side, Current-Sensing Application
8.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
8.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 37 is given in Equation 1:
VOUT = ILOAD ìRSHUNT ìGain
(1)
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Typical Application (continued)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using Equation 2:
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV900x to produce an output voltage of roughly 0 V to 4.9 V. The gain needed by the TLV900x
to produce the necessary output voltage is calculated using Equation 3:
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
is used to size the resistors, RF and RG, to set the gain of the TLV900x to 49 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Choosing RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 38 shows the
measured transfer function of the circuit shown in Figure 37.
8.2.1.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
Figure 38. Low-Side, Current-Sense, Transfer Function
8.2.2 Single-Supply Photodiode Amplifier
Photodiodes are used in many applications to convert light signals to electrical signals. The current through the
photodiode is proportional to the light energy applied to it and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal suitable for processing in an MCU. The circuit shown in
Figure 39 is an example single-supply photodiode amplifier circuit using the TLV9002.
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Typical Application (continued)
+3.3V
R1
11.5 kΩ
CF
10 pF
VREF
R2
357 Ω
RF
309 kΩ
+3.3V
œ
TLV9002
VOUT
+
VREF
CPD
47 pF
IIN
0-10 µA
RL
10 kꢀ
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Figure 39. Single-Supply Photodiode Amplifier Circuit
8.2.2.1 Design Requirements
The design requirements for this design are:
•
•
•
•
Supply Voltage: 3.3 V
Input: 0 µA to 10 µA
Output: 0.1 V to 3.2 V
Bandwidth: 50 kHz
8.2.2.2 Detailed Design Procedure
The transfer function between the output voltage, VOUT, the input current, IIN, and the reference voltage, VREF, is
defined in Equation 5.
VOUT = IIN ìRF + VREF
(5)
Where
≈
∆
«
’
÷
R1 ìR2
R1 + R2 ◊
VREF = V ì
+
(6)
Set VREF to 100mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
calculated in Equation 7.
VREF
0.1 V
3.3 V
=
= 0.0303
V+
(7)
The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω.
The required feedback resistance can be calculated based on the input current and desired output voltage.
VOUT - VREF
3.2 V - 0.1 V
10 mA
kV
A
RF =
=
= 310
ö 309 kW
I
IN
(8)
Calculate the value for the feedback capacitor based RF and the desired –3-dB bandwidth, f-3dB using
Equation 9.
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Typical Application (continued)
1
1
CF =
=
= 10.3 pF ö 10 pF
2ì pìRF ì f-3dB 2ì pì309 kWì50 kHz
(9)
The minimum op amp bandwidth required for this application is based on the value of RF, CF and the
capacitance on the IN– pin of the TLV9002 which is equal to the sum of the photodiode shunt capacitance, CPD,
the common-mode input capacitance CCM and the differential input capacitance CD as shown in Equation 10.
C
= CPD + CCM + CD = 47 pF+ 5 pF +1pF = 53 pF
IN
(10)
The minimum op amp bandwidth is calculated in Equation 11.
CIN + CF
f=BGW
í
í 324 kHz
2
2ì pìRF ì CF
(11)
The 1-MHz bandwidth of the TLV900x meets the minimum bandwidth requirement and remains stable in this
application configuration.
8.2.2.3 Application Curves
The measured current-to-voltage transfer function for photodiode amplifier circuit is shown in Figure 40. The
measured DC performance of the photodiode amplifier circuit is shown in Figure 41.
Figure 40. Photodiode Amplifier Circuit AC Gain Results
Figure 41. Photodiode Amplifier Circuit DC Results
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9 Power Supply Recommendations
The TLV900x series is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. The section presents parameters that may exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see the table.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
9.1 Input and ESD Protection
The TLV900x series incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10-
mA, as stated in the table. Figure 42 shows how a series input resistor can be added to the driven input to limit
the input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept
to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
Figure 42. Input Current Protection
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Ensure to physically separate digital and analog grounds, paying attention to the flow of the
ground current. For more detailed information, see Circuit Board Layout Techniques.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible, as shown in Figure 44. Keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly
reduce leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
Figure 43. Schematic Representation for Figure 44
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
VS+
GND
OUT A
V+
RF
OUT B
GND
-IN A
+IN A
Vœ
OUT B
-IN B
RF
RG
GND
VIN B
VIN A
RG
+IN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor. Place as
close to the device
as possible.
VSœ
Ground (GND) plane on another layer
as possible.
Figure 44. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
•
•
EMI Rejection Ratio of Operational Amplifiers.
Circuit Board Layout Techniques.
11.2 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV9001
TLV9002
TLV9004
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TLV9002IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
TL9002
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9002IDR
SOIC
D
8
2500
330.0
15.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jan-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
TLV9002IDR
D
8
2500
Pack Materials-Page 2
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