LXT388LE [ETC]
PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC ; PCM收发器|双| CEPT PCM - 30 / E - 1 | CMOS | QFP | 100PIN |塑料\n
| 型号： | LXT388LE |
| 厂家： | 
ETC |
| 描述： | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC
|
| 文件： | 总78页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LXT388
Dual T1/E1/J1 Transceiver
Datasheet
The LXT388 is a dual short haul Pulse Code Modulation (PCM) transceiver for use in both
1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four receivers and two
transmitters in a single LQFP-100 package.
The transmit drivers provide low impedance independent of the transmit pattern and supply
voltage variations. The LXT388 transmits shaped waveforms meeting G.703 and T1.102
specifications. The LXT388 meets the latest transmit return loss specifications, such as ETSI
ETS-300166.
The LXT388 differential receivers provide high noise margin for T1/E1 short-haul operation. In
addition, the LXT388 includes two extra receiver/jitter attenuation blocks that can be used for
Driver Performance Monitoring (DPM) in the active channels. These blocks can also be used to
provide jitter attenuation in the receive and transmit paths simultaneously.
Jitter attenuation performance meets the latest international specifications such as CTR12/13.
The jitter attenuator was optimized for Synchronous Optical NETwork/Synchronous Digital
Hierarchy (SONET/SDH) applications including a 32/64 bit FIFO and a second order DPLL.
The LXT388 includes Intel Hitless Protection Switching (Intel HPS) feature which helps
increase quality of service and eliminates relays in redundancy and 1+1 protection applications.
Fast tristate-able drivers and a constant delay jitter attenuator are critical to achieving Intel
HPS.
Applications
■ SONET/SDH tributary interfaces
■ Digital cross connects
■ Microwave transmission systems
■ M13, E1-E3 MUX
■ Public/private switching trunk line
interfaces
Product Features
■ Driver Performance Monitor (DPM)
■ Tx and Rx Jitter Attenuator
■ Intel HPS for 1 to 1 protection without
relays
■ HDB3, B8ZS, or AMI line encoder/decoder
■ Single rail 3.3V supply with 5V tolerant
inputs
■ Analog/digital and remote loopback testing
functions
■ Superior crystal-less jitter attenuator
■ LOS per ITU G.775, ETS 300 233 and
—Meets ETSI CTR12/13, ITU G.736,
G.742, G.823 and AT&T Pub 62411
specifications
T1.231
■ JTAG Boundary Scan test port per IEEE
1149.1
—Optimized for SONET/SDH
applications, meets ITU G.783 mapping
jitter specification
■ 100 pin LQFP package
■ Low power consumption of 150mW per
channel (typical)
—Constant throughput delay jitter
attenuator
As of January 15, 2001, this document replaces the Level One document
LXT388 — Dual T1/E1/J1 Transceiver.
Order Number: 249269-002
February 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT388 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Contents
1.0
2.0
Pin Assignments and Signal Description ......................................................10
Functional Description...........................................................................................21
2.1
2.2
Initialization..........................................................................................................21
2.1.1 Reset Operation .....................................................................................21
Receiver ..............................................................................................................22
2.2.1 Loss of Signal Detector ..........................................................................23
2.2.2 Alarm Indication Signal (AIS) Detection .................................................23
2.2.3 In Service Code Violation Monitoring .....................................................24
Transmitter ..........................................................................................................24
2.3.1 Transmit Pulse Shaping .........................................................................25
Line Protection ....................................................................................................26
Driver Failure Monitor..........................................................................................26
Driver Performance Monitor ................................................................................29
Jitter Attenuation .................................................................................................30
2.7.1 Transmit and Receive Jitter Attenuation ................................................31
Loopbacks...........................................................................................................32
2.8.1 Analog Loopback....................................................................................32
2.8.2 Digital Loopback.....................................................................................33
2.8.3 Remote Loopback ..................................................................................33
2.8.4 Transmit All Ones (TAOS)......................................................................34
Intel Hitless Protection Switching (Intel HPS)................................................35
Operation Mode Summary ..................................................................................35
Interfacing with 5V logic ......................................................................................36
Parallel Host Interface.........................................................................................36
2.12.1 Motorola Interface ..................................................................................37
2.12.2 Intel Interface..........................................................................................38
Interrupt Handling................................................................................................38
2.13.1 Interrupt Sources....................................................................................38
2.13.2 Interrupt Enable......................................................................................38
2.13.3 Interrupt Clear ........................................................................................38
Serial Host Mode.................................................................................................39
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.0
4.0
Register Descriptions.............................................................................................40
JTAG Boundary Scan.............................................................................................47
4.1
4.2
4.3
4.4
Overview .............................................................................................................47
Architecture .........................................................................................................47
TAP Controller.....................................................................................................47
JTAG Register Description..................................................................................49
4.4.1 Boundary Scan Register (BSR)..............................................................50
4.4.2 Device Identification Register (IDR) .......................................................52
4.4.3 Bypass Register (BYR) ..........................................................................52
4.4.4 Analog Port Scan Register (ASR) ..........................................................52
4.4.5 Instruction Register (IR) .........................................................................53
Datasheet
3
LXT388 — Dual T1/E1/J1 Transceiver
5.0
6.0
Test Specifications..................................................................................................55
5.1 Recommendations and Specifications................................................................77
Mechanical Specifications ...................................................................................78
Figures
1
2
LXT388 Block Diagram .........................................................................................9
LXT388 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and
Package Markings...............................................................................................10
Pullup Resistor to RESET ...................................................................................22
50% AMI Encoding..............................................................................................25
External Transmit/Receive Line Circuitry............................................................28
Driver Performance Monitoring ...........................................................................29
Jitter Attenuator Loop..........................................................................................31
Transmit and Receive Jitter Attenuation .............................................................32
Analog Loopback ................................................................................................33
Digital Loopback..................................................................................................33
Remote Loopback...............................................................................................34
TAOS Data Path .................................................................................................34
TAOS with Digital Loopback ...............................................................................35
TAOS with Analog Loopback ..............................................................................35
Serial Host Mode Timing.....................................................................................39
LXT388 JTAG Architecture .................................................................................47
JTAG State Diagram...........................................................................................49
Analog Test Port Application...............................................................................54
Transmit Clock Timing Diagram..........................................................................61
Receive Clock Timing Diagram...........................................................................62
JTAG Timing .......................................................................................................63
Non-Multiplexed Intel Mode Read Timing...........................................................64
Multiplexed Intel Read Timing.............................................................................65
Non-Multiplexed Intel Mode Write Timing ...........................................................66
Multiplexed Intel Mode Write Timing...................................................................67
Non-Multiplexed Motorola Mode Read Timing....................................................68
Multiplexed Motorola Mode Read Timing............................................................69
Non-Multiplexed Motorola Mode Write Timing....................................................70
Multiplexed Motorola Mode Write Timing............................................................71
Serial Input Timing ..............................................................................................72
Serial Output Timing ...........................................................................................72
E1, G.703 Mask Templates.................................................................................73
T1, T1.102 Mask Templates ...............................................................................74
Jitter Tolerance Performance..............................................................................75
Jitter Transfer Performance ................................................................................76
Output Jitter for CTR12/13 applications..............................................................77
Low Quad Flat Package (LQFP) Dimensions .....................................................78
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
4
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Tables
1
2
3
4
5
6
7
8
Assignments and Signal Descriptions - Power and N/C .....................................11
Pin Assignments and Signal Descriptions - Digital Interface...............................11
Pin Assignments and Signal Descriptions - Analog Interface .............................15
Pin Assignments and Signal Descriptions - JTAG Port.......................................15
Pin Assignments and Signal Descriptions - Microprocessor/Configuration.........16
Line Length Equalizer Inputs...............................................................................26
Jitter Attenuation Specifications ..........................................................................30
Operation Mode Summary ..................................................................................35
Microprocessor Parallel Interface Selection........................................................37
Serial and Parallel Port Register Addresses .......................................................40
Register Bit Names .............................................................................................40
ID Register, ID (00H)...........................................................................................41
Analog Loopback Register, ALOOP (01H)..........................................................42
Remote Loopback Register, RLOOP (02H) ........................................................42
TAOS Enable Register, TAOS (03H) ..................................................................42
LOS Status Monitor Register, LOS (04H) ...........................................................42
DFM Status Monitor Register, DFM (05H) ..........................................................42
LOS Interrupt Enable Register, LIE (06H)...........................................................43
DFM Interrupt Enable Register, DIE (07H)..........................................................43
LOS Interrupt Status Register, LIS (08H)............................................................43
DFM Interrupt Status Register, DIS (09H)...........................................................43
Software Reset Register, RES (0AH)..................................................................43
Reserved (0BH)...................................................................................................43
Digital Loopback Register, DL (0CH) ..................................................................44
LOS/AIS Criteria Register, LCS (0DH)................................................................44
Automatic TAOS Select Register, ATS (0EH).....................................................44
Global Control Register, GCR (0FH)...................................................................44
Pulse Shaping Indirect Address Register, PSIAD (10H).....................................45
Pulse Shaping Data Register, PSDAT (11H) ......................................................45
Output Enable Register, OER (12H) ...................................................................46
AIS Status Monitor Register, AIS (13H) ..............................................................46
AIS Interrupt Enable Register, AISIE (14H) ........................................................46
AIS Interrupt Status Register, AISIS (15H) .........................................................46
TAP State Description.........................................................................................48
Boundary Scan Register (BSR)...........................................................................50
Device Identification Register (IDR) ....................................................................52
Analog Port Scan Register (ASR) .......................................................................53
Instruction Register (IR) ......................................................................................53
Absolute Maximum Ratings.................................................................................55
Recommended Operating Conditions .................................................................55
DC Characteristics ..............................................................................................56
E1 Transmit Transmission Characteristics..........................................................57
E1 Receive Transmission Characteristics...........................................................57
T1 Transmit Transmission Characteristics..........................................................58
T1 Receive Transmission Characteristics...........................................................59
Jitter Attenuator Characteristics ..........................................................................60
Analog Test Port Characteristics.........................................................................61
Transmit Timing Characteristics..........................................................................61
Receive Timing Characteristics...........................................................................62
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Datasheet
5
LXT388 — Dual T1/E1/J1 Transceiver
50
51
52
53
54
55
56
58
57
Intel Mode Read Timing Characteristics .............................................................63
JTAG Timing Characteristics ..............................................................................63
Intel Mode Write Timing Characteristics .............................................................65
Motorola Bus Read Timing Characteristics.........................................................67
Motorola Mode Write Timing Characteristics ......................................................69
Serial I/O Timing Characteristics.........................................................................71
Transformer Specifications3 ................................................................................72
T1.102 1.544 Mbit/s Pulse Mask Specifications..................................................73
G.703 2.048 Mbit/s Pulse Mask Specifications...................................................73
6
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Revision History
Revision
Date
Description
-002
02/12/01
Figure 2, changed pin 70 from TCK to TDI.
Figure 2, changed pin 71 from GND to TCK.
Moved Product Features from page 9 to page 1.
Added Intel to page 1, 3, and 35.
Datasheet
7
LXT388 — Dual T1/E1/J1 Transceiver
8
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 1. LXT388 Block Diagram
MODE
JTAG
LOOP 0..3
SERIAL/
PARALLEL
PORT
HARDWARE / SOFTWARE CONTROL
JASEL
CLKE
MCLK
LOS
LOS
DATA SLICER
RTIP
RPOS
JITTER
CLOCK
ATTENUATOR
RX OR TX
PATH
B8ZS / HDB3
DECODER
RECOVERY
RCLK
RRING
TTIP
RNEG
LINE DRIVER
TPOS
JITTER
ATTENUATOR
RX OR TX
PATH
PULSE
SHAPER
B8ZS / HDB3
ENCODER
TCLK
TRING
TNEG
0
RTIP
1
LOS
LOS
DATA SLICER
RTIP
RPOS
JITTER
ATTENUATOR
RX OR TX
PATH
CLOCK
B8ZS / HDB3
DECODER
RECOVERY
RCLK
RRING
RNEG
TPOS
JITTER
ATTENUATOR
RX OR TX
PATH
B8ZS / HDB3
ENCODER
TCLK
TNEG
MONITORING / JA
2
3
Datasheet
9
LXT388 — Dual T1/E1/J1 Transceiver
1.0
Pin Assignments and Signal Description
Figure 2. LXT388 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and
Package Markings
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
VCC
MOT
1
GND
2
R / W
DS
TDO
3
TRST
TMS
4
VCC
5
GND
TDI
6
VCC
TCK
7
GND
VCC
8
VCC
VCC
9
VCC
GND
10
11
12
13
14
15
16
17
18
19
20
GND
GND
GND
TCLK2
TPOS2
TNEG2
RCLK2
RPOS2
RNEG2
LOS2
TCLK3
TPOS3
TNEG3
RCLK3
RPOS3
RNEG3
LOS3
TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
RNEG1
LOS1
TCLK0
TPOS0
TNEG0
RCLK0
RPOS0
RNEG0
LOS0
Rev #
LXT388LE XX
XXXXXX
XXXXXXXX
Part #
LOT #
FPO #
55
54
53
52
51
21
22
23
24
25
Package Topside Markings
Marking
Definition
Part #
Rev #
Lot #
Unique identifier for this product family.
Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information.
Identifies the batch.
FPO #
Identifies the Finish Process Order.
10
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 1. Assignments and Signal Descriptions - Power and N/C
Pin #
LQFP
Symbol
I/O1
Description
5, 7, 10,
11, 65, 66,
74
GND
VCC
S
S
S
Power Supply Ground. Connect all pins to power supply ground.
Power Supply. Connect all pins to +3.3 volt power supply
4, 6, 8, 9,
67, 68, 75,
Transmit Driver Power Supply. Power supply pins for the output drivers. TVCC pins can
be connected to either a 3.3V or 5V power supply. Refer to “Transmitter” on page 24 for
details.
-
TVCC
Transmit Driver Power Supply. Power supply pin for the port 0 output driver. TVCC pins
can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter
description.
26
TVCC0
S
29
32
TGND0
TGND1
S
S
Transmit Driver Ground. Ground pin for the output driver.
Transmit Driver Ground.
Transmit Driver Power Supply. Power supply pin for the port 1 output driver. TVCC pins
can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter
description.
35
38
TVCC1
S
Transmit Driver Power Supply. Power supply pin for the port 0 output driver. TVCC pins
can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter
description.
TVCC0
N/C
S
39
40
N/C
Not Connected. These pins must be left open for normal operation.
41
44
TGND2
TGND3
S
S
Transmit Driver Ground.
Transmit Driver Ground.
45
46
Not Connected. These pins must be left open for normal operation.
N/C
N/C
Transmit Driver Power Supply. Power supply pin for the port 1 output driver. TVCC pins
can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter
description.
47
TVCC1
N/C
S
50
NC
Not Connected. These pins must be left open for normal operation.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Table 2. Pin Assignments and Signal Descriptions - Digital Interface
Pin #
LQFP
Symbol
I/O1
Description
12
TCLK1
DI
Transmit Clock.
TPOS1/
TDATA1
DI
DI
Transmit Positive Data.
Transmit Data.
13
TNEG1/
UBS1
DI
DI
Transmit Negative Data.
Unipolar/Bipolar Select.
14
15
RCLK1
DO
Receive Clock.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Datasheet
11
LXT388 — Dual T1/E1/J1 Transceiver
Table 2. Pin Assignments and Signal Descriptions - Digital Interface (Continued)
Pin #
LQFP
Symbol
I/O1
Description
RPOS1/
RDATA1
DO
DO
Receive Positive Data.
Receive Data.
16
RNEG1/
BPV1
DO
DO
Receive Negative Data.
Bipolar Violation Detect.
17
18
LOS1
DO
Loss of Signal.
Transmit Clock. During normal operation TCLK is active, and TPOS and TNEG are
sampled on the falling edge of TCLK. If TCLK is Low, the output drivers enter a low power
high Z mode. If TCLK is High for more than 16 clock cycles the pulse shaping circuit is
disabled and the transmit output pulse widths are determined by the TPOS and TNEG
duty cycles.
TCLK
Operating Mode
Normal operation
Clocked
H
TAOS (if MCLK supplied)
Disable transmit pulse shaping (when
MCLK is not available)
19
TCLK0
DI
H
L
Driver outputs enter tri-state
When pulse shaping is disabled, it is possible to overheat and damage the LXT384
device by leaving transmit inputs high continuously. For example a programmable ASIC
might leave all outputs high until it is programmed. To prevent this clock one of these
signals: TPOS, TNEG, TCLK or MCLK. Another solution is to set one of these signals
low: TPOS, TNEG, TCLK, or OE.
Note that the TAOS generator uses MCLK as a timing reference. In order to assure that
the output frequency is within specification limits, MCLK must have the applicable
stability.
Transmit Positive Data.
Transmit Data.
Transmit Negative Data.
DI
DI
Unipolar/Bipolar Select.
TPOS0/
TDATA0
20
Bipolar Mode:
TPOS/TNEG are active high NRZ inputs. TPOS indicates the transmission of a positive
pulse whereas TNEG indicates the transmission of a negative pulse.
.
Unipolar Mode:
When TNEG/UBS is pulled High for more than 16 consecutive TCLK clock cycles,
unipolar I/O is selected. In unipolar mode, B8ZS/HDB3 or AMI encoding/decoding is
determined by the CODEN pin (hardware mode) or by the CODEN bit in the GCR register
(software mode).
TDATA is the data input in unipolar I/O mode.
TPOS
TNEG
Selection
TNEG0/
UBS0
DI
DI
21
0
1
0
1
0
0
1
1
Space
Positive Mark
Negative Mark
Space
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
12
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 2. Pin Assignments and Signal Descriptions - Digital Interface (Continued)
Pin #
LQFP
Symbol
I/O1
Description
Receive Clock.
Normal Mode:
This pin provides the recovered clock from the signal received at RTIP and RRING.
Under LOS conditions there is a transition from RCLK signal (derived from the recovered
data) to MCLK signal at the RCLK output.
22
RCLK0
DO
Data Recovery Mode:
If MCLK is High, the clock recovery circuit is disabled and RPOS and RNEG are internally
connected to an EXOR that is fed to the RCLK output for external clock recovery
applications.
RCLK will be in high impedance state if the MCLK pin is Low.
Receive Positive.
Receive Data.
Receive Negative Data.
Bipolar Violation Detect.
Bipolar Mode:
DO
DO
RPOS0/
RDATA0
23
In clock recovery mode these pins act as active high bipolar non return to zero (NRZ)
receive signal outputs. A High signal on RPOS corresponds to receipt of a positive pulse
on RTIP/RRING. A High signal on RNEG corresponds to receipt of a negative pulse on
RTIP/RRING. These signals are valid on the falling or rising edges of RCLK depending
on the CLKE input.
In Data recovery Mode these pins act as RZ data receiver outputs. The output polarity is
selectable with CLKE (Active High output polarity when CLKE is High and Active Low
Polarity when CLKE is Low).
RPOS and RNEG will go to the high impedance state when the MCLK pin is Low.
Unipolar Mode:
In uni-polar mode, the LXT388 asserts BPV High if any in-service Line Code Violation is
detected. RDATA acts as the receive data output.
RNEG0/
BPV0
DO
DO
24
25
Hardware Mode: During a LOS condition, RPOS and RNEG will remain active.
Host Mode: RPOS and RNEG will either remain active or insert AIS into the receive path.
Selection is determined by the RAISEN bit in the GCR register.
Loss of Signal. LOS goes High to indicate a loss of signal, i.e. when the incoming signal has
no transitions for a specified time interval. The LOS condition is cleared and the output pin
returns to Low when the incoming signal has sufficient number of transitions in a specified time
interval. see “Loss of Signal Detector” on page 23
LOS0
LOS3
DO
D
51
52
Loss of Signal.
DO
RNEG3/
BPV3
DO
DO
Receive Negative Data.
Bipolar Violation Detect.
RPOS3/
RDATA3
DO
DO
Receive Positive Data.
Receive Data.
53
54
55
RCLK3
DO
Receive Clock.
TNEG3/
UBS3
DI
DI
Transmit Negative Data.
Unipolar/Bipolar Select.
TPOS3/
TDATA3
DI
DI
Transmit Positive Data.
Transmit Data.
56
57
TCLK3
DI
Transmit Clock.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Datasheet
13
LXT388 — Dual T1/E1/J1 Transceiver
Table 2. Pin Assignments and Signal Descriptions - Digital Interface (Continued)
Pin #
LQFP
Symbol
I/O1
Description
58
LOS2
DO
Loss of Signal.
RNEG2/
BPV2
DO
DO
Receive Negative Data.
Bipolar Violation Detect.
59
RPOS2/
RDATA2
DO
DO
Receive Positive Data.
Receive Data.
60
61
62
RCLK2
DO
Receive Clock.
TNEG2/
UBS2
DI
DI
Transmit Negative Data.
Unipolar/Bipolar Select.
TPOS2/
TDATA2
DI
DI
Transmit Positive Data.
Transmit Data.
63
64
TCLK2
DI
Transmit Clock.
Master Clock. MCLK is an independent, free-running reference clock. It’s frequency
should be 1.544 MHz for T1 operation and 2.048 MHz for E1 operation.
This reference clock is used to generate several internal reference signals:
•
•
•
•
•
Timing reference for the integrated clock recovery unit
Timing reference for the integrated digital jitter attenuator
Generation of RCLK signal during a loss of signal condition
Reference clock during a blue alarm transmit all ones condition
Reference timing for the parallel processor wait state generation logic
78
MCLK
DI
If MCLK is High, the PLL clock recovery circuit is disabled. In this mode, the LXT388
operates as simple data receiver.
If MCLK is Low, the complete receive path is powered down and the output pins RCLK,
RPOS and RNEG are switched to Tri-state mode.
MCLK is not required if LXT388 is used as a simple analog front-end without clock
recovery and jitter attenuation.
Note that wait state generation via RDY/ACK is not available if MCLK is not provided.
Reset Input. (Added in Revision B1) In either hardware mode or software mode, setting
RESET low will begin to initialize the LXT388 and freeze the device until set high. One
microsecond after setting RESET high, initialization will complete and the LXT388 will be
ready for normal operation. Only revision B1 requires a pull up resistor to VCC at this pin
between 1 and 10 kohms in value. It is necessary to retain the pull up resistor for other
revisions. Please refer to the section on Reset Operation for more information.
100
RESET
DI
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
14
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 3. Pin Assignments and Signal Descriptions - Analog Interface
Pin #
LQFP
Symbol
I/O1
Description
Transmit Tip.
Transmit Ring.
27
28
TTIP0
AO
AO
These pins are differential line driver outputs. TTIP and TRING will be in high impedance
state if the TCLK pin is Low or the OE pin is Low. In software mode, TTIP and TRING can
be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output Enable
Register (OER).
TRING0
Receive Tip.
30
31
RTIP0
AI
AI
Receive Ring.
RRING0
These pins are the inputs to the differential line receiver. Data and clock are recovered
and output on the RPOS/RNEG and RCLK pins.
33
34
TRING1
TTIP1
AO
AO
Transmit Ring.
Transmit Tip.
36
37
RRING1
RTIP1
AI
AI
Receive Ring.
Receive Tip.
42
43
RTIP2
AI
AI
Receive TIP.
RRING2
Receive Ring.
48
49
RRING3
RTIP3
AI
AI
Receive Ring.
Receive Tip.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Table 4. Pin Assignments and Signal Descriptions - JTAG Port
Pin #
LQFP
Symbol
I/O1
Description
76
77
AT2
AT1
AO
AI
JTAG Analog Output Test Port 2.
JTAG Analog Input Test Port 1.
JTAG Controller Reset. Input is used to reset the JTAG controller. TRST is pulled up
internally and may be left disconnected.
72
TRST
JTAG Test Mode Select. Used to control the test logic state machine. Sampled on rising
edge of TCK. TMS is pulled up internally and may be left disconnected.
71
69
73
TMS
TCK
TDO
DI
DI
JTAG Clock. Clock input for JTAG. Connect to GND when not used.
JTAG Data Output. Test Data Output for JTAG. Used for reading all serial configuration
and test data from internal test logic. Updated on falling edge of TCK.
DO
JTAG Data Input. Test Data input for JTAG. Used for loading serial instructions and data
into internal test logic. Sampled on rising edge of TCK. TDI is pulled up internally and may
be left disconnected.
70
TDI
DI
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Datasheet
15
LXT388 — Dual T1/E1/J1 Transceiver
Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O1
Description
Motorola/Intel/Codec Enable Select.
Host Mode:
When Low, the host interface is configured for Motorola microcontrollers. When High, the
host interface is configured for Intel microcontrollers.
MOT/INTL/
CODEN
DI
DI
1
Hardware Mode:
This pin determines the line encode/decode selection when in unipolar mode:
When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1 respectively. When
High, enables AMI encoder/decoder (transparent mode).
Read/Write (Motorola Mode).
Read Enable (Intel mode).
Line Length Equalizer (Hardware Mode).
Host Mode
R / W/
RD/
DI
DI
DI
2
This pin functions as the read/write signal in Motorola mode and as the Read Enable in
Intel mode.
LEN1
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse. Refer to Table 6.
Data Strobe (Motorola Mode).
Write Enable (Intel mode).
Serial Data Input (Serial Mode).
Line Length Equalizer (Hardware Mode).
Host Mode
DS/
WR/
SDI/
LEN0
DI
DI
DI
DI
3
This pin acts as data strobe in Motorola mode and as Write Enable in Intel mode. In serial
mode this pin is used as Serial Data Input.
Hardware Mode
This pin determines the shape and amplitude of the transmit pulse. Refer to Table 6.
Mode Select. This pin is used to select the operating mode of the LXT386. In Hardware
Mode, the parallel processor interface is disabled and hardwired pins are used to control
configuration and report status.
In Parallel Host Mode, the parallel port interface pins are used to control configuration and
report status.
In Serial Host Mode the serial interface pins: SDI, SDO, SCLK and CS are used
79
MODE
DI
MODE
Operating Mode
Hardware Mode
L
H
Parallel Host Mode
Serial Host Mode
Vcc/2
For Serial Host Mode, the pin should connected to a resistive divider consisting of two 10
kΩ resistors across VCC and Ground.
Interrupt. This active Low, maskable, open drain output requires an external 10k pull up
resistor. If the corresponding interrupt enable bit is enabled, INT goes Low to flag the host
when the LXT388 changes state (see details in the interrupt handling section). The
microprocessor INT input should be set to level triggering.
80
INT
DO
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
16
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O1
Description
Data Transfer acknowledge (Motorola Mode).
Ready (Intel mode).
Serial Data Output (Serial Mode).
Motorola Mode
A Low signal during a databus read operation indicates that the information is valid. A
Low signal during a write operation acknowledges that a data transfer into the addressed
register has been accepted (acknowledge signal).Wait states only occur if a write cycle
immediately follows a previous read or write cycle (e.g. read modify write).
ACK/
RDY/
SDO
DO
DO
DO
81
Intel Mode
A High signal acknowledges that a register access operation has been completed (Ready
Signal). A Low signal on this pin signals that a data transfer operation is in progress. The
pin goes tristate after completion of a bus cycle.
Serial Mode
If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low, SDO is valid on
the falling edge of SCLK. This pin goes into high Z state during a serial port write access.
Address Latch Enable (Host Mode).
Shift Clock (Serial Mode).
Address Strobe (Motorola Mode).
Line Length Equalizer (Hardware Mode).
Host Mode
ALE/
SCLK/
AS/
DI
DI
DI
DI
The address on the multiplexed address/data bus is clocked into the device with the
falling edge of ALE.
82
In serial Host mode this pin acts as serial shift clock.
In Motorola mode this pin acts a an active Low address strobe.
Hardware Mode
LEN2
This pin determines the shape and amplitude of the transmit pulse in transceivers 0 and
1. It also determines the receiver setting (T1 or E1) in all the receivers. Please refer to
Table 6 on page 26.
Output Driver Enable. If this pin is asserted Low all analog driver outputs immediately
enter a high impedance mode to support redundancy applications without external
mechanical relays. All other internal circuitry stays active. In software mode, TTIP and
TRING can be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output
Enable Register (OER).
83
OE
DI
Clock Edge Select. In clock recovery mode, setting CLKE High causes RDATA or RPOS
and RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge
of SCLK. Setting CLKE Low makes RDATA or RPOS and RNEG to be valid on the rising
edge of RCLK and SDO to be valid on the falling edge of SCLK. In Data recovery Mode,
RDATA or RPOS/RNEG are active High output polarity when CLKE is High and active low
polarity when CLKE is Low.
84
CLKE
DI
CLKE
Low
RPOS/RNEG
SDO
RCLK
RCLK
SCLK
SCLK
High
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Datasheet
17
LXT388 — Dual T1/E1/J1 Transceiver
Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O1
Description
Address Select Inputs.
89
88
87
86
85
A4
A3
A2
A1
A0
DI
DI
DI
DI
DI
Host Mode
In non-multiplexed host mode, these pins function as non-multiplexed address pins. In
multiplexed host mode, these pins must be connected to Ground.
Hardware Mode
These pins must be grounded.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
18
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O1
Description
Loopback Mode Select/Parallel Data bus.
Host Mode:
When a non-multiplexed microprocessor interface is selected, these pins function as a bi-
directional 8-bit data port.
When a multiplexed microprocessor interface is selected, these pins carry both bi-
directional 8-bit data and address inputs A0 -A7.
In serial Mode, D0-7 should be grounded.
Hardware Mode:
In hardware mode, these pins control the operation of transceivers 0, 1 and receivers 2, 3
according to the table below.
During remote loopback mode, data on TPOS and TNEG is ignored and data received on
RTIP and RRING is looped around and retransmitted on TTIP and TRING. Note: in data
recovery mode, the pulse template cannot be guaranteed while in a remote loopback.
90
91
92
93
94
95
96
97
D0/LOOP0
D1/LOOP1
D2/LOOP2
D3/LOOP3
D4/DLOOP0
D5/DLOOP1
D6/DLOOP2
D7/DLOOP3
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
DI/O
In analog local loopback mode, data received on RTIP and RRING is ignored and data
transmitted on TTIP and TRING is internally looped around and routed back to the
receiver inputs.
Operating Mode
Transceivers 0,1
Operating Mode
Receivers 2, 3
LOOP
DLOOP
Open
x
x
0
1
Normal Mode
Normal Mode
0
1
1
Remote Loopback
-
Analog Local Loopback
Digital Local Loopback
-
Digital Local Loopback
In digital local loopback mode, data received on TCLK/TPOS/TNEG is digitally looped
back to RCLK/RPOS/RNEG.
Figure 9 through Figure 14 illustrate the different loopback modes.
Note: When these inputs are left open, they stay in a high impedance state. Therefore,
the layout design should not route signals with fast transitions near the LOOP pins. This
practice will minimize capacitive coupling.
Multiplexed/Non-Multiplexed Select.
When Low the parallel host interface operates in non-multiplexed mode. When High the
parallel host interface operates in multiplexed mode. In hardware mode tie this unused
input low.
99
MUX
DI
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
Datasheet
19
LXT388 — Dual T1/E1/J1 Transceiver
Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration
Pin #
LQFP
Symbol
I/O1
Description
Chip Select/Jitter Attenuator Select.
Host Mode
This active Low input is used to access the serial/parallel interface. For each read or write
operation, CS must transition from High to Low, and remain Low.
Hardware Mode
This input determines the Jitter Attenuator position in the data path.
CS/
DI
DI
98
JASEL
JASEL
JA Position
L
H
Z
Transmit path
Receive path
Disabled
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
20
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
2.0
Functional Description
The LXT388 is a fully integrated dual line interface unit designed for T1 1.544 Mbps and E1 2.048
Mbps short haul applications. It features two complete transceivers and two additional receiver and
jitter attenuation blocks. These block allow the LXT388 to work as a quad T1/E1 receiver with
jitter attenuation. Alternatively, these blocks can be used for Driver Performance Monitoring
(DPM) in the transceiver channel. They can also be used for jitter attenuation in the receive and
transmit paths simultaneously as discussed in “Driver Performance Monitoring” on page 29.
Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive.
These two lines comprise a digital data loop for full duplex transmission.
The LXT388 can be controlled through hard-wired pins or by a microprocessor through a serial or
parallel interface (Host mode).
The transmitter timing reference is TCLK, and the receiver reference clock is MCLK. The LXT388
is designed to operate without any reference clock when used as an analog front-end (line driver
and data recovery). MCLK is mandatory if the on chip clock recovery capability is used. All four
clock recovery circuits share the same reference clock defined by the MCLK input signal.
2.1
Initialization
During power up, the transceiver remains static until the power supply reaches approximately 60%
of VCC. During power-up, an internal reset sets all registers to their default values and resets the
status and state machines for the LOS.
2.1.1
Reset Operation
With revision B1, no-connect pin 100 converted to the RESET pin. Only revsion B1 requires a pull
up resistor to VCC at pin 100 in the LQFP package as shown in Figure 3.
There are two methods of resetting the LXT388:
1. Override Reset - Setting the RESET pin low in either hardware mode or host mode. Until the
RESET pin returns high, the LXT388 remains frozen and will not function. Once the RESET
pin has returned high, the LXT388 will operaate normally. Override Reset changes all the
internal registers to their default values.
2. Software Reset - Writing to the RES reset register initiates a 1microsecond reset cycle, except
in Intel non-multiplexed mode. In Intel non-multiplexed mode, the reset cycle takes 2
microseconds. Please refer to Host Mode section for more information. This operation
changes all LXT388 registers to their default values.
Datasheet
21
LXT388 — Dual T1/E1/J1 Transceiver
Figure 3. Pullup Resistor to RESET
VCC
1K
100
RESET
LXT388
2.2
Receiver
The four receivers in the LXT388 are identical. The following paragraphs describe the operation of
one.
The twisted-pair input is received via a 1:2 step down transformer. Positive pulses are received at
RTIP, negative pulses at RRING. Recovered data is output at RPOS and RNEG in the bipolar mode
and at RDATA in the unipolar mode. The recovered clock is output at RCLK. RPOS/RNEG
validation relative to RCLK is pin selectable using the CLKE pin.
The receive signal is processed through the peak detector and data slicers. The peak detector
samples the received signal and determines its maximum value. A percentage of the peak value is
provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For DSX-1
applications (line length inputs LEN2-0 from 011 to 111) the threshold is set to 70% (typical) of the
peak value. This threshold is maintained above the specified level for up to 15 successive zeros
over the range of specified operating conditions. For E1 applications (LEN2-0 = 000), the
threshold is set to 50% (typical).
The receiver is capable of accurately recovering signals with up to 12 dB of attenuation (from 2.4
V), corresponding to a received signal level of approximately 500 mV. Maximum line length is
1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level,
the peak detectors are held above a minimum level of 0.150 V (typical) to provide immunity from
impulsive noise.
After processing through the data slicers, the received signal goes to the data and timing recovery
section. The data and timing recovery circuits provide an input jitter tolerance better than required
by Pub 62411 and ITU G.823, as shown in Test Specifications, Figure 34.
Depending on the options selected, recovered clock and data signals may be routed through the
jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either
bipolar or unipolar data.
22
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
2.2.1
Loss of Signal Detector
The loss of signal detector in the LXT388 uses a dedicated analog and digital loss of signal
detection circuit. It is independent of its internal data slicer comparators and complies to the latest
ITU G.775 and ANSI T1.231 recommendations. Under software control, the detector can be
configured to comply to the ETSI ETS 300 233 specification (LACS Register). In hardware mode,
the LXT388 supports LOS per G.775 for E1 and ANSI T1.231 for T1 operation.
The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented
each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the
operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is
replaced by MCLK at the RCLK output. When the LOS condition is cleared, the LOS flag is reset
and another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will
reflect the data content at the receiver input during the entire LOS detection period for that channel.
2.2.1.1
E1 Mode
In G.775 mode a loss of signal is detected if the signal is below 200mV (typical) for 32 consecutive
pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit
period) with no more than 15 consecutive zeros and the signal level exceeds 250mV (typical), the
LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK.
In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048
consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low when
the incoming signal has transitions when the signal level is equal or greater than 250mV for more
than 32 consecutive pulse intervals. This mode is activated by setting the LACS register bit to one.
If it is necessary to use AIS with LOS, see errata 10.3 for a way to implement this.
2.2.1.2
2.2.1.3
T1 Mode
The T1.231 LOS detection criteria is employed. LOS is detected if the signal is below 200mV for
175 contiguous pulse positions. The LOS condition is terminated upon detecting an average pulse
density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a
pulse. The incoming signal is considered to have transitions when the signal level is equal or
greater than 250mV.
Data Recovery Mode
In data recovery mode the LOS digital timing is derived from a internal self timed circuit. RPOS/
RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775
recommendation. The LXT388 monitors the incoming signal amplitude. Any signal below 200mV
for more than 30µs (typical) will assert the corresponding LOS pin. The LOS condition is cleared
when the signal amplitude rises above 250mV. The LXT388 requires more than 10 and less than
255 bit periods to declare a LOS condition in accordance to ITU G.775.
2.2.2
Alarm Indication Signal (AIS) Detection
The AIS detection is performed by the receiver independent of any loopback mode. This feature is
available in host mode only. Because there is no clock in data recovery mode, AIS detection will
not work in that mode. AIS requires MCLK to have clock applied, since this function depends on
the clock to count the number of ones in an interval.
Datasheet
23
LXT388 — Dual T1/E1/J1 Transceiver
2.2.2.1
E1 Mode
One detection mode suitable for both ETSI and ITU is available when the LACS register bits are
cleared to zero. If the LACS register bit is set to one, see errata 10.3 to implement this.
ETSI ETS300233 and G.775 detection
The AIS condition is declared when the received data stream contains less than 3 zeros within a
period of 512 bits.
The AIS condition is cleared when 3 or more zeros within 512 bits are detected.
2.2.2.2
T1 Mode
ANSI T1.231 detection is employed.
The AIS condition is declared when less than 9 zeros are detected in any string of 8192 bits. This
corresponds to a 99.9% ones density over a period of 5.3 ms.
The AIS condition is cleared when the received signal contains 9 or more zeros in any string of
8192 bits.
2.2.3
In Service Code Violation Monitoring
In unipolar I/O mode with HDB3/B8ZS decoding, the LXT388 reports bipolar violations on
RNEG/BPV for one RCLK period for every HDB3/B8ZS code violation that is not part of the zero
code substitution rules. In AMI mode, all bipolar violations (two consecutive pulses with the same
polarity) are reported at the BPV output.
2.3
Transmitter
The two low power transmitters of the LXT388 are identical.
Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA
in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization. Unipolar I/O
and HDB3/B8ZS/AMI encoding/decoding is selected by pulling TNEG High for more than 16
consecutive TCLK clock cycles. The transmitter samples TPOS/TNEG or TDATA inputs on the
falling edge of TCLK. Refer to the Test Specifications Section for MCLK and TCLK timing
characteristics. If TCLK is not supplied, the transmitter remains powered down and the TTIP/
TRING outputs are held in a High Z state. In addition, fast output tristatability is also available
through the OE pin (all ports) and/or the port’s OEx bit in the Output Enable Register (OER).
Zero suppression is available only in Unipolar Mode. The two zero-suppression types are B8ZS,
used in T1 environments, and HDB3, used in E1 environments. The scheme selected depends on
whether the device is set for T1 or E1 operation (determined by LEN2-0 pulse shaping settings).
The LXT388 also supports AMI line coding/decoding as shown in Figure 4. In Hardware mode,
AMI coding/decoding is selected by the CODEN pin. In host mode, AMI coding/decoding is
selected by bit 4 in the GCR (Global Control Register).
24
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 4. 50% AMI Encoding
TTIP
Bit Cell
1
1
0
TRING
Each output driver is supplied by a separate power supply (TVCC and TGND). The transmit pulse
shaper is bypassed if no MCLK is supplied while TCLK is pulled high. In this case TPOS and
TNEG control the pulse width and polarity on TTIP and TRING. With MCLK supplied and TCLK
pulled high the driver enters TAOS (Transmit All Ones pattern). Note: The TAOS generator uses
MCLK as a timing reference. In order to assure that the output frequency is within specification
limits, MCLK must have the applicable stability.TAOS is inhibited during Remote Loopback.
2.3.0.1
Hardware Mode
In hardware mode, pins LEN0-2 determine the pulse shaping as described in Table 6 on page 26.
The LEN settings also determine whether the operating mode is T1 or E1. Note that in T1 operation
mode, all four ports will share the same pulse shaping setting. Independent pulse shaping for each
channel is available in host mode.
2.3.0.2
2.3.1
Host Mode
In Host Mode, the contents of the Pulse Shaping Data Register (PSDAT) determines the shape of
pulse output at TTIP/TRING. Refer to Table 28 on page 45 and Table 29 on page 45.
Transmit Pulse Shaping
The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped
pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The
line driver provides a constant low output impedance regardless of whether it is driving marks,
spaces or if it is in transition. This well controlled dynamic impedance provides excellent return
loss when used with external precision resistors (± 1% accuracy) in series with the transformer.
2.3.1.1
Output Driver Power Supply
The output driver power supply (TVCC pins) can be either 3.3V or 5V nominal. When TVCC=5V,
LXT388 drives both E1 (75Ω/120Ω) and T1 100Ω lines through a 1:2 transformer and 11Ω/9.1Ω
series resistors.
When TVCC=3.3V, the LXT388 drives E1 (75Ω/120Ω) lines through a 1:2 transformer and 11Ω
series resistor. A configuration with a 1:2 transformer and without series resistors should be used to
drive T1 100Ω lines.
Datasheet
25
LXT388 — Dual T1/E1/J1 Transceiver
Table 6. Line Length Equalizer Inputs
LEN2
LEN1
LEN0
Line Length1
Cable Loss2
Operation Mode
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0 - 133 ft. ABAM
0.6 dB
1.2 dB
1.8 dB
2.4 dB
3.0 dB
133 - 266 ft. ABAM
266 - 399 ft. ABAM
399 - 533 ft. ABAM
533 - 655 ft. ABAM
T1
E1
E1 G.703, 75Ω coaxial cable and 120Ω twisted pair cable.
1. Line length from LXT388 to DSX-1 cross-connect point.
2. Maximum cable loss at 772KHz.
Removing the series resistors for T1 applications with TVCC=3.3V, improves the power
consumption of the device. See Table 40 on page 55.
Series resistors in the transmit configuration improve the transmit return loss performance. Good
transmit return loss performance minimizes reflections in harsh cable environments. In addition,
series resistors provide protection against surges coupled to the device. The resistors should be
used in systems requiring protection switching without external relays. Please refer to Figure 5 on
page 28 for the recommended external line circuitry.
2.3.1.2
Power Sequencing
For the LXT384, we recommend sequencing TVCC first then VCC second or at the same time as
TVCC to prevent excessive current draw.
2.4
Line Protection
Figure 5 on page 28 shows recommended line interface circuitry. In the receive side, the 1 kΩ
series resistors protect the receiver against current surges coupled into the device. Due to the high
receiver impedance (70 kΩ typical) the resistors do not affect the receiver sensitivity. In the
transmit side, the Schottky diodes D1-D4 protect the output driver.While not mandatory for normal
operation, these protection elements are strongly recommended to improve the design robustness.
2.5
Driver Failure Monitor
The LXT388 transceiver incorporates a internal power Driver Failure Monitor (DFM) in parallel
with TTIP and TRING that is capable of detecting secondary shorts without cable. DFM is
available only in configurations with no transmit series resistors (T1 mode with TVCC=3.3V).
This feature is available in the serial and parallel host modes but not available in the hardware
mode of operation.
A capacitor, charged via a measure of the driver output current and discharged by a measure of the
maximum allowable current, is used to detect a secondary short failure. Secondary shorted lines
draw excess current, overcharging the cap. When the capacitor charge deviates outside the nominal
26
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
charge window, a driver short circuit fail (DFM) is reported in the respective register by setting an
interrupt. During a long string of spaces, a short-induced overcharge eventually bleeds off, clearing
the DFM flag.
Note: Unterminated lines of adequate length (λ/4) may effectively behave as short-circuits as seen
by the driver and therefore trigger the DFM. Under these circumstances, the alarm should be
disabled.
In addition, the LXT388 features output driver short-circuit protection. When the output current
exceeds 100 mA, LXT388 limits the driver’s output voltage to avoid damage.
Datasheet
27
LXT388 — Dual T1/E1/J1 Transceiver
Figure 5. External Transmit/Receive Line Circuitry
TVCC
TVCC
TVS1
68µF
1
0.1µF
TVCC
D4
RT
1:2
TTIP
D3
3.3V
Tx LINE
2
VCC
GND
560pF
TVCC
0.1µF
D2
D1
TRING
RT
3
LXT388
(ONE CHANNEL)
1k
Ω
1:2
RTIP
RR
Rx LINE
0.22µF
RR
RRING
1k
Ω
1
2
3
Common decoupling capacitor for all TVCC and TGND pins.
Typical value. Adjust for actual board parasitics to obtain optimum return loss.
Refer to Transformer Specifications Table for transformer specifications.
28
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 6. Driver Performance Monitoring
TVCC
D4
D3
RT
1:2
TTIP
560pF
TRANSMITTER # 0/1
TVCC
D2
D1
TRING
RT
LXT388
0.1
µF
0.1
µF
1.8 kΩ
1.8 k
Ω
RTIP
470
470
Ω
Ω
0.22µF
RECEIVER # 2/3
LOS / DPM
RRING
2.6
Driver Performance Monitor
The two additional receiver blocks in the LXT388 can be used to monitor the transmitter
performance in channels 0 and 1 as illustrated in Figure 6.
The transmitter outputs in channels 0 and 1 are connected to receivers 2 and 3 through capacitive
coupling. If the output driver stops transmitting data, the LOS output in the monitoring receiver
will be asserted indicating a driver failure. Therefore, the LOS output effectively acts as a driver
performance monitor indicator (DPM). This alarm is also available in host mode through the LOS
registers.
The DPM set and reset operation is identical to the LOS set and reset operation as described in
“Loss of Signal Detector” on page 23.
Datasheet
29
LXT388 — Dual T1/E1/J1 Transceiver
Note: T1/E1 receiver operation in channels 2 and 3 is determined by the LEN settings as described in
Table 6 on page 26.
2.7
Jitter Attenuation
A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL
is internal and requires no external crystal nor high-frequency (higher than line rate) reference
clock.
The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the FIFO64 bit in the GCR). Data is
clocked into the FIFO with the associated clock signal (TCLK or RCLK), and clocked out of the
FIFO with the dejittered JAL clock. See Figure 7. When the FIFO is within two bits of overflowing
or underflowing, the FIFO adjusts the output clock by 1/8 of a bit period. The Jitter Attenuator
produces a control delay of 17 or 33 bits in the associated path (refer to test specifications). This
feature is required for hitless switching applications. This advanced digital jitter attenuator meets
latest jitter attenuation specifications. See Table 7.
Under software control, the low limit jitter attenuator corner frequency depends on FIFO length
and the JACF bit setting (this bit is in the GCR register). In Hardware Mode, the FIFO length is
fixed to 64 bits. The corner frequency is fixed to 6 Hz for T1 mode and 3.5 Hz for E1 mode.
Table 7. Jitter Attenuation Specifications
T1
E1
AT&T Pub 62411
GR-253-CORE1
ITU-T G.736
ITU-T G.7423
ITU-T G.7834
ETSI CTR12/13
BAPT 220
TR-TSY-0000092
1. Category I, R5-203.
2. Section 4.6.3.
3. Section 6.2 When used with the SXT6234 E2-E1 mux/demux.
4. Section 6.2.3.3 combined jitter when used with the SXT6251 21E1 mapper.
30
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 7. Jitter Attenuator Loop
FIFO64
TPOS
TPOSo
RPOS
RPOSi
TNEG
TNEGo
RNEG
FIFO
RNEGi
IN CK
OUT CK
TCLK
TCLK
RCLK
IN
OUT
DPLL
RCLKi
JASEL0-1
JASEL0-1
MCLK
JACF
x 32
GCR control bits
In Host Mode, the Global Control Register (GCR) determines whether the JAL is positioned in the
receive path, transmit path or disabled. In Hardware Mode, the JAL position is determined by the
JASEL pin.
2.7.1
Transmit and Receive Jitter Attenuation
Simultaneous transmit and receive jitter attenuation can be implemented using the additional jitter
attenuators in the receiver/JA blocks 2 and 3. Please refer to Figure 8. In this example, the jitter
attenuator in channels 0 and 1 is placed in the transmit path. Receive path jitter attenuation is
obtained by routing the corresponding RCLK/RPOS/RNEG signals through the JAs in blocks 2
and 3. This is accomplished by enabling a digital loopback in these channels. Note that the CLKE
pin should be tied High to allow direct connection between RCLK/RPOS/RNEG and TCLK/
TPOS/TNEG. Connections in Figure 8 are shown for bipolar mode operation. In unipolar mode
(TNEG=High), RCLK and RDATA should be connected to TCLK and TDATA. Bipolar violations
for channels 0 and 1 will be reported at the BPV (RNEG) outputs in those channels.
Datasheet
31
LXT388 — Dual T1/E1/J1 Transceiver
Figure 8. Transmit and Receive Jitter Attenuation
TRANSCEIVERS, #0, 1
TCLK
TPOS
TNEG
TTIP
Timing &
Control
JA
TRING
RTIP
RCLK
RPOS
RNEG
Timing
& Data
Recovery
RRING
LOS
1
MONITORING/JA, #2, 3
TCLK
TPOS
TNEG
JA
RCLK
RPOS
RNEG
RTIP
Timing
& Data
Recovery
RRING
LOS/DPM
* If Enabled
Inverter not necessary if CLKE is high. However, if
CLKE is low, inverter required.
1
2.8
Loopbacks
The LXT388 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback
mode is selected with the LOOPn pins. In software mode, the ALOOP, DLOOP and RLOOP
registers are employed.
2.8.1
Analog Loopback
When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver
inputs (RTIP & RRING) as shown in Figure 9. Data and clock are output at RCLK, RPOS &
RNEG pins for the corresponding transceiver. Note that signals on the RTIP & RRING pins are
ignored during analog loopback.
32
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 9. Analog Loopback
TCLK
TPOS
TNEG
TTIP
Timing &
Control
JA*
JA*
TRING
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
* If Enabled
2.8.2
Digital Loopback
The digital loopback function is available in software and Hardware mode. When selected, the
transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK,
RPOS & RNEG pins (Figure 10). The data presented on TCLK, TPOS & TNEG is also output on
the TTIP & TRING pins. Note that signals on the RTIP & RRING pins are ignored during digital
loopback.
Figure 10. Digital Loopback
TCLK
TPOS
TNEG
TTIP
Timing &
Control
JA*
JA*
TRING
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
* If Enabled
2.8.3
Remote Loopback
During remote loopback (Figure 11) the RCLK, RPOS & RNEG outputs routed to the transmit
circuits and output on the TTIP & TRING pins. Note that input signals on the TCLK, TPOS &
TNEG pins are ignored during remote loopback.
Datasheet
33
LXT388 — Dual T1/E1/J1 Transceiver
Figure 11. Remote Loopback
TCLK
TPOS
TNEG
TTIP
Timing &
Control
JA*
JA*
TRING
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
* If Enabled
Note: In data recovery mode, the pulse template cannot be guaranteed while in a remote loopback.
2.8.4
Transmit All Ones (TAOS)
In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles.
In software mode, TAOS mode is set by asserting the corresponding bit in the TAOS Register. In
addition, automatic ATS insertion (in case of LOS) may be set using the ATS Register. Note that
the TAOS generator uses MCLK as a timing reference, therefore TAOS doesn’t work in data
recovery mode. In order to assure that the output frequency is within specification limits, MCLK
must have the applicable stability. DLOOP does not function with TOAS active.
Figure 12. TAOS Data Path
MCLK
TAOS mode
Timing &
Control
TTIP
TCLK
TPOS
TNEG
TRING
(ALL 1’s)
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
JA*
RRING
* If Enabled
34
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 13. TAOS with Digital Loopback
MCLK
TAOS Mode
Timing &
Control
TTIP
TCLK
TPOS
TNEG
JA*
JA*
TRING
(ALL 1’s)
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
RRING
* If Enabled
Figure 14. TAOS with Analog Loopback
MCLK
TAOS Mode
Timing &
Control
TCLK
TPOS
TNEG
TTIP
TRING
(ALL 1’s)
RCLK
RPOS
RNEG
RTIP
Timing
Recovery
JA*
RRING
* If Enabled
2.9
Intel Hitless Protection Switching (Intel HPS)
The LXT388 transceivers include an output driver tristatability feature for T1/E1/J1 redundancy
applications. This feature greatly reduces the cost of implementing redundancy protection by
eliminating external relays. Please refer to Application Note 249134 “LXT380/1/4/6/8
Redundancy Applications” for guidelines on implementing redundancy systems for both T1/E1/J1
operation using the LXT380/1/4/6/8.
2.10
Operation Mode Summary
Table 8 lists summarizes all LXT388 hardware settings and corresponding operating modes.
Table 8. Operation Mode Summary
MCLK
TCLK
LOOP1
Receive Mode
Transmit Mode
Loopback
Clocked
Clocked
Clocked
Clocked
Clocked
Clocked
Open
Data/Clock recovery
Data/Clock recovery
Data/Clock recovery
Pulse Shaping ON
Pulse Shaping ON
Pulse Shaping ON
No Loopback
Remote Loopback
Analog Loopback
L
H
1. Hardware mode only.
Datasheet
35
LXT388 — Dual T1/E1/J1 Transceiver
Table 8. Operation Mode Summary (Continued)
MCLK
TCLK
LOOP1
Receive Mode
Transmit Mode
Loopback
Clocked
L
Open
Data/Clock recovery
Data/Clock Recovery
Data/Clock Recovery
Data/Clock Recovery
Data/Clock Recovery
Data/Clock Recovery
Power Down
Power down
Power down
No Loopback
No effect on op.
No Analog Loopback
No Loopback
Clocked
L
L
Clocked
L
H
Power down
Clocked
H
Open
Transmit All Ones
Pulse Shaping ON
Transmit All Ones
Pulse Shaping ON
Pulse Shaping ON
Pulse Shaping ON
Pulse Shaping OFF
Pulse Shaping OFF
Pulse Shaping OFF
Power down
Clocked
H
L
Remote Loopback
No effect on op.
No Loopback
Clocked
H
H
L
L
Clocked
Open
Clocked
L
Power Down
No Remote Loopback
No effect on op.
No Loopback
L
Clocked
H
Power Down
L
H
Open
Power Down
L
H
L
Power Down
No Remote Loop
No effect on op.
No Loopback
L
H
H
X
Power Down
L
L
Power Down
H
H
H
H
H
H
H
H
Clocked
Open
L
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Data Recovery
Pulse Shaping ON
Pulse Shaping OFF
Pulse Shaping ON
Power down
No Loopback
Clocked
Remote Loopback
Analog Loopback
No Loopback
Clocked
H
L
L
Open
L
Pulse Shaping OFF
Pulse Shaping OFF
Pulse Shaping OFF
Pulse Shaping OFF
Remote Loopback
No Loopback
H
H
H
Open
L
Remote Loopback
Analog Loopback
H
1. Hardware mode only.
2.11
2.12
Interfacing with 5V logic
The LXT388 can interface directly with 5V logic. The internal input pads are tolerant to 5V outputs
from TTL and CMOS family devices.
Parallel Host Interface
The LXT388 incorporates a highly flexible 8-bit parallel microprocessor interface. The interface is
generic and is designed to support both non-multiplexed and multiplexed address/data bus systems
for Motorola and Intel bus topologies. Two pins (MUX and MOT/INTL) select four different
operating modes as shown in Table 9.
36
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 9. Microprocessor Parallel Interface Selection
MUX
MOT/INTL
Operating Mode
Low
Low
High
High
Low
High
Low
High
Motorola Non-Multiplexed
Intel Non-Multiplexed
Motorola Multiplexed
Intel Multiplexed
The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed
operation and an 8-bit address/data bus for multiplexed operation. WR, RD, R/W, CS, ALE, DS,
INT and RDY/ACK are used as control signals. A significant enhancement is an internal wait-state
generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In
Motorola mode ACK Low signals valid information is on the data bus. During a write cycle a Low
signal acknowledges the acceptance of the write data.
In Intel mode RDY High signals to the controlling processor that the bus cycle can be completed.
While Low the microprocessor must insert wait states. This allows the LXT388 to interface with
wait-state capable micro controllers, independent of the processor bus speed. To activate this
function a reference clock is required on the MCLK pin.
There is one exception to write cycle timing for Intel non-multiplexed mode: Register 0Ah, the
reset register. Because of timing issues, the RDY line remains high after the first part of the cycle
is done, not signalling write cycle completion with another transition low. Add 2 microseconds of
delay to allow the reset cycle to completely initialize the device before proceeding.
An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to
the microprocessor.
The LXT388 has a 5 bit address bus and provides 18 user accessible 8-bit registers for
configuration, alarm monitoring and control of the chip.
2.12.1
Motorola Interface
The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode
the falling edge of DS is used to latch the address information on the address bus. In multiplexed
operation the address on the multiplexed address data bus is latched into the device with the falling
edge of AS. In non-multiplexed mode, AS should be pulled High.
The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference
for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/
W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising
edge on DS.
Both cycles require the CS signal to be Low and the Address pins to be actively driven by the
microprocessor. Note that CS and DS can be connected together in Motorola mode. In a write cycle
the data bus is driven by the microprocessor. In a read cycle the bus is driven by the LXT388.
Datasheet
37
LXT388 — Dual T1/E1/J1 Transceiver
2.12.2
Intel Interface
The Intel interface is selected by asserting the MOT/INTL pin High. The LXT388 supports non-
multiplexed interfaces with separate address and data pins when MUX is asserted Low, and
multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of
ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS
is used as the WR signal. A read cycle is indicated to the LXT388 when the processor asserts RD
Low while the WR signal is held High. A write operation is indicated to the LXT388 by asserting
WR Low while the RD signal is held High. Both cycles require the CS signal to be Low.
2.13
Interrupt Handling
2.13.1
Interrupt Sources
There are three interrupt sources:
1. Status change in the Loss Of Signal (LOS) status register (04H). The LXT388’s analog/digital
loss of signal processor continuously monitors the receiver signal and updates the specific
LOS status bit to indicate presence or absence of a LOS condition.
2. Status change in the Driver Failure Monitoring (DFM) status register (05H). The LXT388’s
smart power driver circuit continuously monitors the output drivers signal and updates the
specific DFM status bit to indicate presence or absence of a secondary driver short circuit
condition.
3. Status change in the Alarm Indication Signal (AIS) status register (13H).The LXT388’s
receiver monitors the incoming data stream and updates the specific AIS status bit to indicate
presence or absence of a AIS condition.
2.13.2
Interrupt Enable
The LXT388 provides a latched interrupt output (INT). An interrupt occurs any time there is a
transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM
and AIS interrupt enable registers (respectively). Writing a logic “1” into the mask register will
enable the respective bit in the respective Interrupt status register to generate an interrupt. The
power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the
operation of the status registers.
Registers 08H, 09H and 15H are the LOS, DFM and AIS (respectively) interrupt status registers.
When there is a transition on any enabled bit in a status register, the associated bit of the interrupt
status register is set and an interrupt is generated (if one is not already pending). When an interrupt
occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down
device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR
operation.
2.13.3
Interrupt Clear
When an interrupt occurs, the interrupt service routine (ISR) should read the interrupt status
registers (08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register
clears the "sticky" bit set by the interrupt. Automatically clearing the register prepares it for the
next interrupt. The ISR should then read the corresponding status monitor register to obtain the
current status of the device. Note: there are three status monitor registers: the LOS (04H), the DFM
38
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
(05H) and the AIS (013H). Reading either status monitors register will clear its corresponding
interrupts on the rising edge of the read or data strobe. When all pending interrupts are cleared, the
INT pin goes High.
2.14
Serial Host Mode
The LXT388 operates in Serial Host Mode when the MODE pin is tied to VCC÷2. Figure 15 shows
the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/
Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W
determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte
address specific registers (the address decoder ignores bits A7-6). The data byte depends on both
the value of bit R/W and the address of the register as set in the Command/Address byte.
Figure 15. Serial Host Mode Timing
CS
SCLK
INPUT DATA BYTE
D2 D3 D4 D5
ADDRESS/COMMAND BYTE
R/W A1 A2
A3 A4 A5
A6 A7
D0 D1
D6
D7
SDI
X
X
SDO - REMAINS HIGH Z
SDO IS DRIVEN IF R/W = 1
R/W = 1: Read from the LXT388
R/W = 0: Write to the LXT388
X = Don’t care
Datasheet
39
LXT388 — Dual T1/E1/J1 Transceiver
3.0
Register Descriptions
Table 10. Serial and Parallel Port Register Addresses
Address
Name
Symbol
Mode
Serial Port
A7-A1
Parallel Port
A7-A0
ID Register
ID
ALOOP
RLOOP
TAOS
LOS
DFM
LIE
xx00000
xx00001
xx00010
xx00011
xx00100
xx00101
xx00110
xx00111
xx01000
xx01001
xx01010
xx01011
xx01100
xx01101
xx01110
xx01111
xxx00000
xxx00001
xxx00010
xxx00011
xxx00100
xxx00101
xxx00110
xxx00111
xxx01000
xxx01001
xxx01010
xxx01011
xxx01100
xxx01101
xxx01110
xxx01111
R
Analog Loopback
R/W
R/W
R/W
R
Remote Loopback
TAOS Enable
LOS Status Monitor
DFM Status Monitor
LOS Interrupt Enable
DFM Interrupt Enable
LOS Interrupt Status
DFM Interrupt Status
Software Reset Register
Performance Monitoring
Digital Loopback
R
R/W
R/W
R
DIE
LIS
DIS
R
RES
MON
DL
R/W
R/W
R/W
R/W
R/W
R/W
LOS/AIS Criteria Selection
Automatic TAOS Select
Global Control Register
LOSC
ATS
GCR
Pulse Shaping Indirect
Address Register
PSIAD
PSDAT
xx10000
xx10001
xxx10000
xxx10001
R/W
R/W
Pulse Shaping Data
Register
Output Enable Register
AIS Status Register
AIS Interrupt Enable
AIS Interrupt Status
OER
AIS
xx10010
xx10011
xx10100
xx10101
xxx10010
xxx10011
xxx10100
xxx10101
R/W
R
AISIE
AISIS
R/W
R
Table 11. Register Bit Names
Register
Bit
Name
ID Register
Sym
RW
7
6
5
4
3
2
1
0
ID
R
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
reserve
d
Analog Loopback
Remote Loopback
ALOOP R/W
RLOOP R/W
-
-
-
-
-
-
-
-
reserved
reserved
AL1
RL1
AL0
RL0
reserve
d
40
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 11. Register Bit Names (Continued)
Register
Bit
Name
Sym
RW
7
6
5
4
3
2
1
0
reserve
d
TAOS Enable
TAOS
LOS
DFM
LIE
R/W
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
reserved
LOS2
TAOS1
LOS1
DFM1
LIE1
TAOS0
LOS0
DFM0
LIE0
LOS Status Monitor
DFM Status Monitor
LOS Interrupt Enable
DFM Interrupt Enable
LOS Interrupt Status
DFM Interrupt Status
LOS3
reserve
d
R
reserved
LIE2
R/W
R/W
R
LIE3
reserve
d
DIE
reserved
LIS2
DIE1
LIS1
DIE0
LIS0
LIS
LIS3
reserve
d
DIS
R
reserved
DIS1
DIS0
Software Reset
Register
RES
-
R/W
R/W
-
-
-
-
RES3
RES2
RES1
RES0
reserve reserve reserve reserve reserve
Reserved
reserved reserved reserved
d
d
d
d
d
Digital Loopback
DL
R/W
R/W
-
-
-
-
DL3
DL2
DL1
DL0
LOS/AIS Criteria Select
LACS
-
-
-
-
LACS3
LACS2
LACS1
LACS0
reserve
d
Automatic TAOS Select
Global Control Register
ATS
R/W
R/W
-
-
-
-
reserved
JACF
ATS1
ATS0
reserve RAISE
GCR
CDIS
CODEN FIFO64
JASEL1
JASEL0
d
N
Pulse Shaping Indirect
Address Register
reserve reserve reserve reserve reserve
PSIAD R/W
PSDAT R/W
LENAD2 LENAD1 LENAD0
d
d
d
d
d
Pulse Shaping Data
Register
reserve reserve reserve reserve reserve
LEN2
LEN1
OE1
LEN0
OE0
d
d
d
d
d
reserve
d
Output Enable Register
OER
R/W
-
-
-
-
reserved
AIS Status Register
AIS Interrupt Enable
AIS Interrupt Status
AIS
R
R/W
R
-
-
-
-
-
-
-
-
-
-
-
-
AIS3
AIS2
AIS1
AIS0
AISIE
AISIS
AISIE3
AISIS3
AISIE2
AISIS2
AISIE1
AISIS1
AISIE0
AISIS0
Table 12. ID Register, ID (00H)
Bit
Name
Function
This register contains a unique revision code and is mask programmed.
Revision
A1
ID Code
00h
7-0
ID7-ID0
B1
21h
B2
22h
Datasheet
41
LXT388 — Dual T1/E1/J1 Transceiver
Table 13. Analog Loopback Register, ALOOP (01H)
Bit
Name
Function
1-0
7-2
AL1-AL0
-
Setting a bit to “1” enables analog local loopback for transceivers 1- 0 respectively.
Write “0” to these positions for normal operation.
Table 14. Remote Loopback Register, RLOOP (02H)
Bit
Name
Function
1-0
7-2
RL1-RL0
-
Setting a bit to “1” enables remote loopback for transceivers 1-0 respectively.
Write “0” to these positions for normal operation.
Table 15. TAOS Enable Register, TAOS (03H)
Bit1
Name
Function2
Setting a bit to “1” causes a continuous stream of marks to be sent out at the TTIP and
TRING pins of the respective transceiver 1-0.
1-0
7-2
TAOS1-TAOS0
-
Write “0” to these positions for normal operation.
1. On power up all register bits are set to “0”.
2. MCLK is used as timing reference. If MCLK is not available then the channel TCLK is used as the reference. TAOS is not
available in data recovery mode and line driver mode (MCLK=TCLK=High).
Table 16. LOS Status Monitor Register, LOS (04H)
Bit1
Name
Function
Respective bit(s) are set to “1” every time the LOS processor detects a valid loss of signal
condition in receivers 3-0.
3-0
LOS3-LOS0
1. On power up all register bits are set to “0”. Any change in the state causes an interrupt. All LOS interrupts are cleared by a
single read operation.
Table 17. DFM Status Monitor Register, DFM (05H)
Bit1
Name
Function
Respective bit(s) are set to “1” every time the short circuit monitor detects a valid
secondary output driver short circuit condition in transceivers 1-0. Note that DFM is
available only in configurations with no transmit series resistors (T1 mode with
TVCC=3.3V).
1-0
7-2
DFM1-DFM0
-
Write “0” to these positions for normal operation.
1. On power-up all the register bits are set to “0”. All DFM interrupts are cleared by a single read operation.
42
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 18. LOS Interrupt Enable Register, LIE (06H)
Bit1
Name
Function
3-0
7-4
LIE1-LIE0
-
Receiver 3-0 LOS interrupts are enabled by writing a “1” to the respective bit.
Write “0” to these positions for normal operation.
1. On power-up all the register bits are set to “0”and all interrupts are disabled.
Table 19. DFM Interrupt Enable Register, DIE (07H)
Bit1
Name
Function
1-0
7-2
DIE13-DIE0
-
Transceiver 1-0 DFM interrupts are enabled by writing a “1” to the respective bit.
Write “0” to these positions for normal operation.
1. On power-up all the register bits are set to “0”and all interrupts are disabled.
Table 20. LOS Interrupt Status Register, LIS (08H)
Bit
Name
Function
These bits are set to “1” every time a LOS status change has occurred since the last clear
interrupt in receivers 3-0 respectively.
3-0
LIS3-LIS0
Table 21. DFM Interrupt Status Register, DIS (09H)
Bit
Name
Function
These bits are set to “1” every time a DFM status change has occurred since the last
cleared interrupt in transceivers 1-0 respectively.
1-0
DIS1-DIS0
Table 22. Software Reset Register, RES (0AH)
Bit
Name
Function
Writing to this register initiates a 1 microsecond reset cycle, except in Intel non-
multiplexed mode. When using Intel non-multiplexed host mode, extend cycle time to 2
microseconds. Please refer to Host Mode section for more information. This operation
sets all LXT388 registers to their default values.
3-0
RES3-RES0
Table 23. Reserved (0BH)
Bit
Name
Function
7-0
reserved
Write “0” to these positions for normal operation.
Datasheet
43
LXT388 — Dual T1/E1/J1 Transceiver
Table 24. Digital Loopback Register, DL (0CH)
Bit1
Name
Function2
3-0
DL3-DL0
Setting a bit to “1” enables digital loopback for the respective channel.
1. On power up all register bits are set to “0”.
2. During digital loopback LOS and TAOS stay active and independent of TCLK, while data received on TPOS/TNEG/TCKLK is
looped back to RPOS/RNEG/RCLK.
Table 25. LOS/AIS Criteria Register, LCS (0DH)
Bit1
Name
Function2
T1 Mode2
Don’t care. T1.231 compliant LOS/AIS detection is used.
LCS3-LCS01
E1 Mode
3-0
Setting a bit to “1” selects the ETS1 300233 LOS. Setting a bit to “0” selects G.775 LOS
mode. AIS works correctly for both ETSI and ITU when the bit is cleared to “0”. See
errata revision 10.3 or higher for a way to implement ETSI LOS and AIS.
1. On power-on reset the register is set to “0”.
2. T1 or E1 operation mode is determined by the PSDR settings.
Table 26. Automatic TAOS Select Register, ATS (0EH)
Bit1
Name
Function
Setting a bit to “1” enables automatic TAOS generation whenever a LOS condition is
detected in the respective transceiver.
1-0
7-2
ATS1-ATS0
-
Write “0” to these positions for normal operation.
1. On power-on reset the register is set to “0”.This feature is not available in data recovery and line driver mode (MCLK= High
and TCLK = High)
Table 27. Global Control Register, GCR (0FH)
Bit1
Name
Function
0
JASEL0
These bits determine the jitter attenuator position.
JASEL0
JASEL1
JA Position
1
1
0
0
1
x
Transmit Path
Receive Path
Disabled
1
JASEL1
This bit determines the jitter attenuator low limit 3dB corner frequency. Refer to the Jitter
Attenuator specifications for details (Table 46 on page 60).
2
3
JACF
This bit determines the jitter attenuator FIFO depth:
FIFO64
0 = 32 bit
1 = 64 bit
1. On power-on reset the register is set to “0”.
44
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 27. Global Control Register, GCR (0FH) (Continued)
Bit1
Name
Function
This bit selects the zero suppression code for unipolar operation mode:
4
CODEN
0 = B8ZS/HDB3 (T1/E1 respectively)
1 = AMI
This bit controls enables/disables the short circuit protection feature:
5
CDIS
0 = enabled
1 = disabled
This bit controls automatic AIS insertion in the receive path when LOS occurs:
0 = Receive AIS insertion disabled on LOS
1 = RPOS/RNEG = AIS on LOS
6
7
RAISEN
-
Note: this feature is not available in data recovery mode (MCLK=High). Disable AIS
interrupts when changing this bit value to prevent inadvertent interrupts.
Reserved.
1. On power-on reset the register is set to “0”.
Table 28. Pulse Shaping Indirect Address Register, PSIAD (10H)
Bit1
Name
Function
The three bit value written to these bits determine the channel to be addressed:
0H = channel 0
1H = channel 1
2H = receiver 2
3H = receiver 3
0-2
LENAD 0-2
Data can be read from (written to) the Pulse Shaping Data Register (PSDAT).
Reserved.
3 - 7
-
1. On power-on reset the register is set to “0”.
Table 29. Pulse Shaping Data Register, PSDAT (11H)
Bit
Name
Function
LEN0-2 determine the LXT388 operation mode (T1 or E1) in all the receivers. In addition,
for T1 operation, LEN2-0 set transmit pulse shaping in order to meet T1.102 pulse
template at the DSX-1 cross-connect point for various cable lengths.
Operation
Mode
LEN2
LEN1
LEN0
Line Length
Cable Loss2
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0 - 133 ft. ABAM
133 - 266 ft. ABAM
266 - 399 ft. ABAM
399 - 533 ft. ABAM
533 - 655 ft. ABAM
0.6 dB
1.2 dB
1.8 dB
2.4 dB
3.0 dB
0-2
LEN 0-2 1,3
T1
E1 G.703, 75Ω coaxial cable and 120 Ω
0
0
0
E1
twisted pair cable.
3 - 7
-
Reserved.
1. On power-on reset the register is set to “0”.
2. Maximum cable loss at 772 KHz.
3. When reading LEN, bit values appear inverted. “B1” revision silicon will fix this so the bits read back correctly.
Datasheet
45
LXT388 — Dual T1/E1/J1 Transceiver
Table 30. Output Enable Register, OER (12H)
Bit1
Name
Function
1-0
7-2
OE1 - OE0
-
Setting a bit to “1” tristates the output driver of the corresponding transceiver.
Write “0” to these positions for normal operation.
1. On power-up all the register bits are set to “0”.
Table 31. AIS Status Monitor Register, AIS (13H)
Bit1
Name
Function
Respective bit(s) are set to “1” every time the receiver detects a AIS condition in receivers
3-0.
3-0
AIS3-AIS0
1. On power-up all the register bits are set to “0”. All AIS interrupts are cleared by a single read operation.
Table 32. AIS Interrupt Enable Register, AISIE (14H)
Bit1
Name
Function
3-0
7-4
AISIE3-AISIE0
-
Transceiver 3-0 AIS interrupts are enabled by writing a “1” to the respective bit.
Write “0” to these positions for normal operation.
1. On power-up all the register bits are set to “0”.
Table 33. AIS Interrupt Status Register, AISIS (15H)
Bit1
Name
Function
These bits are set to “1” every time a AIS status change has occurred since the last clear
interrupt in receivers 3-0 respectively.
3-0
AISIS3-AISIS0
1. On power-up all the register bits are set to “0”.
46
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
4.0
JTAG Boundary Scan
4.1
Overview
The LXT388 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy
access to the interface pins for board testing purposes.
In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT388 also
includes analog test port capabilities. This feature provides access to the TIP and RING signals in
each channel (transmit and receive). This way, the signal path integrity across the primary winding
of each coupling transformer can be tested.
4.2
Architecture
Figure 16 represents the LXT388 basic JTAG architecture. The LXT388 JTAG architecture
includes a TAP Test Access Port Controller, data registers and an instruction register. The
following paragraphs describe these blocks in detail.
Figure 16. LXT388 JTAG Architecture
Boundry Scan Data Register
BSR
Analog Port Scan Register
ASR
Device Identification Register
MUX
TDO
TDI
IDR
Bypass Register
BYR
Instruction Register
IR
TCK
TAP
Controller
TMS
TRST
4.3
TAP Controller
The TAP controller is a 16 state synchronous state machine controlled by the TMS input and
clocked by TCK (Figure 17).The TAP controls whether the LXT388 is in reset mode, receiving an
instruction, receiving data, transmitting data or in an idle state. Table 34 describes in detail each of
the states represented in Figure 17.
Datasheet
47
LXT388 — Dual T1/E1/J1 Transceiver
Table 34. TAP State Description
State
Description
In this state the test logic is disabled. The device is set to normal operation mode. While
in this state, the instruction register is set to the ICODE instruction.
Test Logic Reset
Run -Test/Idle
Capture - DR
Shift - DR
The TAP controller stays in this state as long as TMS is low. Used to perform tests.
The Boundary Scan Data Register (BSR) is loaded with input pin data.
Shifts the selected test data registers by one stage word its serial output.
Data is latched into the parallel output of the BSR when selected.
Used to load the instruction register with a fixed instruction.
Shifts the instruction register by one stage.
Update - DR
Capture - IR
Shift - IR
Update - IR
Loads a new instruction into the instruction register.
Pause - IR
Pause - DR
Momentarily pauses shifting of data through the data/instruction registers.
Exit1 - IR
Exit1 - DR
Exit2 - IR
Exit2 - DR
Temporary states that can be used to terminate the scanning process.
48
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 17. JTAG State Diagram
1
TEST-LOGIC
RESET
0
0
1
1
1
RUN TEST/IDLE
SELECT-DR
SELECT-IR
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
0
SHIFT-DR
SHIFT-IR
1
1
1
0
1
EXIT1-DR
EXIT1-IR
0
0
0
PAUSE-DR
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
0
UPDATE-DR
UPDATE-IR
1
0
1
0
4.4
JTAG Register Description
The following paragraphs describe each of the registers represented in Figure 16.
Datasheet
49
LXT388 — Dual T1/E1/J1 Transceiver
4.4.1
Boundary Scan Register (BSR)
The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply
and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register.
Bidirectional pins or tristatable pins require more than one position in the register. Table 35 shows
the BSR scan cells and their functions. Data into the BSR is shifted in LSB first.
Table 35. Boundary Scan Register (BSR)
Pin
Signal
I/O
Type
Bit
Symbol
Bit #
Comments
0
LOS3
O
O
LOS3
RNEG3
RNEG3
HIZ3 controls the RPOS3, RNEG3 and RCLK3 pins. Setting HIZ3 to “0”
enables output on the pins. Setting HIZ3 to “1” tristates the pins.
N/A
-
HIZ3
RPOS3
RCLK3
TNEG3
TPOS3
TCLK3
LOS2
O
O
I
RPOS3
RCLK3
TNEG3
TPOS3
TCLK3
LOS2
I
I
O
O
RNEG2
RNEG2
HIZ2 controls the RPOS2, RNEG2 and RCLK2 pins. Setting HIZ2 to “0”
enables output on the pins. Setting HIZ2 to “1” tristates the pins.
N/A
-
HIZ2
RPOS2
RCLK2
TNEG2
TPOS2
TCLK2
MCLK
MODE
INT
O
O
I
RPOS2
RCLK2
TNEG2
TPOS2
TCLK2
I
I
I
MCLK
I
MODE
O
INTRUPTB
SDORDYENB controls the ACK pin. Setting SDORDYENB to “0” enables
output on ACK pin. Setting SDORDYENB to “1” tristates the pin.
N/A
-
SDORDYENB
ACK
ALE
OE
O
I
SDORDY
ALE
OE
I
CLKE
A0
I
CLKE
A0
I
A1
I
A1
A2
I
A2
1. LOOP4 corresponds to DLOOP0.
2. LOOP5 corresponds to DLOOP1.
3. LOOP6 corresponds to DLOOP2.
4. LOOP7 corresponds to DLOOP3..
50
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 35. Boundary Scan Register (BSR) (Continued)
Pin
Signal
I/O
Type
Bit
Symbol
Bit #
Comments
A3
I
A3
A4
I
A4
LOOP0
LOOP0
LOOP1
LOOP1
LOOP2
LOOP2
LOOP3
LOOP3
LOOP41
LOOP41
LOOP52
LOOP52
LOOP63
LOOP63
LOOP74
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PADD0
PDO0
PADI1
PDO1
PADI2
PDO2
PADI3
PDO3
PADI4
PDO4
PADI5
PDO5
PADI6
PDO6
PADI7
PDOENB controls the LOOP0 through LOOP7 pins.
Setting PDOENB to “0” configures the pins as outputs. The output value
N/A
-
PDOENB
to the pin is set in PDO[0..7].
Setting PDOENB to “1” tristates all the pins. The input value to the pins
can be read in PADD[0..7].
LOOP7
CS
I/O
PDO7
CSB
I
I
MUX
MUX
RESET
MOT/INTL
R/W
I
RSTB
IMB
I
I
RDB
DS
I
WRB
TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
I
TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
I
I
O
O
HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZ1 to “0”
enables output on the pins. Setting HIZ1 to “1” tristates the pins.
N/A
-
HIZ1
1. LOOP4 corresponds to DLOOP0.
2. LOOP5 corresponds to DLOOP1.
3. LOOP6 corresponds to DLOOP2.
4. LOOP7 corresponds to DLOOP3..
Datasheet
51
LXT388 — Dual T1/E1/J1 Transceiver
Table 35. Boundary Scan Register (BSR) (Continued)
Pin
Signal
I/O
Type
Bit
Symbol
Bit #
Comments
RNEG1
LOS1
O
O
I
RNEG1
LOS1
TCLK0
TPOS0
TNEG0
RCLK0
RPOS0
TCLK0
TPOS0
TNEG0
RCLK0
RPOS0
I
I
O
O
HIZ0 controls the RPOS0, RNEG0 and RCLK0 pins. Setting HIZ0 to “0”
enables output on the pins. Setting HIZ0 to “1” tristates the pins.
N/A
-
HIZ0
RNEG0
LOS0
O
O
RNEG0
LOS0
1. LOOP4 corresponds to DLOOP0.
2. LOOP5 corresponds to DLOOP1.
3. LOOP6 corresponds to DLOOP2.
4. LOOP7 corresponds to DLOOP3..
4.4.2
Device Identification Register (IDR)
The IDR register provides access to the manufacturer number, part number and the LXT388
revision. The register is arranged per IEEE 1149.1 and is represented in Table 36. Data into the IDR
is shifted in LSB first.
Table 36. Device Identification Register (IDR)
Bit #
Comments
31 - 28
27 - 12
11 - 1
0
Revision Number
Part Number
Manufacturer Number
Set to “1”
4.4.3
4.4.4
Bypass Register (BYR)
The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the
TDO output.
Analog Port Scan Register (ASR)
The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the
INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to
the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into
the ASR is shifted in LSB first.
52
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 37 shows the 8 possible control codes and the corresponding operation on the analog port.
The Analog Test Port can be used to verify continuity across the coupling transformers primary
winding.
The Analog Test Port can be used to verify continuity across the coupling transformer’s primary
winding as shown in Figure 18. By applying a stimulus to the AT1 input, a known voltage will
appear at AT2 for a given load. This, in effect, tests the continuity of a receive or transmit interface.
Table 37. Analog Port Scan Register (ASR)
ASR Control Code
AT1 Forces Voltage To:
AT2 Senses Voltage From:
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
TTIP0
TTIP1
TRING0
TRING1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RTIP0
RTIP1
RTIP2
RTIP3
RRING0
RRING1
RRING2
RRING3
Reserved
Reserved
Reserved
Reserved
4.4.5
Instruction Register (IR)
The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted
LSB first. Table 38 shows the valid instruction codes and the corresponding instruction description.
Table 38. Instruction Register (IR)
Instruction
Code #
Comments
Connects the BSR to TDI and TDO. Input pins values are loaded into the BSR.
Output pins values are loaded from the BSR.
EXTEST
000
Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through AT1 and
AT2. Refer to Table 37.
INTEST_ANALOG
010
Connects the BSR to TDI and TDO. The normal path between the LXT388 logic and
the I/O pins is maintained. The BSR is loaded with the signals in the I/O pins.
SAMPLE / PRELOAD
IDCODE
100
110
111
Connects the IDR to the TDO pin.
Serial data from the TDI input is passed to the TDO output through the 1 bit Bypass
Register.
BYPASS
Datasheet
53
LXT388 — Dual T1/E1/J1 Transceiver
Figure 18. Analog Test Port Application
JTAG Port
ASR Register
RTIP3
Receiver w/JA 3
Receiver w/JA 2
Transceiver 1
RRING3
n/c
n/c
RTIP2
RRING2
n/c
n/c
RTIP1
RRING1
TTIP1
TRING1
RTIP0
1K
RRING0
Transceiver 0
1K
TTIP0
TRING0
AT2
AT1
54
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
5.0
Test Specifications
Table 39 through Table 58 and Figure 19 through Figure 36 represent the performance
specifications of the LXT388 and are guaranteed by test except, where noted, by design. The
minimum and maximum values listed in Table 41 through Table 58 are guaranteed over the
recommended operating conditions specified in Table Table 40.
Table 39. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
DC supply voltage
Vcc
Tvcc 0-3
Vin
-0.5
-0.5
4.0
7.0
5.5
V
V
V
DC supply voltage
Input voltage on any digital pin
GND-0.5
VCC + 0.5
VCC + 0.5
Input voltage on RTIP, RRING1
Vin
GND-0.5
2000
V
ESD voltage on any Pin 2
Vin
Iin
–
V
Transient latch-up current on any pin
Input current on any digital pin 3
DC input current on TTIP, TRING 3
DC input current on RTIP, RRING 3
Storage temperature
100
10
mA
mA
mA
mA
°C
Iin
-10
–
Iin
±100
±100
+150
Iin
–
Tstor
-65
Case Temperature, 100 pin LQFP
package
T
–
–
120
120
mW
case
Case Temperature, 160 pin PBGA
package
T
°C/W
case
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1. Referenced to ground.
2. Human body model.
3. Constant input current.
Table 40. Recommended Operating Conditions
Parameter
LEN
Sym
Min
Typ
Max
Unit
Test Condition
Digital supply voltage (VCC)
VCC
3.135
3.3
3.465
V
3.3V ± 5%
Transmitter supply voltage, TVCC=5V
nominal
TVCC
4.75
5.0
3.3
5.25
V
V
5V ± 5%
Transmitter supply voltage, TVCC=3.3V
nominal
TVCC
Ta
3.135
3.465
3.3V ± 5%
Ambient operating temperature
-40
-
25
45
+85
60
°C
Average Digital Power Supply Current 1, 4
I
mA
VCC
1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all
channels.
2. Power consumption includes power absorbed by line load and external transmitter components.
3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length
(LEN = 101).
4. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load.
Datasheet
55
LXT388 — Dual T1/E1/J1 Transceiver
Table 40. Recommended Operating Conditions (Continued)
Parameter
LEN
Sym
Min
Typ
Max
Unit
Test Condition
108
60
123
-
mA
mA
100% 1’s
50% 1’s
Average Transmitter Power Supply Current,
T1 Mode 1, 2, 3
I
-
TVCC
Output load at TTIP and TRING
Rl
25
–
–
Ω
Device Power Consumption
LEN
Mode
TVCC
Load
Typ
Max1,2
Unit
Test Condition
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
350
-
470
-
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
50% 1’s
100% 1’s
50% 1’s
100% 1’s
50% 1’s
100% 1’s
50% 1’s
100% 1’s
50% 1’s
100% 1’s
50% 1’s
100% 1’s
75 Ω
000
000
-
330
-
E1
3.3V
120 Ω
100 Ω
75 Ω
430
-
410
-
T13
E1
3.3V
5.0V
5.0V
101-111
000
640
-
470
-
640
-
440
-
120 Ω
100 Ω
000
650
-
580
-
T13
101-111
870
1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all
channels.
2. Power consumption includes power absorbed by line load and external transmitter components.
3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length
(LEN = 101).
4. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load.
Table 41. DC Characteristics
Parameter
Sym
Vih
Min
Typ
Max
Unit
Test Condition
High level input voltage
Low level input voltage
High level output voltage1
Low level output voltage1
2
–
–
–
–
–
–
–
0.8
V
V
V
V
V
Vil
Voh
Vol
2.4
–
VCC
IOUT= 400µA
IOUT= 1.6mA
0.4
Low level input voltage
Vinl
–
1/3VCC-0.2
Midrange level input
voltage
MODE,
LOOP0-3
Vinm
1/3VCC+0.2
1/2VCC
2/3VCC-0.2
V
and
High level input voltage
Low level input current
High level input current
Vinh
Iinl
Iinh
Iil
2/3VCC+0.2
–
–
–
–
V
JASEL
–
50
µA
µA
µA
µA
–
50
Input leakage current
-10
-10
+10
+10
Tri state leakage current
Ihz
56
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 41. DC Characteristics (Continued)
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
Tri state output current
Ihz
–
–
1
µA
TTIP, TRING
2 x 11 Ω series
resistors and 1:2
transformer
mA
Line short circuit current
–
–
–
–
–
–
50
50
RMS
Input Leakage (TMS, TDI, TRST)
µA
Table 42. E1 Transmit Transmission Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
75Ω
2.14
2.7
2.37
3.0
2.60
3.3
V
V
Output pulse
amplitude
–
Tested at the line side
120Ω
75Ω
-0.237
-0.3
0.237
0.3
V
V
Peak voltage of a
space
–
120Ω
Transmit amplitude variation with supply
Difference between pulse sequences
–
–
-1
+1
%
200
mV
For 17 consecutive pulses
Pulse width ratio of the positive and negative
pulses
At the nominal half
amplitude
–
–
0.95
1.05
Transmit transformer turns ratio for
1:2
Rt = 11 Ω ± 1%
75/120Ω characteristic impedance
Note: 51kHz to 102 kHz
Note: Transmit
Note: 102 kHz to 2.048
return loss
15
15
15
17
17
17
dB
dB
dB
Using components in the
LXD384 evaluation board.
MHz
–
–
75 Ω coaxial
cable1
Note: 2.048 MHz to 3.072
MHz
51kHz to 102 kHz
Transmit return
15
15
15
20
20
20
dB
dB
dB
Using components in the
LXD384 evaluation board.
loss 120 Ω twisted
102 kHz to 2.048 MHz
–
–
–
pair cable1
2.048 MHz to 3.072 MHz
Transmit intrinsic jitter; 20Hz to 100kHz
–
0.030
0.050
U.I.
U.I.
U.I.
Tx path TCLK is jitter free
JA Disabled
Bipolar mode
Transmit path delay
2
7
Unipolar mode
1. Guaranteed by design and other correlation methods.
Table 43. E1 Receive Transmission Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
Permissible cable attenuation
Receiver dynamic range
–
–
–
–
12
dB
Vp
@1024 kHz
DR
0.5
–
Per G.703, O.151 @ 6 dB
cable Attenuation
Signal to noise interference margin
S/Ι
-15
–
–
dB
Data decision threshold
Data slicer threshold
SRE
43
50
57
%
Rel. to peak input voltage
–
–
150
–
mV
1. Guaranteed by design and other correlation methods.
Datasheet
57
LXT388 — Dual T1/E1/J1 Transceiver
Table 43. E1 Receive Transmission Characteristics (Continued)
Parameter
Loss of signal threshold
Sym
Min
Typ
Max
Unit
Test Condition
–
–
–
–
200
50
–
–
mV
mV
LOS hysteresis
32
G.775 recommendation
Consecutive zeros before loss of signal
LOS reset
–
–
–
–
–
–
–
2048
ETSI 300 233 specification
12.5%
–
1’s density
Low limit
1Hz to 20Hz
36
1.5
0.2
U.I.
U.I.
U.I.
G735 recommendation
Note 1
input jitter
tolerance 1
20Hz to 2.4kHz
18kHz to 100kHz
–
–
–
Cable Attenuation is 6 dB
Differential receiver input impedance
Input termination resistor tolerance
Common mode input impedance to ground
–
–
–
–
–
–
70
–
–
±1
–
k Ω
%
@1.024 MHz
20
k W
Measured against nominal
impedance using
components in the LXD384
evaluation board.
51 kHz - 102 kHz
20
20
20
dB
dB
dB
Input return
102 - 2048 kHz
loss1
–
–
2048kHz - 3072 kHz
LOS delay time
–
–
–
–
10
–
30
–
σ
marks
U.I.
Data recovery mode
Data recovery mode
Wide band jitter
LOS reset
–
255
Receive intrinsic jitter, RCLK output
0.040 0.0625
Bipolar mode
Receive
1
6
U.I.
JA Disabled
path delay
Unipolar mode
U.I.
1. Guaranteed by design and other correlation methods.
Table 44. T1 Transmit Transmission Characteristics
Parameter
Output pulse amplitude
Sym
Min
Typ
Max
Unit
Test Condition
–
–
–
2.4
-0.15
–
3.0
–
3.6
+0.15
–
V
V
Ω
Measured at the DSX
Peak voltage of a space
Driver output impedance1
1
@ 772 KHz
Transmit amplitude variation with power
supply
–
-1
–
+1
%
Ratio of positive to negative pulse amplitude
Difference between pulse sequences
Pulse width variation at half amplitude
10Hz - 8KHz
–
–
–
0.95
–
–
–
–
1.05
200
20
–
T1.102, isolated pulse
mV
ns
For 17 consecutive
pulses, GR-499-CORE
–
0.020
0.025
0.025
0.050
Jitter added by
8KHz - 40KHz
Transmitter1
AT&T Pub 62411
–
–
–
UI
pk-pk
10Hz - 40KHz
TCLK is jitter free.
Wide Band
Output power
@ 772 KHz
levels2
T1.102 - 1993
12.6
-29
dBm
dBm
–
–
17.9
Referenced to power at
772 KHz
@ 1544 KHz
1. Guaranteed by design and other correlation methods.
2. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern.
58
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 44. T1 Transmit Transmission Characteristics (Continued)
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
With transmit series
resistors (TVCC=5V).
Using components in the
LXD384 evaluation
board.
51kHz to 102 kHz
15
15
15
21
21
21
dB
dB
dB
Transmit return
loss 1
102 kHz to 2.048 MHz
2.048 MHz to 3.072 MHz
–
–
Bipolar mode
2
7
U.I.
U.I.
Transmit path delay
JA Disabled
Unipolar mode
1. Guaranteed by design and other correlation methods.
2. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern.
Table 45. T1 Receive Transmission Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
@ 772 KHz
Permissible cable attenuation
Receiver dynamic range
Signal to noise interference margin
Data decision threshold
Data slicer threshold
–
DR
S/I
SRE
–
–
0.5
-16.5
63
–
–
12
–
dB
Vp
dB
%
–
–
@ 655 ft. of 22 ABAM cable
Rel. to peak input voltage
70
150
200
50
175
–
77
–
–
mV
mV
mV
–
Loss of signal threshold
LOS hysteresis
–
–
–
–
–
–
Consecutive zeros before loss of signal
LOS reset
–
100
12.5%
250
–
T1.231 - 1993
–
–
1’s density
Low limit
0.1Hz to 1Hz
138
28
U.I.
U.I.
U.I.
input jitter
tolerance 1
4.9Hz to 300Hz
10KHz to 100KHz
-
-
-
AT&T Pub. 62411
@772 kHz
0.4
Differential receiver input impedance
Input termination resistor tolerance
Common mode input impedance to ground
-
-
-
-
-
-
70
-
±1
-
k Ω
%
20
-
k Ω
Measured against nominal
impedance. Using
components in the LXD384
evaluation board.
51 KHz - 102 KHz
20
20
20
dB
dB
dB
Input return
102 - 2048 KHz
loss1
-
-
2048 KHz - 3072 KHz
LOS delay time
-
-
-
-
10
-
30
-
µs
-
Data recovery mode
Data recovery mode
Wide band jitter
LOS reset
-
0.035
1
255
Receive intrinsic jitter, RCLK output1
0.0625
U.I.
U.I.
U.I.
Bipolar mode
Receive
JA Disabled
path delay
Unipolar mode
6
1. Guaranteed by design and other correlation methods.
Datasheet
59
LXT388 — Dual T1/E1/J1 Transceiver
Table 46. Jitter Attenuator Characteristics
Parameter
Min
Typ
Max
Unit
Test Condition
32bit
FIFO
-
2.5
-
Hz
JACF =
0
64bit
FIFO
-
-
-
-
-
-
-
3.5
2.5
3.5
3
-
-
-
-
-
-
-
Hz
Hz
Hz
Hz
Hz
Hz
Hz
E1 jitter attenuator 3dB
corner frequency, host
mode1
32bit
FIFO
JACF =
1
64bit
FIFO
32bit
FIFO
Sinusoidal jitter modulation
JACF =
0
64bit
FIFO
3
T1 jitter attenuator 3dB
corner frequency, host
mode1
32bit
FIFO
6
JACF =
1
64bit
FIFO
6
E1
T1
-
-
3.5
6
-
-
Hz
Hz
Jitter attenuator 3dB corner
frequency, hardware mode1
32bit
FIFO
-
-
-
-
17
33
24
56
-
-
-
-
UI
UI
UI
UI
Delay through the Jitter attenuator
only. Add receive and transmit path
delay for total throughput delay.
Data latency delay
64bit
FIFO
32bit
FIFO
Input jitter tolerance before FIFO
overflow or underflow
64bit
FIFO
@ 3 Hz
-0.5
-0.5
+19.5
+19.5
@ 40 Hz
E1 jitter attenuation
@ 400 Hz
ITU-T G.736, See Figure 35 on
page 76
–
–
dB
@ 100 KHz
@ 1 Hz
@ 20 Hz
0
0
AT&T Pub. 62411, See Figure 35 on
page 76
T1 jitter attenuation
@ 1 KHz
@ 1.4 KHz
@ 70 KHz
33.3
40
40
–
–
dB
UI
Output Jitter in remote loopback1
0.060
0.11
ETSI CTR12/13 Output jitter
1. Guaranteed by design and other correlation methods.
60
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 47. Analog Test Port Characteristics
Parameter
3 dB bandwidth
Sym
Min
Typ
Max
Unit
Test Condition
At13db
At1iv
-
5
-
-
MHz
V
Input voltage range
Output voltage range
0
0
VCC
VCC
At2ov
-
V
Figure 19. Transmit Clock Timing Diagram
TCLK
tSUT
tHT
TPOS
TNEG
Table 48. Transmit Timing Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
E1
T1
MCLK
MCLK
–
–
–
2.048
1.544
–
–
–
MHz
MHz
ppm
%
Master clock frequency
Master clock tolerance
Master clock duty cycle
-100
40
219
291
-
100
60
269
356
-
–
–
E1
T1
E1
T1
Tw
244
324
2.048
1.544
–
ns
Output pulse width
Tw
ns
Tclke1
Tclkt1
Tclkt
Tclkb
Tdc
MHz
MHz
ppm
MHz
%
Transmit clock frequency
-
-
Transmit clock tolerance
Transmit clock burst rate
Transmit clock duty cycle
-50
-
+50
20
90
–
Gapped transmit clock
NRZ mode
10
–
RZ mode (TCLK = H for
>16 clock cycles)
E1 TPOS/TNEG pulse width (RZ mode)
Tmpwe1
236
–
252
ns
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
Delay time OE Low to driver High Z
Tsut
Tht
20
20
-
-
-
-
-
ns
ns
µs
µs
Toez
Ttz
-
1
Delay time TCLK Low to driver High Z
50
60
75
Datasheet
61
LXT388 — Dual T1/E1/J1 Transceiver
Table 49. Receive Timing Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Condition
E1
T1
–
–
–
±80
–
ppm
Relative to
nominal frequency
Clock recovery capture range
MCLK = ±100
ppm
–
±180
–
ppm
Receive clock duty cycle 1
Receive clock pulse width 1
Rckd
Tpw
40
50
488
648
244
324
244
324
–
60
529
713
285
389
285
389
–
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
E1
T1
E1
T1
E1
T1
447
583
203
259
203
259
20
Tpw
Tpwl
Tpwl
Tpwh
Tpwh
Tr
Receive clock pulse width Low time
Receive clock pulse width High time
Rise/fall time 4
@ CL=15 pF
E1
T1
E1
T1
E1
T1
Tpwdl
Tpwdl
200
250
200
200
200
200
–
244
324
244
324
244
324
–
300
400
–
RPOS/RNEG pulse width (MCLK=H) 2
RPOS/RNEG to RCLK rising setup time
Tsur
–
–
RCLK Rising to RPOS/RNEG hold time
Thr
–
Delay time between RPOS/RNEG and RCLK
–
5
MCLK = H 3
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK
duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823).
2. Clock recovery is disabled in this mode.
3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit.
4. For all digital outputs.
Figure 20. Receive Clock Timing Diagram
tPW
RCLK
tPWH
tSUR
tPWL
tHR
RPOS
RNEG
CLKE = 1
tSUR
tHR
RPOS
RNEG
CLKE = 0
62
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 50. Intel Mode Read Timing Characteristics
Parameter2
Sym
Min
Typ1
Max
Unit
Test Conditions
Address setup time to latch
Tsalr
Tvl
10
30
10
0
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Valid address latch pulse width
Latch active to active read setup time
Chip select setup time to active read
Chip select hold time from inactive read
Address hold time from inactive ALE
Active read to data valid delay time
Address setup time to RD inactive
Address hold time from RD inactive
Inactive read to data tri-state delay time
Valid read signal pulse width
Tslr
Tscsr
Thcsr
Thalr
Tprd
Thar
Tsar
0
5
10
1
–
–
–
–
–
–
–
–
–
50
–
5
–
Tzrd
Tvrd
Tint
3
35
–
60
–
Inactive read to inactive INT delay time
Active chip select to RDY delay time
Active ready Low time
10
12
40
3
Tdrdy
Tvrdy
Trdyz
0
–
Inactive ready to tri-state delay time
–
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C = 100pF on D0-D7, all other outputs are loaded with 50pF.
L
Table 51. JTAG Timing Characteristics
Parameter
Sym
Min
Typ
Max
Unit
Test Conditions
Cycle time
Tcyc
Tsut
Tht
200
50
50
-
-
-
-
-
-
-
ns
ns
ns
ns
J-TMS/J-TDI to J-TCK rising edge time
J-CLK rising to J-TMS/L-TDI hold time
J-TCLK falling to J-TDO valid
-
Tdod
50
Figure 21. JTAG Timing
tCYC
TCK
tSUR
tHT
TMS
TDI
tDOD
TDO
Datasheet
63
LXT388 — Dual T1/E1/J1 Transceiver
Figure 22. Non-Multiplexed Intel Mode Read Timing
tSAR
ADDRESS
A4 - A0
ALE
tHAR
(pulled High)
tHCSR
tSCSR
CS
RD
tVRD
tPRD
tZRD
D7 - D0
INT
DATA OUT
tINT
tDRDY
tRDYZ
tDRDY
tVRDY
Tristate
Tristate
RDY
64
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 23. Multiplexed Intel Read Timing
tVL
tSLR
ALE
tSCSR
tHSCR
CS
tVRD
tPRD
RD
tSALR
tZRD
DATA OUT
tINT
tHALR
ADDRESS
AD7-AD0
INT
tDRDY
tDRDY
tVRDY
tRDYZ
Tristate
Tristate
RDY
Table 52. Intel Mode Write Timing Characteristics
Parameter2
Sym
Min
Typ1
Max
Unit
Test Conditions
Address setup time to latch
Tsalw
Tvl
10
30
10
0
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Valid address latch pulse width
Latch active to active write setup time
Chip select setup time to active write
Chip select hold time from inactive write
Address hold time from inactive ALE
Data valid to write active setup time
Data hold time to active write
Tslw
Tscsw
Thcsw
Thalw
Tsdw
Thdw
Thaw
Tsaw
0
5
40
30
2
–
–
–
–
–
–
–
–
Address setup time to WR inactive
Address hold time from WR inactive
6
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C = 100pF on D0-D7, all other outputs are loaded with 50pF.
L
3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset
Operation and Host Mode sections for more information.
Datasheet
65
LXT388 — Dual T1/E1/J1 Transceiver
Table 52. Intel Mode Write Timing Characteristics (Continued)
Parameter2
Sym
Min
Typ1
Max
Unit
Test Conditions
Valid write signal pulse width
Inactive write to inactive INT delay time
Chip select to RDY delay time3
Active ready Low time
Tvwr
Tint
60
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
10
12
40
3
Tdrdy
Tvrdy
Trdyz
0
–
Inactive ready to tri-state delay time3
–
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C = 100pF on D0-D7, all other outputs are loaded with 50pF.
L
3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset
Operation and Host Mode sections for more information.
Figure 24. Non-Multiplexed Intel Mode Write Timing
tSAW
A4-A0
ALE
CS
ADDRESS
(pulled High)
tHAW
tSCSW
tHCSW
tVWR
WR
tHDW
tSDW
D7-D0
INT
WRITE DATA
tINT
tDRDY
tDRDY
tVRDY
tRDYZ
Tristate
Tristate
RDY
66
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 25. Multiplexed Intel Mode Write Timing
tSLW
ALE
CS
tVL
tSCSW
tHCSW
tVWR
WR
tHALW
tHDW
tSDW
tSALW
ADDRESS
WRITE DATA
tINT
AD7-AD0
INT
tDRDY
tDRDYZ
tDRDY
tVRDY
Tristate
Tristate
RDY
Table 53. Motorola Bus Read Timing Characteristics
Parameter2
Sym
Min
Typ1
Max
Unit
Test Conditions
Address setup time to address or data strobe
Address hold time from address or data strobe
Valid address strobe pulse width
Tsar
Thar
10
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Tvas
Tsrw
95
10
0
–
R/W setup time to active data strobe
–
R/W hold time from inactive data strobe
Chip select setup time to active data strobe
Chip select hold time from inactive data strobe
Address strobe active to data strobe active delay
Delay time from active data strobe to valid data
Delay time from inactive data strobe to data High Z
Valid data strobe pulse width
Thrw
Tscs
–
0
–
Thcs
Tasds
Tpds
Tdz
0
–
20
3
–
30
30
–
3
Tvds
Tint
60
–
Inactive data strobe to inactive INT delay time
Data strobe inactive to address strobe inactive delay
DS asserted to ACK asserted delay
10
–
Tdsas
Tdackp
Tdack
Tpack
15
–
40
10
0
DS deasserted to ACK deasserted delay
Active ACK to valid data delay
–
–
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C = 100pF on D0-D7, all other outputs are loaded with 50pF.
L
Datasheet
67
LXT388 — Dual T1/E1/J1 Transceiver
Figure 26. Non-Multiplexed Motorola Mode Read Timing
ADDRESS
tSAR tHAR
A4-A0
AS
(pulled High)
tSRW
tHRW
R/W
tSCS
tHCS
CS
DS
tVDS
tPDS
tDZ
D7-D0
INT
DATA OUT
tINT
tDACKP
tPACK
tDACK
ACK
68
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 27. Multiplexed Motorola Mode Read Timing
tVAS
tDSAS
AS
tSRW
tHRW
R/W
tSCS
tHCS
CS
tASDS
tVDS
DS
tPDS
tSAR
tHAR
tDZ
DATA OUT
ADDRESS
D7-D0
INT
tINT
tDACKP
tDACK
tPACK
ACK
Table 54. Motorola Mode Write Timing Characteristics
Parameter2
Sym
Min
Typ1
Max
Unit
Test Conditions
Address setup time to address strobe
Address hold time to address strobe
Valid address strobe pulse width
Tsas
Thas
Tvas
Tsrw
Thrw
Tscs
Thcs
Tasds
Tsdw
Thdw
Tvds
Tint
10
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
95
10
0
–
R/W setup time to active data strobe
R/W hold time from inactive data strobe
Chip select setup time to active data strobe
Chip select hold time from inactive data strobe
Address strobe active to data strobe active delay
Data setup time to DS deassertion
–
–
0
–
0
–
20
40
30
60
–
–
–
Data hold time from DS deassertion
Valid data strobe pulse width
–
–
Inactive data strobe to inactive INT delay time
10
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C = 100pF on D0-D7, all other outputs are loaded with 50pF.
L
Datasheet
69
LXT388 — Dual T1/E1/J1 Transceiver
Table 54. Motorola Mode Write Timing Characteristics (Continued)
Parameter2
Sym
Min
Typ1
Max
Unit
Test Conditions
Data strobe inactive to address strobe inactive delay
Active data strobe to ACK output enable time
DS asserted to ACK asserted delay
Tdsas
Tdack
15
0
–
–
–
–
ns
ns
ns
12
40
Tdackp
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C = 100pF on D0-D7, all other outputs are loaded with 50pF.
L
Figure 28. Non-Multiplexed Motorola Mode Write Timing
A4-A0
AS
ADDRESS
tSAS
tHAS
(pulled High)
tSRW
tHRW
tHCS
R/W
CS
tSCS
tVDS
DS
tSDW
tHDW
WRITE DATA
D7-D0
INT
tINT
tDACKP
tDACK
ACK
70
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 29. Multiplexed Motorola Mode Write Timing
tVAS
tDSAS
AS
tHRW
tSRW
R/W
tHCS
tSCS
CS
tASDS
tVDS
DS
tHDW
tSDW
tSAS
tHAS
ADDRESS
WRITE DATA
tINT
D7-D0
INT
tDACKP
tDACK
ACK
Table 55. Serial I/O Timing Characteristics
Parameter
Rise/fall time any pin
Sym
Min
Typ1
Max
Unit
Test Condition
Trf
Tdc
-
-
-
-
-
-
-
-
-
-
-
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load 1.6mA, 50 pF
SDI to SCLK setup time
SCLK to SDI hold time
SCLK Low time
5
-
-
Tcdh
Tcl
5
25
25
-
-
SCLK High time
Tch
-
SCLK rise and fall time
CS falling edge to SCLK rising edge
Last SCLK edge to CS rising edge
CS inactive time
Tr, Tf
Tcc
50
-
10
10
50
-
Tcch
Tcwh
Tcdv
-
-
SCLK to SDO valid delay time
5
SCLK falling edge or CS rising edge to SDO
High Z
Tcdz
-
10
-
ns
1. Typical figures are at 25 C° and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
71
LXT388 — Dual T1/E1/J1 Transceiver
Figure 30. Serial Input Timing
CS
t
CWH
t
CC
t
CH
t
CCH
t
CL
SCLK
SDI
tCDH
tCDH
t
DC
LSB
LSB
MSB
CONTROL BYTE
DATA BYTE
Figure 31. Serial Output Timing
CLKE = 0
2
3
4
5
6
6
7
7
8
8
9
10
11
12
13
14
15
16
1
SCLK
CS
tCCH
t
CDZ
SDO
4
0
9
1
2
3
5
6
7
CLKE = 1
2
3
4
5
10
11
12
13
14
15
16
1
SCLK
CS
t
CCH
t
CDZ
4
0
1
2
3
5
6
7
SDO
Table 56. Transformer Specifications3
Primary
Inductance
mH
Leakage
Inductance
µH
Interwinding
Capacitance
pF
Dielectric Breakdown
DCR
Ω
(max.)
Voltage
Tx/Rx
Turns Ratio1
V2
(min.)
(max.)
(max.)
(min.)
0.70 pri
TX
RX
1:2
1:2
1.2
1.2
0.60
0.60
60
60
1500 Vrms
1500 Vrms
1.20 sec
1.10 pri
1.10 sec
1. Transformer turns ratio accuracy is ± 2%.
2. This parameter is application dependent.LIU side: Line side.
3. Refer to the FAQ or Application Note “Transformer Specification for Intel Transceiver Applications “ for recommended
magnetics.
72
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Table 57. G.703 2.048 Mbit/s Pulse Mask Specifications
Cable
Unit
Parameter
TWP
120
Coax
Test load impedance
75
Ω
V
Nominal peak mark voltage
3.0
2.37
Nominal peak space voltage
0 ±0.30
244
0 ±0.237
244
V
Nominal pulse width
ns
%
%
Ratio of positive and negative pulse amplitudes at center of pulse
Ratio of positive and negative pulse amplitudes at nominal half amplitude
95-105
95-105
95-105
95-105
Figure 32. E1, G.703 Mask Templates
269 ns
(244+25)
V = 100%
194 ns
(244- 50)
NOMINAL PULSE
50%
244 ns
219 ns
(244-25)
0%
20%
488 ns
(244+244)
Table 58. T1.102 1.544 Mbit/s Pulse Mask Specifications
Cable
Parameter
Unit
TWP
Test load impedance
100
3.0
Ω
V
Nominal peak mark voltage
Nominal peak space voltage
Nominal pulse width
0 ±0.15
324
V
ns
%
Ratio of positive and negative pulse amplitudes
95-105
Datasheet
73
LXT388 — Dual T1/E1/J1 Transceiver
Figure 33. T1, T1.102 Mask Templates
1.20
1.00
0.80
0.60
0.40
0.20
0.00
-0.80
-0.60
-0.40
-0.20
0.00
-0.20
0.20
0.40
0.60
0.80
1.00
1.20
-0.40
-0.60
Time [UI]
74
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 34. Jitter Tolerance Performance
1000 UI
100 UI
28 UI
@ 4.9 Hz
AT&T 62411, Dec 1990 (T1)
18 UI @ 1.8 Hz
LXT388 typ.
28 UI
@ 300 Hz
10 UI
GR-499-CORE, Dec 1995 (T1)
5 UI @ 500 Hz
0.4 UI
ITU G.823, Mar 1993 (E1)
@ 10 kHz
1 UI
1.5 UI
@ 2.4 kHz
1.5 UI
@ 20 Hz
0.2 UI
@ 18 kHz
0.1 UI @ 8 kHz
.1 UI
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
Datasheet
75
LXT388 — Dual T1/E1/J1 Transceiver
Figure 35. Jitter Transfer Performance
10 dB
E1
ITU G.736 Template
0.5 dB @ 40Hz
0.5 dB @ 3Hz
0 dB
-10 dB
-20 dB
-30 dB
f 3dB =2.5 Hz
-19.5 dB @ 20 kHz
-19.5 dB @ 400 Hz
f 3dB =3.5 Hz
-40 dB
-60 dB
LXT388 typ.
-80 dB
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz 100 kHz
Frequency
10 dB
0 dB @ 1 Hz
0 dB @ 20 Hz 0.1 dB @ 40 Hz
0.5 dB @ 350 Hz
T1
0 dB
AT&T Pub 62411
GR-253-CORE
TR-TSY-000009
-10 dB
-6 dB @
2 Hz
-20 dB
-30 dB
-33.3 dB @ 1 kHz
-33.7 dB @ 2.5kHz
-40 dB @ 1.4 kHz
f 3dB = 3 Hz
-40 dB @ 70 kHz
-49.2 dB @ 15kHz
f 3dB = 6 Hz
-40 dB
-60 dB
-80 dB
LXT388 typ.
-60 dB @ 57 Hz
1 Hz
10 Hz
100 Hz
1 kHz
10 kHz 100 kHz
Frequency
76
Datasheet
Dual T1/E1/J1 Transceiver — LXT388
Figure 36. Output Jitter for CTR12/13 applications
0.2
0.15
0.1
LXT388 typ, f 3dB = 2.5Hz & 3.5 Hz
0.05
0
10 Hz
20 Hz
100 Hz
1 kHz
10 kHz
100 kHz
Frequency
5.1
Recommendations and Specifications
AT&T
Pub 62411
ANSI T1.102 - 199X Digital Hierarchy Electrical Interface
ANSI T1.231 - 1993 Digital Hierarchy Layer 1 In-Service Digital Transmission Performance
Monitoring
Bellcore
Bellcore
Bellcore
G.703
G. 704
G.735
TR-TSY-000009 Asynchronous Digital Multiplexes Requirements and Objectives
GR-253-CORE SONET Transport Systems Common Generic Criteria
GR-499-CORE Transport Systems Generic Requirements
Physical/electrical characteristics of hierarchical digital interfaces
Functional characteristics of interfaces associated with network nodes
Characteristics of Primary PCM multiplex equipment operating at 2048 kbit/s and
offering digital access at 384 kbit/s and/or synchronous digital access at 64 kbit/s
Characteristics of a synchronous digital multiplex equipment operating at 2048
kbit/s
G.736
G.772
G.775
Protected Monitoring Points provided on Digital Transmission Systems
Loss of signal (LOS) and alarm indication (AIS) defect detection and clearance
criteria
G.783
G.823
O.151
Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional
Blocks
The control of jitter and wander within digital networks which are based on the
2048 kbit/s hierarchy
Specification of instruments to measure error performance in digital systems
OFTEL OTR-001 Short Circuit Current Requirements
ETS 300166 Physical and Electrical Characteristics
ETS 300386-1 Electromagnetic Compatibility Requirement
Datasheet
77
LXT388 — Dual T1/E1/J1 Transceiver
6.0
Mechanical Specifications
Figure 37. Low Quad Flat Package (LQFP) Dimensions
100 Pin LQFP
•
•
Part Number LXT388LE
Extended Temperature Range (-40°C to 85° C)
ALL DIMENSIONS IN MILLIMETERS
All dimensions and tolerances conform to ANSI Y14.5M-1982.
16.00 BSC
14.00 BSC
12.00 BSC
0.22
±0.05
16.00 BSC
14.00 BSC 12.00 BSC
Pin #1 Index
0.50
BSC
2 3
1
See Detail "A"
1.60
max
0.05 min
0.15 max
1.40 ±0.05
DETAIL "A"
0.20
min
0.60
±0.15
1.00
REF
78
Datasheet
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