LXT9785BC [ETC]

LAN TRANSCEIVER|OCTAL|BGA|241PIN|PLASTIC ; LAN收发器|八路| BGA | 241PIN |塑料\n


型号：	LXT9785BC
厂家：	ETC
描述：	LAN TRANSCEIVER\|OCTAL\|BGA\|241PIN\|PLASTIC LAN收发器\|八路\| BGA \| 241PIN \|塑料\n 局域网
文件：	总138页 (文件大小：1573K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LXT9785

Advanced 10/100 8-Port PHY

Datasheet

The LXT9785 is an 8-port Fast Ethernet PHY Transceiver that supports IEEE 802.3 physical

layer applications at both 10Mbps and 100Mbps. This device provides both Serial/Source

Synchronous (SMII/SS-SMII) and Reduced Media Independent (RMII) Interfaces for switching

and other independent port applications.

All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for

both 10Mbps or 100Mbps (10BASE-T and 100BASE-TX) Ethernet over twisted-pair, or

100Mbps (100BASE-FX) Ethernet over fiber-optic media .

The LXT9785 provides three discrete LED driver outputs for each port. The device supports

both half-duplex and full-duplex operation at 10Mbps and 100Mbps and requires only a single

2.5V power supply.

Applications

■ 10BASE-T, 10/100BASE-TX, or

100BASE-FX Switches and multi-port

NICs.

Product Features

■ Eight IEEE 802.3-compliant 10BASE-T or ■ JTAG boundary scan.

100BASE-TX ports with integrated filters.

■ 2.5V operation.

■ Multiple RMII or SMII/SS-SMII ports for

independent PHY port operation.

■ Optimized for dual-high stacked RJ-45

■ Configurable via MDIO port or external

applications.

control pins.

■ Proprietary Optimal Signal Processing™

architecture improves SNR by 3 dB over

ideal analog filters.

■ Low power consumption; 250 mW per port

typical.

■ Auto MDIX crossover capabilities.

■ 208-pin PQFP and 241-pin BGA packages.

■ Robust baseline wander correction.

■ 100BASE-FX fiber-optic capability on all

■ MDIO sectionalization into 2x4 or 1x8

ports.

configurations.

■ Supports both auto-negotiation systems and

legacy systems without auto-negotiation

capability.

As of January 15, 2001, this document replaces the Level One document

known as LXT9785 Advanced 10/100 8-Port PHY Datasheet.

Order Number: 249241-002

January 2001

Information in this document is provided in connection with Intel^®products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The LXT9785 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current

characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling

1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Contents

1.0

Pin Assignments and Signal Descriptions....................................................12

1.1 Signal Name Conventions...................................................................................39

Functional Description...........................................................................................51

2.0

2.1

Introduction..........................................................................................................51

2.1.1 OSP™ Architecture................................................................................51

2.1.2 Comprehensive Functionality.................................................................51

2.1.2.1 Sectionalization .........................................................................52

Interface Descriptions..........................................................................................52

2.2.1 10/100 Network Interface .......................................................................52

2.2.1.1 Twisted-Pair Interface ...............................................................53

2.2.1.2 MDI Crossover (MDIX)..............................................................53

2.2.1.3 Fiber Interface ...........................................................................53

Media Independent Interface (MII) Interfaces .....................................................53

2.3.1 Global MII Mode Select..........................................................................54

2.3.2 Internal Loopback...................................................................................54

2.3.3 RMII Data Interface ................................................................................54

2.3.4 Serial Media Independent Interface (SMII) and Source Synchronous Data

Interfaces54

2.2

2.3

2.3.4.1 SMII Interface ............................................................................54

2.3.4.2 Source Synchronous Interface ..................................................55

2.3.5 Configuration Management Interface.....................................................55

2.3.6 MII Isolate...............................................................................................55

2.3.6.1 MDIO Management Interface....................................................55

2.3.6.2 MII Sectionalization ...................................................................57

2.3.6.3 MII Interrupts .............................................................................57

2.3.6.4 Hardware Control Interface .......................................................57

Operating Requirements .....................................................................................58

2.4.1 Power Requirements..............................................................................58

2.4.2 Clock/SYNC Requirements....................................................................58

2.4.2.1 Reference Clock........................................................................58

2.4.2.2 TxClk Signal (SS-SMII only)......................................................58

2.4.2.3 TxSYNC Signal (SMII/SS-SMII) ................................................58

2.4.2.4 RxSYNC Signal (SS-SMII only).................................................58

2.4.2.5 RxCLK Signal (SS-SMII only)....................................................58

Initialization..........................................................................................................59

2.5.1 MDIO Control Mode ...............................................................................59

2.5.2 Hardware Control Mode .........................................................................59

2.5.3 Power-Down Mode.................................................................................60

2.5.3.1 Global (Hardware) Power Down................................................60

2.5.3.2 Port (Software) Power Down.....................................................61

2.5.4 Reset......................................................................................................61

2.5.5 Hardware Configuration Settings ...........................................................62

Link Establishment ..............................................................................................62

2.6.1 Auto-Negotiation.....................................................................................62

2.6.1.1 Base Page Exchange................................................................62

2.6.1.2 Next Page Exchange.................................................................62

2.4

2.5

2.6

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.6.1.3 Controlling Auto-Negotiation .....................................................63

2.6.1.4 Link Criteria ...............................................................................63

2.6.1.5 Parallel Detection ......................................................................63

Serial MII Operation ............................................................................................64

2.7.1 SMII Reference Clock ............................................................................67

2.7.2 TxSYNC Pulse (SMII/SS-SMII)..............................................................67

2.7.3 Transmit Data Stream............................................................................67

2.7.3.1 Transmit Enable ........................................................................67

2.7.3.2 Transmit Error ...........................................................................67

2.7.4 Receive Data Stream.............................................................................68

2.7.4.1 Carrier Sense ............................................................................68

2.7.4.2 Receive Data Valid....................................................................68

2.7.4.3 Receive Error ............................................................................68

2.7.4.4 Receive Status Encoding ..........................................................68

2.7.5 Collision..................................................................................................68

2.7.5.1 Source Synchronous SMII.........................................................70

RMII Operation....................................................................................................74

2.8.1 RMII Reference Clock............................................................................74

2.8.2 Transmit Enable.....................................................................................74

2.8.3 Carrier Sense & Data Valid....................................................................74

2.8.4 Receive Error .........................................................................................74

2.8.5 Out-of-Band Signalling...........................................................................74

2.8.6 4B/5B Coding Operations ......................................................................74

100Mbps Operation.............................................................................................78

2.9.1 100BASE-X Network Operations ...........................................................78

2.9.2 100BASE-X Protocol Sublayer Operations............................................78

2.9.2.1 PCS Sublayer............................................................................78

2.9.3 PMA Sublayer ........................................................................................80

2.9.3.1 Twisted-Pair PMD Sublayer......................................................82

2.9.3.2 Fiber PMD Sublayer..................................................................82

10Mbps Operation...............................................................................................83

2.10.1 Preamble Handling.................................................................................83

2.10.2 Dribble Bits.............................................................................................83

2.10.3 Link Test.................................................................................................83

2.10.3.1Link Failure................................................................................84

2.10.4 Jabber ....................................................................................................84

Monitoring Operations.........................................................................................84

2.11.1 Monitoring Auto-Negotiation...................................................................84

2.11.2 Per-Port LED Driver Functions...............................................................84

2.11.3 Out-of-Band Signalling...........................................................................85

2.11.4 Boundary Scan Interface........................................................................86

2.11.5 State Machine ........................................................................................86

2.11.6 Instruction Register ................................................................................86

2.11.7 Boundary Scan Register ........................................................................87

2.7

2.8

2.9

2.10

2.11

3.0

Application Information.........................................................................................88

3.1

3.2

Design Recommendations..................................................................................88

General Design Guidelines .................................................................................88

3.2.1 Power Supply Filtering ...........................................................................88

3.2.2 Power and Ground Plane Layout Considerations..................................89

3.2.2.1 Chassis Ground.........................................................................89

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

3.2.3 MII Terminations.....................................................................................89

3.2.4 Twisted-Pair Interface ............................................................................90

3.2.4.1 Magnetics Information ...............................................................90

3.2.5 The Fiber Interface.................................................................................90

3.2.6 LED Circuit .............................................................................................90

Typical Application Circuits .................................................................................92

3.3

4.0

5.0

6.0

Test Specifications..................................................................................................94

Package Specifications .......................................................................................136

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figures

LXT9785 Block Diagram .....................................................................................11

LXT9785 RMII 208-Pin PQFP Assignments .......................................................12

LXT9785 SMII 208-Pin PQFP Assignments .......................................................13

LXT9785 SS-SMII 208-Pin PQFP Assignments .................................................14

LXT9785 RMII 241-Ball PBGA Assignments ......................................................15

LXT9785 SMII 241-Ball PBGA Assignments ......................................................16

LXT9785 SS-SMII 241-Ball PBGA Assignments ................................................17

LXT9785 Interfaces.............................................................................................52

Internal Loopback................................................................................................54

Management Interface Read Frame Structure....................................................56

Management Interface Write Frame Structure....................................................56

Port Address Scheme .........................................................................................56

Interrupt Logic .....................................................................................................57

Initialization Sequence ........................................................................................60

Auto-Negotiation Operation.................................................................................63

Typical SMII Interface Diagram...........................................................................65

Typical SMII Quad Sectionalization Diagram......................................................66

100Mbps Serial MII Data Flow............................................................................67

Serial MII Transmit Synchronization ...................................................................68

Serial MII Receive Synchronization ....................................................................69

Typical SS-SMII Interface Diagram.....................................................................71

Typical SS-SMII Quad Sectionalization Diagram................................................72

Source Synchronous Transmit Timing................................................................73

Source Synchronous Receive Timing.................................................................73

RMII Data Flow ...................................................................................................75

Typical RMII Interface Diagram...........................................................................76

Typical RMII Quad Sectionalization Diagram......................................................77

100BASE-X Frame Format .................................................................................78

Protocol Sublayers..............................................................................................79

LED Pulse Stretching..........................................................................................85

RMII Programmable Out-of-Bank Signaling........................................................86

LED Circuit..........................................................................................................91

Power and Ground Supply Connections.............................................................92

Typical Twisted-Pair Interface.............................................................................93

Typical Fiber Interface.........................................................................................93

SMII - 100BASE-TX Receive Timing ..................................................................98

SMII - 100BASE-TX Transmit Timing .................................................................99

SMII - 100BASE-FX Receive Timing ................................................................100

SMII - 100BASE-FX Transmit Timing ...............................................................101

SMII - 10BASE-T Receive Timing.....................................................................102

SMII - 10BASE-T Transmit Timing....................................................................103

Source Synchronous SMII 100BASE-TX Receive Timing ................................104

Source Synchronous SMII 100BASE-TX Transmit Timing ...............................105

Source Synchronous SMII - 100BASE-FX Receive Timing..............................106

Source Synchronous SMII - 100BASE-FX Transmit Timing.............................107

Source Synchronous SMII - 10BASE-T Receive Timing ..................................108

Source Synchronous SMII - 10BASE-T Transmit Timing .................................109

RMII - 100BASE-TX Receive Timing ................................................................110

RMII - 100BASE-TX Transmit Timing ...............................................................111

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

RMII - 100BASE-FX Receive Timing ................................................................112

RMII - 100BASE-FX Transmit Timing ...............................................................113

RMII - 10BASE-T Receive Timing.....................................................................114

RMII - 10BASE-T Transmit Timing....................................................................115

Auto-Negotiation and Fast Link Pulse Timing ...................................................116

Fast Link Pulse Timing......................................................................................116

MDIO Write Timing (MDIO Sourced by MAC)...................................................117

MDIO Read Timing (MDIO Sourced by PHY) ...................................................117

Power-Up Timing...............................................................................................118

Reset Recovery Timing.....................................................................................118

PHY Identifier Bit Mapping ................................................................................122

LXT9785 208-Pin PQFP Plastic Package Specification....................................136

LXT9785 241-Ball PBGA Package Specification (LXT9785BC) .......................137

Tables

RMII PQFP Pin List .............................................................................................18

SMII PQFP Pin List .............................................................................................25

SS-SMII PQFP Pin List .......................................................................................32

LXT9785 RMII Signal Descriptions .....................................................................39

LXT9785 SMII / SS-SMII Common Signal Descriptions......................................41

LXT9785 SMII Specific Signal Descriptions........................................................41

LXT9785 SS-SMII Specific Signal Descriptions..................................................42

MDIO Control Interface Signals...........................................................................43

LXT9785 Signal Detect .......................................................................................44

LXT9785 Network Interface Signal Descriptions.................................................44

LXT9785 JTAG Test Signal Descriptions............................................................45

LXT9785 Miscellaneous Signal Descriptions ......................................................46

LXT9785 LED Signal Descriptions......................................................................48

LXT9785 Power Supply Signal Descriptions.......................................................49

Unused / Reserved Pins......................................................................................50

MDIX Selection....................................................................................................53

MII Mode Select ..................................................................................................54

Global Hardware Configuration Settings.............................................................62

SMII Signal Summary..........................................................................................64

RX Status Encoding Bit Definitions .....................................................................69

Source Synchronous SMII..................................................................................70

4B/5B Coding ......................................................................................................80

BSR Mode of Operation ......................................................................................87

Supported JTAG Instructions ..............................................................................87

Magnetics Requirements.....................................................................................91

Absolute Maximum Ratings.................................................................................94

Operating Conditions...........................................................................................94

Digital I/O Characteristics (VCCIO = 2.5V +/- 5%)..............................................95

Digital I/O Characteristics (VCCIO = 3.3V +/- 5%)..............................................96

Required Clock Characteristics...........................................................................96

100BASE-TX Transceiver Characteristics ..........................................................96

100BASE-FX Transceiver Characteristics ..........................................................97

10BASE-T Transceiver Characteristics...............................................................97

SMII - 100BASE-TX Receive Timing Parameters...............................................98

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

SMII - 100BASE-TX Transmit Timing Parameters..............................................99

SMII - 100BASE-FX Receive Timing Parameters.............................................100

SMII - 100BASE-FX Transmit Timing Parameters............................................101

SMII - 10BASE-T Receive Timing Parameters .................................................102

SMII-10BASE-T Transmit Timing Parameters ..................................................103

Source Synchronous SMII 100BASE-TX Receive Timing Parameters.............104

Source Synchronous SMII 100BASE-TX Transmit Timing ...............................105

Source Synchronous SMII - 100BASE-FX Receive Timing Parameters ..........106

Source Synchronous SMII - 100BASE-FX Transmit Timing Parameters .........107

Source Synchronous SMII - 10BASE-T Receive Timing Parameters...............108

Source Synchronous SMII - 10BASE-T Transmit Timing Parameters..............109

RMII - 100BASE-TX Receive Timing Parameters.............................................110

RMII - 100BASE-TX Transmit Timing Parameters............................................111

RMII - 100BASE-FX Receive Timing Parameters.............................................112

RMII - 100BASE-FX Transmit Timing Parameters............................................113

RMII - 10BASE-T Receive Timing Parameters.................................................114

RMII - 10BASE-T Transmit Timing Parameters................................................115

Auto-Negotiation and Fast Link Pulse Timing Parameters ...............................116

MDIO Timing Parameters .................................................................................117

Power-Up Timing Parameters..........................................................................118

Reset Recovery Timing Parameters .................................................................118

Control Register (Address 0).............................................................................120

Status Register (Address 1)..............................................................................121

PHY Identification Register 1 (Address 2).........................................................122

PHY Identification Register 2 (Address 3).........................................................122

Auto-Negotiation Advertisement Register (Address 4)4 ...................................123

Auto-Negotiation Link Partner Base Page Ability Register (Address 5)............124

Auto-Negotiation Expansion (Address 6)..........................................................125

Auto-Negotiation Next Page Transmit Register (Address 7).............................125

Auto-Negotiation Link Partner Next Page Receive Register (Address 8) .........126

Port Configuration Register (Address 16, Hex 10)............................................127

Quick Status Register (Address 17, Hex 11) ....................................................128

Interrupt Enable Register (Address 18, Hex 12) ...............................................128

Interrupt Status Register (Address 19, Hex 13) ................................................130

LED Configuration Register (Address 20, Hex 14) ...........................................131

Receive Error Count Register (Address 21)......................................................132

RMII Out-of-Band Signalling Register (Address 25) .........................................133

Trim Enable Register (Address 27)...................................................................133

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Revision History

Date

Revision

Description

January 2001

002

Global: Add bar to all LEDm_n for active low status.

Tables 1, 2 and 3: Add RMII, SMII, and SS-SMII numeric pin lists.

Introduction: Deleted “(up to 100 meters)” and “(up to 185 meters)”.

Sectionalization: Change second sentence.

SMII/SS-SMII Interfaces: Delete text from “SMII Interface: “The SMII interface only operates with

VCCIO at 3.3V (refer to Table 26 on page 73).”

Reference Clock: Changed language.

Simplified SMII Application Diagram: Delete old Figure 17 -- redundant.

Under Purpose, switch descriptions for TXD and RXD.

Per-Port LED Driver Functions: Add text to third paragraph after first line:

LED Circuits: Add LED Circuit text and diagram.

Power and Ground Connections: Add 0.1 µF capacitor value to figure.

Typical Twisted-Pair Interface: Change capacitor value from 0.1 µF to .01 µF.

Delete old Figure 35 and old Table 33, SMII Sync Timing (Parameters)

Delete Old Figure 37 Typical RMII Interface -- redundant.

Absolute Maximum Ratings: Change Operating temperature for Case under Max from “120” to

“+120”.

Operating Conditions: Two lines for Recommended Supply Voltage for VCCPECL are:

I/O (SD_2P5V = 0); Sym=VCCPECL; Min=3.14; Typ (2.5)=2.5; Typ (3.3)=3.3; Max=3.46

I/O (SD_2P5V = 1): Sym= VCCPECL; Min=2.38; TypTyp=2.5 ; Max=2.53. For Supply Voltage, I/O

(SD_205V = 1) under Max, change value from “2.53” to “2.63”.

Delete Table note 3

Digital I/O Characteristics (2.5V): Change Output Low Voltage/Max = 0.2 (was 0.1); Output High

voltage/Min = 2.07 (was 2.27). Add to Input Low voltage SD pins: Sym=VIL-SD, Max=0.755V.

Add to Input High voltage SD pins: Sym=VIH-SD, Min=1.58V. Add new line: Output Low voltage

(LEDn_m pins)

Digital I/O Characteristics (3.3V): Add new table.

Required Clock Characteristics: Delete “Input Low voltage” and “Input High voltage” lines.

100BASE-FX Transceiver Characteristics: Remove TBDs.

Modify all timing diagrams and related tables due to completion of Intel’s design verification testing.

Control Register (Address 0): Restructure table notes.

Status Register (Address 1): Change as follows: 1 = Extended register capabilities

0 = Basic register capabilities.

Auto-Negotiation Advertisement Register (Address 4): Add table note 4: “Restart Auto-Negotiation

process whenever Register 4 is written/modified.” Table note 2: Change pin “79” to pin “50”. Table

note 3: Change “LED/CFG” to “CFG”.

Port Configuration Register (Address 16, Hex 10): For Register bit 16.7 under description, change

to: “Write as one. Ignore on read”. (changed from zero)

Receive Error Count Register: Add text to paragraph under Description.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 1. LXT9785 Block Diagram

8 Port Global

Functions

RMII/SMII Contr

ADD_<4:0>

Management /

RESET

Mode Select

Logic & LED

Drivers

MDIO

PWRDN

MDC

Clock

Generator

REFCLK

MDINT

SYNC (SMII only)

Manchester

Encoder

Driver

Pulse

Shaper

TXDn

TP /

Fiber

Out

TPFOPn

TPFONn

Parallel/Serial

Converter

Scrambler

& Encoder

100

ECL

Driver

Auto

Negotiation

Mgmt

Counters

CIM

Fiber

select n

Media

Select

Clock Generator

Adaptive EQ with BL

Wander Cancellation

100TX

100FX

10BT

Port LED

Drivers

LEDn_<2:0>

RXDn

Manchester

TPFIPn

TPFINn

TP /

Fiber In

Serial to

Parallel

Converter

Decoder

Slicer

Decoder &

Descrambler

100

Carrier Sense

Data Valid

Error Detect

Per-Port Functions

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

1.0

Pin Assignments and Signal Descriptions

Figure 2. LXT9785 RMII 208-Pin PQFP Assignments

CRS_DV6..... 1

RXER6..... 2

TXEN6..... 3

TXD6_0..... 4

TXD6_1..... 5

REFCLK1..... 6

RXD5_1..... 7

RXD5_0..... 8

GNDIO..... 9

156 .......TPFIN7

155 .......GNDR7

154 .......TPFOP7

153 .......TPFON7

152 .......VCCT6/7

151 .......TPFON6

150 .......TPFOP6

149 .......GNDR6

148 .......GNDT6/7

147 .......TPFIN6

146 .......TPFIP6

145 .......VCCR6

144 .......VCCR5

143 .......TPFIP5

142 .......TPFIN5

141 .......GNDR5

140 .......TPFOP5

139 .......TPFON5

138 .......VCCT4/5

137 .......TPFON4

136 .......TPFOP4

135 .......GNDR4

134 .......GNDT4/5

133 .......TPFIN4

132 .......TPFIP4

131 .......VCCR4

130 .......VCCR3

129 .......TPFIP3

128 .......TPFIN3

127 .......GNDT2/3

126 .......GNDR3

125 .......TPFOP3

124 .......TPFON3

123 .......VCCT2/3

122 .......TPFON2

121 .......TPFOP2

120 .......GNDR2

119 .......TPFIN2

118 .......TPFIP2

117 .......VCCR2

116 .......VCCR1

115 .......TPFIP1

114 .......TPFIN1

113 .......GNDT0/1

112 .......GNDR1

111 .......TPFOP1

110 .......TPFON1

109 .......VCCT0/1

108 .......TPFON0

107 .......TPFOP0

106 .......GNDR0

105 .......TPFIN0

CRS_DV5..... 10

RXER5..... 11

TXEN5..... 12

TXD5_0..... 13

TXD5_1..... 14

RXD4_1..... 15

RXD4_0..... 16

CRS_DV4..... 17

VCCIO..... 18

GNDIO..... 19

RXER4..... 20

TXEN4..... 21

TXD4_0..... 22

TXD4_1..... 23

MDC1..... 24

MDIO1..... 25

MDINT1..... 26

RXD3_1..... 27

RXD3_0..... 28

VCCIO..... 29

GNDIO..... 30

CRS_DV3..... 31

RXER3..... 32

TXEN3..... 33

TXD3_0..... 34

TXD3_1..... 35

RXD2_1..... 36

RXD2_0..... 37

GNDIO..... 38

CRS_DV2..... 39

RXER2..... 40

TXEN2..... 41

TXD2_0..... 42

TXD2_1..... 43

REFCLK0..... 44

RXD1_1..... 45

RXD1_0..... 46

VCCIO..... 47

GNDIO..... 48

CRS_DV1..... 49

ER1/PAUSE..... 50

TXEN1..... 51

TXD1_0..... 52

Part #

LOT #

FPO #

LXT9785 XX

XXXXXX

XXXXXXXX

Rev #

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 3. LXT9785 SMII 208-Pin PQFP Assignments

N/C..... 1

N/C..... 2

N/C..... 3

TXD6..... 4

N/C..... 5

156 .......TPFIN7

155 .......GNDR7

154 .......TPFOP7

153 .......TPFON7

152 .......VCCT6/7

151 .......TPFON6

150 .......TPFOP6

149 .......GNDR6

148 .......GNDT6/7

147 .......TPFIN6

146 .......TPFIP6

145 .......VCCR6

144 .......VCCR5

143 .......TPFIP5

142 .......TPFIN5

141 .......GNDR5

140 .......TPFOP5

139 .......TPFON5

138 .......VCCT4/5

137 .......TPFON4

136 .......TPFOP4

135 .......GNDR4

134 .......GNDT4/5

133 .......TPFIN4

132 .......TPFIP4

131 .......VCCR4

130 .......VCCR3

REFCLK1..... 6

N/C..... 7

RXD5..... 8

GNDIO..... 9

N/C..... 10

N/C..... 11

N/C..... 12

TXD5..... 13

N/C..... 14

N/C..... 15

RXD4..... 16

N/C..... 17

VCCIO..... 18

GNDIO..... 19

N/C..... 20

N/C..... 21

TXD4..... 22

N/C..... 23

MDC1..... 24

MDIO1..... 25

MDINT1..... 26

N/C..... 27

RXD3..... 28

VCCIO..... 29

GNDIO..... 30

N/C..... 31

Part #

LOT #

FPO #

LXT9785 XX

XXXXXX

XXXXXXXX

Rev #

129 .......TPFIP3

128 .......TPFIN3

127 .......GNDT2/3

126 .......GNDR3

125 .......TPFOP3

124 .......TPFON3

123 .......VCCT2/3

122 .......TPFON2

121 .......TPFOP2

120 .......GNDR2

119 .......TPFIN2

118 .......TPFIP2

117 .......VCCR2

116 .......VCCR1

115 .......TPFIP1

114 .......TPFIN1

113 .......GNDT0/1

112 .......GNDR1

111 .......TPFOP1

110 .......TPFON1

109 .......VCCT0/1

108 .......TPFON0

107 .......TPFOP0

106 .......GNDR0

105 .......TPFIN0

N/C..... 32

N/C..... 33

TXD3..... 34

SYNC0..... 35

N/C..... 36

RXD2..... 37

GNDIO..... 38

N/C..... 39

N/C..... 40

N/C..... 41

TXD2..... 42

N/C..... 43

REFCLK0..... 44

N/C..... 45

RXD1..... 46

VCCIO..... 47

GNDIO..... 48

N/C..... 49

PAUSE..... 50

N/C..... 51

TXD1..... 52

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 4. LXT9785 SS-SMII 208-Pin PQFP Assignments

N/C..... 1

N/C..... 2

N/C..... 3

TXD6..... 4

N/C..... 5

156 .......TPFIN7

155 .......GNDR7

154 .......TPFOP7

153 .......TPFON7

152 .......VCCT6/7

151 .......TPFON6

150 .......TPFOP6

149 .......GNDR6

148 .......GNDT6/7

147 .......TPFIN6

146 .......TPFIP6

145 .......VCCR6

144 .......VCCR5

143 .......TPFIP5

142 .......TPFIN5

141 .......GNDR5

140 .......TPFOP5

139 .......TPFON5

138 .......VCCT4/5

137 .......TPFON4

136 .......TPFOP4

135 .......GNDR4

134 .......GNDT4/5

133 .......TPFIN4

132 .......TPFIP4

131 .......VCCR4

130 .......VCCR3

129 .......TPFIP3

128 .......TPFIN3

127 .......GNDT2/3

126 .......GNDR3

125 .......TPFOP3

124 .......TPFON3

123 .......VCCT2/3

122 .......TPFON2

121 .......TPFOP2

120 .......GNDR2

119 .......TPFIN2

118 .......TPFIP2

117 .......VCCR2

116 .......VCCR1

115 .......TPFIP1

114 .......TPFIN1

113 .......GNDT0/1

112 .......GNDR1

111 .......TPFOP1

110 .......TPFON1

109 .......VCCT0/1

108 .......TPFON0

107 .......TPFOP0

106 .......GNDR0

105 .......TPFIN0

REFCLK1..... 6

RXD5..... 7

N/C..... 8

GNDIO..... 9

N/C..... 10

N/C..... 11

N/C..... 12

TXD5..... 13

N/C..... 14

RXD4..... 15

N/C..... 16

RX_SYNC1..... 17

VCCIO..... 18

GNDIO..... 19

N/C..... 20

RX_CLK1..... 21

TXD4..... 22

N/C..... 23

MDC1..... 24

MDIO1..... 25

MDINT1..... 26

RXD3..... 27

N/C..... 28

VCCIO..... 29

GNDIO..... 30

N/C..... 31

Part #

LOT #

FPO #

LXT9785 XX

XXXXXX

XXXXXXXX

Rev #

TX_CLK0..... 32

N/C..... 33

TXD3..... 34

TX_SYNC0..... 35

RXD2..... 36

N/C..... 37

GNDIO..... 38

N/C..... 39

N/C..... 40

N/C..... 41

TXD2..... 42

N/C..... 43

REFCLK0..... 44

RXD1..... 45

N/C..... 46

VCCIO..... 47

GNDIO..... 48

N/C..... 49

PAUSE..... 50

N/C..... 51

TXD1..... 52

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 5. LXT9785 RMII 241-Ball PBGA Assignments

RMI

CRS_D

GNDD

VCCIO

RXD1_0

TXD2_1

TXD3_1

TXEN3

VCCIO

GNDD

MDIO1

TXD4_0

RXER4

RXD4_0

TXEN5

RXER5

TXD6_1

RXER6

CRS_D

CRS_

DV6

RXD0_1

VCCIO

GNDD

TXEN1

GNDD

TXD1_0

GNDD

RXD1_1

TXD2_0

GNDD

RXD2_0

TXEN2

GNDD

RXD2_1

RXER2

GNDD

RXD3_1

MDINT1

RXD3_0

GNDD

MDC1

TXD4_1

GNDD

TXEN4

VCCIO

TXD5_1

GNDD

TXD5_0

GNDD

TXD6_0

GNDD

VCCD

RXD5_0

TXEN6

VCCIO

TXD7_0

RXD7_1

N/C

RXD5_1

RXD6_0

GNDD

RXD6_1

GNDD

CRS_D

RXD0_0

RXER3

RXD4_1

TXD7_1

TXEN7

RXD7_0

LED7_3

N/C

RXER0/

MDIX

RXER1/

PAUSE

CRS_D

TXD1_1

TXD3_0

RXER7

GNDD

CRS_D

REF

CLK0

REF

CLK1

CRS_D

MDC0

TXD0_0

LED3_1

N/C

TXEN0

MDIO0

LED3_2

LED2_2

LED1_2

LED0_1

CFG_2

ADD_2

GNDD

VCCD

N/C

MDINT0

LED2_3

LED1_3

LED0_3

TXD0_1

LED3_3

N/C

LED7_2

LED6_3

LED5_3

LED4_3

LED4_2

LED7_1

LED6_1

LED5_1

N/C

LED2_1

N/C

GNDD

N/C

LED6_2

LED5_2

LED4_1

LED1_1

N/C

VCCD

N/C

VCCD

SGND

AMDIX_

LED0_2

CFG_3

ADD_3

ADD_0

SD0

VCC

PECL

VCC

PECL

PWR

DWN

SEC

TION

MODE

SEL_0

MODE

SEL_1

MDDIS

CFG_1

ADD_1

ADD_4

TxSLE

W_1

GND

PECL

GND

PECL

G_FX/

RESET

TDO

TCK

TMS

SD5

TRST

SD7

TxSLE

W_0

SD1

SD3

VCCT

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

TDI

SD_2P5

SD2

VCCR

GNDR

GNDT

VCCR

GNDT

SD4

SD6

TPFIP

(0)

TPFON(

TPFIP

(2)

TPFIN

(3)

TPFON

(4)

TPFIP

(6)

TPFOP

(7)

TPFIP

(7)

GNDT

TPFIN

(0)

TPFOP

(0)

TPFOP

(1)

TPFIN

(1)

TPFIN

(2)

TPFOP

(2)

TPFON

(3)

TPFIP

(3)

TPFIP

(4)

TPFOP

(4)

TPFOP

(5)

TPFIN

(5)

TPFIN

(6)

TPFOP

(6)

TPFON

(7)

TPFIN

(7)

TPFON

(0)

TPFIP

(1)

TPFON

(2)

TPFOP

(3)

TPFIN

(4)

TPFON

(5)

TPFIP

(5)

TPFON

(6)

GNDT

GNDR

GNDT

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 6. LXT9785 SMII 241-Ball PBGA Assignments

SMI

GNDD

VCCIO

RXD1

N/C

SYNC0

N/C

VCCIO

GNDD

MDIO1

TXD4

N/C

RXD4

N/C

RXD0

MDIX

GNDD

TXD1

N/C

TXD2

GNDD

PAUSE

GNDD

VCCD

N/C

RXD2

N/C

GNDD

N/C

MDC1

N/C

VCCIO

N/C

TXD5

GNDD

TXD6

GNDD

VCCD

RXD5

N/C

RXD6

GNDD

N/C

VCCIO

GNDD

MDINT1

RXD3

SYNC1

N/C

GNDD

N/C

GNDD

N/C

GNDD

N/C

TXD3

GNDD

VCCIO

TXD7

N/C

REF

CLK0

REF

CLK1

MDC0

TXD0

LED3_1

N/C

GNDD

RXD7

GNDD

LED7_2

LED6_3

LED5_3

LED4_3

LED4_2

MDINT0

LED2_3

LED1_3

LED0_3

MDIO0

LED3_2

LED2_2

LED1_2

LED0_1

CFG_2

ADD_2

N/C

LED7_3

N/C

LED3_3

N/C

LED7_1

LED6_1

LED5_1

N/C

LED2_1

N/C

GNDD

N/C

LED6_2

LED5_2

LED4_1

LED1_1

N/C

VCCD

N/C

VCCD

SGND

AMDIX_

LED0_2

CFG_3

ADD_3

ADD_0

SD0

VCC

PECL

VCC

PECL

PWR

DWN

SECTIO

MODE

SEL_0

MODE

SEL_1

MDDIS

CFG_1

ADD_1

ADD_4

TxSLE

W_1

GND

PECL

GND

PECL

G_FX/

RESET

TDO

TCK

TMS

SD5

TRST

SD7

TxSLE

W_0

SD1

SD3

VCCT

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

TDI

SD_2P5

SD2

VCCR

GNDR

GNDT

VCCR

GNDT

SD4

SD6

TPFIP

(0)

TPFON(

TPFIP

(2)

TPFIN

(3)

TPFON(

TPFIP

(6)

TPFOP(

TPFIP

(7)

GNDT

TPFIN(

TPFOP(

TPFIN(

TPFOP(

TPFON(

TPFIP

(3)

TPFIP

(4)

TPFOP(

TPFIN

(5)

TPFIN

(6)

TPFOP(

TPFON(

TPFIN(

TPFON(

TPFIP

(1)

TPFON(

TPFOP(

TPFIN

(4)

TPFON(

TPFIP

(5)

TPFON(

GNDT

GNDR

GNDT

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 7. LXT9785 SS-SMII 241-Ball PBGA Assignments

SS-

SMI

TX_SY

NC0

GNDD

VCCIO

N/C

VCCIO

GNDD

MDIO1

TXD4

N/C

RX_

CLK1

RX_SY

NC1

RXD0

VCCIO

GNDD

N/C

RXD0

MDIX

GNDD

TXD1

GNDD

RXD1

N/C

TXD2

GNDD

PAUSE

GNDD

VCCD

N/C

GNDD

RXD2

N/C

RXD3

MDINT1

N/C

MDC1

N/C

TXD5

GNDD

TXD6

N/C

RXD5

N/C

RXD6

TX_CL

TX_SY

NC1

VCCIO

N/C

RXD4

N/C

GNDD

TX_CL

N/C

GNDD

TXD3

GNDD

VCCIO

TXD7

RXD7

N/C

GNDD

N/C

RX_

CLK0

Rx_SY

NC0

REF

CLK0

REF

CLK1

MDC0

TXD0

LED3_1

N/C

GNDD

VCCD

N/C

GNDD

LED7_2

LED6_3

LED5_3

LED4_3

LED4_2

MDINT0

LED2_3

LED1_3

LED0_3

MDIO0

LED3_2

LED2_2

LED1_2

LED0_1

CFG_2

ADD_2

N/C

LED3_3

N/C

LED7_3

N/C

LED7_1

LED6_1

LED5_1

N/C

LED2_1

N/C

GNDD

N/C

LED6_2

LED5_2

LED4_1

LED1_1

N/C

VCCD

N/C

VCCD

SGND

AMDIX_

LED0_2

CFG_3

ADD_3

ADD_0

SD0

VCC

PECL

VCC

PECL

PWR

DWN

SEC

TION

MODE

SEL_0

MODE

SEL_1

MDDIS

CFG_1

ADD_1

ADD_4

TxSLE

W_1

GND

PECL

GND

PECL

G_FX/

RESET

TDO

TCK

TMS

SD5

TRST

SD7

TxSLE

W_0

SD1

SD3

VCCT

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

VCCT

VCCR

GNDR

TDI

SD_2P

SD2

VCCR

GNDR

GNDT

VCCR

GNDT

SD4

SD6

TPFIP

(0)

TPFON

(1)

TPFIP

(2)

TPFIN

(3)

TPFON

(4)

TPFIP

(6)

TPFOP

(7)

TPFIP

(7)

GNDT

TPFIN

(0)

TPFOP

(0)

TPFOP

(1)

TPFIN

(1)

TPFIN

(2)

TPFOP

(2)

TPFON

(3)

TPFIP

(3)

TPFIP

(4)

TPFOP

(4)

TPFOP

(5)

TPFIN

(5)

TPFIN

(6)

TPFOP

(6)

TPFON

(7)

TPFIN

(7)

TPFON

(0)

TPFIP

(1)

TPFON

(2)

TPFOP

(3)

TPFIN

(4)

TPFON

(5)

TPFIP

(5)

TPFON

(6)

GNDT

GNDR

GNDT

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List

Reference for Full

Description

Symbol

Type¹

CRS_DV6

RXER6

TXEN6

O, TS, SL

O, TS, SL, ID

I, ID

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 8 on page 43

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

TXD6_0

TXD6_1

REFCLK1

RXD5_1

RXD5_0

GNDIO

I, ID

O, TS, ID

O, TS

–

CRS_DV5

RXER5

TXEN5

O, TS, SL

O, TS, SL, ID

I, ID

TXD5_0

TXD5_1

RXD4_1

RXD4_0

CRS_DV4

VCCIO

I, ID

O, TS,ID

O, TS

O, TS, SL

–

GNDIO

–

RXER4

TXEN4

O, TS, SL, ID

I, ID

TXD4_0

TXD4_1

MDC1

I, ID

I, ST, ID

I/O, TS, SL, IP

OD, TS, SL, IP

O, TS, ID

O, TS

MDIO1

MDINT1

RXD3_1

RXD3_0

VCCIO

–

GNDIO

–

CRS_DV3

RXER3

TXEN3

O, TS, SL

O, TS, SL, ID

I, ID

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

TXD3_0

I, ID

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 12 on page 46

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

Table 12 on page 46

Table 4 on page 39

Table 8 on page 43

Table 14 on page 49

Table 8 on page 43

TXD3_1

RXD2_1

RXD2_0

GNDIO

O, TS, ID

O, TS

–

CRS_DV2

RXER2

O, TS, SL

O, TS, SL, ID

TXEN2

I, ID

TXD2_0

TXD2_1

REFCLK0

RXD1_1

RXD1_0

VCCIO

I, ID

O, TS, ID

O, TS

–

GNDIO

–

CRS_DV1

O, TS, SL

RXER1/PAUSE O, TS, SL, ID

TXEN1

I, ID

TXD1_0

TXD1_1

RXD0_1

RXD0_0

VCCIO

I, ID

O, TS, ID

O, TS

–

GNDIO

–

CRS_DV0

RXER0/MDIX

TXEN0

O, TS, SL

O, TS, SL, ID

I, ID

TXD0_0

TXD0_1

MDC0

I, ID

I, ST, ID

MDIO0

I/O, TS, SL, IP

VCCD

–

GNDD

–

MDINT0

OD, TS, SL, IP

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

100

101

LED3_3

OD, TS, SO, IP

OD, TS, SL, IP

–

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 12 on page 46

Table 8 on page 43

Table 12 on page 46

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

LED3_2

LED3_1

LED2_3

LED2_2

LED2_1

GNDIO

LED1_3

LED1_2

LED1_1

VCCD

OD, TS, SL, IP

–

GNDD

–

LED0_3

LED0_2

LED0_1

AMDIX_EN

MDDIS

CFG_3

CFG_2

CFG_1

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

TxSLEW_1

TxSLEW_0

SD_2P5V

SD0

OD, TS, SL, IP

I, ST, IP

I, ST, ID

SD1

VCCPECL

GNDPECL

SD2

–

SD3

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

N/C

–

Table 15 on page 50

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

VCCR0

TPFIP0

TPFIN0

GNDR0

TPFOP0

TPFON0

VCCT0/1

TPFON1

TPFOP1

GNDR1

GNDT0/1

TPFIN1

TPFIP1

VCCR1

VCCR2

TPFIP2

TPFIN2

GNDR2

TPFOP2

TPFON2

VCCT2/3

TPFON3

TPFOP3

GNDR3

GNDT2/3

TPFIN3

TPFIP3

VCCR3

VCCR4

TPFIP4

TPFIN4

GNDT4/5

GNDR4

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

TPFOP4

AO/AI

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 15 on page 50

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

Table 11 on page 45

TPFON4

VCCT4/5

TPFON5

TPFOP5

GNDR5

TPFIN5

TPFIP5

VCCR5

VCCR6

TPFIP6

TPFIN6

GNDT6/7

GNDR6

TPFOP6

TPFON6

VCCT6/7

TPFON7

TPFOP7

GNDR7

TPFIN7

TPFIP7

VCCR7

N/C

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

AO/AI

–

N/C

–

SD4

SD5

GNDPECL

VCCPECL

SD6

–

SD7

TDI

I, ST, IP

O, TS

I, ST, IP

TDO

TMS

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

TCK

I, ST, ID

Table 11 on page 45

Table 15 on page 50

Table 12 on page 46

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 4 on page 39

Table 14 on page 49

Table 4 on page 39

TRST

I, ST, IP

N/C

–

G_FX/TP

PWRDWN

RESET

Section

ModeSel0

ModeSel1

SGND

I, ST, ID

I, ST, IP

I, ST, ID

–

LED4_1

LED4_2

LED4_3

GNDD

OD, TS, SL, IP

–

VCCD

–

LED5_1

LED5_2

LED5_3

GNDIO

LED6_1

LED6_2

LED6_3

LED7_1

LED7_2

LED7_3

GNDD

OD, TS, SL, IP

–

OD, TS, SL, IP

–

VCCD

–

RXD7_1

RXD7_0

GNDIO

CRS_DV7

RXER7

TXEN7

TXD7_0

O, TS, ID

O, TS

–

O, TS, SL

O, TS, SL, ID

I, ID

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 1. RMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

204

205

206

207

208

TXD7_1

I, ID

Table 4 on page 39

Table 14 on page 49

RXD6_1

RXD6_0

GNDIO

VCCIO

O, TS, ID

O, TS

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak Internal

Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 2. SMII PQFP Pin List

Reference for Full

Symbol

Type¹

Description

N/C

–

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 6 on page 41

Table 14 on page 49

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 6 on page 41

Table 15 on page 50

Table 14 on page 49

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 8 on page 43

Table 15 on page 50

Table 6 on page 41

Table 14 on page 49

Table 15 on page 50

N/C

–

N/C

–

TXD6

N/C

I, ID

REFCLK1

N/C

–

RXD5

GNDIO

N/C

O, TS

–

N/C

–

N/C

–

TXD5

N/C

I, ID

–

N/C

O, TS,ID

RXD4

N/C

O, TS

–

VCCIO

GNDIO

N/C

–

O, TS, SL, ID

N/C

I, ID

TXD4

N/C

I, ID

–

MDC1

MDIO1

MDINT1

N/C

I, ST, ID

I/O, TS, SL, IP

OD, TS, SL, IP

–

RXD3

VCCIO

GNDIO

N/C

O, TS

–

N/C

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

TXD3

I, ID

Table 5 on page 41

Table 6 on page 41

Table 15 on page 50

Table 6 on page 41

Table 14 on page 49

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 6 on page 41

Table 14 on page 49

Table 15 on page 50

Table 12 on page 46

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 6 on page 41

Table 14 on page 49

Table 15 on page 50

Table 12 on page 46

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 8 on page 43

Table 14 on page 49

Table 8 on page 43

SYNC0

N/C

I, ID

–

RXD2

GNDIO

N/C

O, TS

–

N/C

–

N/C

–

TXD2

N/C

I, ID

–

REFCLK0

N/C

–

RXD1

VCCIO

GNDIO

N/C

O, TS

–

PAUSE

N/C

I, ID

–

TXD1

N/C

I, ID

–

N/C

–

RXD0

VCCIO

GNDIO

N/C

O, TS

–

MDIX

N/C

I, ID

–

TXD0

N/C

I, ID

–

MDC0

MDIO0

VCCD

GNDD

MDINT0

I, ST, ID

I/O, TS, SL, IP

–

OD, TS, SL, IP

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

100

101

LED3_3

OD, TS, SO, IP

OD, TS, SL, IP

–

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 12 on page 46

Table 8 on page 43

Table 12 on page 46

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

LED3_2

LED3_1

LED2_3

LED2_2

LED2_1

GNDIO

LED1_3

LED1_2

LED1_1

VCCD

OD, TS, SL, IP

–

GNDD

–

LED0_3

LED0_2

LED0_1

AMDIX_EN

MDDIS

CFG_3

CFG_2

CFG_1

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

TxSLEW_1

TxSLEW_0

SD_2P5V

SD0

OD, TS, SL, IP

I, ST, IP

I, ST, ID

SD1

VCCPECL

GNDPECL

SD2

–

SD3

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

N/C

–

Table 15 on page 50

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

VCCR0

TPFIP0

TPFIN0

GNDR0

TPFOP0

TPFON0

VCCT0/1

TPFON1

TPFOP1

GNDR1

GNDT0/1

TPFIN1

TPFIP1

VCCR1

VCCR2

TPFIP2

TPFIN2

GNDR2

TPFOP2

TPFON2

VCCT2/3

TPFON3

TPFOP3

GNDR3

GNDT2/3

TPFIN3

TPFIP3

VCCR3

VCCR4

TPFIP4

TPFIN4

GNDT4/5

GNDR4

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

TPFOP4

TPFON4

VCCT4/5

TPFON5

TPFOP5

GNDR5

TPFIN5

TPFIP5

VCCR5

VCCR6

TPFIP6

TPFIN6

GNDT6/7

GNDR6

TPFOP6

TPFON6

VCCT6/7

TPFON7

TPFOP7

GNDR7

TPFIN7

TPFIP7

VCCR7

N/C

AO/AI

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 15 on page 50

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

Table 11 on page 45

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

N/C

–

SD4

SD5

GNDPECL

VCCPECL

SD6

–

SD7

TDI

I, ST, IP

O, TS

I, ST, IP

TDO

TMS

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

TCK

I, ST, ID

Table 11 on page 45

Table 15 on page 50

Table 12 on page 46

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 4 on page 39

Table 6 on page 41

Table 14 on page 49

Table 15 on page 50

Table 5 on page 41

TRST

I, ST, IP

N/C

–

G_FX/TP

PWRDWN

RESET

Section

ModeSel0

ModeSel1

SGND

I, ST, ID

I, ST, IP

I, ST, ID

–

LED4_1

LED4_2

LED4_3

GNDD

VCCD

OD, TS, SL, IP

–

LED5_1

LED5_2

LED5_3

GNDIO

LED6_1

LED6_2

LED6_3

LED7_1

LED7_2

LED7_3

GNDD

VCCD

OD, TS, SL, IP

–

OD, TS, SL, IP

–

N/C

O, TS, ID

RXD7

O, TS

GNDIO

N/C

–

N/C

–

N/C

–

TXD7

I, ID

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 2. SMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

204

205

206

207

208

SYNC1

I, ID

Table 6 on page 41

Table 15 on page 50

Table 6 on page 41

Table 14 on page 49

N/C

–

O, TS

–

RXD6

GNDIO

VCCIO

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List

Reference for Full

Description

Symbol

Type¹

N/C

–

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 5 on page 41

Table 7 on page 42

Table 15 on page 50

Table 14 on page 49

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 7 on page 42

Table 15 on page 50

Table 7 on page 42

Table 14 on page 49

Table 15 on page 50

Table 7 on page 42

Table 5 on page 41

Table 15 on page 50

Table 8 on page 43

Table 7 on page 42

Table 15 on page 50

Table 14 on page 49

Table 15 on page 50

Table 7 on page 42

Table 15 on page 50

N/C

–

N/C

–

TXD6

N/C

I, ID

REFCLK1

RXD5

N/C

O, TS, ID

–

GNDIO

N/C

–

N/C

–

N/C

–

TXD5

N/C

I, ID

–

RXD4

N/C

O, TS, ID

–

RX_SYNC1

VCCIO

GNDIO

N/C

O, TS, ID

–

RX_CLK1

TXD4

N/C

O, TS, ID

I, ID

–

MDC1

MDIO1

MDINT1

RXD3

N/C

I, ST, ID

I/O, TS, SL, IP

OD, TS, SL, IP

O, TS, ID

–

VCCIO

GNDIO

N/C

–

TX_CLK0

N/C

I, ID

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

TXD3

I, ID

Table 5 on page 41

Table 7 on page 42

Table 15 on page 50

Table 14 on page 49

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 5 on page 41

Table 7 on page 42

Table 15 on page 50

Table 14 on page 49

Table 15 on page 50

Table 12 on page 46

Table 15 on page 50

Table 5 on page 41

Table 15 on page 50

Table 7 on page 42

Table 15 on page 50

Table 14 on page 49

Table 7 on page 42

Table 12 on page 46

Table 7 on page 42

Table 5 on page 41

Table 15 on page 50

Table 8 on page 43

Table 14 on page 49

Table 8 on page 43

TX_SYNC0

RXD2

N/C

I, ID

O, TS, ID

–

GNDIO

N/C

–

N/C

–

N/C

–

TXD2

N/C

I, ID

–

REFCLK0

RXD1

N/C

O, TS, ID

–

VCCIO

GNDIO

N/C

–

PAUSE

N/C

I, ID

–

TXD1

N/C

I, ID

–

RXD0

N/C

O, TS, ID

–

VCCIO

GNDIO

RX_SYNC0

MDIX

–

O, TS, ID

I, ID

RX_CLK0

TXD0

N/C

–

I, ID

–

MDC0

MDIO0

VCCD

GNDD

MDINT0

I, ST, ID

I/O, TS, SL, IP

–

OD, TS, SL, IP

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

100

101

LED3_3

OD, TS, SO, IP

OD, TS, SL, IP

–

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 12 on page 46

Table 8 on page 43

Table 12 on page 46

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

LED3_2

LED3_1

LED2_3

LED2_2

LED2_1

GNDIO

LED1_3

LED1_2

LED1_1

VCCD

OD, TS, SL, IP

–

GNDD

–

LED0_3

LED0_2

LED0_1

AMDIX_EN

MDDIS

CFG_3

CFG_2

CFG_1

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

TxSLEW_1

TxSLEW_0

SD_2P5V

SD0

OD, TS, SL, IP

I, ST, IP

I, ST, ID

SD1

VCCPECL

GNDPECL

SD2

–

SD3

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

N/C

–

Table 15 on page 50

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

VCCR0

TPFIP0

TPFIN0

GNDR0

TPFOP0

TPFON0

VCCT0/1

TPFON1

TPFOP1

GNDR1

GNDT0/1

TPFIN1

TPFIP1

VCCR1

VCCR2

TPFIP2

TPFIN2

GNDR2

TPFOP2

TPFON2

VCCT2/3

TPFON3

TPFOP3

GNDR3

GNDT2/3

TPFIN3

TPFIP3

VCCR3

VCCR4

TPFIP4

TPFIN4

GNDT4/5

GNDR4

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

TPFOP4

TPFON4

VCCT4/5

TPFON5

TPFOP5

GNDR5

TPFIN5

TPFIP5

VCCR5

VCCR6

TPFIP6

TPFIN6

GNDT6/7

GNDR6

TPFOP6

TPFON6

VCCT6/7

TPFON7

TPFOP7

GNDR7

TPFIN7

TPFIP7

VCCR7

N/C

AO/AI

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 10 on page 44

Table 14 on page 49

Table 15 on page 50

Table 9 on page 44

Table 14 on page 49

Table 9 on page 44

Table 11 on page 45

AO/AI

–

AO/AI

–

AI/AO

–

AI/AO

–

AO/AI

–

AO/AI

–

AI/AO

–

N/C

–

SD4

SD5

GNDPECL

VCCPECL

SD6

–

SD7

TDI

I, ST, IP

O, TS

I, ST, IP

TDO

TMS

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Symbol

Type¹

Description

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

TCK

I, ST, ID

Table 11 on page 45

Table 15 on page 50

Table 12 on page 46

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 13 on page 48

Table 14 on page 49

Table 7 on page 42

Table 15 on page 50

Table 14 on page 49

Table 15 on page 50

Table 7 on page 42

Table 15 on page 50

Table 5 on page 41

TRST

I, ST, IP

N/C

–

G_FX/TP

PWRDWN

RESET

Section

ModeSel0

ModeSel1

SGND

I, ST, ID

I, ST, IP

I, ST, ID

–

LED4_1

LED4_2

LED4_3

GNDD

OD, TS, SL, IP

–

VCCD

–

LED5_1

LED5_2

LED5_3

GNDIO

LED6_1

LED6_2

LED6_3

LED7_1

LED7_2

LED7_3

GNDD

OD, TS, SL, IP

–

OD, TS, SL, IP

–

VCCD

–

RXD7

O, TS, ID

N/C

–

GNDIO

N/C

–

TX_CLK1

N/C

I, ID

–

TXD7

I, ID

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 3. SS-SMII PQFP Pin List (Continued)

Reference for Full

Description

Symbol

Type¹

204

205

206

207

208

TX_SYNC1

RXD6

I, ID

Table 7 on page 42

Table 15 on page 50

Table 14 on page 49

O, TS, ID

N/C

–

GNDIO

VCCIO

1. AI=Analog Input, AO=Analog Output, I=Input, O=Output,

OD=Open Drain output, ST=Schmitt Triggered input, TS=Tri-

State-able output, SL=Slew-rate Limited output, IP=Weak

Internal Pull-up, ID=Weak Internal Pull-down

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

1.1

Signal Name Conventions

Signal names may contain either a port designation or a serial designation, or a combination of the

two designations. Signal naming conventions are as follows:

• Port Number Only. Individual signals that apply to a particular port are designated by the

Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit

Enable signals would be identified as TXEN0, TXEN1, and TXEN2.

• Serial Number Only. A set of signals which are not tied to any specific port are designated by

the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set

of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.

• Port and Serial Number. In cases where each port is assigned a set of multiple signals, each

signal is designated in the following order: Signal Mnemonic, Port Designation, an

underscore, and the serial designation. For example, a set of three Port Configuration signals

would be identified as RXD0_0 and RXD0_1, RXD1_0 and RXD1_1, and RXD2_0 and

RXD2_1.

Table 4. LXT9785 RMII Signal Descriptions

Pin-Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

Reference Clock. 50 MHz RMII reference clock is always required. RMII

inputs are sampled on the rising edge of REFCLK, RMII outputs are

sourced on the falling edge. See “Clock/SYNC Requirements” on page 58

for detailed CLK requirements.

E6,

E12

REFCLK0

REFCLK1

E2,

TXD0_0

TXD0_1

Transmit Data - Port 0. Inputs containing 2-bit parallel di-bits to be

transmitted from port 0 are clocked in synchronously to REFCLK.

I, ID

C3,

TXD1_0

TXD1_1

Transmit Data - Port 1. Inputs containing 2-bit parallel di-bits to be

transmitted from Port 1 are clocked in synchronously to REFCLK

TXD2_0

TXD2_1

Transmit Data - Port 2. Inputs containing 2-bit parallel di-bits to be

transmitted from port 2 are clocked in synchronously to REFCLK.

D8,

TXD3_0

TXD3_1

Transmit Data - Port 3. Inputs containing 2-bit parallel di-bits to be

transmitted from Port 3 are clocked in synchronously to REFCLK.

A11,

C10

TXD4_0

TXD4_1

Transmit Data - Port 4. Inputs containing 2-bit parallel di-bits to be

transmitted from Port 4 are clocked in synchronously to REFCLK.

B13,

D11

TXD5_0

TXD5_1

Transmit Data - Port 5. Inputs containing 2-bit parallel di-bits to be

transmitted from Port 5 are clocked in synchronously to REFCLK.

D13,

A16

TXD6_0

TXD6_1

Transmit Data - Port 6. Inputs containing 2-bit parallel di-bits to be

transmitted from Port 6 are clocked in synchronously to REFCLK.

203

204

E14,

C16

TXD7_0

TXD7_1

Transmit Data - Port 7. Inputs containing 2-bit parallel di-bits to be

transmitted from Port 7 are clocked in synchronously to REFCLK.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. RXD[0:7]_0, RXD[0:7]_1, CRS_DV[0:7] and RXER[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes and

during H/W reset.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 4. LXT9785 RMII Signal Descriptions (Continued)

Pin-Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

E3,

TXEN0

B2,

C6,

A7,

B11,

A14,

C14,

D16

TXEN1

TXEN2

TXEN3

TXEN4

TXEN5

TXEN6

TXEN7

Transmit Enable - Ports 0-7. Active High input enables respective port

transmitter. This signal must be synchronous to the REFCLK.

I, ID

202

C2,

RXD0_0

RXD0_1

O, TS

O, TS, ID

Receive Data - Port 0. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

A3,

RXD1_0

RXD1_1

O, TS

O, TS, ID

Receive Data - Port 1. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

B6,

RXD2_0

RXD2_1

O, TS

O, TS, ID

Receive Data - Port 2. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

D9,

RXD3_0

RXD3_1

O, TS

O, TS, ID

Receive Data - Port 3. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

A13,

C12

RXD4_0

RXD4_1

O, TS

O, TS, ID

Receive Data - Port 4. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

B14,

B15

RXD5_0

RXD5_1

O, TS

O, TS, ID

Receive Data - Port 5. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

206

205

C15,

B17

RXD6_0

RXD6_1

O, TS

O, TS, ID

Receive Data - Port 6. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

198

197

E16,

F14

RXD7_0

RXD7_1

O, TS

O, TS, ID

Receive Data - Port 7. Receive data signals (2-bit parallel di-bits) are

driven synchronously to REFCLK.

E4,

C4,

A5,

B8,

B12,

D12,

B16,

E15

CRS_DV0

CRS_DV1

CRS_DV2

CRS_DV3

CRS_DV4

CRS_DV5

CRS_DV6

CRS_DV7

Carrier Sense/Receive Data Valid - Ports 0-7. On detection of valid

carrier, these signals are asserted asynchronously with respect to

REFCLK. CRS_DVn is deasserted on loss of carrier, synchronous to

REFCLK.

O, TS, SL,

200

D2,

D5,

D7,

C8,

A12,

A15,

A17,

D17

RXER0

RXER1

RXER2

RXER3

RXER4

RXER5

RXER6

RXER7

Receive Error - Ports 0-7. These signals are synchronous to the

respective REFCLK. Active High indicates that received code group is

invalid, or that PLL is not locked.

O, TS, SL,

201

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. RXD[0:7]_0, RXD[0:7]_1, CRS_DV[0:7] and RXER[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes and

during H/W reset.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 5. LXT9785 SMII / SS-SMII Common Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description²

PQFP

PBGA

E2,

C3,

B5,

D8,

A11,

B13,

D13,

E14

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

Transmit Data - Ports 0-7. These serial input streams provide data to be

transmitted to the network. The LXT9785 clocks the data in synchronously to

REFCLK.

I, ID

203

Reference Clock. The LXT9785 always requires a 125 MHz reference clock

input. Refer to Functional Description for detailed clock requirements. REFCLK0

and REFCLK1 are always connected regardless of sectionalization mode.

E6,

REFCLK0

REFCLK1

E12

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

Table 6. LXT9785 SMII Specific Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

SMII Synchronization. The MAC must generate a SYNC pulse every 10

REFCLK cycles to synchronize the SMII. SYNC0 is used when 1x8 port

sectionalization is selected. SYNC0 and SYNC1 are to be used when 2x4

port sectionalization is chosen.

204

A6,

C16

SYNC0

SYNC1

I, ID

C2,

A3,

B6,

D9,

A13,

B14,

C15,

E16

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

Receive Data - Ports 0-7. These serial output streams provide data

received from the network. The LXT9785 drives the data out synchronously

to REFCLK.

O, TS

206

198

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

3. RXD[0:7] outputs are tri-stated in Isolation and H/W Power-Down modes and during H/W reset.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 7. LXT9785 SS-SMII Specific Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

SS-SMII Transmit Synchronization. The MAC must generate a TX_SYNC

pulse every 10 TX_CLK cycles to mark the start of TXD segments.

TX_SYNC0 is used when 1x8 port sectionalization is selected.

204

A6,

C16

TX_SYNC0

TX_SYNC1

I, ID

SS-SMII Receive Synchronization. The LXT9785 generates these pulses

every 10 RX_CLK cycles to mark the start of RXD segments for the MAC.

RX_SYNC1 is used and RX_SYNC0 is tri-stated when 1x8 port

sectionalization is selected. These outputs are only enabled when SS-SMII

mode is enabled.

RX_SYNC0

RX_SYNC1

E4,

B12

O, TS,

SS-SMII Transmit Clock. The MAC sources this 125 MHz clock as the

timing reference for TXD and TX_SYNC. Only TX_CLK0 is used when 1x8

port sectionalization is selected. See “Clock/SYNC Requirements” on page 58 for

detailed clock requirements.

201

C8,

D17

TX_CLK0

TX_CLK1

I, ID

SS-SMII Receive Clock. The LXT9785 generates these clocks, based on

REFCLK, to provide a timing reference for RXD and RX_SYNC to the MAC.

RX_CLK1 used and RX_CLK0 is tri-stated when 1x8 port sectionalization is

selected. See “Clock/SYNC Requirements” on page 58 for detailed clock

requirements. These outputs are only enabled when SS-SMII mode is

enabled.

E3,

B11

RX_CLK0

RX_CLK1

O, TS,

B1,

B4,

C7,

B9,

C12,

B15,

B17,

F14

RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

Receive Data - Ports 0-7. These serial output streams provide data received

from the network. The LXT9785 drives the data out synchronously to

REFCLK.

O, TS,

205

197

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. RXD[0:7], RXSYNC[0:1], and RXCLK[0:1] outputs are tri-stated in Isolation and H/W Power-Down modes and during H/W

reset.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 8. MDIO Control Interface Signals

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3,4

PQFP

PBGA

Management Data Input/Output. Bidirectional serial data channel for

communication between the PHY and MAC or switch ASIC. Only MDIO0

is used when 1x8 port sectionalization is selected. In 2x4 port

sectionalization mode, MDIO0 accesses ports 0-3 and MDIO1 accesses

Ports 4-7. For an example, refer to Figure 22 on page 72.

F3,

A10

MDIO0

MDIO1

I/O, TS, SL,

Management Data Interrupt. When bit 18.1 = 1, an active Low output on

this Pin indicates status change. Only MDINT0 is used when 1x8 port

F1,

MDINT0

MDINT1

OD,TS, SL, sectionalization is selected. In 2x4 port sectionalization mode, MDINT0

is associated with Ports 0-3 and MDINT1 is associated with Ports 4-7. For

an example, refer to Figure 22 on page 72.

Management Data Clock. Clock for the MDIO serial data channel.

Maximum frequency is 20 MHz. Only MDC0 is used when 1x8 port

sectionalization is selected. In 2x4 port sectionalization mode, MDC0

clocks Ports 0-3 register accesses and MDC1 clocks Ports 4-7 register

accesses. For an example, refer to Figure 22 on page 72.

E1,

B10

MDC0

MDC1

I, ST, ID

Management Disable. When MDDIS is tied High, the MDIO port is

completely disabled and the Hardware Control Interface pins set their

respective bits at power up and reset.

When MDDIS is pulled Low at power up or reset, via the internal pull-down

resistor or by tieing it to ground, the Hardware Control Interface Pins

control only the initial or “default” values of their respective register bits.

After the power-up/reset cycle is complete, bit control reverts to the MDIO

serial channel.

MDDIS

I, ST, ID

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. MDIO[0:1] and MDINT[0:1] outputs are tri-stated in H/W Power-Down mode and during H/W reset.

4. Supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation, where X is the

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 9. LXT9785 Signal Detect

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

Signal Detect 2.5 Volt Interface. When the SD interface is at 2.5 V, tie this

input to VCCPECL. Floating this input or tieing it to GNDPECL indicates that

a 3.3 V SD interface is being used.

SD_2P5V

I, ST, ID

P2,

N4,

P3,

N5,

P15,

P16,

P17,

N17

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

Signal Detect - Ports 0-7. The SD inputs are only applicable for ports set in

Fiber mode.

100

101

161

162

165

166

When SD is high, the process of searching for receive idles for the purpose of

bring link up is initiated.

If SD is low, link is declared lost.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

3. Tie SD[0:7] inputs to GNDPECL if unused.

Table 10. LXT9785 Network Interface Signal Descriptions

Pin/Ball Designation

Symbol

Type¹

Signal Description

PQFP

PBGA

107, 108

111, 110

121, 122

125, 124

136, 137

140, 139

150, 151

154, 153

T2, U1,

T3, R4,

T6, U5,

U7, T7,

T10, R10,

T11, U11,

T14,U15,

R14, T15

TPFOP0, TPFON0

TPFOP1, TPFON1

TPFOP2, TPFON2

TPFOP3, TPFON3

TPFOP4, TPFON4

TPFOP5, TPFON5

TPFOP6, TPFON6

TPFOP7, TPFON7

Twisted-Pair/Fiber Outputs², Positive & Negative,

Ports 0-7.

During 100BASE-TX or 10BASE-T operation, TPFO pins drive

802.3 compliant pulses onto the line.

AO/AI

During 100BASE-FX operation, TPFO pins produce differential

PECL outputs for fiber transceivers.

104, 105

115, 114

118, 119

129, 128

132, 133

143, 142

146, 147

157, 156

R2, T1,

U3, T4,

R6, T5,

T8, R8,

TPFIP0, TPFIN0

TPFIP1, TPFIN1

TPFIP2, TPFIN2

TPFIP3, TPFIN3

TPFIP4, TPFIN4

TPFIP5, TPFIN5

TPFIP6, TPFIN6

TPFIP7, TPFIN7

Twisted-Pair/Fiber Inputs³, Positive & Negative,

Ports 0-7.

During 100BASE-TX or 10BASE-T operation, TPFI pins receive

differential 100BASE-TX or 10BASE-T signals from the line.

AI/AO

T9, U9,

U13, T12,

R12, T13,

R16, T16

During 100BASE-FX operation, TPFI pins receive differential

PECL inputs from fiber transceivers.

1. Type Column Coding: AI = Analog Input, AO = Analog Output.

2. Switched to Inputs (see TPFIP/N desc.) when not in Fiber mode and MDIX is not active [i.e., Twisted-Pair, non-crossover MDI

mode].

3. Switched to Outputs (see TPFOP/N desc.) when not in Fiber mode and MDIX is not active [i.e., Twisted-Pair, non-crossover

MDI mode].

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 11. LXT9785 JTAG Test Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

167

PBGA

N14

TDI

I, ST, IP

O, TS

Test Data Input. Test data sampled with respect to the rising edge of TCK.

Test Data Output. Test data driven with respect to the falling edge of TCK.

Test Mode Select.

168

169

170

171

N15

N16

M16

M17

TDO

TMS

TCK

I, ST, IP

I, ST, ID

I, ST, IP

Test Clock. Clock input for JTAG test.

TRST

Test Reset. Reset input for JTAG test.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Tri-State-able output, SMT = Schmitt Triggered input, SL

= Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. TDO output is tri-stated in H/W Power-Down mode and during H/W reset.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 12. LXT9785 Miscellaneous Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description²

PQFP

PBGA

Tx Output Slew Controls 0 and 1 Defaults.

These pins are read at startup or reset. Their value at that time is used to

set the default state of register bits 27.11:10 for all ports. These register

bits can be read and overwritten after startup / reset.

These pins select the TX output slew rate for all ports (rise and fall time)

as follows:

TxSLEW_0

TxSLEW_1

N3,

I, ST, ID

TxSLEW_1

TxSLEW_0

Slew Rate (Rise and Fall Time)

3.3 ns

3.6 ns

3.9 ns

4.2 ns

Pause Default. This pin is read at startup or reset. Its value at that time is

used to set the default state of register bit 4.10 for all ports. This register

bit can be read and overwritten after startup / reset.

When High, the LXT9785 advertises Pause capabilities on all ports during

auto-negotiation.

PAUSE

I, ID

This pin is shared with RMII-RXER1. An external pull-up resistor (see

applications section for value) can be used to set Pause active while

RXER1 is tri-stated during H/W reset. If no pull-up is used, the default

Pause state is set inactive via the internal pull-down resistor.

Power-Down. When High, forces the LXT9785 into global power-down

mode.

174

175

L14

PWRDWN

RESET

I, ST, ID

I, ST, IP

Pin is not on JTAG chain.

Reset. This active low input is OR’ed with the control register Reset bit

(0.15). When held Low, all outputs are forced to inactive state.

M15

Pin is not on JTAG chain

Address <4:0>. Sets base address. Each port adds its port number

(starting with 0) to this address to determine its PHY address.

Port 0 Address = Base

L4,

M2,

M3,

N1,

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

Port 1 Address = Base + 1

Port 2 Address = Base + 2

Port 3 Address = Base + 3

Port 4 Address = Base + 4

Port 5 Address = Base + 5

Port 6 Address = Base + 6

Port 7 Address = Base + 7

I, ST, ID

Mode Select[1:0]

00 = RMII

01 = SMII

10 = SS-SMII

11= Reserved

178

177

L17,

L16

MODESEL_1

MODESEL_0

I, ST, ID

All ports are configured the same. Interfaces cannot be mixed and must

be all RMII, SMII, or SS-SMII.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 12. LXT9785 Miscellaneous Signal Descriptions (Continued)

Pin/Ball

Designation

Symbol

Type¹

Signal Description²

PQFP

PBGA

Sectionalization Select. This pin selects sectionalization into separate

ports.

176

L15

SECTION

I, ST, ID

0 = 1x8 ports,

1 = 2x4 ports

Auto-MDIX Enable Default. This pin is read at startup or reset. Its value

at that time is used to set the default state of register bit 27.9 for all ports.

These register bits can be read and overwritten after startup / reset. Refer

to Table 16 on page 53.

AMDIX_EN

I, ST, IP

When active (high), automatic MDI crossover (MDIX) (regardless of

segmentation) is selected for all ports. When inactive (low) MDIX is

selected according to the MDIX pin.

MDIX Select Default. This pin is read at startup or reset. Its value at that

time is used to set the default state of register bit 27.8 for all ports. These

Table 16 on page 53.

When AMDIX_EN is active this pin is ignored.

When AMDIX_EN is inactive, all ports are forced to the MDI or the MDIX

function regardless of segmentation. If this pin is active (high), MDI

crossover (MDIX) is selected. If this pin is inactive, non-crossover MDI

mode is set.

MDIX

I, ID

This pin is shared with RMII-RXER0. An external pull-up resistor (see

applications section for value) can be used to set MDIX active while

RXER0 is tri-stated during H/W reset. If no pull-up is used, the default

MDIX state is set inactive via the internal pull-down resistor. Do not tie this

pin directly to VCCIO (vs. using a pull-up) in non-RMII modes.

Global Port Configuration Defaults 1-3. These pins are read at startup

or reset. Their value at that time is used to set the default state of register

bits shown in Table 18 on page 62 for all ports. These register bits can be

read and overwritten after startup / reset.

L2,

L3,

CFG_3

CFG_2

CFG_1

I, ST, ID

When operating in Hardware Control Mode, these pins provide

configuration control options for all the ports (refer to page 62 for details).

Global FX/TP Enable Default. This pin is read at startup or reset. Its

value at that time is used to set the default state of register bit 16.0 for all

ports. These register bits can be read and overwritten after startup /

reset. Refer to “Port Configuration Register (Address 16, Hex 10)” on

page 127.

173

M14

G_FX/TP

This input selects whether all the ports are defaulted to TP vs. FX mode.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 13. LXT9785 LED Signal Descriptions

Pin/Ball

Designation

Symbol

Type¹

Signal Description^2,3

PQFP

PBGA

Port 0 LED Drivers 1-3. These pins drive LED indicators for Port 0.

OD, TS, SL, Each LED can display one of several available status conditions as

K3,

K2,

LED0_1

LED0_2

LED0_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

Port 1 LED Drivers 1-3. These pins drive LED indicators for Port 1.

OD, TS, SL, Each LED can display one of several available status conditions as

J4,

J3,

LED1_1

LED1_2

LED1_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

Port 2 LED Drivers 1-3. These pins drive LED indicators for Port 2.

OD, TS, SL, Each LED can display one of several available status conditions as

H2,

H3,

LED2_1

LED2_2

LED2_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

Port 3 LED Drivers 1-3. These pins drive LED indicators for Port 3.

OD, TS, SL, Each LED can display one of several available status conditions as

F2,

G3,

LED3_1

LED3_2

LED3_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

Port 4 LED Drivers 1-3. These pins drive LED indicators for Port 4.

OD, TS, SL, Each LED can display one of several available status conditions as

180

181

182

K16,

K17,

J17

LED4_1

LED4_2

LED4_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

Port 5 LED Drivers 1-3. These pins drive LED indicators for Port 5.

OD, TS, SL, Each LED can display one of several available status conditions as

185

186

187

J15,

J16,

H17

LED5_1

LED5_2

LED5_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

Port 6 LED Drivers 1-3. These pins drive LED indicators for Port 6.

OD, TS, SL, Each LED can display one of several available status conditions as

189

190

191

H15,

H16,

G17

LED6_1

LED6_2

LED6_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

Port 7 LED Drivers 1-3. These pins drive LED indicators for Port 7.

OD, TS, SL, Each LED can display one of several available status conditions as

192

193

194

G15,

F17,

F16

LED7_1

LED7_2

LED7_3

selected by the LED Configuration Register (refer to Table 70 on

page 131 for details).

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also

disabled when the output is enabled.

3. The LED outputs are tri-stated in H/W Power-Down mode and during H/W reset.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 14. LXT9785 Power Supply Signal Descriptions

Pin/Ball Designation

Symbol

Type

Signal Description

PQFP

PBGA

65, 78, 184, G13, J14,

VCCD

Digital Power Supply - Core. +2.5V supply for core digital circuits.

196

F5, J5

Digital Power Supply - I/O Ring. +2.5/3.3V supply for digital I/O

circuits. The digital input circuits running off of this rail, having a TTL-level

threshold and over-voltage protection, may be interfaced with 3.3/5.0 V,

when the IO supply is 3.3V, and 2.5/3.3/5.0 V when 2.5V.

A2, A8,

C1, C11,

D14

18, 29, 47,

56, 208

VCCIO

VCCPECL

VCCR

Digital Power Supply - PECL Signal Detect Inputs. +2.5/3.3V supply

for PECL Signal Detect input circuits. If Fiber Mode is not used, tie these

pins to GNDPECL to save power.

98, 164

L13, L5

103, 116,

117, 130,

131, 144,

145, 158

N13, P4,

P7, P8,

P9, P10,

P11, P12

Analog Power Supply - Receive. +2.5V supply for all analog receive

circuits.

N6, N7,

N9, N11,

N12

109, 123,

138, 152

Analog Power Supply - Transmit. +2.5V supply for all analog transmit

circuits.

VCCT

A1, A9,

B3, B7,

C5, C13,

C17, D1,

D3, D6,

D10, D15,

E5, E7,

E9, E11,

E13, E17,

F13, H8,

H9, H10,

J8, J9,

66, 79,

183, 195

Digital Ground. Ground return for core digital supplies (VCCD). All

ground pins can be tied together using a single ground plane.

GNDD

J10, K8,

K9, K10

9, 19, 30,

38, 48, 57,

74, 188,

GNDIO

Digital GND - I/O Ring. Ground return for digital I/O circuits (VCCIO).

199, 207

Digital GND - PECL Signal Detect Inputs. Ground return for PECL

Signal Detect input circuits.

99, 163

M5, M13

GNDPECL

GNDR

106, 112,

120, 126,

135, 141,

149, 155

P5, P6,

P13, R7,

R9, R11,

R13, U8

Analog Ground - Receive. Ground return for receive analog supply. All

ground pins can be tied together using a single ground plane.

P14, R1,

R3, R5,

R15, R17,

T17, U2,

U4, U6,

U10, U12,

U14, U16,

U17

113, 127,

134, 148

Analog Ground - Transmit. Ground return for transmit analog supply.

All ground pins can be tied together using a single ground plane.

GNDT

SGND

Substrate Ground. Ground for chip substrate. All ground pins can be

tied together using a single ground plane.

179

K14

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 15. Unused / Reserved Pins

Pin/Ball Designation

Symbol

Type¹

Signal Description

PQFP

PBGA

F15, G2,

G5, G14,

G16, H4,

H14, J2,

J13, K4,

K15

N/C

No Connection.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS = Tri-State-able

output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-Down.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

2.0

Functional Description

2.1

Introduction

The LXT9785 is an 8-port Fast Ethernet 10/100 PHY transceiver that supports 10Mbps and

100Mbps networks, complying with all applicable requirements of IEEE 802.3 standards. The

device incorporates a Serial MII (SMII), Source Synchronous SMII (SS-SMII), and a Reduced MII

(RMII) to enable each individual network port to interface with multiple 10/100 MACs. Each port

directly drives either a 100BASE-TX line or a 10BASE-T line. The LXT9785 also supports

100BASE-FX operation via a Pseudo-ECL (PECL) interface. The device has a 241-pin BGA or a

208- pin QFP package.

2.1.1

OSP™ Architecture

The Intel LXT9785 incorporates high-efficiency Optimal Signal Processing™ design techniques,

combining the best properties of digital and analog signal processing to produce a truly optimal

device.

The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by

as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques

in the receive equalizer avoids the quantization noise and calculation truncation errors found in

traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result

is improved receiver noise and cross-talk performance.

The OSP architecture also requires substantially less computational logic than traditional DSP-

based designs. The result is lower power consumption and reduced logic switching noise generated

by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable

source of EMI when generated from the device’s power supplies.

The OSP-based LXT9785 provides improved data recovery, EMI performance and power

consumption.

2.1.2

Comprehensive Functionality

The LXT9785 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media

Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device

also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX

connections.

On power-up, the LXT9785 reads its configuration inputs to check for forced operation settings. If

not configured for forced operation, each port uses auto-negotiation/parallel detection to

automatically determine line operating conditions. If the PHY device on the other side of the link

supports auto-negotiation, the LXT9785 auto-negotiates with it using Fast Link Pulse (FLP)

Bursts. If the PHY partner does not support auto-negotiation, the LXT9785 automatically detects

the presence of either link pulses (10Mbps PHY) or Idle symbols (100Mbps PHY) and set its

operating conditions accordingly.

The LXT9785 provides half-duplex and full-duplex operation at 100Mbps and10Mbps.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.1.2.1

Sectionalization

The LXT9785’s sectional design allows flexibility with large multiport MACs and ASICs. With the

use of the Section pin, the LXT9785 can be configured into a single 8-port or two separate 4-port

sections, each with its own MDIO (with separate MDC clock) and MII data (with separate

REFCLK/TX_CLK/RX_CLK clocks) interfaces. See Figure 17 on page 66, Figure 22 on page 72,

and Figure 27 on page 77.

2.2

Interface Descriptions

2.2.1

10/100 Network Interface

The LXT9785 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or

100Mbps Ethernet over fiber media (100BASE-FX). Each network interface port consists of four

external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and

fiber. The LXT9785 pinout is designed to interface seamlessly with dual-high stacked RJ-45

connectors. Refer to Table 10 on page 44 for specific pin assignments.

The LXT9785 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.

When not transmitting data, the device generates IEEE 802.3-compliant link pulses or idle code.

Input signals are decoded either as a 100BASE-TX, 100BASE-FX, or 10BASE-T input, depending

on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine

the speed of this interface.

Figure 8. LXT9785 Interfaces

TXENn

TXDn_0

TXDn_1

TXCLK

TPFOPn

TPFONn

Network

I/F

DATA

I/F

RXCLK

RXDn_1

TPFIPn

TPFINn

RXDn_0

RXERn

CRS_DVn

MDIOn

MDCn

MDIO

Mgmt

I/F

MDINTn

MDDIS

Direct Drive

LEDn_2

Port LEDs/

Controls

LEDn_2

LEDn_3

+3.3V

+2.5V

MDIX_Enb

Mode Select

ADD<4:0>

Addr &

MDIX/

Contr

VCCIO

VCCD

GNDD

+2.5V

.01uF

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

2.2.1.1

Twisted-Pair Interface

The LXT9785 supports either 100BASE-TX or 10BASE-T connections over 100Ω, Category 5,

Unshielded Twisted-Pair (UTP). Only a transformer, load resistors, RJ-45, and bypass capacitors

are required to complete this interface. Using Intel’s patented waveshaping technology, the

transmitter shapes the outgoing signal to help reduce the need for external EMI filters. Four slew

rate settings (refer to Table 12 on page 46) allow the designer to match the output waveform to the

magnetic characteristics. Both transmit and receive terminations are built into the LXT9785 so no

external components are required between the LXT9785 and the external transformer. The

transmitter uses a transformer with a center tap to help reduce power consumption.

When operating at 100Mbps, MLT3 symbols are continuously transmitted and received. When not

transmitting data, the LXT9785 generates “IDLE” symbols.

During 10Mbps operation, LXT9785 encoded data is exchanged. When no data are being

exchanged, the line is left in an idle state.

2.2.1.2

MDI Crossover (MDIX)

The LXT9785 crossover function, which is compliant to the IEEE 802.3, clause 23 standard,

connects the transmit output of the device to the far-end receiver in a link segment. This function

can be disabled via register bit 27.9:8 or by using the hardware configuration pins.

Table 16. MDIX Selection

AMDIX_EN

MDIX

MDIX Mode

MDIX Disabled

MDIX forced

AUTO-MDIX

2.2.1.3

Fiber Interface

The LXT9785 provides a PECL interface that complies with the ANSI X3.166 specification. This

interface is suitable for driving a fiber-optic coupler (see Figure 35 on page 93).

Fiber ports cannot be enabled via auto-negotiation and must be enabled via the Global Hardware

Control Interface pins or MDIO registers. All ports are selected for fiber or twisted-pair when

configured via hardware, and can only be intermixed via software. Using external circuitry, the

LXT9785 can interface the fiber transceiver with 2.5V, 3.3V, or 5V supply voltages. Fiber mode

per port may be selected using register 16.0. Please refer to Table 10 on page 44 for correct pin

assignments.

2.3

Media Independent Interface (MII) Interfaces

The LXT9785 supports Reduced MII or Serial MII, but not concurrently. The interface mode

selection pins configures the device for either RMII or SMII/SS-SMII on all eight ports. Refer to

Table 17 for the mode select settings.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.3.1

Global MII Mode Select

The mode select pins are used for MII interface configuration settings upon power-up sequencing.

All ports are configured the same and cannot be intermixed.

Table 17. MII Mode Select

ModeSel1

ModeSel0

RMII

SMII

SS-SMII

Reserved

2.3.2

Internal Loopback

A test loopback function is available for 10Mbps and 100Mbps mode testing. Bits 0.8, 0.13, and

0.14 must be set to 1 for correct operation. When data is looped back, whatever the MAC transmits

is looped back in its entirety, including the preamble.

Figure 9. Internal Loopback

LXT9785

Driver

RMII/

SMII/

SS-

SMII

inter

face

Analog

Block

Digital

Block

Loopback

Driver

2.3.3

RMII Data Interface

The LXT9785 provides a separate RMII for each network port, each complying with the RMII

standard. The RMII includes both a data interface and an MDIO management interface. The RMII

Data Interface exchanges data between the LXT9785 and up to eight Media Access Controllers

(MACs).

2.3.4

Serial Media Independent Interface (SMII) and Source Synchronous

Data Interfaces

2.3.4.1

SMII Interface

The LXT9785 provides an independent serial interface for each network port. All SMII ports use a

common reference clock and SYNC signal. The SMII Data Interface exchanges data between the

LXT9785 and multiple Media Access Controllers (MACs). All signals are synchronous to the

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

reference clock. One SYNC control stream is sourced by the MAC to the PHY. Both the transmit

and receive data streams are segmented into boundaries delimited by the SYNC pulses. This

interface is expected to operate up to 6 inches of trace lengths.

2.3.4.2

Source Synchronous Interface

The new revision to the SMII interface, SS-SMII, allows for a longer trace length and helps to

relieve timing constraints, requiring the addition of four new signals, TxCLK, TxSYNC, RxCLK,

and RxSYNC. The transmit TxClk and TxSync are sourced from the MAC to the PHY and

referenced to the RefCLK input. The receive RxCLK and RxSync are sourced by the PHY to the

MAC and in reference to the RefCLK.

2.3.5

2.3.6

Configuration Management Interface

The LXT9785 provides an MDIO Management Interface and a Hardware Control Interface (via the

CFG pins) for device configuration and management. Mode control selection is provided via the

MDDIS pin as shown in Table 8 on page 43. When sectionalization (2x4) is selected, separate

MDIO interfaces are enabled (see Figure 14 on page 60).

MII Isolate

In applications where the MII needs to be isolated from the bus, the RMII and the SMII/SS-SMII

configurations can be tri-stated using Register 0.10. Ports 0 and 1 control RxClk0, RxClk1,

RxSync0, and RxSync1. When 2x4 sectionalization is selected, ports 1-3 and 5-7 can be

individually port isolated. For global shut down, Ports 0 and 1 must be isolated to control the

RxClkn and RxSyncn synchronization pins. If ports 0 and 1 are individually set to isolate, the

remaining associated quad sectionalization ports must also be set to isolate.

2.3.6.1

MDIO Management Interface

The LXT9785 supports the IEEE 802.3 MII Management Interface, also known as the

Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to

monitor and control the state of the LXT9785. The MDIO interface consists of a physical

connection, a specific protocol that runs across the connection, and an internal set of addressable

registers. Some registers are required and their functions are defined by the IEEE 802.3

specification. Additional registers allow for expanded functionality. Specific bits in the registers

are referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit

number (0-15).

The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this

interface is controlled by the MDDIS input pin. When MDDIS is High, all the MDIOs are

completely disabled. The Hardware Control Interface provides primary configuration control.

When MDDIS is Low, the MDIO port is enabled for both read and write operations and the

Hardware Control Interface is not used. The timing for the MDIO Interface is shown in Table 53

on page 117. MDIO read and (write) cycles are shown in Figure 10 (read) and Figure 11 (write)

on page 56.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 10. Management Interface Read Frame Structure

MDC

MDIO

(Read)

D15 D14

D14 D1

D15

32 "1"s

Turn

Around

Data

Read

Idle

Preamble

Op Code

PHY Address

High Z

Write

Figure 11. Management Interface Write Frame Structure

MDC

MDIO

(Write)

D15

D14

32 "1"s

Turn

Around

Idle

Preamble

Op Code

PHY Address

Data

Idle

Write

The protocol allows one controller to communicate with multiple LXT9785 chips. Pins

ADD_<4:0> determine the base address. Each port adds its port number to the base address to

obtain its port address as shown in Figure 12.

Figure 12. Port Address Scheme

BASE ADD_<4:0>

(example ADD_<4:0> = 4)

LXT9785

PHY ADD_<4:0> (BASE+0)

ex. 4

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

PHY ADD_<4:0> (BASE+1)

ex. 5

PHY ADD_<4:0> (BASE+2)

ex. 6

PHY ADD_<4:0> (BASE+3)

ex. 7

PHY ADD_<4:0> (BASE+4)

ex. 8

PHY ADD_<4:0> (BASE+5)

ex. 9

PHY ADD_<4:0> (BASE+7)

ex. 11

Port 7

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

2.3.6.2

MII Sectionalization

When sectionalized into two quad sections, the MDIO bus splits into two separate PHY access

ports. Ports 0-3 of the MDIO section operate independently of ports 4-7. The MII isolate function

is unaffected and operates normally. Sectionalization is selected by pulling pin 176 High on the

initial power-up sequence (refer to Figure 14 on page 60). In applications that need

sectionalization, such as 1x8 and 2x4 and have a single MDIO bus structure, it is necessary that the

addressing scheme be contiguous. For example, the first eight ports are addressed 0-7, so the next

four ports must be addressed 8-11.

2.3.6.3

MII Interrupts

The LXT9785 provides a single per-section interrupt pin that is available to all ports. Interrupt

logic is shown in Figure 13. The LXT9785 also provides two dedicated interrupt registers for each

port. Register 18 provides interrupt enable and mask functions and Register 19 provides interrupt

status. Setting bit 18.1 to 1 enables a port to request interrupt via the MDINT pin. An active Low

on this pin indicates a status change on the device. Because it is a shared interrupt, there is no

indication which port is requesting interrupt service (see Figure 13).

There are five conditions that may cause an interrupt:

• Auto-negotiation complete.

• Speed status change.

• Duplex status change.

• Link status change.

• Isolate status change.

Figure 13. Interrupt Logic

Event X Enable Reg

AND

Event X Status Reg

Port

Combine

Logic

Interrupt Pin

AND

Per Event

Per port

Force Interrupt

Interrupt Enable

Interrupt (Event) Status Register is cleared on read.

X = Any Interrupt capability

2.3.6.4

Hardware Control Interface

The LXT9785 provides a Hardware Control Interface for applications where the MDIO is not

desired. Refer to “Initialization” on page 59 for additional details.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.4

Operating Requirements

2.4.1

Power Requirements

The LXT9785 requires four power supply inputs: VCCD, VCCA, VCCPECL and VCCIO. The

digital and analog circuits require 2.5V supplies (VCCD, VCCR, and VCCT). These inputs may be

supplied from a single source although decoupling is required to each respective ground. The fiber

VCCPECL supply can be connected to either 2.5V or 3.3V.

A separate power supply may be used for the MII, JTAG and MDIO (VCCIO) interfaces. The

power supply may be either +2.5V or +3.3V. VCCIO should be supplied from the same power

source used to supply the controller on the other side of the interface. Refer to Table 27 on page 94

for I/O characteristics.

As a matter of good practice, these supplies should be as clean as possible. Typical filtering and

decoupling are shown in Figure 33 on page 92.

2.4.2

Clock/SYNC Requirements

Reference Clock

2.4.2.1

The LXT9785 requires a constant enabled reference clock (REFCLK). REFCLK’s frequency must

be 50 MHz for RMII or 125 MHz for SMII/SS-SMII. The reference clock is used to generate

transmit signals and recover receive signals. A crystal-based clock is recommended over a derived

clock (i.e., PLL-based) to minimize transmit jitter. Refer to Table 30 on page 96 for clock timing

requirements.

For applications that use a single 8-port sectionalization, RefClk0 and RefClk1 must always be tied

together and to the source.

2.4.2.2

2.4.2.3

2.4.2.4

2.4.2.5

TxClk Signal (SS-SMII only)

The LXT9785 requires a 125 MHz input transmit clock synchronous with TxDatan. See Figure 23

on page 73.

TxSYNC Signal (SMII/SS-SMII)

The LXT9785 requires a 12.5 MHz input pulse for SMII synchronization. See Figure 23 on page

73.

RxSYNC Signal (SS-SMII only)

The LXT9785 provides a 12.5 MHz output pulse synchronous with the RxDATAn outputs. See

Figure 24 on page 73.

RxCLK Signal (SS-SMII only)

In SMII mode, the LXT9785 provides a 125 MHz clock output in reference to the output

RxDATAn. Rx Clk is referenced and synchronized to the RefCLK. See Figure 24 on page 73.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

2.5

Initialization

When the LXT9785 is first powered on, reset, or encounters a link failure state, it checks the MDIO

network link. The configuration bits may be set by the Hardware Control or MDIO interface as

shown in Figure 14 on page 60.

2.5.1

2.5.2

MDIO Control Mode

In the MDIO Control mode, the LXT9785 reads the Hardware Control Interface pins to set the

initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to

the MDIO interface.

Hardware Control Mode

In the Hardware Control Mode, the LXT9785 disables direct write operations to the MDIO

registers via the MDIO Interface. On power-up or hardware reset, the LXT9785 reads the

Hardware Control Interface pins and sets the MDIO registers accordingly.

The following modes are available using either Hardware Control or MDIO Control:

• Force network link to 100BASE-FX (Fiber).

• Force network link operation to:

— 100BASE-TX, Full-Duplex

— 100BASE-TX, Half-Duplex

— 10BASE-T, Full-Duplex

— 10BASE-T, Half-Duplex

• Allow auto-negotiation/parallel-detection.

• Auto/Manual MDIX enable/disable.

• Pause for full duplex links operation.

• Global Output Slew Rate Control.

When the network link is forced to a specific configuration, the LXT9785 immediately begins

operating the network interface as commanded. When auto-negotiation is enabled, the LXT9785

begins the auto-negotiation/ parallel-detection operation.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 14. Initialization Sequence

Power-up or Reset

Read H/W Control

Interface

Initialize MDIO Registers

MDIO Control

Mode

Hardware Control

Mode

MDDIS Voltage

Level?

Low

High

Pass Control to MDIO

Interface

Disable MDIO Writes

Software

Reset?

Hardware

Reset?

Yes

Reset MDIO Registers to

values read at H/W

Control Interface at last

Hardware Reset

2.5.3

Power-Down Mode

The LXT9785 incorporates numerous features to maintain the lowest power possible. The device

can be put into a low-power state via register 0 as well as a near-zero power state with the power

down pin. When in power-down mode, the device is not capable of receiving or transmitting

packets.

The lowest power operation is achieved using the Global power-down pin. This pin powers down

every circuit in the device, including all clocks. This power-down pin is active High. All registers

are unaltered and maintained when the Global PWRDWN pin is released.

Individual ports (software power down) can be powered down using Control Register 0, bit 1. This

bit powers down a significant portion of the port, but clocks to the register section remain active.

This allows the management interface to remain active during register power-down. The power-

down bit is active High.

2.5.3.1

Global (Hardware) Power Down

The global power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the

following conditions are true:

• All LXT9785 ports and the clock are shut down.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

• All outputs are tri-stated.

• All weak pad pull-up and pull-down resistors are disabled.

• The MDIO registers are not accessible.

• Configuration pins are not read upon release of the PWRDWN pin, and registers are reloaded

with the value of the last Hardware reset.

2.5.3.2

Port (Software) Power Down

Individual port power-down control is provided by bit 0.11 in the respective port Control Registers

(refer to Table 57 on page 120). During individual port power-down, the following conditions are

true:

• The individual port is shut down.

• The MDIO registers remain accessible.

• Pull-up and pull-down resisters are not affected and the outputs are not tri-stated.

• The register remains unchanged.

2.5.4

Reset

The LXT9785 provides both hardware and software resets. Configuration control of Auto-

Negotiation, speed, and duplex mode selection is handled differently for each. During a hardware

reset, settings for bits 0.13, 0.12, and 0.8 are read in from the pins (refer to Table 18 for pin settings

and Table 57 on page 120 for register bit definitions).

During a software reset (0.15 = 1), the bit settings are not re-read from the pins, and revert back to

the values that were read in during the last hardware reset. Any changes to pin values from the last

hardware reset is not detected during a software reset.

During a hardware reset, register information is unavailable for 1 ms after deassertion of the reset.

All MII interface pins are disabled during a hardware reset and released to the bus on deassertion

of reset.

During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be

polled to see when the part has completed reset (0.15 = 0). Pull up and pull down resisters are not

affected.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.5.5

Hardware Configuration Settings

The LXT9785 provides a hardware option to set the initial device configuration. The hardware

option uses three Global CFG pins that provide control for all ports (see Table 18).

Table 18. Global Hardware Configuration Settings

CFG

Desired Mode

Resulting Register Bit Values

Pin Settings¹

AutoNeg

Speed

Duplex

0.12

0.13

0.8

4.8

4.7

4.6

4.5

Half

Full

Half

Full

Half

Full

Half

Full

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

N/A

Auto-Negotiation Advertisement

Disabled

100

N/A

Enabled

10/100

1. Refer to for CFG pin assignments.

2.6

Link Establishment

2.6.1

Auto-Negotiation

The LXT9785 attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP)

bursts. Each burst consists of 33 link pulses spaced 62.5 µs apart. Odd link pulses (clock pulses)

are always present. Link pulses (data pulses) may also be present or absent to indicate a “1” or a

“0”. Each FLP burst exchanges 16 bits of data, referred to as a “page”. All devices that support

auto-negotiation must implement the “Base Page”, defined by IEEE 802.3 (registers 4 and 5). The

LXT9785 also supports the optional “Next Page” function (registers 7 and 8).

2.6.1.1

2.6.1.2

Base Page Exchange

By exchanging Base Pages, the LXT9785 and its link partner communicate their capabilities to

each other. Both sides must receive at least three identical base pages for negotiation to proceed.

Each side finds their highest common capabilities, exchange more pages, and agree on the

operating state of the line.

Next Page Exchange

Additional information, exceeding that required by base page exchange, is also sent via “Next

Pages”. The LXT9785 fully supports the IEEE 802.3 method of negotiation via Next Page

exchange. The Next Page exchange uses register 7 to send information and register 8 to receive it.

Next Page exchange occurs only if both ends of the link advertise their ability to exchange Next

Pages. A special mode has been added to make next page exchange easier for software. When

negotiation occurs, preventing the user from reading an old value in register 6 and assuming there

is valid information in registers 5 and 8. Additionally, register 6 contains a new bit that indicates

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

when the current received page is the base page. This information is useful for recognizing when

next pages must be re-sent due to the start of a new negotiation process. Bit 16.1 and the page

received bit are also cleared upon reading register 6.

2.6.1.3

Controlling Auto-Negotiation

When auto-negotiation is controlled by software, the following steps are recommended:

• After power-up, power-down, or reset, the power-down recovery time, as specified in Table 54

on page 118, must be exhausted before proceeding.

• Set the auto-negotiation advertisement register bits.

• Enable auto-negotiation (set MDIO bit 0.12 = 1).

2.6.1.4

Link Criteria

In 100Mbps mode, link is established when the scrambler becomes locked and remains locked for

approximately 50ms. Link remains up unless the descrambler receives less than 12 consecutive idle

symbols in any 2 ms period. This provides a very robust operation, filtering out any small noise hits

that may disrupt the link.

In 10Mbps mode, link is established based on the link state machine found in IEEE 802.3, 14.X.

Receiving 100Mbps idle patterns does not bring up a 10Mbps link.

2.6.1.5

Parallel Detection

In parallel with auto-negotiation, the LXT9785 also monitors for 10Mbps Normal Link Pulses

(NLP) or 100Mbps Idle symbols. If either symbol is detected, the device automatically reverts to

the corresponding operating mode. Parallel detection allows the LXT9785 to communicate with

devices that do not support auto-negotiation.

Figure 15. Auto-Negotiation Operation

Power-Up, Reset,

Link Failure

Start

Disable

Auto-Negotiation

Enable

0.12 = 0

0.12 = 1

Auto-Neg/Parallel Detection

Check Value

0.12

Go To Forced

Settings

Attempt Auto-

Negotiation

Listen for 100TX

Idle Symbols

Listen for 10T

Link Pulses

YES

Done

Link Set?

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.7

Serial MII Operation

The LXT9785 exchanges transmit and receive data with the controller via the Serial MII (SMII).

The SMII performs the following functions:

• Conveys complete MII information between a 10/100 PHY and MAC with two pins per port.

• Allows a multi-port MAC/PHY communication with one system clock.

• Operates in both half and full duplex.

• Supports per-packet switching between 10Mbps and 100Mbps data rates.

The Serial MII operates at 125 MHz using a global reference clock and frame synchronization

signal (REFCLK and SYNC). Each port has an individual two-line data interface (TXDn and

RXDn). All signals are synchronous to REFCLK. Table 19 summarizes the SMII signals.

Data is exchanged in 10-bit serial words. Each word contains one data byte (two nibbles of 4B

coded data) and two status bits. When the port is operating at 100Mbps, each word contains a new

data byte. When the port is operating at 10Mbps, each data byte is repeated 10 times.

Table 19. SMII Signal Summary

Signal

TXD

PHY

From

MAC

Purpose

Transmit data & control

Synchronization

SYNC

RXD

PHY

MAC

PHY

Receive data & control

MAC &

PHY

REFCLK

System

Synchronization

1. Refer to Table 5 on page 41 for detailed signal descriptions.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 16. Typical SMII Interface Diagram

Typical SMII Interface

in a 16-Port System

SECTION

TxDatan

SYNC0

RxData

MDIO0

MDC0

MDINT0

RefCLK0 RefCLK1

125 MHz Sourced

Externally or from

Switch ASIC

SYSTEM CLK

RefCLK0 RefCLK1

TxDatan

SYNC0

RxDatan

MDIO0

MDC0

MDINT0

SECTION

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 17. Typical SMII Quad Sectionalization Diagram

Typical SMII Interface in a

24-Port System

RefClk0 RefClk1

TxDatan

SYNC0

RxDatan

MDIO0

MDC0

MDINT0

SECTION

TxData

SYNC0

RxData

MDIO0

MDC0

MDINT0

RefClk0

125 MHz Sourced

Externally or from

Switch ASIC

RefClk1

TxDatan

SYNC1

RxData

VCC

MDINT1

MDIO1

MDC1

SECTION

MDINT0

MDIO0

MDC0

TxDatan

SYNC0

RxDatan

SECTION

RefClk0 RefClk1

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 18. 100Mbps Serial MII Data Flow

Strip

Serial Data Stream

To/From

TX_EN &

TX_ER

Status

Bits

2 Nibbles Tx/Rx Data

2 Symbols Tx/Rx Data

S0 S1 S2 S3 S4

MAC

S0 S1 D0 D1 D2

D0 D1 D2 D3

4B/5B

To/From

PMD

Sublayer

Insert

CRS &

RX_DV

Status

Bits

D3 D4 D5 D6 D7

S0 S1 S2 S3 S4

2.7.1

2.7.2

2.7.3

SMII Reference Clock

The REFCLK operates at 125 MHz. The transmit and receive data and control streams must always

be synchronized to the REFCLK by the MAC and PHY. The LXT9785 samples these signals on

the rising edge of the REFCLK.

TxSYNC Pulse (SMII/SS-SMII)

The TxSYNC pulse delimits segment boundaries and synchronizes with REFCLK. The MAC must

continuously generate a TxSYNC pulse once every 10 REFCLK cycles. The TxSYNC pulse

signals the start of each new segment (see Figure 22 on page 72).

Transmit Data Stream

Transmit data and control information are signaled in ten- bit segments. In 100Mbps mode, each

segment contains a new byte of data. In 10Mbps mode, the MAC must repeat a 10M serial word

ten times on TXD. The LXT9785 may sample that serial word at any point.

The TxSYNC pulse signals the start of a new segment as shown in Figure 19 on page 68.

2.7.3.1

2.7.3.2

Transmit Enable

The MAC must assert the TX_EN bit in each segment of TXData, and de-assert TX_ENn after the

last segment of the packet.

Transmit Error

When the MAC asserts the TX_ER bit in 100BASE-X mode, the LXT9785 drives “H” symbols

onto the network interface. TX_ER does not have any function in 10M operation.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 19. Serial MII Transmit Synchronization

CLOCK

TxSYNC

TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TX_ER

2.7.4

Receive Data Stream

Receive data and control information are signalled in ten- bit segments. In 100Mbps mode, each

segment contains a new byte of data. In 10Mbps mode, each segment is repeated ten times (except

for the CRS bit), and the MAC can sample any of the ten segments.

2.7.4.1

2.7.4.2

Carrier Sense

The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS

bit is set in real time, even in 10Mbps mode (all other bits are repeated in 10 sequential segments).

Receive Data Valid

The LXT9785 asserts the RX_DV bit (slot 1) when it receives a valid packet. The assertion timing

changes depending on line operating speed:

• For 100 TX and 100 FX links, the RX_DV bit is asserted from the first nibble of preamble to

the last nibble of the data packet.

• For 10 BT links, the entire preamble is truncated. The RX_DV bit is asserted with the first

nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of the

packet.

2.7.4.3

2.7.4.4

Receive Error

When the LXT9785 receives an invalid symbol from the network in 100BASE-TX mode, it drives

“1110” on the associated RXD pin.

Receive Status Encoding

The LXT9785 encodes status information onto the RXD line during IPG as seen in Table 20 on

page 69. Status bit RXD<5> indicates the validity of the upper nibble (RXD<7:4> of the last byte

of the previous frame). RXD and RX_DV are passed through the internal elasticity FIFO to smooth

any clock rate differences between the recovered clock and the 125 MHz reference clock.

2.7.5

Collision

The SMII interface does not provide a collision output and relies on the MAC to interpret COL

conditions using CRS and TX_EN. CRS is unaffected by the transmit path.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 20. Serial MII Receive Synchronization

CLOCK

RxSYNC

RXD0

RXER

RXD1

Speed

RXD2

Duplex

RXD3

Link

RXD4

Jabber

RXD5

Valid

RXD6

FCE

RXD7

CRS

RX_DV

Table 20. RX Status Encoding Bit Definitions

Signal

Definition

Carrier Sense - identical to MII, except that it is not an asynchronous signal.

CRS

Receive Data Valid - identical to MII. When RX_DV = 0, status information is

transmitted to the MAC. When RX_DV = 1, received data is transmitted to the

MAC.

0 = Status Byte

1 = Valid Data Byte

RX_DV

RX_ER

(RXD0)

Inter-frame status bit RXD0 indicates whether or not the PHY detected an error

somewhere in the previous frame.

0 = No Error

1 = Error

SPEED

(RXD1)

0 = 10Mbps

1 = 100Mbps

Inter-frame status bit RXD1 indicates port operating speed.

Inter-frame status bit RXD2 indicates port duplex condition.

Inter-frame status bit RXD3 indicates port link status.

Inter-frame status bit RXD4 indicates port jabber status.

DUPLEX

(RXD2)

0 = Half

1 = Full

LINK

(RXD3)

0 = Down

1 = Up

JABBER

(RXD4)

0 = OK

1 = Error

VALID

(RXD5)

Inter-frame status bit RXD5 conveys the validity of the upper nibble of the last byte 0 = Invalid

of the previous frame. 1 = Valid

False Carrier

(RXD6)

Inter-frame status bit RXD6 indicates whether or not the PHY has detected a false 0 = No FC detected

carrier event.

1 = FC detected

RXD7

This bit is set to 1.

Always = 1

1. Both RXD0 and RXD5 bits are valid in the segment immediately following a frame, and remain valid until the first data

segment of the next frame begins.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.7.5.1

Source Synchronous SMII

Some system designs require the PHY to be placed between 3 to 12 inches away from the MAC. A

new source synchronous SMII definition has been added because of this requirement. To provide a

source synchronous interface between the PHY and MAC, the PHY must drive the RxClk and the

RxSYNC signals to the MAC. Also, the MAC must drive the TxClk and the TxSYNC signal to the

PHY. The RefClk is also needed to synchronize the data to the PHY’s core clock domain. TxData is

clocked in using TxClk and then synchronized to RefClk and transmitted to the twisted-pair. The

RxData is synchronized to the RxClk. See Figure 24 on page 73.

Table 21. Source Synchronous SMII

Signal

TxData

PHY

From

MAC

Purpose

Transmit data & control

Transmit clock

TxCLK

PHY

MAC

PHY

TxSYNC

RxData

RxCLK

RxSYNC

RefClk

Synchronization pulses

Receive data & control

Receive clock

PHY

Receive Synchronization

Synchronization

System

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 21. Typical SS-SMII Interface Diagram

Typical SS-SMII Interface in

a 16-Port System

SECTION

TxDatan

TxSYNC0

TxCLK0

RxDatan

RxSYNC1

RxCLK1

MDIO0

MDC0

MDINT0

RefCLK0,1

125 MHz Sourced

Externally or from

Switch ASIC

SYS_CLK

RefCLK0,1

TxDatan

TxSYNC0

TxCLK0

RxData

RxSYNC1

RxCLK1

MDIO0

MDC0

MDINT0

SECTION

Note: For SMII operation TxCLK1, RxSYNCn and RxCLKn pins are ignored

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 22. Typical SS-SMII Quad Sectionalization Diagram

Typical SS-SMII Interface

in a 24-Port System

RefClk0 RefClk1

TxDatan

TxSYNC0

TxCLK0

RxDatan

RxSYNC1

RxCLK1

MDIO0

MDC0

MDINT0

SECTION

TxDatan

TxSYNC0

TxCLK0

RxData

RxSYNC0

RxCLK0

MDIO0

MDC0

MDINT0

RefClk0

125 MHz Sourced

Externally or from

Switch ASIC

RefClk1

TxData

TxSYNC1

TxCLK1

RxData

RxSYNC1

RxCLK1

VCC

MDINT1

MDIO1

MDC1

SECTION

MDINT0

MDIO0

MDC0

TxData

TxSYNC0

TxCLK0

RxData n

RxSYNC1

RxCLK1

SECTION

RefClk0 RefClk1

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 23. Source Synchronous Transmit Timing

SS-SMII Transmit Timing

TxCLK

TxSYNC

TxData

TXER

TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER

TxCLK

TxSYNC

TxData

TXER

Frcerr Speed

Dplx LINK Jabr

TXEN

TXER

All signals are

synchronous to the clock

Figure 24. Source Synchronous Receive Timing

SS-SMII Receive Timing

RxCLK

RxSYNC

RxData

CRS

RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS

RxCLK

RxSYNC

RxData

CRS

RXERSpeed

CRS

RXDV

Dplx LINK Jabr UPnib FlsCar

All signals are

synchronous to the clock

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.8

RMII Operation

The LXT9785 provides an independent Reduced MII port for each network port. Each RMII uses

four signals to pass received data to the MAC: RXDn<1:0>, RXERn, and CRS_DVn (where n

reflects the port number). Three signals are used to transmit data from the MAC: TXDn_<1:0> and

TXENn. Both receive and transmit signals are clocked by REFCLK. Data transmission across the

RMII is implemented in di-bit pairs which equal a 4-bit wide nibble.

2.8.1

2.8.2

RMII Reference Clock

The LXT9785 requires a 50 MHz reference clock (REFCLK). The device samples the RMII input

signals on the rising edge of REFCLK and drives RMII output signals on the falling edge.

Transmit Enable

TXENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert

TXENn at the same time as the first nibble of preamble. TXENn must be de-asserted after the last

bit of the packet.

2.8.3

2.8.4

Carrier Sense & Data Valid

The LXT9785 asserts CRS_DVn when it detects activity on the line. However, RXDn outputs

zeros until the received data is decoded and available for transfer to the controller.

Receive Error

Whenever the LXT9785 receives an errored symbol from the network, it asserts RXERn. When it

detects a bad Start-of-Stream Delimiter (SSD) it drives a “10” jam pattern on the RXD pins to

indicate a false carrier event.

2.8.5

2.8.6

Out-of-Band Signalling

The LXT9785 has the capability of encoding status information in the RXData stream during IPG.

See “Monitoring Operations” on page 84 for details.

4B/5B Coding Operations

The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However,

data is normally transmitted across the RMII interface in 2-bit nibblets or “di-bits”. The LXT9785

incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit nibbles, and a

4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit symbols for the

100BASE-X connection. Figure 25 on page 75 shows the data conversion flow from nibbles to

symbols. Table 22 on page 80 shows 4B/5B symbol coding (not all symbols are valid).

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 25. RMII Data Flow

Reduced MII Mode Data Flow

Parallel

Serial

Scramble

D0 D2

D1 D3

-1

4B/5B

MLT3

D0 D1 D2 D3

S0 S1 S2 S3 S4

De-

Scramble

Transition = 1.

No Transition = 0.

All transitions must follow

pattern: 0, +1, 0, -1, 0, +1...

Serial

Parallel

di-bit

pairs

4-bit

nibbles

5-bit

symbols

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 26. Typical RMII Interface Diagram

Typical RMII Interface

in a 16-Port System

SECTION

TxD0n

TxD1n

TxENn

RxD0n

RxD1n

CRS_DVn

RxERn

MDIO0

MDC0

MDINT0

RefClk0

RefClk1

50 Mhz Sourced

Externally or from

Switch ASIC

RefClk0

MDINT0

RefClk1

MDIO0

MDC0

TxD0

TxD1

TxEN

RxD0

RxD1

CRS_DV

RxER

SECTION

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 27. Typical RMII Quad Sectionalization Diagram

Typical RMII Interface

in a 24-Port System

RefClk0 RefClk1

TxD0n

TxD1n

TxENn

RxD0n

RxD1n

CRS_DVn

RxERn

MDIO0

MDC0

MDINT0

SECTION

TxD0n

TxD1n

TxENn

RxD0n

RxD1n

CRS_DVn

RxERn

MDIO0

MDC0

MDINT0

RefClk0

50 MHz Sourced

Externally or from

Switch ASIC

RefClk1

TxD0

TxD1

TxEN

RxD0

RxD1

CRS_DV

VCC

RxER

MDINT1

MDIO1

MDC1

SECTION

MDINT0

MDIO0

MDC0

TxD0

TxD1

TxEN

RxD0

RxD1

CRS_DV

RxER

SECTION

RefClk0 RefClk1

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.9

100Mbps Operation

2.9.1

100BASE-X Network Operations

During 100BASE-X operation, the LXT9785 transmits and receives 5-bit symbols across the

network link. Figure 28 shows the structure of a standard frame packet. When the MAC is not

actively transmitting data, the LXT9785 sends out Idle symbols on the line.

In 100BASE-TX mode, the device scrambles the data and transmits it to the network using MLT-3

line code. The MLT-3 signals received from the network are descrambled and decoded, and sent

across the RMII to the MAC.

In 100BASE-FX mode, the LXT9785 transmits and receives NRZI signals across the PECL

interface. An external 100FX transceiver module is required to complete the fiber connection.

As shown in Figure 28, the MAC starts each transmission with a preamble pattern. As soon as the

LXT9785 detects the start of preamble, it transmits a J/K Start-of-Stream Delimiter (SSD) symbol

to the network. It then encodes and transmits the rest of the packet, including the balance of the

preamble, the Start-of-Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the

LXT9785 transmits the T/R End-of-Stream Delimiter (ESD) symbol and then returns to

transmitting Idle symbols.

Figure 28. 100BASE-X Frame Format

64-Bit Preamble

(8 Octets)

Destination and Source

Address (6 Octets each)

Packet Length

(2 Octets)

Data Field

(Pad to minimum packet size)

Frame Check Field InterFrame Gap / Idle Code

(4 Octets)

(> 12 Octets)

CRC

IFG

SFD

P0 P1 P6

DA DA SA SA L1

D0 D1 Dn

Replaced by

/T/R/ code-groups

End-of-Stream Delimiter (ESD)

Replaced by

Start-of-Frame

Delimiter (SFD)

/J/K/ code-groups

Start-of-Stream

Delimiter (SSD)

2.9.2

100BASE-X Protocol Sublayer Operations

In a 7-layer communications model, the LXT9785 is a Physical Layer 1 (PHY) device. The

LXT9785 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA),

and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE

802.3u specification. The following paragraphs discuss the LXT9785 operation from the reference

model point of view.

2.9.2.1

PCS Sublayer

The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/

decoding function. For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the

PMD-layer line driver as long as TXEN is de-asserted. For 10T operation, the PCS layer merely

provides a bus interface and serialization/de-serialization function. 10T operation does not use the

4B/5B encoder.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Preamble Handling

When the MAC asserts TXEN, the PCS substitutes a /J/K/ symbol pair, also known as the Start-of-

Stream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer

continues to encode the remaining RMII data until TXEN is de-asserted (see Table 22 on page 80).

It then returns to supplying IDLE symbols to the line driver.

The PCS layer performs the opposite function in the receive direction by substituting two preamble

nibbles for the SSD.

Dribble Bits

The LXT9785 handles dribbles bits in all modes. If one through four dribble bits are received, the

nibble is passed across the RMII, padded with ones if necessary. If five through seven dribble bits

are received, the second nibble is not sent to the RMII bus.

Figure 29. Protocol Sublayers

MII Interface

LXT9785

PCS

Encoder/Decoder

Serializer/De-serializer

Sublayer

PMA

Sublayer

Link/Carrier Detect

PECL Interface

PMD

Sublayer

Scrambler/

De-scrambler

Fiber Transceiver

100BASE-TX

100BASE-FX

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.9.3

PMA Sublayer

Table 22. 4B/5B Coding

4B Code

Code Type

5B Code

4 3 2 1 0

Name

Interpretation

3 2 1 0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

1 1 1 1 0

0 1 0 0 1

1 0 1 0 0

1 0 1 0 1

0 1 0 1 0

0 1 0 1 1

0 1 1 1 0

0 1 1 1 1

1 0 0 1 0

1 0 0 1 1

1 0 1 1 0

1 0 1 1 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 1

1 1 1 11

1 1 0 0 0

1 0 0 0 1

0 1 1 0 1

0 0 1 1 1

0 0 1 0 0

0 0 0 0 0

0 0 0 0 1

0 0 0 1 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 1 0 0

1 0 0 0 0

1 1 0 0 1

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

Data 8

Data 9

Data A

Data B

Data C

Data D

Data E

Data F

DATA

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

I ¹

J ²

K ²

T ³

R ³

H ⁴

IDLE

undefined

0 1 0 1

Idle. Used as inter stream fill code.

Start-of-Stream Delimiter (SSD), part 1 of 2.

CONTROL

0 1 0 1

Start-of-Stream Delimiter (SSD), part 2 of 2.

undefined

End-of-Stream Delimiter (ESD), part 1 of 2.

End-of-Stream Delimiter (ESD), part 2 of 2.

Transmit Error. Used to force signalling errors.

Invalid

INVALID

1. The /I/ (Idle) code group is sent continuously between frames.

2. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/.

3. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/.

4. An /H/ (Error) code group is used to signal an error condition.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Link

In 100Mbps mode, the LXT9785 establishes a link whenever the scrambler becomes locked and

remains locked for approximately 50 ms. Whenever the scrambler loses lock (<12 consecutive idle

symbols during a 2 ms window), the link is taken down. This provides a robust link, filtering out

any small noise hits that may otherwise disrupt the link. Furthermore, 100Mbps idle patterns will

not bring up a 10Mbps link.

The LXT9785 reports link failure via the RMII status bits (1.2, 17.10, and 19.4) and interrupt

functions. If auto-negotiate is enabled, link failure causes the device to re-negotiate.

Link Failure Override

The LXT9785 normally transmits 100Mbps data packets or Idle symbols only if it detects the link

is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1 overrides this

function, allowing the LXT9785 to transmit data packets even when the link is down. This feature

is provided as a diagnostic tool.

Note: Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-

negotiation is enabled, the LXT9785 automatically begins transmitting FLP bursts if the link goes

down.

Carrier Sense/Data Valid (RMII)

The LXT9785 asserts CRS_DV whenever the respective port receiver is in a non-idle state (as

defined by the RMII Specification Revision 1.2), including false carrier events. Assertion of

CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not

complete when CRS_DV is asserted, the LXT9785 outputs 00 on the RXD1:0 lines until the

decoded data are available.

When the line returns to an idle state, CRS_DV is de-asserted asynchronously with respect to

REFCLK. If the FIFO still contains data to be passed to the MAC via the RMII when CRS is de-

asserted, CRS_DV toggles on nibble boundaries until the FIFO is empty. For 100BASE-X signals,

CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz.

Carrier Sense (SMII)

For 100TX and 100FX links, a Start-of-Stream Delimiter (SSD) or /J/K/ symbol pair causes

assertion of carrier sense (CRS). An End-of-Stream Delimiter (ESD), or /T/R/ symbol pair causes

de-assertion of CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/

R/. In this event, the RX_ER bit in the RX Status Frame is asserted for one clock cycle when CRS

is de-asserted.

For 10T links, CRS assertion is based on receipt of valid preamble, and de-assertion on receipt of

an End-of-Frame (EOF) marker.

Receive Data Valid (SMII)

The LXT9785 asserts the RX_DV bit when it receives a valid packet. However, RXD outputs zeros

until the received data are decoded and available for transfer to the controller.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.9.3.1

Twisted-Pair PMD Sublayer

The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and

descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as

receiving, polarity correction, and baseline wander correction functions.

Scrambler/Descrambler (100TX Only)

The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using

an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial

whenever IDLE symbols are received.

The scrambler/descrambler can be bypassed by setting bit 16.12 = 1. The scrambler is

automatically bypassed when the fiber port is enabled. Scrambler bypass is provided for diagnostic

and test support.

Baseline Wander Correction

The LXT9785 provides a baseline wander correction function which makes the device robust

under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is, by

definition, “unbalanced”. This means that the DC average value of the signal voltage can “wander”

significantly over short time intervals (tenths of seconds). This wander may cause receiver errors,

particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the

wander are completely data dependent.

The LXT9785 baseline wander correction characteristics allow the device to recover error-free data

while receiving worst-case “killer” packets over all cable lengths.

Polarity Correction

The LXT9785 automatically detects and corrects for the condition where the receive signal

(TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses or four inverted

End-of-Frame (EOF) markers are received consecutively. If link pulses or data are not received by

the maximum receive time-out period, the polarity state is reset to a non-inverted state.

2.9.3.2

Fiber PMD Sublayer

The LXT9785 provides a PECL interface for connection to an external fiber-optic transceiver. (The

external transceiver provides the PMD function for fiber media.) The device uses an NRZI format

for the fiber interface. The fiber interface operates at 100Mbps and does not support 10FL

applications.

Far End Fault Indications

The LXT9785 Signal Detect pins independently detect signal faults from the local fiber

transceivers via the SD pins. The device also uses bit 1.4 to report Remote Fault indications

received from its link partner. The device “ORs” both fault conditions to set bit 1.4. Bit 1.4 is set

once and clears when read.

Either fault condition causes the LXT9785 to drop the link unless Forced Link Pass is selected

(16.14 = 1). Link down condition is then reported via interrupts and status bits.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

In response to locally detected signal faults (SD activated by the local fiber transceiver), the

affected port can transmit the far end fault code if fault code transmission is enabled by bit 16.2.

• When bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT9785 transmits

far end fault code if fault conditions are detected by the Signal Detect pins.

• When bit 16.2 = 0, the LXT9785 does not transmit far end fault code. It continues to transmit

idle code and may or may not drop link depending on the setting for bit 16.14.

The occurrence of a Far End Fault causes all transmission of data from the Reconciliation Sublayer

to stop and the Far End fault code to begin. The Far End Fault code consists of 84 ones’s followed

by a single “0” and is repeated until the Far End Fault condition is removed.

2.10

10Mbps Operation

The LXT9785 operates as a standard 10BASE-T transceiver and supports all the standard 10Mbps

functions. During 10BASE-T (10T) operation, the LXT9785 transmits and receives Manchester-

encoded data across the network link. When the MAC is not actively transmitting data, the device

sends out link pulses on the line.

In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals

received from the network are decoded by the LXT9785 and sent across the RMII to the MAC.

Note: The LXT9785 does not support fiber connections at 10Mbps.

2.10.1

Preamble Handling

The LXT9785 offers two options for preamble handling, selected by bit 16.5. In 10T Mode when

bit 16.5 = 0, the device strips the entire preamble off the received packets. CRS_DV is asserted

simultaneously with SFD. CRS_DV is held Low for the duration of the preamble. When CRS_DV

is asserted, the very first two nibbles driven by the LXT9785 are the SFD “5D” hex followed by the

body of the packet.

When bit 16.5 = 1 in 10T mode, the LXT9785 passes the preamble through the RMII and asserts

CRS_DV simultaneously.

2.10.2

2.10.3

Dribble Bits

The LXT9785 device handles dribble bits in all modes. If one through four dribble bits are

received, the nibble is passed across the RMII. If five through seven dribble bits are received, the

second nibble is not sent onto the RMII bus.

Link Test

The LXT9785 always transmits link pulses in 10T mode. When enabled, the link test function

monitors the connection for link pulses. Once link pulses are detected, data transmission is enabled

and remains enabled as long as either the link pulses or data transmission continue. If link pulses

stop, the data transmission is disabled.

If the link test function is disabled, the LXT9785 transmits to the connection regardless of detected

link pulses. The link test function is disabled by setting bit 16.14 = 1.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

2.10.3.1

2.10.4

Link Failure

Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this

condition occurs, the LXT9785 returns to the auto-negotiation phase if auto-negotiation is enabled.

Jabber

If a transmission exceeds the jabber timer, the LXT9785 disables the transmit and loopback

functions. The RMII does not include a Jabber pin, but the MAC may read Register 1 or 25 to

determine Jabber status. The LXT9785 automatically exits jabber mode after the unjab time has

expired. This function is disabled by setting bit 16.10 = 1.

2.11

Monitoring Operations

2.11.1

Monitoring Auto-Negotiation

Auto-negotiation may be monitored as follows:

• Bits 1.2 and 17.10 = 1 once the link is established.

• Additional bits in Register 1 (refer to Table 58 on page 121) and Register 17 (refer to Table 67

on page 128) can be used to determine the link operating conditions and status.

2.11.2

Per-Port LED Driver Functions

The LXT9785 incorporates three direct drive LEDs per port (LEDn_1, LEDn_2, and LEDn_3). On

power up, all the LEDs lights up for approximately one second after reset de-asserts. Each LED

may be programmed to one of several different display modes using the LED Configuration

the following conditions:

• Operating Speed

• Transmit Activity

• Receive Activity

• Collision Condition

• Link Status

• Duplex Mode

• Isolate Condition

The LEDs can also be programmed to display various combined status conditions. For example,

setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications:

• If Link is down, LED is off.

• If Link is up, LED is on.

• If Link is up AND activity is detected, the LED blinks at the stretch interval selected by bits

20.3:2 and continues to blink as long as activity is present.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

The LED driver pins are open drain circuits (10mA max current rating). Refer to “LED Circuit” on

page 90 under the Application Information Section for LED circuit design details. The LED

Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during

this pulse stretch period, the event occurs again, the pulse stretch time is further extended (see

Table 70 on page 131).

When an event such as receiving a packet occurs, it is edge detected and starts the stretch timer.

The LED driver remains asserted until the stretch timer expires. If another event occurs before the

stretch timer expires, the stretch timer is reset and the stretch time extended.

When a long event (such as duplex status) occurs, it is edge detected and starts the stretch timer.

When the stretch timer expires, the edge detector is reset so that a long event causes another pulse

to be generated from the edge detector. The edge detector resets the stretch timer, causing the LED

driver to remain asserted. Figure 30 shows how the stretch operation functions.

Figure 30. LED Pulse Stretching

Event

LED

stretch

Note: The direct drive LED outputs in this diagram are shown as active Low.

2.11.3

Out-of-Band Signalling

The LXT9785 provides an out-of-band signalling option to transfer status information across the

RMII receive interface. This feature is enabled when register 25.0 = 1 and uses the RXD(1:0) data

bus during the Inter-Packet Gap (IPG) time as shown in Figure 31.

The two status bits transferred across the RXD bus are software selectable via Register 25 (see

Table 72 on page 133).

In normal operation, the LXT9785 stuffs the RXD bus with zeros during the IPG. A software-

selectable bit enables the RMII out-of-band signalling feature. Once this bit is set, the LXT9785

replaces the zeros with selected status bits during the IPG.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 31. RMII Programmable Out-of-Bank Signaling

REFCLK

CRS_DV

status 1

status 0

status 1

status 0

data

status 1

status 0

status 1

status 0

status 1

status 0

status 1

status 0

RX D(1)

RX D(0)

status 1

status 0

1. When network activity is detected, the LXT9785 asserts CRS_DV asynchronously with respect to REFCLK.

2. After CRS_DV is asserted, the LXT9785 will zero-stuff the RXData bits until the received data has been processed through

the FIFO.

3. When network activity ceases, the LXT9785 de-asserts CRS_DV synchronously with respect to REFCLK. CRS_DV will

toggle until all data in the FIFO has been processed through the RMII. Once the FIFO is empty, LXT9785 will drive the status

bits selected by the Out-of-Band Signalling Register (refer to Table 72 on page 133) on the RXD outputs.

The LXT9785 includes an IEEE 1149.1 boundary scan test port for board level testing. All digital

input, output, and input/output pins are accessible.

2.11.4

Boundary Scan Interface

This interface consists of five pins (TMS, TDI, TDO, TCK and TRST). It includes a state machine,

data register array, and instruction register. The TMS and TDI pins are internally pulled up and the

TCK pin is internally pulled down. TDO does not have an internal pull-up or pull-down.

2.11.5

2.11.6

State Machine

The TAP controller is a 16-state machine driven by the TCK and TMS pins. Upon reset, the

TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are

High for five TCK periods.

Instruction Register

The IDCODE instruction is always invoked after the state machine resets. The decode logic

ensures the correct data flow to the Data registers according to the current instruction. Valid

instructions are listed in Table 24 on page 87.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

2.11.7

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two stages. A flip-flop and a latch are used for the

serial shift stage and the parallel output stage. There are four modes of operation as listed in Table

23.

Table 23. BSR Mode of Operation

Mode

Description

Capture

Shift

Update

System Function

Table 24. Supported JTAG Instructions

Data

Name

Code

Description

External Test

EXTEST

IDCODE

SAMPLE

High Z

0000000000000000

1111111111111110

1111111111111000

1111111111001111

1111111111101111

1111111111111111

BSR

ID Code Inspection

Sample Boundary

Force Float

ID REG

BSR

Bypass

BSR

Clamp

BYPASS

Bypass Scan

Bypass

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

3.0

Application Information

3.1

Design Recommendations

The LXT9785 is designed to comply with IEEE 802.3 requirements to provide outstanding receive

Bit Error Rate (BER), and long-line-length performance. To achieve maximum performance from

the LXT9785, attention to detail and good design practices are required. Refer to the LXT9785

Design and Layout Guide application note for detailed design and layout information.

3.2

General Design Guidelines

Adherence to generally accepted design practices is essential to minimize noise levels on power

and ground planes. Up to 50 mV maximum of noise is considered acceptable. High-frequency

switching noise can be reduced, and its effects eliminated, by following these simple guidelines

throughout the design:

• Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC

or ground plane that is not located adjacent to the signal layer.

• Use ample bulk and decoupling capacitors throughout the design (a value of 0.01 µF is

recommended for decoupling caps).

• Provide ample power and ground planes.

• Provide termination on all high-speed switching signals and clock lines.

• Provide impedance matching on long traces to prevent reflections.

• Route high-speed signals next to a continuous, unbroken ground plane.

• Filter and shield DC-DC converters, oscillators, etc.

• Do not route any digital signals between the LXT9785 and the RJ-45 connectors at the edge of

the board.

• Do not extend any circuit power and ground plane past the center of the magnetics or to the

edge of the board. Use this area for chassis ground, or leave it void.

3.2.1

Power Supply Filtering

Power supply ripple and digital switching noise on the VCC plane may cause EMI problems and

degrade line performance. The best approach to this problem is to minimize ground noise as much

as possible using good general techniques and by filtering the VCC plane. It is generally difficult

to predict in advance the performance of any design, although certain factors greatly increase the

risk of having problems:

• Poorly-regulated or over-burdened power supplies.

• Wide data busses (32-bits+) running at a high clock rate.

• DC-to-DC converters.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Intel recommends filtering the power supply to the analog VCC pins of the LXT9785. This has two

benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT9785,

helping with line performance. Second, if the VCC planes are laid out correctly, digital switching

noise is kept away from external connectors, reducing EMI problems.

The recommended implementation is to break the VCC plane into two sections. The digital section

supplies power to the VCCD and VCCIO pins of the LXT9785. The analog section supplies power

to the VCCA pins. The break between the two planes should run underneath the device. In designs

with more than one the LXT9785, a single continuous analog VCC plane can be used to supply

them all.

The digital and analog VCC planes should be joined at one or more points by ferrite beads. The

beads should produce at least a 100Ω impedance at 100 MHz. Beads should be placed so that

current flow is evenly distributed. The maximum current rating of the beads should be at least

150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10 uF) should

be placed on each side of each bead.

In addition, a high-frequency bypass cap (0.01uF) should be placed near each analog VCC pin.

3.2.2

Power and Ground Plane Layout Considerations

Great care needs to be taken when laying out the power and ground planes.

• Follow the guidelines in the LXT9785 Design and Layout Guide (Application Note 151) for

locating the split between the digital and analog VCC planes.

• Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the magnetics, and

the RJ-45 connectors.

• Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the

ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.

3.2.2.1

Chassis Ground

For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the

board and is isolated via moats and keep-out areas from all circuit-ground planes and active

signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used

to terminate unused signal pairs (Bob Smith termination). In single-point grounding applications,

provide a single connection between chassis and circuit grounds with a 2 kV isolation capacitor. In

multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide

2 kV isolation to the Bob Smith termination.

3.2.3

MII Terminations

Series termination resistors are required on all the SS-SMII output signals driven by the LXT9785.

Special trace layout consideration should be used when using the SMII interface. Keep all traces

orthogonal and as short as possible. Whenever possible, route the clock and sync traces evenly

between the longest and shortest data routes. This minimizes round-trip, clock-to-data delays and

allows a larger margin to the setup and hold requirements.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

3.2.4

Twisted-Pair Interface

Use the following standard guidelines for a twisted-pair interface:

• Place the magnetics as close as possible to the LXT9785.

• Keep transmit pair traces as short as possible; both traces should have the same length.

• Avoid vias and layer changes as much as possible.

• Keep the transmit and receive pairs apart to avoid cross-talk.

• Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the

transmit traces two to three layers from the ground plane, with no intervening signals.

• Improve EMI performance by filtering the TPO center tap. A single ferrite bead rated at 400

mA may be used to supply center tap current to all ports.

3.2.4.1

Magnetics Information

The LXT9785 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit

transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from

static voltages across the connectors and cables. Refer to Table 25 on page 91 for transformer

requirements. Before committing to a specific component, designers should contact the

manufacturer for current product specifications, and validate the magnetics for the specific

application.

3.2.5

3.2.6

The Fiber Interface

The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic

transceiver. The transmit and receive pair should be DC-coupled to the transceiver, and biased

appropriately. Refer to the fiber transceiver manufacturer’s recommendations for termination

circuitry. Figure 35 on page 93 shows a typical example.

LED Circuit

Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected via a current-

limiting resistor to a positive-voltage rail. The LEDs are turned on when the output pin drives Low.

The open-drain LED pins are 5V tolerant, allowing use of either a 3.3V or 5V rail. A 5V rail eases

LED component selection by allowing more common, high-forward voltage LEDs to be used.

Refer to Figure 32 for a circuit illustration.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 32. LED Circuit

V_LED

LEDn_m

Outside

Inside

V_LED= 3.3 to 5 Volts +/- 5%

Table 25. Magnetics Requirements

Parameter

Min

Nom

Max

Units

Test Condition

Rx turns ratio

–

1:1

0.6

–

Tx turns ratio

–

Insertion loss

0.0

350

–

1.1

–

µH

Primary inductance

Transformer isolation

–

Differential to common mode

rejection

–

.1 to 60 MHz

-16

-10

–

60 to 100 MHz

30 MHz

Return Loss

80 MHz

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

3.3

Typical Application Circuits

Figure 33 through Figure 35 show typical application circuits for the LXT9785.

Figure 33. Power and Ground Supply Connections

SGND

GNDR/GNDT

0.01µF

VCCR/VCCT

10µF

Analog Supply Plane

Ferrite

Bead

LXT9785

Digital Supply Plane

10µF

+2.5V

VCCD

GNDD

VCCIO

0.01µF

+ 2.5V

or +3.3V

+2.5V

or +3.3V

VCCPECL

GNDPECL

0.1µF

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 34. Typical Twisted-Pair Interface

TPFOP

RJ-45

1:1

TPFON

TPFIP

Ω

1:1

LXT9785

Ω

TPFIN

.01 µF

* = 0.001

F /

* = 0.001

µF /

2.0 kV

VCCT

.01µF

0.1µF

GNDA

1. The 100Ω transmit load termination resistor typically required is integrated in the LXT9785.

2. The 100Ω receive load termination resistor typically required is integrated in the LXT9785.

Figure 35. Typical Fiber Interface

VCCPECL

+3.3V

Ω

0.01- 0.1uF

Ω

TPFONn

TPFOPn

TD-

TD+

VCCPECL

+3.3V

LXT9785

Fiber Txcvr

130

Ω

SD/TPn

Ω

GNDS

TPFINn

TPFIPn

RD-

RD+

2D_2P5V

130

Ω

130

GNDS

Ω

GNDPECL

3.3V

VCCPECL

1. The SD_2P5V pin must be connected to the VCCPECL supply.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

4.0

Test Specifications

Note: Table 26 through Table 55 and Figure 36 through Figure 59 represent the target specifications of

the LXT9785. These specifications are not guaranteed and are subject to change without notice.

Minimum and maximum values listed in Table 28 through Table 55 apply over the recommended

operating conditions specified in Table 27.

Table 26. Absolute Maximum Ratings

Parameter

Sym

Min

Max

Units

Supply voltage

Operating temperature

VCC

TOPA

TOPC

TST

-0.3

3.46

+85

Ambient

Case

ºC

–

+120

+150

Storage temperature

-65

Caution: Exceeding these values may cause permanent damage. Functional operation under these

conditions is not implied. Exposure to maximum rating conditions for extended periods may

affect device reliability.

Table 27. Operating Conditions

Typ

Parameter

Sym

Min

Max

Units

(2.5 VCCIO)

(3.3 VCCIO)

Ambient

TOPA

TOPC

–

108

2.63

3.46

2.63

810

160

410

200

765

ºC

Operating temperature

Supply voltage²

Case

–

Analog & Digital

I/O

Vcca, Vccd

Vccio

2.38

3.14

2.38

–

2.5

N/A

2.5

3.3

N/A

I/O (SD_2P5V = 0)

I/O (SD_2P5V = 1)

VCCPECL

ICC

ICCIO

ICC

780

380

710

100BASE-TX

100BASE-FX

–

130

170

–

ICCIO

ICC

–

Operating Current - RMII 10BASE-T

ICCIO

ICC

–

Power-Down Mode

Hardware

ICCIO

ICC

–

500

540

Auto-Negotiation

ICCIO

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Voltages with respect to ground unless otherwise specified.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 27. Operating Conditions (Continued)

Typ

Parameter

Sym

Min

Max

Units

(2.5 VCCIO)

(3.3 VCCIO)

ICC

–

800

380

740

830

160

410

200

770

130

100BASE-TX

100BASE-FX

10BASE-T

ICCIO

ICC

130

170

110

ICCIO

ICC

Operating Current - SMII

ICCIO

ICC

Power-Down Mode

Hardware

ICCIO

ICC

520

800

380

740

570

Auto-Negotiation

100BASE-TX

100BASE-FX

10BASE-T

ICCIO

ICC

835

200

410

200

770

180

ICCIO

ICC

170

150

ICCIO

ICC

Operating Current -

SS-SMII

ICCIO

ICC

Power-Down Mode

Hardware

ICCIO

ICC

530

570

Auto-Negotiation

ICCIO

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Voltages with respect to ground unless otherwise specified.

Table 28. Digital I/O Characteristics (VCCIO = 2.5V +/- 5%)

Parameter

Input Low voltage

Sym

Min

Typ

Max

Units

Test Conditions

VIL

VIH

–

1.75

-100

–

0.75

–

Input High voltage

–

Input current

100

0.2

0.5

–

µA

0.0 < VI < VCC

IOL = 4 mA

IOL = 10 mA

IOH = -4 mA

–

Output Low voltage

VOL

Output Low voltage (LEDm_n pins)

Output High voltage

VOL-LED

VOH

–

2.07

–

Input Low voltage SD pins

Input High voltage SD pins

VIL-SD

VIH-SD

0.755

–

1.58

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Table 29. Digital I/O Characteristics (VCCIO = 3.3V +/- 5%)

Parameter

Input Low voltage

Sym

Min

Typ

Max

Units

Test Conditions

VIL

VIH

–

2.0

-100

–

0.8

–

Input High voltage

–

Input current

100

0.2

0.4

–

µA

0.0 < VI < VCC

IOL = 4 mA

IOL = 10 mA

IOH = -4 mA

–

Output Low voltage

VOL

Output Low voltage (LEDm_n pins)

Output High voltage

VOL-LED

VOH

–

2.4

–

Input Low voltage SD pins

Input High voltage SD pins

VIL-SD

VIH-SD

1.515

–

2.42

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 30. Required Clock Characteristics

Parameter

SMII Input frequency

Sym

Min

Typ

Max

Units

Test Conditions

–

125

–

MHz

ppm

–

RMII Input frequency

–

Input clock frequency tolerance¹

Input clock duty cycle¹

∆f

–

± 50

Tdc

RMII selection

SMII/SS-SMII selection

SS-SMII only

Input clock duty cycle - RefClk,TxCLK¹

Output RxClk duty cycle

1. Parameter is guaranteed by design; not subject to production testing.

2. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 31. 100BASE-TX Transceiver Characteristics

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Peak differential output voltage

Signal amplitude symmetry

Signal rise/fall time

0.95

–

1.05

102

Note 2

Vss

Rise/fall time symmetry

–

0.5

rfs

Offset from 16 ns pulse width at

50% of pulse peak

Duty cycle distortion

Overshoot

–

+/- 0.5

–

Jitter magnitude (measured

differentially)

tx-jit

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Measured at the line side of the transformer, line replaced by 100Ω (+/-1%) resistor.

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 32. 100BASE-FX Transceiver Characteristics

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Transmitter

Peak differential output voltage

(single ended)

VOP

0.6

–

1.44

–

Signal rise/fall time

1.6

1.4

10 to 90%, 2.0 pF load

Jitter magnitude (measured

differentially)

–

tx-jit

Receiver

Peak differential input voltage

Common mode input range

VIP

0.55

–

VCMIR

–

VCC - 0.5

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

Table 33. 10BASE-T Transceiver Characteristics

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Transmitter

Peak differential output voltage

Link transmit period

VOP

2.2

2.5

2.8

Note 2

–

Jitter magnitude added by the

MAU and PLS sections ^{3, 4}

–

tx-jit

Receiver

Receive input impedance³

Link min receive timer

ZIN

–

100

–

Ω

Between TPFIP and TPFIN

TLRmin

TLRmax

VDS

–

Link max receive timer

–

150

–

Differential squelch threshold

475

mV Peak

5 MHz square wave input

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.

2. Parameter is guaranteed by design; not subject to production testing.

3. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU.

4. After line model specified by IEEE 802.3 for 10BASE-T MAU.

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 36. SMII - 100BASE-TX Receive Timing

REFCLK

SYNC

RXD

TPFI

Table 34. SMII - 100BASE-TX Receive Timing Parameters

Parameter

Sym

Min Typ

Max Units

Test Conditions

RXD output delay from REFCLK rising

edge

Minimum CL = 5 pF

Maximum CL = 20 pF

1.5

–

RXD Rise/Fall Time

1.0

–

Synchronous sampling of

SMII

Receive start of /J/ to CRS asserted

–

BT²

Receive start of /T/ to CRS de-

asserted

Synchronous sampling of

SMII

–

BT²

SYNC setup to REFCLK rising edge

SYNC hold from REFCLK rising edge

1.5

1.0

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 37. SMII - 100BASE-TX Transmit Timing

REFCLK

SYNC

TXD

TPFO

Table 35. SMII - 100BASE-TX Transmit Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

SYNC setup to REFCLK rising edge and

TXD setup to REFCLK rising edge

1.5

–

SYNC hold from REFCLK rising edge and

TXD hold from REFCLK rising edge

1.0

–

TXEN sampled to start of /J/

–

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

LXT9785 — Advanced 10/100 8-Port PHY

Figure 38. SMII - 100BASE-FX Receive Timing

REFCLK

SYNC

RXD

TPFI

Table 36. SMII - 100BASE-FX Receive Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

RXD output delay from REFCLK rising

edge

Minimum CL = 5 pF

Maximum CL = 20 pF

1.5

–

RXD Rise/Fall Time

–

Synchronous

sampling of SMII

Receive start of /J/ to CRS asserted

–

BT²

Receive start of /T/ to CRS de-

asserted

Synchronous

sampling of SMII

–

BT²

SYNC setup to REFCLK rising edge

SYNC hold from REFCLK rising edge

1.5

1.0

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

100

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 39. SMII - 100BASE-FX Transmit Timing

REFCLK

SYNC

TXD

TPFO

Table 37. SMII - 100BASE-FX Transmit Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

SYNC setup to REFCLK rising edge and

TXD setup to REFCLK rising edge

1.5

–

SYNC hold from REFCLK rising edge

and TXD hold from REFCLK rising edge

1.0

–

TXEN sampled to start of /J/

–

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

101

LXT9785 — Advanced 10/100 8-Port PHY

Figure 40. SMII - 10BASE-T Receive Timing

REFCLK

SYNC

RXD

TPFI

Table 38. SMII - 10BASE-T Receive Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Minimum CL = 5 pF

RXD output delay from

REFCLK rising edge

1.5

–

Maximum CL = 20 pF

RXD Rise/Fall Time

–

Receive Start-of-Frame to CRS

asserted

–

BT³

Synchronous sampling of SMII²

Receive Start-of-Idle to CRS

de-asserted

–

BT³

Synchronous sampling of SMII²

SYNC setup to REFCLK rising

edge

1.5

1.0

–

SYNC hold from REFCLK rising

edge

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. Assumes each SMII segment is sampled for CRS.

3. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

102

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 41. SMII - 10BASE-T Transmit Timing

REFCLK

SYNC

TXD

TPFO

Table 39. SMII-10BASE-T Transmit Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

SYNC setup to REFCLK rising edge and

TXD setup to REFCLK rising edge

1.5

–

SYNC hold to REFCLK rising edge and

TXD hold from REFCLK rising edge

1.0

–

TXEN sampled to start-of-frame

–

12.5

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

103

LXT9785 — Advanced 10/100 8-Port PHY

Figure 42. Source Synchronous SMII 100BASE-TX Receive Timing

REFCLK

RX_CLK

RX_SYNC

RXD

TPFI

Table 40. Source Synchronous SMII 100BASE-TX Receive Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

REFCLK rising edge to RX_CLK

rising edge

–

1.5

–

RXD/RX_SYNC output delay from

RX_CLK rising edge

Minimum CL = 5 pF

Maximum CL = 40 pF

1.5

–

RXD/RX_SYNC Rise/Fall time

1.0

–

Receive start of /J/ to CRS

asserted

–

BT²

Receive start of /T/ to CRS

deasserted

–

BT²

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

104

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 43. Source Synchronous SMII 100BASE-TX Transmit Timing

TX_CLK

TX_SYNC

TXD

TPFO

Table 41. Source Synchronous SMII 100BASE-TX Transmit Timing

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

SYNC setup to TX_CLK rising edge and

TXD setup to TX_CLK rising edge

1.5

–

SYNC hold from TX_CLK rising edge and

TXD hold to TX_CLK rising edge

1.0

–

TXEN sampled to start of /J/

–

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

105

LXT9785 — Advanced 10/100 8-Port PHY

Figure 44. Source Synchronous SMII - 100BASE-FX Receive Timing

REFCLK

RX_CLK

RX_SYNC

RXD

TPFI

Table 42. Source Synchronous SMII - 100BASE-FX Receive Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

REFCLK rising edge to RxCLK rising edge

–

1.5

–

RXD/RX_SYNC output delay from

RX_CLK rising edge

Minimum CL = 5 pF

Maximum CL = 40 pF

1.5

–

RXD/RX_SYNC Rise/Fall time

–

Receive start of /J/ to CRS asserted

Receive start of /T/ to CRS deasserted

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

106

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 45. Source Synchronous SMII - 100BASE-FX Transmit Timing

TX_CLK

TX_SYNC

TXD

TPFO

Table 43. Source Synchronous SMII - 100BASE-FX Transmit Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

SYNC setup to REFCLK rising edge and

TXD setup to REFCLK rising edge

1.5

–

SYNC hold from REFCLK rising edge and

TXD hold to REFCLK rising edge

1.0

–

TXD to TPFO Latency

–

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

107

LXT9785 — Advanced 10/100 8-Port PHY

Figure 46. Source Synchronous SMII - 10BASE-T Receive Timing

REFCLK

RX_CLK

RX_SYNC

RXD

TPFI

Table 44. Source Synchronous SMII - 10BASE-T Receive Timing Parameters

Parameter

Sym

Min Typ

Max Units

Test Conditions

REFCLK rising edge to RX_CLK rising

edge

–

1.5

–

RXD/RX_SYNC output delay from

RX_CLK rising edge

Minimum CL = 5 pF

Maximum CL = 40 pF

1.5

–

RXD/RX_SYNC Rise/Fall time

–

Synchronous sampling of

SMII²

Receive Start-of-Frame to CRS asserted

–

BT³

Synchronous sampling of

SMII²

Receive Start-of-Idle to CRS de-asserted

–

BT³

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. Assumes each SMII segment is sampled for CRS.

3. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

108

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 47. Source Synchronous SMII - 10BASE-T Transmit Timing

TX_CLK

TX_SYNC

TXD

TPFO

Table 45. Source Synchronous SMII - 10BASE-T Transmit Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

TX_SYNC setup to TX_CLK rising edge and

TXD setup to TX_CLK rising edge

1.5

–

TX_SYNC hold to TX_CLK rising edge and

TXD hold from TX_CLK rising edge

1.0

–

TXD to TPFO Latency

–

12.5

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

109

LXT9785 — Advanced 10/100 8-Port PHY

Figure 48. RMII - 100BASE-TX Receive Timing

REFCLK

RXD(1:0)

TPFI

CRS_DV

Table 46. RMII - 100BASE-TX Receive Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

RXD<1:0>/CRS_DV output delay from REFCLK

rising edge³

–

Receive start of /J/ to CRS_DV asserted

Receive start of /T/ to CRS_DV de-asserted

–

BT²

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

3. Values and conditions from RMII Specification, Rev. 1.2.

110

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 49. RMII - 100BASE-TX Transmit Timing

REFCLK

TXD(1:0)

TPFO

TX_EN

Table 47. RMII - 100BASE-TX Transmit Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

TXD<1:0>/TX_EN setup to REFCLK rising edge

–

TXD<1:0>/TX_EN hold from REFCLK rising

edge

–

TX_EN sampled to TPFO out (Tx latency)

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

111

LXT9785 — Advanced 10/100 8-Port PHY

Figure 50. RMII - 100BASE-FX Receive Timing

REFCLK

RXD(1:0)

TPFI

CRS_DV

Table 48. RMII - 100BASE-FX Receive Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

RXD<1:0>/CRS_DV output delay from REFCLK

rising edge³

–

Receive start of /J/ to CRS_DV asserted

Receive start of /T/ to CRS_DV de-asserted

–

BT²

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

3. Values and conditions from RMII Specification, Rev. 1.2.

112

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 51. RMII - 100BASE-FX Transmit Timing

REFCLK

TXD(1:0)

TPFO

TX_EN

Table 49. RMII - 100BASE-FX Transmit Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

TXD<1:0>/TX_EN setup to REFCLK rising edge

TXD<1:0>/TX-EN hold from REFCLK rising edge

TX_EN sampled to TPFO out (Tx latency)

–

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

113

LXT9785 — Advanced 10/100 8-Port PHY

Figure 52. RMII - 10BASE-T Receive Timing

REFCLK

RXD(1:0)

TPFI

CRS_DV

Table 50. RMII - 10BASE-T Receive Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

RXD<1:0>/CRS_DV output delay from REFCLK

rising edge³

–

TPFI in to CRS_DV asserted

1.5

BT²

–

TPFI quiet to CRS_DV de-asserted

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

3. Values and conditions from RMII Specification, Rev. 1.2.

114

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 53. RMII - 10BASE-T Transmit Timing

REFCLK

TXD(1:0)

TPFO

TX_EN

Table 51. RMII - 10BASE-T Transmit Timing Parameters

Test

Conditions

Parameter

Sym

Min

Typ

Max

Units

TXD<1:0>/TX_EN setup to REFCLK rising edge

–

TXD<1:0>/TX_EN hold from REFCLK rising

edge

–

TX_EN sampled to TPFO out (Tx latency)

8.5

10.5

BT²

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

2. “BT” signifies bit times at the line rate (i.e., BT = 100 ns if using 10BASE-T, BT = 10 ns if using 100BASE-

TX or 100BASE-FX).

Datasheet

115

LXT9785 — Advanced 10/100 8-Port PHY

Figure 54. Auto-Negotiation and Fast Link Pulse Timing

Clock Pulse

Data Pulse

Clock Pulse

TPFOP

Figure 55. Fast Link Pulse Timing

FLP Burst

TPFOP

Table 52. Auto-Negotiation and Fast Link Pulse Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Clock/Data pulse width

Clock pulse to Data pulse

Clock pulse to Clock pulse

FLP burst width

–

55.5

111

–

100

–

69.5

139

–

µs

–

FLP burst to FLP burst

Clock/Data pulses per burst

–

1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production

testing.

116

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 56. MDIO Write Timing (MDIO Sourced by MAC)

MDC

MDIO

Figure 57. MDIO Read Timing (MDIO Sourced by PHY)

MDC

MDIO

Table 53. MDIO Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

MDIO setup before MDC, sourced by

STA

–

MDIO hold after MDC,

sourced by STA

–

MDC to MDIO output delay, sourced

by PHY

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

Datasheet

117

LXT9785 — Advanced 10/100 8-Port PHY

Figure 58. Power-Up Timing

VCC

tPDR

MDIO,etc

Table 54. Power-Up Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Voltage Threshold

2.1

–

Power-Up recovery time

tPDR

100

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

Figure 59. Reset Recovery Timing

tPW

RESET

tRcdly

MDIO,etc

Table 55. Reset Recovery Timing Parameters

Parameter

Sym

Min

Typ

Max

Units

Test Conditions

Reset pulse width

tPW

–

Reset recovery delay

tRcdly

0.4

1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production

testing.

118

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

5.0

The LXT9785 register set includes multiple 16-bit registers, 17 registers per port. Table 56 presents

a complete register listing. Table 57 through Table 72 define individual registers and Table 74

provides a consolidated memory map of all registers.

Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and

Media Independent Interface” and “Physical Layer Link Signalling for 10/100Mbps Auto-

Negotiation” sections of the IEEE 802.3 standard.

Additional registers (16 through 20) are defined in accordance with the IEEE 802.3 standard for

adding unique chip functions.

Table 56. Register Set

Address

Bit Assignments

Control Register

Status Register

Refer to Table 57 on page 120

Refer to Table 58 on page 121

Refer to Table 59 on page 122

Refer to Table 60 on page 122

Refer to Table 61 on page 123

Refer to Table 62 on page 124

Refer to Table 63 on page 125

Refer to Table 64 on page 125

PHY Identification Register 1

PHY Identification Register 2

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Base Page Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Transmit Register

Auto-Negotiation Link Partner Next Page Receive Register Refer to Table 65 on page 126

1000BASE-T/100BASE-T2 Control Register

1000BASE-T/100BASE-T2 Status Register

Extended Status Register

Port Configuration Register

Quick Status Register

Not Implemented

23 - 24

28-31

Not Implemented

Refer to Table 66 on page 127

Refer to Table 67 on page 128

Refer to Table 68 on page 128

Refer to Table 69 on page 130

Refer to Table 70 on page 131

Refer to Table 71 on page 132

Interrupt Enable Register

Interrupt Status Register

LED Configuration Register

Receive Error Count Register

Reserved

RMII Out-of-Band Signalling Register

Reserved

Refer to Table 72 on page 133

Refer to Table 73 on page 133

Trim Enable Register

Reserved

Datasheet

119

LXT9785 — Advanced 10/100 8-Port PHY

Table 57. Control Register (Address 0)

Bit

Name

Description

Type ²

Default

1 = PHY reset

R/W

0.15

Reset

0¹

0 = normal operation

1 = Enable loopback mode

0 = Disable loopback mode

0.14

Loopback

R/W

0.6 0.13

1 = Reserved

0 = 1000Mbps (not allowed)

1 = 100Mbps

0.13⁴Speed Selection

R/W

LHR³

0 = 10Mbps

1 = Enable Auto-Negotiation Process

0 = Disable Auto-Negotiation Process

Auto-Negotiation

Enable

0.12⁴

R/W

LHR³

1 = power-down

0 = normal operation

0.11

0.10

Power-Down

Isolate

R/W

1 = Electrically isolate PHY from RMII or SMII interface

0 = normal operation

Restart

R/W

1 = Restart Auto-Negotiation Process

0 = normal operation

0.9

0¹

Auto-Negotiation

1 = Full Duplex

0 = Half Duplex

0.8⁴

Duplex Mode

Collision Test

R/W

LHR³

This bit is ignored by the LXT9785

0.7

1 = Enable COL signal test

0 = Disable COL signal test

0.6 0.13

1 = Reserved

0 = 1000Mbps (not allowed)

1 = 100Mbps

Speed Selection

1000 Mb/s

0.6

R/W

0 = 10Mbps

0.5:0

Reserved

Write as 0, ignore on Read

00000

1. During a hardware reset, all LHR information is latched in from the pins. During a software reset (0.15), the

LHR information is not re-read from the pins. This information reverts back to the information that was read

in during the hardware reset. During a hardware rest, register information is unavailable from 1 ms after de-

assertion of the reset. During a software reset (0.15) the registers are available for reading. The reset bit

should be polled to see when the part has completed reset.

2. R/W = Read/Write, RO = Read Only, SC = Self Clearing when read.

3. LHR = Latched on Hardware Reset. Bits 0.12, 0.13, and 0.8 are initialized based on the pin configuration

value.

4. Default value of bits 0.12, 0.13, and 0.8 are determined by hardware pins.

120

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 58. Status Register (Address 1)

Bit

Name

Description

Type ¹

Default

1 = PHY able to perform 100BASE-T4

0 = PHY not able to perform 100BASE-T4

1.15 100BASE-T4

100BASE-X Full

Duplex

1 = PHY able to perform full-duplex 100BASE-X

0 = PHY not able to perform full-duplex 100BASE-X

1.14

100BASE-X Half

Duplex

1 = PHY able to perform half-duplex 100BASE-X

0 = PHY not able to perform half-duplex 100BASE-X

1.13

1 = PHY able to operate at 10Mbps in full-duplex mode

0 = PHY not able to operate at 10Mbps full-duplex

mode

1.12 10Mbps Full Duplex

1.11 10Mbps Half Duplex

1 = PHY able to operate at 10Mbps in half-duplex mode

0 = PHY not able to operate at 10Mbps in half-duplex

100BASE-T2 Full

Duplex

1 = PHY able to perform full-duplex 100BASE-T2

0 = PHY not able to perform full-duplex 100BASE-T2

1.10

100BASE-T2 Half

Duplex

1 = PHY able to perform half duplex 100BASE-T2

0 = PHY not able to perform half-duplex 100BASE-T2

1.9

1 = Extended status information in register 15

0 = No extended status information in register 15

1.8

1.7

Extended Status

Reserved

1 = Ignore on read

1 = PHY accepts management frames with preamble

suppressed

0 = PHY will not accept management frames with

preamble suppressed

MF Preamble

Suppression

1.6

Auto-Negotiation

complete

1 = Auto-negotiation complete

0 = Auto-negotiation not complete

1.5

1.4

1.3

1.2

RO/LH

Note 2

1 = Remote fault condition detected

0 = No remote fault condition detected

Remote Fault

Auto-Negotiation

Ability

1 = PHY is able to perform Auto-Negotiation

0 = PHY is not able to perform Auto-Negotiation

RO/LL

Note 2

1 = Link is up

0 = Link is down

Link Status

RO/LH

Note 2

1 = Jabber condition detected

0 = Jabber condition not detected

1.1

1.0

Jabber Detect

1 = Extended register capabilities

0 = Basic register capabilities

Extended Capability

1. RO = Read Only

2. Bits that Latch High (LH) or Latch Low (LL) automatically clear when read.

Datasheet

121

LXT9785 — Advanced 10/100 8-Port PHY

Table 59. PHY Identification Register 1 (Address 2)

Bit

Name

Description

Type ¹

Default

The PHY identifier composed of bits 3 through 18 of the

OUI

2.15:0 PHY ID Number

1. RO = Read Only

0013 hex

Table 60. PHY Identification Register 2 (Address 3)

Bit

Name

Description

Type ¹

Default

011110

001111

XXXX

The PHY identifier composed of bits 19

through 24 of the OUI

3.15:10 PHY ID Number

Manufacturer’s

3.9:4

6 bits containing manufacturer’s part number

Model Number

Manufacturer’s

Revision

Number

4 bits containing manufacturer’s revision

(See Table 3 in

Specification

Update)

3.3:0

number

1. RO = Read Only

Figure 60. PHY Identifier Bit Mapping

Organizationally Unique Identifier

18 19

I/G

PHY ID Register #1 (Address 2)

PHY ID Register #2 (Address 3)

Manufacturer’s

Model Number

Revision

Number

The Level One OUI is 00207B hex.

122

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 61. Auto-Negotiation Advertisement Register (Address 4)⁴

Bit

Name

Description

Type ¹

Default

1 = Port has ability to send multiple pages

0 = Port has no ability to send multiple pages

4.15

4.14

4.13

4.12

4.11

Reserved

R/W

Ignore on read

1 = Remote fault

0 = No remote fault

Remote Fault

Reserved

R/W

Ignore

Asymmetric

Pause

Pause operation defined in Clause 40 and 27

1 = Pause operation enabled for full-duplex links

0 = Pause operation disabled

Note 2 &

Note 3

4.10

Pause

R/W

1 = 100BASE-T4 capability is available

0 = 100BASE-T4 capability is not available

(The LXT9785 does not support 100BASE-T4 but allows this

bit to be set to advertise in the Auto-Negotiation sequence for

100BASE-T4 operation. An external 100BASE-T4 transceiver

could be switched in if this capability is desired.)

4.9

100BASE-T4

R/W

100BASE-TX 1 = Port is 100BASE-TX full duplex capable

4.8

4.7

R/W

Note 3

full duplex

0 = Port is not 100BASE-TX full duplex capable.

1 = Port is 100BASE-TX capable

0 = Port is not 100BASE-TX capable

100BASE-TX

1 = Port is 10BASE-T full duplex capable

0 = Port is not 10BASE-T full duplex capable

10BASE-T

full duplex

4.6

4.5

R/W

Note 3

1 = Port is 10BASE-T capable

10BASE-T

0 = Port is not 10BASE-T capable

<00001> = IEEE 802.3

<00010> = IEEE 802.9 ISLAN-16T

Selector

4.4:0 Field,

S<4:0>

<00000> = Reserved for future Auto-Negotiation development

<11111> = Reserved for future Auto-Negotiation development

Unspecified or reserved combinations should not be

transmitted

R/W

00001

1. R/W = Read/Write, RO = Read Only

2. The default setting of bit 4.10 (PAUSE) is determined by pin 50. Pause operation is only valid for full-duplex

modes.

3. Default settings for bits 4.5:8 are determined by CFG pins as described in Table 18 on page 62.

^{4. Restart Auto-Negotiation process whenever Reg 4. is written/modified}.

Datasheet

123

LXT9785 — Advanced 10/100 8-Port PHY

Table 62. Auto-Negotiation Link Partner Base Page Ability Register (Address 5)

Bit

Name

Description

Type ¹

Default

1 = Link Partner has ability to send multiple pages

0 = Link Partner has no ability to send multiple pages

5.15 Next Page

1 = Link Partner has received Link Code Word from the

LXT9785.

5.14 Acknowledge

0 = Link Partner has not received Link Code Word from the

the LXT9785

1 = Remote fault

0 = No remote fault

5.13 Remote Fault

5.12 Reserved

Ignore on read

Pause operation defined in Clause 40 and 27

Asymmetric

Pause

5.11

1 = Link Partner is Pause capable

0 = Link Partner is not Pause capable

1 = Link Partner is Pause capable

0 = Link Partner is not Pause capable

5.10 Pause

1 = Link Partner is 100BASE-T4 capable

0 = Link Partner is not 100BASE-T4 capable

5.9

5.8

5.7

100BASE-T4

100BASE-TX

full duplex

1 = Link Partner is 100BASE-TX full duplex capable

0 = Link Partner is not 100BASE-TX full duplex capable

1 = Link Partner is 100BASE-TX capable

0 = Link Partner is not 100BASE-TX capable

100BASE-TX

10BASE-T

full duplex

1 = Link Partner is 10BASE-T full duplex capable

0 = Link Partner is not 10BASE-T full duplex capable

5.6

5.5

1 = Link Partner is 10BASE-T capable

0 = Link Partner is not 10BASE-T capable

10BASE-T

<00001> = IEEE 802.3

<00010> = IEEE 802.9 ISLAN-16T

Selector Field

S<4:0>

5.4:0

<00000> = Reserved for future Auto-Negotiation development

<11111> = Reserved for future Auto-Negotiation development

Unspecified or reserved combinations shall not be transmitted

00000

1. RO = Read Only

124

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 63. Auto-Negotiation Expansion (Address 6)

Bit

Name

Description

Type ¹

Default

6.15:6 Reserved

Ignore on read

This bit indicates the status of the Auto-Negotiation

variable, base page. It flags synchronization with the Auto-

Negotiation state diagram allowing detection of interrupted

links. This bit is only used if bit 16.1 (Alternate NP feature)

is set.

RO/

6.5

Base Page

Parallel

1 = base_page = true

0 = base_page = false

1 = Parallel detection fault has occurred.

Detection Fault 0 = Parallel detection fault has not occurred.

RO/

6.4

6.3

6.2

Link Partner 1 = Link partner is next page able

Next Page Able 0 = Link partner is not next page able

1 = Local device is next page able

Next Page Able

0 = Local device is not next page able

Indicates that a new page has been received and the

received code word has been loaded into register 5 or

6.1

Page Received 1 = Three identical and consecutive link code words have

been received from link partner

0 = Three identical and consecutive link code words have

not been received from link partner

Link Partner A/ 1 = Link partner is auto-negotiation able

6.0

N Able

0 = Link partner is not auto-negotiation able

1. RO = Read Only, LH = Latching High cleared when read

Table 64. Auto-Negotiation Next Page Transmit Register (Address 7)

Bit

Name

Description

Type ¹

Default

(NP)

1 = Additional next pages follow

0 = Last page

7.15

R/W

7.14 Reserved

Write as 0, ignore on read

Message Page 1 = Message page

7.13

7.12

R/W

(MP)

0 = Unformatted page

Acknowledge 2 1 = Complies with message

R/W

(ACK2)

0 = Cannot comply with message

1 = Previous value of the transmitted Link Code Word

equalled logic zero

0 = Previous value of the transmitted Link Code Word

equalled logic one

Toggle

(T)

7.11

Message/

7.10:0 Unformatted

Code Field

MP = 1: Code interpreted as “message page”

MP = 0: Code interpreted as “unformatted page”

R/W

00000000001

1. R/W = Read Write, RO = Read Only

Datasheet

125

Advanced 10/100 8-Port PHY — LXT9785

Table 65. Auto-Negotiation Link Partner Next Page Receive Register (Address 8)

Bit

Name

Description

Type ¹

Default

(NP)

1 = Link Partner has additional next pages to send

0 = Link Partner has no additional next pages to send

8.15

1 = Link Partner has received Link Code Word from

the LXT9785

Acknowledge

(ACK)

8.14

0 = Link Partner has not received Link Code Word

from the LXT9785

1 = Page sent by the Link Partner is a Message Page

Message Page

(MP)

8.13

8.12

0 = Page sent by the Link Partner is an Unformatted

Page

Acknowledge 2

(ACK2)

1 = Link Partner will comply with the message

0 = Link Partner cannot comply with the message

1 = Previous value of the transmitted Link Code Word

equalled logic zero

0 = Previous value of the transmitted Link Code Word

equalled logic one

Toggle

(T)

8.11

Message/

8.10:0 Unformatted

Code Field

MP = 1: Code interpreted as “message page”

MP = 0: Code interpreted as “unformatted page”

00000000000

1. RO = Read Only

Product Specification

126

Advanced 10/100 8-Port PHY — LXT9785

Table 66. Port Configuration Register (Address 16, Hex 10)

Bit

Name

Reserved

Description

Write as 0, ignore on read

Type ¹

Default

16.15

R/W

1 = Force Link pass. Sets appropriate registers and LEDs

to Pass.

16.14

Link Disable

R/W

0 = Normal operation

1 = Disable Twisted-Pair transmitter

0 = Normal Operation

16.13

16.12

16.11

16.10

Transmit Disable

R/W

Bypass Scramble 1 = Bypass Scrambler and Descrambler

(100BASE-TX)

0 = Normal Operation

Bypass 4B5B

(100BASE-TX)

1 = Bypass 4B5B encoder and decoder

0 = Normal Operation

Jabber

(10BASE-T)

1 = Disable Jabber

0 = Normal operation

This bit is ignored by the LXT9785

SQE

(10BASE-T)

16.9

R/W

1 = Enable Heart Beat

0 = Disable Heart Beat

TP Loopback

(10BASE-T)

1 = Disable TP loopback during half duplex operation

0 = Normal Operation

16.8

16.7

R/W

Reserved

Write as one. Ignore on read

0 = FIFO allows packets up to 2 KBytes

1 = FIFO allows packets up to 9 KBytes

16.6

16.5

FIFO Size

R/W

Packet sizes assume a 100 ppm difference between the

reference clock and the recovered clock.

Preamble Enable. The implementation of this bit is

10BASE-T only.

PRE_EN

0 = Set RX_DV high coincident with SFD

1 = Set RX_DV high and RXD=preamble when CRS is

asserted.

16.4

16.3

Reserved

Write as zero. Ignore on read

R/W

Far End Fault

Transmission

Enable

1 = Enable Far End Fault Transmission

0 = Disable Far End Fault Transmission

16.2

R/W

Alternate NP

Feature

1 = Enable alternate auto-negotiate next page feature

0 = Disable alternate auto-negotiate next page feature

16.1

16.0

R/W

1 = Select fiber mode for this port

0 = Select TP mode for this port

Note 2

Fiber Select

1. R/W = Read/Write

2. The default value of bit 16.0 is determined by the G_FX/TP pin for the respective port.

If G_FX/TPn is tied Low, the default value of bit 16.0 = 0. If G_FX/TPn is not tied Low, the default value of

bit 16.0 = 1.

Datasheet

127

Table 67. Quick Status Register (Address 17, Hex 11)

Bit

Name

Description

Type ¹

Default

17.15 Reserved

Always 0

1 = The LXT9785 is operating in 100BASE-TX mode.

0 = The LXT9785 is not operating 100BASE-TX mode.

17.14 10/100 Mode

1 = The LXT9785 is transmitting a packet

0 = The LXT9785 is not transmitting a packet

17.13 Transmit Status

17.12 Receive Status

17.11 Collision Status

17.10 Link

1 = The LXT9785 is receiving a packet

0 = The LXT9785 is not receiving a packet

1 = Collision is occurring

0 = No collision

1 = Link is up

0 = Link is down

1 = Full duplex

0 = Half duplex

17.9

17.8

Duplex Mode

1 = The LXT9785 is in Auto-Negotiation Mode

0 = The LXT9785 is in manual mode

Auto-Negotiation

1 = Auto-negotiation process completed

0 = Auto-negotiation process not completed

Auto-Negotiation

Complete

17.7

17.6

This bit is only valid when auto-negotiate is enabled, and is

equivalent to bit 1.5.

1 = FIFO error has occurred (Overflow or Underflow)

0 = No FIFO error has occurred

FIFO Error

1 = Polarity is reversed

0 = Polarity is not reversed

17.5

17.4

Polarity

Pause

1 = The LXT9785 is Pause capable

0 = The LXT9785 is Not Pause capable

1 = Error Occurred (Remote Fault, RxERCntFUL, FIFO

error, Jabber, Parallel Detect Fault)

0 = No error occurred

17:3

Error

17:2

17:1

17.0

Reserved

Ignore

Always 0

1. RO = Read Only, LH = Latching High cleared when read.

Table 68. Interrupt Enable Register (Address 18, Hex 12)

Bit

Name

Description

Write as 0, ignore on read

Type ¹

Default

18.15:9 Reserved

R/W

Mask for Counter Full

18.8

18.7

CNTRMSK

ANMSK

R/W

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Auto-Negotiate Complete

R/W

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

1. R/W = Read/Write

Advanced 10/100 8-Port PHY — LXT9785

Table 68. Interrupt Enable Register (Address 18, Hex 12) (Continued)

Bit

Name

Description

Type ¹

Default

Mask for Speed Interrupt

18.6

SPEEDMSK

R/W

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Duplex Interrupt

18.5

18.4

18.3

DUPLEXMSK

LINKMSK

R/W

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Link Status Interrupt

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

Mask for Isolate Interrupt

ISOLMSK

1 = Enable event to cause interrupt

0 = Do not allow event to cause interrupt

18.2

18.1

Reserved

INTEN

Write as 0, ignore on read

R/W

1 = Enable interrupts on this port

0 = Disable interrupts on this port

1 = Test Force interrupt on MDINT

0 = Normal operation

18.0

TINT

R/W

1. R/W = Read/Write

Datasheet

129

LXT9785 — Advanced 10/100 8-Port PHY

Table 69. Interrupt Status Register (Address 19, Hex 13)

Bit

Name

Description

Type ¹

Default

19.15:9 Reserved

Ignore on read

RxER Counter Full Status

N/A

1 = One of the internal counters has reached its maximum

value

0 = The internal counters have not reached maximum values

19.8

19.7

RxERCntFUL

RO/SC

Auto-Negotiation Status

ANDONE

1= Auto-Negotiation has completed

0= Auto-Negotiation has not completed

Speed Change Status

1 = A Speed Change has occurred since last reading this

19.6

19.5

19.4

SPEEDCHG

RO/SC

0 = A Speed Change has not occurred since last reading this

Duplex Change Status

1 = A Duplex Change has occurred since last reading this

DUPLEXCHG register

0 = A Duplex Change has not occurred since last reading

this register

Link Status Change Status

1 = A Link Change has occurred since last reading this

LINKCHG

0 = A Link Change has not occurred since last reading this

MII Isolate Change Status

1 = A Isolate change has occurred since last reading this

19.3

19.2

Isolate

MDINT

RO/SC

0 = A Isolate change has not occurred since last reading this

1 = RMII/SMII/SS-SMII interrupt pending

0 = No RMII/SMII/SS-SMII interrupt pending

19.1

19.0

Reserved

Ignore on read

RO/SC

1. R/W = Read/Write, RO = Read Only, SC = Self Clearing - cleared when read

130

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 70. LED Configuration Register (Address 20, Hex 14)

Bit

Name

Description

Type ¹Default

0000 = Display Speed Status (Continuous, Default)

0001 = Display Transmit Status (Stretched)

0010 = Display Receive Status (Stretched)

0011 = Display Collision Status (Stretched)

0100 = Display Link Status (Continuous)

0101 = Display Duplex Status (Continuous)

0110 = Display Isolate Status (Continuous)

0111 = Display Receive or Transmit Activity (Stretched)

1000 = Test mode- turn LED on (Continuous)

1001 = Test mode- turn LED off (Continuous)

1010 = Test mode- blink LED fast (Continuous)

1011 = Test mode- blink LED slow (Continuous)

1100 = Display Link and Receive Status combined ²

(Stretched)³

LED1

20.15:12

R/W

0000

Programming

bits

1101 = Display Link and Activity Status combined ²

(Stretched)³

1110 = Display Duplex and Collision Status combined ⁴

(Stretched)³

1111 = Display Link and Rx_ERR Status combined ²(Blink)

0000 = Display Speed Status

0001 = Display Transmit Status

0010 = Display Receive Status

0011 = Display Collision Status

0100 = Display Link Status

0101 = Display Duplex Status

0110 = Display Isolate Status

0111 = Display Receive or Transmit Activity

1000 = Test mode- turn LED on

1001 = Test mode- turn LED off

1010 = Test mode- blink LED fast

1011 = Test mode- blink LED slow

1100 = Display Link and Receive Status combined ²

(Stretched)³

LED2

20.11:8

R/W

1101

Programming

bits

1101 = Display Link and Activity Status combined ²

(Default)(Stretched)³

1110 = Display Duplex and Collision Status combined ⁴

(Stretched)³

1111 = Display Link and Rx_ERR Status combined ²(Blink)

1. R/W = Read/Write, RO = Read Only, LH = Latching High.

2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).

3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are

stretched regardless of the value of 20.1.

4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

Datasheet

131

LXT9785 — Advanced 10/100 8-Port PHY

Table 70. LED Configuration Register (Address 20, Hex 14) (Continued)

Bit

Name

Description

Type ¹Default

0000 = Display Speed Status

0001 = Display Transmit Status

0010 = Display Receive Status

0011 = Display Collision Status

0100 = Display Link Status

0101 = Display Duplex Status

0110 = Display Isolate Status

0111 = Display Receive or Transmit Activity

1000 = Test mode- turn LED on

1001 = Test mode- turn LED off

1010 = Test mode- blink LED fast

1011 = Test mode- blink LED slow

1100 = Display Link and Receive Status combined ²

(Stretched)³

LED3

20.7:4

R/W

1110

Programming

bits

1101 = Display Link and Activity Status combined ²

(Stretched)³

1110 = Display Duplex and Collision Status combined ⁴

(Default) (Blink)³

1111 = Display Link and Rx_ERR Status combined ²(Blink)

00 = Stretch LED events to 30 ms

01 = Stretch LED events to 60 ms

10 = Stretch LED events to 100 ms

11 = Reserved

20.3:2

LEDFREQ

R/W

PULSE-

STRETCH

1 = Enable pulse stretching of all LEDs

0 = Disable pulse stretching of all LEDs ²

20.1

20.0

R/W

Reserved

1. R/W = Read/Write, RO = Read Only, LH = Latching High.

2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up.

The secondary LED driver (Receive, Activity, or Error) causes the LED to change state (blink).

3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are

stretched regardless of the value of 20.1.

4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex.

Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs.

Table 71. Receive Error Count Register (Address 21)

Bit

Name

Description

Type ¹

Default

A 16-bit counter value indicating the number of times a

receive packet with errors occurred. Only one event gets

Receive Error counted per packet. When maximum count is reached, the

RO/

21.15:0

Count

16-bit counter remains full until cleared. Refer to the

discussion of “Out-of-Band Signalling” on page 74 for

details.

1. RO = Read Only

S/C = Self Clearing when read

132

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Table 72. RMII Out-of-Band Signalling Register (Address 25)

Bit

Name

Description

Type ¹

Default

25:15:7 Reserved

Reserved

R/W

These three bits select which status information is

available on the RXD(1) bit of the RMII bus.

000 = Link

001 = Speed

010 = Duplex

25:6:4

BIT1

R/W

000

011 = Auto-negotiation complete

100 = Polarity reversed

101 = Jabber detected

110 = Interrupt pending

111 = Isolate

These three bits select which status information is

available on the RXD(0) bit of the RMII bus.

000 = Link

001 = Speed

010 = Duplex

25.3:1

BIT0

R/W

000

011 = Auto-negotiation complete

100 = Polarity reversed

101 = Jabber detected

110 = Interrupt pending

111 = Isolate

1 = Enable programmable RMII Out-of-Band

signalling. When enabled, bits 6:1 specify which

status bits are available on the RMII RXD data bus.

25.0

PROGRMII

R/W

0 = Disable Out-of-Band signalling.

1. R/W = Read/Write

RO = Read Only

Table 73. Trim Enable Register (Address 27)

00 = 3.3 ns (default is pins SLEWCTRL<1:0>

Per-Port

27.11:10 Rise Time

Control

01 = 3.6 ns

10 = 3.9 ns

11 = 4.2 ns

R/W

0 = Disable auto MDIX (default is pin auto_mdix_en)

1 = Enable auto MDIX

27.9

27.8

27.7

AMDIX_EN

MDIX

R/W

Note 2

Manual MDI/MDIX selection:

0 = MDI, transmit on pair A and receive on pair B

1 = MDIX transmit on pair B and receive on pair A

1 = Enable analog loop back (transmits on twisted-pair)

0 = Disable analog loop back

Analog

Loop back

1. The default setting of register bit 27.8 is determined by pin 59.

Datasheet

133

Table 74. Register Bit Map

Bit Fields

Reg Title

Addr

B15

B14

B13

B12

B11

B10

Control Register

Speed

Select

A/N

Power

Down

Re-start

A/N

Duplex

Mode

Speed

Select

Reset

Loopback

Isolate

COL Test

Reserved

Control

Status

Enable

Status Register

100Base-

X Full

Duplex

10Mbps

Full

Duplex

10Mbps

Half

Duplex

100Base-

T2 Full

Duplex

Preamble

Suppress

Extended

Capability

100Base-X

Half Duplex

100Base-T2

Half Duplex

Extended

Status

A/N

Complete

Remote

Fault

Jabber

Detect

100Base-T4

Reserved

A/N Ability

Link Status

PHY ID Registers

PHY ID 1

PHY ID2

PHY ID No

MFR Model No

MFR Rev No

Auto-Negotiation Advertisement Register

100Base-

TX Full

Duplex

A/N

Advertise

Remote

Fault

Asymm

Pause

100Base-

10Base-T

Full Duplex

Reserved

Pause

100Base-T4

10Base-T

IEEE Selector Field

Auto-Negotiation Link Partner Base Page Ability Register

100Base-

TX Full

Duplex

A/N Link

Ability

Remote

Fault

Asymm

Pause

100Base-

10Base-T

Full Duplex

Ack

Pause

100Base-T4

10Base-T

IEEE Selector Field

Auto-Negotiation Expansion Register

Parallel

Detect

Fault

LinkPartner

Able

Link

Partner

A/N Able

A/N

Expansion

Able

Page

Received

Reserved

Base Page

Auto-Negotiation Next Page Transmit Register

A/N Next

Page

Txmit

Message

Page

Reserved

Ack 2

Toggle

Message / Unformatted Code Field

Auto-Negotiation Link Partner Next Page Ability Register

A/N Link

Ack

Message Page

Ack 2

Toggle

Message / Unformatted Code Field

Table 74. Register Bit Map (Continued)

Bit Fields

B8 B7

Reg Title

Addr

B15

B14

B13

B12

B11

B10

Port Configuration Register

Bypass

Scrambler

Bypass

4B/5B

Loopback

Remote

Fault

Enable

Port

Config

Jabber

(10T)

SQE

Link

Disable

Txmit

Disable

Alternate

Fiber

Select

Reserved

FIFO Size

PRE_EN

Reserved

(10T)

(100TX)

(10T)

Quick Status Register

Quick

Status

10/100

Mode

Transmit

Status

Receiver

Status

Collision

Status

Duplex

Mode

Auto-Neg

Complete

Reserved

Link

Auto-Neg

FIFO Error

Polarity

Pause

Error

Reserved

Interrupt Enable Register

Interrupt

Enable

Counter

Mask

Auto-Neg

Mask

Speed

Mask

Duplex

Mask

Isolate

Mask

Interrupt

Enable

Test

Interrupt

Reserved

Link Mask

Interrupt Status Register

Rx_ER

Auto-Neg

Counter

Done

Interrupt

Status

Speed

Change

Duplex

Change

Link

Change

Isolate

Change

MD Interrupt

Reserved

Full

LED Configuration Register

LED

Config

Pulse

Stretch

LED1

LED2

LED3

LED Freq

Receive Error Count Register

Rcv Error

Count

Receive Error Count

False Carrier Counter Register

Reserved

Programmable RMII Out-of-Band Signalling Register

RMII OOB

Signalling

Program

RMII

Reserved

Bit 1

Bit 0

Programmable RMII Out-of-Band Signalling Register

Per Port Slew

Control

Auto-MDIX

Manual

MDIX

Analog

Loop

Trim

Enable

Reserved

LXT9785 — Advanced 10/100 8-Port PHY

6.0

Package Specifications

Figure 61. LXT9785 208-Pin PQFP Plastic Package Specification

208-Pin Plastic Quad Flat Package

• Part Number LXT9785HC

• Commercial Temperature Range (0°C to 70°C)

Millimeters

Max

Dim

Min

D₁

4.10

0.25

3.20

3.60

0.27

30.90

28.30

30.90

28.30

0.17

E₁

30.30

27.70

30.30

27.70

.50 BASIC

0.50

0.75

θ₂

1.30 REF

L₁

0°

5°

7°

A₂

16°

A₁

θ₃

136

Datasheet

Advanced 10/100 8-Port PHY — LXT9785

Figure 62. LXT9785 241-Ball PBGA Package Specification (LXT9785BC)

Datasheet

137

LXT9785BC [ETC]

相关型号：

LXT9785HC

LXT980AHC

LXT980QC

LXT981QC

LXT981QC

LXT983AHC

LXT983AHC

LXT983QC

LXT9860

LXT9860AHC

LXT9860HC

LXT9863