M21L216128A-15T [ETC]
128 K x 16 SRAM HIGH SPEED CMOS SRAM; 128千×16的SRAM高速CMOS SRAM
| 型号： | M21L216128A-15T |
| 厂家： | 
ETC |
| 描述： | 128 K x 16 SRAM HIGH SPEED CMOS SRAM |
| 文件： | 总14页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M21L216128A
128 K x 16 SRAM
SRAM
HIGH SPEED CMOS SRAM
FEATURES
ORDERING INFORMATION
Fast access times : 10, 12, and 15ns
44-pin 400mil SOJ
Fast OE access times : 5, 6, and 7ns
Single +3.3V ± 0.3V power supply
44-pin 400mil TSOP (TypeII)
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Acess Time
PACKING
TYPE
PRODUCT NO.
(ns)
Center power and ground pins for greater noise immunity
M21L216128A-10J
10
SOJ
Easy memory expansive with CE and OE options
Automatic CE power down
M21L216128A-10T
TSOP
SOJ
M21L216128A-12J
12
M21L216128A-12T
TSOP
SOJ
M21L216128A-15J
15
M21L216128A-15T
TSOP
GENERAL DESCRIPTION
The M21L216128A is
a
high speed, low power
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
asynchronous SRAM containing 2,097,152 bits and
organized as 131,072 by 16 bits, it is produced by high
performance CMOS process.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
problems, this device offers chip enable ( CE ), separate byte
LB
HE
) and output enable ( OE ) with this
enable controls (
organization.
and
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
A5
A4
A3
A5
A4
A3
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
1
2
3
4
5
6
7
8
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
1
2
3
4
5
6
7
8
A6
A6
A7
A2
A7
A2
O E
A1
A1
OE
H B
A0
A0
HB
LB
C E
CE
LB
D Q 1 6
D Q 1 5
D Q 1 4
D Q 1 3
G N D
D Q 1
D Q 2
D Q 3
D Q 4
V C C
DQ1
DQ2
DQ3
DQ16
DQ15
DQ14
DQ13
GND
VC C
DQ12
DQ11
DQ10
DQ9
N C
9
1 0
1 1
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
DQ4
VCC
G ND
DQ5
DQ6
DQ7
DQ8
W E
V C C
D Q 1 2
D Q 1 1
D Q 1 0
D Q 9
N C
G N D
D Q 5
D Q 6
D Q 7
D Q 8
W E
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
A1 6
A1 5
A1 4
A1 3
A1 2
A8
A8
A16
A9
A9
A15
A1 0
A1 1
N C
A10
A11
N C
A14
A13
A12
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 1/14
M21L216128A
Block Diagram
512
X 4096
MEMORY ARRAY
DQ9
Pin Descriptions
Pin No.
Symbol
A0 - A16
CE
Description
1 - 5, 18 - 22,
24-27, 42 - 44
Address Inputs
6
Chip Enable Input
7 - 10, 13 - 16,
29 - 32, 35 - 38
DQ1 - DQ16
Data Inputs/Outputs
17
39
40
Write Enable Input
WE
LB
Lower Byte Enable Input (DQ1 to DQ8)
Higher Byte Enable Input (DQ9 to
DQ16)
HB
41
Output Enable Input
OE
VCC
GND
NC
11, 33
12, 34
23, 28
Power
Ground
No Connection
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
2/14
M21L216128A
ABSOLUTE MAXIMUM RATINGS *
CC
*Stresses greater than those listed under Absolute
Maximum. Ratings may permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Voltage on V Supply Relative to Vss … ……-0.5V to +4.6V
IN
V
CC
…………………………………………..….-0.5V to V +1.0V
Operating Temperature, Topr ………………….. 0 ° to +70°
C
C
Storage Temperature (plastic) ……………….-55 ° to +125°
C
C
Junction Temperature ……………………………………+125°
C
Power Dissipation …..…………………………………….…1.0W
Short Circuit Output Current ………………………………50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS
CC
(All Temperature Ranges ; V = 3.3V ± 0.3V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
CONDITIONS
SYMBOL
MIN
2.2
MAX
UNITS NOTES
IH
V
CC
+0.5
V
V
V
1,2
1,2
II
V
-0.5
-10
0.8
µ A
0V ≤ VIN ≤ VCC
Output(s) disable
0V ≤ VOUT ≤ VCC
I
10
5
LI
Output Leakage Current
µ A
LO
I
-5
Output High Voltage
Output Low Voltage
Supply Voltage
OH
OH
I
I
= -4.0 mA
= 8.0 mA
V
V
V
2.4
V
V
V
1
1
OL
OL
CC
0.4
3.6
1
3.0
MAX
DESCRIPTION
CONDITIONS
SYMBOL
UNITS NOTES
-10 -12 -15
Power Supply
IL
CC
Device selected; CE ≤ V ; V =MAX;
CC
I
190 160 130
mA
mA
3
Current : Operating
MAX
f=f
; outputs open
SB1
TTL Standby
I
IH
CC
MAX
CE ≥ V ; V =MAX; f=f
35
10
30
10
25
10
CC
CC
CE1 ≥ V -0.2; V = MAX;
SB2
CMOS Standby
I
mA
CC -
all other inputs≤ GND +0.2 or ≥ V 0.2;
all inputs static ; f=0
CAPACITANCE
DESCRIPTION
Input Capacitance
CONDITIONS
SYMBOL MAX
UNITS NOTES
I
C
6
8
pF
pF
4
4
A
T =
; f=1 MHz
25°C
Input/Output Capacitance(DQ)
I/O
C
CC
V
=3.3V
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 3/14
M21L216128A
AC ELECTRICAL CHARACTERISTICS
CC
(Note 5)(All Temperature Ranges; V =3.3V ± 0.3V)
Notes
-10
-12
-15
DESCRIPTION
Read Cycle
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
RC
Read Cycle Time
t
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
Access access time
t
10
10
12
12
15
15
ACE
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low-Z
Output Disable to output in High-Z
Byte Enable access time
Byte Enable to output in Low-Z
Byte disable to output in High-Z
Write Cycle
t
OH
t
3
3
4
4
4
4
CLZ
t
4,7
CHZ
t
5
5
6
6
7
7
4,6,7
OE
t
OLZ
t
0
0
0
0
0
0
OHZ
t
5
6
6
7
7
8
4,6
BE
t
BLZ
t
4,7
BHZ
t
5
6
7
4,6,7
WC
Write cycle time
t
10
8
12
8
15
9
ns
ns
CW
Chip Enable to end of write
t
Address valid to end of write, with
OE HIGH
AW
t
8
8
9
ns
AS
Address setup time
t
0
0
0
0
0
0
ns
ns
ns
WR
Address hold from end of write
Write pulse width
t
WP2
t
10
10
11
WP1
t
8
8
9
ns
Write pulse width, with OE HIGH
Data setup time
DW
t
5
0
3
6
0
4
7
0
5
ns
ns
ns
ns
ns
DH
Data hold time
t
OW
Write disable to output in Low-Z
Byte Enable to output in High-Z
Byte Enable to end of write
t
4,7
WHZ
t
5
6
7
4,6,7
BW
t
8
8
9
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 4/14
M21L216128A
TRUTH TABLE
MODE
DQ1-DQ8
DQ9-DQ16
POWER
OE
L
CE
L
WE
H
H
H
L
LE
L
HE
H
L
LOW BYTE READ (DQ1-DQ8)
HIGH BYTE READ (DQ9-DQ16)
WORD READ (DQ1-DQ16)
Q
HIGH-Z
Q
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
STANBY
L
L
H
L
HIGH-Z
Q
L
L
L
Q
LOW BYTE WRITE (DQ1-DQ8)
HIGH BYTE WRITE (DQ9-DQ16)
WORD WRITE (DQ1-DQ16)
L
X
X
X
X
H
X
L
H
L
D
HIGH-Z
D
L
L
H
L
HIGH-Z
D
L
L
L
D
L
X
H
X
X
H
X
X
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
OUTPUT DISABLE
STANDBY
L
H
X
H
AC TEST CONDITIONS
Input plus levels
0V to 3.0V
1.5ns
Input rise and fail times
Input timing reference levels
Output reference levels
Output load
1.5V
1.5V
See Figures 1 and 2
3.3V
317
DQ
Z0 =50
DQ
5pF
30pF
50
351
Vt=1.5V
Fig.1 OUTPUT LOAD EQUIVALENT
Fig.2 OUTPUT LOAD EQUIVALENT
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 5/14
M21L216128A
NOTES
1. All voltages referenced to GND (VSS).
IH
≤
≤
RC
2. Overshoot : V
+6.0V for t
t
/2.
/2.
IL
≤
≤
RC
Undershoot : V
-2.0V for t
t
CC
3.
I
is given without output current. ICC increases with greater output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted.
6. Output loading is specified with CL=5pF as in Fig.2. Transition is measured± 500mV from steady static voltage.
CHZ
CLZ
WHZ
OW
7. At any give temperature and voltage conditions, t
is less than t and t
is less than t
WE
8.
is High for Read cycle.
9. Device is continuously selected. Chip enable and output enables are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip enable.
RC
11. t =Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a Write cycle.
13. Capacitance derating applies to capacitance different from the load capacitance shown in
Fig. 1.
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 6/14
M21L216128A
Timing Waveforms
Read Cycle 1(8, 9)
R C
t
Ad dr es s
A A
t
C H
t
Dou t
Read Cycle 2(7, 8, 9, 10)
R C
t
Ad dr es s
A A
t
C E
A C E
C H Z
t
t
C L Z
t
B E
t
HB, LB
B H Z
t
B L Z
t
OE
O E
t
O H Z
t
O L Z
t
Dou t
: D O N ' T C A R E
: U N D E F I N E D
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 7/14
M21L216128A
Timing Waveforms (continued)
Write Cycle 1(7, 12, 13)
(Write Enable Controlled with Output Enable OE active LOW)
W C
t
A d d r e s s
W R
t
A W
t
C W
t
C E
B W
t
H B , L B
A S
t
W P 2
t
W E
D W
t
D H
t
t
D i n
W H Z
t
O W
D o u t
D O N ' T C A R E
U N D E F I N E D
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 8/14
M21L216128A
Timing Waveforms (continued)
Write Cycle 2(12, 13)
(Write Enable Controlled with Output Enable OE active HIGH)
W C
t
A d d r e s s
W R
t
A W
t
C W
t
C E
B W
t
H B , L B
A S
t
W P 1
t
W E
D W
t
D H
t
D i n
H I G H - Z
D o u t
D O N ' T C A R E
U N D E F I N E D
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 9/14
M21L216128A
Timing Waveforms (continued)
Write Cycle 3(12, 13)
(Chip Enable Controlled)
t W C
A d d r e s s
W R
t
t A W
t A S
t C W
t B W
C E
H B , L B
t W P 1
W E
t D W
t D H
D in
H I G H - Z
D o u t
D O N ' T C A R E
U N D E F I N E D
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 10/14
M21L216128A
Timing Waveforms (continued)
Write Cycle 4(12, 13)
(Byte Enable Controlled)
t W C
A d d r e s s
t A W
t C W
t B W
C E
t A S
t W R
H B , L B
t W P 1
W E
t D W
t D H
D in
H I G H - Z
D o u t
D O N ' T C A R E
U N D E F I N E D
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 11/14
M21L216128A
PACKING DIMENSIONS
44-LEAD
SOJ
SRAM(400mil)
DIMENSION ( INCH )
DIMENSION ( MM )
SYMBOL
MIN
0.128
0.082
0.025
0.015
0.015
0.007
0.007
1.120
0.435
0.394
0º
NOM
MAX
0.148
-
MIN
3.25
2.08
0.60
0.38
0.38
0.18
0.18
28.45
11.05
10.01
0º
NOM
MAX
3.76
-
A
A1
A2
b
0.138
3.51
-
-
-
-
-
-
-
-
0.020
0.018
0.013
0.011
1.130
0.445
0.405
10º
0.51
0.46
0.21
0.28
28.70
11.30
10.29
10º
b1
c
-
-
-
-
c1
D
0.008
1.125
0.440
0.400
0.20
28.58
11.18
10.16
E
E1
e
0.050BSC
1.27 BSC
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0 12/14
M21L216128A
PACKING DIMENSIONS
44-LEAD TSOP(II)
SRAM(400mil)
Symbol
Dimension in mm
Dimension in inch
Min
Norm
Max
1.20
0.15
1.05
0.45
0.40
0.21
0.16
18.54
Min
Norm
Max
A
A1
A2
B
B1
C
C1
D
ZD
E
0.047
0.006
0.042
0.018
0.016
0.008
0.006
0.730
0.05
0.95
0.30
0.30
0.12
0.10
18.28
0.002
0.037
0.012
0.012
0.005
0.004
0.720
1.00
0.35
0.039
0.014
18.41
0.805 REF
11.76
0.725
0.0317 REF
0.463
11.56
10.03
0.40
11.96
10.29
0.69
0.455
0.395
0.016
0.471
0.4
0.027
E1
L
10.16
0.59
0.400
0.023
L1
e
0.80 REF
0.80 BSC
0.031 REF
0.0315 BSC
θ
°
°
°
°
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
13/14
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
14/14
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