M4TKVE6AE [ETC]
32-bit Microcontroller;
| 型号： | M4TKVE6AE |
| 厂家： | 
ETC |
| 描述： | 32-bit Microcontroller 微控制器 |
| 文件： | 总144页 (文件大小：3123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M4TK
ARM® Cortex® -M
32-bit Microcontroller
NuMicro® Family
M4TK Series
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
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TABLE OF CONTENTS
1
2
GENERAL DESCRIPTION............................................................................................8
FEATURES .................................................................................................................10
NuMicro® M4TK Features ..................................................................................................10
Abbreviations...............................................................................................................16
PARTS INFORMATION LIST AND PIN CONFIGURATION........................................18
NuMicro® M4TK Selection Guide .......................................................................................18
2.1
4.1
3
4
4.1.1 NuMicro® M4TK Naming Rule.......................................................................................................... 18
4.1.2 NuMicro® M4TK CAN Series (CAN+USB) Selection Guide............................................................. 19
4.2
Pin Configuration ...............................................................................................................20
4.2.1 NuMicro® M4TK CAN Series (CAN+USB) LQFP48 Pin Diagram.................................................... 20
4.2.2 NuMicro® M4TK CAN Series (CAN+USB) LQFP64 Pin Diagram.................................................... 21
4.2.3 NuMicro® M4TK CAN Series (CAN+USB) LQFP100 Pin Diagram.................................................. 22
4.3
Pin Description...................................................................................................................23
4.3.1 M4TK CAN Series(CAN+USB) LQFP48 Pin Description................................................................. 23
4.3.2 M4TK CAN Series(CAN+USB) LQFP64 Pin Description................................................................. 30
4.3.3 M4TK CAN Series(CAN+USB) LQFP100 Pin Description............................................................... 39
4.3.4 GPIO Multi-function Pin Summary ................................................................................................... 51
5
6
BLOCK DIAGRAM.......................................................................................................60
5.1
NuMicro® M4TK Block Diagram .........................................................................................60
FUNCTIONAL DESCRIPTION ....................................................................................61
ARM® Cortex® -M4 Core .....................................................................................................61
System Manager................................................................................................................64
6.1
6.2
6.2.1 Overview........................................................................................................................................... 64
6.2.2 System Reset ................................................................................................................................... 64
6.2.3 Power Modes and Wake-up Sources............................................................................................... 71
6.2.4 System Power Distribution ............................................................................................................... 73
6.2.5 System Memory Map ....................................................................................................................... 75
6.2.6 SRAM Memory Organization............................................................................................................ 78
6.2.7 System Timer (SysTick) ................................................................................................................... 81
6.2.8 Nested Vectored Interrupt Controller (NVIC) ................................................................................... 81
6.3
Clock Controller .................................................................................................................82
6.3.1 Overview........................................................................................................................................... 82
6.3.2 Clock Generator ............................................................................................................................... 84
6.3.3 System Clock and SysTick Clock..................................................................................................... 85
6.3.4 Peripherals Clock ............................................................................................................................. 86
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6.3.5 Power-down Mode Clock ................................................................................................................. 87
6.3.6 Clock Output..................................................................................................................................... 87
6.4
Flash Memeory Controller (FMC).......................................................................................89
6.4.1 Overview........................................................................................................................................... 89
6.4.2 Features ........................................................................................................................................... 89
6.5
External Bus Interface (EBI)...............................................................................................90
6.5.1 Overview........................................................................................................................................... 90
6.5.2 Features ........................................................................................................................................... 90
6.6
General Purpose I/O (GPIO)..............................................................................................91
6.6.1 Overview........................................................................................................................................... 91
6.6.2 Features ........................................................................................................................................... 91
6.7
PDMA Controller (PDMA) ..................................................................................................92
6.7.1 Overview........................................................................................................................................... 92
6.7.2 Features ........................................................................................................................................... 92
6.8
Timer Controller (TMR) ......................................................................................................93
6.8.1 Overview........................................................................................................................................... 93
6.8.2 Features ........................................................................................................................................... 93
6.9
PWM Generator and Capture Timer (PWM).......................................................................94
6.9.1 Overview........................................................................................................................................... 94
6.9.2 Features ........................................................................................................................................... 94
6.10 Watchdog Timer (WDT) .....................................................................................................96
6.10.1 Overview........................................................................................................................................... 96
6.10.2 Features ........................................................................................................................................... 96
6.11 Window Watchdog Timer (WWDT) ....................................................................................97
6.11.1 Overview........................................................................................................................................... 97
6.11.2 Features ........................................................................................................................................... 97
6.12 Real Time Clock (RTC)......................................................................................................98
6.12.1 Overview........................................................................................................................................... 98
6.12.2 Features ........................................................................................................................................... 98
6.13 UART Interface Controller (UART).....................................................................................99
6.13.1 Overview........................................................................................................................................... 99
6.13.2 Features ........................................................................................................................................... 99
6.14 Smart Card Host Interface (SC) .......................................................................................101
6.14.1 Overview......................................................................................................................................... 101
6.14.2 Features ......................................................................................................................................... 101
6.15 I2C Serial Interface Controller (I2C)...................................................................................102
6.15.1 Overview......................................................................................................................................... 102
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6.15.2 Features ......................................................................................................................................... 102
6.16 Serial Peripheral Interface (SPI).......................................................................................103
6.16.1 Overview......................................................................................................................................... 103
6.16.2 Features ......................................................................................................................................... 103
6.17 USB Device Controller (USBD) ........................................................................................104
6.17.1 Overview......................................................................................................................................... 104
6.17.2 Features ......................................................................................................................................... 104
6.18 USB 1.1 Host Controller (USBH)......................................................................................105
6.18.1 Overview......................................................................................................................................... 105
6.18.2 Features ......................................................................................................................................... 105
6.19 USB On-The-Go (OTG) ...................................................................................................106
6.19.1 Overview......................................................................................................................................... 106
6.19.2 Features ......................................................................................................................................... 106
6.20 Controller Area Network (CAN)........................................................................................107
6.20.1 Overview......................................................................................................................................... 107
6.20.2 Features ......................................................................................................................................... 107
6.21 Touch Key (TK)................................................................................................................108
6.21.1 Overview......................................................................................................................................... 108
6.21.2 Features ......................................................................................................................................... 108
6.22 CRC Controller (CRC)......................................................................................................109
6.22.1 Overview......................................................................................................................................... 109
6.22.2 Features ......................................................................................................................................... 109
6.23 Enhanced 12-bit Analog-to-Digital Converter (EADC) ......................................................110
6.23.1 Overview......................................................................................................................................... 110
6.23.2 Features ......................................................................................................................................... 110
6.24 Digital to Analog Converter (DAC)....................................................................................111
6.24.1 Overview......................................................................................................................................... 111
6.24.2 Features ......................................................................................................................................... 111
6.25 Analog Comparator Controller (ACMP) ............................................................................112
6.25.1 Overview......................................................................................................................................... 112
6.25.2 Features ......................................................................................................................................... 112
7
8
APPLICATION CIRCUIT ...........................................................................................113
ELECTRICAL CHARACTERISTICS..........................................................................114
8.1
8.2
8.3
Absolute Maximum Ratings..............................................................................................114
DC Electrical Characteristics............................................................................................115
AC Electrical Characteristics............................................................................................121
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8.3.1 External 4~24 MHz High Speed Crystal (HXT) Input Clock........................................................... 121
8.3.2 External 4~20 MHz High Speed Crystal (HXT) Oscillator.............................................................. 121
8.3.3 22.1184 MHz Internal High Speed RC Oscillator (HIRC) .............................................................. 122
8.3.4 32.768 kHz External Low Speed Crystal (LXT) Input Clock .......................................................... 123
8.3.5 32.768 kHz External Low Speed Crystal (LXT) Oscillator ............................................................. 123
8.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC) .......................................................................... 124
8.4
Analog Characteristics .....................................................................................................125
8.4.1 12-bit SAR ADC.............................................................................................................................. 125
8.4.2 LDO ................................................................................................................................................ 127
8.4.3 Low Voltage Reset ......................................................................................................................... 127
8.4.4 Brown-out Detector ........................................................................................................................ 127
8.4.5 Power-on Reset.............................................................................................................................. 127
8.4.6 Temperature Sensor ...................................................................................................................... 128
8.4.7 Comparator..................................................................................................................................... 129
8.4.8 12-bit DAC...................................................................................................................................... 129
8.4.9 Internal Voltage Reference............................................................................................................. 130
8.4.10 USB PHY........................................................................................................................................ 130
8.5
Flash DC Electrical Characteristics ..................................................................................132
I2C Dynamic Characteristics.............................................................................................133
SPI Dynamic Characteristics............................................................................................134
8.6
8.7
8.7.1 Dynamic Characteristics of Data Input and Output Pin.................................................................. 134
8.8
I2S Dynamic Characteristics.............................................................................................137
PACKAGE DIMENSIONS..........................................................................................139
LQFP 100L (14x14x1.4 mm footprint 2.0 mm)..................................................................139
LQFP 64L (10x10x1.4 mm footprint 2.0 mm) ...................................................................140
LQFP 64L (7x7x1.4 mm footprint 2.0 mm) .......................................................................141
LQFP 48L (7x7x1.4mm footprint 2.0mm) .........................................................................142
9
9.1
9.2
9.3
9.4
10 REVISION HISTORY.................................................................................................143
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List of Figures
Figure 4.1-1 NuMicro® M4TK Selection Code.................................................................................................... 18
Figure 4.2-1 NuMicro® M4TK CAN Series (CAN+USB) LQFP 48-pin Diagram................................................. 20
Figure 4.2-2 NuMicro® M4TK CAN Series (CAN+USB) LQFP 64-pin Diagram................................................. 21
Figure 4.2-3 NuMicro® M4TK CAN Series (CAN+USB) LQFP 100-pin Diagram............................................... 22
Figure 5.1-1 NuMicro® M4TK Block Diagram..................................................................................................... 60
Figure 6.1-1 Cortex® -M4 Block Diagram............................................................................................................ 61
Figure 6.2-1 System Reset Sources .................................................................................................................. 65
Figure 6.2-2 nRESET Reset Waveform ............................................................................................................. 68
Figure 6.2-3 Power-on Reset (POR) Waveform ................................................................................................ 68
Figure 6.2-4 Low Voltage Reset (LVR) Waveform............................................................................................. 69
Figure 6.2-5 Brown-out Detector (BOD) Waveform ........................................................................................... 70
Figure 6.2-6 Power Mode State Machine........................................................................................................... 71
Figure 6.2-7 NuMicro® M4TK Power Distribution Diagram ................................................................................ 74
Figure 6.2-8 SRAM Block Diagram .................................................................................................................... 78
Figure 6.2-9 SRAM Memory Organization ......................................................................................................... 79
Figure 6.3-1 Clock Generator Global View Diagram.......................................................................................... 83
Figure 6.3-2 Clock Generator Block Diagram .................................................................................................... 84
Figure 6.3-3 System Clock Block Diagram......................................................................................................... 85
Figure 6.3-4 HXT Stop Protect Procedure ......................................................................................................... 86
Figure 6.3-5 SysTick Clock Control Block Diagram ........................................................................................... 86
Figure 6.3-6 Clock Source of Clock Output........................................................................................................ 87
Figure 6.3-7 Clock Output Block Diagram.......................................................................................................... 88
Figure 8.3-1 Typical Crystal Application Circuit ............................................................................................... 122
Figure 8.3-2 HIRC Accuracy vs. Temperature ................................................................................................. 122
Figure 8.3-3 Typical Crystal Application Circuit ............................................................................................... 124
Figure 8.4-1 Typical connection diagram using the ADC................................................................................. 126
Figure 8.4-2 Power-up Ramp Condition........................................................................................................... 128
Figure 8.6-1 I2C Timing Diagram...................................................................................................................... 133
Figure 8.7-1 SPI Master Mode Timing Diagram............................................................................................... 134
Figure 8.7-2 SPI Slave Mode Timing Diagram................................................................................................. 136
Figure 8.8-1 I2S Master Mode Timing Diagram................................................................................................ 138
Figure 8.8-2 I2S Slave Mode Timing Diagram.................................................................................................. 138
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List of Tables
Table 1-1 Key Features Support Table .................................................................................................................8
Table 3-1 List of Abbreviations........................................................................................................................... 17
Table 4-1 M4TK GPIO Multi-function Table ....................................................................................................... 59
Table 6-1 Reset Value of Registers ................................................................................................................... 67
Table 6-2 Power Mode Difference Table............................................................................................................ 71
Table 6-3 Clocks in Power Modes...................................................................................................................... 73
Table 6-4 Condition of Entering Power-down Mode Again ................................................................................ 73
Table 6-5 Address Space Assignments for On-Chip Controllers....................................................................... 77
Table 6-6 NuMicro® M4TK Series UART Feature............................................................................................ 100
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1
GENERAL DESCRIPTION
The M4TK series includes a total of 33 ARM® Cortex® -M4F based products, including the M4TK
CAN Series which is pin compatible with M051 LQFP48 and M058S LQFP64. By planning a
complete product line, Nuvoton hopes to fulfill the demand for the ARM® Cortex® -M4F core with
products at all levels and realize its customer commitment: total support for long-term
competitiveness enhancement, and to fulfill their current product development demand and future
innovation imagination.
The M4TK series embedded with the ARM® Cortex® -M4F core supports DSC (digital signal
controller) and FPU (float point unit) and features high performance computing capability running
up to 72 MHz, built-in 256/128KB Flash ROM, 32/16 KB SRAM complying with IEC60730, built-in
boot ROM and independent 4 KB in-system programming Flash ROM for developing more flexible
online upgrade code that support external UART, SPI, I2C, CAN and USB. It also supports EBI to
provide greater flexibility for external memory. The entire M4TK series is provided with
outstanding specifications: four 32-bit timers, dual watchdogs, and integrates plenty of peripherals
such as PDMA and RTCs, five UARTs that support 16-byte FIFO, three sets of SPI controllers
that support quad mode, two I²C devices that support SMBus and PMBus, two sets of I2S, two
LINs, CAN bus, ISO-7816-3 interface, full-speed USB OTG, full-speed USB devices, 16-channel
12-bit ADC with 1 MSPS conversion rate, built-in reference voltage (VREF) for circuit generation,
12-bit DAC, two analog comparators and temperature detectors.
The M4TK series provides two special designs. One is high-resolution 144 MHz PWM with high-
speed electromechanical control timer and resolution<7ns. In conjunction with a driver ADC, it
delivers hardware brake protection and pulse capture functions to save MCU computing burden
and effectively carry out advanced computing required by motor control, making it exceptionally
outstanding in industrial automation and motor control performance. The other is VAI (Voltage
Adjustment Interface) system to support voltage level adjustment with individual I/O (1.8V-5.5V)
for saving additional cost on adjusting the interface voltage difference of peripheral components.
The M4TK series also provides the wide operating voltage (2.5V-5.5V) and 5V-tolerance input I/O
to significantly enhance system stability, industrial operating temperature (-40°C - 105°C),
22.1184 MHz internal RC oscillator (HIRC variation < ±2%) and 32.768 kHz external crystal
oscillator to trim HIRC (HIRC variation < ±0.25%) working at -40˚C- 105˚C to boost system
immunity and adequately fulfill the high precision demand of communications. The M4TK series is
specifically suitable for high-performance and high-precision applications, such as industrial
control, system automation, security surveillance, autotronics and digital power control.
Product Line
USB
CAN UART
I2C
I2S
SPI
PWM
ADC
DAC
RTC
EBI
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M4TK
Table 1-1 Key Features Support Table
The NuMicro® M4TK series is suitable for a wide range of applications such as:
Industrial Automation
PLCs
Inverters
Home Automation
Security Alarm System
Power Metering
Portable Data Collector
Portable RFID Reader
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System Supervisors
Smart Card Reader
Printer
Bar Code Scanner
Motor Control
Digital Power
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2 FEATURES
2.1 NuMicro® M4TK Features
Core
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ARM® Cortex® -M4F core running up to 72 MHz
Supports DSP extension with hardware divider
Supports IEEE 754 compliant Floating-point Unit (FPU)
Supports Memory Protection Unit (MPU)
One 24-bit system timer
Supports Low Power Sleep mode by WFI and WFE instructions
Single-cycle 32-bit hardware multiplier
Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
(NVIC)
–
Supports programmable mask-able interrupts
Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
Flash Memory
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Supports 128/256 KB application ROM (APROM)
Supports 4 KB Flash for loader (LDROM)
Supports Data Flash with configurable memory size
Supports In-System-Programming (ISP), In-Application-Programming (IAP) update
embedded flash memory
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Supports 2 KB page erase for all embedded flash
Boot Loader
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16 KB embedded ROM
Supports Nuvoton native In-System-Programming (ISP) for UART0, SPI0, I2C0, CAN*1
and USB*2
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Supports direct boot from Boot Loader by pin selection
SRAM Memory
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32/16 KB embedded SRAM
16/8 KB with hardware parity check
Supports byte-, half-word- and word-access
Supports exception (NMI) generated once a parity check error occurs
Supports PDMA mode
PDMA (Peripheral DMA)
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Supports 12/8 independent configurable channels for automatic data transfer between
memories and peripherals
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Supports Normal and Scatter-Gather Transfer modes
Supports two types of priorities modes: Fixed-priority and Round-robin modes
Supports byte-, half-word- and word-access
Auto increment of the source and destination address
Supports single and burst transfer type
Clock Control
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Built-in 22.1184 MHz internal high speed RC oscillator (HIRC) for system operation
(variation < 2% at -40˚C ~ +105˚C)
Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-
up operation
Built-in 4~20 MHz external high speed crystal oscillator (HXT) for precise timing
operation
Built-in 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and
low-power system operation
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Supports one PLL up to 144 MHz for high performance system operation, sourced
from HIRC and HXT
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Supports clock failure detection for high/low speed external crystal oscillator
Supports exception (NMI) generated once a clock failure detected
Supports clock output
GPIO
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Four I/O modes
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level trigger setting
Supports high driver and high sink current I/O (up to 20 mA at 5V)
Supports software selectable slew rate control
Supports 5V-tolerance function for following pins
PA.0 ~ PA.15, PC.0 ~ PC.7, PC.9 ~ PC.15, PD.5 ~ PD.8, PD.10 ~ PD.15, PE.0
~ PE.14, PF.2, PF.5 ~ PF.6
PA.0 ~ PA.15, PB.14 ~ PB.14, PC.0 ~ PC.8, PC.10 ~ PC.13, PD.4 ~ PD.7,
PD.12 ~ PD.15, PE.0 ~ PE.1, PE.3 ~ PE.5, PE.8 ~ PE.13, PF.2.
–
Supports up to 85/55/42 GPIOs for LQFP100/64/48 respectively
Timer
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Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
Independent clock source for each timer
Provides One-shot, Periodic, Toggle and Continuous Counting operation modes
Supports event counting function to count the event from external pin
Supports input capture function to capture or reset counter value
Watchdog Timer
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Supports multiple clock sources from LIRC (default selection), HCLK/2048 and LXT
8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source)
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Window Watchdog Timer
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Supports multiple clock sources from HCLK/2048 (default selection) and LIRC
Window set by 6-bit counter with 11-bit prescale
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on time-out
RTC
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Supports external power pin VBAT
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
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Supports wake-up function
Supports 80 bytes spare registers
Programmable spare register erase function
Supports 32KHz Oscillator gain control
Supports tamper detection function
PWM
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Supports up to 12 independent PWM outputs with 16-bit resolution
Supports maximum clock frequency up to 144MHz
Supports 12-bit clock prescale
Supports one-shot or auto-reload counter operation mode
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Supports up, down or up-down PWM counter type
Supports synchronous function
Supports dead time with maximum divided 12-bit prescale
Supports brake function source from pin, comparator output and system safety events
Supports PWM auto recovery function after brake condition removed
Supports mask function and tri-state output for each PWM pin
Supports PWM events interrupt
Supports trigger EADC/DAC start conversion
Supports up to 12 independent input capture channels with rising/falling capture and
with counter reload option
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Supports capture counter with 16-bit resolution
Supports capture interrupt
Supports capture PDMA mode
UART
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Supports up to four UARTs – UART0, UART1, UART2 and UART3
Supports 16-byte FIFOs with programmable level trigger
Supports auto flow control ( CTS and RTS)
Supports IrDA (SIR) function
Supports RS-485 9-bit mode and direction control
UART0 and UART1 support LIN function
Programmable baud-rate generator up to 1/16 system clock
Supports wake-up function
Supports PDMA mode
Smart Card Interface
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One set of ISO-7816-3 port
Compliant to ISO-7816-3 T=0, T=1
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8 bit time-out counters for Answer to Request (ATR) and waiting times
processing
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Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation/deactivation sequence process
Supports hardware warm reset sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART function
SPI
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Supports one set of SPI Quad controller – SPI0
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the byte reorder function
Supports Byte or Word Suspend mode
Supports PDMA mode
Supports 3-wired, no slave select signal, bi-direction interface
Master up to 32 MHz, and Slave up to 16 MHz (when chip works at VDD = 5V)
SPI/ I2S
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Supports up to two sets of SPI controllers – SPI1 and SPI2
Supports Master or Slave mode operation
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 4-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports the byte reorder function
Supports Byte or Word Suspend mode
Supports 3-wire, no slave select signal, bi-direction interface
Master mode up to 36 MHz and Slave mode up to 18 MHz (when chip works at VDD
5V)
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Supports up to two sets of I2S by SPI controllers – SPI1 and SPI2
Interface with external audio CODEC
Supports Master and Slave mode
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports mono and stereo audio data
Supports PCM mode A, PCM mode B, I2S and MSB justified data format
Each provides two 4-word FIFO data buffers, one for transmitting and the other for
receiving
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I2C
Generates interrupt requests when buffer levels cross a programmable boundary
Each supports two PDMA requests, one for transmitting and the other for receiving
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Supports up to two sets of I2C devices
Supports Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
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Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
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Programmable clocks allow versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports SMBus and PMBus
Supports speed up to 1Mbps
Supports multi-address Power-down wake-up function
CAN 2.0
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Supports up to one set of CAN controller
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1M bit/s
Each supports 32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Object)
Supports interrupts
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Supports power-down wake-up function
USB 2.0 FS Controller
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Supports one set of USB 2.0 FS OTG
FS Host compatible with Open HCI 1.0 specification
Compliant to USB specification version 2.0
OTG compliant with USB OTG Supplement 1.3
On-chip USB Transceiver
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
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Provides 8 programmable endpoints
Supports 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
On-chip 5V to 3.3V LDO for USB PHY
EBI
–
–
Supports two dedicated external chip select pins for each memory block
Supports accessible space up to 1 MB for each bank, actually external addressable
space is dependent on package pin out
–
–
–
–
–
Supports 8-/16-bit data width
Supports byte write in 16-bit data width mode
Supports PDMA mode
Supports Address/Data multiplexed Mode
Supports Timing parameters individual adjustment for each memory block
EADC
–
–
–
–
–
–
–
–
–
–
Analog input voltage range: 0~ VREF (Max to AVDD)
Supports single 12-bit SAR ADC conversion
12-bit resolution and 10-bit accuracy is guaranteed
Up to 1MSPS conversion rate at 5.0V
Up to 16 external single-ended analog input channels
Up to 8 differential analog input pairs
Supports single ADC interrupt
Supports external VREF pin
Support internal reference voltages from Band-gap and Voltage divider
An A/D conversion can be triggered by Software enable, External pin, Timer 0~3
overflow pulse trigger and PWM trigger
–
Supports 3 internal channels for VBAT, band-gap VBG input and Temperature sensor
input
–
Supports PDMA transfer
DAC
–
–
–
–
–
–
Supports a 12-bit voltage type DAC
Rail to rail settle time 8us
External reference voltage VREF
Max. output voltage AVDD -0.2V at buffer mode
Conversion started by software enable or PDMA trigger
Supports PDMA mode
Touch Key
–
–
–
–
–
–
Supports up to 16 touch keys
Supports programmable sensitivity adjustment for each channel
Supports programmable scan speed for different applications
Supports any key Wake-up for low-power applications
Supports manual/one-time or periodic key-scan initiation
Supports programmable interrupt options for automatic key-scan and interrupt
generation
Analog Comparator
–
–
–
–
–
Up to two rail-to-rail analog comparators
Supports a multiplexed I/O pin at positive node.
Supports I/O pins, band-gap, Voltage divider and DAC output at negative node
Supports programmable speed and power consumption
Interrupts generated when compare results change (Interrupt event condition is
programmable)
–
–
Supports Power-down Wake-up
Supports triggers for break events and cycle-by-cycle control for PWM
Jan. 06, 2016
Page 14 of 144
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M4TK
Cyclic Redundancy Calculation Unit
–
–
–
–
–
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
Programmable initial value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum.
Supports 8-/16-/32-bit of data width
–
Interrupt generated once checksum error occurs
Voltage Adjustable Interface
–
–
Supports user Configurable 1.8~5.5V I/O Interface with a dedicated power input (VDDIO
)
Supports UART1, SPI0, SPI1, I2C1 or I2C0 interface
Supports 96-bit Unique ID (UID)
Supports 128-bit Unique Customer ID (UCID)
One built-in temperature sensor with 1℃ resolution
Brown-out detector
–
–
With 4 levels: 4.4 V/ 3.7 V/ 2.7 V/ 2.2 V
Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–
Threshold voltage levels: 2.0 V
Operating Temperature: -40℃~105℃
Packages
–
–
–
–
–
All Green package (RoHS)
LQFP 100-pin (14mm x 14mm)
LQFP 64-pin (10mm x 10mm)
LQFP 64-pin (7mm x 7mm)
LQFP 48-pin (7mm x 7mm)
Note:
*1: For optional part numbers which support CAN
*2: For optional part numbers which support USB
Jan. 06, 2016
Page 15 of 144
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M4TK
3 ABBREVIATIONS
Acronym
ACMP
ADC
AES
APB
AHB
BOD
CAN
DAP
DES
EBI
Description
Analog Comparator Controller
Analog-to-Digital Converter
Advanced Encryption Standard
Advanced Peripheral Bus
Advanced High-Performance Bus
Brown-out Detection
Controller Area Network
Debug Access Port
Data Encryption Standard
External Bus Interface
EPWM
FIFO
FMC
FPU
GPIO
HCLK
HIRC
HXT
Enhanced Pulse Width Modulation
First In, First Out
Flash Memory Controller
Floating-point Unit
General-Purpose Input/Output
The Clock of Advanced High-Performance Bus
22.1184 MHz Internal High Speed RC Oscillator
4~20 MHz External High Speed Crystal Oscillator
In Application Programming
In Circuit Programming
IAP
ICP
ISP
In System Programming
LDO
LIN
Low Dropout Regulator
Local Interconnect Network
10 kHz internal low speed RC oscillator (LIRC)
Memory Protection Unit
LIRC
MPU
NVIC
PCLK
PDMA
PLL
Nested Vectored Interrupt Controller
The Clock of Advanced Peripheral Bus
Peripheral Direct Memory Access
Phase-Locked Loop
PWM
QEI
Pulse Width Modulation
Quadrature Encoder Interface
Secure Digital
SD
SPI
Serial Peripheral Interface
Jan. 06, 2016
Page 16 of 144
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M4TK
SPS
Samples per Second
TDES
TK
Triple Data Encryption Standard
Touch Key
TMR
UART
UCID
USB
Timer Controller
Universal Asynchronous Receiver/Transmitter
Unique Customer ID
Universal Serial Bus
WDT
WWDT
Watchdog Timer
Window Watchdog Timer
Table 3-1 List of Abbreviations
Jan. 06, 2016
Page 17 of 144
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M4TK
4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro® M4TK Selection Guide
4.1.1
NuMicro® M4TK Naming Rule
ARM–Based
32-bit Microcontroller
M4TK-X X X X X
CPU Core
®
Corte -M4
TK: Touch key
Temperature
E: -40oC ~ +105oC
Reserved
SRAM Size
3: 16KB
6: 32KB
Package Type
Flash ROM
L: LQFP 48 7x7mm
S: LQFP 64 7x7mm
R: LQFP 64 10x10mm
V: LQFP 100 14x14mm
E: 128KB
G: 256KB
Figure 4.1-1 NuMicro® M4TK Selection Code
In this document, M4TKxG means the part numbers which include 256 KB flash, M4TKxE means the
part numbers which include 128 KB flash.
Jan. 06, 2016
Page 18 of 144
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M4TK
4.1.2
NuMicro® M4TK CAN Series (CAN+USB) Selection Guide
Connectivity
M4TKLG6A
E
LQFP
48
256 32
4
4
4
4
4
4
34
34
48
48
80
80
4
4
4
4
4
4
3+1
3+1
4+1
4+1
4+1
4+1
1
1
1
1
1
1
3
3
3
3
3
3
2
2
2
2
2
2
√
√
√
√
√
√
2
2
2
2
2
2
2
2
2
2
2
2
OTG 10
OTG 10
OTG 12
OTG 12
OTG 12
OTG 12
2
2
2
2
2
2
1
1
1
1
1
1
8-ch
8-ch
6
6
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
LQFP
48
M4TKLE6AE 128 32
M4TKRG6A
256 32
E
LQFP
64
12-ch 11
12-ch 11
16-ch 16
16-ch 16
M4TKRE6A
128 32
E
LQFP
64
M4TKVG6A
256 32
E
LQFP
100
LQFP
100
M4TKVE6AE 128 32
*Marked in this table (4+1) means 4 UART + 1 SC UART
*SC (ISO-7816) supports full duplex UART mode
Jan. 06, 2016
Page 19 of 144
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M4TK
4.2 Pin Configuration
NuMicro® M4TK CAN Series (CAN+USB) LQFP48 Pin Diagram
Corresponding Part Number: M4TKLG6AE, M4TKLE6AE
4.2.1
PA.3
PA.2
PA.1
PA.0
VDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
PE.0
PC.4
PC.3
PC.2
PC.1
AVDD
VREF
PB.0
PB.1
PB.2
PB.3
PB.4
PC.0
LQFP 48-pin
LDO_CAP
VSS
PF.4/XT1_IN
PF.3/XT1_OUT
PD.7
PF.2
Figure 4.2-1 NuMicro® M4TK CAN Series (CAN+USB) LQFP 48-pin Diagram
Jan. 06, 2016
Page 20 of 144
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M4TK
4.2.2
NuMicro® M4TK CAN Series (CAN+USB) LQFP64 Pin Diagram
Corresponding Part Number: M4TKRG6AE, M4TKRE6AE
PA.3
PA.2
PA.1
PA.0
VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PC.5
PC.4
PC.3
PC.2
PC.1
VDD
PC.0
AVDD
VREF
LDO_CAP
VDD
LQFP 64-pin
PB.0
PB.1
PB.2
PB.3
PB.4
PB.8
PB.11
PB.12
VSS
PF.4/XT1_IN
PF.3/XT1_OUT
PD.7
PD.15
PD.14
PD.13
PD.12
Figure 4.2-2 NuMicro® M4TK CAN Series (CAN+USB) LQFP 64-pin Diagram.
Jan. 06, 2016
Page 21 of 144
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M4TK
4.2.3
NuMicro® M4TK CAN Series (CAN+USB) LQFP100 Pin Diagram
Corresponding Part Number: M4TKVG6AE, M4TKVE6AE
USB_ID
USB_VDD33_CAP
PE.2
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PC.5
PE.0
PC.4
PA.3
PC.3
PA.2
PC.2
PA.1
PC.1
PA.0
PC.0
PA.12
PA.13
PA.14
PA.15
VSS
PC.14
PC.13
PC.12
PC.11
PC.10
PC.9
VDD
LQFP 100-pin
AVDD
LDO_CAP
VDD
VREF
PB.0
VSS
PB.1
PF.4/XT1_IN
PF.3/XT1_OUT
PD.7
PB.2
PB.3
PB.4
PD.15
PD.14
PD.13
PD.12
PD.11
PD.10
PB.8
PB.9
PB.10
PB.11
PB.12
Figure 4.2-3 NuMicro® M4TK CAN Series (CAN+USB) LQFP 100-pin Diagram.
Jan. 06, 2016
Page 22 of 144
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M4TK
4.3 Pin Description
4.3.1
M4TK CAN Series(CAN+USB) LQFP48 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
Pin Name
PB.5
Type
I/O
A
MFP*
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
Description
1
General purpose digital I/O pin.
EADC analog input channel 13.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Touch Key3.
EADC_CH13
SPI0_MOSI0
SPI1_MOSI
TK3
I/O
I/O
A
ACMP0_P2
EBI_AD6
PB.6
A
Comparator0 positive input pin.
EBI address/data bus bit 6.
General purpose digital I/O pin.
EADC analog input channel 14.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
Touch Key4.
I/O
I/O
A
2
EADC_CH14
SPI0_MISO0
SPI1_MISO
TK4
I/O
I/O
A
ACMP0_P1
EBI_AD5
PB.7
A
Comparator0 positive input pin.
EBI address/data bus bit 5.
General purpose digital I/O pin.
EADC analog input channel 15.
SPI0 serial clock pin.
I/O
I/O
A
3
EADC_CH15
SPI0_CLK
SPI1_CLK
TK5
I/O
I/O
A
SPI1 serial clock pin
Touch Key5.
ACMP0_P0
EBI_AD4
nRESET
A
Comparator0 positive input pin.
EBI address/data bus bit 4.
I/O
I
4
5
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PD.0
I/O
O
I
MFP0
MFP2
MFP3
MFP4
MFP5
MFP8
MFP0
General purpose digital I/O pin.
I2S1 master clock output pin.
Data receiver input pin for UART0.
Touch Key6.
SPI1_I2SMCLK
UART0_RXD
TK6
A
A
I
ACMP1_N
INT3
Comparator1 negative input pin.
External interrupt3 input pin.
Ground pin for analog circuit.
6
AVSS
P
Jan. 06, 2016
Page 23 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
PD.1
Type
MFP*
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP0
MFP1
MFP8
MFP0
MFP1
MFP0
MFP1
MFP0
MFP3
MFP4
Description
7
I/O
I
General purpose digital I/O pin.
PWM0 counter synchronous trigger input pin.
Data transmitter output pin for UART0.
Touch Key10.
PWM0_SYNC_IN
UART0_TXD
TK10
O
A
A
I/O
O
I/O
I
ACMP1_P2
T0
Comparator1 positive input pin.
Timer0event counter input / toggle output
EBI read enable output pin.
EBI_nRD
PD.2
8
General purpose digital I/O pin.
ADC external trigger input.
STADC
T0_EXT
TK11
I
Timer0 external capture input.
Touch Key11.
A
A
I
ACMP1_P1
PWM0_BRAKE0
EBI_nWR
INT0
Comparator1 positive input pin.
PWM0 break input 0
O
I
EBI write enable output pin.
External interrupt0 input pin.
9
PD.3
I/O
I/O
I
General purpose digital I/O pin.
Timer2 event counter input / toggle output
Timer1 external capture input
Touch Key12.
T2
T1_EXT
TK12
A
A
I
ACMP1_P0
PWM0_BRAKE1
EBI_MCLK
INT1
Comparator1 positive input pin.
PWM0 break input 1
O
I
EBI external clock output pin
External interrupt1 input pin.
10
11
VBAT
Power supply by batteries for RTC and PF.0~PF.2.
General purpose digital I/O pin.
External 32.768 kHZ (low speed) crystal output pin.
External interrupt5 input pin.
PF.0
I/O
O
X32_OUT
INT5
I
12
13
14
PF.1
I/O
I
General purpose digital I/O pin.
External 32.768 kHZ (low speed) crystal input pin.
General purpose digital I/O pin.
TAMPER detector loop pin
X32_IN
PF.2
I/O
I/O
I/O
I
TAMPER
PD.7
General purpose digital I/O pin.
PWM0 counter synchronous trigger input pin.
Timer1 event counter input / toggle output
PWM0_SYNC_IN
T1
I/O
Jan. 06, 2016
Page 24 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
ACMP0_O
PWM0_CH5
EBI_nRD
PF.3
Type
O
MFP*
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP0
MFP1
MFP3
MFP0
MFP0
Description
Comparator0 output.
I/O
O
PWM0 output/capture input.
EBI read enable output pin.
General purpose digital I/O pin.
External 4~20 MHz (high speed) crystal output pin.
I2C1 clock pin.
15
16
I/O
O
XT1_OUT
I2C1_SCL
PF.4
I/O
I/O
I
General purpose digital I/O pin.
External 4~20 MHz (high speed) crystal input pin.
I2C1 data input/output pin.
Ground pin for digital circuit.
LDO output pin.
XT1_IN
I2C1_SDA
VSS
I/O
A
17
18
LDO_CAP
A
Note: This pin needs to be connected with a 1uF
capacitor.
19
PC.0
I/O
I/O
I
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP0
MFP2
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
UART2_nCTS
CAN0_TXD
PWM0_CH0
EBI_AD8
INT2
Clear to Send input pin for UART2.
CAN bus transmitter input.
PWM0 output/capture input.
EBI address/data bus bit 8.
External interrupt2 input pin.
General purpose digital I/O pin.
Clock Out
I
I/O
I/O
I
20
PC.1
I/O
O
CLKO
STDAC
I
DAC external trigger input.
Request to Send output pin for UART2.
CAN bus receiver input.
UART2_nRTS
CAN0_RXD
PWM0_CH1
EBI_AD9
PC.2
O
I
I/O
I/O
I/O
I
PWM0 output/capture input.
EBI address/data bus bit 9.
General purpose digital I/O pin.
SPI2 slave select pin.
21
SPI2_SS
UART2_TXD
ACMP1_O
PWM0_CH2
EBI_AD10
PC.3
O
Data transmitter output pin for UART2.
Comparator1 output .
O
I/O
I/O
I/O
I/O
PWM0 output/capture input.
EBI address/data bus bit 10.
General purpose digital I/O pin.
SPI2 MOSI (Master Out, Slave In) pin.
22
SPI2_MOSI
Jan. 06, 2016
Page 25 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
UART2_RXD
USB_VBUS_ST
PWM0_CH3
EBI_AD11
PC.4
Type
I
MFP*
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
Description
Data receiver input pin for UART2.
USB external VBUS regulator status pin.
PWM0 output/capture input.
I
I/O
I/O
I/O
I/O
I/O
O
EBI address/data bus bit 11.
23
General purpose digital I/O pin.
SPI2 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
SPI2_MISO
I2C1_SCL
USB_VBUS_EN
PWM0_CH4
EBI_AD12
PE.0
USB external VBUS regulator enable pin.
PWM0 output/capture input.
I/O
I/O
I/O
I/O
I/O
I
EBI address/data bus bit 12.
24
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
I2C1_SDA
T2_EXT
I2C1 data input/output pin.
Timer2 external capture input
SmartCard card detect pin.
SC0_CD
I
PWM0_CH0
EBI_nCS1
INT4
I/O
O
PWM0 output/capture input.
EBI chip select 1 enable output pin.
External interrupt4 input pin.
I
25
26
27
PF.5
I/O
I
General purpose digital I/O pin.
Serial wired debugger clock pin
General purpose digital I/O pin.
Serial wired debugger data pin
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI0 1st MISO (Master In, Slave Out) pin.
Clear to Send input pin for UART1.
I2C0 SMBus SMBALTER# pin
SmartCard data pin.
ICE_CLK
PF.6
I/O
I/O
I/O
I/O
I/O
I
ICE_DAT
PE.10
SPI1_MISO
SPI0_MISO0
UART1_nCTS
I2C0_SMBAL
SC0_DAT
PE.11
O
I/O
I/O
I/O
I/O
O
28
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
Request to Send output pin for UART1.
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SmartCard clock pin.
SPI1_MOSI
SPI0_MOSI0
UART1_nRTS
I2C0_SMBSUS
SC0_CLK
O
O
Jan. 06, 2016
Page 26 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
PE.12
Type
I/O
I/O
I/O
O
MFP*
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
Description
29
General purpose digital I/O pin.
SPI1 slave select pin
SPI1_SS
SPI0_SS
UART1_TXD
I2C0_SCL
PE.13
SPI0 slave select pin.
Data transmitter output pin for UART1.
I2C0 clock pin.
I/O
I/O
I/O
I/O
I
30
General purpose digital I/O pin.
SPI1 serial clock pin
SPI1_CLK
SPI0_CLK
UART1_RXD
I2C0_SDA
VDDIO
SPI0 serial clock pin.
Data receiver input pin for UART1.
I2C0 data input/output pin.
Power supply for PE.10~PE.13.
Power supply from USB* host or HUB.
USB differential signal D-.
USB differential signal D+.
USB identification.
I/O
A
31
32
33
34
USB_VBUS
USB_D-
A
I
USB_D+
I
USB_ID
I
36
37
USB_VDD33_CAP
A
Internal power regulator output 3.3V decoupling pin.
Note: This pin needs to be connected with a 1uF
capacitor.
PA.3
I/O
I
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
General purpose digital I/O pin.
USB external VBUS regulator status pin.
Data receiver input pin for UART0.
Request to Send output pin for UART0.
I2C0 clock pin.
USB_VBUS_ST
UART0_RXD
UART0_nRTS
I2C0_SCL
SC0_PWR
PWM1_CH2
EBI_AD3
I
O
I/O
O
SmartCard power pin.
I/O
I/O
I/O
O
PWM1 output/capture input.
EBI address/data bus bit 3.
38
PA.2
General purpose digital I/O pin.
USB external VBUS regulator enable pin.
Data transmitter output pin for UART0.
Clear to Send input pin for UART0.
I2C0 data input/output pin.
USB_VBUS_EN
UART0_TXD
UART0_nCTS
I2C0_SDA
SC0_RST
PWM1_CH3
EBI_AD2
O
I
I/O
O
SmartCard reset pin.
I/O
I/O
I/O
PWM1 output/capture input.
EBI address/data bus bit 2.
39
PA.1
General purpose digital I/O pin.
Jan. 06, 2016
Page 27 of 144
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M4TK
Pin No.
Pin Name
UART1_nRTS
UART1_RXD
CAN0_TXD
SC0_DAT
PWM1_CH4
EBI_AD1
Type
O
MFP*
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
Description
Request to Send output pin for UART1.
Data receiver input pin for UART1.
CAN bus transmitter input.
SmartCard data pin.
I
I
I/O
I/O
I/O
I/O
I
PWM1 output/capture input.
EBI address/data bus bit 1.
General purpose digital I/O pin.
Clear to Send input pin for UART1.
Data transmitter output pin for UART1.
CAN bus receiver input.
40
PA.0
UART1_nCTS
UART1_TXD
CAN0_RXD
SC0_CLK
PWM1_CH5
EBI_AD0
O
I
O
SmartCard clock pin.
I/O
I/O
I
PWM1 output/capture input.
EBI address/data bus bit 0.
External interrupt0 input pin.
INT0
41
VDD
A
Power supply for I/O ports and LDO source for internal
PLL and digital function.
42
43
AVDD
VREF
A
I
MFP0
MFP0
Power supply for internal analog circuit.
Voltage reference input for ADC.
Note: This pin needs to be connected with a 1uF
capacitor.
44
PB.0
I/O
A
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
General purpose digital I/O pin.
EADC analog input.
EADC_CH0
SPI0_MOSI1
UART2_RXD
T2
I/O
I
SPI0 2nd MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART2.
Timer2 event counter input / toggle output
DAC analog output
I/O
A
DAC
EBI_nWRL
INT1
O
EBI low byte write enable output pin.
External interrupt1 input pin.
I
45
PB.1
I/O
A
General purpose digital I/O pin.
EADC analog input channel 1.
EADC_CH1
SPI0_MISO1
UART2_TXD
T3
I/O
O
SPI0 2nd MISO (Master In, Slave Out) pin.
Data transmitter output pin for UART2.
Timer3 event counter input / toggle output
SmartCard reset pin.
I/O
O
SC0_RST
PWM0_SYNC_OUT
EBI_nWRH
O
PWM0 counter synchronous trigger output pin.
EBI high byte write enable output pin
O
Jan. 06, 2016
Page 28 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
PB.2
Type
I/O
A
MFP*
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
Description
46
General purpose digital I/O pin.
EADC analog input channel 2.
SPI0 serial clock pin.
EADC_CH2
SPI0_CLK
SPI1_CLK
UART1_RXD
SC0_CD
I/O
I/O
I
SPI1 serial clock pin
Data receiver input pin for UART1.
SmartCard card detect pin.
General purpose digital I/O pin.
EADC analog input channel 3.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
EADC analog input channel 4.
SPI0 slave select pin.
I
47
PB.3
I/O
A
EADC_CH3
SPI0_MISO0
SPI1_MISO
UART1_TXD
PB.4
I/O
I/O
O
48
I/O
A
EADC_CH4
SPI0_SS
I/O
I/O
I
SPI1_SS
SPI1 slave select pin
UART1_nCTS
ACMP0_N
EBI_AD7
Clear to Send input pin for UART1.
Comparator0 negative input pin.
EBI address/data bus bit 7.
A
I/O
Jan. 06, 2016
Page 29 of 144
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M4TK
4.3.2
M4TK CAN Series(CAN+USB) LQFP64 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Pin No.
Pin Name
PB.15
Type
I/O
A
MFP*
MFP0
MFP1
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
Description
1
General purpose digital I/O pin.
EADC analog input channel 12.
Touch Key2.
EADC_CH12
TK2
A
ACMP0_P3
EBI_nCS1
PB.5
A
Comparator0 positive input pin.
EBI chip select 1 enable output pin.
General purpose digital I/O pin.
EADC analog input channel 13.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Touch Key3.
O
2
3
4
I/O
A
EADC_CH13
SPI0_MOSI0
SPI1_MOSI
TK3
I/O
I/O
A
ACMP0_P2
EBI_AD6
PB.6
A
Comparator0 positive input pin.
EBI address/data bus bit 6.
General purpose digital I/O pin.
EADC analog input channel 14.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
Touch Key4.
I/O
I/O
A
EADC_CH14
SPI0_MISO0
SPI1_MISO
TK4
I/O
I/O
A
ACMP0_P1
EBI_AD5
PB.7
A
Comparator0 positive input pin.
EBI address/data bus bit 5.
General purpose digital I/O pin.
EADC analog input channel 15.
SPI0 serial clock pin.
I/O
I/O
A
EADC_CH15
SPI0_CLK
SPI1_CLK
TK5
I/O
I/O
A
SPI1 serial clock pin
Touch Key5.
ACMP0_P0
EBI_AD4
nRESET
A
Comparator0 positive input pin.
EBI address/data bus bit 4.
I/O
I
5
6
External reset input: active LOW, with an internal pull-up.
Set this pin low reset to initial state.
PD.0
I/O
O
I
MFP0
MFP2
MFP3
General purpose digital I/O pin.
I2S1 master clock output pin.
Data receiver input pin for UART0.
SPI1_I2SMCLK
UART0_RXD
Jan. 06, 2016
Page 30 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
TK6
Type
A
MFP*
MFP4
MFP5
MFP8
MFP0
MFP0
MFP4
MFP7
MFP0
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
Description
Touch Key6.
ACMP1_N
INT3
A
Comparator1 negative input pin.
External interrupt3 input pin.
Ground pin for analog circuit.
General purpose digital I/O pin.
Touch Key0.
I
7
8
AVSS
P
PD.8
I/O
A
TK8
EBI_nCS0
PD.9
O
I/O
A
EBI chip select 0 enable output pin.
General purpose digital I/O pin.
Touch Key8.
9
TK9
ACMP1_P3
EBI_ALE
PD.1
A
Comparator1 positive input pin.
EBI address latch enable output pin.
General purpose digital I/O pin.
PWM0 counter synchronous trigger input pin.
Data transmitter output pin for UART0.
Touch Key10.
O
I/O
I
10
PWM0_SYNC_IN
UART0_TXD
TK10
O
A
ACMP1_P2
T0
A
Comparator1 positive input pin.
Timer0event counter input / toggle output
EBI read enable output pin.
General purpose digital I/O pin.
ADC external trigger input.
Timer0 external capture input.
Touch Key11.
I/O
O
I/O
I
EBI_nRD
PD.2
11
STADC
T0_EXT
TK11
I
A
ACMP1_P1
PWM0_BRAKE0
EBI_nWR
INT0
A
Comparator1 positive input pin.
PWM0 break input 0
I
O
I
EBI write enable output pin.
External interrupt0 input pin.
General purpose digital I/O pin.
Timer2 event counter input / toggle output
Timer1 external capture input
Touch Key12.
12
PD.3
I/O
I/O
I
T2
T1_EXT
TK12
A
ACMP1_P0
PWM0_BRAKE1
EBI_MCLK
INT1
A
Comparator1 positive input pin.
PWM0 break input 1
I
O
I
EBI external clock output pin
External interrupt1 input pin.
Jan. 06, 2016
Page 31 of 144
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M4TK
Pin No.
13
Pin Name
VBAT
Type
MFP*
MFP0
MFP0
MFP1
MFP8
MFP0
MFP1
MFP0
MFP1
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP3
MFP4
MFP5
MFP6
MFP7
Description
Power supply by batteries for RTC and PF.0~PF.2.
General purpose digital I/O pin.
External 32.768 kHZ (low speed) crystal output pin.
External interrupt5 input pin.
14
PF.0
I/O
O
X32_OUT
INT5
I
15
16
17
PF.1
I/O
I
General purpose digital I/O pin.
External 32.768 kHZ (low speed) crystal input pin.
General purpose digital I/O pin.
TAMPER detector loop pin
X32_IN
PF.2
I/O
I/O
I/O
I
TAMPER
PD.12
General purpose digital I/O pin.
SPI2 slave select pin.
SPI2_SS
UART3_TXD
PWM1_CH0
EBI_ADR16
PD.13
O
Data transmitter output pin for UART3.
PWM1 output/capture input.
I/O
O
EBI address bus bit 16.
18
19
20
21
I/O
I/O
I
General purpose digital I/O pin.
SPI2 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART3.
PWM1 output/capture input.
SPI2_MOSI
UART3_RXD
PWM1_CH1
EBI_ADR17
PD.14
I/O
O
EBI address bus bit 17.
I/O
I/O
I
General purpose digital I/O pin.
SPI2 MISO (Master In, Slave Out) pin.
Clear to Send input pin for UART3.
PWM1 output/capture input.
SPI2_MISO
UART3_nCTS
PWM1_CH2
EBI_ADR18
PD.15
I/O
O
EBI address bus bit 18.
I/O
I/O
O
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
UART3_nRTS
PWM1_CH3
EBI_ADR19
PD.7
Request to Send output pin for UART3.
PWM1 output/capture input.
I/O
O
EBI address bus bit 19.
I/O
I
General purpose digital I/O pin.
PWM0 counter synchronous trigger input pin.
Timer1 event counter input / toggle output
Comparator0 output.
PWM0_SYNC_IN
T1
I/O
O
ACMP0_O
PWM0_CH5
EBI_nRD
I/O
O
PWM0 output/capture input.
EBI read enable output pin.
Jan. 06, 2016
Page 32 of 144
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M4TK
Pin No.
Pin Name
PF.3
Type
I/O
O
MFP*
MFP0
MFP1
MFP3
MFP0
MFP1
MFP3
MFP0
MFP0
Description
22
General purpose digital I/O pin.
External 4~20 MHz (high speed) crystal output pin.
I2C1 clock pin.
XT1_OUT
I2C1_SCL
PF.4
I/O
I/O
I
23
General purpose digital I/O pin.
External 4~20 MHz (high speed) crystal input pin.
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
VSS
I/O
A
24
25
Ground pin for digital circuit.
VDD
A
Power supply for I/O ports and LDO source for internal
PLL and digital function.
26
27
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
PC.0
I/O
I/O
I
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
UART2_nCTS
CAN0_TXD
PWM0_CH0
EBI_AD8
INT2
Clear to Send input pin for UART2.
CAN bus transmitter input.
PWM0 output/capture input.
EBI address/data bus bit 8.
External interrupt2 input pin.
General purpose digital I/O pin.
Clock Out
I
I/O
I/O
I
28
PC.1
I/O
O
CLKO
STDAC
I
DAC external trigger input.
Request to Send output pin for UART2.
CAN bus receiver input.
UART2_nRTS
CAN0_RXD
PWM0_CH1
EBI_AD9
PC.2
O
I
I/O
I/O
I/O
I
PWM0 output/capture input.
EBI address/data bus bit 9.
General purpose digital I/O pin.
SPI2 slave select pin.
29
SPI2_SS
UART2_TXD
ACMP1_O
PWM0_CH2
EBI_AD10
PC.3
O
Data transmitter output pin for UART2.
Comparator1 output .
O
I/O
I/O
I/O
I/O
I
PWM0 output/capture input.
EBI address/data bus bit 10.
General purpose digital I/O pin.
SPI2 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART2.
USB external VBUS regulator status pin.
30
SPI2_MOSI
UART2_RXD
USB_VBUS_ST
I
Jan. 06, 2016
Page 33 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
PWM0_CH3
EBI_AD11
PC.4
Type
I/O
I/O
I/O
I/O
I/O
O
MFP*
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP6
MFP7
MFP0
MFP3
MFP5
MFP6
MFP7
MFP0
MFP3
MFP6
MFP7
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP2
MFP4
MFP5
MFP0
MFP1
MFP2
MFP4
Description
PWM0 output/capture input.
EBI address/data bus bit 11.
General purpose digital I/O pin.
SPI2 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
31
SPI2_MISO
I2C1_SCL
USB_VBUS_EN
PWM0_CH4
EBI_AD12
PC.5
USB external VBUS regulator enable pin.
PWM0 output/capture input.
EBI address/data bus bit 12.
General purpose digital I/O pin.
I2S2 master clock output pin.
PWM0 output/capture input.
EBI address/data bus bit 13.
General purpose digital I/O pin.
I2C1 SMBus SMBALTER# pin
Comparator1 output .
I/O
I/O
I/O
O
32
33
SPI2_I2SMCLK
PWM0_CH5
EBI_AD13
PC.6
I/O
I/O
I/O
O
I2C1_SMBAL
ACMP1_O
PWM1_CH0
EBI_AD14
PC.7
O
I/O
I/O
I/O
O
PWM1 output/capture input.
EBI address/data bus bit 14.
General purpose digital I/O pin.
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1 output/capture input.
EBI address/data bus bit 15.
General purpose digital I/O pin.
Serial wired debugger clock pin
General purpose digital I/O pin.
Serial wired debugger data pin
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SPI0 2nd MISO (Master In, Slave Out) pin.
I2C1 clock pin.
34
I2C1_SMBSUS
PWM1_CH1
EBI_AD15
PF.5
I/O
I/O
I/O
I
35
36
37
ICE_CLK
PF.6
I/O
I/O
I/O
O
ICE_DAT
PE.8
UART1_TXD
SPI0_MISO1
I2C1_SCL
SC0_PWR
PE.9
I/O
I/O
O
SmartCard power pin.
38
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART1.
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
UART1_RXD
SPI0_MOSI1
I2C1_SDA
I/O
I/O
Jan. 06, 2016
Page 34 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
SC0_RST
PE.10
Type
O
MFP*
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
Description
SmartCard reset pin.
39
I/O
I/O
I/O
I
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI0 1st MISO (Master In, Slave Out) pin.
Clear to Send input pin for UART1.
I2C0 SMBus SMBALTER# pin
SmartCard data pin.
SPI1_MISO
SPI0_MISO0
UART1_nCTS
I2C0_SMBAL
SC0_DAT
PE.11
O
I/O
I/O
I/O
I/O
O
40
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
Request to Send output pin for UART1.
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SmartCard clock pin.
SPI1_MOSI
SPI0_MOSI0
UART1_nRTS
I2C0_SMBSUS
SC0_CLK
PE.12
O
O
41
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI1 slave select pin
SPI1_SS
SPI0_SS
SPI0 slave select pin.
UART1_TXD
I2C0_SCL
PE.13
Data transmitter output pin for UART1.
I2C0 clock pin.
I/O
I/O
I/O
I/O
I
42
General purpose digital I/O pin.
SPI1 serial clock pin
SPI1_CLK
SPI0_CLK
UART1_RXD
I2C0_SDA
VDDIO
SPI0 serial clock pin.
Data receiver input pin for UART1.
I2C0 data input/output pin.
I/O
A
43
44
45
46
Power supply for PE.8~PE.13.
Power supply from USB* host or HUB.
USB differential signal D-.
USB_VBUS
USB_D-
A
I
USB_D+
I
USB differential signal D+.
USB_ID
I
USB identification.
48
49
USB_VDD33_CAP
A
Internal power regulator output 3.3V decoupling pin.
Note: This pin needs to be connected with a 1uF
capacitor.
PA.3
I/O
MFP0
MFP1
MFP2
MFP3
General purpose digital I/O pin.
USB_VBUS_ST
UART0_RXD
UART0_nRTS
I
I
USB external VBUS regulator status pin.
Data receiver input pin for UART0.
Request to Send output pin for UART0.
O
Jan. 06, 2016
Page 35 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
I2C0_SCL
SC0_PWR
PWM1_CH2
EBI_AD3
Type
I/O
O
MFP*
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP0
Description
I2C0 clock pin.
SmartCard power pin.
I/O
I/O
I/O
O
PWM1 output/capture input.
EBI address/data bus bit 3.
General purpose digital I/O pin.
USB external VBUS regulator enable pin.
Data transmitter output pin for UART0.
Clear to Send input pin for UART0.
I2C0 data input/output pin.
SmartCard reset pin.
50
PA.2
USB_VBUS_EN
UART0_TXD
UART0_nCTS
I2C0_SDA
SC0_RST
PWM1_CH3
EBI_AD2
O
I
I/O
O
I/O
I/O
I/O
O
PWM1 output/capture input.
EBI address/data bus bit 2.
General purpose digital I/O pin.
Request to Send output pin for UART1.
Data receiver input pin for UART1.
CAN bus transmitter input.
SmartCard data pin.
51
PA.1
UART1_nRTS
UART1_RXD
CAN0_TXD
SC0_DAT
PWM1_CH4
EBI_AD1
I
I
I/O
I/O
I/O
I/O
I
PWM1 output/capture input.
EBI address/data bus bit 1.
General purpose digital I/O pin.
Clear to Send input pin for UART1.
Data transmitter output pin for UART1.
CAN bus receiver input.
52
PA.0
UART1_nCTS
UART1_TXD
CAN0_RXD
SC0_CLK
PWM1_CH5
EBI_AD0
O
I
O
SmartCard clock pin.
I/O
I/O
I
PWM1 output/capture input.
EBI address/data bus bit 0.
External interrupt0 input pin.
Ground pin for digital circuit.
INT0
53
54
VSS
A
VDD
A
Power supply for I/O ports and LDO source for internal
PLL and digital function.
55
56
AVDD
VREF
A
I
MFP0
MFP0
Power supply for internal analog circuit.
Voltage reference input for ADC.
Note: This pin needs to be connected with a 1uF
capacitor.
57
PB.0
I/O
A
MFP0
MFP1
General purpose digital I/O pin.
EADC analog input.
EADC_CH0
Jan. 06, 2016
Page 36 of 144
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Pin No.
Pin Name
SPI0_MOSI1
UART2_RXD
T2
Type
I/O
I
MFP*
MFP2
MFP3
MFP4
MFP5
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
Description
SPI0 2nd MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART2.
Timer2 event counter input / toggle output
DAC analog output
I/O
A
DAC
EBI_nWRL
INT1
O
EBI low byte write enable output pin.
External interrupt1 input pin.
I
58
PB.1
I/O
A
General purpose digital I/O pin.
EADC analog input channel 1.
SPI0 2nd MISO (Master In, Slave Out) pin.
Data transmitter output pin for UART2.
Timer3 event counter input / toggle output
SmartCard reset pin.
EADC_CH1
SPI0_MISO1
UART2_TXD
T3
I/O
O
I/O
O
SC0_RST
PWM0_SYNC_OUT
EBI_nWRH
PB.2
O
PWM0 counter synchronous trigger output pin.
EBI high byte write enable output pin
General purpose digital I/O pin.
EADC analog input channel 2.
SPI0 serial clock pin.
O
59
I/O
A
EADC_CH2
SPI0_CLK
SPI1_CLK
UART1_RXD
SC0_CD
I/O
I/O
I
SPI1 serial clock pin
Data receiver input pin for UART1.
SmartCard card detect pin.
I
60
PB.3
I/O
A
General purpose digital I/O pin.
EADC analog input channel 3.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
Data transmitter output pin for UART1.
General purpose digital I/O pin.
EADC analog input channel 4.
SPI0 slave select pin.
EADC_CH3
SPI0_MISO0
SPI1_MISO
UART1_TXD
PB.4
I/O
I/O
O
61
I/O
A
EADC_CH4
SPI0_SS
SPI1_SS
UART1_nCTS
ACMP0_N
EBI_AD7
PB.8
I/O
I/O
I
SPI1 slave select pin
Clear to Send input pin for UART1.
Comparator0 negative input pin.
EBI address/data bus bit 7.
A
I/O
I/O
A
62
General purpose digital I/O pin.
EADC analog input channel 5.
EADC_CH5
Jan. 06, 2016
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Rev.1.00
M4TK
Pin No.
Pin Name
UART1_nRTS
PWM0_CH2
PB.11
Type
O
MFP*
MFP4
MFP6
MFP0
MFP1
MFP4
MFP0
MFP1
MFP4
Description
Request to Send output pin for UART1.
PWM0 output/capture input.
General purpose digital I/O pin.
EADC analog input channel 8.
Touch Key0.
I/O
I/O
A
63
EADC_CH8
TK0
A
64
PB.12
I/O
A
General purpose digital I/O pin.
EADC analog input channel 9.
Touch Key1.
EADC_CH9
TK1
A
Jan. 06, 2016
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M4TK
4.3.3
M4TK CAN Series(CAN+USB) LQFP100 Pin Description
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0] = 0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4] = 0x5.
Pin No.
Pin Name
PB.13
Type
I/O
A
MFP*
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
Description
1
General purpose digital I/O pin.
EADC analog input channel 10.
General purpose digital I/O pin.
EADC analog input channel 11.
General purpose digital I/O pin.
EADC analog input channel 12.
Touch Key2.
EADC_CH10
PB.14
2
3
I/O
A
EADC_CH11
PB.15
I/O
A
EADC_CH12
TK2
A
ACMP0_P3
EBI_nCS1
PB.5
A
Comparator0 positive input pin.
EBI chip select 1 enable output pin.
General purpose digital I/O pin.
EADC analog input channel 13.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI1 MOSI (Master Out, Slave In) pin.
Touch Key3.
O
4
5
6
7
I/O
A
EADC_CH13
SPI0_MOSI0
SPI1_MOSI
TK3
I/O
I/O
A
ACMP0_P2
EBI_AD6
PB.6
A
Comparator0 positive input pin.
EBI address/data bus bit 6.
General purpose digital I/O pin.
EADC analog input channel 14.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
Touch Key4.
I/O
I/O
A
EADC_CH14
SPI0_MISO0
SPI1_MISO
TK4
I/O
I/O
A
ACMP0_P1
EBI_AD5
PB.7
A
Comparator0 positive input pin.
EBI address/data bus bit 5.
General purpose digital I/O pin.
EADC analog input channel 15.
SPI0 serial clock pin.
I/O
I/O
A
EADC_CH15
SPI0_CLK
SPI1_CLK
TK5
I/O
I/O
A
SPI1 serial clock pin
Touch Key5.
ACMP0_P0
EBI_AD4
nRESET
A
Comparator0 positive input pin.
EBI address/data bus bit 4.
External reset input: active LOW, with an internal pull-up.
I/O
I
Jan. 06, 2016
Page 39 of 144
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M4TK
Pin No.
Pin Name
Type
MFP*
Description
Set this pin low reset to initial state.
8
PD.0
I/O
O
I
MFP0
MFP2
MFP3
MFP4
MFP5
MFP8
MFP0
MFP0
General purpose digital I/O pin.
I2S1 master clock output pin.
Data receiver input pin for UART0.
Touch Key6.
SPI1_I2SMCLK
UART0_RXD
TK6
A
A
I
ACMP1_N
INT3
Comparator1 negative input pin.
External interrupt3 input pin.
Ground pin for analog circuit.
9
AVSS
P
A
10
VDD
Power supply for I/O ports and LDO source for internal
PLL and digital function.
11
12
VSS
A
I/O
A
MFP0
MFP0
MFP4
MFP0
MFP4
MFP7
MFP0
MFP4
MFP5
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
Ground pin for digital circuit.
General purpose digital I/O pin.
Touch Key7.
PC.8
TK7
13
14
PD.8
I/O
A
General purpose digital I/O pin.
Touch Key0.
TK8
EBI_nCS0
PD.9
O
I/O
A
EBI chip select 0 enable output pin.
General purpose digital I/O pin.
Touch Key8.
TK9
ACMP1_P3
EBI_ALE
PD.1
A
Comparator1 positive input pin.
EBI address latch enable output pin.
General purpose digital I/O pin.
PWM0 counter synchronous trigger input pin.
Data transmitter output pin for UART0.
Touch Key10.
O
I/O
I
15
PWM0_SYNC_IN
UART0_TXD
TK10
O
A
ACMP1_P2
T0
A
Comparator1 positive input pin.
Timer0event counter input / toggle output
EBI read enable output pin.
General purpose digital I/O pin.
ADC external trigger input.
Timer0 external capture input.
Touch Key11.
I/O
O
I/O
I
EBI_nRD
PD.2
16
STADC
T0_EXT
TK11
I
A
ACMP1_P1
PWM0_BRAKE0
EBI_nWR
INT0
A
Comparator1 positive input pin.
PWM0 break input 0
I
O
I
EBI write enable output pin.
External interrupt0 input pin.
Jan. 06, 2016
Page 40 of 144
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M4TK
Pin No.
Pin Name
PD.3
Type
I/O
I/O
I
MFP*
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP0
MFP2
MFP4
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
Description
17
General purpose digital I/O pin.
Timer2 event counter input / toggle output
Timer1 external capture input
Touch Key12.
T2
T1_EXT
TK12
A
ACMP1_P0
PWM0_BRAKE1
EBI_MCLK
INT1
A
Comparator1 positive input pin.
PWM0 break input 1
I
O
EBI external clock output pin
External interrupt1 input pin.
General purpose digital I/O pin.
SPI1 serial clock pin
I
18
PD.4
I/O
I/O
I/O
A
SPI1_CLK
I2C0_SDA
TK13
I2C0 data input/output pin.
Touch Key13.
PWM0_BRAKE0
T0
I
PWM0 break input 0
I/O
I/O
O
Timer0event counter input / toggle output
General purpose digital I/O pin.
Clock Out
19
PD.5
CLKO
SPI1_MISO
I2C0_SCL
TK14
I/O
I/O
A
SPI1 MISO (Master In, Slave Out) pin.
I2C0 clock pin.
Touch Key14.
PWM0_BRAKE1
T1
I
PWM0 break input 1
I/O
I/O
I/O
A
Timer1 event counter input / toggle output
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
Touch Key15.
20
21
PE.3
SPI1_MOSI
TK15
PWM0_CH3
PD.6
I/O
I/O
O
PWM0 output/capture input.
General purpose digital I/O pin.
Clock Out
CLKO
SPI1_SS
UART0_RXD
TK16
I/O
I
SPI1 slave select pin
Data receiver input pin for UART0.
Touch Key16.
A
ACMP0_O
PWM0_CH5
EBI_nWR
VBAT
O
Comparator0 output.
I/O
O
PWM0 output/capture input.
EBI write enable output pin.
Power supply by batteries for RTC and PF.0~PF.2.
22
A
Jan. 06, 2016
Page 41 of 144
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M4TK
Pin No.
Pin Name
PF.0
Type
I/O
O
MFP*
MFP0
MFP1
MFP8
MFP0
MFP1
MFP0
MFP1
MFP0
MFP4
MFP0
MFP4
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP2
MFP3
MFP6
MFP7
MFP0
MFP3
MFP4
Description
23
General purpose digital I/O pin.
External 32.768 kHZ (low speed) crystal output pin.
External interrupt5 input pin.
X32_OUT
INT5
I
24
25
26
27
28
PF.1
I/O
I
General purpose digital I/O pin.
External 32.768 kHZ (low speed) crystal input pin.
General purpose digital I/O pin.
TAMPER detector loop pin
X32_IN
PF.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TAMPER
PD.10
General purpose digital I/O pin.
Timer2 event counter input / toggle output
General purpose digital I/O pin.
Timer3 event counter input / toggle output.
General purpose digital I/O pin.
SPI2 slave select pin.
T2
PD.11
T3
PD.12
SPI2_SS
UART3_TXD
PWM1_CH0
EBI_ADR16
PD.13
O
Data transmitter output pin for UART3.
PWM1 output/capture input.
I/O
O
EBI address bus bit 16.
29
30
31
32
I/O
I/O
I
General purpose digital I/O pin.
SPI2 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART3.
PWM1 output/capture input.
SPI2_MOSI
UART3_RXD
PWM1_CH1
EBI_ADR17
PD.14
I/O
O
EBI address bus bit 17.
I/O
I/O
I
General purpose digital I/O pin.
SPI2 MISO (Master In, Slave Out) pin.
Clear to Send input pin for UART3.
PWM1 output/capture input.
SPI2_MISO
UART3_nCTS
PWM1_CH2
EBI_ADR18
PD.15
I/O
O
EBI address bus bit 18.
I/O
I/O
O
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_CLK
UART3_nRTS
PWM1_CH3
EBI_ADR19
PD.7
Request to Send output pin for UART3.
PWM1 output/capture input.
I/O
O
EBI address bus bit 19.
I/O
I
General purpose digital I/O pin.
PWM0 counter synchronous trigger input pin.
Timer1 event counter input / toggle output
PWM0_SYNC_IN
T1
I/O
Jan. 06, 2016
Page 42 of 144
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M4TK
Pin No.
Pin Name
ACMP0_O
PWM0_CH5
EBI_nRD
PF.3
Type
O
MFP*
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP0
MFP1
MFP3
MFP0
MFP0
Description
Comparator0 output.
I/O
O
PWM0 output/capture input.
EBI read enable output pin.
General purpose digital I/O pin.
External 4~20 MHz (high speed) crystal output pin.
I2C1 clock pin.
33
34
I/O
O
XT1_OUT
I2C1_SCL
PF.4
I/O
I/O
I
General purpose digital I/O pin.
External 4~20 MHz (high speed) crystal input pin.
I2C1 data input/output pin.
XT1_IN
I2C1_SDA
VSS
I/O
A
35
36
Ground pin for digital circuit.
VDD
A
Power supply for I/O ports and LDO source for internal
PLL and digital function.
37
38
LDO_CAP
A
MFP0
LDO output pin.
Note: This pin needs to be connected with a 1uF
capacitor.
PC.9
I/O
O
MFP0
MFP2
MFP6
MFP0
MFP2
MFP6
MFP0
MFP2
MFP6
MFP0
MFP2
MFP6
MFP0
MFP2
MFP6
MFP0
MFP6
MFP0
MFP2
MFP3
MFP4
General purpose digital I/O pin.
I2S2 master clock output pin.
PWM1 output/capture input.
General purpose digital I/O pin.
SPI2 MOSI (Master Out, Slave In) pin.
PWM1 output/capture input.
General purpose digital I/O pin.
SPI2 MISO (Master In, Slave Out) pin.
PWM1 output/capture input.
General purpose digital I/O pin.
SPI2 serial clock pin.
SPI2_I2SMCLK
PWM1_CH0
PC.10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
39
40
41
42
SPI2_MOSI
PWM1_CH1
PC.11
SPI2_MISO
PWM1_CH2
PC.12
SPI2_CLK
PWM1_CH3
PC.13
PWM1 output/capture input.
General purpose digital I/O pin.
SPI2 slave select pin.
SPI2_SS
PWM1_CH4
PC.14
I/O
I/O
I/O
I/O
I/O
I
PWM1 output/capture input.
General purpose digital I/O pin.
PWM1 output/capture input.
General purpose digital I/O pin.
SPI2 serial clock pin.
43
44
PWM1_CH5
PC.0
SPI2_CLK
UART2_nCTS
CAN0_TXD
Clear to Send input pin for UART2.
CAN bus transmitter input.
I
Jan. 06, 2016
Page 43 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
PWM0_CH0
EBI_AD8
INT2
Type
I/O
I/O
I
MFP*
MFP6
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP5
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP6
MFP7
MFP0
MFP2
MFP3
MFP4
MFP5
MFP6
Description
PWM0 output/capture input.
EBI address/data bus bit 8.
External interrupt2 input pin.
General purpose digital I/O pin.
Clock Out
45
PC.1
I/O
O
CLKO
STDAC
I
DAC external trigger input.
Request to Send output pin for UART2.
CAN bus receiver input.
UART2_nRTS
CAN0_RXD
PWM0_CH1
EBI_AD9
PC.2
O
I
I/O
I/O
I/O
I
PWM0 output/capture input.
EBI address/data bus bit 9.
General purpose digital I/O pin.
SPI2 slave select pin.
46
47
48
49
SPI2_SS
UART2_TXD
ACMP1_O
PWM0_CH2
EBI_AD10
PC.3
O
Data transmitter output pin for UART2.
Comparator1 output .
O
I/O
I/O
I/O
I/O
I
PWM0 output/capture input.
EBI address/data bus bit 10.
General purpose digital I/O pin.
SPI2 MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART2.
USB external VBUS regulator status pin.
PWM0 output/capture input.
EBI address/data bus bit 11.
General purpose digital I/O pin.
SPI2 MISO (Master In, Slave Out) pin.
I2C1 clock pin.
SPI2_MOSI
UART2_RXD
USB_VBUS_ST
PWM0_CH3
EBI_AD11
PC.4
I
I/O
I/O
I/O
I/O
I/O
O
SPI2_MISO
I2C1_SCL
USB_VBUS_EN
PWM0_CH4
EBI_AD12
PE.0
USB external VBUS regulator enable pin.
PWM0 output/capture input.
EBI address/data bus bit 12.
General purpose digital I/O pin.
SPI2 serial clock pin.
I/O
I/O
I/O
I/O
I/O
I
SPI2_CLK
I2C1_SDA
T2_EXT
I2C1 data input/output pin.
Timer2 external capture input
SmartCard card detect pin.
PWM0 output/capture input.
SC0_CD
I
PWM0_CH0
I/O
Jan. 06, 2016
Page 44 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
EBI_nCS1
INT4
Type
O
MFP*
MFP7
MFP8
MFP0
MFP2
MFP6
MFP7
MFP0
MFP3
MFP5
MFP6
MFP7
MFP0
MFP3
MFP6
MFP7
MFP0
MFP3
MFP5
MFP6
MFP7
MFP8
MFP0
MFP3
MFP5
MFP6
MFP7
MFP8
MFP0
MFP1
MFP0
MFP1
MFP0
MFP3
MFP0
Description
EBI chip select 1 enable output pin.
External interrupt4 input pin.
General purpose digital I/O pin.
I2S2 master clock output pin.
PWM0 output/capture input.
EBI address/data bus bit 13.
General purpose digital I/O pin.
I2C1 SMBus SMBALTER# pin
Comparator1 output .
I
50
PC.5
I/O
O
SPI2_I2SMCLK
PWM0_CH5
EBI_AD13
PC.6
I/O
I/O
I/O
O
51
I2C1_SMBAL
ACMP1_O
PWM1_CH0
EBI_AD14
PC.7
O
I/O
I/O
I/O
O
PWM1 output/capture input.
EBI address/data bus bit 14.
General purpose digital I/O pin.
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
PWM1 output/capture input.
EBI address/data bus bit 15.
General purpose digital I/O pin.
I2C1 clock pin.
52
53
I2C1_SMBSUS
PWM1_CH1
EBI_AD15
PE.4
I/O
I/O
I/O
I/O
O
I2C1_SCL
SC0_PWR
PWM1_BRAKE0
EBI_nCS0
INT0
SmartCard power pin.
I
PWM1 break input 0
O
EBI chip select 0 enable output pin.
External interrupt0 input pin.
General purpose digital I/O pin.
I2C1 data input/output pin.
SmartCard reset pin.
I
54
PE.5
I/O
I/O
O
I2C1_SDA
SC0_RST
PWM1_BRAKE1
EBI_ALE
INT1
I
PWM1 break input 1
O
EBI address latch enable output pin.
External interrupt1 input pin.
General purpose digital I/O pin.
Serial wired debugger clock pin
General purpose digital I/O pin.
Serial wired debugger data pin
General purpose digital I/O pin.
Data transmitter output pin for UART3.
General purpose digital I/O pin.
I
55
56
57
58
PF.5
I/O
I
ICE_CLK
PF.6
I/O
I/O
I/O
O
ICE_DAT
PA.8
UART3_TXD
PA.9
I/O
Jan. 06, 2016
Page 45 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
UART3_RXD
PA.7
Type
I
MFP*
MFP3
MFP0
MFP2
MFP3
MFP7
MFP0
MFP2
MFP3
MFP7
MFP0
MFP2
MFP3
MFP7
MFP0
MFP2
MFP7
MFP0
MFP0
Description
Data receiver input pin for UART3.
General purpose digital I/O pin.
SPI1 serial clock pin
59
I/O
I/O
I
SPI1_CLK
T0_EXT
EBI_AD7
PA.6
Timer0 external capture input.
EBI address/data bus bit 7.
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
Timer1 external capture input
EBI address/data bus bit 6.
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
Timer2 external capture input
EBI address/data bus bit 5.
General purpose digital I/O pin.
SPI1 slave select pin
I/O
I/O
I/O
I
60
61
62
SPI1_MISO
T1_EXT
EBI_AD6
PA.5
I/O
I/O
I/O
I
SPI1_MOSI
T2_EXT
EBI_AD5
PA.4
I/O
I/O
I/O
I/O
A
SPI1_SS
EBI_AD4
VSS
EBI address/data bus bit 4.
Ground pin for digital circuit.
63
64
VDD
A
Power supply for I/O ports and LDO source for internal
PLL and digital function.
65
PE.1
I/O
I
MFP0
MFP3
MFP5
MFP6
MFP0
MFP1
MFP2
MFP4
MFP5
MFP0
MFP1
MFP2
MFP4
MFP5
MFP0
MFP1
General purpose digital I/O pin.
Timer3 external capture input
SmartCard card detect pin.
T3_EXT
SC0_CD
I
PWM0_CH1
PE.8
I/O
I/O
O
PWM0 output/capture input.
General purpose digital I/O pin.
Data transmitter output pin for UART1.
SPI0 2nd MISO (Master In, Slave Out) pin.
I2C1 clock pin.
66
UART1_TXD
SPI0_MISO1
I2C1_SCL
SC0_PWR
PE.9
I/O
I/O
O
SmartCard power pin.
67
I/O
I
General purpose digital I/O pin.
Data receiver input pin for UART1.
SPI0 2nd MOSI (Master Out, Slave In) pin.
I2C1 data input/output pin.
UART1_RXD
SPI0_MOSI1
I2C1_SDA
SC0_RST
PE.10
I/O
I/O
O
SmartCard reset pin.
68
I/O
I/O
General purpose digital I/O pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI1_MISO
Jan. 06, 2016
Page 46 of 144
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M4TK
Pin No.
Pin Name
SPI0_MISO0
UART1_nCTS
I2C0_SMBAL
SC0_DAT
PE.11
Type
I/O
I
MFP*
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP0
MFP0
MFP0
MFP0
MFP0
MFP0
Description
SPI0 1st MISO (Master In, Slave Out) pin.
Clear to Send input pin for UART1.
I2C0 SMBus SMBALTER# pin
SmartCard data pin.
O
I/O
I/O
I/O
I/O
O
69
General purpose digital I/O pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
Request to Send output pin for UART1.
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
SmartCard clock pin.
SPI1_MOSI
SPI0_MOSI0
UART1_nRTS
I2C0_SMBSUS
SC0_CLK
PE.12
O
O
70
I/O
I/O
I/O
O
General purpose digital I/O pin.
SPI1 slave select pin
SPI1_SS
SPI0_SS
SPI0 slave select pin.
UART1_TXD
I2C0_SCL
PE.13
Data transmitter output pin for UART1.
I2C0 clock pin.
I/O
I/O
I/O
I/O
I
71
General purpose digital I/O pin.
SPI1 serial clock pin
SPI1_CLK
SPI0_CLK
UART1_RXD
I2C0_SDA
VDDIO
SPI0 serial clock pin.
Data receiver input pin for UART1.
I2C0 data input/output pin.
I/O
A
72
73
74
75
Power supply for PE.8~PE.13.
Power supply from USB* host or HUB.
USB differential signal D-.
USB_VBUS
USB_D-
A
I
USB_D+
I
USB differential signal D+.
USB_ID
I
USB identification.
77
USB_VDD33_CAP
A
Internal power regulator output 3.3V decoupling pin.
Note: This pin needs to be connected with a 1uF
capacitor.
78
79
PE.2
I/O
I/O
I/O
I
MFP0
MFP6
MFP0
MFP1
MFP2
MFP3
MFP4
General purpose digital I/O pin.
PWM1 output/capture input.
PWM1_CH1
PA.3
General purpose digital I/O pin.
USB external VBUS regulator status pin.
Data receiver input pin for UART0.
Request to Send output pin for UART0.
I2C0 clock pin.
USB_VBUS_ST
UART0_RXD
UART0_nRTS
I2C0_SCL
I
O
I/O
Jan. 06, 2016
Page 47 of 144
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M4TK
Pin No.
Pin Name
SC0_PWR
PWM1_CH2
EBI_AD3
Type
O
MFP*
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP3
MFP4
MFP5
MFP6
MFP7
MFP8
MFP0
MFP2
MFP4
MFP0
MFP4
MFP0
MFP3
MFP4
Description
SmartCard power pin.
I/O
I/O
I/O
O
PWM1 output/capture input.
EBI address/data bus bit 3.
General purpose digital I/O pin.
USB external VBUS regulator enable pin.
Data transmitter output pin for UART0.
Clear to Send input pin for UART0.
I2C0 data input/output pin.
SmartCard reset pin.
80
PA.2
USB_VBUS_EN
UART0_TXD
UART0_nCTS
I2C0_SDA
SC0_RST
PWM1_CH3
EBI_AD2
O
I
I/O
O
I/O
I/O
I/O
O
PWM1 output/capture input.
EBI address/data bus bit 2.
General purpose digital I/O pin.
Request to Send output pin for UART1.
Data receiver input pin for UART1.
CAN bus transmitter input.
SmartCard data pin.
81
PA.1
UART1_nRTS
UART1_RXD
CAN0_TXD
SC0_DAT
PWM1_CH4
EBI_AD1
I
I
I/O
I/O
I/O
I/O
I
PWM1 output/capture input.
EBI address/data bus bit 1.
General purpose digital I/O pin.
Clear to Send input pin for UART1.
Data transmitter output pin for UART1.
CAN bus receiver input.
82
PA.0
UART1_nCTS
UART1_TXD
CAN0_RXD
SC0_CLK
PWM1_CH5
EBI_AD0
O
I
O
SmartCard clock pin.
I/O
I/O
I
PWM1 output/capture input.
EBI address/data bus bit 0.
External interrupt0 input pin.
General purpose digital I/O pin.
I2S1 master clock output pin.
CAN bus transmitter input.
General purpose digital I/O pin.
CAN bus receiver input.
INT0
83
PA.12
I/O
O
SPI1_I2SMCLK
CAN0_TXD
PA.13
I
84
85
I/O
I
CAN0_RXD
PA.14
I/O
I
General purpose digital I/O pin.
Clear to Send input pin for UART2.
I2C0 SMBus SMBALTER# pin
UART2_nCTS
I2C0_SMBAL
O
Jan. 06, 2016
Page 48 of 144
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M4TK
Pin No.
Pin Name
PA.15
Type
I/O
O
MFP*
MFP0
MFP3
MFP4
MFP0
MFP0
Description
86
General purpose digital I/O pin.
Request to Send output pin for UART2.
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
Ground pin for digital circuit.
UART2_nRTS
I2C0_SMBSUS
VSS
O
87
88
A
VDD
A
Power supply for I/O ports and LDO source for internal
PLL and digital function.
89
90
AVDD
VREF
A
I
MFP0
MFP0
Power supply for internal analog circuit.
Voltage reference input for ADC.
Note: This pin needs to be connected with a 1uF
capacitor.
91
PB.0
I/O
A
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP8
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP6
MFP7
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP0
MFP1
MFP2
MFP3
General purpose digital I/O pin.
EADC analog input.
EADC_CH0
SPI0_MOSI1
UART2_RXD
T2
I/O
I
SPI0 2nd MOSI (Master Out, Slave In) pin.
Data receiver input pin for UART2.
Timer2 event counter input / toggle output
DAC analog output
I/O
A
DAC
EBI_nWRL
INT1
O
EBI low byte write enable output pin.
External interrupt1 input pin.
I
92
PB.1
I/O
A
General purpose digital I/O pin.
EADC analog input channel 1.
SPI0 2nd MISO (Master In, Slave Out) pin.
Data transmitter output pin for UART2.
Timer3 event counter input / toggle output
SmartCard reset pin.
EADC_CH1
SPI0_MISO1
UART2_TXD
T3
I/O
O
I/O
O
SC0_RST
PWM0_SYNC_OUT
EBI_nWRH
PB.2
O
PWM0 counter synchronous trigger output pin.
EBI high byte write enable output pin
General purpose digital I/O pin.
EADC analog input channel 2.
SPI0 serial clock pin.
O
93
I/O
A
EADC_CH2
SPI0_CLK
SPI1_CLK
UART1_RXD
SC0_CD
I/O
I/O
I
SPI1 serial clock pin
Data receiver input pin for UART1.
SmartCard card detect pin.
I
94
PB.3
I/O
A
General purpose digital I/O pin.
EADC analog input channel 3.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
EADC_CH3
SPI0_MISO0
SPI1_MISO
I/O
I/O
Jan. 06, 2016
Page 49 of 144
Rev.1.00
M4TK
Pin No.
Pin Name
UART1_TXD
PB.4
Type
O
MFP*
MFP4
MFP0
MFP1
MFP2
MFP3
MFP4
MFP5
MFP7
MFP0
MFP1
MFP4
MFP6
MFP0
MFP1
MFP0
MFP1
MFP0
MFP1
MFP4
MFP0
MFP1
MFP4
Description
Data transmitter output pin for UART1.
General purpose digital I/O pin.
EADC analog input channel 4.
SPI0 slave select pin.
95
I/O
A
EADC_CH4
SPI0_SS
SPI1_SS
UART1_nCTS
ACMP0_N
EBI_AD7
PB.8
I/O
I/O
I
SPI1 slave select pin
Clear to Send input pin for UART1.
Comparator0 negative input pin.
EBI address/data bus bit 7.
General purpose digital I/O pin.
EADC analog input channel 5.
Request to Send output pin for UART1.
PWM0 output/capture input.
General purpose digital I/O pin.
EADC analog input channel 6.
General purpose digital I/O pin.
EADC analog input channel 7.
General purpose digital I/O pin.
EADC analog input channel 8.
Touch Key0.
A
I/O
I/O
A
96
EADC_CH5
UART1_nRTS
PWM0_CH2
PB.9
O
I/O
I/O
A
97
98
99
EADC_CH6
PB.10
I/O
A
EADC_CH7
PB.11
I/O
A
EADC_CH8
TK0
A
100
PB.12
I/O
A
General purpose digital I/O pin.
EADC analog input channel 9.
Touch Key1.
EADC_CH9
TK1
A
Jan. 06, 2016
Page 50 of 144
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M4TK
4.3.4
GPIO Multi-function Pin Summary
MFP* = Multi-function pin. (Refer to section SYS_GPx_MFPL and SYS_GPx_MFPH)
PA.0 MFP0 means SYS_GPA_MFPL[3:0]=0x0.
PA.9 MFP5 means SYS_GPA_MFPH[7:4]=0x5.
Group
Pin Name
MFP*
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
MFP1
Type
A
O
O
A
A
A
A
A
O
O
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
I
Description
ACMP0_N
Comparator0 negative input pin.
Comparator0 output.
ACMP0_O
ACMP0_O
ACMP0_P0
ACMP0_P1
ACMP0_P2
ACMP0_P3
ACMP1_N
Comparator0 output.
ACMP0
Comparator0 positive input pin.
Comparator0 positive input pin.
Comparator0 positive input pin.
Comparator0 positive input pin.
Comparator1 negative input pin.
Comparator1 output .
ACMP1_O
ACMP1_O
ACMP1_P0
ACMP1_P1
ACMP1_P2
ACMP1_P3
EADC_CH0
EADC_CH1
EADC_CH2
EADC_CH3
EADC_CH4
EADC_CH5
EADC_CH6
EADC_CH7
EADC_CH8
EADC_CH9
EADC_CH10
EADC_CH11
EADC_CH12
EADC_CH13
EADC_CH14
EADC_CH15
STADC
Comparator1 output .
ACMP1
Comparator1 positive input pin.
Comparator1 positive input pin.
Comparator1 positive input pin.
Comparator1 positive input pin.
ADC0 analog input.
ADC1 analog input.
ADC2 analog input.
ADC3 analog input.
ADC4 analog input.
ADC5 analog input.
ADC6 analog input.
ADC7 analog input.
EADC
ADC8 analog input.
ADC9 analog input.
ADC10 analog input.
ADC11 analog input.
ADC12 analog input.
ADC13 analog input.
ADC14 analog input.
ADC15 analog input.
ADC external trigger input.
Jan. 06, 2016
Page 51 of 144
Rev.1.00
M4TK
Group
Pin Name
CAN0_RXD
CAN0_RXD
CAN0_RXD
CAN0_TXD
CAN0_TXD
CAN0_TXD
CLKO
MFP*
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP1
MFP1
MFP1
MFP5
MFP2
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
Type
I
Description
CAN bus receiver input.
CAN bus receiver input.
CAN bus receiver input.
CAN bus transmitter input.
CAN bus transmitter input.
CAN bus transmitter input.
Clock Out
I
I
CAN0
I
I
I
O
CLKO
DAC
CLKO
O
Clock Out
CLKO
O
Clock Out
DAC
A
DAC analog output
STDAC
I
DAC external trigger input.
EBI address/data bus bit 0.
EBI address/data bus bit 1.
EBI address/data bus bit 2.
EBI address/data bus bit 3.
EBI address/data bus bit 4.
EBI address/data bus bit 4.
EBI address/data bus bit 5.
EBI address/data bus bit 5.
EBI address/data bus bit 6.
EBI address/data bus bit 6.
EBI address/data bus bit 7.
EBI address/data bus bit 7.
EBI address/data bus bit 8.
EBI address/data bus bit 9.
EBI address/data bus bit 10.
EBI address/data bus bit 11.
EBI address/data bus bit 12.
EBI address/data bus bit 13.
EBI address/data bus bit 14.
EBI address/data bus bit 15.
EBI address bus bit 16.
EBI address bus bit 17.
EBI address bus bit 18.
EBI_AD0
EBI_AD1
EBI_AD2
EBI_AD3
EBI_AD4
EBI_AD4
EBI_AD5
EBI_AD5
EBI_AD6
EBI_AD6
EBI_AD7
EBI_AD7
EBI_AD8
EBI_AD9
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
EBI_AD14
EBI_AD15
EBI_ADR16
EBI_ADR17
EBI_ADR18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
EBI
O
O
Jan. 06, 2016
Page 52 of 144
Rev.1.00
M4TK
Group
Pin Name
EBI_ADR19
EBI_ALE
MFP*
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP7
MFP3
MFP4
MFP4
MFP3
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP3
MFP3
MFP3
MFP4
MFP3
MFP3
MFP3
MFP4
MFP3
MFP3
Type
O
Description
EBI address bus bit 19.
O
EBI address latch enable output pin.
EBI address latch enable output pin.
EBI external clock output pin
EBI chip select 0 enable output pin.
EBI chip select 0 enable output pin.
EBI chip select 1 enable output pin.
EBI chip select 1 enable output pin.
EBI read enable output pin.
EBI read enable output pin.
EBI write enable output pin.
EBI write enable output pin.
EBI high byte write enable output pin
EBI low byte write enable output pin.
I2C0 clock pin.
EBI_ALE
O
EBI_MCLK
EBI_nCS0
EBI_nCS0
EBI_nCS1
EBI_nCS1
EBI_nRD
O
O
O
O
O
O
EBI_nRD
O
EBI_nWR
O
EBI_nWR
O
EBI_nWRH
EBI_nWRL
I2C0_SCL
I2C0_SCL
I2C0_SCL
I2C0_SDA
I2C0_SDA
I2C0_SDA
I2C0_SMBAL
I2C0_SMBAL
I2C0_SMBSUS
I2C0_SMBSUS
I2C1_SCL
I2C1_SCL
I2C1_SCL
I2C1_SCL
I2C1_SDA
I2C1_SDA
I2C1_SDA
I2C1_SDA
I2C1_SMBAL
I2C1_SMBSUS
O
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I2C0 clock pin.
I2C0 clock pin.
I2C0 data input/output pin.
I2C0 data input/output pin.
I2C0 data input/output pin.
I2C0 SMBus SMBALTER# pin
I2C0 SMBus SMBALTER# pin
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
I2C1 clock pin.
I2C0
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I2C1 clock pin.
I2C1 clock pin.
I2C1 clock pin.
I2C1 data input/output pin.
I2C1 data input/output pin.
I2C1 data input/output pin.
I2C1 data input/output pin.
I2C1 SMBus SMBALTER# pin
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
I2C1
O
Jan. 06, 2016
Page 53 of 144
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M4TK
Group
Pin Name
SPI1_I2SMCLK
SPI1_I2SMCLK
SPI2_I2SMCLK
SPI2_I2SMCLK
ICE_CLK
MFP*
MFP2
MFP2
MFP2
MFP2
MFP1
MFP1
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP8
MFP6
MFP5
MFP6
MFP5
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP2
MFP3
Type
Description
O
I2S1 master clock output pin.
I2S1 master clock output pin.
I2S2 master clock output pin.
I2S2 master clock output pin.
Serial wired debugger clock pin
Serial wired debugger data pin
External interrupt0 input pin.
External interrupt0 input pin.
External interrupt0 input pin.
External interrupt1 input pin.
External interrupt1 input pin.
External interrupt1 input pin.
External interrupt2 input pin.
External interrupt3 input pin.
External interrupt4 input pin.
External interrupt5 input pin.
PWM0 break input 0
I2S1
O
O
I2S2
ICE
O
I
ICE_DAT
I/O
INT0
I
INT0
INT1
INT0
I
INT0
I
INT1
I
I
INT1
INT1
I
INT2
INT3
INT4
INT5
INT2
I
INT3
I
INT4
I
INT5
I
PWM0_BRAKE0
PWM0_BRAKE0
PWM0_BRAKE1
PWM0_BRAKE1
PWM0_CH0
PWM0_CH0
PWM0_CH1
PWM0_CH1
PWM0_CH2
PWM0_CH2
PWM0_CH3
PWM0_CH3
PWM0_CH4
PWM0_CH5
PWM0_CH5
PWM0_CH5
PWM0_SYNC_IN
PWM0_SYNC_IN
I
I
PWM0 break input 0
I
PWM0 break input 1
I
PWM0 break input 1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 output/capture input.
PWM0 counter synchronous trigger input pin.
PWM0 counter synchronous trigger input pin.
PWM0
I
Jan. 06, 2016
Page 54 of 144
Rev.1.00
M4TK
Group
Pin Name
MFP*
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP6
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
MFP5
Type
O
Description
PWM0_SYNC_OUT
PWM1_BRAKE0
PWM1_BRAKE1
PWM1_CH0
PWM1_CH0
PWM1_CH0
PWM1_CH0
PWM1_CH1
PWM1_CH1
PWM1_CH1
PWM1_CH1
PWM1_CH2
PWM1_CH2
PWM1_CH2
PWM1_CH3
PWM1_CH3
PWM1_CH3
PWM1_CH4
PWM1_CH4
PWM1_CH5
PWM1_CH5
SC0_CD
PWM0 counter synchronous trigger output pin.
PWM1 break input 0
I
I
PWM1 break input 1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
PWM1 output/capture input.
SmartCard card detect pin.
SmartCard card detect pin.
SmartCard card detect pin.
SmartCard clock pin.
PWM1
SC0_CD
I
SC0_CD
I
SC0_CLK
O
SC0_CLK
O
SmartCard clock pin.
SC0_DAT
I/O
I/O
O
SmartCard data pin.
SC0
SC0_DAT
SmartCard data pin.
SC0_PWR
SmartCard power pin.
SC0_PWR
O
SmartCard power pin.
SC0_PWR
O
SmartCard power pin.
SC0_RST
O
SmartCard reset pin.
SC0_RST
O
SmartCard reset pin.
SC0_RST
O
SmartCard reset pin.
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Group
Pin Name
SC0_RST
MFP*
MFP5
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP3
MFP2
MFP2
MFP1
MFP3
MFP3
MFP2
MFP2
MFP1
MFP3
MFP3
MFP2
MFP2
MFP1
MFP2
MFP2
MFP1
MFP3
MFP2
Type
O
Description
SmartCard reset pin.
SPI0_CLK
SPI0_CLK
SPI0_CLK
SPI0_MISO0
SPI0_MISO0
SPI0_MISO0
SPI0_MISO1
SPI0_MISO1
SPI0_MOSI0
SPI0_MOSI0
SPI0_MOSI1
SPI0_MOSI1
SPI0_SS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SPI0 serial clock pin.
SPI0 serial clock pin.
SPI0 serial clock pin.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0 1st MISO (Master In, Slave Out) pin.
SPI0 2nd MISO (Master In, Slave Out) pin.
SPI0 2nd MISO (Master In, Slave Out) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0 1st MOSI (Master Out, Slave In) pin.
SPI0 2nd MOSI (Master Out, Slave In) pin.
SPI0 2nd MOSI (Master Out, Slave In) pin.
SPI0 slave select pin.
SPI0
SPI0_SS
SPI0 slave select pin.
SPI1_CLK
SPI1_CLK
SPI1_CLK
SPI1_CLK
SPI1_CLK
SPI1_MISO
SPI1_MISO
SPI1_MISO
SPI1_MISO
SPI1_MISO
SPI1_MOSI
SPI1_MOSI
SPI1_MOSI
SPI1_MOSI
SPI1_SS
SPI1 serial clock pin
SPI1 serial clock pin
SPI1 serial clock pin
SPI1 serial clock pin
SPI1 serial clock pin
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MISO (Master In, Slave Out) pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 slave select pin
SPI1
SPI1_SS
SPI1 slave select pin
SPI1_SS
SPI1 slave select pin
SPI1_SS
SPI1 slave select pin
SPI2
SPI2_CLK
SPI2 serial clock pin.
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Group
Pin Name
SPI2_CLK
SPI2_CLK
SPI2_CLK
SPI2_MISO
SPI2_MISO
SPI2_MISO
SPI2_MOSI
SPI2_MOSI
SPI2_MOSI
SPI2_SS
SPI2_SS
SPI2_SS
TAMPER
TK0
MFP*
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP2
MFP1
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP4
MFP6
MFP6
MFP3
MFP3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Description
SPI2 serial clock pin.
SPI2 serial clock pin.
SPI2 serial clock pin.
SPI2 MISO (Master In, Slave Out) pin.
SPI2 MISO (Master In, Slave Out) pin.
SPI2 MISO (Master In, Slave Out) pin.
SPI2 MOSI (Master Out, Slave In) pin.
SPI2 MOSI (Master Out, Slave In) pin.
SPI2 MOSI (Master Out, Slave In) pin.
SPI2 slave select pin.
SPI2 slave select pin.
SPI2 slave select pin.
TAMPER detector loop pin
Touch Key0
I
I
TAMPER
I/O
A
TK1
A
Touch Key1
TK2
A
Touch Key2
TK3
A
Touch Key3
TK4
A
Touch Key4
TK5
A
Touch Key5
TK6
A
Touch Key6
TK7
A
Touch Key7
TK
TK8
A
Touch Key0
TK9
A
Touch Key8
TK10
A
Touch Key10
TK11
A
Touch Key11
TK12
A
Touch Key12
TK13
A
Touch Key13
TK14
A
Touch Key14
TK15
A
Touch Key15
TK16
A
Touch Key16
T0
I/O
I/O
I
Timer0event counter input / toggle output
Timer0event counter input / toggle output
Timer0 external capture input
Timer0 external capture input
T0
TMR0
T0_EXT
T0_EXT
I
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Group
Pin Name
T1
MFP*
MFP6
MFP4
MFP3
MFP3
MFP1
MFP4
MFP4
MFP4
MFP3
MFP4
MFP4
MFP3
MFP3
MFP3
MFP3
MFP2
MFP3
MFP2
MFP3
MFP3
MFP1
MFP3
MFP3
MFP4
MFP1
MFP3
MFP3
MFP4
MFP3
MFP1
MFP4
MFP3
MFP1
MFP4
Type
Description
I/O
I/O
I
Timer1 event counter input / toggle output
Timer1 event counter input / toggle output
Timer1 external capture input
T1
TMR1
T1_EXT
T1_EXT
I
Timer1 external capture input
T2
I/O
I/O
I/O
I
Timer2 event counter input / toggle output
Timer2 event counter input / toggle output
Timer2 event counter input / toggle output
Timer2 external capture input
T2
TMR2
T2
T2_EXT
T2_EXT
I
Timer2 external capture input
T3
I/O
I/O
I
Timer3 event counter input / toggle output
Timer3 event counter input / toggle output
Timer3 external capture input
T3
TMR3
T3_EXT
T3_EXT
I
Timer3 external capture input
UART0_RXD
UART0_RXD
UART0_RXD
UART0_TXD
UART0_TXD
UART0_nCTS
UART0_nRTS
UART1_RXD
UART1_RXD
UART1_RXD
UART1_RXD
UART1_TXD
UART1_TXD
UART1_TXD
UART1_TXD
UART1_nCTS
UART1_nCTS
UART1_nCTS
UART1_nRTS
UART1_nRTS
UART1_nRTS
I
Data receiver input pin for UART0.
Data receiver input pin for UART0.
Data receiver input pin for UART0.
Data transmitter output pin for UART0.
Data transmitter output pin for UART0.
Clear to Send input pin for UART0.
Request to Send output pin for UART0.
Data receiver input pin for UART1.
Data receiver input pin for UART1.
Data receiver input pin for UART1.
Data receiver input pin for UART1.
Data transmitter output pin for UART1.
Data transmitter output pin for UART1.
Data transmitter output pin for UART1.
Data transmitter output pin for UART1.
Clear to Send input pin for UART1.
Clear to Send input pin for UART1.
Clear to Send input pin for UART1.
Request to Send output pin for UART1.
Request to Send output pin for UART1.
Request to Send output pin for UART1.
I
I
UART0
O
O
I
O
I
I
I
I
O
O
O
O
I
UART1
I
I
O
O
O
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Group
Pin Name
MFP*
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP3
MFP4
MFP1
MFP4
MFP1
MFP1
MFP1
MFP1
MFP1
Type
Description
UART2_RXD
UART2_RXD
UART2_TXD
UART2_TXD
UART2_nCTS
UART2_nCTS
UART2_nRTS
UART2_nRTS
UART3_RXD
UART3_RXD
UART3_TXD
UART3_TXD
UART3_nCTS
UART3_nCTS
UART3_nRTS
UART3_nRTS
USB_VBUS_EN
USB_VBUS_EN
USB_VBUS_ST
USB_VBUS_ST
X32_IN
I
I
Data receiver input pin for UART2.
Data receiver input pin for UART2.
O
O
I
Data transmitter output pin for UART2.
Data transmitter output pin for UART2.
Clear to Send input pin for UART2.
UART2
I
Clear to Send input pin for UART2.
O
O
I
Request to Send output pin for UART2.
Request to Send output pin for UART2.
Data receiver input pin for UART3.
I
Data receiver input pin for UART3.
O
O
I
Data transmitter output pin for UART3.
Data transmitter output pin for UART3.
Clear to Send input pin for UART3.
UART3
I
Clear to Send input pin for UART3.
O
O
O
O
I
Request to Send output pin for UART3.
Request to Send output pin for UART3.
USB external VBUS regulator enable pin.
USB external VBUS regulator enable pin.
USB external VBUS regulator status pin.
USB external VBUS regulator status pin.
External 32.768 kHZ (low speed) crystal input pin.
External 32.768 kHZ (low speed) crystal output pin.
External 4~20 MHz (high speed) crystal input pin.
External 4~20 MHz (high speed) crystal output pin.
USB
I
I
LXT
HXT
X32_OUT
O
I
XT1_IN
XT1_OUT
O
Table 4-1 M4TK GPIO Multi-function Table
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5 BLOCK DIAGRAM
5.1 NuMicro® M4TK Block Diagram
Figure 5.1-1 NuMicro® M4TK Block Diagram
Jan. 06, 2016
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6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex® -M4 Core
The Cortex® -M4 processor, a configurable, multistage, 32-bit RISC processor, has three AMBA
AHB-Lite interfaces for best parallel performance and includes an NVIC component. The
processor with optional hardware debug functionality can execute Thumb code and is compatible
with other Cortex-M profile processors. The profile supports two modes -Thread mode and
Handler mode. Handler mode is entered as a result of an exception. An exception return can only
be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of
an exception return. The Cortex® -M4F is a processor with the same capability as the Cortex® -M4
processor and includes floating point arithmetic functionality. The NuMicro® M4TK family is
embedded with Cortex® -M4F processor. Throughout this document, the name Cortex® -M4 refers
to both Cortex® -M4 and Cortex® -M4F processors. The Figure 6.1-1 shows the functional controller
of the processor.
Figure 6.1-1 Cortex® -M4 Block Diagram
Cortex® -M4 processor features:
A low gate count processor core, with low latency interrupt processing that has:
A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual
Banked Stack Pointer (SP)
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Hardware integer divide instructions, SDIV and UDIV
Handler and Thread modes
Thumb and Debug states
Support for interruptible-continued instructions LDM, STM, PUSH, and POP for
low interrupt latency
Automatic processor state saving and restoration for low latency Interrupt
Service Routine (ISR) entry and exit
Support for ARMv6 big-endian byte-invariant or little-endian accesses
Support for ARMv6 unaligned accesses
Floating Point Unit (FPU) in the Cortex® -M4F processor providing:
32-bit instructions for single-precision (C float) data-processing operations
Combined Multiply and Accumulate instructions for increased precision (Fused
MAC)
Hardware support for conversion, addition, subtraction, multiplication with
optional accumulate, division, and square-root
Hardware support for denormals and all IEEE rounding modes
32 dedicated 32-bit single precision registers, also addressable as 16 double-
word registers
Decoupled three stage pipeline
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core
to achieve low latency interrupt processing. Features include:
External interrupts. Configurable from 1 to 240 (the NuMicro® M4TK family
configured with 64 interrupts)
Bits of priority, configurable from 3 to 8
Dynamic reprioritization of interrupts
Priority grouping which enables selection of preempting interrupt levels and
nonpreempting interrupt levels
Support for tril-chaining and late arrival of interrupts, which enables back-to-back
interrupt processing without the overhead of state saving and restoration
between interrupts.
Processor state automatically saved on interrupt entry, and restored on interrupt
exit with on instruction overhead
Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
Memory Protection Unit (MPU). An optional MPU for memory protection, including:
Eight memory regions
Sub Region Disable (SRD), enabling efficient use of memory regions
The ability to enable a background region that implements the default memory
map attributes
Low-cost debug solution that features:
Debug access to all memory and registers in the system, including access to
memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is
Jan. 06, 2016
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asserted.
Serial Wire Debug Port(SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP)
debug access
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
and code patches
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,
data tracing, and system profiling
Optional Instrumentation Trace Macrocell (ITM) for support of printf() style
debugging
Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
(TPA), including Single Wire Output (SWO) mode
Optional Embedded Trace Macrocell (ETM) for instruction trace.
Bus interfaces:
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode,
Dcode, and System bus interfaces
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB)
interface
Bit-band support that includes atomic bit-band write and read operations.
Memory access alignment
Write buffer for buffering of write data
Exclusive access transfers for multiprocessor systems
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6.2 System Manager
6.2.1 Overview
The system manager provides the functions of system control, power modes, wake-up sources,
reset sources, system memory map, product ID and multi-function pin control. The following
sections describe the functions for
System Reset
Power Modes and Wake-up Sources
System Power Distribution
SRAM Memory Organization
System Control Register for Part Number ID, Chip Reset and Multi-function Pin
Control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control register
6.2.2
System Reset
The system reset can be issued by one of the events listed below. These reset event flags can be
read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip
through peripheral reset signals. Software reset can trigger reset through control registers.
Hardware Reset Sources
–
–
–
–
–
Power-on Reset (POR)
Low level on the nRESET pin
Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
Low Voltage Reset (LVR)
Brown-out Detector Reset (BOD Reset)
Software Reset Sources
–
–
CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])
MCU Reset to reboot but keeping the booting setting from APROM or LDROM by
writing 1 to SYSRESETREQ (AIRCR[2])
–
CPU Reset for Cortex® -M4 core Only by writing 1 to CPURST (SYS_IPRST0[1])
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Glitch Filter
36 us
nRESET
~50k ohm
@5v
POROFF(SYS_PORCTL[15:0])
Power-on
Reset
VDD
LVREN(SYS_BODCTL[7])
Reset Pulse Width
3.2ms
Low Voltage
Reset
AVDD
BODRSTEN(SYS_BODCTL[3])
Brown-out
Reset
WDT/WWDT
Reset
System Reset
Reset Pulse Width
64 WDT clocks
Reset Controller
CPU Lockup
Reset
Reset Pulse Width
2 system clocks
CHIP Reset
CHIPRST(SYS_IPRST0[0])
MCU Reset
SYSRSTREQ(AIRCR[2])
Reset Pulse Width
2 system clocks
Software Reset
CPU Reset
CPURST(SYS_IPRST0[1])
Figure 6.2-1 System Reset Sources
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There are a total of 9 reset sources in the NuMicro® family. In general, CPU reset is used to reset
Cortex-M4 only; the other reset sources will reset Cortex-M4 and all peripherals. However, there
are small differences between each reset source and they are listed in Table 6-1.
Reset Sources
POR
0x001
NRESET
WDT
LVR
BOD
Lockup
CHIP
MCU
CPU
Register
SYS_RSTSTS
Bit 1 = 1
Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1
Bit 5 = 1 Bit 7 =
1
CHIPRST
0x0
-
-
-
-
-
-
-
-
-
(SYS_IPRST0[0])
BODEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
(SYS_BODCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0
CONFIG0 CONFIG0 CONFIG0
BODVL
(SYS_BODCTL[2:1])
BODRSTEN
(SYS_BODCTL[3])
HXTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_PWRCTL[0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
LXTEN
0x0
0x1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_PWRCTL[1])
WDTCKEN
0x1
0x1
(CLK_APBCLK0[0])
HCLKSEL
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
(CLK_CLKSEL0[2:0])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTSEL
0x3
0x0
0x0
0x0
0x0
0x0
0x3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(CLK_CLKSEL1[1:0])
HXTSTB
-
(CLK_STATUS[0])
LXTSTB
-
(CLK_STATUS[1])
PLLSTB
-
(CLK_STATUS[2])
HIRCSTB
-
(CLK_STATUS[4])
CLKSFAIL
0x0
(CLK_STATUS[7])
RSTEN
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(WDT_CTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
WDTEN
(WDT_CTL[7])
WDT_CTL
0x0700
0x0700
0x0700
0x0700
0x0700
-
0x0700
-
-
except bit 1 and bit 7.
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WDT_ALTCTL
WWDT_RLDCNT
WWDT_CTL
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
-
-
0x0000
0x0000
0x3F0800
0x0000
0x3F
-
-
-
-
-
-
-
-
-
-
-
-
0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 -
WWDT_STATUS
WWDT_CNT
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
0x0000
0x3F
-
-
-
BS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPCTL[1])
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
BL
(FMC_ISPCTL[16])
FMC_DFBA
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
-
-
Reload
from
CONFIG1
-
-
-
-
CONFIG1 CONFIG1 CONFIG1 CONFIG1 CONFIG1
CBS
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
Reload
from
CONFIG0
(FMC_ISPSTS[2:1))
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
MBS
(FMC_ISPSTS[3])
PGFF
0x0
-
0x0
-
-
-
-
0x0
-
-
-
-
(FMC_ISPSTS[5])
VECMAP
Reload
base
Reload
on base
Reload
Reload
Reload
Reload
base
CONFIG0
on base on base on base on
on
(FMC_ISPSTS[23:
CONFIG0 CONFIG0 CONFIG0 CONFIG0 CONFIG0
Peripheral
Reset Value
9])
Other
-
Registers
FMC Registers
Reset Value
Note: ‘-‘ means that the value of register keeps original setting.
Table 6-1 Reset Value of Registers
6.2.2.1 nRESET Reset
The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an
asynchronous reset input pin and can be used to reset system at any time. When the nRESET
voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be
reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above
0.7 VDD and the state keeps longer than 36 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be
set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset
waveform.
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nRESET
0.7 VDD
0.2 VDD
36 us
36 us
nRESET
Reset
Figure 6.2-2 nRESET Reset Waveform
6.2.2.2 Power-on Reset (POR)
The Power-on reset (POR) is used to generate a stable system reset signal and forces the
system to be reset when power-on to avoid unexpected behavior of MCU. When applying the
power to MCU, the POR module will detect the rising voltage and generate reset signal to system
until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be
set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by
writing 1 to it. Figure 6.2-3 shows the power-on reset waveform.
VPOR
0.1V
VDD
Power-on
Reset
Figure 6.2-3 Power-on Reset (POR) Waveform
6.2.2.3 Low Voltage Reset (LVR)
If the Low Voltage Reset function is enabled by setting the Low Voltage Reset Enable Bit LVREN
(SYS_BODCTL[7]) to 1, after 200us delay, LVR detection circuit will be stable and the LVR
function will be active. Then LVR function will detect AVDD during system operation. When the
AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time set by LVRDGSEL
(SYS_BODCTL[14:12]), chip will be reset. The LVR reset will control the chip in reset state until
the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time set by
LVRDGSEL (SYS_BODCTL[14:12]). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the previous
reset source is nRESET reset. The default setting of Low Voltage Reset is enabled without De-
glitch function. Figure 6.2-4 shows the Low Voltage Reset waveform.
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AVDD
VLVR
T1
T2
( < LVRDGSEL)
( =LVRDGSEL)
T3
( =LVRDGSEL)
Low Voltage Reset
LVREN
200 us
Delay for LVR stable
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
6.2.2.4 Brown-out Detector Reset (BOD Reset)
If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit
BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AVDD during system
operation. When the AVDD voltage is lower than VBOD and the state keeps longer than De-glitch
time set by BODDGSEL (SYS_BODCTL[10:8]), chip will be reset. The BOD reset will control the
chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De-
glitch time set by BODDGSEL (SYS_BODCTL[10:8]). The default value of BODEN, BODVL and
BODRSTEN is set by flash controller user configuration register CBODEN (CONFIG0 [23]),
CBOV (CONFIG0 [22:21]) and CBORST(CONFIG0[20]) respectively. User can determine the
initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-Out Detector
waveform.
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AVDD
VBODH
VBODL
Hysteresis
T1
T2
(< BODDGSEL)
(= BODDGSEL)
BODOUT
T3
(= BODDGSEL)
BODRSTEN
Brown-out
Reset
Figure 6.2-5 Brown-out Detector (BOD) Waveform
6.2.2.5 Watchdog Timer Reset (WDT)
In most industrial applications, system reliability is very important. To automatically recover the
MCU from failure status is one way to improve system reliability. The watchdog timer(WDT) is
widely used to check if the system works fine. If the MCU is crashed or out of control, it may
cause the watchdog time-out. User may decide to enable system reset during watchdog time-out
to recover the system and take action for the system crash/out-of-control after reset.
Software can check if the reset is caused by watchdog time-out to indicate the previous reset is a
watchdog reset and handle the failure of MCU after watchdog time-out reset by checking
WDTRF(SYS_RSTSTS[2]).
6.2.2.6 CPU Reset, CHIP Reset and MCU Reset
The CPU Reset means only Cortex® -M4 core is reset and all other peripherals remain the same
status after CPU reset. User can set the CPURST(SYS_IPRST0[1]) to 1 to assert the CPU Reset
signal.
The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and
BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG setting. User can set the
CHIPRST(SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal.
The MCU Reset is similar with CHIP Reset. The difference is that BS(FMC_ISPCTL[1]) will not be
reloaded from CONFIG setting and keep its original software setting for booting from APROM or
LDROM. User can set the SYSRESETREQ(AIRCR[2]) to 1 to assert the MCU Reset.
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6.2.3
Power Modes and Wake-up Sources
There are several wake-up sources in Idle mode and Power-down mode. Table 6-2 lists the
available clocks for each power mode.
Power Mode
Definition
Normal Mode
Idle Mode
Power-Down Mode
CPU is in active state
CPU is in sleep state
CPU is in sleep state and all
clocks stop except LXT and
LIRC. SRAM content retended.
Entry Condition
Chip is in normal mode after CPU executes WFI instruction. CPU sets sleep mode enable
system reset released
and power down enable and
executes WFI instruction.
Wake-up Sources
N/A
All interrupts
RTC, WDT, I²C, Timer, UART,
BOD, GPIO, USBH, USBD,
OTG, CAN, ACMP and TK
Available Clocks
After Wake-up
All
All except CPU clock
LXT and LIRC
N/A
CPU back to normal mode
CPU back to normal mode
Table 6-2 Power Mode Difference Table
System reset released
Normal Mode
CPU Clock ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
CPU executes WFI
Interrupts occur
1. SCR(SCB[2]) = 1
Wake-up events
occur
2. PD_EN(PWRCTL[7]) = 1 and
PDWTCPU(PWRCTL[8]) = 1
3. CPU executes WFI
Idle Mode
Power-down Mode
CPU Clock OFF
CPU Clock OFF
HXT, HIRC, HCLK, PCLK OFF
LXT, LIRC ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash Halt
Flash Halt
Figure 6.2-6 Power Mode State Machine
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1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode.
2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If RTC clock source is selected as LXT and LXT is on.
Normal Mode
ON
Idle Mode
Power-Down Mode
Halt
HXT (4~20 MHz XTL)
ON
ON
ON
ON
ON
ON
Halt
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
HIRC (12/16 MHz OSC)
ON
Halt
LXT (32768 Hz XTL)
ON
ON/OFF1
ON/OFF2
Halt
LIRC (10 kHz OSC)
PLL
ON
ON
LDO
ON
ON
CPU
ON
Halt
HCLK/PCLK
SRAM retention
FLASH
EBI
ON
Halt
ON
ON
ON
Halt
ON
Halt
GPIO
ON
Halt
PDMA
TIMER
PWM
ON
Halt
ON
ON/OFF3
Halt
ON
WDT
ON
ON/OFF4
Halt
WWDT
RTC
ON
ON
ON/OFF5
Halt
UART
SC
ON
ON
Halt
I2C
ON
Halt
SPI
ON
Halt
USBH
USBG
OTG
ON
Halt
ON
Halt
ON
Halt
CAN
ON
Halt
TK
ON
Halt
EADC
DAC
ON
Halt
ON
Halt
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ACMP
ON
ON
Halt
Table 6-3 Clocks in Power Modes
Wake-up sources in Power-down mode:
RTC, WDT, I²C, Timer, UART, BOD, GPIO, USBH, USBD, OTG, CAN, ACMP and TK
After chip enters power down, the following wake-up sources can wake chip up to normal mode.
Table 6-4 lists the condition about how to enter Power-down mode again for each peripheral.
*User needs to wait this condition before setting PD_EN(PWRCTL[6]) and execute WFI to enter
Power-down mode.
Wake-Up
Wake-Up Condition
System Can Enter Power-Down Mode Again Condition*
Source
BOD
Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF].
GPIO
GPIO Interrupt
Timer Interrupt
After software write 1 to clear the INTSRC[n] bit.
TIMER
After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF
(TIMERx_INTSTS[0]).
WDT
RTC
WDT Interrupt
Alarm Interrupt
After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).
After software writes 1 to clear ALMIF (RTC_INTSTS[0]).
After software writes 1 to clear TICKIF (RTC_INTSTS[1]).
Time Tick Interrupt
Snoop Detection Interrupt After software writes 1 to clear SNPDIF (RTC_INTSTS[2]).
UART
I2C
RX Data wake-up
nCTS wake-up
After software writes 1 to clear DATWKIF (UARTx_INTSTS[17]).
After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]).
Falling edge in the I2C_SDA
or I2C_CLK
After software writes 1 to clear WKIF( I2C_WKSTS[0]).
USBH
USBD
OTG
CAN
TK
Remote Wake-up
Remote Wake-up
After software writes 1 to clear CSC (HcRhPortStatus1[16]).
After software writes 1 to clear BUSIF (USBD_INTSTS[0]).
After software writes 1 to clear OTG_INTSTS[IDCHGIF].
OTG ID Pin Wake-Up
Falling edge in the CAN_RX After software writes 0 to clear WAKUP_STS (CAN_WU_STATUS [0]).
Wake-up by Key
Touch/Release or Any Key After software writes 1 to clear TK_STATUS[TKIFx].
Touch
ACMP
Comparator Power-Down
After software writes 1 to clear ACMP_STATUS[WKIFx].
Wake-Up Interrupt
Table 6-4 Condition of Entering Power-down Mode Again
6.2.4
System Power Distribution
In this chip, power distribution is divided into five segments:
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Analog power from AVDD and AVSS provides the power for analog components
operation. The VREF should be connected with an external 1uF capacitor that should
be located close to the VREF pin to avoid power noise for analog applications.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from VDD offers the power for operating the USB transceiver.
RTC power from VBAT provides the power for PF.0~PF.2, RTC and 80 bytes backup
registers.
A dedicated power from VDDIO supplies the power for PE.8~PE.13.
The outputs of internal voltage regulators, LDO_CAP and USB_VDD33_CAP, require an external
capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be
the same voltage level of the digital power (VDD). The Figure 6.2-7 shows the power distribution of
the NuMicro® M4TK.
Internal
Reference
Voltage
32.768 kHz
crystal
oscillator
USB_D+
USB_D-
USB
Transceiver
12-bit ADC
12-bit DAC
IO Cell
USB_VDD33_CAP
1uF
3.3V
AVDD
AVSS
Analog
Comparator
1.8V
RTC &
80 bytes
backup
register
Brown-
out
Detector
Low
Voltage
Reset
Touch
sensor
VBAT to 1.8V
LDO
5V to 3.3V
LDO
VDD
Temperature
Sensor
SRAM
Flash
Digital Logic
IO Cell
PE.8~PE.13
1.8V
LDO_CAP
1uF
22.1184 MHz
10 kHz
PLL
POR18
HIRC
LIRC
Oscillator
Oscillator
VDDIO
GPIO except
PF.0 ~PF.2 and
PE.8~PE.13
4~20 MHz
crystal
oscillator
XT1_OUT
XT1_IN
VDD to 1.8V
LDO
Power On
Control
POR50
IO Cell
M451 Power Distribution
Figure 6.2-7 NuMicro® M4TK Power Distribution Diagram
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6.2.5
System Memory Map
The NuMicro® M4TK series provides 4G-byte addressing space. The memory locations assigned to
each on-chip controllers are shown in theTable 6-5. The detailed register definition, memory space,
and programming will be described in the following sections for each on-chip peripheral. The NuMicro®
M4TK series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF
0x0000_0000 – 0x0003_FFFF
0x0004_0000 – 0x0005_FFFF
0x0006_0000 – 0x0007_FFFF
0x2000_0000 – 0x2000_3FFF
0x2000_4000 – 0x2000_7FFF
0x2000_8000 – 0x2000_BFFF
0x2000_C000 – 0x2000_FFFF
0x6000_0000 – 0x6FFF_FFFF
FLASH_BA
FLASH_BA
Reserved
FLASH Memory Space (128KB) (M4TKxE Only)
FLASH Memory Space (256KB) (M4TKxG Only)
Reserved
Reserved
Reserved
SRAM0_BA
SRAM1_BA
Reserved
SRAM Memory Space
SRAM Memory Space
Reserved
Reserved
Reserved
EXTMEM_BA
External Memory Space for EBI Interface (256 MB)
Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF)
0x4000_0000 – 0x4000_01FF
0x4000_0200 – 0x4000_02FF
0x4000_0300 – 0x4000_03FF
0x4000_4000 – 0x4000_4FFF
0x4000_8000 – 0x4000_8FFF
0x4000_9000 – 0x4000_9FFF
0x4000_B000 – 0x4000_BFFF
0x4000_C000 – 0x4000_CFFF
0x4000_D000 – 0x4000_DFFF
0x4001_0000 – 0x4001_0FFF
0x4001_9000 – 0x4001_9FFF
0x4003_0000 – 0x4003_0FFF
0x4003_1000 – 0x4003_1FFF
0x5000_8000 – 0x5000_FFFF
SYS_BA
CLK_BA
NMI_BA
System Control Registers
Clock Control Registers
NMI Control Registers
GPIO Control Registers
Peripheral DMA Control Registers
USB Host Control Registers
Reserved
GPIO_BA
PDMA_BA
USBH_BA
Reserved
FMC_BA
Reserved
EBI_BA
Flash Memory Control Registers
Reserved
External Bus Interface Control Registers
Reserved
Reserved
Reserved
CRC_BA
Reserved
Reserved
CRC Generator Registers
Reserved
APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
0x4004_0000 – 0x4004_0FFF
0x4004_1000 – 0x4004_1FFF
0x4004_3000 – 0x4004_3FFF
0x4004_4000 – 0x4004_4FFF
0x4004_5000 – 0x4004_5FFF
WDT_BA
Watchdog Timer Control Registers
Real Time Clock (RTC) Control Register
Enhanced Analog-Digital-Converter (EADC) Control Registers
Reserved
RTC_BA
EADC_BA
Reserved
ACMP01_BA
Analog Comparator 0/ 1 Control Registers
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0x4004_6000 – 0x4004_6FFF
0x4004_7000 – 0x4004_7FFF
0x4004_8000 – 0x4004_8FFF
0x4004_9000 – 0x4004_9FFF
0x4004_D000 – 0x4004_DFFF
0x4005_0000 – 0x4005_0FFF
0x4005_1000 – 0x4005_1FFF
0x4005_8000 – 0x4005_8FFF
0x4005_9000 – 0x4005_9FFF
0x4005_C000 – 0x4005_CFFF
0x4005_D000 – 0x4005_DFFF
0x4006_0000 – 0x4006_0FFF
0x4006_1000 – 0x4006_1FFF
0x4006_2000 – 0x4006_2FFF
0x4006_3000 – 0x4006_3FFF
0x4007_0000 – 0x4007_0FFF
0x4007_1000 – 0x4007_1FFF
0x4007_2000 – 0x4007_2FFF
0x4007_3000 – 0x4007_3FFF
0x4007_4000 – 0x4007_4FFF
0x4007_5000 – 0x4007_5FFF
0x4008_0000 – 0x4008_0FFF
0x4008_1000 – 0x4008_1FFF
0x4008_2000 – 0x4008_2FFF
0x4008_3000 – 0x4008_3FFF
0x4008_4000 – 0x4008_4FFF
0x4009_0000 – 0x4009_0FFF
0x4009_1000 – 0x4009_1FFF
0x4009_2000 – 0x4009_2FFF
0x4009_3000 – 0x4009_3FFF
0x4009_4000 – 0x4009_4FFF
0x4009_5000 – 0x4009_5FFF
0x400A_0000 – 0x400A_0FFF
0x400A_1000 – 0x400A_1FFF
0x400B_0000 – 0x400B_0FFF
Reserved
DAC_BA
Reserved
DAC Control Registers
Reserved
Reserved
Reserved
OTG_BA
TMR01_BA
TMR23_BA
PWM0_BA
PWM1_BA
Reserved
Reserved
SPI0_BA
SPI1_BA
SPI2_BA
Reserved
UART0_BA
UART1_BA
UART2_BA
UART3_BA
Reserved
Reserved
I2C0_BA
Reserved
USB OTG Control Register
Timer0/Timer1 Control Registers
Timer2/Timer3 Control Registers
PWM0 Control Registers
PWM1 Control Registers
Reserved
Reserved
SPI0 Control Registers
SPI1 Control Registers
SPI2 Control Registers
Reserved
UART0 Control Registers
UART1 Control Registers
UART2 Control Registers
UART3 Control Registers
Reserved
Reserved
I2C0 Control Registers
I2C1 Control Registers
Reserved
I2C1_BA
Reserved
Reserved
Reserved
SC0_BA
Reserved
Reserved
Smartcard Host 0 Control Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CAN0_BA
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CAN0 Bus Control Registers
Reserved
Reserved
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0x400B_1000 – 0x400B_1FFF
0x400B_0000 – 0x400B_0FFF
0x400B_1000 – 0x400B_1FFF
0x400C_0000 – 0x400C_0FFF
0x400E_0000 – 0x400E_0FFF
0x400E_2000 – 0x400E_2FFF
0x5008_0000 – 0x5008_0FFF
Reserved
Reserved
Reserved
USBD_BA
Reserved
TK_BA
Reserved
Reserved
Reserved
USB Device Control Register
Reserved
Touch Key Control Registers
Reserved
Reserved
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF
0xE000_E100 – 0xE000_ECFF
0xE000_ED00 – 0xE000_ED8F
SCS_BA
SCS_BA
SCS_BA
System Timer Control Registers
External Interrupt Controller Control Registers
System Control Registers
Table 6-5 Address Space Assignments for On-Chip Controllers
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6.2.6
SRAM Memory Organization
The M4TK supports embedded SRAM with total 32 KB size and the SRAM organization is
separated to two banks: SRAM bank0 and SRAM bank1. Each of these two banks has 16 KB
address space and can be accessed simultaneously. The SRAM bank0 supports parity error
check to make sure chip operating more stable.
Supports total 32 KB SRAM
Supports byte / half word / word write
Supports fixed 16 KB SRAM bank for independent access
Supports parity error check function for SRAM bank0
Supports oversize response error
Supports remap address to 0x1000_0000
AHB interface
SRAM decoder
controller
SRAM bank0
SRAM bank1
AHB interface
SRAM decoder
controller
Figure 6.2-8 SRAM Block Diagram
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Figure 6.2-9 shows the SRAM organization of M4TK. There are two SRAM banks in M4TK and
each bank is addressed to 16 KB. The bank0 address space is from 0x2000_0000 to
0x2000_3FFF. The bank1 address space is from 0x2000_4000 to 0x2000_7FFF. The address
between 0x2000_8000 to 0x3FFF_FFFF is illegal memory space and chip will enter hardfault if
CPU accesses these illegal memory addresses.
The address of each bank is remapping from 0x2000_0000 to 0x1000_0000. CPU can read
SRAM bank0 through 0x2000_0000 to 0x2000_3FFF or 0x1000_0000 to 0x1000_3FFF, and read
SRAM bank1 through 0x2000_4000 to 0x2000_7FFF or 0x1000_4000 to 0x1000_7FFF.
0x3FFF_FFFF
Reserved
0x2000_8000
0x2000_7FFF
0x1000_7FFF
remapping
16 KB
16 KB
SRAM bank1
SRAM bank1
0x2000_4000
0x2000_3FFF
0x1000_4000
0x1000_3FFF
remapping
16 KB
16 KB
SRAM bank0
SRAM bank0
0x2000_0000
0x1000_0000
32 KB device
32 KB device
Figure 6.2-9 SRAM Memory Organization
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SRAM bank0 has byte parity error check function. When CPU is accessing SRAM bank0, the
parity error checking mechanism is dynamic operating. As parity error occurred, the PERRIF
(SYS_SRAM_STATUS[0]) will be asserted to 1 and the SYS_SRAM_ERRADDR register will
recode the address with parity error. Chip will enter interrupt when SRAM parity error occurred if
PERRIEN (SYS_SRAM_INTCTL[0]) is set to 1. When SRAM parity error occurred, chip will stop
detecting SRAM parity error until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit.
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6.2.7
System Timer (SysTick)
The Cortex® -M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value
Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks.
When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit
clears on reads.
The SYST_VAL value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer will count from the SYST_LOAD value
rather than an arbitrary value when it is enabled.
If the SYST_LOAD is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the “ARM® Cortex™-M4 Technical Reference
Manual” and “ARM® v6-M Architecture Reference Manual”.
6.2.8
Nested Vectored Interrupt Controller (NVIC)
The NVIC and the processor core interface are closely coupled to enable low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked, or nested, interrupts to enable tail-chaining of interrupts. You can only fully access
the NVIC from privileged mode, but you can cause interrupts to enter a pending state in user
mode if you enable the Configuration and Control Register. Any other user mode access causes a
bus fault. You can access all NVIC registers using byte, halfword, and word accesses unless
otherwise stated. NVIC registers are located within the SCS (System Control Space). All NVIC
registers and system debug registers are little-endian regardless of the endianness state of the
processor.
The NVIC supports:
An implementation-defined number of interrupts, in the range 1-240 interrupts.
A programmable priority level of 0-15 for each interrupt; a higher level corresponds to
a lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non Maskable Interrupt (NMI)
WIC with Ultra-low Power Sleep mode support
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
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6.3 Clock Controller
6.3.1 Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a clock divider. The chip will not
enter Power-down mode until CPU sets the Power-down enable bit PDEN(CLK_PWRCTL[7]) and
Cortex® -M4 core executes the WFI instruction. After that, chip enters Power-down mode and wait
for wake-up interrupt source triggered to leave Power-down mode. In Power-down mode, the
clock controller turns off the 4~20 MHz external high speed crystal (HXT) and 22.1184 MHz
internal high speed RC oscillator (HIRC) to reduce the overall system power consumption. The
Figure 6.3-1 shows the clock generator and the overview of the clock source control.
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CPUCLK
HCLK
CPU
22.1184
MHz
CRC
EBI
22.1184 MHz
111
011
010
001
000
4~24
MHz
10 kHz
1/(HCLKDIV+1)
PDMA
I2C0
PLLFOUT
32.768 kHz
4~24 MHz
32.768
kHz
PCLK0
PCLK1
CAN0
I2C1
DAC
10 kHz
CLK_CLKSEL0[2:0]
ACMP01
22.1184 MHz
22.1184 MHz
4~24 MHz
111
101
1
0
10 kHz
PLL FOUT
TMR 0
T0~T1
PCLK0
011
010
TMR 1
CLK_PLLCTL[19]
32.768 kHz
4~24 MHz
10 kHz
001
000
BOD
22.1184 MHz
FMC
USB
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
PLLFOUT
PCLK1
1/(USBDIV+1)
1/(EADCDIV+1)
EADC
22.1184 MHz
10 kHz
111
101
10 kHz
32.768 kHz
TMR 2
TMR 3
1
T2~T3
PCLK1
RTC
011
010
0
32.768 kHz
4~24 MHz
001
000
CLK_CLKSEL3[8]
22.1184 MHz
11
10
CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]
HCLK
Clock Output
32.768 kHz
4~24 MHz
01
00
22.1184 MHz
1/2
111
HCLK
1/2
CPUCLK
011
010
001
000
CLK_CLKSEL1[29:28]
22.1184 MHz
1
0
4~24 MHz
1/2
SysTick
32.768 kHz
11
10
PCLK0
4~24 MHz
SYST_CTRL[2]
PLLFOUT
SPI0
SPI2
01
00
4~24 MHz
CLK_CLKSEL0[5:3]
CLK_CLKSEL2[3:2]
CLK_CLKSEL2[7:6]
PCLK0
1
0
PWM 0
PLLFOUT
22.1184 MHz
11
10
CLK_CLKSEL2[0]
PCLK1
PLLFOUT
SPI1
01
00
PCLK1
4~24 MHz
1
0
PWM 1
PLLFOUT
CLK_CLKSEL2[5:4]
CLK_CLKSEL2[1]
22.1184 MHz
PCLK0
11
10
10 kHz
1/2048
11
10
01
1/(SC0DIV+1)
SC0
PLLFOUT
4~24 MHz
HCLK
WDT
01
00
32.768 kHz
CLK_CLKSEL1[1:0]
CLK_CLKSEL3[1:0]
10 kHz
22.1184 MHz
32.768 kHz
PLLFOUT
11
10
11
WWDT
HCLK
1/2048
10
01
00
1/(UARTDIV+1)
UART 0-3
CLK_CLKSEL1[31:30]
4~24 MHz
CLK_CLKSEL1[25:24]
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-1 Clock Generator Global View Diagram
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6.3.2
Clock Generator
The clock generator consists of 5 clock sources, which are listed below:
32.768 kHz external low speed crystal oscillator (LXT)
4~20 MHz external high speed crystal oscillator (HXT)
Programmable PLL output clock frequency (PLLFOUT), PLL source can be selected
from external 4~20 MHz external high speed crystal (HXT) or 22.1184 MHz internal
high speed oscillator (HIRC)
22.1184 MHz internal high speed RC oscillator (HIRC)
10 kHz internal low speed RC oscillator (LIRC)
LXTEN (CLK_PWRCTL[1])
X32_IN
External 32.768
kHz Crystal
LXT
(LXT)
X32_OUT
HXTEN (CLK_PWRCTL[0])
HXT
XT1_IN
External 4~24
PLLSRC (CLK_PLLCTL[19])
MHz Crystal
(HXT)
XT1_OUT
0
1
PLL FOUT
PLL
HIRCEN (CLK_PWRCTL[2])
Internal
22.1184 MHz
Oscillator
(HIRC)
HIRC
LIRC
LIRCEN (CLK_PWRCTL[3])
Internal 10 kHz
Oscillator
(LIRC)
Figure 6.3-2 Clock Generator Block Diagram
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6.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources, which were generated from clock generator block. The
clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram
is shown in the Figure 6.3-3.
HCLKSEL
(CLK_CLKSEL0[2:0])
HIRC
111
CPUCLK
LIRC
PLLFOUT
LXT
CPU
AHB
011
010
001
000
HCLK
PCLK0
PCLK1
1/(HCLKDIV+1)
HCLKDIV
(CLK_CLKDIV0[3:0])
APB0
APB1
HXT
CPU in Power Down Mode
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-3 System Clock Block Diagram
There are two clock fail detectors to observe HXT and LXT clock source and they have individual
enable and interrupt control. When HXT detector is enabled, the HIRC clock is enabled
automatically. When LXT detector is enabled, the LIRC clock is enabled automatically.
When HXT clock detector is enabled, the system clock will auto switch to HIRC if HXT clock stop
being detected on the following condition: system clock source comes from HXT or system clock
source comes from PLL with HXT as the input of PLL. If HXT clock stop condition is detected, the
HXTFIF (CLK_CLKDSTS[0]) is set to 1 and chip will enter interrupt if HXTFIE (CLK_CLKDCTL[5])
is set to 1. User can trying to recover HXT by disable HXT and enable HXT again to check if the
clock stable bit is set to 1 or not. If HXT clock stable bit is set to 1, it means HXT is recover to
oscillate after re-enable action and user can switch system clock to HXT again.
The HXT clock stop detect and system clock switch to HIRC procedure is shown in the Figure
6.3-4.
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Set HXTFDEN To enable
HXT clock detector
NO
HXTFIF = 1?
YES
System clock source =
“HXT” or “PLL with
HXT” ?
System clock keep
original clock
NO
YES
Switch system clock to
HIRC
Figure 6.3-4 HXT Stop Protect Procedure
The clock source of SysTick in Cortex® -M4 core can use CPU clock or external clock
(SYST_CTRL[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The
block diagram is shown in the Figure 6.3-5.
STCLKSEL
(CLK_CLKSEL0[5:3])
HIRC
111
011
010
001
000
1/2
1/2
1/2
HCLK
HXT
LXT
STCLK
HXT
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-5 SysTick Clock Control Block Diagram
6.3.4
Peripherals Clock
The peripherals clock has different clock source switch setting, which depends on the different
peripheral. Please refer to the CLK_CLKSEL1 and CLK_CLKSEL2 register description in 5.3.8.
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6.3.5
Power-down Mode Clock
When entering Power-down mode, system clocks, some clock sources and some peripheral
clocks are disabled. Some clock sources and peripherals clock are still active in Power-down
mode.
For theses clocks, which still keep active, are listed below:
Clock Generator
10 kHz internal low speed RC oscillator (LIRC) clock
32.768 kHz external low speed crystal oscillator (LXT) clock
Peripherals Clock (When the modules adopt LXT or LIRC as clock source)
6.3.6
Clock Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock
divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).
When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When
writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock
reaches low state and stays in low state.
CLKOSEL (CLK_CLKSEL1[29:28])
CLKOCKEN (CLK_APBCLK0[6])
HIRC
11
HCLK
CLKO_CLK
10
01
00
LXT
HXT
Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable.
Figure 6.3-6 Clock Source of Clock Output
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CLKOEN
(CLK_CLKOCTL[4])
Enable
FREQSEL
(CLK_CLKOCTL[3:0])
divide-by-2 counter
16 chained
divide-by-2 counter
CLKO_CLK
1/22
1/23
…...
1/215 1/216
DIVIDER1*
(FRQDIV[5])
1/2
CLK1HZEN
(CLK_CLKOCTL[6])
0000
0001
:
16 to 1
MUX
0
1
:
0
1
1110
CLKO
1111
RTCSEL(CLK_CLKSEL3[8])
LIRC
LXT
0
1
1 Hz clock from RTC
/32768
Figure 6.3-7 Clock Output Block Diagram
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6.4 Flash Memeory Controller (FMC)
6.4.1 Overview
The NuMicro® M4TK series is equipped with 128/256 KB on-chip embedded flash for application
and configurable Data Flash to store some application dependent data. A User Configuration
block provides for system initiation. A 4 KB loader ROM (LDROM) is used for In-System-
Programming (ISP) function. A 16KB Boot Loader consists of native ISP functions. A 4KB cache
with zero wait cycle is used to improve flash access performance. This chip also supports In-
Application-Programming (IAP) function, user switches the code executing without the chip reset
after the embedded flash updated.
6.4.2
Features
Supports 128/256 KB application ROM (APROM).
Supports 4 KB loader ROM (LDROM).
Supports Data Flash with configurable memory size.
Supports 8 bytes User Configuration block to control system initiation.
Supports 2 KB page erase for all embedded flash.
Supports Boot Loader with native In-System-Programming (ISP) functions.
Supports 32-bit/64-bit and multi-word flash programming function.
Supports fast flash programming verification function.
Supports checksum calculation function.
Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update
embedded flash memory.
Supports cache memory to improve flash access performance and reduce power
consumption.
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6.5 External Bus Interface (EBI)
6.5.1 Overview
The NuMicro® M4TK is equipped with an external bus interface (EBI) for external device used. To
save the connections between external device and the NuMicro® M4TK, EBI operating at address
bus and data bus multiplex mode. The EBI supports two chip selects that can connect two
external devices with different timing setting requirement.
6.5.2
Features
The External Bus Interface (EBI) has the following functions:
Supports address bus and data bus multiplex mode to save the address pins
Supports two chip selects with polarity control
Supports external devices with max. 1 MB size for each chip select
Supports variable external bus base clock (MCLK) which based on HCLK
Supports 8-bit or 16-bit data width for each chip select
Supports variable address latch enable time (tALE)
Supports variable data access time (tACC) and data access hold time (tAHD) for each
chip select
Supports configurable idle cycle for different access condition: Idle of Write command
finish (W2X) and Idle of Read-to-Read (R2R)
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6.6 General Purpose I/O (GPIO)
6.6.1 Overview
The NuMicro® M4TK series has up to 87 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 87 pins are arranged in 6 ports named
as PA, PB, PC, PD, PE and PF. PA, PB, PC, and PD has 16 pins on port. PE has 15 pins on
port.PF has 8 pins on port. Each of the 87 pins is independent and has the corresponding register
bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V.
6.6.2
Features
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports High Drive and High Slew Rate I/O mode
Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
CIOIN = 0, all GPIO pins in Quasi-bidirectional mode after chip reset
CIOIN = 1, all GPIO pins in input mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the wake-up function
Supports 5V-tolerance function for following pins
PA.0 ~ PA.15, PC.0 ~ PC.7, PC.9 ~ PC.15, PD.5 ~ PD.8, PD.10 ~ PD.15, PE.0 ~
PE.14, PF.2, PF.5 ~ PF.6
PA.0 ~ PA.15, PB.14 ~ PB.14, PC.0 ~ PC.8, PC.10 ~ PC.13, PD.4 ~ PD.7, PD.12 ~
PD.15, PE.0 ~ PE.1, PE.3 ~ PE.5, PE.8 ~ PE.13, PF.2.
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6.7 PDMA Controller (PDMA)
6.7.1 Overview
The peripheral direct memory access (PDMA) controller is used to provide high-speed data
transfer. The PDMA controller can transfer data from one address to another without CPU
intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free
for other applications. The PDMA controller has a total of 12 channels and each channel can
perform transfer between memory and peripherals or between memory and memory.
6.7.2
Features
Supports 12 independently configurable channels
Supports selectable 2 level of priority (fixed priority or round-robin priority)
Supports transfer data width of 8, 16, and 32 bits
Supports source and destination address increment size can be byte, half-word, word
or no increment
Supports software and SPI, UART, DAC, ADC and PWM request
Supports Scatter-Gather mode to perform sophisticated transfer through the use of
the descriptor link list table
Supports single and burst transfer type
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6.8 Timer Controller (TMR)
6.8.1 Overview
The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, delay timing, clock generation, and event counting by external input pins, and
interval measurement by external capture pins.
6.8.2
Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle-output and continuous counting operation modes
24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])
Supports event counting function
24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])
Supports external capture pin event for interval measurement
Supports external capture pin event to reset 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
Support Timer0 time-out interrupt signal to trigger Touch-Key scan
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to trigger PWM,
EADC and DAC function
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6.9 PWM Generator and Capture Timer (PWM)
6.9.1 Overview
The M4TK provides two PWM generators － PWM0 and PWM1 as 錯誤! 找不到參照來源。. Each
PWM supports 6 channels of PWM output or input capture. There is a 12-bit prescaler to support
flexible clock to the 16-bit PWM counter with 16-bit comparator. The PWM counter supports up,
down and up-down counter types. PWM using comparator compared with counter to generate
events. These events use to generate PWM pulse, interrupt and trigger signal for EADC/DAC to
start conversion.
The PWM generator supports two standard PWM output modes: Independent mode and
Complementary mode, they have difference architecture. There are two output functions based
on standard output modes: Group function and Synchronous function. Group function can be
enabled under Independent mode or complementary mode. Synchronous function only enabled
under complementary mode. Complementary mode has two comparators to generate various
PWM pulse with 12-bit dead-time generator and another free trigger comparator to generate
trigger signal for EADC. For PWM output control unit, it supports polarity output, independent pin
mask and brake functions.
The PWM generator also supports input capture function. It supports latch PWM counter value to
corresponding register when input channel has a rising transition, falling transition or both
transition is happened. Capture function also support PDMA to transfer captured data to memory.
6.9.2
Features
6.9.2.1 PWM function features
Supports maximum clock frequency up to144MHz
Supports up to two PWM modules, each module provides 6 output channels.
Supports independent mode for PWM output/Capture input channel
Supports complementary mode for 3 complementary paired PWM output channel
Dead-time insertion with 12-bit resolution
Synchronous function for phase control
Two compared values during one period
Supports 12-bit pre-scalar from 1 to 4096
Supports 16-bit resolution PWM counter
Up, down and up/down counter operation type
Supports one-shot or auto-reload counter operation mode
Supports group function
Supports synchronous function
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Brake source from pin, analog comparator and system safety events (clock
failed, SRAM parity error, Brown-out detection and CPU lockup).
Noise filter for brake source from pin
Edge detect brake source to control brake state until brake interrupt cleared
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Level detect brake source to auto recover function after brake condition removed
Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Brake condition happened
Supports trigger EADC/DAC on the following events:
PWM counter match zero, period value or compared value
PWM counter match free trigger comparator compared value (only for EADC)
6.9.2.2 Capture Function Features
Supports up to 12 capture input channels with 16-bit resolution
Supports rising or falling capture condition
Supports input rising/falling capture interrupt
Supports rising/falling capture with counter reload option
Supports PDMA transfer function for PWM all channels
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6.10 Watchdog Timer (WDT)
6.10.1 Overview
The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an
unknown state. This prevents system from hanging for an infinite period of time. Besides, this
Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.
6.10.2 Features
18-bit free running up counter for WDT time-out interval
Selectable time-out interval (24 ~ 218) and the time-out interval is 1.6 ms ~ 26.214s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset
delay period
Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in
Config0 register
Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or
LXT.
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6.11 Window Watchdog Timer (WWDT)
6.11.1 Overview
The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified
window period to prevent software run to uncontrollable status by any unpredictable condition.
6.11.2 Features
6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the
WWDT time-out window period flexible
Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter period of
WWDT counter
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6.12 Real Time Clock (RTC)
6.12.1 Overview
The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC
offers programmable time tick and alarm match interrupts. The data format of time and calendar
messages are expressed in BCD format. A digital frequency compensation feature is available to
compensate external crystal oscillator frequency accuracy.
The RTC controller also offers 80 bytes spare registers to store user’s important information. The
spare registers content is cleared when specified event on tamper pin is detected.
6.12.2 Features
Supports real time counter in RTC_TIME (hour, minute, second) and calendar counter in
RTC_CAL (year, month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in
RTC_TALM and RTC_CALM
Supports alarm time (hour, minute, second) and calendar (year, month, day) mask enable in
RTC_TAMSK and RTC_CAMSK
Selectable 12-hour or 24-hour time scale in RTC_CLKFMT register
Supports Leap Year indication in RTC_LEAPYEAR register
Supports Day of the Week counter in RTC_WEEKDAY register
Frequency of RTC clock source compensate by RTC_FREQADJ register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
Supports 80 bytes spare registers and a snoop pin detection to clear the content of these
spare registers
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6.13 UART Interface Controller (UART)
6.13.1 Overview
The NuMicro® M4TK series provides four channels of Universal Asynchronous
Receiver/Transmitters (UART). UART Controller performs Normal Speed UART and supports
flow control function. The UART Controller performs a serial-to-parallel conversion on data
received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU.
Each UART Controller channel supports ten types of interrupts. The UART controller also
supports IrDA SIR, RS-485 and auto-baud rate measuring function.
6.13.2 Features
Full-duplex asynchronous communications
Separates receive and transmit 16/16 bytes entry FIFO for data payloads
Supports hardware auto-flow control
Programmable receiver buffer trigger level
Supports programmable baud rate generator for each channel individually
Supports nCTS and RX data wake-up function
Supports 8-bit receiver buffer time-out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting DLY (UART_TOUT [15:8])
Supports Auto-Baud Rate measurement
Supports break error, frame error, parity error and receive/transmit buffer overflow detection
function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5-, 6-, 7-, 8- bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Supports IrDA SIR function mode
Supports for 3/16 bit duration for normal mode
Supports LIN function mode (Only UART0 /UART1 with LIN function)
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detection function for receiver
Supports RS-485 function mode
Supports RS-485 9-bit mode
Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
UART Feature
UART0 / UART1
UART2 / UART3
SC_UART
FIFO
16 Bytes
16 Bytes
4 Bytes
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Auto Flow Control (CTS/RTS)
IrDA
√
√
-
√
√
-
LIN
√
-
-
RS-485 Function Mode
Auto-Flow Control
nCTS Wake-up
√
√
-
√
√
-
√
√
-
RX Data Wake-up
Auto-Baud Rate Measurement
STOP Bit Length
Word Length 5, 6,7, 8 bits
Even / Odd Parity
Stick Bit
√
√
-
√
√
-
1, 1.5, 2 bit
1, 1.5, 2 bit
1, 2 bit
√
√
√
√
√
√
√
√
-
√= Supported
Table 6-6 NuMicro® M4TK Series UART Feature
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6.14 Smart Card Host Interface (SC)
6.14.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/INTENC 7816-3 standard and
fully compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.14.2 Features
ISO-7816-3 T = 0, T = 1 compliant.
EMV2000 compliant
One ISO-7816-3 port
Separates receive/transmit 4 byte entry FIFO for data payloads.
Programmable transmission clock frequency.
Programmable receiver buffer trigger level.
Programmable guard time selection (11 ETU ~ 267 ETU).
A 24-bit and two 8-bit timers for Answer to Request (ATR) and waiting times
processing.
Supports auto inverse convention function.
Supports transmitter and receiver error retry and error number limiting function.
Supports hardware activation sequence, hardware warm reset sequence and
hardware
deactivation sequence process.
Supports hardware auto deactivation sequence when detected the card removal.
Supports UART mode
Full duplex, asynchronous communications.
Separates receiving / transmitting 4 bytes entry FIFO for data payloads.
Supports programmable baud rate generator.
Supports programmable receiver buffer trigger level.
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting EGT (SC_EGT[7:0]).
Programmable even, odd or no parity bit generation and detection.
Programmable stop bit, 1- or 2- stop bit generation
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6.15 I2C Serial Interface Controller (I2C)
6.15.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
There are two sets of I2C controller which supports Bus Management (System Management
(SM)/Power Management (PM) bus compatible) and Power-down wake-up function.
6.15.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the I2C bus include:
Supports up to two I2C ports
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data on
the bus
Serial clock synchronization allow devices with different bit rates to communicate via one
serial bus
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and
timer-out counter overflows.
Programmable clocks allow for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( four slave address with mask option)
Supports Bus Management (SM/PM compatible) function
Supports Power-down wake-up function
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6.16 Serial Peripheral Interface (SPI)
6.16.1 Overview
The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and
allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-
direction interface. The NuMicro® M4TK series contains up to three sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each SPI controller can be
configured as a master or a slave device.
SPI0 controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also
supports Dual and Quad I/O Transfer mode. SPI1 and SPI2 controller also support I2S mode to
connect external audio CODEC.
6.16.2 Features
SPI Mode
Up to three sets of SPI controllers
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual and Quad I/O Transfer mode for SPI0
Configurable bit length of a transaction word from 8 to 32-bit
Provides separate 4-/8-level depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Supports Byte Reorder function
Supports PDMA transfer
Supports 3-Wire, no slave selection signal, bi-direction interface
I2S Mode for SPI1 and SPI2
Supports Master or Slave
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Provides separate 4-level depth transmit and receive FIFO buffers
Supports monaural and stereo audio data
Supports PCM mode A, PCM mode B, I2S and MSB justified data format
Supports PDMA transfer
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6.17 USB Device Controller (USBD)
6.17.1 Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device. It is
compliant with USB 2.0 full-speed device specification and supports Control/Bulk/Interrupt/
Isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through buffer
segmentation register (USBD_BUFSEGx).
There are 8 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of “Endpoint Control” is also used to manage the data
sequential synchronization, endpoint state, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the no-event-wake-up, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USBD_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USBD_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disconnect function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables SE0 bit (USBD_SE0), the USB
controller will force the output of USB_D+ and USB_D- to level low and its function is disabled.
After disable the SE0 bit, host will enumerate this USB device again.
For more information on the Universal Serial Bus, please refer to Universal Serial Bus
Specification Revision 1.1.
6.17.2 Features
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB
and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer types
Supports suspend function when no bus activity existing for 3 ms
Supports 8 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size
Provides remote wake-up capability
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6.18 USB 1.1 Host Controller (USBH)
6.18.1 Overview
This chip is equipped with a USB 1.1 Host Controller (USBH) that supports Open Host Controller
Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to
manage the devices and data transfer of Universal Serial Bus (USB).
The USBH supports an integrated Root Hub with a USB port, a DMA for real-time data transfer
between system memory and USB bus, port power control and port over current detection.
The USBH is responsible for detecting the connect and disconnect of USB devices, managing
data transfer, collecting status and activity of USB bus, providing power control and detecting over
current of attached USB devices.
6.18.2 Features
Supports Universal Serial Bus (USB) Specification Revision 1.1.
Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.
Supports both full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.
Supports Control, Bulk, Interrupt and Isochronous transfers.
Supports an integrated Root Hub.
Supports a USB host port shared with USB device (OTG function).
Supports port power control and port over current detection.
Supports DMA for real-time data transfer.
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6.19 USB On-The-Go (OTG)
6.19.1 Overview
The OTG controller interfaces to USB PHY and USB controllers which consist of a USB 1.1 host
controller and a USB 2.0 FS device controller. The OTG controller supports HNP and SRP protocols
defined in the “On-The-Go and Embedded Host Supplement to the USB 2.0 Revision 1.3
Specification”.
USB frame, including USB host, USB device, and OTG controller, can be configured as Host-only,
Device-only, ID-dependent or OTG Device mode defined in USBROLE (SYS_USBPHY[1:0]). In Host-
only mode, USB frame acts as USB host. USB frame can support both full-speed and low-speed
transfer. In Device-only mode, USB frame acts as USB device. USB frame only supports full-speed
transfer. In ID-dependent mode, USB frame can be USB Host or USB device depends on USB_ID pin
state. In OTG device mode, the role of USB frame depends on the definition of OTG specification.
USB frame only supports full-speed transfer when OTG device acts as a peripheral.
6.19.2 Features
Built in USB PHY
Configurable to operate as:
Host-only
Device-only
ID-dependent: The role of USB frame is only dependent on USB_ID pin value--
as USB Host (USB_ID pin is low) or USB Device (USB_ID pin is high). Not
support HNP or SRP protocol.
OTG device: dependent on USB_ID pin status to be A-device (USB_ID pin is
low) or B-device (USB_ID pin is high). Support HNP and SRP protocols.
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6.20 Controller Area Network (CAN)
6.20.1 Overview
The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and
Module Interface (Refer to 錯誤! 找不到參照來源。) The CAN Core performs communication
according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up
to 1MBit/s. For the connection to the physical layer, additional transceiver hardware is required.
For communication on a CAN network, individual Message Objects are configured. The Message
Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message
RAM. All functions concerning the handling of messages are implemented in the Message Handler.
These functions include acceptance filtering, the transfer of messages between the CAN Core and the
Message RAM, and the handling of transmission requests as well as the generation of the module
interrupt.
The register set of the C_CAN can be accessed directly by the software through the module interface.
These registers are used to control/configure the CAN Core and the Message Handler and to access
the Message RAM.
6.20.2 Features
Supports CAN protocol version 2.0 part A and B
Bit rates up to 1 MBit/s
32 Message Objects
Each Message Object has its own identifier mask
Programmable FIFO mode (concatenation of Message Objects)
Maskable interrupt
Disabled Automatic Re-transmission mode for Time Triggered CAN applications
Programmable loop-back mode for self-test operation
16-bit module interfaces to the AMBA APB bus
Supports wake-up function
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6.21 Touch Key (TK)
6.21.1 Overview
The capacitive touch-key sensing controller supports several programmable sensitivity levels for
different applications to detect the finger touched or near the electrode covered by dielectric. It
supports up to 16 touch-keys with single-scan or programmable periodic key-scans, and system
can be waked-up by any key for low power applications.
6.21.2 Features
Supports up to 16 touch-keys.
Supports flexible reference channel setting, at least 1 reference channel needed.
Programmable sensitivity levels for each channel.
Programmable scanning speed for different applications.
Supports any touch-key wake-up for low-power applications.
Supports single key-scan and programmable periodic key-scan.
Programmable interrupt options for key-scan complete with or without threshold control.
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6.22 CRC Controller (CRC)
6.22.1 Overview
The Cyclic Redundancy Check (CRC) generator can perform CRC calculation with programmable
polynomial settings.
6.22.2 Features
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
CRC-CCITT: X16 + X12 + X5 + 1
CRC-8: X8 + X2 + X + 1
CRC-16: X16 + X15 + X2 + 1
CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
Programmable seed value
Supports programmable order reverse setting for input data and CRC checksum
Supports programmable 1’s complement setting for input data and CRC checksum
Supports 8/16/32-bit of data width
8-bit write mode: 1-AHB clock cycle operation
16-bit write mode: 2-AHB clock cycle operation
32-bit write mode: 4-AHB clock cycle operation
Supports using PDMA to write data to perform CRC operation
Jan. 06, 2016
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6.23 Enhanced 12-bit Analog-to-Digital Converter (EADC)
6.23.1 Overview
The M4TK series contains one 12-bit successive approximation analog-to-digital converter
(SAR A/D converter) with 16 external input channels and 3 internal channels. The A/D
converter can be started by software trigger, PWM0/1 triggers, timer0~3 overflow pulse
triggers, ADINT0, ADINT1 interrupt EOC (End of conversion) pulse trigger and external pin
(STADC) input signal.
6.23.2 Features
Analog input voltage range: 0~VREF (Max to AVDD).
Reference voltage from VREF pin or AVDD.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 16 single-end analog external input channels or 8 pair differential analog input
channels.
3 internal channels, they are band-gap voltage (VBG), temperature sensor (VTEMP), and
Battery power (VBAT
)
Four ADC interrupts (ADINT0~3) with individual interrupt vector addresses.
Maximum ADC clock frequency is 20 MHz.
Up to 1 Msps conversion rate.
Configurable ADC internal sampling time.
Up to 19 sample modules
Each of sample module 0~15 which is configurable for ADC converter channel
EADC_CH0~15 and trigger source.
Sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap
voltage, temperature sensor, and battery power (VBAT).
Double buffer for sample module 0~3
Configurable sampling time for each sample module.
Conversion results are held in 19 data registers with valid and overrun indicators.
An A/D conversion can be started by:
Write 1 to SWTRGn (EADC_SWTRG[n] , n = 0~18)
External pin STADC
Timer0~3 overflow pulse triggers
ADINT0 and ADINT1 interrupt EOC (End of conversion) pulse triggers
PWM triggers
Supports PDMA transfer
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6.24 Digital to Analog Converter (DAC)
6.24.1 Overview
The DAC module is a 12-bit, voltage output digital-to-analog converter. It can be used in
conjunction with the PDMA controller. The DAC integrates a voltage output buffer that can be
used to reduce output impendence and drive external loads directly without having to add an
external operational amplifier.
6.24.2 Features
Analog output voltage range: 0~AVDD.
Reference voltage from internal reference voltage (INT_VREF), VREF pin or AVDD.
DAC maximum conversion updating rate 1M sps.
Supports voltage output buffer mode and bypass voltage output buffer mode.
Supports software and hardware trigger to start DAC conversion.
Supports PDMA request.
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6.25 Analog Comparator Controller (ACMP)
6.25.1 Overview
The M4TK contains two comparators. The comparator output is logic 1 when positive input is
greater than negative input; otherwise, the output is 0. Each comparator can be configured to
generate an interrupt when the comparator output value changes.
6.25.2 Features
Analog input voltage range: 0 ~ AVDD (voltage of AVDD pin)
Supports hysteresis function
Supports wake-up function
Selectable input sources of positive input and negative input
ACMP0 supports
4 positive sources
ACMP0_P0, ACMP0_P1, ACMP0_P2, or ACMP0_P3
4 negative sources
ACMP0_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC output (DAC_OUT)
ACMP1 supports
4 positive sources
ACMP1_P0, ACMP1_P1, ACMP1_P2, or ACMP1_P3
4 negative sources
ACMP1_N
Comparator Reference Voltage (CRV)
Internal band-gap voltage (VBG)
DAC output (DAC_OUT)
Shares one ACMP interrupt vector for all comparators
Jan. 06, 2016
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M4TK
7 APPLICATION CIRCUIT
AVCC
VREF
AVDD
USB_VBUS
USB_D-
USB_D+
USB_ID
USB OTG Slot
FB
DVCC
VDD
USB_VDD33_CAP
VDDIO
0.1uF
1uF
1uF
VBAT
VSS
DVCC
Power
0.1uF
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
CS
VDD
VSS
FB
CLK
MISO
MOSI
SPI Device
AVSS
VDD
DVCC
4.7K
DVCC
ICE_CLK
ICE_DAT
nRESET
VSS
SWD
Interface
4.7K
M4TK Series
CLK
DIO
20p
I2C_SCL
I2C_SDA
VDD
VSS
I2C Device
XT1_IN
4~ 24 MHz
crystal
20p
20p
DVCC
XT1_OUT
X32_IN
Crystal
SC_PWR
32.768kHz
crystal
20p
SC_RST
SC_CLK
Smart Card Slot
X32_OUT
SC_DAT
SC_ Detect
DVCC
ODB Port
CAN Transceiver
CAN_TX
CAN_RX
D
R
CAN_H
CAN_L
Reset
Circuit
10K
CAN
nRST
10uF/10V
PC COM Port
RS 232 Transceiver
ROUT RIN
RXD
TXD
UART
LDO CAP
_
TIN
TOUT
LDO
1uF
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8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
Symbol
VDD VSS
VIN
Parameter
Min
-0.3
VSS - 0.3
4
Max
+7.0
VDD + 0.3
20
Unit
V
DC Power Supply
Input Voltage
V
1/tCLCL
TA
Oscillator Frequency
MHz
Operating Temperature
-40
+105
+150
120
℃
TST
Storage Temperature
-55
IDD
Maximum Current into VDD
-
mA
mA
mA
mA
mA
mA
ISS
Maximum Current out of VSS
120
Maximum Current sunk by a I/O pin
Maximum Current sourced by a I/O pin
Maximum Current sunk by total I/O pins
Maximum Current sourced by total I/O pins
35
35
IIO
100
100
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the
lift and reliability of the device.
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M4TK
8.2 DC Electrical Characteristics
(VDD - VSS = 2.5 ~ 5.5 V, TA = 25C)
SPECIFICATION
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Operation voltage
VDD
2.5
-
5.5
V
VDD = 2.5 V ~ 5.5 V up to 72 MHz
Power supply for
PE.8~PE.13
VDDIO
1.8
2.5
-
-
5.5
5.5
V
V
RTC Operation
voltage for
VBAT
PF.0~PF.2
Power Ground
VSS / AVSS
-0.3
1.62
0
0.3
1.98
1.225
V
V
V
LDO Output Voltage
VLDO
1.8
1.21
VDD ≥ 2.5 V
Band-gap Voltage
VBG
1.175
VDD = 2.5 V ~ 5.5 V, TA = 25C
Allowed voltage
difference for VDD
and AVDD
VDD-AVDD
-0.3
0
0.3
V
All digital
modules
VDD
HXT
HIRC
PLL
IDD1
-
64
-
mA
Operating Current
Normal Run Mode
HCLK = 72 MHz
while(1){}
5.5V
5.5V
12 MHz
12 MHz
X
X
V
V
V
X
IDD2
IDD3
IDD4
-
-
-
32
63
31
-
-
-
mA
mA
mA
3.3V
3.3V
12 MHz
12 MHz
X
X
V
V
V
X
executed from flash
IDD5
IDD6
IDD7
IDD8
IDD9
IDD10
IDD11
-
-
-
-
-
-
-
45
23
45
22
20
10
20
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
V
V
V
V
V
V
V
X
X
X
V
X
V
X
V
X
V
Operating Current
Normal Run Mode
HCLK = 50 MHz
while(1){}
executed from flash
Operating Current
Normal Run Mode
X
HCLK =22.1184
MHz
X
while(1){}
IDD12
-
10
-
mA
3.3V
X
V
X
X
executed from flash
Operating Current
Normal Run Mode
HCLK = 12 MHz
while(1){}
IDD13
IDD14
IDD15
IDD16
IDD17
IDD18
-
-
-
-
-
-
12
6
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
X
X
X
X
X
X
V
X
V
X
V
X
12
6
executed from flash
Operating Current
Normal Run Mode
3.4
1.9
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M4TK
SPECIFICATION
Parameter
Symbol
Test Conditions
Min.
Typ.
3.3
Max.
Unit
mA
mA
HCLK =4 MHz
while(1){}
IDD19
IDD20
-
-
-
-
3.3V
3.3V
12 MHz
12 MHz
X
X
X
X
V
X
1.8
executed from flash
LXT
All digital
modules
VDD
HIRC
PLL
(kHz)
IDD21
-
153
139
-
uA
Operating Current
HCLK = 32.768 kHz
while(1){}
5.5V
5.5V
32.768
32.768
X
X
X
X
V
X
uA
uA
uA
IDD22
IDD23
IDD24
executed from flash
133
120
3.3V
3.3V
32.768
32.768
X
X
X
X
V
X
-
-
-
-
HXT
/LXT
LIRC
(kHz)
All digital
modules
VDD
PLL
Operating Current
Normal Run Mode
HCLK = 10 kHz
while(1){}
IDD25
134
μA
5.5V
5.5V
3.3V
3.3V
X
X
X
X
10
10
10
10
X
X
X
X
V
X
V
X
IDD26
IDD27
IDD28
-
-
-
130
121
117
-
-
-
μA
μA
μA
Executed from
Flash
Operating Current
Idle Mode
All digital
modules
VDD
HXT
HIRC
PLL
IIDLE1
-
42
-
mA
HCLK = 72 MHz
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
3.3V
3.3V
5.5V
5.5V
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
X
X
X
X
X
X
X
X
X
V
V
V
V
X
X
V
V
V
V
V
V
V
V
X
X
X
X
X
X
V
X
V
X
V
X
V
X
V
X
V
X
V
X
IIDLE2
IIDLE3
IIDLE4
IIDLE5
IIDLE6
IIDLE7
IIDLE8
IIDLE9
IIDLE10
IIDLE11
IIDLE12
IIDLE13
IIDLE14
-
-
-
-
-
-
-
-
-
-
-
-
9
42
8
-
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating Current
Idle Mode
30
6
HCLK = 50 MHz
30
6
Operating Current
Idle Mode
12
3
X
HCLK =22.1184
MHz
12
3
X
X
Operating Current
Idle Mode
8
12 MHz
12 MHz
2
HCLK =12 MHz
IIDLE15
-
8
-
mA
3.3V
12 MHz
X
X
V
IIDLE16
IIDLE17
-
-
2
-
-
mA
mA
3.3V
5.5V
12 MHz
12 MHz
X
X
X
X
X
V
Operating Current
2.5
Jan. 06, 2016
Page 116 of 144
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M4TK
SPECIFICATION
Parameter
Symbol
Test Conditions
Min.
Typ.
0.9
Max.
Unit
mA
mA
Idle Mode
IIDLE18
IIDLE19
IIDLE20
-
-
-
-
5.5V
3.3V
12 MHz
12 MHz
X
X
X
X
X
V
HCLK =4 MHz
2.4
-
-
-
0.8
-
-
-
mA
3.3V
12 MHz
X
X
X
Operating Current
Idle Mode
LXT
All digital
modules
VDD
HIRC
PLL
(kHz)
IIDLE21
143
uA
32.768 kHz
5.5V
5.5V
32.768
32.768
X
X
X
X
V
X
IIDLE22
IIDLE23
IIDLE24
128
130
115
uA
uA
uA
3.3V
3.3V
32.768
32.768
X
X
X
X
V
X
Operating Current
Idle Mode
HXT
/LXT
LIRC
(kHz)
All digital
modules
VDD
PLL
IIDLE25
-
131
-
uA
at 10 kHz
5.5V
5.5V
3.3V
3.3V
X
X
X
X
10
10
10
10
X
X
X
X
V
X
V
X
IIDLE26
IIDLE27
IIDLE28
-
-
-
127
118
113
-
-
-
μA
μA
μA
Standby Current
LXT
HXT/HI
RC/PLL
RAM
retension
VDD
RTC
Power-down Mode
(Deep Sleep Mode)
(kHz)
IPWD1
20
A
5.5V
5.5V
3.3V
3.3V
X
X
X
X
X
X
V
X
V
V
V
V
V
IPWD2
IPWD3
IPWD4
22
18
20
32.768
X
A
A
A
32.768
VBAT = 5.0 V, 32.768 kHz external low speed crystal
oscillator (LXT), RTC ON and VDD/AVDD power
domain OFF.
1.7
1.9
8.1
uA
RTC Operating
Current
IVBAT
VBAT = 3.0 V, 32.768 kHz external low speed crystal
oscillator (LXT), RTC ON and VDD/AVDD power
domain OFF.
1.6
-55
-
1.8
-45
-67
7.7
-30
-75
uA
A
A
Input Current at
/RESET[1]
IIN
VDD = 3.3V, VIN = 0.45V
Logic 0 Input
Current (Quasi-
bidirectional mode)
IIL
VDD = VDDIO = VBAT = 5.5 V, VIN = 0V
Logic 1 to 0
Transition Current
(Quasi-bidirectional
mode) [*3]
ITL
-
-610
-650
VDD = VDDIO = VBAT =5.5 V, VIN = 2.0V
A
A
VDD = VDDIO = VBAT =5.5 V, 0 < VIN < VDD
Input Leakage
Current
ILK
-1
-
+1
Open-drain or input only mode
Jan. 06, 2016
Page 117 of 144
Rev.1.00
M4TK
SPECIFICATION
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
-0.3
-0.3
-
-
0.8
0.6
VDD = VDDIO = VBAT = 4.5 V
Input Low Voltage
(TTL input)
VIL1
V
VDD = VDDIO = VBAT = 2.5 V
Input Low Voltage
(TTL input for PE8
~ PE13)
VDD = VBAT = 2.5 ~ 5.5 V
VIL2
-0.3
-
0.3
V
V
V
VDDIO = 1.8 V
VDD
+
2.0
1.5
-
-
VDD = VDDIO = VBAT = 5.5 V
VDD = VDDIO = VBAT = 3.0 V
0.3
Input High Voltage
(TTL input)
VIH1
VDD
+
0.3
Input High Voltage
(TTL input for PE8
~ PE13)
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO
0.3
+
VIH2
VHY
VIL3
1.0
-
VDDIO = 1.8 V
Hysteresis voltage of
PA, PB, PC, PD,PE,
PF (Schmitt input)
0.2VDD
V
0
0
-
-
0.8
0.4
V
VDD = 4.5 V
VDD = 2.5 V
Input Low Voltage
XT1[*2]
VDD
0.3
+
3.5
-
-
V
VDD = 5.5 V
VDD = 3.0 V
Input High Voltage
XT1[*2]
VIH3
VDD
0.3
+
2.4
0.6
0
X32 Output Pin
VXOUT
0.9
V
Input Low Voltage
X32I[*4]
VXOUT -
0.3
VIL4
-
V
Input High Voltage
X32I[*4]
VXOUT
+0.3
VIH4
1.8
V
Negative going
threshold
VIL5
-0.3
-
-
0.2 VDD
V
(Schmitt input),
nRST
Positive going
threshold
VDD
+
VIH5
0.7 VDD
V
0.3
(Schmitt input),
nRST
Internal nRESET
pin pull up resistor
RRST
40
150
kΩ
Input Low Voltage
(Schmitt input)
VIL6
-0.3
-
-
-
0.3 VDD
V
VDD = VDDIO = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V ~ 5.5V
Input Low Voltage
0.3
VDDIO
VIL7
-0.3
V
V
(Schmitt input for
PE8~ PE13)
Input High Voltage
(Schmitt input)
VDD
+
VIH6
0.7 VDD
VDD = VDDIO = VBAT = 2.5 ~ 5.5 V
0.3
Jan. 06, 2016
Page 118 of 144
Rev.1.00
M4TK
SPECIFICATION
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Input Low Voltage
0.7
VDDIO
VDDIO
0.3
+
VIH7
-
V
VDDIO = 1.8 V ~ 5.5V
(Schmitt input for
PE8~ PE13)
Source Current
(Quasi-bidirectional
Mode)
ISR11
ISR12
ISR13
-300
-50
-400
-80
-
-
-
VDD = VDDIO = VBAT = 4.5 V, VS = 2.4 V
VDD = VDDIO = VBAT = 2.7 V, VS = 2.2 V
VDD = VDDIO = VBAT = 2.5 V, VS = 2.0 V
A
A
A
-40
-73
Source Current
(Quasi-bidirectional
Mode for PE8~
PE13)
VDD = VBAT = 2.5 ~ 5.5 V
ISR14
-11
-19
A
VDDIO = 1.8 V, VS = 1.6 V
Source Current
(Push-pull Mode)
ISR21
ISR22
ISR23
-20
-3
-26
-5.2
-5
-
-
-
mA
mA
mA
VDD = VDDIO = VBAT = 4.5 V, VS = 2.4 V
VDD = VDDIO = VBAT = 2.7 V, VS = 2.2 V
VDD = VDDIO = VBAT = 2.5 V, VS = 2.0 V
-2.5
Source Current
(Set IO as Push-pull
Mode and basic
driving strength
VDD = VBAT = 2.5 ~ 5.5 V
ISR24
-1
-1.5
mA
VDDIO = 1.8 V, VS = 1.6 V
Only for
PE8~PE13)
Source Current
VDD = VBAT = 2.5 ~ 5.5 V
ISR31
ISR32
ISR33
ISR34
-28
-5.3
-4.9
-1.5
-47
-8.8
-8.1
-2.5
-
-
-
mA
mA
mA
mA
(Set IO as Push-pull
Mode and high
driving strength
VDDIO = 4.5 V, VS = 2.4 V
VDD = VBAT = 2.5 ~ 5.5 V
Only for
PE8~PE13)
VDDIO = 2.7 V, VS = 2.2 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 2.5 V, VS = 2.0 V
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V, VS = 1.6 V
Sink Current
ISK11
ISK12
ISK13
10
6
17
11
10
-
-
-
mA
mA
mA
VDD = VDDIO = VBAT = 4.5 V, VS = 0.45 V
VDD = VDDIO = VBAT = 2.7 V, VS = 0.45 V
VDD = VDDIO = VBAT = 2.5 V, VS = 0.45 V
(Quasi-bidirectional,
Open-Drain and
Push-pull Mode)
5
Sink Current
VDD = VBAT = 2.5 ~ 5.5 V
ISK14
3.6
6
mA
(Only for
PE8~PE13)
VDDIO = 1.8 V, VS = 0.45 V
Sink Current
VDD = VBAT = 2.5 ~ 5.5 V
ISK21
ISK22
ISK23
14.7
9.2
24.5
15.3
14.1
mA
mA
mA
(Set IO as high
driving strength
VDDIO = 4.5 V, VS = 0.45 V
VDD = VBAT = 2.5 ~ 5.5 V
Only for
PE8~PE13)
VDDIO = 2.7 V, VS = 0.45 V
VDD = VBAT = 2.5 ~ 5.5 V
8.5
VDDIO = 2.5 V, VS = 0.45 V
Jan. 06, 2016
Page 119 of 144
Rev.1.00
M4TK
SPECIFICATION
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VDD = VBAT = 2.5 ~ 5.5 V
VDDIO = 1.8 V, VS = 0.45 V
ISK24
5.4
9
mA
Notes:
1. nRESET pin is a Schmitt trigger input.
2. XT1_IN is a CMOS input.
3. All pins can source a transition current when they are being externally driven from 1 to 0. In the condition of
VDD=5.5V, the transition current reaches its maximum value when VIN approximates to 2V.
4. If X32I is as external clock input, the input high voltage should be lower than 1.8V to avoid chip damage.
Jan. 06, 2016
Page 120 of 144
Rev.1.00
M4TK
8.3 AC Electrical Characteristics
8.3.1
External 4~24 MHz High Speed Crystal (HXT) Input Clock
tCLCL
tCLCH
90%
10%
VIH
tCLCX
VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
Parameter
Min
Typ
Max
-
Unit
ns
ns
ns
ns
V
Test Conditions
tCHCX
tCLCX
tCLCH
tCHCL
VIH
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
Input High Voltage
Input Low Voltage
10
-
-
-
-
-
-
-
-
-
-
10
-
2
15
15
VDD
2
0.7VDD
0
VIL
0.3VDD
V
8.3.2
External 4~20 MHz High Speed Crystal (HXT) Oscillator
Symbol
VHXT
Parameter
Operation Voltage
Temperature
Min.
2.5
-40
-
Typ.
Max
5.5
105
-
Unit
V
Test Conditions
-
-
-
TA
℃
-
12 MHz, VDD = 5.5V
12 MHz, VDD = 3.3V
-
2
mA
mA
MHz
IHXT
Operating Current
Clock Frequency
-
0.8
-
-
fHXT
4
20
8.3.2.1 Typical Crystal Application Circuits
Crystal
C1
10~20 pF
C2
4 MHz ~ 20 MHz
10~20 pF
Jan. 06, 2016
Page 121 of 144
Rev.1.00
M4TK
XTAL1
XTAL2
4~20 MHz
Crystal
C1
C2
Vss
Vss
Figure 8.3-1 Typical Crystal Application Circuit
8.3.3
22.1184 MHz Internal High Speed RC Oscillator (HIRC)
Symbol
Parameter
Supply Voltage
Center Frequency
Min
1.62
-
Typ
1.8
Max
Unit
V
Test Conditions
VHRC
fHRC
IHRC
1.98
-
22.1184
-
MHz
%
-
TA = 25 ℃, VDD = 5 V
-1
+1
+2
-
Calibrated Internal
TA = -40 ~ 105
Oscillator Frequency
-2
-
-
%
VDD = 2.5 V ~ 5 .5 V
TA = 25 ℃, VDD = 5 V
Operating Current
790
μA
HIRC oscillator accuracy vs. temperature
0.80%
0.60%
0.40%
0.20%
0.00%
-0.20%
-0.40%
-0.60%
-0.80%
-1.00%
-1.20%
-1.40%
-50
0
50
100
150
Max
Min
TA ℃
Note: Number of test samples: 10.
Figure 8.3-2 HIRC Accuracy vs. Temperature
Jan. 06, 2016
Page 122 of 144
Rev.1.00
M4TK
8.3.4
32.768 kHz External Low Speed Crystal (LXT) Input Clock
tCLCL
tCLCH
90%
10%
Xin_VIH
tCLCX
Xin_VIL
tCHCL
tCHCX
Note: Duty cycle is 50%.
Symbol
tCHCX
tCLCX
Parameter
Min
TBD
TBD
TBD
TBD
Xout+0.3
0
Typ
Max
-
Unit
ns
ns
ns
ns
V
Test Conditions
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
-
-
-
-
-
-
-
-
-
-
-
tCLCH
TBD
TBD
1.8
tCHCL
Xin_VIH
Xin_VIL
Xout
LXT Input Pin Input High Voltage
LXT Input Pin Input Low Voltage
LXT Output Pin
Xout-0.3
0.9
V
0.6
V
8.3.5
32.768 kHz External Low Speed Crystal (LXT) Oscillator
Parameter
Condition
Min.
2.5
Typ.
Max.
5.5
Unit
Operation Voltage VBAT
Operation Temperature
Operation Current
-
-
-
-
V
℃
-40
105
32.768KHz at VBAT=5V
External crystal
1.6
A
Clock Frequency
-
32.768
-
kHz
8.3.5.1 LXT Typical Crystal Application Circuits
CRYSTAL
C1
C2
10~20 pF
32.768 kHz
10~20 pF
Jan. 06, 2016
Page 123 of 144
Rev.1.00
M4TK
X32_IN
X32_OUT
Crystal
C1
C2
Vss
Vss
Figure 8.3-3 Typical Crystal Application Circuit
8.3.6
10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
VLRC
Parameter
Supply Voltage
Center Frequency
Min
2.5
-
Typ
-
Max
5.5
-
Unit
V
Test Conditions
-
-
10
kHz
VDD = 2.5 V ~ 5.5 V
-30
-50
-
-
+30
+50
%
%
TA = 25
fLRC
Oscillator Frequency
VDD = 2.5 V ~ 5.5 V
TA = -40 ~ +105
Jan. 06, 2016
Page 124 of 144
Rev.1.00
M4TK
8.4 Analog Characteristics
8.4.1 12-bit SAR ADC
Symbol
Parameter
Min
Typ
Max
Unit
Bit
Test Condition
-
Resolution
12
-
DNL
INL
EO
EG
EA
Differential Nonlinearity Error
Integral Nonlinearity Error
Offset Error
-
-
-
-
-
-
±2
±2
-
LSB
LSB
LSB
LSB
LSB
-
-
-
-
3
-
Gain Error (Transfer Gain)
Absolute Error
-3
-
-
4
-
-
-
Monotonic
Guaranteed
-
-
-
-
-
21
AVDD = 4.5~5.5 V
AVDD = 2.5~5.5 V
FADC
ADC Clock Frequency
MHz
8.4
AVDD = 4.5~5.5 V
TCONV = 21 clock
FADC = 21 Mhz
-
-
-
1000
400
kSPS
FS
Sample Rate (FADC/TCONV)
AVDD = 2.5~5.5 V
TCONV = 21 clock
FADC = 8.4 Mhz
-
kSPS
1/FADC
1/FADC
Default: 6 (1/FADC
)
TACQ
Acquisition Time (Sample Stage)
Total Conversion Time
2~9
EADC_SCTLx[31:24]=0
TCONV = TACQ+ 15
TCONV
16~23
Default: 21 (1/FADC)
EADC_SCTLx[31:24]=0
#1
AVDD
Supply Voltage
2.5
-
2.8
-
5.5
V
mA
V
-
#1
IDDA
Supply Current (Avg.)
Analog Input Voltage
Reference Voltage
Input Capacitance
Input Load
-
0
-
VREF
AVDD
-
AVDD = 5 V
#1
VIN
-
VREF
2.5
-
-
V
AVDD = 5 V
#1
CIN
6
pF
kΩ
-
-
#1
RIN
-
6.5
-
Note:
#1: Design by guarantee, no test in production.
Jan. 06, 2016
Page 125 of 144
Rev.1.00
M4TK
EF (Full scale error) = EO + EG
Gain Error Offset Error
EG
EO
4095
4094
4093
4092
Ideal transfer curve
7
6
5
4
3
2
1
ADC
output
code
Actual transfer curve
DNL
1 LSB
4095
Analog input voltage
(LSB)
Offset Error
EO
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve
and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from
the actual transfer curve.
Typical connection diagram using the ADC
VDD
(1)
RIN
12-bit
Converter
AINx
(1)
CIN
Figure 8.4-1 Typical connection diagram using the ADC
(1) Refer to ADC spec for the values of RIN, CIN
Jan. 06, 2016
Page 126 of 144
Rev.1.00
M4TK
8.4.2
LDO
Symbol
Parameter
DC Power Supply
Output Voltage
Temperature
Min
2.5
Typ
-
Max
5.5
Unit
V
Test Condition
VDD
VLDO
TA
-
-
1.62
-40
1.8
25
1.98
105
V
Notes:
1. It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 1μF Capacitor must be connected between LDO_CAP pin and the closest VSS
pin of the device.
8.4.3
Low Voltage Reset
Symbol
AVDD
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
TA
-40
-
25
105
5
-
ILVR
Quiescent Current
1
AVDD = 5.5 V
TA = 105 ℃
TA = 25 ℃
TA = -40 ℃
2.00
1.90
1.70
2.20
2.00
1.90
2.45
2.10
2.10
VLVR
Threshold Voltage
V
V
8.4.4
Brown-out Detector
Symbol
AVDD
TA
Parameter
Supply Voltage
Temperature
Min
0
Typ
-
Max
5.5
Unit
V
Test Condition
-
℃
μA
V
-40
-
25
105
140
4.6
-
IBOD
Quiescent Current
-
AVDD = 5.5 V
4.2
3.5
2.55
2.05
4.3
3.6
2.6
2.1
4.4
3.7
2.7
2.2
4.5
3.8
2.75
2.25
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
BOV_VL [1:0] = 11
BOV_VL [1:0] = 10
BOV_VL [1:0] = 01
BOV_VL [1:0] = 00
3.9
V
Brown-out Voltage
(Falling edge)
VBOD
2.85
2.35
4.7
V
V
V
4.0
V
Brown-out Voltage
(Rising edge)
VBOD
2.9
V
2.4
V
8.4.5
Power-on Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
Jan. 06, 2016
Page 127 of 144
Rev.1.00
M4TK
℃
TA
Temperature
-40
1.6
25
2
105
2.4
-
-
VPOR
Reset Voltage
V
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
-
-
-
-
100
mV
V/ms
ms
VDD Raising Rate to Ensure
Power-on Reset
0.025
0.5
-
-
Minimum Time for VDD Stays at
VPOR to Ensure Power-on Reset
VDD
tPOR
RRVDD
VPOR
Time
Figure 8.4-2 Power-up Ramp Condition
8.4.6
Temperature Sensor
Symbol
Parameter
Temperature
Current Consumption
Gain
Min
-40
-
Typ
-
Max
105
-
Unit
℃
Test Condition
TA
ITEMP
16
μA
-
-
mV/℃
mV
-1.55
735
-1.672
748
-1.75
755
Offset
TA = 0 ℃
Note:
1. The temperature sensor formula for the output voltage (Vtemp) is as below equation.
2. Vtemp (mV) = Gain (mV/ ) x Temperature ( ) + Offset (mV)
Jan. 06, 2016
Page 128 of 144
Rev.1.00
M4TK
8.4.7
Comparator
Symbol
Parameter
Min
2.5
-40
-
Typ
-
Max
5.5
105
70
Unit
V
Test Condition
VCMP
TA
Supply Voltage
Temperature
℃
25
35
10
-
-
ICMP
VOFF
VSW
VCOM
-
Operation Current
Input Offset Voltage
Output Swing
μA
mV
V
AVDD = 5 V
AVDD = 5 V
0.1
0.1
40
AVDD - 0.1
AVDD – 0.1
-
-
-
-
Input Common Mode Range
DC Gain
-
V
70*
dB
VCM = 1.2 V,
VDIFF = 0.1 V
TPGD
Propagation Delay
-
125
-
ns
VHYS
TSTB
Hysteresis
Stable time
-
-
±40
±60
1
mV
AVDD = 5 V
AVDD = 5 V
0.26
μs
Note:
*Guaranteed by design, not tested in production.
8.4.8
12-bit DAC
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Condition
AVDD
NR
Analog Supply Voltage
Resolution
2.5
-
5.5
12
bit
V
VREF
Reference Supply Voltage
2.5
-
AVDD
-1
-
-
-
-
-
-
-
-
-
-
±0.5
10-bit, buffer OFF
12-bit, buffer OFF
10-bit, buffer OFF
12-bit, buffer OFF
10-bit, buffer OFF
12-bit, buffer OFF
10-bit, buffer OFF
12-bit, buffer OFF
10-bit, buffer OFF
12-bit, buffer OFF
DNL
INL
OE
GE
AE
Differential Non-linearity Error
Integral Non-linearity Error
Offset Error
LSB
LSB
LSB
±0.5
-2.5
±1
-
-
-
-
-
-
-
-
±2.5
+1
+2
-2
Gain Error
LSB
LSB
-8
-2
Absolute Error
-8
-
Monotonic
Output Voltage
Resistive Load
Output Impedance
Capacitive Load
10-bit guaranteed
VREF – 0.15
VO
0.1
7.5
-
V
Buffer ON
Buffer ON
RLOAD
RO
-
8.2
-
-
kΩ
kΩ
pF
22.5
20
CLOAD
-
Buffer OFF
Jan. 06, 2016
Page 129 of 144
Rev.1.00
M4TK
-
-
-
--
-
50
Buffer ON
AVDD = 5.5V, buffer ON
VREF = 5.5V
IDDA
IREF
Analog Supply Current
350
260
uA
uA
Reference Supply Current
-
Transition between the
lowest and the highest
input codes when VO
reaches final value ±1
LSB
TSTAB
Settling Time
-
4
8
us
Transition between
adjacent codes
FS
Update Rate
-
-
-
-
1
MSPS
us
TWAKEUP
Wake-up Time
10
8.4.9
Internal Voltage Reference
Symbol
VVREF
Parameter
Min.
2.5
Typ.
Max.
5.5
Unit
V
Test Condition
-
AVDD
Vref1
Vref2
Vref3
Vref4
Vref(2.56V)
2.483
1.986
2.98
2.560
2.048
3.072
4.096
2.637
2.109
3.164
4.219
V
AVDD >= 2.9V
AVDD >= 2.5V
AVDD >= 3.4V
AVDD >= 4.5V
Vref(2.048V)
Vref(3.072V)
Vref(4.096V)
V
V
3.973
V
8.4.10 USB PHY
8.4.10.1 Low-full-Speed DC Electrical Specifications
Symbol
Parameter
Input High (driven)
Min.
2.0
-
Typ.
Max.
Unit
V
Test Conditions
VIH
VIL
VDI
-
-
-
-
Input Low
0.8
V
-
Differential Input Sensitivity
0.2
V
|PADP-PADM|
Differential
VCM
0.8
0.8
-
-
2.5
2.0
V
V
Includes VDI range
-
Common-mode Range
Single-ended Receiver
Threshold
VSE
Receiver Hysteresis
-
0
200
mV
V
-
VOL
VOH
Output Low (driven)
-
-
0.3
3.6
2.0
1.575
-
-
Output High (driven)
Output Signal Cross Voltage
Pull-up Resistor
2.8
1.3
1.425
-
V
-
VCRS
RPU
ZDRV
CIN
-
V
-
-
-
kΩ
Ω
Driver Output Resistance
Transceiver Capacitance
10
-
Steady state drive*
Pin to GND
-
20
pF
*Driver output resistance doesn’t include series resistor resistance.
Jan. 06, 2016
Page 130 of 144
Rev.1.00
M4TK
8.4.10.2 USB Full-Speed Driver Electrical Characteristics
Symbol
Parameter
Min.
4
Typ.
Max.
20
Unit
ns
Test Conditions
CL=50p
TFR
TFF
Rise Time
Fall Time
-
-
-
4
20
ns
CL=50p
TFRFF
Rise and Fall Time Matching
90
111.11
%
TFRFF=TFR/TFF
8.4.10.3 USB LDO Specification
Symbol
VBUS
Parameter
VBUS Pin Input Voltage
LDO Output Voltage
Min.
4.0
2.97
-
Typ.
5.0
Max.
5.5
3.63
-
Unit
Test Conditions
V
V
-
-
-
VDD33
Cbp
3.3
External Bypass Capacitor
1.0
uF
Jan. 06, 2016
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8.5 Flash DC Electrical Characteristics
Symbol
Parameter
Supply Voltage
Endurance
Min
Typ
Max
Unit
V
Test Condition
[2]
VFLA
1.62
1.8
1.98
NENDUR
TRET
20,000
-
-
cycles[1]
year
ms
Data Retention
Page Erase Time
Program Time
Read Current
Program Current
Erase Current
100
20
60
-
-
TERASE
TPROG
IDD1
-
TA = 25
-
us
-
13.5
mA
IDD2
-
10
12
-
-
mA
IDD3
-
mA
Notes:
1. Number of program/erase cycles.
2. VFLA is source from chip LDO output voltage.
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8.6 I2C Dynamic Characteristics
Standard Mode[1][2]
Fast Mode[1][2]
Symbol
Parameter
Unit
Min.
4.7
Max.
-
Min.
1.2
Max.
tLOW
SCL low period
SCL high period
-
uS
uS
uS
uS
uS
uS
nS
uS
nS
nS
pF
tHIGH
tSU; STA
tHD; STA
tSU; STO
tBUF
4
4.7
4
-
0.6
-
Repeated START condition setup time
START condition hold time
STOP condition setup time
Bus free time
-
1.2
-
-
-
-
0.6
4
0.6
-
4.7[3]
250
0[4]
-
-
1.2[3]
-
tSU;DAT
tHD;DAT
tr
Data setup time
-
100
-
Data hold time
3.45[5]
1000
300
400
0[4]
0.8[5]
300
300
400
SCL/SDA rise time
20+0.1Cb
tf
SCL/SDA fall time
-
-
-
Cb
Capacitive load for each bus line
-
Notes:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher
than 8 MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
Figure 8.6-1 I2C Timing Diagram
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8.7 SPI Dynamic Characteristics
8.7.1 Dynamic Characteristics of Data Input and Output Pin
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI MASTER MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20MHz
22.5
-
27.5
ns
tDS
Data input setup time
Data input hold time
Data output valid time
Data output hold time
2
4
-
-
-
-
-
-
-
ns
ns
ns
ns
tH(MI)
tV
1
-
tH(MO)
0
SPI MASTER MODE (VDD = 3.0~3.6 V, 30 PF LOADING CAPACITOR)
tW(SCKH)
tW(SCKL)
SPI high and low time, peripheral clock
= 20MHz
22.5
-
27.5
ns
tDS
Data input setup time
Data input hold time
Data output valid time
Data output hold time
2
4
ns
ns
ns
ns
tH(MI)
tV
-
-
1
-
tH(MO)
0
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
tr(SCK)
tf(SCK)
SPI data output
(SPI_MOSI)
Data Valid
Data Valid
tDS
tDH
SPI data input
(SPI_MISO)
Data Valid
Data Valid
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
tV
SPI data output
(SPI_MOSI)
Data Valid
tDH
Data Valid
Data Valid
tDS
SPI data input
(SPI_MISO)
Data Valid
Figure 8.7-1 SPI Master Mode Timing Diagram
Jan. 06, 2016
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SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
SPI SLAVE MODE (VDD = 4.5 V~5.5V, 30 PF LOADING CAPACITOR)
Peripheral
clock
tSS
Slave select setup time
Slave select hold time
3
2
-
-
-
-
Peripheral
clock
tSH
tDS
Data input setup time
Data input hold time
Data output access time
Data output valid time
Data output hold time
2
5.5
-
-
-
-
ns
ns
ns
ns
ns
tH(SI)
ta(SO)
tV
-
-
18.5-
-
18
24.5
-
-
tH(SO)
6
SPI SLAVE MODE (VDD = 3.0 V ~ 3.6 V, 30 PF LOADING CAPACITOR)
Peripheral
clock
tSS
Slave select setup time
Slave select hold time
3
2
-
-
-
-
Peripheral
clock
tSH
tDS
Data input setup time
Data input hold time
Data output access time
Data output valid time
Data output hold time
2
6
-
-
-
-
-
ns
ns
ns
ns
ns
tH(SI)
ta(SO)
tV
-
24
30
-
-
23
-
tH(SO)
7
Jan. 06, 2016
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SSACTPOL=1
SSACTPOL=0
tSS
tSH
SPI SS
CLKPOL=0
TXNEG=1
RXNEG=0
SPI Clock
CLKPOL=1
TXNEG=0
RXNEG=1
tV
SPI data output
(SPI_MISO)
Data Valid
Data Valid
Data Valid
tDH
tDS
SPI data input
(SPI_MOSI)
Data Valid
SSACTPOL=1
tSS
tSH
SPI SS
SSACTPOL=0
CLKPOL=0
TXNEG=0
RXNEG=1
SPI Clock
CLKPOL=1
TXNEG=1
RXNEG=0
ta(so)
tV
SPI data output
(SPI_MISO)
Data Valid
tDH
Data Valid
tDS
SPI data input
(SPI_MOSI)
Data Valid
Data Valid
Figure 8.7-2 SPI Slave Mode Timing Diagram
Jan. 06, 2016
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8.8
I2S Dynamic Characteristics
Symbol
Parameter
I2S clock high time
I2S clock low time
WS valid time
Min
42
37
7
Max
Unit
Test Conditions
tw(CKH)
tw(CKL)
tv(WS)
th(WS)
tsu(WS)
th(WS)
-
-
-
-
-
-
Master fPCLK = MHz, data: 24 bits, audio
frequency = 256 kHz
Master mode
Master mode
Slave mode
Slave mode
ns
WS hold time
1
WS setup time
WS hold time
34
0
I2S slave input clock
duty cycle
DuCy(SCK)
25
75
%
Slave mode
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
th(SD_ST)
tv(SD_MT)
th(SD_MT)
0
0
0
0
-
-
-
Master receiver
Data input setup time
Data input hold time
Slave receiver
-
Master receiver
-
Slave receiver
ns
Data output valid time
Data output hold time
Data output valid time
Data output hold time
32
-
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
16
-
5
-
0
Jan. 06, 2016
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CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
tv(WS)
WS output
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_MR)
Bitn receive
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_MR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.8-1 I2S Master Mode Timing Diagram
CPOL = 0
CPOL = 1
tw(CKH)
tw(CKL)
th(WS)
WS input
SDtransmit
tv(SD_ST)
Bitn transmit
th(SD_SR)
Bitn receive
tsu(WS)
th(SD_ST)
LSB transmit(2)
MSB transmit
MSB receive
LSB transmit
tsu(SD_SR)
SDreceive
LSB receive(2)
LSB receive
Figure 8.8-2 I2S Slave Mode Timing Diagram
Jan. 06, 2016
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9 PACKAGE DIMENSIONS
9.1 LQFP 100L (14x14x1.4 mm footprint 2.0 mm)
Jan. 06, 2016
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9.2 LQFP 64L (10x10x1.4 mm footprint 2.0 mm)
Jan. 06, 2016
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9.3 LQFP 64L (7x7x1.4 mm footprint 2.0 mm)
Jan. 06, 2016
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9.4 LQFP 48L (7x7x1.4mm footprint 2.0mm)
H
36
25
37
24
H
13
48
12
1
Controlling dimension
:
Millimeters
Dimension in inch
Dimension in mm
Symbol
Min Nom Max Min Nom Max
A
1
0.002 0.004 0.006 0.05
0.053 0.055 0.057 1.35
0.10 0.15
A
2
1.40
1.45
0.25
0.20
7.10
7.10
0.65
9.10
A
0.006
0.004
0.008 0.010 0.15 0.20
b
c
D
0.006
0.10 0.15
0.008
7.00
7.00
6.90
6.90
0.35
0.272 0.276 0.280
0.272 0.276 0.280
E
0.020
0.354
0.354
0.014
0.350
0.350
0.018
0.026
0.50
e
H
D
0.358 8.90 9.00
0.358 8.90 9.00
9.10
0.60 0.75
1.00
E
H
0.024 0.030
0.45
0
L
L
Y
0.039
0.004
7
1
0.10
7
0
0
Jan. 06, 2016
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10 REVISION HISTORY
Date
Revision
Description
2016.01.06
1.00
Preliminary version.
Jan. 06, 2016
Page 143 of 144
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M4TK
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Jan. 06, 2016
Page 144 of 144
Rev.1.00
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