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MAX8952降压型调节器 [ETC]

; - 12号的铝制车身绘（ RAL 7032 ）
MAX8952降压型调节器
型号： MAX8952降压型调节器
厂家： ETC    ETC
描述：


- 12号的铝制车身绘（ RAL 7032 ）
文件： 总64页 (文件大小：3511K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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19-5318; Rev 0; 6/10  
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♦ 27੆ཆĂ3nn!y!3nn!XMQॖᓤ  
``````````````````````````````````` ።፿  
``````````````````````````````` 
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ຳ
ۇ
QD  
PART  
TEMP RANGE  
PIN-PACKAGE  
16 Bump WLP  
(0.5mm pitch)  
MAX8952EWE+T  
-40°C to +85°C  
,
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ာᇄ໺)Qc*0९੝SpIT
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``````````````````````````` 
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``````````````````````````````` ፛୭๼ᒙ  
TOP VIEW  
(BUMPS ON BOTTOM)  
2.5V TO  
5.5V  
1.8V TO  
3.6V  
VID1  
A3  
IN1  
A1  
AGND  
A2  
IN2  
A4  
+
MAX8952  
IN2  
V
DD  
10μF  
10μF  
0.1μF  
0.1μF  
1μH  
10μF  
2.5V TO  
5.5V  
V
LX  
OUT  
SNS+  
B1  
EN  
B2  
LX  
B3  
LX  
B4  
SCL  
SDA  
(0.77V TO  
1.40V)  
0.1μF  
11Ω  
PGND  
IN1  
PGND  
0.1μF  
PGND  
SNS-  
C1  
VID0  
C2  
SYNC  
EN  
C3  
SCL  
D3  
C4  
SYNC  
D4  
SNS+  
SNS-  
VID0  
CPU  
V
DD  
SDA  
D2  
VID1  
D1  
AGND  
WLP 0.5mm PITCH  
________________________________________________________________ Maxim Integrated Products  
۾
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ABSOLUTE MAXIMUM RATINGS  
IN1, IN2 to AGND..................................................-0.3V to +6.0V  
to AGND.........................................................-0.3V to +4.0V  
Operating Temperature Range ...........................-40°C to +85°C  
V
DD  
Junction to Ambient Thermal Resistance (θ ) (Note 1)...49°C/W  
JA  
LX, SNS+, VID0, VID1, EN to AGND..........-0.3V to (V  
SCL, SDA, SYNC to AGND.........................-0.3V to (V  
PGND, SNS- to AGND...........................................-0.3V to +0.3V  
RMS LX Current ..............................................................2500mA  
+ 0.3V)  
+ 0.3V)  
Junction Temperature......................................................+150°C  
Storage Temperature Range.............................-65°C to +150°C  
Soldering Temperature (reflow) .......................................+260°C  
IN1  
DD  
Continuous Power Dissipation (T = +70°C)  
A
NBY9:63  
16-Bump WLP 0.5mm Pitch  
(derate 20.4mW/°C above +70°C).........................1632mW  
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-  
layer board. For detailed information on package thermal considerations, refer to china.maxim-ic.com/thermal-tutorial.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
(V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at  
DD A  
IN1  
IN2  
AGND  
PGND  
T
A
= +25°C.) (Note 2)  
PARAMETER  
IN1, IN2 Operating Range  
CONDITIONS  
MIN  
2.5  
TYP  
MAX  
5.5  
UNITS  
V
V
V
Operating Range  
1.8  
3.6  
DD  
V
Undervoltage Lockout  
DD  
V
falling  
falling  
0.54  
2.10  
0.865  
50  
1.35  
2.20  
V
DD  
(UVLO) Threshold  
V
UVLO Hysteresis  
mV  
V
DD  
IN_ Undervoltage Lockout  
(UVLO) Threshold  
V
V
2.15  
IN_  
IN1  
IN_ UVLO Hysteresis  
70  
mV  
μA  
T
A
T
A
T
A
T
A
T
A
T
A
= +25°C  
= +85°C  
= +25°C  
= +85°C  
= +25°C  
= +85°C  
0.01  
0.01  
0.25  
0.25  
0.35  
0.35  
1
1
1
= V  
= 5.5V,  
IN2  
V
Shutdown Supply Current  
DD  
EN = V  
= AGND  
DD  
IN1, IN2 Shutdown Supply  
Current  
V
= V  
= 5.5V,  
IN1  
IN2  
μA  
μA  
EN = V  
= AGND  
DD  
V
V
= V  
= 5.5V, SCL = SDA =  
IN1  
IN2  
IN1, IN2 Standby Supply Current  
, EN = AGND, I2C ready  
DD  
V
= V  
= V  
= 3.6V,  
DD  
IN1  
IN2  
T
= +25°C  
= +85°C  
0.02  
0.02  
1
A
A
V
Standby Supply Current  
μA  
SCL = SDA = V , EN = AGND,  
DD  
DD  
I2C ready  
T
LOGIC INTERFACE  
EN, VID0, VID1  
SYNC, SCL, SDA  
EN, VID0, VID1  
SYNC, SCL, SDA  
1.4  
V
V
= V  
= 2.5V to 5.5V,  
IN1  
DD  
IN2  
Logic Input High Voltage (V  
)
IH  
V
V
= 1.8V to 3.6V  
0.7 x V  
DD  
0.4  
V
V
= V = 2.5V to 5.5V,  
IN1  
DD  
IN2  
Logic Input Low Voltage (V )  
IL  
= 1.8V to 3.6V  
0.3 x V  
DD  
T
A
T
A
= +25°C  
= +85°C  
-1  
0.01  
0.01  
+1  
SDA, SCL, SYNC Logic Input  
Current  
V
= 0V or V = 3.6V,  
IL IH  
μA  
EN = AGND  
2
_______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
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NBY9:63  
ELECTRICAL CHARACTERISTICS (continued)  
(V  
IN1  
= V  
= 3.6V, V  
= V  
= 0V, V = 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =  
DD A A  
IN2  
AGND  
PGND  
+25°C.) (Note 2)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Controlled by I2C command:  
VID0_PD = 1  
VID1_PD = 1  
VID0, VID1, EN Logic Input  
Pulldown Resistor  
200  
320  
450  
kΩ  
EN_PD = 1  
2
I C INTERFACE  
SDA Output Low Voltage  
I2C Clock Frequency  
I
= 3mA  
0.03  
0.1  
0.4  
V
SDA  
400  
kHz  
Bus-Free Time Between START  
and STOP  
t
t
1.3  
0.6  
μs  
μs  
BUF  
Hold Time REPEATED START  
Condition  
HD_STA  
SCL Low Period  
SCL High Period  
t
t
1.3  
0.6  
0.2  
0.2  
μs  
μs  
LOW  
HIGH  
Setup Time REPEATED START  
Condition  
t
0.6  
0.1  
μs  
SU_STA  
SDA Hold Time  
t
t
t
0
-0.01  
0.05  
0.1  
μs  
μs  
μs  
HD_DAT  
SU_DAT  
SU_STO  
SDA Setup Time  
0.1  
0.6  
Setup Time for STOP Condition  
STEP-DOWN DC-DC REGULATOR  
FPWM_EN_ = 0, V  
FPWM_EN_ = 1, V  
= 1.27V, no switching  
54  
9
80  
μA  
OUT  
IN1 + IN2  
Supply Current  
= 1.27V, f = 3.25MHz  
mA  
OUT  
sw  
Minimum Output Capacitance  
Required for Stability  
V
= 0.77V to 1.40V,  
= 0 to 2.5A  
OUT  
10  
μF  
I
OUT  
OUT Voltage Range  
10mV steps  
Rising, 50mV hysteresis (typ)  
0.770  
1.65  
1.400  
1.9  
V
V
Output Overvoltage Protection  
1.8  
_______________________________________________________________________________________  
3
3/6Bଢ଼ኹቯ
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ELECTRICAL CHARACTERISTICS (continued)  
(V  
IN1  
= V  
= 3.6V, V  
= V  
= 0V, V = 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =  
DD A A  
IN2  
AGND  
PGND  
+25°C.) (Note 2)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
%
No load, V  
FPWM_EN_ = 1  
= 2.5V to 5.5V, V  
= 1.27V,  
IN_  
OUT  
OUT  
OUT  
-0.5  
+0.5  
NBY9:63  
No load, V = 2.5V to 5.5V, V  
= 0.77V,  
= 1.40V,  
IN_  
OUT Voltage Accuracy  
Load Regulation  
-1.0  
-0.5  
+1.0  
+0.5  
FPWM_EN_ = 1  
No load, V = 2.5V to 5.5V, V  
IN_  
FPWM_EN_ = 1  
R is the resistance from LX to SNS+ (output)  
L
R /25  
L
V/A  
RAMP[2:0] = 000  
RAMP[2:0] = 001  
RAMP[2:0] = 010  
RAMP[2:0] = 011  
RAMP[2:0] = 100  
RAMP[2:0] = 101  
RAMP[2:0] = 110  
RAMP[2:0] = 111  
32.50  
16.25  
8.125  
4.063  
2.031  
1.016  
0.508  
0.254  
RAMP Timer  
mV/μs  
Peak Current Limit  
(p-Channel MOSFET)  
3.45  
2.7  
4.2  
3.6  
2.5  
4.8  
4.5  
3.0  
A
A
A
Valley Current Limit  
(n-Channel MOSFET)  
Hysteretic mode  
PWM mode  
Negative Current Limit  
(n-Channel MOSFET)  
2.0  
n-Channel Zero-Crossing  
Threshold  
50  
mA  
Ω
LX pFET On-Resistance  
IN2 to LX, I = -200mA  
LX  
0.08  
0.06  
0.16  
0.12  
+1  
FPWM_EN_ = 0,  
LX nFET On-Resistance  
Ω
LX to PGND, I = 200mA  
LX  
T
T
= +25°C  
= +85°C  
-1  
0.03  
0.05  
3.25  
A
LX Leakage  
V
= 5.5V or 0V  
μA  
LX  
A
Internal oscillator, PWM mode  
2.82  
2.43  
3.56  
4.06  
Internal oscillator, power-save mode before entering  
PWM mode  
3.25  
Operating Frequency  
13MHz = f  
, SYNC[1:0] = 01  
f
f
f
/4  
MHz  
SYNC  
SYNC  
SYNC  
SYNC  
19.2MHz = f  
, SYNC[1:0] = 10 or 11  
/6  
/8  
SYNC  
26MHz = f  
, SYNC[1:0] = 00  
SYNC  
4
_______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
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ஂ໭Lj  
ᄋ৙
ތ
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࣡
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Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
ELECTRICAL CHARACTERISTICS (continued)  
(V  
IN1  
= V  
= 3.6V, V  
= V  
= 0V, V = 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =  
DD A A  
IN2  
AGND  
PGND  
+25°C.) (Note 2)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Forced-PWM mode (FPWM_EN_ = 1), minimum duty  
cycle = 0%  
Minimum Duty Cycle  
Maximum Duty Cycle  
16  
%
60  
30  
%
ns  
Ω
Minimum On- and Off-Time  
OUT Discharge Resistance  
40  
50  
During shutdown or UVLO, from SNS+ to PGND  
650  
600  
SNS+, SNS- Input Impedance  
400  
850  
kΩ  
Time Delay from PWM  
to Power-Save Mode  
Time required for error amplifier to stabilize before  
switching mode  
70  
μs  
μs  
Time Delay from Power-Save  
Mode to PWM  
Time required for error amplifier to stabilize before  
switching mode  
140  
SYNCHRONIZATION (SYNC)  
SYNC[1:0] = 00  
SYNC[1:0] = 1X  
SYNC[1:0] = 01  
18.9  
14.2  
9.5  
26.0  
19.2  
13.0  
13  
38.0  
28.5  
19.0  
SYNC Capture Range  
MHz  
ns  
SYNC Pulse Width  
PROTECTION CIRCUITS  
Thermal-Shutdown Hysteresis  
Thermal Shutdown  
20  
°C  
°C  
+160  
Note 2: All devices are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by  
A
design.  
_______________________________________________________________________________________  
5
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ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
````````````````````````````````````````````````````````````````````````` 
࢜
ቯ৔ᔫᄂቶ  
(Typical Operating Circuit, V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.1V, V  
= 1.8V, T = +25°C, unless otherwise noted.)  
A
IN1  
IN2  
AGND  
PGND  
OUT  
DD  
EFFICIENCY vs. LOAD CURRENT  
(1.0V OUTPUT, SYNC OFF)  
EFFICIENCY vs. LOAD CURRENT  
(1.1V OUTPUT, SYNC OFF)  
EFFICIENCY vs. LOAD CURRENT  
(1.4V OUTPUT, SYNC OFF)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
90  
80  
70  
60  
NBY9:63  
V
IN  
= 3.2V  
3.6V  
V
= 3.2V  
3.6V  
V
IN  
= 3.2V  
3.6V  
IN  
50  
40  
30  
20  
10  
0
4.2V  
4.2V  
4.2V  
FORCED PWM  
FORCED PWM  
FORCED PWM  
0.0001 0.001  
0.01  
0.1  
1
10  
0.0001 0.001  
0.01  
0.1  
1
10  
0.0001 0.001  
0.01  
0.1  
1
10  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
EFFICIENCY vs. LOAD CURRENT  
(1.0V OUTPUT, 26MHz SYNC)  
EFFICIENCY vs. LOAD CURRENT  
(1.1V OUTPUT, 26MHz SYNC)  
EFFICIENCY vs. LOAD CURRENT  
(1.4V OUTPUT, 26MHz SYNC)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
V
IN  
= 3.2V  
3.6V  
V
= 3.2V  
3.6V  
V
IN  
= 3.2V  
3.6V  
IN  
4.2V  
4.2V  
4.2V  
FORCED PWM  
0.1  
FORCED PWM  
0.1  
FORCED PWM  
0.0001 0.001  
0.01  
1
10  
0.0001 0.001  
0.01  
1
10  
0.0001 0.001  
0.01  
0.1  
1
10  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
SWITCHING FREQUENCY  
vs. LOAD CURRENT  
NO-LOAD SUPPLY CURRENT vs.  
SUPPLY VOLTAGE (POWER SAVE)  
SWITCHING FREQUENCY  
vs. TEMPERATURE  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
3.6  
3.5  
3.4  
3.3  
3.2  
3.1  
FORCED PWM  
26MHz SYNC  
NO SYNC  
TRANSITION TO PWM  
POWER SAVE  
NO SYNC  
1.3V OUTPUT, 500mA LOAD  
V
IN  
= 3.6V  
= 1.4V  
V
OUT  
3.0  
0
0.5  
1.0  
1.5  
2.0  
2.5  
2.5  
3.5  
4.5  
5.5  
-40  
-15  
10  
35  
60  
85  
LOAD CURRENT (A)  
SUPPLY VOLTAGE (V)  
TEMPERATURE (°C)  
6
_______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
```````````````````````````````````````````````````````````````````` 
࢜
ቯ৔ᔫᄂቶ)ኚ*  
(Typical Operating Circuit, V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.1V, V = 1.8V, T = +25°C, unless otherwise noted.)  
DD A  
IN1  
IN2  
AGND  
PGND  
OUT  
NO-LOAD SUPPLY CURRENT vs.  
SUPPLY VOLTAGE (FORCED PWM)  
OUTPUT VOLTAGE vs. LOAD CURRENT  
OUTPUT VOLTAGE vs. LOAD CURRENT  
20  
18  
16  
14  
12  
10  
8
1.42  
1.115  
NO SYNC  
T = +25°C  
A
T = +85°C  
A
1.41  
1.40  
1.39  
1.38  
1.37  
1.36  
1.110  
FORCED PWM  
1.105  
26MHz SYNC  
1.100  
1.095  
T = -40°C  
A
POWER SAVE  
6
POWER SAVE  
4
1.090  
V
= 3.6V  
V
OUT  
= 3.6V  
= 1.1V  
IN  
IN  
2
V
OUT  
= 1.4V  
V
0
1.085  
2.5  
3.5  
4.5  
5.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
SUPPLY VOLTAGE (V)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LIGHT LOAD SWITCHING WAVEFORMS  
OUTPUT VOLTAGE vs. LOAD CURRENT  
MAXMAX8952 toc14  
1.010  
1.005  
1.000  
0.995  
0.990  
0.985  
0.980  
FORCED PWM  
V
OUT  
20mV/div  
2V/div  
V
LX  
POWER SAVE  
I
L
V
OUT  
= 3.6V  
= 1.0V  
IN  
200mA/div  
V
10mA LOAD, V  
= 1.3V  
OUT  
0
0.5  
1.0  
1.5  
2.0  
2.5  
2μs/div  
LOAD CURRENT (A)  
MEDIUM LOAD SWITCHING  
WAVEFORMS  
HEAVY LOAD SWITCHING WAVEFORMS  
MAX8952 toc16  
MAX8952 toc15  
20mV/div  
2V/div  
V
20mV/div  
V
OUT  
OUT  
V
LX  
V
2V/div  
LX  
I
L
1A/div  
I
1.8A LOAD  
500mA LOAD  
= 1.3V  
500mA/div  
L
V
= 1.3V  
V
OUT  
OUT  
200ns/div  
200ns/div  
_______________________________________________________________________________________  
7
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
```````````````````````````````````````````````````````````````````` 
࢜
ቯ৔ᔫᄂቶ)ኚ*  
(Typical Operating Circuit, V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.1V, V = 1.8V, T = +25°C, unless otherwise noted.)  
DD A  
IN1  
IN2  
AGND  
PGND  
OUT  
LIGHT LOAD STARTUP WAVEFORMS  
HEAVY LOAD STARTUP WAVEFORMS  
MAX8952 toc17  
MAX8952 toc18  
10I LOAD  
1I LOAD  
NBY9:63  
V
OUT  
V
1V/div  
1V/div  
OUT  
400mA  
I
IN  
100mA/div  
500mA/div  
200mA/div  
I
IN  
I
L
I
L
500mA/div  
5V/div  
V
V
EN  
5V/div  
EN  
200μs/div  
200μs/div  
PREBIAS STARTUP WAVEFORMS  
LINE TRANSIENT RESPONSE (4.2V TO  
(FORCED PWM)  
3.2V TO 4.2V), SYNC OFF  
MAX8952 toc19  
MAX8952 toc20  
OUTPUT PREBIASED TO 1.3V  
STARTUP TO 1.1V  
1V/div  
V
IN  
V
OUT  
500mV/div  
1A/div  
V
20mV/div  
OUT  
I
L
200mA/div  
I
L
300mA LOAD  
20μs/div  
V
EN  
5V/div  
200μs/div  
LOAD TRANSIENT RESPONSE  
LINE TRANSIENT RESPONSE (4.2V TO  
(1mA TO 1A)  
3.2V TO 4.2V), 26MHz SYNC  
MAX8952 toc22  
MAX8952 toc21  
50mV/div  
1V/div  
V
IN  
V
OUT  
V
OUT  
20mV/div  
I
L
500mA/div  
1A/div  
I
200mA/div  
L
300mA LOAD  
20μs/div  
I
OUT  
40μs/div  
8
_______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
```````````````````````````````````````````````````````````````````` 
࢜
ቯ৔ᔫᄂቶ)ኚ*  
(Typical Operating Circuit, V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.1V, V = 1.8V, T = +25°C, unless otherwise noted.)  
DD A  
IN1  
IN2  
AGND  
PGND  
OUT  
LOAD TRANSIENT RESPONSE  
(1A to 1mA)  
LOAD TRANSIENT RESPONSE  
(5mA TO 1.8A)  
MAX8952 toc23  
MAX8952 toc24  
50mV/div  
V
OUT  
V
OUT  
50mV/div  
I
500mA/div  
I
L
L
1A/div  
1A/div  
I
1A/div  
OUT  
I
OUT  
40μs/div  
40μs/div  
SYNCHRONIZATION RESPONSE  
(26MHz SYNC)  
LOAD TRANSIENT RESPONSE  
(1.8A to 5mA)  
MAX8952 toc26  
MAX8952 toc25  
FORCED PWM, NO LOAD  
V
2V/div  
SYNC  
V
OUT  
100mV/div  
1A/div  
V
OUT  
20mV/div  
I
L
V
2V/div  
LX  
I
200mA/div  
L
I
1A/div  
OUT  
1μs/div  
20μs/div  
OUTPUT VOLTAGE CHANGE RESPONSE  
MAX8952 toc27  
10I LOAD,  
POWER SAVE  
32mV/μs RAMP  
V
VID0  
2V/div  
1.3V  
0.9V  
0.9V  
500mV/div  
V
OUT  
I
L
200mA/div  
40μs/div  
_______________________________________________________________________________________  
9
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
``````````````````````````````````````````````````````````````````````````` ፛୭ႁී  
፛୭  
෗
߂
 
৖ถ  
ෝผ
࢟
Ꮞ
࢟
ኹၒྜྷLjၒྜྷ
࢟
ኹपᆍᆐ3/6Wᒗ6/6WăᏴJO2ਜ਼ၒྜྷ
࢟
Ꮞᒄମ
ڔ
ᓤጙৈ22Ω
࢟
ᔜLjᄰਭጙৈ  
1/2μG
ࡼ
ჿࠣ
࢟
ྏ୓JO2๬വᒗBHOELj
࢟
ྏ።஧೟ణதJDहᒙă୓JO2ਜ਼JO3ೌ୻ᒗᄴጙ
࢟
Ꮞă  
A1  
IN1  
NBY9:63  
ෝผ
࢐
Lj୓BHOEೌ୻ᒗQDC୻
࢐
ཌᎮă  
A2  
A3  
AGND  
VID1  
࢟
ኹJE఼ᒜၒྜྷLjWJE1ਜ਼WJE2
ࡼ
൝૷ᓨზኡᐋ࿸ᒙၒ߲
࢟
ኹ
ࡼ
଎
ࡀ
໭ă  
࢟
Ꮞ
࢟
ኹၒྜྷLjၒྜྷ
࢟
ኹपᆍᆐ3/6Wᒗ6/6WăJO3ᆐด
ݝ
q৥
ࡸ
ਜ਼o৥
ࡸ
NPTGFU৙
࢟
Ljᄰਭೝৈ21μG  
ਜ਼ጙৈ1/2μGჿࠣ
࢟
ྏ୓JO3๬വᒗQHOELj
࢟
ྏ።஧೟ణதJDहᒙă୓JO2ਜ਼JO3ೌ୻ᒗᄴጙ
࢟
Ꮞă  
A4  
IN2  
ၒ߲
࢟
ኹᏐ
࣡
ଶ
ހ
Ljᑵၒྜྷ
࣡
ă୓TOT,ᒇ୻ೌ୻
ࡵ
ঌᏲၒ߲ă  
B1  
B2  
SNS+  
EN  
൝૷ဧถၒྜྷă୓FOད
ࣅ
ᆐ঱
࢟
ຳဟLjဧถED.EDଢ଼ኹቯ
ࢯ
ஂ໭Ǘད
ࣅ
ᒗ
࢟ࢅ
ຳဟLj໭ୈ஠ྜྷ  
ਈ
ࣥ
ෝါăਈ
ࣥ
ෝါሆLjক൝૷ၒྜྷด
ݝ
௥ᎌጙৈሆ౯ᒗBHOE
࢟ࡼ
ᔜă  
࢟
ঢೌ୻
࣡
LjMYೌ୻ᒗด
ݝ
q৥
ࡸ
ਜ਼o৥
ࡸ
NPTGFU
ࡼ
ധ૵ăMYᏴਈ
ࣥ
ෝါሆᆐ঱ᔜă  
ၒ߲
࢟
ኹᏐ
࣡
ଶ
ހ
Ljঌၒྜྷ
࣡
ăᏴঌᏲ
ࠀ
ᒇ୻ೌ୻
ࢅࡵ
ᐅဉ
࢐
ຳෂă  
࢟
ኹJE఼ᒜၒྜྷLjWJE1ਜ਼WJE2
ࡼ
൝૷ᓨზኡᐋ࿸ᒙၒ߲
࢟
ኹ
ࡼ
଎
ࡀ
໭ă  
B3, B4  
C1  
LX  
SNS-  
VID0  
PGND  
C2  
C3, C4  
৖ൈ
࢐
Lj୓ೝৈQHOE੆ཆೌ୻ᒗQDC୻
࢐
ཌᎮă  
൝૷ၒྜྷ
࢟
ᏎLj୓W ೌ୻ᒗད
ࣅ
TEBĂTDMਜ਼TZOD
ࡼ
൝૷
࢟
Ꮞăᄰਭጙৈ1/2μGჿࠣ
࢟
ྏ୓W  
EE  
EE  
D1  
V
DD  
3
๬വᒗBHOEă
ࡩ
W ሆଢ଼ᒗVWMPඡሢጲሆဟLjJ D଎
ࡀ
໭আᆡLj
ࡣ
ᏴকෝါሆFO఼ᒜ྆཭ᎌ቉ă  
EE  
3
D2  
D3  
SDA  
SCL  
J Dၫ௣ၒྜྷLjᏴTDM
ࡼ
࿟ဍዘ
ࣗ
ནၫ௣LjᏴTDM
ࡼ
ሆଢ଼ዘၒ߲ၫ௣ă  
3
J Dဟᒩၒྜྷă  
ᅪ
ݝ
ဟᒩᄴ
ݛ
ၒྜྷLj୓TZODೌ୻ᒗ24NI{Ă2:/3NI{૞37NI{ᇹᄻဟᒩăభ༓ᒜED.ED
ࢯ
ஂ໭Ꭷᅪ
ݝ
 
ဟᒩᄴ
ݛ
Lj௥ᄏན௼᎖J D࿸ᒙLj
ݬ
୅
ܭ
9ăTZODᇄด
ݝ
ሆ౯Lj
ݙ
ဧ፿TZODဟ።୓໚ೌ୻ᒗBHOEă  
D4  
SYNC  
3
10 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
SYNC  
OSC  
CLOCK GEN  
IN2  
LX  
V
DD  
2
I C INTERFACE  
SCL  
SDA  
PWM LOGIC  
IN1  
EN  
PGND  
IN1  
V
DAC  
VOLTAGE  
CONTROL, V  
SNS+  
SNS-  
,
REF  
VID0  
VID1  
BIAS, ETC.  
AGND  
ᅄ2/!ऱౖᅄ  
Ᏼ
ݙ
ᄴၒ߲ෝါሆభ
߈ܠ
ጲሆ
ݬ
ၫǖ  
• ၒ߲
࢟
ኹपᆍᆐ1/88Wᒗ2/51WLj
ޠݛ
ᆐ21nW  
• ৔ᔫෝါǖ༓ᒜQXN૞ဏ
࢟
 
````````````````````````````````` ሮᇼႁී  
NBY9:63ᆐ঱቉4/36NI{ଢ଼ኹቯఎਈ
ࢯ
ஂ໭Ljభᄋ৙঱
ࡉ
 
3/6B
ࡼ
ၒ߲
࢟
ഗă໭ୈ৔ᔫᏴ3/6Wᒗ6/6Wၒྜྷ
࢟
ኹपᆍLj  
ၒ߲
࢟
ኹభᄰਭJ3D୻ా࿸ᒙᏴ1/88Wᒗ2/51WLj
ޠݛ
ᆐ  
21nWăཝ
ތ
ॊᏐ
࣡
ଶ
ހ
ཀྵۣঌᏲ
࣡
ᄋ৙றཀྵ
ࡼ
ᒇഗ
࢟
ኹă  
ᏴᑳৈঌᏲĂ
࢟
Ꮞਜ਼ᆨ
ࣞ
पᆍดLjၒ߲ᔐᇙ
ތ
ቃ᎖ 2/6&ă  
• ဧถ0ணᒏఎਈຫൈᎧᅪ
ݝ
ဟᒩᏎ
ࡼ
ᄴ
ݛ
 
WJE10WJE2Ꭷ৔ᔫෝါᒄମ
ࡼ
ਈᇹ༿
ݬ
୅
ܭ
2ă  
WJE`ၒྜྷ௥ᎌด
ݝ
ሆ౯
࢟
ᔜLjJDဧถઁLjభᄰਭDPOUSPM  
଎
ࡀ
໭ணᒏᑚቋሆ౯
࢟
ᔜLjဧஸზ
࢟
ഗଢ଼ᒗᔢቃăFOᆐ  
ࢅ
࢟
ຳဟLjDPOUSPM଎
ࡀ
໭আᆡ
ࡵ
෦ཱྀᒋLjဧถሆ౯  
࢟
ᔜă  
ࣅ
ზ
࢟
ኹ
ࢯ
ஂ  
ၒ߲
࢟
ኹభဧ፿WJE1ਜ਼WJE2൝૷ၒྜྷ
ࣅ
ზ
ࢯ
ஂLj࠭႐ৈ  
Ꮎሌ
ࢾ
ፃ
ࡼ
৔ᔫෝါ0
࢟
ኹ๼ᒙᒦ஠ቲኡᐋă  
ܭ
2/!WJE1ਜ਼WJE2๼ᒙ  
DEFAULT  
SWITCHING  
MODE  
DEFAULT  
OUTPUT  
VOLTAGE (V)  
DEFAULT  
SYNCHRONIZATION  
2
VID1  
VID0  
MODE  
I C REGISTER  
0
0
1
1
0
1
0
1
MODE0  
MODE1  
MODE2  
MODE3  
Table 3  
Table 4  
Table 5  
Table 6  
POWER SAVE  
POWER SAVE  
POWER SAVE  
POWER SAVE  
OFF  
OFF  
OFF  
OFF  
1.40  
1.00  
1.40  
1.10  
______________________________________________________________________________________ 11  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
ဏ
࢟
ෝါሆLjNBY9:63 QXNఎਈຫൈན௼᎖ঌᏲ
࢟
ഗă  
ဧถ  
ᒦ
ࢀ
ঌᏲਜ਼ᒮᏲᄟୈሆLjJD৔ᔫᏴৼ
ࢾ
ຫൈQXNෝါǗ༵  
ᏲᄟୈሆLjJD৔ᔫᏴᒣૄෝါăᓜᎌ
ࡼ
ᒣૄQXN఼ᒜ૦  
ᒜۣᑺ೫঱቉ൈĂ౐Ⴅ༤ધਜ਼౐Ⴅၾზሰ።ăᑚᒬ఼ᒜ  
૦ᒜ੪଼
࡝
ǖ
ࡩ
ၒ߲
࢟
ኹ
ࢅ
᎖ᆮኹඡሢဟLjᇙ
܈ތ
୷໭  
ᄰਭ
ࡴ
ᄰ঱
ܟ
ఎਈ໪
ࣅ
ጙৈఎਈᒲ໐ăఎਈۣ
ࡴߒ
ᄰᓨ  
ზᒇᒗ
ࡵࡉ
ᔢቃ
ࡴ
ᄰဟମ݀༦ၒ߲
࢟
ኹ঱᎖ᆮኹඡሢᎧ  
ᒣૄ
࢟
ኹᒄਜ਼Lj૞ᑗ
࢟
ঢ
࢟
ഗ঱᎖ሢഗඡሢă঱
ܟ
ఎਈ  
ጙ
ࣥࡡ
ఎLjᐌᏴ
ࡵࡉ
ᔢቃ
ࣥ
ఎဟମ݀༦ၒ߲
࢟
ኹᏳ
ࠨ
ሆ  
ଢ଼
ࡵ
ᆮኹඡሢጲሆᒄ༄ۣ
ࣥߒ
ఎᓨზăఎਈ
ࣥ
ఎ໐ମLj  
ࢅ
ܟ
ᄴ
ݛ
ᑳഗ໭
ࡴ
ᄰۣ݀
ࡴߒ
ᄰᓨზLjᒇ
ࡵ
঱
ܟ
ఎਈᏳ  
ࠨ
ࡴ
ᄰ૞
࢟
ঢ
࢟
ഗ୻தഃăด
ݝ
ᄴ
ݛ
ᑳഗ
࢟
വဏབྷ೫ᅪ  
ݝ
ቆᄂ૥औ૵਌ă  
NBY9:63!ED.EDଢ଼ኹቯ
ࢯ
ஂ໭ᄰਭFO൝૷ၒྜྷဧถ0ண  
ᒏăFOၒྜྷభ୻၊঱
ࡉ
WJO2
ࡼ
ၒྜྷ
࢟
ኹLjཀྵۣFO൝૷ၒ  
ྜྷభᎅ৉ᒬቧ੓0
࢟
Ꮞ
࢟
ኹ఼ᒜă  
FOၒྜྷ௥ᎌด
ݝ
ሆ౯
࢟
ᔜLjਈ
ܕ
ᄟୈሆཀྵۣFOह
࢟
ăጙ  
ࡡ
ဧถJDLjభᄰਭDPOUSPM଎
ࡀ
໭ண፿কሆ౯
࢟
ᔜ)୅
ܭ
 
8*Ljဧஸზ
࢟
ഗଢ଼ᒗᔢቃăFOᆐ
࢟ࢅ
ຳဟLjDPOUSPM଎  
ࡀ
໭আᆡ
ࡵ
෦ཱྀᒋLjဧถFOĂWJE1ਜ਼WJE2
ࡼ
ሆ౯
࢟
ᔜă  
ਈ᎖࿟
࢟
ਜ਼
࢟ࣥ
ၿኔጲૺ৔ᔫෝါ
ܤ
છ
ࡼ
ሮᇼቧᇦLj༿  
ݬ
ఠᅄ3ਜ਼ᅄ4ă  
NBY9:63  
ED.ED
ࢯ
ஂ໭৔ᔫෝါ  
JD৔ᔫᏴ႐ᒬෝါᒄጙLj௥ᄏན௼᎖WJE`ၒྜྷᓨზ)୅
ܭ
 
2*ă࿟
࢟
ဟLjJDᒙᆐNPEF1ᒗNPEF4ဏ
࢟
৔ᔫෝါăඛ  
ᒬ৔ᔫෝါሆLjED.EDଢ଼ኹ
ࢯ
ஂ໭௿భ࿸ᒙ৔ᔫᏴဏ
࢟
ෝ  
ါ૞༓ᒜQXNෝါăጲ࿟࿸ᒙᄰਭቖNPEF`଎
ࡀ
໭ဣሚ  
)༿
ݬ
ఠ
ܭ
4ᒗ
ܭ
7*LjᏤ኏Ᏼྀੜဟମখ
ܤ
৔ᔫෝါă  
ো௣ೌኚਭഃ
ࡼ
ᒲ໐ၫ஠ቲQXNਜ਼ᒣૄ৔ᔫෝါᒄମ
ࡼ
 
ᓞધă
ࡩ
ଶ
ࣶࡵހ
᎖27ৈೌኚਭഃᒲ໐ဟLjED.EDଢ଼ኹᓞ  
ધ໭୓ဧถᒣૄ৔ᔫ
ࡼ
ມᒙăᑵཀྵມᒙઁLjྙਫೌኚਭ  
ഃᒲ໐ၫިਭ35ৈLjED.EDଢ଼ኹᓞધ໭ᐌఎဪᒣૄ৔ᔫă  
A
B
C
D
E
IN_  
1.40V  
1.40V  
1.10V  
OUT  
EN  
VID1  
VID0  
V
DD  
A: POWER CONNECTED TO IN1 AND IN2.  
B: EN LOGIC INPUT PULLED HIGH, OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I C REGISTER FOR MODE0 (SEE TABLE 1).  
C: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I C REGISTER FOR MODE2.  
2
2
2
D: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I C REGISTER FOR MODE3.  
2
E: V PULLED HIGH, ENABLING I C INTERFACE.  
DD  
ᅄ3/!࿟
࢟
ਭ
߈
 
12 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
A
B
IN_  
OUT  
EN  
V
DD  
2
A: V PULLED LOW, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1) AND THE OUTPUT VOLTAGE CHANGES TO THE DEFAULT VALUE.  
DD  
B: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS SHUTDOWN MODE.  
ᅄ4b/!ᏴFOᒄ༄౯
ࢅ
W ஠ቲਈ
ࣥ
 
EE  
A
B
IN_  
OUT  
EN  
V
DD  
2
A: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS I C READY MODE, OUTPUT DISABLED.  
2
B: V PULLED LOW, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).  
DD  
ᅄ4c/!ᏴW ᒄ༄౯
ࢅ
FO஠ቲਈ
ࣥ
 
EE  
A
IN_  
OUT  
EN  
V
DD  
2
A: IN_ DROPS BELOW UVLO, IC ENTERS SHUTDOWN MODE, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).  
ᅄ4d/!ᎅ᎖JO2་ኹჄ
ࢾ
ऎ஠ྜྷਈ
ࣥ
 
______________________________________________________________________________________ 13  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
ᒣૄ৔ᔫ໐ମLjᎅ᎖ဧ፿৸ᒋ
ࢯ
ஂLjჅጲ
ࡀ
Ᏼஸზᒇഗ  
ပ
ࢯ
Lj
ݬ
୅ᅄ5ă  
ሤᄴăဏ
࢟
ෝါሆLj
ࡩ
߲ሚሆါ௼
ࡼࢾ
ঌᏲ
࢟
ഗဟLjᐌ  
࠭ᒣૄෝါ༤ધ
ࡵ
ৼ
ࢾ
ఎਈຫൈǖ  
৔ᔫᏴဏ
࢟
ෝါ༦ঌᏲ
࢟
ഗᐐ
ࡍ
ᐆ
߅
ೌኚਭഃᒲ໐ၫቃ  
᎖27ဟLj୐ೂQXNෝါມᒙăᅲ
߅
ມᒙઁLjྙਫਭഃᒲ  
໐ၫሆଢ଼ᒗ9ৈጲሆLjED.EDᓞધ໭ᐌఎ໪QXN৔ᔫăᎅ  
᎖ᏴঌᏲ
࢟
ഗᐐ
ࡍ
ᎧED.EDᓞધ໭ఎ໪QXN
ݷ
ᔫᒄମ
ࡀ
 
Ᏼዓ
ߕ
Ljᓞધ໭ၒ߲ถ৫Ᏼᒣૄ৔ᔫ໐ମᑽ
ߒ
൸ঌ੗
࢟
 
ഗLjሮᇼᓨზᅄ༿
ݬ
ఠᅄ6ă  
V
− V  
V
OUT  
V × f  
IN OSC  
IN  
OUT  
I
=
×
OUT  
2×L  
༓ᒜQXNෝါሆLj
ࢯ
ஂ໭৔ᔫᏴৼ
ࢾ
)4/36NI{૞Ꭷᅪ
ݝ
 
ဟᒩᏎᄴ
ݛ
*ఎਈຫൈLjᎧၒ߲ঌᏲᇄਈă  
NBY9:63  
༓ᒜQXNෝါሆLjᎅ᎖ఎਈቕ݆ᆡ᎖ৼ
ࢾ
ఎਈຫൈ
ࡼ
ᑳ  
ၫ۶Ljྏጵ൉߹Ljፐࠥऻ
ޟ
း੝
ࢅ
ᐅဉᇹᄻă
ࡣ
༓ᒜ  
QXNෝါᏴ༵Ᏺᄟୈሆ
ࡼ
৖੒঱᎖ဏ
࢟
ෝါă  
ဏ
࢟
ᄂቶᏴ༵Ᏺဟဧ໭ୈ஠ྜྷᒣૄෝါLjো௣ঌᏲᄟୈ  
ଢ଼
ࢅ
ఎਈຫൈLj࠭ऎᄋ঱৔ᔫ቉ൈăᏴᒦ
ࢀ
ঌᏲਜ਼ᒮᏲ  
ᄟୈሆLj
ࢯ
ஂ໭৔ᔫᏴৼ
ࢾ
ఎਈຫൈLjᎧ༓ᒜQXNෝါ  
ྟ໪
ࣅ
 
JD௥ᎌด
ݝ
ྟ໪
࢟ࣅ
വLjถ৫ጴᒜ໪
ࣅ
ਭ
ࡼ߈
಍፻
࢟
ഗLj  
ଢ଼
ࢅ
ၒྜྷ
࢟
Ꮞ
ࡼ
ၾ
ܤ
)
ݬ
୅
࢜
ቯ৔ᔫᄂቶ*ăྟ໪
࣪ࣅ
᎖঱  
ᔜၒྜྷᏎᎄ໚ᎌ፿LjಿྙMj,ਜ਼ସቶ
ߔ࢟
ăဧถJD஠ྜྷᎾ  
ມᒙၒ߲ဟLjJDᒊቲጙ
ࠨ
ᅲᑳ
ࡼ
ྟ໪
ࣅ
ਭ
߈
ă  
REGULATION  
THRESHOLD  
OUTPUT  
RIPPLE  
ᅄ5/!ᒣૄ৔ᔫෝါሆ
ࡼ
ၒ߲
ࢯ
ஂ  
MORE THAN 16 CONSECUTIVE  
ZERO-CROSSING CYCLES  
PWM MODE  
WITH POWER-SAVE  
MODE BIASED  
PWM  
MODE  
POWER SAVE NOT READY  
LESS THAN 8 CONSECUTIVE  
ZERO-CROSSING CYCLES  
LESS THAN 8 CONSECUTIVE  
ZERO-CROSSING CYCLES  
AND PWM MODE READY  
MORE THAN 24 CONSECUTIVE  
ZERO-CROSSING CYCLES  
AND POWER-SAVE MODE READY  
MORE THAN 24 CONSECUTIVE  
ZERO-CROSSING CYCLES  
POWER-SAVE  
MODE WITH  
PWM BIASED  
POWER-SAVE  
MODE  
PWM NOT READY  
LESS THAN 16 CONSECUTIVE  
ZERO-CROSSING CYCLES  
ᅄ6/!ED.EDଢ଼ኹᓞધ໭
ࡼ
ෝါ
ܤ
છ  
14 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
࢟
ኹሆଢ଼໐ମ
ۻ
ணᒏăᎌᏎቓൈ఼ᒜဵ༓ᒜQXNෝါሆ  
ࡼ
ৼᎌ৖ถă  
ᄴ
ݛ
ᑳഗ  
ด
ݝ
o৥
ࡸ
ᄴ
ݛ
ᑳഗ໭ဏབྷ೫ᅪ
ݝ
ቆᄂ૥औ૵਌Ljభᄋ঱  
ᓞધ቉ൈăᄴ
ݛ
ᑳഗ໭Ᏼඛৈఎਈᒲ໐
ࡼ
ઁ
ۍ
ᒲ໐)
ࣥ
ఎ  
ဟମ*
ࡴ
ᄰăᏴࠥ໐ମLj
࢟
ঢೝ
࢟࣡
ኹनᓞLj
࢟
ঢ
࢟
ഗሣ  
ቶሆଢ଼ăQXNෝါሆLjᄴ
ݛ
ᑳഗ໭Ᏼఎਈᒲ໐உၦဟ
ࣥ
 
ఎăဏ
࢟
ෝါሆLjᄴ
ݛ
ᑳഗ໭Ᏼ
࢟
ঢ
࢟
ഗሆଢ଼
ࢅࡵ
᎖  
61nB!)
࢜
ቯᒋ*૞ఎਈᒲ໐உၦဟ
ࣥ
ఎLj௥ᄏན௼᎖၅ሌ  
खည෾ᒬᓨౚă  
ږ
ᑍሆါଐႯၒ߲
࢟
ኹ݆
ࣅ
Ⴅൈ
ࡼ
ᔢ
ࡍ
ᒋਜ਼ᔢቃᒋǖ  
V
1
OUT _LSB  
t
=
×
RAMP _MIN  
RAMP _ CODE  
t
2
CLK _MAX  
V
1
OUT _LSB  
t
=
×
RAMP _MAX  
RAMP _ CODE  
t
2
CLK _MIN  
ၒ߲
࢟
ኹ݆
ࣅ
Ⴅൈ఼ᒜ  
ါᒦǖ  
V
=10mV  
NBY9:63భᎌᏎ఼ᒜၒ߲
࢟
ኹ
ࡼ
݆
ࣅ
ႥൈLjᄰਭJ3D୻ా  
࿸ᒙ)
ݬ
୅ᅄ7Ăᅄ8ਜ਼ᅄ9*ăSBNQ଎
ࡀ
໭
ࡼ
ၫᒋ఼ᒜၒ߲  
࢟
ኹ
ࡼ
݆
ࣅ
ႥൈăSBNQ`EPXOᆡ఼ᒜဏ
࢟
ෝါሆၒ߲  
࢟
ኹ
ࡼ
ሆଢ଼ቓൈă
ࢯ
ஂ໭ᒙᆐဏ
࢟
ෝါ༦SBNQ`EPXO  
ᆡ༹ഃဟLjᐌᎅᇄᏎᏄୈ௼
ࢾ
ၒ߲
࢟
ኹ
ࡼ
ሆଢ଼ቓൈLj
ࢯ
 
ஂ໭ၒ߲
࢟
ኹᎅၒ߲
࢟
ྏਜ਼ᅪ
ݝ
ঌᏲ௼
ࢾ
ሆଢ଼Ⴅൈă༵  
Ᏺᄟୈሆၒ߲
࢟
ኹၱିႥ
ࢅࣞ
᎖SBNQਖ
ࡼࢾ
ၫᒋǗᒮᏲ  
ᄟୈሆLjၒ߲
࢟
ኹ
ࡼ
ၱିႥ
ࡍݙࣞ
᎖SBNQਖ
ࡼࢾ
Ⴅൈă  
ဏ
࢟
ෝါሆLjSBNQ`EPXOᒙᆡဟLjਭഃ
܈
୷໭Ᏼၒ߲  
OUT _LSB  
1
t
t
=
CLK _MAX  
f
SW _MIN  
1
=
CLK _MIN  
f
SW _MAX  
gTX >!4/36NI{! 21&LjQXN৔ᔫෝါ  
gTX >!4/36NI{! 36&Ljᒣૄ৔ᔫෝါ  
f
SYNC  
n
f
=
SW  
OUTPUT  
VOLTAGE  
DELTA V = 10mV  
gTZOD >!ᅪ
ݝ
ဟᒩຫൈ  
V
'
OUT  
o!>!5!)24NI{ຫൈ*Ă7!)2:/3NI{ຫൈ*ਜ਼9!)37NI{ຫൈ*  
SBNQ`DPEF!>!SBNQ\3;1^଎
ࡀ
໭
ࡼ
ၫᒋ)
ݬ
୅
ܭ
:*  
10mV/RAMP RATE  
TIME  
ེਭᏲۣઐ  
V
OUT  
ེਭᏲۣઐ፿᎖ሢᒜJD
ࡼ
ᔐ৖੒ăด
ݝ
ᆨ
ࠅࣞ
ঢ໭ଶ
ࡵހ
 
਌በᆨ
ࣞ
ިਭ,271°D )
࢜
ቯᒋ*ဟLjED.EDଢ଼ኹ
ࢯ
ஂ໭ਈ
ࣥ
Lj  
ᅄ7/!࿟ဍ਽ၫ  
FINAL  
OUTPUT  
VOLTAGE  
OUTPUT  
VOLTAGE  
V
OUT  
DELTA  
V = 10mV  
10mV/RAMP  
RATE  
V
OUT  
'
MODE CHANGE  
TO HIGHER VOUT  
MODE CHANGE  
TO LOWER VOUT  
TIME  
ᅄ8/!ሆଢ଼਽ၫ  
ᅄ9/!
ࡉ
ࡵ
ᔢᒫᒋᒄ༄
ࡼ
ෝါ
ܤ
છ  
______________________________________________________________________________________ 15  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
SDA  
NBY9:63  
SCL  
DATA LINE STABLE DATA VALID  
CHANGE OF DATA ALLOWED  
3
ᅄ:/!J Dᆡ
ࠅ
ၒ  
ဧJDದསăஉᆨሆଢ଼31°D )
࢜
ቯᒋ*ઁLjED.EDଢ଼ኹ
ࢯ
ஂ໭  
TUBSUਜ਼TUPQᄟୈ  
Ᏻ
ࠨ
ఎ໪LjೌኚེਭᏲᄟୈሆተ
߅
൴
ߡ
ါၒ߲ă  
ࠈ
ቲ୻ాᇄ቉ဟLjTEBਜ਼TDMᆐహሔ঱
࢟
ຳăᓍ૦ᄰਭख  
႙TUBSUᄟୈ໪
ࣅ
ᄰቧLjTUBSUᄟୈဵTDMᆐ঱
࢟
ຳဟLj  
TEBᎅ঱
ࡼࢅࡵ
ᄢ
ܤ
ǗTUPQᄟୈဵTDMᆐ঱
࢟
ຳဟLjTEB  
ᎅ
ࡵࢅ
঱
ࡼ
ᄢ
ܤ
)ᅄ21*ă  
ེਭᏲ໐ମLjJ3D୻ాۣ
ߒ
ᎌ቉Lj݀ᆒ
ߒ
ཝ
ݝ
଎
ࡀ
໭ၫᒋă  
3
J D୻ా  
J3Dରྏ
ࡼ
3ሣ
ࠈ
ቲ୻ా఼ᒜଢ଼ኹᓞધ໭
ࡼ
ၒ߲
࢟
ኹĂ݆
ࣅ
 
ႥൈĂ৔ᔫෝါਜ਼ᄴ
ݛ
ă
ࠈ
ቲᔐሣᎅጙোၷሶ
ࠈ
ቲၫ௣  
ሣ)TEB*ਜ਼ጙো
ࠈ
ቲဟᒩၒྜྷ)TDM*ᔝ
߅
ăᓍ఼ᒜ໭Ᏼᔐሣ  
࿟໪
ࣅ
ၫ௣
ࠅ
ၒ݀
ޘ
ညTDMቧ੓LjᏤ኏ၫ௣
ࠅ
ၒă  
౶ᔈᓍ૦
ࡼ
TUBSUᄟୈᄰᒀJDఎဪ
ࠅ
ၒăᓍ૦ᄰਭख႙ऻ  
።
ࡊ
ጲૺႲઁ
ࡼ
TUPQᄟୈ౶உၦ
ࠅ
ၒ)ৎ
ࣶ
ቧᇦ༿
ݬ
୅።  
J3DᆐఎധᔐሣLjTEBਜ਼TDMኊገ࿟౯
࢟
ᔜ)611Ω૞ৎ
ࡍ
*ă  
TEBਜ਼TDMሣభጲኡᐋ
ࠈ
ೊጙৈ
࢟
ᔜ)35Ω*Ljۣઐ໭ୈၒྜྷ  
ݙ
၊ᔐሣ࿟঱ኹବख़
ࡼ
Ⴜ਴ă
ࠈ
ೊ
࢟
ᔜથ୓ᔐሣቧ੓
ࡼ
 
ࠈ
ཷਜ਼ሆ
ߡ
ଢ଼ᒗᔢቃă  
SDA  
SCL  
ᆡ
ࠅ
ၒ  
ඛৈTDMဟᒩᒲ໐
ࠅ
ၒጙৈၫ௣ᆡăᏴTDMဟᒩ൴
ࡼߡ
঱  
࢟
ຳ໐ମLjTEB࿟
ࡼ
ၫ௣
ܘ
ኍۣ
ߒ
ᆮ
ࢾ
)
ݬ
୅ᅄ:*ă
ࡩ
TDM  
ᆐ঱
࢟
ຳဟLjTEB
ܤࡼ
છ
ܭ
ာ఼ᒜቧ੓)ৎ
ࣶ
ቧᇦ༿
ݬ
୅  
TUBSUਜ਼TUPQᄟୈ
ݝ
ॊ*ă  
ඛৈ
ࠅ
ၒኔ೰
࣒
ᎅTUBSU )T*ᄟୈਜ਼TUPQ )Q*ᄟୈ
ࡌ
۞
߅
 
ᑷăඛৈၫ௣۞
ࣞޠ
ᆐ:ᆡLj9ᆡၫ௣ᒄઁᆐ።
ࡊ
ᆡăJDᑽ  
ߒ
TDMຫൈ঱
ࡉ
511lI{
ࡼ
ၫ௣
ࠅ
ၒă  
START  
CONDITION  
STOP  
CONDITION  
3
ᅄ21/!J D!TUBSUਜ਼TUPQᄟୈ  
16 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
SDA  
SCL  
MASTER  
TRANSMITTER/RECEIVER  
SLAVE  
TRANSMITTER/RECEIVER  
SLAVE RECEIVER  
3
ᅄ22/!J Dᓍ0࠭๼ᒙ  
ࡊ
ݝ
ॊ*LjTUPQᄟୈျहᔐሣăᆐ೫ሶ࠭૦ख႙ጙᇹ೰ෘ  
എLjᓍ૦ख႙SFQFBUFE TUBSU )Ts*ෘഎLjऎ
ݙ
ဵTUPQ  
ෘഎLjۣ
ߒ
఼ᒜᔐሣăᄰ
ޟ
༽ౚሆLjSFQFBUFE TUBSU  
ෘഎᏴ৖ถ࿟
ࢀ
ᄴ᎖
ޟ
ਖ
ࡼ
TUBSUෘഎă  
SDA OUTPUT  
FROM TRANSMITTER  
D0  
D7  
D6  
NOT ACKNOWLEDGE  
ଶ
ࡵހ
TUPQᄟୈ૞
ݙ
ᑵཀྵ
࢐ࡼ
ᒍဟLjJDᏴด
ݝ
୓TDM࠭
ࠈ
 
ా
ࣥ
ఎLjᒇ
ࡵ
ሆጙৈTUBSUᄟୈLj࠭ऎ୓ၫᔊᐅဉਜ਼ౣᄰ  
ଢ଼ᒗᔢቃă  
SDA OUTPUT  
FROM RECEIVER  
ACKNOWLEDGE  
8
SCL FROM  
MASTER  
ᇹᄻ๼ᒙ  
1
2
9
J3Dᔐሣ࿟
ޘ
ညሿᇦ
ࡼ
໭ୈ
߂
ᆐख႙໭Lj୻၃ሿᇦ
ࡼ
໭ୈ  
߂
ᆐ୻၃໭ă఼ᒜሿᇦ
ࡼ
໭ୈᆐᓍ૦Lj၊ᓍ૦఼ᒜ
ࡼ
໭  
ୈ
߂
ᆐ࠭૦Lj
ݬ
୅ᅄ22ă  
CLOCK PULSE FOR  
ACKNOWLEDGEMENT  
START CONDITION  
።
ࡊ
 
3
ᅄ23/!J D።
ࡊ
 
ख႙໭ਜ਼୻၃໭ᏴTUBSUਜ਼TUPQᄟୈᒄମ
ࠅ
ၒ
ࡼ
ၫ௣ᔊ  
ஂၫ೟
ݙ
၊ሢᒜăඛৈ9ᆡᔊஂઁ
ܟ
ৌጙৈ።
ࡊ
ᆡă።
ࡊ
 
ᆡဵ୻၃໭Ᏼᓍ૦
ޘ
ည
ࡼ
ጙৈऄᅪ።
ࡊ
ဟᒩ൴
ߡ
໐ମᏴ  
TEB࿟
ޘ
ည
࢟ࢅࡼ
ຳቧ੓ă
ۻ
ኰᒍ
ࡼ
࠭૦୻၃໭
ܘ
ኍᏴ၃  
ࡵ
ඛৈᔊஂઁ
ޘ
ညጙৈ።
ࡊ
Ljᓍ૦୻၃໭ጐ
ܘ
ኍᏴ၃
ࡵ
 
࠭૦ख႙໭ख߲
ࡼ
ඛৈᔊஂઁ
ޘ
ညጙৈ።
ࡊ
Lj
ݬ
୅ᅄ23ă  
଎
ࡀ
໭আᆡ  
ࡩ
JO2૞WEE
࢟
ኹሆଢ଼ᒗሤ።
ࡼ
VWMPඡሢጲሆဟLjJ3D଎  
ࡀ
໭আᆡ
ࡵ
෦ཱྀᒋ)
ݬ
୅Fmfdusjdbm!Dibsbdufsjtujdt
ܭ
*ă  
ৎቤၒ߲৔ᔫෝါ  
።
ࡊ
໭ୈ
ܘ
ኍᏴ።
ࡊ
ဟᒩ൴
ߡ
໐ମ౯
ࢅ
TEBLj࠭ऎဧTEB  
Ᏼ።
ࡊ
ဟᒩ൴
ࡼߡ
঱
࢟
ຳᒲ໐ดᆮ
ࢾ
ᆐ
࢟ࢅ
ຳ)
ܘ
ኍ൸ᔗ  
୐ೂਜ਼ۣ
ߒ
ဟମ*ăᓍ૦୻၃໭
ܘ
ኍᏴ၃
ࡵ
࠭૦ख߲
ࡼ
ᔢ  
ઁጙৈᔊஂઁ
ޘ
ညጙৈऻ።
ࡊ
ቧ੓Ljᒫᒏၫ௣
ࠅ
ၒăᑚᒬ  
༽ౚሆLjख႙໭
ܘ
ኍۣ
ߒ
TEBᆐ঱
࢟
ຳLjဧᓍ૦
ޘ
ညTUPQ  
ᄟୈă  
ྙਫৎቤၒ߲
࢟
ኹ૞JD
ࡩ
༄৔ᔫෝါሆ
ࡼ
৔ᔫෝါ଎
ࡀ
 
໭Ljၒ߲
࢟
ኹ0৔ᔫෝါᐌᏴJDख႙J3Dၫ௣ᔊஂ።
ࡼࡊ
ᄴ  
ဟৎቤ)୅ᅄ24*ă  
______________________________________________________________________________________ 17  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
A
B
C
D
E
OUT  
S
SLAVE ID  
ASr  
REG PTR  
ASr  
DATA  
A
P
SDA  
VID0  
NBY9:63  
VID1  
V
2
DD  
A: I C START COMMAND.  
2
B: I C SLAVE ADDRESS OF MAX8952 SEND OUT.  
2
C: MAX8952 I C REGISTER POINTER SEND OUT.  
D: MAX8952 DATA SEND OUT.  
E: MAX8952 ISSUES ACKNOWLEDGE AND CHANGES THE OUTPUT VOLTAGE ACCORDING TO NEW I C SETTINGS.  
2
ᅄ24/!ৎቤၒ߲
ݷ
ᔫ  
8* ࠭૦።
ࡊ
ၫ௣ᔊஂă  
9* ࠭૦ৎቤᆐቤၫ௣ă  
:* ᓍ૦ख႙TUPQᄟୈă  
࠭
࢐
ᒍ  
ᔐሣᓍ఼ᒜ໭ᄰਭख႙TUBSUᄟୈਜ਼Ⴒઁ
ࡼ
࠭૦
࢐
ᒍ໪
ࣅ
 
Ꭷ࠭໭ୈ)NBY9:63*
ࡼ
ᄰቧă࠭
࢐
ᒍᔊஂ۞౪8ৈ
࢐
ᒍᆡ  
)2211!111y*ਜ਼ጙৈ
ࣗ
0ቖᆡ)S0 *ă୻၃
ࡵ
ᑵཀྵ
࢐ࡼ
ᒍઁLj  
W
߹೫ቖᔊஂ቏ፇᅪLjJDથభጲቖ
ࣶ
ৈ଎
ࡀ
໭Ljྙᅄ25cჅ  
ာăক቏ፇᏤ኏J3Dᓍ૦ᒑ஠ቲጙ
ࠨ
࠭૦ኰᒍLj૾భ୓ၫ  
௣ख႙
ࡵ
࠭ᒎ
ࢾ
଎
ࡀ
໭ᒎᑣఎဪ
ࡼ
ೌኚ଎
ࡀ
໭ၫ௣్ă  
JDᄰਭᏴ
࢒
:ৈဟᒩᒲ໐ด୓TEB౯
ࢅ
౶ख႙።
ࡊ
ă  
భᒎ
ࢾ
໚჈࠭
࢐
ᒍLjሮᇼ༽ౚ༿Ꭷ৔
ޣ
ೊᇹă  
ቖ
ݷ
ᔫ  
ݧ
፿ጲሆ
ݛ
ᒾೌኚቖྜྷ଎
ࡀ
໭ၫ௣్ǖ  
2* ᓍ૦ख႙TUBSUෘഎă  
JD
ږ
ᑍTNCvtUNਖप
ࢾࡼ
ፃဤܰቖᔊஂ቏ፇLjྙᅄ25bਜ਼ᅄ  
25cჅာăቖᔊஂ቏ፇᏤ኏J3Dᓍ૦໭ୈሶ࠭૦໭ୈख႙2  
ৈᔊஂ
ࡼ
ၫ௣ăቖᔊஂ቏ፇኊገጙৈ଎
ࡀ
໭ᒎᑣ
࢐
ᒍLj  
፿᎖ઁኚ
ࡼ
ቖ
ݷ
ᔫă஧਌໭ୈᒦᒑᎌჅᎌ଎
ࡀ
໭
ࡼ
ጙৈ  
ᔇૹLjJDጐ።
ࡊ
Ⴥᎌ଎
ࡀ
໭ᒎᑣăቖᔊஂ቏ፇྙሆǖ  
3* ᓍ૦ख႙8ᆡ࠭૦
࢐
ᒍLjႲઁৌጙৈቖ
ݷ
ᔫᆡă  
4* 
ۻ
ኰᒍ
ࡼ
࠭૦ᄰਭ౯
ࢅ
TEBख႙።
ࡊ
ă  
5* ᓍ૦ख႙
࢒
ጙৈኊገቖྜྷ
ࡼ
଎
ࡀ
໭
ࡼ
9ᆡ଎
ࡀ
໭ᒎᑣă  
6* ࠭૦።
ࡊ
଎
ࡀ
໭ᒎᑣă  
2* ᓍ૦ख႙TUBSUෘഎă  
3* ᓍ૦ख႙8ᆡ࠭૦
࢐
ᒍLjႲઁৌጙৈቖ
ݷ
ᔫᆡă  
4* 
ۻ
ኰᒍ
ࡼ
࠭૦ᄰਭ౯
ࢅ
TEB஠ቲ።
ࡊ
ă  
5* ᓍ૦ख႙ጙৈ9ᆡ଎
ࡀ
໭ᒎᑣă  
6* ࠭૦።
ࡊ
଎
ࡀ
໭ᒎᑣă  
7* ᓍ૦ख႙ጙৈၫ௣ᔊஂă  
8* ࠭૦።
ࡊ
ၫ௣ᔊஂă  
9* ࠭૦ৎቤᆐቤၫ௣ă  
:* 
࣪
ၫ௣్ด
ࡼ
଎
ࡀ
໭ᒮআ
ݛ
ᒾ7ᒗ9Lj଎
ࡀ
໭ᒎᑣඛ
ࠨ
 
ᔈ
࢕ࣅ
ᐐă  
7* ᓍ૦ख႙ጙৈၫ௣ᔊஂă  
21* ᓍ૦ख႙TUPQᄟୈă  
TNCvtဵJoufm!Dpsq/
ࡼ
࿜
ܪ
ă  
18 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
LEGEND  
MASTER TO  
SLAVE  
SLAVE TO  
MASTER  
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL  
1
7
1
0
1
8
1
8
1
1
NUMBER OF BITS  
S
SLAVE ADDRESS  
A
REGISTER POINTER  
A
DATA  
A
P
R/W  
b) WRITING TO MULTIPLE REGISTERS  
NUMBER OF BITS  
1
7
1
1
8
1
8
1
8
1
...  
S
SLAVE ADDRESS  
0
A
REGISTER POINTER X  
A
DATA X  
A
DATA X+1  
A
R/W  
8
1
8
1
NUMBER OF BITS  
...  
DATA X+n-1  
A
DATA X+n  
A
P
ᅄ25bਜ਼ᅄ25c/!ሶJDቖྜྷၫ௣  
2* ᓍ૦ख႙TUBSUෘഎă  
ࣗ
ݷ
ᔫ  
ࣗ
ན
࡝
ৈ଎
ࡀ
໭)ᔊஂ*
ࡼ
ऱजྙᅄ26bჅာLj
࡝ࣗ
ৈ଎
ࡀ
 
໭ဟǖ  
3* ᓍ૦ख႙8ᆡ࠭૦
࢐
ᒍLjႲઁৌጙৈቖ
ݷ
ᔫᆡă  
4* 
ۻ
ኰᒍ
ࡼ
࠭૦ᄰਭ౯
ࢅ
TEB஠ቲ።
ࡊ
ă  
5* ᓍ૦ख႙ၫ௣్ᒦ
࢒
ጙৈ଎
ࡀ
໭
ࡼ
9ᆡ଎
ࡀ
໭ᒎᑣă  
6* ࠭૦።
ࡊ
଎
ࡀ
໭ᒎᑣă  
2* ᓍ૦ख႙TUBSUෘഎă  
3* ᓍ૦ख႙8ᆡ࠭૦
࢐
ᒍLjႲઁৌጙৈቖ
ݷ
ᔫᆡă  
4* 
ۻ
ኰᒍ
ࡼ
࠭૦ᄰਭ౯
ࢅ
TEB஠ቲ።
ࡊ
ă  
5* ᓍ૦ख႙ጙৈ9ᆡ଎
ࡀ
໭ᒎᑣă  
6* ࠭૦።
ࡊ
଎
ࡀ
໭ᒎᑣă  
7* ᓍ૦ख႙SFQFBUFE TUBSUᄟୈă  
8* ᓍ૦ख႙8ᆡ࠭૦
࢐
ᒍLjႲઁৌጙৈ
ݷࣗ
ᔫᆡă  
9* ࠭૦ᄰਭ౯
ࢅ
TEB஠ቲ።
ࡊ
ă  
7* ᓍ૦ख႙SFQFBUFE TUBSUᄟୈă  
8* ᓍ૦ख႙8ᆡ࠭૦
࢐
ᒍLjႲઁৌጙৈ
ݷࣗ
ᔫᆡă  
9* ࠭૦ᄰਭ౯
ࢅ
TEB஠ቲ።
ࡊ
ă  
:* ࠭૦ख႙9ᆡၫ௣)଎
ࡀ
໭ดྏ*ă  
21* ኊገ
ࣗ
ནৎ
ࣶ
ၫ௣ဟLjᓍ૦ᄰਭ౯
ࢅ
TEB஠ቲ።  
ࡊ
Ǘ૞Ᏼ
ࣗ
ནჅᎌၫ௣ઁLjᄰਭۣ
ߒ
TEBᆐ঱
࢟
ຳ
ޘ
 
ညऻ።
ࡊ
ă  
:* ࠭૦ख႙9ᆡၫ௣)଎
ࡀ
໭ดྏ*ă  
21* ᓍ૦ᄰਭۣ
ߒ
TEBᆐ঱
࢟
ຳ
ޘ
ညऻ።
ࡊ
ă  
22* ᓍ૦ख႙TUPQᄟୈă  
22* 
࣪
ၫ௣్ด
ࡼ
଎
ࡀ
໭ᒮআ
ݛ
ᒾ:ᒗ21Lj଎
ࡀ
໭ᒎᑣඛ  
ࠨ
ᔈ
࢕ࣅ
ᐐă  
23* ᓍ૦ख႙TUPQᄟୈă  
ࠥᅪLjJDభ
ࣗ
ན۞਺
ࣶ
ৈೌኚ଎
ࡀ
໭
ࡼ
ၫ௣్Ljྙᅄ26c  
Ⴥာă
ݧ
፿ጲሆ
ݛ
ᒾೌኚ
ࣗ
ན଎
ࡀ
໭ၫ௣్ǖ  
______________________________________________________________________________________ 19  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
LEGEND  
MASTER TO  
SLAVE  
SLAVE TO  
MASTER  
NBY9:63  
a) READING A SINGLE REGISTER  
1
7
1
0
1
8
1
1
7
1
1
8
1
1
NUMBER OF BITS  
S
SLAVE ADDRESS  
A
REGISTER POINTER  
A
Sr  
SLAVE ADDRESS  
1
A
DATA  
NA  
P
R/W  
R/W  
b) READING MULTIPLE REGISTERS  
NUMBER OF BITS  
1
7
1
1
8
1
1
7
1
8
1
1
1
...  
S
SLAVE ADDRESS  
0
A
REGISTER POINTER X  
A
Sr  
SLAVE ADDRESS  
A
DATA X  
A
R/W  
...  
R/W  
1
8
1
8
8
1
1
NUMBER OF BITS  
...  
DATA X+1  
A
DATA X+n-1  
A
DATA X+n  
NA  
P
ᅄ26bਜ਼ᅄ26c/!࠭JD
ࣗ
ནၫ௣  
SDA  
t
BUF  
t
SU_STA  
t
SU_DAT  
t
HD_STA  
t
LOW  
t
SU_STO  
t
HD_DAT  
t
SCL  
HIGH  
t
HD_STA  
t
t
F
R
START CONDITION  
REPEATED START CONDITION  
STOP  
CONDITION  
START  
CONDITION  
3
ᅄ27/!J Dဟኔᅄ  
20 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
3
ܭ
3/!J D଎
ࡀ
໭  
POINTER  
0x00  
REGISTER  
POR  
BIT7  
BIT6  
BIT5  
BIT4  
BIT3  
BIT2  
BIT1  
BIT0  
OPER  
MODE  
SYNC  
MODE  
MODE0  
MODE1  
MODE2  
MODE3  
0x3F  
VOUT MODE0[5:0]  
VOUT MODE1[5:0]  
VOUT MODE2[5:0]  
VOUT MODE3[5:0]  
OPER  
MODE  
SYNC  
MODE  
0x01  
0x02  
0x03  
0x17  
0x3F  
0x21  
OPER  
MODE  
SYNC  
MODE  
OPER  
MODE  
SYNC  
MODE  
0x04  
0x05  
0x06  
0x08  
0x09  
CONTROL  
SYNC  
0xE0  
0x00  
0x01  
0x20  
0x1A  
EN_PD  
VID0_PD VID1_PD  
—
—
—
—
—
—
—
SYNC[1:0]  
RAMP[2:0]  
—
—
—
—
—
—
RAMP  
FORCE_HYS FORCE_OSC  
RAMP_DOWN  
CHIP_ID1  
CHIP_ID2  
DIE TYPE[7:4]  
DASH[3:0]  
DIE TYPE[3:0]  
MASK REV[3:0]  
3
ܭ
4/!J D଎
ࡀ
໭ǖNPEF1  
ক଎
ࡀ
໭਺ᎌNPEF1
ࡼ
ၒ߲
࢟
ኹਜ਼৔ᔫෝါ఼ᒜLjWJE1 > HOEĂWJE2 > HOEă  
REGISTER NAME  
MODE0  
0x00h  
Address  
Reset Value  
Type  
0x3Fh  
Read/write  
Reset upon V or IN_ UVLO  
Special Features  
DD  
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Converter Operation Mode for MODE0  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
B6  
FPWM_EN0  
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
SYNC_MODE0  
0
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE0  
000000 = 0.77V  
000001 = 0.78V  
110011 = 1.28V  
110100 = 1.29V  
B5  
B4  
B3  
111111  
(1.4V)  
OUT_ MODE0[5:0]  
B2  
110101 = 1.30V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
______________________________________________________________________________________ 21  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
3
ܭ
5/!J D଎
ࡀ
໭ǖNPEF2  
ক଎
ࡀ
໭਺ᎌNPEF2
ࡼ
ၒ߲
࢟
ኹਜ਼৔ᔫෝါ఼ᒜLjWJE2!>!HOEĂWJE1!>!WEE  
ă
REGISTER NAME  
MODE1  
0x01h  
Address  
Reset Value  
Type  
0x17h  
NBY9:63  
Read/write  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Converter Operation Mode for MODE1  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
B6  
FPWM_EN1  
0
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
SYNC_MODE1  
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE1  
000000 = 0.77V  
000001 = 0.78V  
010110 = 0.99V  
010111 = 1.00V  
B5  
B4  
B3  
010111  
(1.00V)  
OUT_MODE1[5:0]  
B2  
011000 = 1.01V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
22 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
3
ܭ
6/!J D଎
ࡀ
໭ǖNPEF3  
ক଎
ࡀ
໭਺ᎌNPEF3
ࡼ
ၒ߲
࢟
ኹਜ਼৔ᔫෝါ఼ᒜLjWJE2!>!WEEĂWJE1!>!HOEă  
REGISTER NAME  
MODE2  
0x02h  
Address  
Reset Value  
Type  
0x3Fh  
Read/write  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Converter Operation Mode for MODE2  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
B6  
FPWM_EN2  
0
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
SYNC_MODE2  
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE2  
000000 = 0.77V  
000001 = 0.78V  
110011 = 1.28V  
110100 = 1.29V  
B5  
B4  
B3  
111111  
(1.4V)  
OUT_MODE2[5:0]  
B2  
110101 = 1.30V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
______________________________________________________________________________________ 23  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
3
ܭ
7/!J D଎
ࡀ
໭ǖNPEF4  
ক଎
ࡀ
໭਺ᎌNPEF4
ࡼ
ၒ߲
࢟
ኹਜ਼৔ᔫෝါ఼ᒜLjWJE2!>!WEEĂWJE1!>!WEE  
ă
REGISTER NAME  
MODE3  
0x03h  
Address  
Reset Value  
Type  
0x21h  
NBY9:63  
Read/write  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Converter Operation Mode for MODE3  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
FPWM_EN3  
0
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
B6  
SYNC_MODE3  
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE3  
000000 = 0.77V  
000001 = 0.78V  
100000 = 1.09V  
100001 = 1.10V  
B5  
B4  
B3  
OUT_MODE3[5:0]  
100001  
B2  
100010 = 1.11V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
24 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
3
ܭ
8/!J D଎
ࡀ
໭ǖDPOUSPM  
ক଎
ࡀ
໭ဧถ૞ண፿ሆ౯
࢟
ᔜă  
REGISTER NAME  
CONTROL  
0x04h  
Address  
Reset Value  
Type  
0xE0h  
Read/write  
Special Features  
Reset upon V , IN_ UVLO or EN pulled low  
DD  
DEFAULT  
VALUE  
BIT  
B7 (MSB)  
B6  
NAME  
EN_PD  
DESCRIPTION  
0 = Pulldown on EN input is disabled.  
1
1 = Pulldown on EN input is enabled.  
0 = Pulldown on VID0 input is disabled.  
1 = Pulldown on VID0 input is enabled.  
VID0_PD  
VID1_PD  
1
1
0 = Pulldown on VID1 input is disabled.  
1 = Pulldown on VID1 input is enabled.  
B5  
B4  
B3  
—
—
—
—
—
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
0
0
0
0
0
B2  
B1  
B0 (LSB)  
______________________________________________________________________________________ 25  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
3
ܭ
9/!J D଎
ࡀ
໭ǖTZOD  
ক଎
ࡀ
໭ᒎ
ࢾ
ᅪ
ݝ
ဟᒩᏎ
ࡼ
ဟᒩຫൈă  
REGISTER NAME  
SYNC  
Address  
0x05h  
0x00h  
Read  
Reset Value  
Type  
NBY9:63  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
Sets Clock Frequency of External Clock Present on SYNC Input  
B7 (MSB)  
00 = 26MHz  
01 = 13MHz  
10 = 19.2MHz  
11 = 19.2MHz  
SYNC[1:0]  
00  
B6  
B5  
B4  
—
—
—
—
—
—
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
0
0
0
0
0
0
B3  
B2  
B1  
B0 (LSB)  
26 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
3
ܭ
:/!J D଎
ࡀ
໭ǖSBNQ  
ক଎
ࡀ
໭఼ᒜ࿟ဍ0ሆଢ଼৖ถă  
REGISTER NAME  
RAMP  
0x06h  
0x01h  
Read  
Address  
Reset Value  
Type  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
Control the RAMP Timing  
000 = 32mV/μs  
001 = 16mV/μs  
010 = 8mV/μs  
B7 (MSB)  
B6  
B5  
RAMP[2:0]  
011 = 4mV/μs  
100 = 2mV/μs  
101 = 1mV/μs  
110 = 0.5mV/μs  
111 = 0.25mV/μs  
000  
Only Valid When Converter is Operating with FPWM_EN_ = 0  
0 = Automatically change between power-save mode and PWM mode,  
depending on load current.  
1 = Converter always operates in power-save mode regardless of load  
current as long as FPWM_EN_ = 0. If FPWM_EN_ = 1, this setting is  
ignored.  
B4  
FORCE_HYS  
FORCE_OSC  
0
0
Force Oscillator While Running in Hysteretic Mode  
0 = Internal oscillator is disabled in power save when operating in  
hysteretic mode.  
B3  
1 = Internal oscillator is enabled in power save even when operating in  
hysteretic mode.  
B2  
B1  
—
RAMP_DOWN  
—
Reserved for future use.  
0
0
1
Active Ramp-Down Control for Power-Save Mode  
0 = Active ramp disabled for power-save mode.  
1 = During ramp-down, the zero-crossing detector is disabled allowing  
negative current to flow through the nMOS device.  
B0 (LSB)  
Reserved for future use.  
______________________________________________________________________________________ 27  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
3
ܭ
21/!J D଎
ࡀ
໭ǖDIJQ`JE2  
ক଎
ࡀ
໭਺ᎌ਌በಢቯ
ܠ
੓)31*ă  
REGISTER NAME  
CHIP_ID1  
Address  
0x08h  
0x20h  
Read  
—
Reset Value  
Type  
NBY9:63  
Special Features  
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
B7 (MSB)  
B6  
DIE_TYPE[7:4]  
BCD character (2)  
BCD character (0)  
0010  
0000  
B5  
B4  
B3  
B2  
DIE_TYPE[3:0]  
B1  
B0 (LSB)  
3
ܭ
22/!J D଎
ࡀ
໭ǖDIJQ`JE3  
ক଎
ࡀ
໭਺ᎌ਌በಢቯ
ܠ
੓ਜ਼ዚෞ
۾ۈ
੓ă  
REGISTER NAME  
CHIP_ID2  
0x09h  
0x1Ah  
Read  
Address  
Reset Value  
Type  
Special Features  
—
DEFAULT  
VALUE  
BIT  
NAME  
DESCRIPTION  
B7 (MSB)  
B6  
DASH[7:4]  
BCD character 1 (1)  
BCD character A (A)  
0001  
1010  
B5  
B4  
B3  
B2  
MASK_REV[3:0]  
B1  
B0 (LSB)  
28 ______________________________________________________________________________________  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
NBY9:63  
৊
ࢾ
MJEFBMLj
࢟
ঢ
࢟
ഗᆬ݆ख़ख़ᒋᆐ1/36 y JPVU)NBY*ă
࢟
 
``````````````````````````````` ።፿ቧᇦ  
ঢ
࢟
ഗख़ᒋᆐ2/236 y JPVU)NBY*ăཀྵۣ
࢟
ঢ
ۥ
ਜ਼
࢟
ഗ
ࡍ
᎖  
࢟
ঢख़ᒋ
࢟
ഗLj༦
࢟
ঢ
ࡼ
ऄ
ࢾ
ᔢ
ࡍ
ᒇഗ
࢟
ഗ
ࡍ
᎖ᔢ
ࡍ
ၒ  
߲
࢟
ഗ)JPVU)NBY**ă
ݧ
፿ቃ᎖MJEFBM
࢟ࡼ
ঢᒋᎌᓐ᎖ିቃ  
࢟
ঢ
ࡁߛ
Lj
ࡣ
ྙਫ
࢟
ঢᒋਭቃLjख़ᒋ
࢟
ঢ
࢟
ഗ୓ᐐ
ࡍ
Ljభ  
ถኊገৎ
ࡼࡍ
ၒ߲
࢟
ྏ౶ጴᒜၒ߲ᆬ݆ă
ݧ
፿
ࡍ
᎖MJEFBM  
ࡼ
࢟
ঢᒋభ૝
ࡻ
୷
ࡼࡍ
ၒ߲
࢟
ഗLj
ࡣ
ኊገᇕಯ
ࡁߛ
୷
ࡍ
 
ࡼ
࢟
ঢă
ܭ
23೰߲೫ᅎୀ
࢟ࡼ
ঢă  
࢟
ঢኡᐋ  
ݧ
፿ሆါଐႯ
࢟
ঢᒋ)MJEFBM*ǖ  
4 × V × D × 1-D  
(
)
IN  
OUT MAX  
L
=
IDEAL  
I
× f  
OSC  
(
)
୓
࢟
ঢ
࢟
ഗᆬ݆
ࡼ
ख़ख़ᒋ࿸
ࢾ
ᆐᔢ
ࡍ
ၒ߲
࢟
ഗ
ࡼ
205Ljᑩ  
࡬
໭ຫൈgPTDᆐ4/36NI{Ljᐴహ
܈
Eᆐǖ  
V
OUT  
D =  
V
IN  
ܭ
23/!ᅎୀ
࢟
ঢ  
INDUCTANCE  
(μH)  
DC RESISTANCE  
CURRENT RATING  
(mA)  
DIMENSIONS  
L x W x H (mm)  
MANUFACTURER  
SERIES  
(Ω typ)  
0.47  
1.0  
0.025  
0.033  
3800  
2700  
DE2815C  
3.2 x 3.0 x 1.5  
Toko  
TDK  
DB3015C  
VLS252010ET  
VLS4012ET  
LPS5015  
1.0  
0.47  
1.0  
0.036  
0.038  
0.050  
0.050  
0.038  
0.055  
0.030  
2700  
2800  
2800  
3900  
3400  
3800  
2600  
3.2 x 3.2 x 1.5  
2.5 x 2.0 x 1.0  
4.0 x 4.0 x 1.2  
5.0 x 5.0 x 1.5  
5.0 x 5.0 x 1.0  
4.4 x 4.4 x 1.4  
4.8 x 4.8 x 1.8  
1.0  
Coilcraft  
Wurth  
LPS5010  
0.47  
0.7  
LPS4414  
744042001  
1.0  
______________________________________________________________________________________ 29  
3/6Bଢ଼ኹቯ
ࢯ
ஂ໭Lj  
ᄋ৙
ތ
ॊᏐ
࣡
ଶ
ހ
Lj3nn!y!3nn!XMQॖᓤ  
ၒྜྷ
࢟
ྏኡᐋ  
৖੒  
ଢ଼ኹቯED.ED
ࢯ
ஂ໭ᒦ
ࡼ
ၒྜྷ
࢟
ྏ፿᎖ଢ଼
ࢅ
࠭
ߔ࢟
૞໚჈  
ၒྜྷ
࢟
Ꮞᇢ၃
࢟ࡼ
ഗख़ᒋLj݀ିቃ఼ᒜ໭ᒦ
ࡼ
ఎਈᐅဉă  
࣪
᎖
ࣶࡍ
ၫ።፿Lj୐ፇ
ݧ
፿21μGჿࠣ
࢟
ྏਜ਼1/2μGჿࠣ
࢟
 
ྏ݀ೊăၒྜྷ
࢟
ྏᏴఎਈຫൈሆ
ࡼ
ᔜఝ።ቃ᎖ၒྜྷᏎᔜ  
ఝLj࠭ऎဧ঱ຫఎਈ
࢟
ഗ
ݙ
્ᄰਭၒྜྷᏎăၒྜྷ
࢟
ྏ
ܘ
 
ኍ൸ᔗଢ଼ኹ
ࢯ
ஂ໭
࣪
ၒྜྷᆬ݆
࢟
ഗ
ࡼ
ገཇăჿࠣ
࢟
ྏऻ  
ޟ
း੝
ࠀ
ಯ࿟
࢟
໐ମ
ࡼ
಍፻
࢟
ഗLjဵၒྜྷ
࢟
ྏ
ࡼ
၅ኡă  
ᑵཀྵኡᐋၒྜྷ
࢟
ྏLjဧၒྜྷᆬ݆
࢟
ഗ፛໦
ࡼ
ᆨဍ
ݙ
ިਭ  
ࡍ
Ꮦ,21°Dă
࣪
᎖ଢ଼ኹቯED.ED
ࢯ
ஂ໭Ljᔢ
ࡍ
ၒྜྷᆬ݆
࢟
 
ഗᆐၒ߲
࢟
ഗ
ࡼ
203ăᔢ
ࡍ
ၒྜྷᆬ݆
࢟
ഗ߲ሚᏴଢ଼ኹ
ࢯ
ஂ  
໭৔ᔫᏴ61&ᐴహ
܈
)WJO > 3 y WPVU*
ࡼ
༽ౚሆăਈ᎖ၒྜྷ  
࢟
ྏኡᐋ
ࡼ
ᅎୀ
ݬ
ၫLj༿
ݬ
ఠNBY9:63ຶৰ
ۇ
ă  
JD௥ᎌེਈ
ࣥ
৖ถLjۣઐJDᏴ਌በᆨ
ࣞ
ިਭ,271°Dဟ
ۻݙ
 
ႼડLjሮᇼቧᇦ༿
ݬ
ఠེਭᏲۣઐ
ݝ
ॊăᆐऴᒏེਭᏲ  
݀Ꮴ኏ඛവ
ࢯ
ஂ໭ᄋ৙ᔢ
ࡍ
ঌᏲ
࢟
ഗLjཀྵۣJD
ޘ
ည
ࡼ
ེ೟  
భጲ੒ྲ
ࡵ
QDC࿟ऻ
ޟ
ᒮገă  
໭ୈᑵཀྵ
ڔ
ᓤᏴ
ށࣶ
QDC࿟ဟLjஉᒗણஹ
ࡼ
ེᔜ)θKB*
࢜
ቯ  
ᒋᆐ5:°D0Xă  
NBY9:63  
QDC
ݚ
௜  
ᎅ᎖
ࡀ
Ᏼ঱Ⴅఎਈ݆ተਜ਼
࢟ࡍ
ഗᄰവLjኊገཱྀᑞ
ݚ
௜QDCLj  
ጲ૝
ࡻ
ᔢଛቶถăJDਜ਼
࢟
ঢĂၒྜྷ
࢟
ྏૺၒ߲
࢟
ྏᒄମ
ࡼ
 
ᔓሣ
ࣞޠ
።஧భถ
࣢
Ǘۣ
࣢ߒ
ĂᒇĂ౑
ࡼ
፛ሣăDJOਜ਼  
DPVU
ࡼ
୻
࣡࢐
።஧೟ణதLj݀ೌ୻ᒗQHOEă୓BHOEਜ਼  
QHOEᒇ୻ೌ୻ᒗ୻
࢐
ཌᎮăNBY9:63ຶৰ
ۇ
ᄋ৙೫ጙৈ  
QDC
ݚ
௜ਜ਼
ݚ
ሣဣಿă  
ၒ߲
࢟
ྏኡᐋ  
ଢ଼ኹቯED.ED
ࢯ
ஂ໭
ࡼ
ၒ߲
࢟
ྏ፿᎖ۣ
ߒ
୷ቃ
ࡼ
ၒ߲ᆬ  
݆Lj݀ཀྵ఼ۣᒜણവᆮ
ࢾ
ă
࣪
᎖
ࣶࡍ
ၫ።፿Lj୐ፇ
ݧ
፿  
21μGჿࠣ
࢟
ྏਜ਼1/2μGჿࠣ
࢟
ྏ݀ೊăၒ߲
࢟
ྏથ
ܘ
ኍᏴ  
ఎਈຫൈሆ௥ᎌ
ࢅ
ᔜఝăჿࠣ
࢟
ྏĂ௡੝ᇕ
࢟
ྏਜ਼ᶉ
࢟
 
ྏ
܈
୷੝းLj໚ᒦჿࠣ
࢟
ྏ௥ᎌᔢ
ࢅ
FTSਜ਼ᔢቃ঱ຫᔜఝă  
``````````````````````````````` በຢቧᇦ  
PROCESS: BiCMOS  
࢟
ྏ)઄൒FTS*
ޘ
ည
ࡼ
ၒ߲ᆬ݆
ࡍ
Ꮦᆐǖ  
I
L PEAK  
(
)
V
=
RIPPLE  
2π × f  
× C  
OSC  
OUT  
``````````````````````````````` ॖᓤቧᇦ  
࢟
ྏFTS
ޘ
ည
ࡼ
ᆬ݆ᆐǖ  
ྙኊᔢத
ࡼ
ॖᓤᅪተቧᇦਜ਼੆๤
ݚ
௜Lj༿
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Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______________________ 31  
© 2010 Maxim Integrated Products  
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MAX8952 2.5A降压型  
调 节器，提供差分远端检测，2mm x 2mm WLP封装 - 概述  
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Maxim > 产品 > 电源和电池管理 > MAX8952  
MAX8952  
2.5A降压型  
调
节器，提供差分远端检测，2mm x 2mm WLP封装  
允许手持产品  
定购信 用户说 所有内容  
的应用处理器运行在最高时钟频率  
概述  
技术文档  
息
明 (0)  
状况  
状况：生产中。  
概述  
数据资料  
。器件工作于2.5V至5.5V输入电压范  
。全差分远  
差小于±1.5%。  
MAX8952高效DC-DC降压开关调 节器可提供高达2.5A输出电流  
完整的数据资料  
，支持手持产品中的通用电池技术。输出电压可通过I²C接口在0.77V至1.40V范 内设置  
下载  
围
围
端检测保证了负载端精确 的直流电压。在整个负载、电源和温度 内输出总误  
范
围
英文  
Rev. 0 (PDF, 2.1MB)  
下载  
中文  
Rev. 0 (PDF, 1.2MB)  
该款IC工作于3.25MHz固定频率，较高的工作频率大大减  
小了外部元件尺寸。转换器的开关频率可以  
同
步至系统主时钟。当同步至外部时钟时，IC测量外部时钟的频率，确 保在开关频率转换到外部时钟  
频率之前保持该时钟稳定。  
片内DAC允许以10mV步长调 节输出电压。输出电压可以通过I²C接口直接设置  
内寄 存器，然后使用2个VID逻辑信号选择适当的寄 存器。器件的其它功能包括可降低浪涌电流的内部  
软启动控制电路、输出过压、过流和过热保护。  
，也可以预先加载至片  
关键特性  
确
应用/使用  
保2.5A输出电流 蜂窝电话与智能电话  
(770mV至1.40V，以10mV为步长) PDA和MP3播放器  
平板PC  
通过I²C接口可编程V  
OUT  
1.40V输出时，初始精度  
在整个负载、电源和温度 内输出精度为±1.5% (DCR ≤ 38.5mΩ)  
电源省电模式提高轻载效率  
定3.25MHz PWM开关频率  
1.0µH小尺寸电感  
可以同步到13MHz、19.2MHz或26MHz系统时钟  
过压和过流保护  
为±0.5%  
范围  
固
工作在2.5V至5.5V输入电源  
热关断保护  
片上FET和同  
步整流器  
400kHz I²C接口  
< 1µA的关断电流  
16焊  
球、2mm x 2mm WLP封装  
图表  
http://china.maxim-ic.com/datasheet/index.mvp/id/6815[2011-1-14 6:23:40]  
 
MAX8952 2.5A降压型  
调 节器，提供差分远端检测，2mm x 2mm WLP封装 - 概述  
典型 工作电路  
更多信  
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新品发布 [ 2010-07-15 ]  
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参考文献： 19-5318 Rev. 0; 2010-07-01  
本页最后一次更新: 2011-01-12  
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© 2011 Maxim Integrated Products版权所有  
http://china.maxim-ic.com/datasheet/index.mvp/id/6815[2011-1-14 6:23:40]  
19-5318; Rev 0; 6/10  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
General Description  
Features  
The MAX8952 high-efficiency DC-to-DC step-down  
switching regulator delivers up to 2.5A of output current.  
The device operates from a 2.5V to 5.5V input voltage  
range, supporting commonly-used battery technologies  
in handsets. The output voltage is I2C programmable  
from 0.77V to 1.40V. Fully differential remote sense  
ensures precise DC regulation at the load. Total output  
error is less than 1.5ꢀ over load, line, and temperature.  
o 2.5A Guaranteed Output Current  
2
o I C Programmable V  
(770mV to 1.40V in 10mV  
OUT  
Steps)  
o Initial Accuracy 0.5ꢀ at 1.40V Output  
o
1.5ꢀ Output Accuracy Oꢁer ꢂoadꢃ ꢂineꢃ and  
Temperature (DCR ≤≤ 38.5mΩ)  
o Power-Saꢁe Mode Increases ꢂight ꢂoad Efficiency  
o Fixed 3.25MHz PWM Switching Frequency  
o Small 1.0µH Inductor  
The IC operates at a 3.25MHz fixed frequency. The high  
operating frequency minimizes the size of external com-  
ponents. The switching frequency of the converter can be  
synchronized to the master clock of the application. When  
synchronizing to an external clock, the IC measures the  
frequency of the external clock to ensure that the clock is  
stable before changing the switching frequency to the  
external clock frequency.  
o Synchronizes to 13MHzꢃ 19.2MHzꢃ or 26MHz  
System Clock When Aꢁailable  
o Oꢁerꢁoltage and Oꢁercurrent Protection  
o Operates from 2.5V to 5.5V Input Supply  
o Thermal Shutdown Protection  
An on-board DAC allows adjustment of the output volt-  
age in 10mV steps. The output voltage can be pro-  
grammed directly through the I2C interface, or by  
preloading a set of on-board registers and using the  
two VID logic signals to select the appropriate register.  
Other features include internal soft-start control circuitry  
to reduce inrush current, output overvoltage, overcur-  
rent, and overtemperature protection.  
o On-Chip FET and Synchronous Rectifier  
2
o 400kHz I C Interface  
o < 1µA Shutdown Current  
o 16-Bumpꢃ 2mm x 2mm WꢂP Package  
Ordering Information  
PART  
TEMP RANGE  
PIN-PACKAGE  
Applications  
16 Bump WLP  
(0.5mm pitch)  
Cell Phones and Smartphones  
PDAs and MP3 Players  
Tablet PCs  
MAX8952EWE+T  
-40°C to +85°C  
+Denotes a lead(Pb)-free/RoHS-compliant package.  
T = Tape and reel.  
Typical Operating Circuit  
Pin Configuration  
TOP VIEW  
(BUMPS ON BOTTOM  
2.5V TO  
5.5V  
1.8V TO  
3.6V  
VID1  
A3  
IN1  
A1  
AGND  
A2  
IN2  
A4  
+
MAX8952  
IN2  
LX  
V
DD  
10µF  
10µF  
0.1µF  
0.1µF  
1µH  
10µF  
2.5V TO  
5.5V  
V
OUT  
SNS+  
B1  
EN  
B2  
LX  
B3  
LX  
B4  
SCL  
SDA  
(0.77V TO  
1.40V)  
0.1µF  
11Ω  
PGND  
IN1  
PGND  
0.1µF  
PGND  
SNS-  
C1  
VID0  
C2  
SYNC  
EN  
C3  
SCL  
D3  
C4  
SYNC  
D4  
SNS+  
SNS-  
VID0  
CPU  
V
SDA  
D2  
DD  
VID1  
D1  
AGND  
WꢂP 0.5mm PITCH  
________________________________________________________________ Maxim Integrated Products  
1
For pricingꢃ deliꢁeryꢃ and ordering informationꢃ please contact Maxim Direct at 1-888-629-4642ꢃ  
or ꢁisit Maxim’s website at www.maxim-ic.com.  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
ABSOꢂUTE MAXIMUM RATINGS  
IN1, IN2 to AGND..................................................-0.3V to +6.0V  
Operating Temperature Range ...........................-40°C to +85°C  
V
to AGND.........................................................-0.3V to +4.0V  
Junction to Ambient Thermal Resistance (θ ) (Note 1)...49°C/W  
DD  
JA  
LX, SNS+, VID0, VID1, EN to AGND..........-0.3V to (V  
SCL, SDA, SYNC to AGND.........................-0.3V to (V  
PGND, SNS- to AGND...........................................-0.3V to +0.3V  
+ 0.3V)  
+ 0.3V)  
Junction Temperature......................................................+150°C  
Storage Temperature Range.............................-65°C to +150°C  
Soldering Temperature (reflow) .......................................+260°C  
IN1  
DD  
RMS LX Current ..............................................................2500mA  
Continuous Power Dissipation (T = +70°C)  
A
16-Bump WLP 0.5mm Pitch  
(derate 20.4mW/°C above +70°C).........................1632mW  
MAX8952  
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-  
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
EꢂECTRICAꢂ CHARACTERISTICS  
(V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at  
DD A  
IN1  
IN2  
AGND  
PGND  
T
A
= +25°C.) (Note 2)  
PARAMETER  
IN1, IN2 Operating Range  
CONDITIONS  
MIN  
2.5  
TYP  
MAX  
5.5  
UNITS  
V
V
V
Operating Range  
1.8  
3.6  
DD  
V
Undervoltage Lockout  
DD  
V
falling  
0.54  
2.10  
0.865  
50  
1.35  
2.20  
V
DD  
(UVLO) Threshold  
V
UVLO Hysteresis  
mV  
V
DD  
IN_ Undervoltage Lockout  
(UVLO) Threshold  
V
V
falling  
2.15  
IN  
IN_ UVLO Hysteresis  
70  
mV  
µA  
T
A
T
A
T
A
T
A
T
A
T
A
= +25°C  
= +85°C  
= +25°C  
= +85°C  
= +25°C  
= +85°C  
0.01  
0.01  
0.25  
0.25  
0.35  
0.35  
1
1
1
= V  
= 5.5V,  
IN2  
IN1  
V
Shutdown Supply Current  
DD  
EN = V  
= AGND  
DD  
IN1, IN2 Shutdown Supply  
Current  
V
= V  
= 5.5V,  
IN1  
IN2  
µA  
µA  
EN = V  
= AGND  
DD  
V
V
= V  
= 5.5V, SCL = SDA =  
IN1  
IN2  
IN1, IN2 Standby Supply Current  
, EN = AGND, I2C ready  
DD  
V
= V  
= V  
= 3.6V,  
DD  
IN1  
IN2  
T
= +25°C  
= +85°C  
0.02  
0.02  
1
A
A
V
Standby Supply Current  
µA  
SCL = SDA = V , EN = AGND,  
DD  
DD  
I2C ready  
T
ꢂOGIC INTERFACE  
EN, VID0, VID1  
SYNC, SCL, SDA  
EN, VID0, VID1  
SYNC, SCL, SDA  
1.4  
V
V
= V  
= 2.5V to 5.5V,  
IN2  
IN1  
DD  
Logic Input High Voltage (V  
)
IH  
V
V
= 1.8V to 3.6V  
0.7 x V  
DD  
0.4  
V
V
= V = 2.5V to 5.5V,  
= 1.8V to 3.6V  
IN1  
DD  
IN2  
Logic Input Low Voltage (V )  
IL  
0.3 x V  
DD  
T
T
= +25°C  
= +85°C  
-1  
0.01  
0.01  
+1  
A
A
SDA, SCL, SYNC Logic Input  
Current  
V
= 0V or V = 3.6V,  
IL IH  
µA  
EN = AGND  
2
_______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
EꢂECTRICAꢂ CHARACTERISTICS (continued)  
(V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =  
DD A A  
IN1  
IN2  
AGND  
PGND  
+25°C.) (Note 2)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Controlled by I2C command:  
VID0_PD = 1  
VID1_PD = 1  
VID0, VID1, EN Logic Input  
Pulldown Resistor  
200  
320  
450  
kΩ  
EN_PD = 1  
2
I C INTERFACE  
SDA Output Low Voltage  
I2C Clock Frequency  
I
= 3mA  
0.03  
0.1  
0.4  
V
SDA  
BUF  
400  
kHz  
Bus-Free Time Between START  
and STOP  
t
t
1.3  
0.6  
µs  
µs  
Hold Time Repeated START  
Condition  
HD_STA  
SCL Low Period  
SCL High Period  
t
t
1.3  
0.6  
0.2  
0.2  
µs  
µs  
LOW  
HIGH  
Setup Time Repeated START  
Condition  
t
0.6  
0.1  
µs  
SU_STA  
SDA Hold Time  
t
t
t
0
-0.01  
0.05  
0.1  
µs  
µs  
µs  
HD_DAT  
SU_DAT  
SU_STO  
SDA Setup Time  
0.1  
0.6  
Setup Time for STOP Condition  
STEP-DOWN DC-DC REGUꢂATOR  
FPWM_EN_ = 0, V  
FPWM_EN_ = 1, V  
= 1.27V, no switching  
54  
9
80  
µA  
OUT  
IN1 + IN2  
Supply Current  
= 1.27V, f = 3.25MHz  
mA  
OUT  
sw  
Minimum Output Capacitance  
Required for Stability  
V
= 0.77V to 1.40V,  
= 0 to 2.5A  
OUT  
10  
µF  
I
OUT  
OUT Voltage Range  
10mV steps  
Rising, 50mV hysteresis (typ)  
0.770  
1.65  
1.400  
1.9  
V
V
Output Overvoltage Protection  
1.8  
_______________________________________________________________________________________  
3
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
EꢂECTRICAꢂ CHARACTERISTICS (continued)  
(V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =  
A A  
IN1  
IN2  
AGND  
PGND  
DD  
+25°C.) (Note 2)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
No load, V  
FPWM_EN_ = 1  
= 2.5V to 5.5V, V  
= 1.27V  
IN_  
OUT  
OUT  
OUT  
-0.5  
+0.5  
No load, V = 2.5V to 5.5V, V  
= 0.77V,  
= 1.40V,  
IN_  
OUT Voltage Accuracy  
Load Regulation  
-1.0  
-0.5  
+1.0  
+0.5  
ꢀ
MAX8952  
FPWM_EN_ = 1  
No load, V = 2.5V to 5.5V, V  
IN_  
FPWM_EN_ = 1  
R is the resistance from LX to SNS+ (output)  
L
R /25  
L
V/A  
RAMP[2:0] = 000  
RAMP[2:0] = 001  
RAMP[2:0] = 010  
RAMP[2:0] = 011  
RAMP[2:0] = 100  
RAMP[2:0] = 101  
RAMP[2:0] = 110  
RAMP[2:0] = 111  
32.50  
16.25  
8.125  
4.063  
2.031  
1.016  
0.508  
0.254  
RAMP Timer  
mV/µs  
Peak Current Limit  
(p-Channel MOSFET)  
3.45  
2.7  
4.2  
3.6  
2.5  
4.8  
4.5  
3.0  
A
A
A
Valley Current Limit  
(n-Channel MOSFET)  
Hysteretic mode  
PWM mode  
Negative Current Limit  
(n-Channel MOSFET)  
2.0  
n-Channel Zero-Crossing  
Threshold  
50  
mA  
Ω
LX pFET On-Resistance  
IN2 to LX, I = -200mA  
LX  
0.08  
0.06  
0.16  
0.12  
+1  
FPWM_EN_ = 0  
LX nFET On-Resistance  
Ω
LX to PGND, I = 200mA  
LX  
T
T
= +25°C  
= +85°C  
-1  
0.03  
0.05  
3.25  
A
LX Leakage  
V
= 5.5V or 0V  
µA  
LX  
A
Internal oscillator, PWM mode  
2.82  
2.43  
3.56  
4.06  
Internal oscillator, power-save mode before entering  
PWM mode  
3.25  
Operating Frequency  
13MHz = f  
, SYNC[1:0] = 01  
f
f
f
/4  
MHz  
SYNC  
SYNC  
SYNC  
SYNC  
19.2MHz = f  
, SYNC[1:0] = 10 or 11  
/6  
/8  
SYNC  
26MHz = f  
, SYNC[1:0] = 00  
SYNC  
4
_______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
EꢂECTRICAꢂ CHARACTERISTICS (continued)  
(V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at T =  
DD A A  
IN1  
IN2  
AGND  
PGND  
+25°C.) (Note 2)  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Forced PWM mode only, minimum duty cycle in  
(FPWM_EN_ = 1) = 0ꢀ  
Minimum Duty Cycle  
Maximum Duty Cycle  
16  
ꢀ
60  
30  
ꢀ
ns  
Ω
Minimum On- and Off-Time  
OUT Discharge Resistance  
40  
50  
During shutdown or UVLO, from SNS+ to PGND  
650  
600  
SNS+, SNS- Input Impedance  
400  
850  
kΩ  
Time Delay from PWM  
to Power-Save Mode  
Time required for error amplifier to stabilize before  
switching mode  
70  
µs  
µs  
Time Delay from Power-Save  
Mode to PWM  
Time required for error amplifier to stabilize before  
switching mode  
140  
SYNCHRONIZATION (SYNC)  
SYNC[1:0] = 00  
SYNC[1:0] = 1X  
SYNC[1:0] = 01  
18.9  
14.2  
9.5  
26.0  
19.2  
13.0  
13  
38.0  
28.5  
19.0  
SYNC Capture Range  
MHz  
ns  
SYNC Pulse Width  
PROTECTION CIRCUITS  
Thermal-Shutdown Hysteresis  
Thermal Shutdown  
20  
°C  
°C  
+160  
Note 2: All devices are 100ꢀ production tested at T = +25°C. Limits over the operating temperature range are guaranteed by  
A
design.  
_______________________________________________________________________________________  
5
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
Typical Operating Characteristics  
(Typical Operating Circuit, V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.1V, V  
= 1.8V, T = +25°C, unless otherwise noted.)  
A
IN1  
IN2  
AGND  
PGND  
OUT  
DD  
EFFICIENCY vs. LOAD CURRENT  
(1.0V OUTPUT, SYNC OFF)  
EFFICIENCY vs. LOAD CURRENT  
(1.1V OUTPUT, SYNC OFF)  
EFFICIENCY vs. LOAD CURRENT  
(1.4V OUTPUT, SYNC OFF)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
90  
80  
70  
60  
MAX8952  
V
= 3.2V  
3.6V  
V
IN  
= 3.2V  
3.6V  
V
IN  
= 3.2V  
3.6V  
IN  
50  
40  
30  
20  
10  
0
4.2V  
4.2V  
4.2V  
FORCED PWM  
FORCED PWM  
FORCED PWM  
0.0001 0.001  
0.01  
0.1  
1
10  
0.0001 0.001  
0.01  
0.1  
1
10  
0.0001 0.001  
0.01  
0.1  
1
10  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
EFFICIENCY vs. LOAD CURRENT  
(1.0V OUTPUT, 26MHz SYNC)  
EFFICIENCY vs. LOAD CURRENT  
(1.1V OUTPUT, 26MHz SYNC)  
EFFICIENCY vs. LOAD CURRENT  
(1.4V OUTPUT, 26MHz SYNC)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
TRANSITION TO PWM  
POWER SAVE  
V
= 3.2V  
3.6V  
V
IN  
= 3.2V  
3.6V  
V
IN  
= 3.2V  
3.6V  
IN  
4.2V  
4.2V  
4.2V  
FORCED PWM  
0.1  
FORCED PWM  
0.1  
FORCED PWM  
0.0001 0.001  
0.01  
1
10  
0.0001 0.001  
0.01  
1
10  
0.0001 0.001  
0.01  
0.1  
1
10  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
SWITCHING FREQUENCY  
vs. LOAD CURRENT  
NO-LOAD SUPPLY CURRENT vs.  
SUPPLY VOLTAGE (POWER SAVE)  
SWITCHING FREQUENCY  
vs. TEMPERATURE  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
3.6  
3.5  
3.4  
3.3  
3.2  
3.1  
FORCED PWM  
26MHz SYNC  
NO SYNC  
TRANSITION TO PWM  
POWER SAVE  
NO SYNC  
1.3V OUTPUT, 500mA LOAD  
V
= 3.6V  
= 1.4V  
IN  
V
OUT  
3.0  
0
0.5  
1.0  
1.5  
2.0  
2.5  
2.5  
3.5  
4.5  
5.5  
-40  
-15  
10  
35  
60  
85  
LOAD CURRENT (A)  
SUPPLY VOLTAGE (V)  
TEMPERATURE (°C)  
6
_______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
Typical Operating Characteristics (continued)  
(Typical Operating Circuit, V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.1V, V = 1.8V, T = +25°C, unless otherwise noted.)  
DD A  
IN1  
IN2  
AGND  
PGND  
OUT  
NO-LOAD SUPPLY CURRENT vs.  
SUPPLY VOLTAGE (FORCED PWM)  
OUTPUT VOLTAGE vs. LOAD CURRENT  
OUTPUT VOLTAGE vs. LOAD CURRENT  
20  
18  
16  
14  
12  
10  
8
1.42  
1.115  
NO SYNC  
T = +25°C  
A
T = +85°C  
A
1.41  
1.40  
1.39  
1.38  
1.37  
1.36  
1.110  
FORCED PWM  
1.105  
26MHz SYNC  
1.100  
1.095  
T = -40°C  
A
POWER SAVE  
6
POWER SAVE  
4
1.090  
V
= 3.6V  
V
OUT  
= 3.6V  
= 1.1V  
IN  
IN  
2
V
OUT  
= 1.4V  
V
0
1.085  
2.5  
3.5  
4.5  
5.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
SUPPLY VOLTAGE (V)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LIGHT LOAD SWITCHING WAVEFORMS  
OUTPUT VOLTAGE vs. LOAD CURRENT  
MAXMAX8952 toc14  
1.010  
1.005  
1.000  
0.995  
0.990  
0.985  
0.980  
FORCED PWM  
V
OUT  
20mV/div  
2V/div  
V
LX  
POWER SAVE  
I
L
V
OUT  
= 3.6V  
= 1.0V  
IN  
200mA/div  
V
10mA LOAD, V  
= 1.3V  
OUT  
0
0.5  
1.0  
1.5  
2.0  
2.5  
2µs/div  
LOAD CURRENT (A)  
MEDIUM LOAD SWITCHING  
WAVEFORMS  
HEAVY LOAD SWITCHING WAVEFORMS  
MAX8952 toc16  
MAX8952 toc15  
20mV/div  
2V/div  
V
20mV/div  
V
OUT  
OUT  
V
LX  
V
2V/div  
LX  
I
L
1A/div  
I
L
1.8A LOAD  
500mA LOAD  
= 1.3V  
500mA/div  
V
OUT  
= 1.3V  
V
OUT  
200ns/div  
200ns/div  
_______________________________________________________________________________________  
7
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
Typical Operating Characteristics (continued)  
(Typical Operating Circuit, V  
= V  
= 3.6V, V  
= V  
= 0V, V  
= 1.1V, V  
= 1.8V, T = +25°C, unless otherwise noted.)  
IN1  
IN2  
AGND  
PGND  
OUT  
DD A  
LIGHT LOAD STARTUP WAVEFORMS  
HEAVY LOAD STARTUP WAVEFORMS  
MAX8952 toc17  
MAX8952 toc18  
10I LOAD  
1I LOAD  
V
OUT  
V
OUT  
1V/div  
1V/div  
MAX8952  
400mA  
I
IN  
100mA/div  
500mA/div  
200mA/div  
I
IN  
I
L
I
L
500mA/div  
5V/div  
V
V
EN  
5V/div  
EN  
200µs/div  
200µs/div  
PREBIAS STARTUP WAVEFORMS  
LINE TRANSIENT RESPONSE (4.2V TO  
(FORCED PWM)  
3.2V TO 4.2V) SYNC OFF  
MAX8952 toc19  
MAX8952 toc20  
OUTPUT PREBIASED TO 1.3V  
STARTUP TO 1.1V  
1V/div  
V
IN  
V
OUT  
500mV/div  
1A/div  
V
OUT  
20mV/div  
I
L
200mA/div  
I
L
300mA LOAD  
20µs/div  
V
EN  
5V/div  
200µs/div  
LINE TRANSIENT RESPONSE (4.2V TO  
LOAD TRANSIENT RESPONSE  
3.2V TO 4.2V) 26MHz SYNC  
(1mA TO 1A)  
MAX8952 toc21  
MAX8952 toc22  
1V/div  
50mV/div  
V
IN  
V
OUT  
V
OUT  
20mV/div  
I
L
500mA/div  
1A/div  
I
L
200mA/div  
300mA LOAD  
20µs/div  
I
OUT  
40µs/div  
8
_______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
Typical Operating Characteristics  
(T = +25°C, unless otherwise noted.)  
A
LOAD TRANSIENT RESPONSE  
(1A to 1mA)  
LOAD TRANSIENT RESPONSE  
(5mA TO 1.8A)  
MAX8952 toc23  
MAX8952 toc24  
50mV/div  
V
OUT  
V
OUT  
50mV/div  
I
500mA/div  
I
L
L
1A/div  
1A/div  
I
1A/div  
OUT  
I
OUT  
40µs/div  
40µs/div  
SYNCHRONIZATION RESPONSE  
(26MHz SYNC)  
LOAD TRANSIENT RESPONSE  
(1.8A to 5mA)  
MAX8952 toc26  
MAX8952 toc25  
FORCED PWM, NO LOAD  
V
2V/div  
SYNC  
V
OUT  
100mV/div  
1A/div  
V
OUT  
20mV/div  
I
L
V
LX  
2V/div  
I
200mA/div  
L
I
1A/div  
OUT  
1µs/div  
20µs/div  
OUTPUT VOLTAGE CHANGE RESPONSE  
MAX8952 toc27  
10I LOAD,  
POWER SAVE  
32mV/µs RAMP  
V
VID0  
2V/div  
1.3V  
0.9V  
0.9V  
500mV/div  
V
OUT  
I
L
200mA/div  
40µs/div  
_______________________________________________________________________________________  
9
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
Pin Description  
PIN  
NAME  
FUNCTION  
Analog Supply Voltage Input. The input voltage range is 2.5V to 5.5V. Install an 11Ω resistor between  
IN1 and the input supply. Bypass the IN1 to AGND with a 0.1µF ceramic capacitor as close as  
possible to the IC. Connect IN1 and IN2 to the same power source.  
A1  
IN1  
A2  
A3  
AGND  
VID1  
Analog Ground. Connect AGND to the PCB ground plane.  
MAX8952  
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output  
voltage.  
Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal  
p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 2x 10µF and 0.1µF ceramic  
capacitor as close as possible to the IC. Connect IN1 and IN2 to the same power source.  
A4  
IN2  
B1  
B2  
SNS+  
EN  
Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load.  
Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in  
shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND.  
Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel  
MOSFETs. LX is high impedance during shutdown.  
B3, B4  
C1  
LX  
SNS-  
VID0  
PGND  
Output Voltage Remote Sense, Negative Input. Connect to a quiet ground directly at the load.  
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output  
voltage.  
C2  
C3, C4  
Power Ground. Connect both PGND bumps to the PCB ground plane.  
Logic Input Supply Voltage. Connect V  
to the logic supply driving SDA, SCL, and SYNC. Bypass  
2
DD  
D1  
V
V
to AGND with a 0.1µF ceramic capacitor. When V  
drops below the UVLO threshold, the I C  
DD  
DD  
DD  
registers are reset, but the EN control is still active in this mode.  
2
D2  
D3  
SDA  
SCL  
I C Data Input. Data is read on the rising edge of SCL and data is clocked out on the falling edge of SCL.  
2
I C Clock Input  
External Clock Synchronization Input. Connect SYNC to a 13MHz, 19.2MHz, or 26MHz system clock.  
2
D4  
SYNC  
The DC-DC regulator can be forced to synchronize to this external clock depending on I C setting. See  
Table 8. SYNC does not have an internal pulldown. Connect SYNC to AGND if not used.  
10 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
SYNC  
OSC  
CLOCK GEN  
IN2  
LX  
V
DD  
2
I C INTERFACE  
SCL  
SDA  
PWM LOGIC  
IN1  
EN  
PGND  
IN1  
V
VOLTAGE  
CONTROL, V  
DAC  
SNS+  
SNS-  
,
REF  
VID0  
VID1  
BIAS, ETC.  
AGND  
Figure 1. Block Diagram  
For each of the different output modes, the following  
parameters are programmable:  
Detailed Description  
The MAX8952 high-efficiency, 3.25MHz step-down  
switching regulator delivers up to 2.5A of output cur-  
rent. The device operates from a 2.5V to 5.5V input  
voltage range, and the output voltage is I2C program-  
mable from 0.77V to 1.40V in 10mV increments. Fully  
differential remote sense ensures precise DC regula-  
tion at the load. Total output error is less than 1.5ꢀ  
over load, line, and temperature.  
•
•
•
Output voltage from 0.77V to 1.40V in 10mV steps  
Mode of operation: Forced PWM or power save  
Enable/disable of synchronization of switching  
frequency to external clock source  
The relation between the VID0/VID1 and operation  
mode is given by Table 1.  
The VID_ inputs have internal pulldown resistors. These  
pulldown resistors can be disabled through the CON-  
TROL register after the IC is enabled, achieving lowest  
possible quiescent current. When EN is low, the CON-  
TROL register is reset to default, enabling the pulldown  
resistors.  
Dynamic Voltage Scaling  
The output voltage is dynamically adjusted by use of  
the VID0 and VID1 logic inputs, allowing selection  
between four predefined operation modes/voltage  
configurations.  
Table 1. VID0 and VID1 Configuration  
DEFAUꢂT  
SWITCHING  
MODE  
DEFAUꢂT  
OUTPUT  
VOꢂTAGE (V)  
DEFAUꢂT  
SYNCHRONIZATION  
2
VID1  
VID0  
MODE  
I C REGISTER  
0
0
1
1
0
1
0
1
MODE0  
MODE1  
MODE2  
MODE3  
Table 3  
Table 4  
Table 5  
Table 6  
POWER SAVE  
POWER SAVE  
POWER SAVE  
POWER SAVE  
OFF  
OFF  
OFF  
OFF  
1.40  
1.00  
1.40  
1.10  
______________________________________________________________________________________ 11  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
In power-save mode, the MAX8952 PWM switching fre-  
quency depends on the load current. For medium to  
high load condition, the IC operates in fixed-frequency  
PWM mode. For light load conditions, the IC operates  
in hysteretic mode. The proprietary hysteretic PWM  
control scheme ensures high efficiency, fast switching,  
and fast transient response. This control scheme is  
simple: when the output voltage is below the regula-  
tion threshold, the error comparator begins a switching  
cycle by turning on the high-side switch. This switch  
remains on until the minimum on-time expires and the  
output voltage is above the regulation threshold plus  
hysteresis or the inductor current is above the current-  
limit threshold. Once off, the high-side switch remains  
off until the minimum off-time expires and the output  
voltage falls again below the regulation threshold.  
During the off period, the low-side synchronous rectifi-  
er turns on and remains on until either the high-side  
switch turns on again or the inductor current  
approaches zero. The internal synchronous rectifier  
eliminates the need for an external Schottky diode.  
Enable  
The MAX8952 DC-DC step-down regulator is  
enabled/disabled using the EN logic input. The EN  
input is able to handle input voltages up to V , ensur-  
IN1  
ing that the EN logic input can be controlled by a wide  
variety of signals/supplies.  
The EN input has an internal pulldown resistor that  
ensures EN is discharged during off conditions. This pull-  
down resistor can be disabled through the CONTROL  
register (see Table 7) once the IC is enabled, achieving  
lowest possible quiescent current. When EN is low, the  
CONTROL register is reset to default, enabling the pull-  
down resistors on EN, VID0, and VID1. See Figures 2  
and 3 for detailed information on power-up and power-  
down sequencing and operation mode changes.  
MAX8952  
DC-DC Regulator Operating Modes  
The IC operates in one of four modes determined by  
the state of the VID_ inputs (see Table 1). At power-up,  
the IC is set to operate in power-save operation for  
MODE0 through MODE3. For each of the operation  
modes, the DC-DC step-down regulator can be set to  
operate in either power-save mode or forced-PWM  
mode. This is done by writing to the MODE_ registers  
(see Table 3 to Table 6). The mode of operation can be  
changed at any time.  
The transition between PWM and hysteretic operation is  
based on the number of consecutive zero-crossing  
cycles. When more than 16 consecutive zero-crossing  
cycles are detected, the DC-DC step-down converter  
enables the bias for hysteretic operation. Once correct-  
A
B
C
D
E
IN  
1.40V  
1.40V  
1.10V  
OUT  
EN  
VID1  
VID0  
V
DD  
A: POWER CONNECTED TO IN1 AND IN2.  
B: EN LOGIC INPUT PULLED HIGH, OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF THE I C REGISTER FOR MODE0 (SEE TABLE 1).  
C: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE I C REGISTER FOR MODE2.  
2
2
2
D: OUTPUT VOLTAGE IS SET TO CONDITION DEFINED BY THE DEFAULT VALUE OF I C REGISTER FOR MODE3.  
2
E: V PULLED HIGH, ENABLING I C INTERFACE.  
DD  
Figure 2. Power-Up Sequence  
12 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
A
B
IN_  
OUT  
EN  
V
DD  
2
A: V PULLED LOW, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1) AND THE OUTPUT VOLTAGE CHANGES TO THE DEFAULT VALUE.  
DD  
B: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS SHUTDOWN MODE.  
Figure 3a. Shutdown by Pulling V  
Low Before EN  
DD  
A
B
IN_  
OUT  
EN  
V
DD  
2
A: EN LOGIC INPUT PULLED LOW, STEP-DOWN REGULATOR ENTERS I C READY MODE, OUTPUT DISABLED.  
2
B: V PULLED LOW, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).  
DD  
Figure 3b. Shutdown by Pulling EN Low Before V  
DD  
A
IN_  
OUT  
EN  
V
DD  
2
A: IN_ DROPS BELOW UVLO, IC ENTERS SHUTDOWN MODE, I C REGISTERS RESET TO DEFAULT VALUES (SEE TABLE 1).  
Figure 3c. Shutdown Due to IN1 Undervoltage Lockout  
______________________________________________________________________________________ 13  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
ly biased and the number of consecutive zero-crossing  
cycles exceeds 24, the DC-DC step-down converter  
begins hysteretic operation.  
switching frequency depending on the load condition.  
With moderate to heavy loading, the regulator switches  
at a fixed switching frequency as it does in forced-PWM  
mode. In power-save mode, the transition from hys-  
teretic mode to fixed-frequency switching occurs at the  
load current specified in the following equation:  
During hysteretic operation, there is a silent DC offset  
due to the use of valley regulation. See Figure 4.  
When operating in power-save mode and the load cur-  
rent is increased so that the number of consecutive  
zero-crossing cycles is less than 16, the PWM mode is  
biased. Once fully biased and the number of zero-  
crossing cycles drops below 8, the DC-DC converter  
then begins PWM operation. Since there is a delay  
between the increase in load current and the  
DC-DC converter starting PWM, the converter supports  
full current on the output during hysteretic operation.  
See Figure 5 for a detailed state diagram.  
V
− V  
2×L  
V
OUT  
V × f  
IN OSC  
IN  
OUT  
I
=
×
OUT  
9
In forced-PWM mode, the regulator operates with a  
constant (3.25MHz or synchronized to external clock  
source) switching frequency regardless of output load.  
Forced-PWM mode is ideal for low-noise systems  
because switching harmonics occur at multiples of the  
constant switching frequency and are easily filtered.  
However, light-load power consumption in forced-PWM  
mode is higher than that of power-save mode.  
Power-save operation offers improved efficiency at light  
loads by changing to hysteretic mode, reducing the  
Soft-Start  
The IC includes internal soft-start circuitry that eliminates  
inrush current at startup, reducing transients on the  
input source (see the Typical Operating Charac-  
REGULATION  
THRESHOLD  
OUTPUT  
RIPPLE  
Figure 4. Output Regulation in Hysteretic Operation  
MORE THAN 16 CONSECUTIVE  
ZERO-CROSSING CYCLES  
PWM MODE  
WITH POWER-SAVE  
MODE BIASED  
PWM  
MODE  
POWER SAVE NOT READY  
LESS THAN 8 CONSECUTIVE  
ZERO-CROSSING CYCLES  
LESS THAN 8 CONSECUTIVE  
ZERO-CROSSING CYCLES  
AND PWM MODE READY  
MORE THAN 24 CONSECUTIVE  
ZERO-CROSSING CYCLES  
AND POWER-SAVE MODE READY  
MORE THAN 24 CONSECUTIVE  
ZERO-CROSSING CYCLES  
POWER-SAVE  
MODE WITH  
PWM BIASED  
POWER-SAVE  
MODE  
PWM NOT READY  
LESS THAN 16 CONSECUTIVE  
ZERO-CROSSING CYCLES  
Figure 5. Mode Change for DC-DC Step-Down Converter  
14 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
teristics). Soft-start is particularly useful for high-imped-  
ance input sources, such as Li+ and alkaline cells.  
When enabling the IC into a prebiased output, the IC  
performs a complete soft-start cycle.  
determined by the output capacitance and the external  
load. Small loads result in an output-voltage decay that  
is slower than that specified by RAMP; large loads  
result in an output-voltage decay that is no faster than  
that specified by RAMP When the RAMP_DOWN bit is  
set in power-save mode, the zero-cross comparator is  
disabled during the ramp-down condition. Active ramp-  
down functionality is inherent in forced-PWM operation.  
Synchronous Rectification  
An internal n-channel synchronous rectifier eliminates  
the need for an external Schottky diode and improves  
efficiency. The synchronous rectifier turns on during the  
second half of each switching cycle (off-time). During  
this time, the voltage across the inductor is reversed,  
and the inductor current ramps down. In PWM mode,  
the synchronous rectifier turns off at the end of the  
switching cycle. In power-save mode, the synchronous  
rectifier turns off when the inductor current falls below  
50mA (typ) or at the end of the switching cycle,  
whichever occurs first.  
Calculate the maximum and minimum values for the  
ramp rate as follows:  
V
1
OUT _LSB  
t
=
×
RAMP _MIN  
RAMP _ CODE  
t
2
CLK _MAX  
V
1
OUT _LSB  
t
=
×
RAMP _MAX  
RAMP _ CODE  
t
2
CLK _MIN  
where:  
Ramp-Rate Control  
The MAX8952 output voltage has an actively controlled  
variable ramp rate, set with the I2C interface (see  
Figures 6, 7, and 8). The value set in the RAMP register  
controls the output voltage ramp rate. The  
RAMP_DOWN bit controls the active ramp-down  
behavior in power-save mode. When the regulator is set  
for power-save mode and the RAMP_DOWN bit is  
cleared, the ramp-down is not actively controlled, and  
the regulator output voltage ramps down at the rate  
V
=10mV  
OUT _LSB  
1
t
t
=
CLK _MAX  
f
SW _MIN  
1
=
CLK _MIN  
f
SW _MAX  
f
f
= 3.25MHz 10ꢀ for PWM operation  
SW  
= 3.25MHz 25ꢀ for hysteretic operation  
SW  
f
OUTPUT  
VOLTAGE  
SYNC  
n
f
=
SW  
DELTA V = 10mV  
f
= frequency of external clock  
SYNC  
V
'
OUT  
n = 4 for 13MHz, 6 for 19.2MHz, and 8 for 26MHz  
RAMP_CODE = value of the RAMP[2:0] register (see  
Table 9)  
10mV/RAMP RATE  
TIME  
V
OUT  
Thermal-Overload Protection  
Thermal-overload protection limits total power dissipa-  
tion in the IC. When internal thermal sensors detect a  
Figure 6. Ramp-Up Function  
FINAL  
OUTPUT  
VOLTAGE  
OUTPUT  
VOLTAGE  
V
OUT  
DELTA  
V = 10mV  
10mV/RAMP  
RATE  
V
'
OUT  
MODE CHANGE  
TO HIGHER VOUT  
MODE CHANGE  
TO LOWER VOUT  
TIME  
Figure 7. Ramp-Down Function  
Figure 8. Mode Change Before Final Value is Reached  
______________________________________________________________________________________ 15  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
SDA  
MAX8952  
SCL  
DATA LINE STABLE DATA VALID  
CHANGE OF DATA ALLOWED  
2
Figure 9. I C Bit Transfer  
die temperature in excess of +160°C (typ), the  
DC-DC step-down regulator is shut down, allowing the  
IC to cool. The DC-DC step-down regulator is turned on  
again after the junction cools by 20°C (typ), resulting in  
a pulsed output during continuous thermal-overload  
conditions.  
bit. The IC supports data transfer rates with SCL fre-  
quencies up to 400kHz.  
START and STOP Conditions  
When the serial interface is inactive, SDA and SCL idle  
high. A master device initiates communication by  
issuing a START condition. A START condition is a  
high-to-low transition on SDA with SCL high. A STOP  
condition is a low-to-high transition on SDA, while SCL  
is high (Figure 10).  
During thermal overload, the I2C interface remains  
active and all register values are maintained.  
2
I C Interface  
An I2C-compatible, 2-wire serial interface controls the  
step-down converter output voltage, ramp rate, operat-  
ing mode, and synchronization. The serial bus consists  
of a bidirectional serial-data line (SDA) and a serial-  
clock input (SCL). The master initiates data transfer on  
the bus and generates SCL to permit data transfer.  
A START condition from the master signals the begin-  
ning of a transmission to the IC. The master terminates  
transmission by issuing a not acknowledge followed by  
I2C is an open-drain bus. SDA and SCL require pullup  
resistors (500Ω or greater). Optional (24Ω) in series  
with SDA and SCL protect the device inputs from high-  
voltage spikes on the bus lines. Series resistors also  
minimize crosstalk and undershoot on bus signals.  
SDA  
SCL  
Bit Transfer  
One data bit is transferred during each SCL clock  
cycle. The data on SDA must remain stable during the  
high period of the SCL clock pulse (see Figure 9).  
Changes in SDA while SCL is high are control signals  
(see the START and STOP Conditions section for more  
information).  
START  
STOP  
CONDITION  
CONDITION  
Each transmit sequence is framed by a START (S) con-  
dition and a STOP (P) condition. Each data packet is 9  
bits long; 8 bits of data followed by the acknowledge  
2
Figure 10. I C START and STOP Conditions  
16 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
SDA  
SCL  
MASTER  
TRANSMITTER/RECEIVER  
SLAVE  
TRANSMITTER/RECEIVER  
SLAVE RECEIVER  
2
Figure 11. I CMaster/Slave Configuration  
a STOP condition (see the Acknowledge section for  
more information). The STOP condition frees the bus.  
To issue a series of commands to the slave, the master  
can issue REPEATED START (Sr) commands instead of  
a STOP command to maintain control of the bus. In  
general, a REPEATED START command is functionally  
equivalent to a regular START command.  
SDA OUTPUT  
FROM TRANSMITTER  
D0  
D7  
D6  
NOT ACKNOWLEDGE  
SDA OUTPUT  
FROM RECEIVER  
When a STOP condition or incorrect address is detect-  
ed, the IC internally disconnects SCL from the serial  
interface until the next START condition, minimizing dig-  
ital noise and feedthrough.  
ACKNOWLEDGE  
8
SCL FROM  
MASTER  
1
2
9
System Configuration  
A device on the I2C bus that generates a message is  
called a transmitter and a device that receives the mes-  
sage is a receiver. The device that controls the mes-  
sage is the master and the devices that are controlled  
by the master are called slaves. See Figure 11.  
CLOCK PULSE FOR  
ACKNOWLEDGEMENT  
START CONDITION  
2
Figure 12. I C Acknowledge  
acknowledge clock pulse (setup and hold times must  
also be met). A master receiver must signal an end of  
data to the transmitter by not generating an acknowl-  
edge on the last byte that has been clocked out of the  
slave. In this case, the transmitter must leave SDA high  
to enable the master to generate a STOP condition.  
Acknowledge  
The number of data bytes between the START and  
STOP conditions for the transmitter and receiver are  
unlimited. Each 8-bit byte is followed by an acknowl-  
edge bit. The acknowledge bit is a high-level signal put  
on SDA by the transmitter during which time the master  
generates an extra acknowledge-related clock pulse. A  
slave receiver that is addressed must generate an  
acknowledge after each byte it receives. Also, a master  
receiver must generate an acknowledge after each  
byte it receives that has been clocked out of the slave  
transmitter. See Figure 12.  
Register Reset  
The I2C resisters reset back to their default values when  
the voltage at either IN1 or V  
drops below the  
DD  
corresponding UVLO threshold (see the Electrical  
Characteristics table).  
Update of Output Operation Mode  
If updating the output voltage or Operation Mode regis-  
ter for the mode that the IC is currently operating in, the  
The device that acknowledges must pull down the  
DATA line during the acknowledge clock pulse, so that  
the DATA line is stable low during the high period of the  
______________________________________________________________________________________ 17  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
A
B
C
D
E
OUT  
S
SLAVE ID  
ASr  
REG PTR  
ASr  
DATA  
A
P
SDA  
VID0  
VID1  
MAX8952  
V
2
DD  
A: I C START COMMAND.  
2
B: I C SLAVE ADDRESS OF MAX8952 SEND OUT.  
2
C: MAX8952 I C REGISTER POINTER SEND OUT.  
D: MAX8952 DATA SEND OUT.  
E: MAX8952 ISSUES ACKNOWLEDGE AND CHANGES THE OUTPUT VOLTAGE ACCORDING TO NEW I C SETTINGS.  
2
Figure 13. Update Output Operation  
output voltage/operation mode is updated at the same  
time the IC sends the acknowledge for the I2C data  
byte (see Figure 13).  
7) The slave acknowledges the data byte.  
8) The slave updates with the new data.  
9) The master sends a STOP condition.  
Slaꢁe Address  
A bus master initiates communication with a slave  
device (MAX8952) by issuing a START condition fol-  
lowed by the slave address. The slave address byte  
consists of 7 address bits (1100 000x) and a read/write  
bit (R/W). After receiving the proper address, the IC  
issues an acknowledge by pulling SDA low during the  
ninth clock cycle.  
In addition to the write-byte protocol, the IC can write to  
multiple registers as shown in Figure 14b. This protocol  
allows the I2C master device to address the slave only  
once and then send data to a sequential block of regis-  
ters starting at the specified register pointer.  
Use the following procedure to write to a sequential  
block of registers:  
1) The master sends a start command.  
Other slave addresses can be assigned. Contact the  
factory for details.  
2) The master sends the 7-bit slave address followed  
by a write bit.  
Write Operations  
The IC recognizes the write byte protocol as defined in  
the SMBus™ specification and shown in Figures 14a and  
14b. The write byte protocol allows the I2C master device  
to send 1 byte of data to the slave device. The write byte  
protocol requires a register pointer address for the sub-  
sequent write. The IC acknowledges any register pointer  
even though only a subset of those registers actually  
exists in the device. The write byte protocol is as follows:  
3) The addressed slave asserts an acknowledge by  
pulling SDA low.  
4) The master sends the 8-bit register pointer of the  
first register to write.  
5) The slave acknowledges the register pointer.  
6) The master sends a data byte.  
7) The slave acknowledges the data byte.  
8) The slave updates with the new data.  
1) The master sends a start command.  
9) Steps 6 to 8 are repeated for as many registers in  
the block, with the register pointer automatically  
incremented each time.  
2) The master sends the 7-bit slave address followed  
by a write bit.  
3) The addressed slave asserts an acknowledge by  
pulling SDA low.  
10) The master sends a STOP condition.  
4) The master sends an 8-bit register pointer.  
5) The slave acknowledges the register pointer.  
6) The master sends a data byte.  
Read Operations  
The method for reading a single register (byte) is  
shown in Figure 15a. To read a single register:  
SMBus is a trademark of Intel Corp.  
18 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
LEGEND  
MASTER TO  
SLAVE  
SLAVE TO  
MASTER  
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL  
1
7
1
0
1
8
1
8
1
1
NUMBER OF BITS  
S
SLAVE ADDRESS  
A
REGISTER POINTER  
A
DATA  
A
P
R/W  
b) WRITING TO MULTIPLE REGISTERS  
NUMBER OF BITS  
1
7
1
1
8
1
8
1
8
1
...  
S
SLAVE ADDRESS  
0
A
REGISTER POINTER X  
A
DATA X  
A
DATA X+1  
A
R/W  
8
1
8
1
NUMBER OF BITS  
...  
DATA X+n-1  
A
DATA X+n  
A
P
Figures 14a and 14b. Writing to the IC  
1) The master sends a start command.  
3) The addressed slave asserts an acknowledge by  
pulling SDA low.  
2) The master sends the 7-bit slave address followed  
by a write bit.  
4) The master sends an 8-bit register pointer of the  
first register in the block.  
3) The addressed slave asserts an acknowledge by  
pulling SDA low.  
5) The slave acknowledges the register pointer.  
6) The master sends a REPEATED START condition.  
4) The master sends an 8-bit register pointer.  
5) The slave acknowledges the register pointer.  
6) The master sends a REPEATED START condition.  
7) The master sends the 7-bit slave address followed  
by a read bit.  
8) The slave asserts an acknowledge by pulling SDA low.  
7) The master sends the 7-bit slave address followed  
by a read bit.  
9) The slave sends the 8-bit data (contents of the reg-  
ister).  
8) The slave asserts an acknowledge by pulling SDA low.  
10) The master asserts an acknowledge by pulling SDA  
low when there is more data to read, or a not  
acknowledge by keeping SDA high when all data  
has been read.  
9) The slave sends the 8-bit data (contents of the  
register).  
10) The master asserts a not acknowledge by keeping  
SDA high.  
11) Steps 9 and 10 are repeated for as many registers  
in the block, with the register pointer automatically  
incremented each time.  
11) The master sends a STOP condition.  
In addition, the IC can read a block of multiple sequential  
registers as shown in Figure 15b. Use the following pro-  
cedure to read a sequential block of registers:  
12) The master sends a STOP condition.  
1) The master sends a start command.  
2) The master sends the 7-bit slave address followed  
by a write bit.  
______________________________________________________________________________________ 19  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
LEGEND  
MASTER TO  
SLAVE  
SLAVE TO  
MASTER  
a) READING A SINGLE REGISTER  
1
7
1
0
1
8
1
1
7
1
1
8
1
1
NUMBER OF BITS  
MAX8952  
S
SLAVE ADDRESS  
A
REGISTER POINTER  
A
Sr  
SLAVE ADDRESS  
1
A
DATA  
A
P
R/W  
R/W  
b) READING MULTIPLE REGISTERS  
NUMBER OF BITS  
1
7
1
1
8
1
1
7
1
8
1
1
1
...  
S
SLAVE ADDRESS  
0
A
REGISTER POINTER X  
A
Sr  
SLAVE ADDRESS  
A
DATA X  
A
R/W  
...  
R/W  
1
8
1
8
8
1
1
NUMBER OF BITS  
...  
DATA X+1  
A
DATA X+n-1  
A
DATA X+n  
A
P
Figures 15a and 15b. Reading from the IC  
SDA  
t
BUF  
t
SU_STA  
t
SU_DAT  
t
HD_STA  
t
LOW  
t
SU_STO  
t
HD_DAT  
t
SCL  
HIGH  
t
HD_STA  
t
R
t
F
START CONDITION  
REPEATED START CONDITION  
STOP  
CONDITION  
START  
CONDITION  
2
Figure 16. I C Timing Diagram  
20 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
2
Table 2. I C Register Map  
POINTER  
REGISTER  
POR  
BIT7  
BIT6  
BIT5  
BIT4  
BIT3  
BIT2  
BIT1  
BIT0  
OPER  
MODE  
SYNC  
MODE  
0x00  
MODE0  
0x3F  
VOUT MODE0[5:0]  
VOUT MODE1[5:0]  
VOUT MODE2[5:0]  
VOUT MODE3[5:0]  
OPER  
MODE  
SYNC  
MODE  
0x01  
0x02  
0x03  
MODE1  
MODE2  
MODE3  
0x17  
0x3F  
0x21  
OPER  
MODE  
SYNC  
MODE  
OPER  
MODE  
SYNC  
MODE  
0x04  
0x05  
0x06  
0x08  
0x09  
CONTROL  
SYNC  
0xE0  
0x00  
0x01  
0x20  
0x1A  
EN_PD  
VID0_PD VID1_PD  
—
—
—
—
—
—
—
SYNC[1:0]  
RAMP[2:0]  
—
—
—
—
—
—
RAMP  
FORCE_HYS FORCE_OSC  
RAMP_DOWN  
CHIP_ID1  
CHIP_ID2  
DIE TYPE[7:4]  
DASH[3:0]  
DIE TYPE[3:0]  
MASK REV[3:0]  
2
Table 3. I C Register: MODE0  
This register contains output voltage and operation mode control for MODE0, VID0 = GND, VID1 = GND.  
REGISTER NAME  
MODE0  
0x00h  
Address  
Reset Value  
Type  
0x3Fh  
Read/write  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Conꢁerter Operation Mode for MODE0  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
FPWM_EN0  
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
B6  
SYNC_MODE0  
0
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE0  
000000 = 0.77V  
000001 = 0.78V  
110011 = 1.28V  
110100 = 1.29V  
B5  
B4  
B3  
111111  
(1.4V)  
OUT_ MODE0 [5:0]  
B2  
110101 = 1.30V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
______________________________________________________________________________________ 21  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
2
Table 4. I C Register: MODE1  
This register contains output voltage and operation mode control for MODE1, VID1 = GND, VID0 = V  
.
DD  
REGISTER NAME  
MODE1  
0x01h  
Address  
Reset Value  
Type  
0x17h  
Read/write  
MAX8952  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Conꢁerter Operation Mode for MODE1  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
FPWM_EN1  
0
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
B6  
SYNC_MODE1  
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE1  
000000 = 0.77V  
000001 = 0.78V  
010110 = 0.99V  
010111 = 1.00V  
B5  
B4  
B3  
010111  
(1.00V)  
OUT_MODE1[5:0]  
B2  
011000 = 1.01V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
22 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
2
Table 5. I C Register: MODE2  
This register contains output voltage and operation mode control for MODE2, VID1 = V , VID0 = GND.  
DD  
REGISTER NAME  
MODE2  
0x02h  
Address  
Reset Value  
Type  
0x3Fh  
Read/write  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Conꢁerter Operation Mode for MODE2  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
FPWM_EN2  
0
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
B6  
SYNC_MODE2  
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE2  
000000 = 0.77V  
000001 = 0.78V  
110011 = 1.28V  
110100 = 1.29V  
B5  
B4  
B3  
111111  
(1.4V)  
OUT_MODE2[5:0]  
B2  
110101 = 1.30V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
______________________________________________________________________________________ 23  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
2
Table 6. I C Register: MODE3  
This register contains output voltage and operation mode control for MODE3, VID1 = V , VID0 = V  
.
DD  
DD  
REGISTER NAME  
MODE3  
0x03h  
Address  
Reset Value  
Type  
0x21h  
Read/write  
MAX8952  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
DC-DC Step-Down Conꢁerter Operation Mode for MODE3  
0 = DC-DC converter automatically changes between hysteretic mode for  
light load conditions and PWM mode for medium to heavy load conditions.  
1 = DC-DC converter operates in forced-PWM mode.  
B7 (MSB)  
FPWM_EN3  
0
0
Disable/Enable Synchronization to External Clock  
0 = DC-DC converter ignores the external SYNC input regardless of  
operation mode.  
B6  
SYNC_MODE3  
1 = DC-DC converter synchronizes to external SYNC input when available.  
Output Voltage Selection for MODE3  
000000 = 0.77V  
000001 = 0.78V  
100000 = 1.09V  
100001 = 1.10V  
B5  
B4  
B3  
OUT_MODE3[5:0]  
100001  
B2  
100010 = 1.11V  
111110 = 1.39V  
B1  
B0 (LSB)  
111111 = 1.40V  
24 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
2
Table 7. I C Register: CONTROꢂ  
This register enables or disables pulldown resistors.  
REGISTER NAME  
CONTROꢂ  
0x04h  
Address  
Reset Value  
Type  
0xE0h  
Read/write  
Special Features  
Reset upon V , IN_ UVLO or EN pulled low  
DD  
DEFAUꢂT  
VAꢂUE  
BIT  
B7 (MSB)  
B6  
NAME  
EN_PD  
DESCRIPTION  
0 = Pulldown on EN input is disabled.  
1
1 = Pulldown on EN input is enabled.  
0 = Pulldown on VID0 input is disabled.  
1 = Pulldown on VID0 input is enabled.  
VID0_PD  
VID1_PD  
1
1
0 = Pulldown on VID1 input is disabled.  
1 = Pulldown on VID1 input is enabled.  
B5  
B4  
B3  
—
—
—
—
—
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
0
0
0
0
0
B2  
B1  
B0 (LSB)  
______________________________________________________________________________________ 25  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
2
Table 8. I C Register: SYNC  
This register specifies the clock frequency of external clock source.  
REGISTER NAME  
SYNC  
0x05h  
0x00h  
Read  
Address  
Reset Value  
Type  
MAX8952  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
Sets Clock Frequency of External Clock Present on SYNC Input  
B7 (MSB)  
00 = 26MHz  
01 = 13MHz  
10 = 19.2MHz  
11 = 19.2MHz  
SYNC[1:0]  
00  
B6  
B5  
B4  
—
—
—
—
—
—
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
0
0
0
0
0
0
B3  
B2  
B1  
B0 (LSB)  
26 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
2
Table 9. I C Register: RAMP  
This register controls of ramp-up/down function.  
REGISTER NAME  
RAMP  
0x06h  
0x01h  
Read  
Address  
Reset Value  
Type  
Special Features  
Reset upon V  
or IN_ UVLO  
DD  
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
Control the RAMP Timing  
000 = 32mV/µs  
001 = 16mV/µs  
010 = 8mV/µs  
B7 (MSB)  
B6  
B5  
RAMP[2:0]  
011 = 4mV/µs  
100 = 2mV/µs  
101 = 1mV/µs  
110 = 0.5mV/µs  
111 = 0.25mV/µs  
000  
Only Valid When Conꢁerter is Operating with FPWM_EN_ = 0  
0 = Automatically change between power-save mode and PWM mode,  
depending on load current.  
1 = Converter always operates in power-save mode regardless of load  
current as long as FPWM_EN_ = 0. If FPWM_EN_ = 1, this setting is  
ignored.  
B4  
FORCE_HYS  
FORCE_OSC  
0
0
Force Oscillator While Running in Hysteretic Mode  
0 = Internal oscillator is disabled in power save when operating in  
hysteretic mode.  
B3  
1 = Internal oscillator is enabled in power save even when operating in  
hysteretic mode.  
B2  
B1  
—
RAMP_DOWN  
—
Reserved for future use.  
0
0
0
Actiꢁe Ramp-Down Control for Power-Saꢁe Mode  
0 = Active ramp disabled for power-save mode.  
1 = During ramp-down, the error crossing detector is disabled allowing  
negative current to flow thought the nMOS device.  
B0 (LSB)  
Reserve for future use.  
______________________________________________________________________________________ 27  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
2
Table 10. I C Register: CHIP_ID1  
This register contains the die type number (20).  
REGISTER NAME  
CHIP_ID1  
0x08h  
0x20h  
Read  
Address  
Reset Value  
Type  
MAX8952  
Special Features  
—
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
B7 (MSB)  
B6  
DIE_TYPE[7:4]  
BCD character (2)  
BCD character (0)  
0010  
0000  
B5  
B4  
B3  
B2  
DIE_TYPE[3:0]  
B1  
B0 (LSB)  
2
Table 11. I C Register: CHIP_ID2  
This register contains the die type dash number and mask revision level.  
REGISTER NAME  
CHIP_ID2  
0x09h  
0x1Ah  
Read  
Address  
Reset Value  
Type  
Special Features  
—
DEFAUꢂT  
VAꢂUE  
BIT  
NAME  
DESCRIPTION  
B7 (MSB)  
B6  
DASH  
BCD character 1 (1)  
BCD character A (A)  
0001  
1010  
B5  
B4  
B3  
B2  
MASK_REV  
B1  
B0 (LSB)  
28 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
Given L  
, the peak-to-peak inductor ripple current  
OUT(MAX)  
IDEAL  
is 0.25 x I  
Applications Information  
. The peak inductor current is 1.125  
Inductor Selection  
x I  
. Make sure that the saturation current of  
OUT(MAX)  
Calculate the inductor value (L  
) using the follow-  
the inductor exceeds the peak inductor current, and  
the rated maximum DC inductor current exceeds the  
IDEAL  
ing formula:  
maximum output current (I  
ues smaller than L  
). Inductance val-  
OUT(MAX)  
can be used to reduce induc-  
4 × V × D × 1-D  
(
)
IN  
OUT MAX  
IDEAL  
L
=
IDEAL  
I
× f  
OSC  
tor size; however, if much smaller values are used,  
peak inductor current rises and a larger output capaci-  
tance may be required to suppress output ripple.  
(
)
This sets the peak-to-peak inductor current ripple to 1/4  
the maximum output current. The oscillator frequency,  
Larger inductance values than L  
can be used to  
IDEAL  
f
, is 3.25MHz, and the duty cycle, D, is:  
OSC  
obtain higher output current, but typically require a  
physically larger inductor size. See Table 12 for rec-  
ommended inductors.  
V
OUT  
D =  
V
IN  
Table 12. Recommended Inductors  
INDUCTANCE  
(µH)  
DC RESISTANCE  
CURRENT RATING  
(mA)  
DIMENSIONS  
ꢂ x W x H (mm)  
MANUFACTURER  
SERIES  
(Ω typ)  
0.47  
1.0  
0.025  
0.033  
3800  
2700  
DE2815C  
3.2 x 3.0 x 1.5  
Toko  
TDK  
DB3015C  
VLS252010ET  
VLS4012ET  
LPS5015  
1.0  
0.47  
1.0  
0.036  
0.038  
0.050  
0.050  
0.038  
0.055  
0.030  
2700  
2800  
2800  
3900  
3400  
3800  
2600  
3.2 x 3.2 x 1.5  
2.5 x 2.0 x 1.0  
4.0 x 4.0 x 1.2  
5.0 x 5.0 x 1.5  
5.0 x 5.0 x 1.0  
4.4 x 4.4 x 1.4  
4.8 x 4.8 x 1.8  
1.0  
Coilcraft  
Wurth  
LPS5010  
0.47  
0.7  
LPS4414  
744042001  
1.0  
______________________________________________________________________________________ 29  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
Input Capacitor Selection  
The input capacitor in a step-down DC-DC regulator  
reduces current peaks drawn from the battery or other  
input power source and reduces switching noise in the  
controller. 10µF ceramic capacitors in parallel with a  
0.1µF ceramic capacitor are recommended for most  
applications. The impedance of the input capacitor at the  
switching frequency should be less than that of the input  
source so that high-frequency switching currents do not  
pass through the input source. The input capacitor must  
meet the input ripple-current requirement imposed by  
the step-down regulator. Ceramic capacitors are pre-  
ferred due to their resilience to power-up surge currents.  
Choose the input capacitor so that the temperature rise  
due to input ripple current does not exceed approxi-  
mately +10°C. For a step-down DC-DC regulator, the  
maximum input ripple current is 1/2 of the output current.  
This maximum input ripple current occurs when the step-  
Power Dissipation  
The IC has a thermal-shutdown feature that protects the  
IC from damage when the die temperature exceeds  
+160°C. See the Thermal-Overload Protection section  
for more information. To prevent thermal overload and  
allow the maximum load current on each regulator, it is  
important to ensure that the heat generated by the IC  
can be dissipated into the PCB.  
When properly mounted on a multilayer PCB, the junc-  
MAX8952  
tion-to-ambient thermal resistance (θ ) is typically  
JA  
49°C/W.  
PCB Layout  
Due to fast switching waveforms and high current  
paths, careful PCB layout is required to achieve optimal  
performance. Minimize trace lengths between the IC  
and the inductor, the input capacitor, and the output  
capacitor; keep these traces short, direct, and wide.  
down regulator operates at 50ꢀ duty factor (V = 2 x  
IN  
The ground connections of C and C  
should be as  
IN  
OUT  
V
). Refer to the MAX8952 Evaluation Kit data sheet  
close together as possible and connected to PGND.  
Connect AGND and PGND directly to the ground plane.  
The MAX8952 Evaluation Kit illustrates an example PCB  
layout and routing scheme.  
OUT  
for specific input capacitor recommendations.  
Output Capacitor Selection  
The step-down DC-DC regulator output capacitor keeps  
output ripple small and ensures control-loop  
stability. A 10µF ceramic capacitor in parallel with a  
0.1µF ceramic capacitor is recommended for most appli-  
cations. The output capacitor must also have low imped-  
ance at the switching frequency. Ceramic, polymer, and  
tantalum capacitors are suitable, with ceramic exhibiting  
the lowest ESR and lowest high-frequency impedance.  
Chip Information  
PROCESS: BiCMOS  
Output ripple due to capacitance (neglecting ESR) is  
approximately:  
I
L PEAK  
(
)
V
=
RIPPLE  
Package Information  
2π × f  
× C  
OSC  
OUT  
For the latest package outline information and land patterns, go  
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in  
the package code indicates RoHS status only. Package draw-  
ings may show a different suffix character, but the drawing per-  
tains to the package regardless of RoHS status.  
Additional ripple due to capacitor ESR is:  
ESR = I ×ESR  
V
(
)
RIPPLE  
L PEAK  
(
)
PACKAGE TYPE  
PACKAGE CODE DOCUMENT NO.  
W162B2+1  
21-0200  
Refer to the MAX8952 Evaluation Kit for specific output  
capacitor recommendations.  
16 WLP 0.5mm Pitch  
30 ______________________________________________________________________________________  
2.5A Step-Down Regulator with Differential  
Remote Sense in 2mm x 2mm WLP  
MAX8952  
Revision History  
REVISION  
NUMBER  
REVISION  
DATE  
PAGES  
CHANGED  
DESCRIPTION  
0
6/10  
Initial release  
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31  
© 2010 Maxim Integrated Products  
Maxim is a registered trademark of Maxim Integrated Products, Inc.  

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