MC2007-EVM [ETC]

Passive Optical Networks;
MC2007-EVM
型号: MC2007-EVM
厂家: ETC    ETC
描述:

Passive Optical Networks

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MC2007-3  
3.3 V PIN Pre-Amplifier with AGC for Applications to  
200 Mbps  
The MC2007-3 is a low-noise, transimpedance amplifier with AGC, manufactured in an advanced, low-cost, sub-  
micron CMOS process. Its wide dynamic range, differential output and high PIN bias make it well suited to high-  
performance telecommunications, especially OC-3/STM-1. However, due to its low cost, the MC2007-3 also meets  
the needs of datacom applications.  
The MC2007-3 is available in die form. For optimum system performance die should be mounted in close proximity  
with the photodetector.  
The MC2007-3 is designed to be used with the MC2045 or M02095 post amplifier IC. When combined with a  
photodiode, the chip set forms a high performance, low cost 3.3V receiver.  
Applications  
Features  
• Optical Receivers (Up to 200 Mbps Operation)  
• SDH / SONET / ATM  
• Fast Ethernet  
• Low-cost, CMOS process  
• Receiver sensitivity typically -39 dBm at 155 Mbps, when integrated  
into a module with suitable photodiode and post-amplifier  
• 140 MHz bandwidth allows wide range of operation: 100, 125, 155,  
and 200 Mbps  
• Typical differential gain of 62 kat low signal levels  
• AGC gives continuous operation to +3 dBm  
• 65 mW power consumption at +3.3 V supply  
• > 35 dB Power-supply noise rejection  
• Available as die only  
• ESCON  
• Passive Optical Networks (PONs)  
• SFP/SFF Transceivers  
• BiDi Transceivers  
Functional Block Diagram  
Series Pass  
Regulator  
PINK  
Bandgap  
1.23 V  
RREF  
Reference  
Generator  
Set Max. Gain  
AGC Control  
R
DOUT  
+1  
TZA  
PINA  
+1  
DOUT  
+1  
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Ordering Information  
Part Number  
Package  
Operating Temperature  
MC2007-XX  
MC2007-XX  
MC2007-EVM  
Waffle pack  
–40 °C to 85 °C  
–40 °C to 85 °C  
–40 °C to 85 °C  
Expanded whole wafer on a ring  
MC2007 evaluation board with MC2045 post amp  
Revision History  
Revision  
Level  
Date  
Description  
E
Preliminary  
Preliminary  
November 2007 Correct PinK absolute maximum information. Update format.  
D
June 2006  
Updated format.  
Updated Absolute Maximum Ratings.  
Added TIA Use with Externally Biased Detectors section.  
C
B
A
Preliminary  
Preliminary  
Preliminary  
June 2004  
June 2003  
Added Note 7 to Table 2-4.  
Added externally biases diode maximum to Absolute Maximum Ratings table.  
December 2000 Initial Release.  
Typical Eye Diagram  
Pad Configuration  
Eye diagram for 155 Mbps at 3 µA input signal  
PP  
Die size 1010 x 960 µm  
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1.0 Product Specification  
1.1  
Absolute Maximum Ratings  
These are the absolute maximum ratings at or beyond which the IC can be expected to fail or be damaged.  
Reliable operation at these extremes for any length of time is not implied.  
Table 1-1.  
Symbol  
Absolute Maximum Ratings  
Parameter  
Rating  
Units  
V
Power supply (V - GND)  
-0.4 to +4.5  
+150  
V
°C  
CC  
CC  
T
Die Junction temperature  
Storage temperature  
J
T
-65 to +150  
°C  
STG  
(1, 2, 3)  
I
PinA maximum input current  
Input voltage at PINA  
4.5  
mApp  
V
PINA  
(2)  
V
-0.4 to +3.6  
10  
PINA  
PINK  
I
Maximum average current sourced out of PINK  
Maximum input voltage at PINK and MON  
mA  
V
V
-0.4 to V +0.4  
PINK  
Dout  
CC  
(4)  
I
Maximum average current sourced out of Dout and DoutB  
Maximum input voltage at Dout and DoutB  
10.0  
mA  
V
(4)  
V
0.0 to V +0.4  
Dout  
CC  
NOTES:  
1. Equivalent to 2.8 mA average current.  
2. Do not exceed either the I or V  
rating. PINA damage will result in performance degradation which is difficult to detect.  
PINA  
PINA  
3. Part must be powered up for PinA to accept this current. With the part unpowered, no current should be sourced into PinA.  
4. Do not exceed either the I or V rating. Output device damage could occur.  
Dout  
Dout  
1.2  
Recommended Operating Conditions  
Table 1-2.  
Recommended Operating Conditions  
Symbol  
Parameter  
Rating  
Units  
V
C
Power supply (V - GND)  
3.3 10ꢀ  
1.0  
V
CC  
PD  
CC  
Max. Photodiode capacitance (V = 1.8 V), for 155 Mbps data rate  
pF  
°C  
PD  
T
Operating ambient temperature  
-40 to +85  
A
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Product Specification  
1.3  
DC Characteristics  
Table 1-3.  
DC Characteristics  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Units  
V
PIN PD bias voltage (PINK - PINA)  
Common mode output voltage  
Supply current  
1.5  
-
1.7  
2.0  
-
V
V
PD  
CM  
CC  
V
V /2  
CC  
I
12  
0.9  
22  
1.04  
32  
1.1  
mA  
V
V
PINA bias voltage with respect to GND  
A
1.4  
AC Characteristics  
Table 1-4.  
Symbol  
AC Characteristics  
Parameter  
Min.  
25  
Typ.  
Max.  
Units  
R
Output impedance (single ended)  
40  
1.5  
-39  
+3  
100  
2.6  
-
pA/(rt(Hz))  
dBm  
OUT  
(1), (2), (3)  
I
Input noise current  
1.0  
-
NOISE  
(1), (2)  
Pin(mean), Min.  
Pin(mean), Max.  
G
Optical sensitivity  
Optical saturation  
(2)  
+1  
-
dBm  
(3), (4)  
Small signal transimpedance  
Single ended:  
kΩ  
26  
52  
31  
62  
35  
70  
Differential:  
(3)  
V
Differential output voltage  
-
110  
-
-
800  
-
mV  
MHz  
ns  
D
(7)  
BW  
T, T  
Bandwidth to -3 dB point (electrical)  
140  
Data out rise/fall times (20ꢀ - 80ꢀ points)  
Pulse width distortion  
-
-
-
-
-
-
-
2
r
f
T
-
10  
10  
100  
12  
-
PWD  
PULSE  
OS  
Pulse overshoot  
-
T
AGC setting time  
-
µs  
AGC  
OS  
AGC overshoot  
-
AGC  
PSRR  
Power supply rejection ratio (<4 MHz)  
35  
30  
dB  
(5)  
Z
Input impedance  
3000  
IN  
NOTES:  
1. Measured with input capacitance, C = 0.7 pF  
IN  
-10  
2. Assuming photodiode response of 0.9 A/W, extinction ratio of 10 dB and BER of 10  
3. The 2007 is designed to drive a load >500 Ω. Measurements are taken into high Z.  
4. Measured at 100 kHz with a test current of 0.5 µA mean (1 µA ).  
PP  
5. Data input amplitude dependant Z is inversely proportional to input photo diode current and measured between 20 kHz and 100 MHz.  
IN  
6. All die are tested and guaranteed at 25°C 5°C. Die are characterized and designed to operate from -40 to +85°C. Optical sensitivity is  
characterized in an optical assembly as an example of what can be achieved, and is not guaranteed. Consult factory for configuration details.  
7. Measured electrically using a 50 source with a 480 resistor and 100 nF capacitor in series with the input to PINA pad and a 0.7 pF capacitor  
to ground with mean input current = 0.5 µA.  
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Product Specification  
Figure 1-1. Typical Performance  
Diff Gain vs Input  
Diff Output vs Input  
70.0  
400  
350  
300  
250  
200  
150  
100  
50  
60.0  
25°C  
50.0  
40.0  
30.0  
20.0  
10.0  
0.0  
25°C  
55°C  
85°C  
55°C  
85°C  
0
-40  
-35  
-30  
-25  
-20  
-15  
-10  
-5  
0
-40  
-35  
-30  
-25  
-20  
-15  
-10  
-5  
0
Input (dBm)  
Input (dBm)  
I
CC vs VCC  
Diff Output vs Frequency  
400  
40.0  
350  
300  
250  
200  
150  
100  
50  
35.0  
30.0  
25.0  
20.0  
15.0  
10.0  
-5dBm  
-10dBm  
-15dBm  
-20dBm  
-25dBm  
-30dBm  
0
3.0  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
3.9  
4.0  
1
10  
100  
1000  
Frequency (MHz)  
Vcc (V)  
Typical -3dB Electrical Bandwidth Vs. Photodiode Capacitance  
130  
120  
110  
100  
90  
80  
70  
60  
50  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
1.8  
2.0  
Photodiode Capacitance (pF)  
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Product Specification  
Figure 1-2. Eye Diagrams  
3 µApp Input  
10 mV/Div.  
1 ns/Div.  
1 mApp Input  
50 mV/Div.  
1 ns/Div.  
NOTE:  
These eye diagrams illustrate how the AGC action changes the bandwidth from the optimum value for best sensitivity at low gain levels to a higher  
value, giving faster rise/fall times at high signal levels, as well as reducing the dynamic range of the output level.  
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2.0 Pin Description  
2.1  
Pin Description  
Table 2-1.  
Pin Description  
Die Pad No  
Name  
Function  
1, 8  
2
GND  
Ground pin. Connect to the most negative supply. Both pins should be used  
D
Non-inverted data output. Differential output with D  
OUT  
OUT  
3, 6  
4
V
Power pin. Connect to most positive supply. Either or both pins may be used  
PIN cathode connection. Connect photodiode between this pin and PINA  
PIN anode connection. Connect photodiode between this pin and PINK  
CC  
PINK  
PINA  
5
7
D
Inverted data output. Differential output with D  
OUT  
OUT  
Figure 2-1. Bare Die Layout  
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3.0 Functional Description  
3.1  
Overview  
The MC2007-3 is a low-noise, transimpedance amplifier with AGC, manufactured in an advanced, low-cost, sub-  
micron CMOS process. Its wide dynamic range, differential output and high PIN bias make it well suited to high-  
performance telecommunications, especially OC-3/STM-1. However, due to its low cost, the MC2007-3 also meets  
the needs of Datacom applications.  
The MC2007-3 is available in die form. For optimum system performance die should be mounted in close proximity  
to the photodetector.  
The MC2007-3 is designed to be used with the MC2045 or M02095 post amplifier IC. When combined with a  
photodiode, the chip set forms a high performance, low cost 3.3V receiver.  
Figure 3-1. Block Diagram  
Series Pass  
Regulator  
PINK  
Bandgap  
1.23 V  
RREF  
Reference  
Generator  
Set Max. Gain  
AGC Control  
R
DOUT  
+1  
TZA  
PINA  
+1  
DOUT  
+1  
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Functional Description  
Figure 3-2. Top Level Diagram  
V
GND  
D
CC  
OUT  
PINK  
PINA  
D
V
GND  
OUT  
CC  
3.2  
Features  
Low-cost, CMOS process  
Receiver sensitivity typically -39 dBm at 155 Mbps, when integrated into a module with suitable photodiode and  
post-amplifier  
140 MHz bandwidth allows wide range of operation: 100, 125, 155, and 200 Mbps  
Typical differential gain of 62 kat low signal levels  
AGC gives continuous operation to +3 dBm  
65 mW power consumption at +3.3 V supply  
> 35 dB Power-supply noise rejection  
Available as die only  
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Functional Description  
3.3  
General Description  
3.3.1  
TIA  
The transimpedance amplifier consists of a high gain single-ended CMOS amplifier (TIA), with a feedback resistor.  
The feedback creates a low impedance at the input and virtually all of the input current passes through the  
feedback resistor, defining the voltage at the output. Advanced CMOS design techniques are employed to maintain  
the stability of this stage across all input conditions.  
Single-ended amplifiers have inherently poor power supply noise rejection. For this reason, an on-chip, low  
dropout, linear regulator has been incorporated into the design to give excellent noise rejection up to several MHz.  
Higher frequency power supply noise must be removed by external decoupling.  
The circuit is designed for PIN photodiodes in the grounded cathode configuration, with the anode connected to the  
input of the TIA and the cathode connected to the PIN K input. The PIN K pad supplies ~1.7V to reverse bias the  
pin diode to reduce capacitance. If a higher reverse voltage is required, the user may supply their own low  
impedance bias supply.  
3.3.2  
AGC  
The MC2007-3 has been designed to operate over the input range of +3 dBm to –39 dBm at long wavelengths. To  
do so, the AGC achieves a dynamic range compression of 50:1 in transimpedance.  
The AGC only operates on signals greater than –30 dBm (@ 0.9 A/W). This knee in the gain response is important  
when setting signal detect functions in the following post amplifier. It also aids in active photodiode alignment.  
3.3.3  
Output Stage  
The signal from the TIA enters a phase splitter and a pair of voltage follower outputs. These are designed to drive a  
high impedance (>500 ) load. They are stable for driving capacitive loads, such as interstage filters.  
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4.0 Applications Information  
4.1  
Filter Design  
The achievable sensitivity of the MC2007-3 is dependant on the noise bandwidth of the amplifier, which varies with  
temperature and process. The bandwidth should therefore be limited by an interstage filter for maximum  
performance. This will typically be a one pole filter, using a capacitor across the outputs. For maximum sensitivity, a  
filter with steeper roll-off and better transient response can be implemented with inductors and capacitors. If the  
module is intended to be used at several rates, interstage filtering should not be employed. Typical application  
circuit shown in Figure 4-1.  
Figure 4-1. Typical Applications Circuit  
+3.3V  
10 nF  
*470 pF  
10 nF  
VCC  
DOUT  
Gnd  
DIN  
PINK  
PINA  
VCC  
CFILT  
D
IN  
Gnd  
DOUT  
10 nF  
100 pF  
MC2045 or  
M02095  
Post amp  
+3.3V  
* The 470 pF capacitor should be mounted inside the TO can/optical sub assembly  
with the MC2007-3 and the photodiode  
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Applications Information  
4.2  
Alternative Input Arrangement  
An alternative arrangement can be used to connect the photodiode, with the photodiode cathode being connected  
directly to V (see Figure 4-2). This requires two decoupling capacitors, one connecting V to ground, and the  
CC  
CC  
other from PIN K to ground. This arrangement reverse biases the photodiode more, but will have inferior low  
frequency noise performance.  
Figure 4-2. Alternative Application Arrangement  
+3.3V  
10 nF  
VPD  
1 nF  
VCC  
470 pF  
PINK  
PINA  
VCC  
100 pF  
+3.3 V  
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4.3  
T0-Can Assembly Recommendations  
Figure 4-3. Typical TO-Can Assembly  
NOT Recommended Example  
PIN Diode  
This bond is  
unreliable  
This bond is too  
long and  
unreliable  
MC2007  
TO Can Leads  
@4 or 5  
Ceramic Shim  
Submount  
TO-CAN Header  
Recommended Example  
MC2007  
PIN Diode  
Metal  
Shim  
TO Can Leads  
@4 or 5  
Ceramic Shim  
Submount  
TO-CAN Header  
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Applications Information  
4.3.1  
Assembly  
The MC2007 is designed to work with a wirebond inductance of 1 nH 0.25 nH. Many existing TO-Can  
configurations will not allow wirebond lengths that short, since the PIN diode submount and the TIA die are more  
than 1 mm away in the vertical direction, due to the need to have the PIN diode in the correct focal plane. This can  
be remedied by raising up the TIA die with a conductive metal shim. This will effectively reduce the bond wire  
length. Refer to Figure 4-3 above for details.  
Mindspeed recommends ball bonding with a 1 mil (25.4 µm) gold wire. For performance reasons the PINA pad is  
smaller than the others and also has less via material connected to it. It therefore requires more care in setting of  
the bonding parameters. For the same reason PINA has no ESD protection.  
In addition, please refer to the Mindspeed Product Bulletin (document number 0201X-PBD-002). Care must be  
taken when selecting chip capacitors, since they must have good low ESR characteristics up to several hundred  
MHz. It is also important that the termination materials of the capacitor be compatible with the attach method used.  
For example, Tin/Lead (Pb/Sn) solder finish capacitors are incompatible with silver-filled epoxies. Palladium/Silver  
(Pd/Ag) terminations are compatible with silver filled epoxies. Solder can be used only if the substrate thick-film  
inks are compatible with Pb/Sn solders.  
4.3.2  
Recommended Assembly Procedures  
For ESD protection the following steps are recommended for TO-Can assembly:  
a. Ensure good humidity control in the environment (to help minimize ESD).  
b. Consider using additional ionization of the air (also helps minimize ESD).  
c. As a minimum, it is best to ensure that the body of the TO-can header or the ground lead of the  
header is grounded through the wire-bonding fixture for the following steps. The best solution also  
ensures that the V lead of the TO-Can is also grounded. When this is done and the procedure  
CC  
below is followed, any positive charge on the wire bonder when bonding to PINA (the very last  
bond placed) will have the PD acting as an ESD diode into PinK of the device. Internally, PinK has  
an ESD diode between it and VCC that will turn on if V is at ground minimizing the ESD event at  
CC  
PINA.  
d. The wire bonder (including the spool, clamp, etc.) must also be grounded.  
1. Wire-bond the ground pad(s) of the die first.  
2. Then wire bond the V pad to the TO-Can lead.  
CC  
3. Then wire bond any other pads going to the TO-Can leads (such as DOUT, DOUT and possibly  
MON).  
4. Next wire-bond any capacitors inside the TO-Can.  
5. Inside the TO-Can, wire bond PINK.  
6. The final step is to wire bond PINA.  
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Applications Information  
4.4  
TIA Use with Externally Biased Detectors  
In some applications, Mindspeed TIAs are used with detectors biased at a voltage greater than available from TIA  
PIN cathode supply. This works well if some basic cautions are observed. When turned off, the input to the TIA  
exhibits the following I/V characteristic:  
Figure 4-4. TIA Use with Externally Biased Detectors, Powered Off  
PINA Unbiased  
100  
50  
0
-800  
-600  
-400  
-200  
0
200  
400  
600  
800  
1000  
1200  
-50  
-100  
-150  
-200  
-250  
-300  
mV  
The impedance of the input is relatively high and can be easily damaged by ESD or EOS.  
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Applications Information  
After the TIA is turned on, the DC servo and AGC circuits attempt to null any input currents (up to the absolute  
maximum stated in Table 1-1) as shown by the I/V curve in Figure 4-5.  
Figure 4-5. TIA Use with Externally Biased Detectors, Powered On  
PINA biased  
1000  
800  
600  
400  
200  
0
-300  
-200  
-100  
0
100  
200  
300  
400  
500  
600  
700  
-200  
-400  
-600  
-800  
-1000  
mV  
It can be seen that any negative voltage below 200 mV is nulled and that any positive going voltage above the PINA  
standing voltage is nulled by the DC servo. The DC servo upper bandwidth varies from part to part, but is generally  
at least 10 kHz.  
When externally biasing a detector such as an APD where the supply voltage of the APD exceeds that for PINA  
Table 1-1, care should be taken to power up the TIA first and to keep the TIA powered up until after the power  
supply voltage of the APD is removed. Failure to do this with the TIA unpowered may result in damage to the input  
FET gate at PINA. In some cases the damage may be very subtle, in that nearly normal operation may be  
experienced with the damage causing slight reductions in bandwidth and corresponding reductions in input  
sensitivity.  
4.4.1  
Treatment of PINK  
PINK still requires bypassing to ground with a high quality 220-1000 pF (470 pF recommended) capacitor, even  
with no other connection to it. The capacitor stabilizes the internal voltage regulator of the TIA.  
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5.0 Packaging Specification  
5.1  
Die Details  
Table 5-1.  
Bare Die Information  
GND  
DOUT  
GND  
DOUT  
VCC  
VCC  
Die size: 1.01 x 0.96 mm  
Die Thickness: 300 µm ±10%  
Die Process Technology: CMOS  
Die Passivation: Silicon Nitride  
PINK  
PINA  
Table 5-2.  
Pad Coordinates  
Pad No.  
Description  
X (µm)  
Y (µm)  
Pad No.  
Description  
X (µm)  
Y (µm)  
1
2
3
4
GND  
-352.  
-352.  
216.7  
111.7  
-261.7  
-352.  
5
6
7
8
PINA  
153.95  
352.  
-360.  
-261.7  
111.7  
216.7  
D
V
CC  
OUT  
V
-352.  
D
352.  
CC  
OUT  
PINK  
-135.95  
GND  
352.  
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General Information:  
Telephone: (949) 579-3000  
Headquarters - Newport Beach  
4000 MacArthur Blvd., East Tower  
Newport Beach, CA 92660  
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© 2006-2007 Mindspeed Technologies , Inc. All rights reserved.  
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Mindspeed Technologies  
16  
Mindspeed Proprietary and Confidential  

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