MC80C0208K [ETC]
8-BIT SINGLE-CHIP MICROCONTROLLERS; 8位单芯片微控制器
| 型号： | MC80C0208K |
| 厂家： | 
ETC |
| 描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 文件： | 总128页 (文件大小：1502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAGNACHIP SEMICONDUCTOR LTD.
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0208/16/24
MC80C0208/16/24
User’s Manual (Ver. 0.2)
Preliminary
REVISION HISTORY
VERSION 0.2 (MAR. 2005) This book
Version 0.2
Published by
MCU Application Team
2005 MagnaChip semiconductor Inc. All right reserved.
Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distributors and Representatives.
MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way re-
sponsible for any violations of patents or other rights of the third party generated by the use of this manual.
MC80F0208/16/24
1. OVERVIEW .................................................................................................................................................... 1
Description .................................................................................................................................................... 1
Features ........................................................................................................................................................ 1
Ordering Information ...............................................................................................................................2
Development Tools ....................................................................................................................................... 3
2. BLOCK DIAGRAM ........................................................................................................................................ 4
3. PIN ASSIGNMENT ........................................................................................................................................ 5
4. PACKAGE DIAGRAM ................................................................................................................................... 6
5. PIN FUNCTION .............................................................................................................................................. 7
Pin Description .............................................................................................................................................. 8
6. PORT STRUCTURES .................................................................................................................................. 10
7. ELECTRICAL CHARACTERISTICS ........................................................................................................... 13
Absolute Maximum Ratings ........................................................................................................................ 13
Recommended Operating Conditions ......................................................................................................... 13
A/D Converter Characteristics .................................................................................................................... 13
DC Electrical Characteristics ...................................................................................................................... 14
AC Characteristics ...................................................................................................................................... 15
Serial Interface Timing Characteristics ....................................................................................................... 16
Typical Characteristic Curves ..................................................................................................................... 17
8. MEMORY ORGANIZATION ........................................................................................................................ 19
Registers ..................................................................................................................................................... 19
Program Memory ........................................................................................................................................ 21
Data Memory .............................................................................................................................................. 25
Addressing Mode ........................................................................................................................................ 31
9. I/O PORTS ................................................................................................................................................... 35
10. CLOCK GENERATOR .............................................................................................................................. 39
11. BASIC INTERVAL TIMER ......................................................................................................................... 40
12. WATCHDOG TIMER ................................................................................................................................. 42
13. WATCH TIMER .......................................................................................................................................... 45
14. TIMER/EVENT COUNTER ........................................................................................................................ 46
8-bit Timer / Counter Mode ......................................................................................................................... 50
16-bit Timer / Counter Mode ....................................................................................................................... 56
8-bit Compare Output (16-bit) ..................................................................................................................... 57
8-bit Capture Mode ..................................................................................................................................... 58
16-bit Capture Mode ................................................................................................................................... 62
PWM Mode ................................................................................................................................................. 65
15. ANALOG TO DIGITAL CONVERTER ....................................................................................................... 68
16. SERIAL INPUT/OUTPUT (SIO) ................................................................................................................. 71
Transmission/Receiving Timing .................................................................................................................. 72
The method of Serial I/O ............................................................................................................................. 74
The Method to Test Correct Transmission .................................................................................................. 74
17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ................................................... 75
UART Serial Interface Functions ................................................................................................................ 75
MAR. 2005 Ver 0.2
MC80F0208/16/24
Serial Interface Configuration ..................................................................................................................... 77
Communication operation ........................................................................................................................... 80
Relationship between main clock and baud rate ........................................................................................ 82
18. BUZZER FUNCTION ................................................................................................................................. 83
19. INTERRUPTS ............................................................................................................................................ 85
Interrupt Sequence ..................................................................................................................................... 87
BRK Interrupt .............................................................................................................................................. 89
Shared Interrupt Vector ............................................................................................................................... 89
Multi Interrupt .............................................................................................................................................. 90
External Interrupt ........................................................................................................................................ 91
20. OPERATION MODE .................................................................................................................................. 93
Operation Mode Switching .......................................................................................................................... 93
21. POWER SAVING OPERATION ................................................................................................................ 94
Sleep Mode ................................................................................................................................................. 94
Stop Mode ................................................................................................................................................... 95
Stop Mode at Internal RC-Oscillated Watchdog Timer Mode ..................................................................... 98
Minimizing Current Consumption .............................................................................................................. 100
22. OSCILLATOR CIRCUIT .......................................................................................................................... 102
23. RESET ..................................................................................................................................................... 103
24. POWER FAIL PROCESSOR ................................................................................................................... 104
25. FLASH PROGRAMMING ........................................................................................................................ 106
Device Configuration Area ........................................................................................................................ 106
26. Emulator EVA. Board Setting .............................................................................................................. 107
27. IN-SYSTEM PROGRAMMING (ISP) ....................................................................................................... 110
Getting Started / Installation ...................................................................................................................... 110
Basic ISP S/W Information ........................................................................................................................ 110
Hardware Conditions to Enter the ISP Mode ............................................................................................ 111
Reference ISP Circuit diagram ................................................................................................................. 113
A. INSTRUCTION ............................................................................................................................................... i
Terminology List ..............................................................................................................................................i
Instruction Map ..............................................................................................................................................ii
Instruction Set ...............................................................................................................................................iii
B. MASK ORDER SHEET ................................................................................................................................ ix
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
MC80F0208/16/24
MC80C0208/16/24
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 10-BIT A/D CONVERTER AND UART
1. OVERVIEW
1.1 Description
The MC80F0208/16/24 is advanced CMOS 8-bit microcontroller with 8K/16K/24K bytes of FLASH(ROM). This is a powerful microcon-
troller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following
standard features : 8K/16K/24K bytes of FLASH, 1K bytes of RAM, 8/16-bit timer/counter, watchdog timer, watch timer, 10-bit A/D con-
verter, 8-bit Serial Input/Output, UART, buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also has 8
high current I/O pins with typical 20mA. In addition, the MC80F0208/16/24 supports power saving modes to reduce power consumption.
Device Name
FLASH(ROM)
RAM
ADC
PWM
I/O PORT
Package
Size
FLASH
MASK ROM
MC80C0208Q
MC80C0208K
MC80C0216Q
MC80C0216K
MC80C0224Q
MC80C0224K
MC80F0208Q
MC80F0208K
MC80F0216Q
MC80F0216K
MC80F0224Q
MC80F0224K
44MQFP
42SDIP
44MQFP
42SDIP
44MQFP
42SDIP
1024
Byte
8KByte
8 channel 1 channel
8 channel 1 channel
8 channel 1 channel
36 port
36 port
36 port
1024
Byte
16KByte
24KByte
1024
Byte
1.2 Features
• 8K/16K/24K Bytes On-chip ROM
- One Serial I/O and two UART
• FLASH Mermory
• One Buzzer Driving port
- Endurance : 100 cycles
- Data Retention : 10 years
- 488Hz ~ 250kHz@4MHz
• Four External Interrupt input ports
• 1024 Bytes On-chip Data RAM
(Included stack memory)
• Fifteen Interrupt sources
- Basic Interval Timer(1)
- External input(4)
• Minimum Instruction Execution Time
- 333ns at 12MHz (NOP instruction)
- Timer/Event counter(5)
- ADC(1)
- Serial Interface(1), UART(2)
- WDT and Watch Timer(1)
• 36 I/O Ports
• One 8-bit Basic Interval Timer
• Four 8-bit and one 16-bit Timer/Event counter
(or three 16-bit Timer/Event counter)
• Built in Noise Immunity Circuit
- Noise filter
- 3-level Power fail detector [3.0V, 2.7V, 2.4V]
• One Watchdog timer
• Power Down Mode
- Stop, Sleep mode
• One Watch timer
• One 10-bit PWM
• Operating Voltage Range
- 2.7V ~ 5.5V (@ 8MHz)
- 4.5V ~ 5.5V (@ 12MHz)
• 8 channel 10-bit A/D converter
• Three 8-bit Serial Communication Interface
MAR. 2005 Ver 0.2
1
MC80F0208/16/24
Preliminary
• Operating Frequency Range
- 0.4 ~ 12MHz
• Oscillator Type
- Crystal, Ceramic resonator, External clock
• 44MQFP, 42SDIP type
• Operating Temperature : -40°C ~ 85°C
1.3 Ordering Information
ROM Type
Device name
MC80C0208Q
ROM Size
8K bytes
RAM size
Package
44MQFP
1024 bytes
MC80C0208K
8K bytes
42SDIP
MC80C0216Q
MC80C0216K
16K bytes
16K bytes
44MQFP
42SDIP
Mask version
1024 bytes
1024 bytes
1024 bytes
1024 bytes
1024 bytes
MC80C0224Q
MC80C0224K
24K bytes
24K bytes
44MQFP
42SDIP
MC80F0208Q
MC80F0208K
8K bytes FLASH
8K bytes FLASH
44MQFP
42SDIP
MC80F0216Q
MC80F0216K
16K bytes FLASH
16K bytes FLASH
44MQFP
42SDIP
FLASH version
MC80F0224Q
MC80F0224K
24K bytes FLASH
24K bytes FLASH
44MQFP
42SDIP
Table 1-1 Ordering Information of MC80F0208/16/24 & MC80C0208/16/24
2
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
1.4 Development Tools
The MC80F0208/16/24 is supported by a full-featured macro as-
sembler, an in-circuit emulator CHOICE-Dr.TM and OTP pro-
grammers. There are two different type of programmers such as
single type and gang type. For mode detail, Macro assembler op-
erates under the MS-Windows 95 and upversioned Windows OS.
Please contact sales part of MagnaChip semiconductor.
- MS-Windows based assembler
Software
- MS-Windows based Debugger
- MC800 C compiler
Hardware
(Emulator)
- CHOICE-Dr.
- CHOICE-Dr. EVA80C0x B/D
- CHOICE - SIGMA I/II(Single writer)
FLASH Writer - PGM Plus I/II/III(Single writer)
- Standalone GANG4 I/II(Gang writer)
Choice-Dr. (Emulator)
PGMplus III ( Single Writer )
Standalone Gang4 II ( Gang Writer )
MAR. 2005 Ver 0.2
3
MC80F0208/16/24
Preliminary
2. BLOCK DIAGRAM
Power
Supply
ADC Power
Supply
R00~R07
R0
PSW
A
PC
X
Y
Stack Pointer
ALU
Data Memory
(1024 bytes)
Program
Memory
Interrupt Controller
Data Table
8-bit Basic
Interval
Timer
System controller
System
Clock Controller
8-bit
Timer/
Counter
Watch/
Watchdog
Timer
8-bit serial
Interface
SIO/UART0
8-bit serial
Interface
UART1
Instruction
Decoder
10-bit
PWM
10-bit
ADC
Timing Generator
Clock
Generator
Driver
Buzzer
R1
R5
R4
R6
R3
R60/AN0
R61/AN1
R62/AN2
R63/AN3
R64/AN4
R65/AN5
R66/AN6
R67/AN7
R10/INT0
R50/INT3
R40
R41
R42/SCK
R43/SI
R44/SO
R45/ACLK0
R46/RxD0
R47/TxD0
R30
R11/INT1
R12/INT2
R13/BUZO
R15/EC0
R51/EC1
R31/ACLK1
R32/RxD1
R33/TxD1
R54/PWM3O/T3O
4
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
3. PIN ASSIGNMENT
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R63 / AN3
DD
42SDIP
(Top View)
AN4 / R64
AN5 / R65
AN6 / R66
AN7 / R67
R00
R62 / AN2
R61 / AN1
R60 / AN0
R54 / PWM3O / T3O
AV
DD
R51 / EC1
R50 / INT3
R47 / TxD0
R46 / RxD0
R45 / ACLK0
R44 / SO
R43 / SI
R01
R02
R03
R04
R05
R06
R07
INT0 / R10
INT1 / R11
INT2 / R12
BUZO / R13
EC0 / R15
R42 / SCK
R41
R40
R33 / TxD1
R32 / RxD1
R31 / ACLK1
R30
RESET
X
OUT
IN
X
V
SS
44MQFP
(Top View)
34
35
36
37
38
39
40
41
42
T3O / PWM3O / R54
AN0 / R60
NC
22
21
20
19
18
17
16
15
14
13
12
R33 / TxD1
R32 / RxD1
R31 / ACLK1
R30
AN1 / R61
AN2 / R62
AN3 / R63
V
DD
MC80F0208Q/16Q/24Q
V
SS
OUT
IN
AN4 / R64
AN5 / R65
AN6 / R66
AN7 / R67
NC
X
X
RESET
R15 / EC0
R13 / BUZO
43
44
MAR. 2005 Ver 0.2
5
MC80F0208/16/24
Preliminary
4. PACKAGE DIAGRAM
42SDIP
UNIT: INCH
1.470
1.450
0.600 BSC
0.550
0.530
0.070 BSC
0.045
0.035
0.020
0.016
0-15°
44MQFP
UNIT: MM
13.45
12.95
10.10
9.90
0-7°
SEE DETAIL “A”
1.03
0.73
2.35 max.
1.60
BSC
0.80 BSC
0.45
0.30
DETAIL “A”
6
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
5. PIN FUNCTION
VDD: Supply voltage.
port with typical 20mA at low level output.
In addition, R3 serves the functions of the following special fea-
tures such as ACLK1 (UART1 Asynchronous serial clock input),
RxD1 (UART1 data input), TxD1 (UART1 data output).
VSS: Circuit ground.
AVDD: Supply voltage to the ladder resistor of ADC circuit.
RESET: Reset the MCU.
R40~R47: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins
with 1 or 0 written to the R4 Port Direction Register R4IO can be
used as outputs or inputs. The internal pull-up resistor can be con-
nected by using the pull-up selection register 4 (PU4).
In addition, R4 serves the functions of the various following spe-
cial features such as SCK (Serial clock), SI (Serial data input), SO
(Serial data output), ACLK0 (UART1 Asynchronous serial clock
input), RxD0 (UART0 data input), TxD0 (UART0 data output).
XIN: Input to the inverting oscillator amplifier and input to the in-
ternal main clock operating circuit.
XOUT: Output from the inverting oscillator amplifier.
R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins
with 1 or 0 written to the R0 Port Direction Register R0IO can be
used as outputs or inputs. The internal pull-up resistor can be con-
nected by using the pull-up selection register 0 (PU0).
R50, R51, R54: R5 is an 3-bit CMOS bidirectional I/O port. R5
pins with 1 or 0 written to the R5 Port Direction Register R5IO
can be used as outputs or inputs.
In addition, R5 serves the functions of the various following spe-
cial features such as INT3 (External interrupt 3), EC1 (Event
counter input 1), PWM3O (PWM output 3)/T3O(Timer3 Com-
pare output).
R10~R13, R15: R1 is an 5-bit CMOS bidirectional I/O port. R1
pins with 1 or 0 written to the R1 Port Direction Register R1IO
can be used as outputs or inputs. The internal pull-up resistor can
be connected by using the pull-up selection register 1 (PU1).
In addition, R1 serves the functions of the various following spe-
cial features such as INT0 (External interrupt 0), INT1 (External
interrupt 1), INT2 (External interrupt 2), BUZO (Buzzer driver
output), EC0 (Event counter input 0).
R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins
with 1 or 0 written to the R6 Port Direction Register R6IO can be
used as outputs or inputs.
In addition, R6 serves the functions of the ADC analog input port
AN[7:0].
R30~R33: R3 is an 4-bit CMOS bidirectional I/O port. R3 pins
with 1 or 0 written to the R3 Port Direction Register R3IO can be
used as outputs or inputs. R3 operates as the high current output
MAR. 2005 Ver 0.2
7
MC80F0208/16/24
Preliminary
5.1 Pin Description
5.1.1 Normal Function Pin Description
Initial
state
Alternate
Function
PIN NAME In/Out
Function
Port0
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Internal pull-up resistor PU0 can be used via software.
R00~R07
I/O
I/O
Input
-
R10
R11
R12
R13
R15
R30
R31
R32
R33
R40
R41
R42
R43
R44
R45
R46
R47
R50
R51
R54
INT0
INT1
INT2
BUZO
EC0
Port 1.
5-bit I/O port.
Input
Can be set in input or output mode in 1-bit units.
Internal pull-up resistor PU1 can be used via software.
-
Port 3.
4-bit I/O port.
Can be set in input or output mode in 1-bit units.
ACLK1
RxD1
TxD1
-
I/O
I/O
Input
Input
-
SCK
SI
Port 4.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Internal pull-up resistor PU4 can be used via software.
SO
ACLK0
RxD0
TxD0
INT3
EC1
Port 5.
3-bit I/O port.
Can be set in input or output mode in 1-bit units.
I/O
I/O
Input
Input
PWM3O/T3O
Port 6.
8-bit I/O port.
R60~R67
AN0~AN7
Can be set in input or output mode in 1-bit units.
RESET
XIN
I
I
System reset input.
Input
Input
-
-
-
Crystal connection for main system clock oscillation.
XOUT
AVDD
O
Output
Analog power/reference voltage input to A/D converter.
Set the same potential as VDD.
-
-
-
VDD
VSS
-
-
Positive power supply.
Ground potential.
-
-
-
-
Table 5-1 Normal Function Pin Description
8
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
5.1.2 Alternate Function Pin Description
Initial
state
Shared
Pin
PIN NAME In/Out
Function
INT0
R10
R11
R12
R50
R13
R15
R51
R42
R43
R44
R45
R46
R47
R31
R32
R33
INT1
INT2
Valid edges(rising, falling, or both rising and falling) can be specified.
External Interrupt request Input.
I
Input
INT3
BUZO
EC0
O
I
Buzzer Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Timer0 Event Counter Input
EC1
I
Timer2 Event Counter Input
SCK
I/O
I
Serial clock input/output of serial interface.
Serial data input of serial interface.
Serial data output of serial interface.
Asynchronous serial interface serial clock input.
Asynchronous serial interface serial data input.
Asynchronous serial interface serial data output.
Asynchronous serial interface serial clock input2.
Asynchronous serial interface serial data input2.
Asynchronous serial interface serial data output2.
Timer3 PWM Output
SI
SO
O
I
ACLK0
RxD0
TxD0
ACLK1
RxD1
TxD1
PWM3O
T3O
I
O
I
I
O
O
I
Output
Input
R54
Timer3 Compare Output
AN0~AN7
Analog input Channel 0 ~ 7 for A/D converter.
R60~R67
Table 5-2 Alternate Function Pin Description
MAR. 2005 Ver 0.2
9
MC80F0208/16/24
Preliminary
6. PORT STRUCTURES
R00~R07, R40, R41
R13(BUZO), R47(TxD0)
V
DD
V
DD
Pull-up
Tr.
Pull-up
Tr.
Pull-up
Reg.
Pull-up
Reg.
V
DD
V
DD
V
BUZO,TxD0
Data Reg.
DD
V
Data Reg.
DD
MUX
Pin
Direction
Reg.
Pin
Direction
Reg.
V
SS
V
SS
V
SS
V
SS
BUZO_EN,TxD0_EN
Data Bus
MUX
MUX
RD
Data Bus
RD
R10(INT0)~ R12(INT2), R15(EC0), R43(SI),
R45(ACLK0), R46(RxD0)
R30
V
DD
Pull-up
Tr.
Pull-up
Reg.
V
DD
V
DD
V
DD
V
DD
Data Reg.
Data Reg.
Pin
Direction
Reg.
Direction
Reg.
Pin
V
SS
V
SS
V
SS
V
SS
Data Bus
Data Bus
MUX
RD
MUX
RD
INT,EC,SI,
RxD0, ACLK0
Noise
Filter
INT_EN, EC_EN
SI_EN, ACLK0_EN, RxD0_EN
10
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
R33(TxD1)
R44(SO, IOSWIN)
V
DD
Pull-up
Tr.
Pull-up
Reg.
V
V
DD
SO
TxD1
DD
V
V
DD
DD
MUX
Data Reg.
MUX
Data Reg.
Direction
Reg.
Pin
Pin
Direction
Reg.
V
V
SS
SS
V
V
SS
SS
TxD1_EN
SO_EN
Data Bus
MUX
MUX
Data Bus
RD
IOSWIN_EN
SI
Noise
Filter
RD
IOSWIN_EN
R42(SCK)
R31(ACLK1), R32(RxD1), R50(INT3), R51(EC1)
V
DD
Pull-up
Tr.
V
DD
Pull-up
Reg.
V
DD
Data Reg.
V
SCK
DD
V
DD
Direction
Reg.
Data Reg.
MUX
Pin
Direction
Reg.
Pin
V
SS
V
SS
V
SCKO_EN
Data Bus
SS
MUX
Data Bus
MUX
RD
Noise
Filter
RD
INT3, EC1
ACLK1, RxD1
SCKI_EN
SCK
Noise
Filter
INT3_EN, EC1_EN
ACLK1_EN, RxD1_EN
MAR. 2005 Ver 0.2
11
MC80F0208/16/24
Preliminary
R54(PWM3O/T3O)
X , X
IN
OUT
V
DD
PWM3O
V
DD
V
DD
Data Reg.
MUX
X
IN
STOP
Pin
Direction
Reg.
V
SS
V
SS
V
V
SS
SS
PWM3_EN
V
DD
MUX
Data Bus
MAIN
CLOCK
X
OUT
RD
V
SS
R60~R67(AN0~AN7)
RESET
V
DD
V
DD
V
DD
Data Reg.
Mask only
Direction
Reg.
Pin
Internal Reset
Pin
V
SS
V
SS
Data Bus
V
SS
MUX
RD
AN[7:0]
ADC_EN & CH_SEL
12
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Parameter
Symbol
VDD
AVDD
VI
Rating
Unit
V
Note
-0.3 ~ +6.5
-
-
Supply Voltage
VDD - 0.3 ~ VDD +0.3
-0.3 ~ VDD +0.3
-0.3 ~ VDD +0.3
V
V
Voltage on any pin with respect to Ground (VSS
)
VO
V
IOH
Maximum output current sourced by (IOH per I/O Pin)
Maximum current (ΣIOH
Maximum current sunk by (IOL per I/O Pin)
10
mA
mA
mA
mA
mW
°C
Normal Votagae Pin
ΣIOH
IOL
)
80
20
ΣIOL
fXIN
Maximum current (ΣIOL)
160
Total Power Dissipation
Storage Temperature
600
-
TSTG
-65 ~ +150
°C
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
Note: Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the de-
vice. This is a stress rating only and functional operation of
the device at any other conditions above those indicated in
7.2 Recommended Operating Conditions
Specifications
Unit
Parameter
Symbol
Condition
Min.
Max.
5.5
5.5
85
fXIN = 0.4 ~ 12MHz
4.5
V
V
VDD
Supply Voltage
Operating Temperature
f
XIN = 0.4 ~ 8MHz
2.7
TOPR
VDD = 4.5 ~ 5.5V
-40
°C
7.3 A/D Converter Characteristics
(Ta=-40~85°C, VSS=0V, VDD= AVDD = 2.7~5.5V @fXIN=4MHz)
Parameter
Resolution
Symbol
-
Conditions
Min.
Typ.
Max.
Unit
BIT
-
-
-
-
-
-
-
10
-
-
-
Total Accuracy
±3
±2
±2
±2
±2
LSB
LSB
LSB
LSB
LSB
ILE
Intergral Linearity Error
Differential Linearity Error
Zero Offset Error
-
AVDD = VDD = 5.12V
fXIN = 4Mhz
DLE
ZOE
FSE
-
-
Full Scale Error
-
10bit conversion
fXIN = 4Mhz
tCON
Conversion Time
13*
-
-
µS
MAR. 2005 Ver 0.2
13
MC80F0208/16/24
Preliminary
Parameter
Analog Input Voltage
Analog Power Supply
Analog Ground
Symbol
VAN
Conditions
Min.
Typ.
Max.
AVDD
Unit
V
VSS
-
-
AVDD
VSS
VDD
-
-
-
V
VSS
VSS+0.3
-
-
-
V
IADIN
IADC
AVDD=VDD=5.12V
AVDD=VDD=5.12V
Analog Input Current
Analog Block Current
-
-
10
µA
µA
200
300
2
Note : 4MHz(f ) / 2 X 13Cycle = 13uS
XIN
7.4 DC Electrical Characteristics
(TA=-40~85°C, VDD=5.0V±10%, VSS=0V, fXIN=8MHz)
Parameter
Symbol
Pin/Condition
Min.
Typ.
Max.
VDD+0.3
DD+0.3
Unit
INT0, INT1, INT2, INT3, EC0, EC1,
SI, SCK, ACLK0, ACLK1, RxD0,
RxD1, RESET
VIH1
0.8VDD
-
V
Input High Voltage
VIH2
VIH3
0.7VDD
0.8VDD
V
R0, R1, R3, R4, R5, R6
XIN
-
-
V
V
VDD+0.3
INT0, INT1, INT2, INT3, EC0, EC1,
SI, SCK, ACLK0,ACLK1, RxD0,
RxD1, RESET
VIL1
0.2VDD
-0.3
-
V
Input Low Voltage
VIL2
VIL3
0.3VDD
R0, R1, R3, R4, R5, R6
XIN
-0.3
-0.3
-
-
-
-
-
-
-
V
V
0.2VDD
VOH1
VOH2
VOL1
VOL2
IOL
R0, R1, R3, R4, R5, R6 (IOH=-0.7mA)
XOUT (IOH=-50µA)
VDD-0.4
VDD-0.5
-
V
Output High Voltage
-
V
R0, R1, R3, R4, R5, R6 (IOL=1.6mA)
XOUT (IOL=50µA)
-
-
0.4
0.5
20
V
Output Low Voltage
High Current
V
R3 (VOL=1V)
-
mA
Input High Leakage
Current
IIH
IIL
R0, R1, R3, R4, R5, R6
R0, R1, R3, R4, R5, R6
-
-
-
1
-
µA
µA
Input Low
Leakage Current
-1
Pull-up Resistor
RPU
RX
R0, R1, R4
XIN, XOUT
10
-
-
100
4.5
kΩ
OSC Feedback Resistor
0.45
MΩ
Internal RC WDT Period
(RCWDT)
IIL
VDD=4.5V
33
-
-
100
0.8
µS
INT0, INT1, INT2, INT3, EC0, EC1,
SI, SCK, ACLK0, ACLK1, RxD0,RxD1
VT
Hysteresis
0.3
V
2.2
2.5
1.9
2.7
3.0
2.4
3.2
3.5
2.9
V
V
V
Power Fail Detect
Voltage
VPFD
14
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Parameter
Symbol
Pin/Condition
Active Mode, X =8MHz
Min.
Typ.
Max.
15
6
Unit
mA
mA
µA
IDD1
-
-
-
-
-
-
-
-
IN
ISLEEP Sleep Mode, X =8MHz
IN
Power Supply Current
ISTOP
Stop Mode, Oscillator Stop, X =4MHz
5
IN
IRCWDT Stop Mode, Oscillator Stop, X =8MHz
40
µA
IN
MAR. 2005 Ver 0.2
15
MC80F0208/16/24
Preliminary
7.5 AC Characteristics
(TA=-40~85°C, VDD=5V±10%, VSS=0V)
Specifications
Parameter
Symbol
Pins
Unit
Min.
Typ.
Max.
fXIN
tST
XIN
Operating Frequency
0.4
-
12
MHz
mS
Oscillation Stabilizing
Time (4MHz)
XIN, XOUT
-
35
-
-
-
-
20
-
External Clock Pulse
Width
tCPW
XIN
XIN
nS
nS
External Clock Transi-
tion Time
t
RCP,tFCP
20
tIW
tSYS
tSYS
Interrupt Pulse Width
RESET Input Width
INT0, INT1, INT2, INT3
RESET
2
8
-
-
-
-
tRST
Event Counter Input
Pulse Width
tECW
tSYS
nS
EC0, EC1
EC0, EC1
2
-
-
-
-
Event Counter Transi-
tion Time
tREC, FEC
t
20
t
= 1/f
t
t
CPW
SYS
XIN
CPW
V
-0.5V
DD
XIN
0.5V
t
t
RCP
FCP
t
t
IW
IW
0.8V
DD
INT0~INT3
RESET
0.2V
DD
t
RST
0.2V
DD
t
t
ECW
ECW
0.8V
DD
EC0, EC1
0.2V
DD
t
t
REC
FEC
Figure 7-1 Timing Chart
16
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7.6 Serial Interface Timing Characteristics
(TA=-40~+85°C, VDD=5V±10%, VSS=0V, fXIN=8MHz)
Specifications
Parameter
Serial Input Clock Pulse
Symbol
Pins
Unit
Min.
Typ.
Max.
tSCYC
tSCKW
tFSCK
tRSCK
tFSIN
tRSIN
tSUS
tSUS
2tSYS+200
tSYS+70
SCK
SCK
-
-
-
-
nS
nS
Serial Input Clock Pulse Width
Serial Input Clock Pulse Transition Time
SCK
SI
-
-
-
-
30
nS
nS
Serial Input Pulse Transition Time
30
-
Serial Input Setup Time (External SCK)
Serial Input Setup Time (Internal SCK)
Serial Input Hold Time
SI
SI
100
200
-
-
-
-
nS
nS
nS
nS
nS
tHS
tSYS+70
4tSYS
SI
tSCYC
tSCKW
tFSCK
tRSCK
16tSYS
Serial Output Clock Cycle Time
Serial Output Clock Pulse Width
SCK
SCK
tSYS-30
Serial Output Clock Pulse Transition Time
Serial Output Delay Time
SCK
SO
30
nS
nS
sOUT
100
t
SCYC
t
t
RSCK
FSCK
t
t
SCKW
SCKW
0.8V
0.2V
DD
DD
SCK
t
t
SUS
HS
0.8V
DD
DD
SI
0.2V
t
t
FSIN
RSIN
t
DS
SO
0.8V
0.2V
DD
DD
Figure 7-2 Serial I/O Timing Chart
MAR. 2005 Ver 0.2
17
MC80F0208/16/24
Preliminary
7.7 Typical Characteristic Curves
This graphs and tables provided in this section are for design
guidance only and are not tested or guaranteed.
The data presented in this section is a statistical summary of data
collected on units from different lots over a period of time. “Typ-
ical” represents the mean of the distribution while “max” or
“min” represents (mean + 3σ) and (mean − 3σ) respectively
where σ is standard deviation
In some graphs or tables the data presented are out-
side specified operating range (e.g. outside specified
VDD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
I
−V
I
I
I
−V
R0,R1,R3~R6 pins
OH
OH
OH OH
R0,R1,R3~R6 pins
I
I
OH
OH
V
=5.0V
V
=3.0V
DD
T =25°C
A
(mA)
DD
(mA)
T =25°C
A
-12
-12
-9
-6
-9
-6
-3
0
-3
0
(V)
V -V
DD OH
V
-V
0.5 1.0
0.5 1.0
1.5 2.0
1.5 2.0
2.5
(V)
DD OH
−V
I
−V
OL1
R0,R1, R4~R6 pins
OL
OL1
R0~R2, R4~R6 pins
OL
I
I
OL
OL
V
=3.0V
V
=5.0V
DD
(mA)
DD
(mA)
T =25°C
T =25°C
A
A
20
40
15
10
30
20
5
0
10
0
V
(V)
OL
0.5 1.0
1.5 2.0
R3 pin
V
0.5 1.0
2.5
1.5 2.0
(V)
OL
−V
I
−V
OL2
OL
V
OL2
R3 pin
OL
I
I
OL
OL
=3.0V
V
=5.0V
DD
(mA)
DD
(mA)
T =25°C
T =25°C
A
A
20
40
15
10
30
20
5
0
10
0
(V)
V
OL
0.5 1.0
1.5 2.0
0.5 1.0
2.5
1.5 2.0
V
(V)
OL
18
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
I
−V
DD
I
−V
I
−V
DD
Main Active Mode
SLEEP
DD
Main Active Mode
STOP DD
Main Active Mode
I
I
I
DD
DD
DD
(mA)
(mA)
(µA)
T =25°C
T =25°C
T =25°C
A
A
A
10
4
4
7.5
5
3
2
3
f
= 12MHz
XIN
8MHz
2
8MHz
V
f
= 12MHz
XIN
f
= 12MHz, 8MHz, 4MHz
XIN
2.5
0
1
0
1
0
4MHz
5
4MHz
5
V
V
DD
DD
DD
(V)
2
3
6
(V)
6
4
2
3
(V)
6
4
2
3
4
5
Operating Area
f
XIN
(MHz)
T = -40~85°C
A
16
Actual Operating Area
2.1~7.0V @ (0.2~8MHz)
2.6~7.0V @ (0.2~16MHz)
14
12
10
8
Spec Operating Area
2.7~5.5V @ (0.4~8MHz)
4.5~5.5V @ (0.4~12MHz)
6
4
2
0
V
(V)
1
2
3
6
4
5
7
DD
MAR. 2005 Ver 0.2
19
MC80F0208/16/24
Preliminary
8. MEMORY ORGANIZATION
The MC80F0208/16/24 has separate address spaces for Program
memory and Data Memory. Program memory can only be read,
not written to. It can be up to 48K bytes of Program memory.
Data memory can be read and written to up to 1024 bytes includ-
ing the stack area.
8.1 Registers
This device has six registers that are the Program Counter (PC),
a Accumulator (A), two index registers (X, Y), the Stack Pointer
(SP), and the Program Status Word (PSW). The Program Counter
consists of 16-bit register.
executed or an interrupt is accepted. However, if it is used in ex-
cess of the stack area permitted by the data memory allocating
configuration, the user-processed data may be lost.
The stack can be located at any position within 100H to 1FFH of
the internal data memory. The SP is not initialized by hardware,
requiring to write the initial value (the location with which the use
of the stack starts) by using the initialization routine. Normally,
the initial value of “FFH” is used.
A
X
ACCUMULATOR
X REGISTER
Y REGISTER
Y
Stack Address (100 ~ 1FF )
H
H
STACK POINTER
SP
Bit 15
8 7
Bit 0
01
SP
H
PROGRAM COUNTER
PCH
PCL
00 ~FF
H
H
PSW
PROGRAM STATUS WORD
Hardware fixed
Figure 8-1 Configuration of Registers
Note: The Stack Pointer must be initialized by software be-
cause its value is undefined after Reset.
Accumulator: The Accumulator is the 8-bit general purpose reg-
ister, used for data operation such as transfer, temporary saving,
and conditional judgement, etc.
Example: To initialize the SP
The Accumulator can be used as a 16-bit register with Y Register
as shown below.
LDX
#0FFH
TXSP
; SP ← FFH
Y
Program Counter: The Program Counter is a 16-bit wide which
consists of two 8-bit registers, PCH and PCL. This counter indi-
cates the address of the next instruction to be executed. In reset
state, the program counter has reset routine address (PCH:0FFH,
PCL:0FEH).
Y
A
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Program Status Word: The Program Status Word (PSW) con-
tains several bits that reflect the current state of the CPU. The
PSW is described in Figure 8-3. It contains the Negative flag, the
Overflow flag, the Break flag the Half Carry (for BCD opera-
tion), the Interrupt enable flag, the Zero flag, and the Carry flag.
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers: In the addressing mode which uses these index
registers, the register contents are added to the specified address,
which becomes the actual address. These modes are extremely ef-
fective for referencing subroutine tables and memory tables. The
index registers also have increment, decrement, comparison and
data transfer functions, and they can be used as simple accumula-
tors.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU after
an arithmetic operation and is also changed by the Shift Instruc-
tion or Rotate Instruction.
[Zero flag Z]
Stack Pointer: The Stack Pointer is an 8-bit register used for oc-
currence interrupts and calling out subroutines. Stack Pointer
identifies the location in the stack to be accessed (save or restore).
This flag is set when the result of an arithmetic operation or data
transfer is “0” and is cleared by any other result.
Generally, SP is automatically updated when a subroutine call is
20
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
MSB
N
LSB
C
V
G
B
H
I
Z
RESET VALUE: 00
PSW
NEGATIVE FLAG
H
CARRY FLAG RECEIVES
CARRY OUT
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE
when G=1, page is selected to “page 1”
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
BRK FLAG
Figure 8-3 PSW (Program Status Word) Register
This flag assigns RAM page for direct addressing mode. In the di-
[Interrupt disable flag I]
rect addressing mode, addressing area is from zero page 00H to
0FFH when this flag is "0". If it is set to "1", addressing area is
assigned 100H to 1FFH. It is set by SETG instruction and cleared
by CLRG.
This flag enables/disables all interrupts except interrupt caused
by Reset or software BRK instruction. All interrupts are disabled
when cleared to “0”. This flag immediately becomes “0” when an
interrupt is served. It is set by the EI instruction and cleared by
the DI instruction.
[Overflow flag V]
[Half carry flag H]
This flag is set to “1” when an overflow occurs as the result of an
arithmetic operation involving signs. An overflow occurs when
the result of an addition or subtraction exceeds +127(7FH) or -
128(80H). The CLRV instruction clears the overflow flag. There
is no set instruction. When the BIT instruction is executed, bit 6
of memory is copied to this flag.
After operation, this is set when there is a carry from bit 3 of ALU
or there is no borrow from bit 4 of ALU. This bit can not be set
or cleared except CLRV instruction with Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish BRK
from TCALL instruction with the same vector address.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the result of
a data or arithmetic operation. When the BIT instruction is exe-
cuted, bit 7 of memory is copied to this flag.
[Direct page flag G]
MAR. 2005 Ver 0.2
21
MC80F0208/16/24
Preliminary
At execution of
a CALL/TCALL/PCALL
At acceptance
of interrupt
At execution
of RET instruction
At execution
of RET instruction
Push
down
01FF
01FE
01FD
01FC
PCH
PCL
01FF
01FE
01FD
PCH
PCL
PSW
01FF
01FE
01FD
PCH
01FF
01FE
01FD
PCH
Pop
up
Push
down
Pop
up
PCL
PCL
PSW
01FC
01FC
01FC
SP before
execution
01FF
01FD
01FF
01FC
01FD
01FF
01FC
01FF
SP after
execution
At execution
At execution
of PUSH instruction
PUSH A (X,Y,PSW)
of POP instruction
POP A (X,Y,PSW)
Push
down
Pop
up
01FF
01FE
01FF
01FE
A
A
0100H
Stack
depth
01FD
01FC
01FD
01FC
01FFH
SP before
01FF
01FE
01FE
01FF
execution
SP after
execution
Figure 8-4 Stack Operation
8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K
bytes, but this device has 32/48K bytes program memory space
only physically implemented. Accessing a location above FFFFH
will cause a wrap-around to 0000H.
CPU begins execution from reset vector which is stored in ad-
dress FFFEH and FFFFH as shown in Figure 8-6.
As shown in Figure 8-5, each area is assigned a fixed location in
Program Memory. Program Memory area contains the user pro-
gram
Figure 8-5, shows a map of Program Memory. After reset, the
22
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
.
The interrupt causes the CPU to jump to specific location, where
it commences the execution of the service routine. The External
interrupt 0, for example, is assigned to location 0FFFCH. The in-
terrupt service locations spaces 2-byte interval: 0FFFAH and
0FFFBH for External Interrupt 1, 0FFFCH and 0FFFDH for Ex-
ternal Interrupt 0, etc.
A000
C000
H
H
Any area from 0FF00H to 0FFFFH, if it is not going to be used,
its service location is available as general purpose Program Mem-
ory.
E000
H
Address
Vector Area Memory
Basic Interval Timer
0FFE0
H
FEFF
FF00
H
H
E2
E4
E6
E8
Watch / Watchdog Timer Interrupt
A/D Converter
FFC0
H
Timer/Counter 4 Interrupt
Timer/Counter 3 Interrupt
Timer/Counter 2 Interrupt
Timer/Counter 1 Interrupt
Timer/Counter 0 Interrupt
Serial Input/Output (SIO)
UART1 Rx/Tx interrupt
UART0 Rx/Tx interrupt
External Interrupt 3
TCALL area
FFDF
FFE0
H
H
Interrupt
Vector Area
FFFF
EA
EC
EE
F0
F2
F4
F6
F8
FA
FC
FE
H
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to reduce
program byte length by using 2 bytes PCALL instead of 3 bytes
CALL instruction. If it is frequently called, it is more useful to
save program byte length.
External Interrupt 2
External Interrupt 1
External Interrupt 0
Table Call (TCALL) causes the CPU to jump to each TCALL ad-
dress, where it commences the execution of the service routine.
The Table Call service area spaces 2-byte for every TCALL:
0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in
Figure 8-7.
RESET
Figure 8-6 Interrupt Vector Area
Example: Usage of TCALL
LDA
#5
TCALL 0FH
;
;
;
1BYTE INSTRUCTION
INSTEAD OF 3 BYTES
NORMAL CALL
:
:
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
;
FUNC_B: LDA
LRG1
2
1
RET
;
;TABLE CALL ADD. AREA
;
ORG
DW
DW
0FFC0H
FUNC_A
FUNC_B
;TCALL ADDRESS AREA
MAR. 2005 Ver 0.2
23
MC80F0208/16/24
Preliminary
Address
Program Memory
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
PCALL Area Memory
Address
0FF00
0FFC0
H
H
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
TCALL 8
PCALL Area
(256 Bytes)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
0FFFF
H
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL→ rel
TCALL→ n
4F35
PCALL 35H
4A
TCALL 4
4A
01001010
4F
35
Reverse
➊
~
~
~
~
~
~
~
~
PC: 11111111 11010110
FH FH DH 6H
NEXT
0D125
H
0FF00
H
➊
0FF00
➊
0FF35
NEXT
H
H
0FFD6
0FFD7
25
H
H
D1
0FFFF
0FFFF
H
H
24
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Example: The usage software example of Vector address for MC80F0208/16/24 .
;Interrupt Vector Table
ORG
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
0FFE0H
BIT_TIMER
WATCH_WDT
ADC
TIMER4
TIMER3
TIMER2
TIMER1
TIMER0
SIO
; BIT
; WDT & WT
; AD Converter
; Timer-4
; Timer-3
; Timer-2
; Timer-1
; Timer-0
; Serial Interface
; UART1 Rx/Tx
; UART0 Rx/Tx
; Ext Int.3
; Ext Int.2
; Ext Int.1
; Ext Int.0
; Reset
UART1
UART0
INT3
INT2
INT1
INT0
RESET
ORG
0A000H
; 24K bytes ROM Start address
;*******************************************
;
MAIN
PROGRAM
*
;*******************************************
RESET:
DI
;Disable All Interrupt
RAMCLEAR:
LDX
LDY
#00H
#0
;USER RAM START ADDRESS LOAD !
RAMCLR1:
LDA
STA
#00H
;Page0 Ram Clear(0000h ~ 00BFh)
{X}+
;
;
;
CMPX #0C0H
BNE
RAMCLR1
INC
Y
!RPR
;
STY
;Page1 Ram Select
;G-FLAG SET !
SETG
LDX
#00H
RAMCLR2:
LDA
STA
#00H
{X}+
CMPX #00H
BNE
RAMCLR2
INC
Y
CMPY #4
BCS
RAMCLR3
;Page1 ~ Page3 Clear(0100h ~ 03FFh)
STY
SETG
!RPR
BRA
RAMCLR2
RAMCLR3:
STY
SETG
LDA
STA
!RPR
;Page4 Clear(0400h ~ 043Fh)
#00H
{X}+
;A <-- #0
;
CMPX #40H
BNE
RAMCLR3
CLRG
;G-FLAG CLEAR !
LDX
TXSP
#0FFH
;Initial Stack Point (01FFh)
MAR. 2005 Ver 0.2
25
MC80F0208/16/24
8.3 Data Memory
Preliminary
Figure 8-8 shows the internal Data Memory space available. Data
Memory is divided into three groups, a user RAM, control regis-
ters, and Stack memory.
Control Registers
The control registers are used by the CPU and Peripheral function
blocks for controlling the desired operation of the device. There-
fore these registers contain control and status bits for the interrupt
system, the timer/ counters, analog to digital converters and I/O
ports. The control registers are in address range of 0C0H to 0FFH.
0000
H
User Memory
(192Bytes)
Note that unoccupied addresses may not be implemented on the
chip. Read accesses to these addresses will in general return ran-
dom data, and write accesses will have an indeterminate effect.
PAGE0
00BF
00C0
H
H
(When “G-flag=0”,
this page0 is selected)
Control
Registers
00FF
H
H
0100
More detailed informations of each register are explained in each
peripheral section.
User Memory
or Stack Area
(256Bytes)
PAGE1
PAGE2
Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write instruc-
tion. Use byte manipulation instruction, for example “LDM”.
01FF
H
H
0200
User Memory
(256Bytes)
Example; To write at CKCTLR
02FF
0300
H
H
LDM
CLCTLR,#0AH;Divide ratio(÷32)
User Memory
(256Bytes)
03BF
03C0
H
H
PAGE3
PAGE4
Stack Area
03FF
H
H
The stack provides the area where the return address is saved be-
fore a jump is performed during the processing routine at the ex-
ecution of a subroutine call instruction or the acceptance of an
interrupt.
0400
User Memory
(64Bytes)
043F
H
H
0440
Not Used
When returning from the processing routine, executing the sub-
routine return instruction [RET] restores the contents of the pro-
gram counter from the stack; executing the interrupt return
instruction [RETI] restores the contents of the program counter
and flags.
04FF
H
Figure 8-8 Data Memory Map
User Memory
The save/restore locations in the stack are determined by the
stack pointed (SP). The SP is automatically decreased after the
saving, and increased before the restoring. This means the value
of the SP indicates the stack location number for the next save.
Refer to Figure 8-4 on page 22.
The MC80F0208/16/24 has 1024 × 8 bits for the user memory
(RAM). RAM pages are selected by RPR (See Figure 8-9).
Note: After setting RPR(RAM Page Select Register), be
sure to execute SETG instruction. When executing CLRG
instruction, be selected PAGE0 regardless of RPR.
R/W R/W R/W
7
-
6
-
5
4
-
3
-
2
1
0
ADDRESS: 0E1
INITIAL VALUE: ---- -000
H
-
RPR2 RPR1 RPR0
RPR
B
System clock source select
000 : PAGE0
001 : PAGE1
010 : PAGE2
011 : PAGE3
100 : PAGE4
Figure 8-9 RPR(RAM Page Select Register)
26
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Initial Value
Addressing
Mode
Address
Register Name
R0 port data register
Symbol
R/W
7
6 5 4 3 2 1 0
byte, bit1
00C0
R0
R/W 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
byte2
byte, bit
byte
00C1
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9
00CA
00CB
00CC
00CD
00CE
00CF
00D0
R0 port I/O direction register
R1 port data register
R0IO
R1
W
R1 port I/O direction register
R1IO
W
Reserved
Reserved
R3
R3 port data register
R/W 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0
byte, bit
byte
R3 port I/O direction register
R4 port data register
R3IO
W
R4
byte, bit
byte
R4 port I/O direction register
R5 port data register
R4IO
W
R/W
W
0 0 0 0 0 0 0 0
R5
-
-
-
-
-
-
0 0 0 0 0
0 0 0 0 0
byte, bit
byte
R5 port I/O direction register
R6 port data register
R5IO
R6
R/W 0 0 0 0 0 0 0 0
byte, bit
byte
R6 port I/O direction register
R6IO
W
0 0 0 0 0 0 0 0
Reserved
Reserved
TM0
Timer 0 mode control register
Timer 0 register
R/W
R
-
-
0 0 0 0 0 0
byte, bit
byte
T0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
00D1
Timer 0 data register
TDR0
CDR0
TM1
W
Timer 0 capture data register
Timer 1 mode control register
Timer 1 data register
R
00D2
00D3
R/W 0 0 0 0 0 0 0 0
byte, bit
byte
TDR1
T1
W
R
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Timer 1 register
00D4
byte
Timer 1 capture data register
CDR1
Reserved
TM2
R
00D5
00D6
Timer 2 mode control register
Timer 2 register
R/W
R
-
-
0 0 0 0 0 0
byte, bit
byte
T2
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
00D7
Timer 2 data register
TDR2
CDR2
TM3
W
Timer 2 capture data register
Timer 3 mode control register
Timer 3 data register
R
00D8
00D9
R/W 0 0 0 0 0 0 0 0
byte, bit
byte
TDR3
T3PPR
W
W
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
Timer 3 PWM period register
Table 8-1 Control Registers
MAR. 2005 Ver 0.2
27
MC80F0208/16/24
Preliminary
Initial Value
Addressing
Mode
Address
Register Name
Symbol
R/W
7
6 5 4 3 2 1 0
Timer 3 register
Timer 3 PWM duty register
T3
T3PDR
CDR3
R
0 0 0 0 0 0 0 0
00DA
R/W 0 0 0 0 0 0 0 0
byte
Timer 3 capture data register
Timer 3 PWM high register
Timer 4 mode control register
Timer 4 low register
R
W
0 0 0 0 0 0 0 0
00DB
00DC
T3PWHR
TM4
-
-
-
-
-
-
0 0 0 0
byte
R/W
R
0 0 0 0 0 0
byte, bit
T4L
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
00DD
00DE
Timer 4 low data register
Timer 4 capture low data register
Timer 4 high register
TDR4L
CDR4L
T4H
W
byte
byte
R
R
Timer 4 high data register
Timer 4 capture high data register
Interrupt flag register
TDR4H
CDR4H
IFR
W
R
00DF
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
R/W
W
-
-
0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0
byte, bit
byte
Buzzer driver register
BUZR
RAM page selection register
SIO mode control register
SIO data shift register
RPR
R/W
-
-
-
-
-
byte, bit
byte, bit
byte, bit
SIOM
R/W 0 0 0 0 0 0 0 1
R/W Undefined
SIOR
Reserved
Reserved
ASIMR0
ASISR0
UART0 mode register
UART0 status register
R/W 0 0 0 0
-
-
0 0
-
byte, bit
byte
R
-
-
-
-
-
0 0 0
UART0 Baud rate generator control register
UART0 Receive buffer register
UART0 Transmit shift register
Interrupt enable register high
Interrupt enable register low
Interrupt request register high
Interrupt request register low
Interrupt edge selection register
A/D converter mode control register
A/D converter result high register
A/D converter result low register
Basic interval timer register
BRGCR0 R/W
0 0 1 0 0 0 0
byte, bit
RXR0
TXR0
R
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
00E9
byte
W
00EA
00EB
00EC
00ED
00EE
00EF
00F0
00F1
IENH
R/W 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 1
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
IENL
IRQH
IRQL
IEDS
ADCM
ADCRH
ADCRL
BITR
R(W) 0 1
Undefined
Undefined
R
R
byte
Undefined
00F2
00F3
byte
Clock control register
CKCTLR
W
0
-
0 1 0 1 1 1
Reserved
Table 8-1 Control Registers
28
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Initial Value
Addressing
Mode
Address
Register Name
Watch dog timer register
Symbol
R/W
7
6 5 4 3 2 1 0
WDTR
WDTDR
SSCR
W
R
0 1 1 1 1 1 1 1
Undefined
00F4
byte
Watch dog timer data register
Stop & sleep mode control register
Watch timer mode register
PFD control register
00F5
00F6
00F7
00F8
00F9
00FA
00FB
00FC
00FD
00FE
00FF
0EE6
0EE7
0EE8
W
0 0 0 0 0 0 0 0
byte
byte, bit
byte, bit
byte
WTMR
PFDR
R/W
R/W
W
0
-
-
-
-
-
0 0 0 0 0
0 0 0
-
-
Port selection register 0
PSR0
0 0 0 0 0 0 0 0
0 0 0 0
Port selection register 1
PSR1
W
-
-
-
-
byte
Reserved
Reserved
PU0
Pull-up selection register 0
Pull-up selection register 1
Pull-up selection register 4
W
W
W
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
byte
byte
byte
PU1
PU4
Reserved
ASIMR1
ASISR1
UART1 mode register
UART1 status register
R/W 0 0 0 0
-
-
0 0
-
byte, bit
byte
R
-
-
-
-
-
0 0 0
UART1 Baud rate generator control register
UART1 Receive buffer register
BRGCR1 R/W
0 0 1 0 0 0 0
byte, bit
RXR1
TXR1
R
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0EE9
byte
UART1 Transmit shift register
W
Table 8-1 Control Registers
1.
2.
The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction.
Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated.
The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation
instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,
content of other seven bits are may varied to unwanted value.
3.
The UART1 control register ASIMR1,ASISR1, BRGCR1,RXR1 and TXR1 are located at EE6H ~ EE9H address.
These address must be accessed(read and written) by absolute addressing manipulation instruction.
*The mark of ‘-’ means this bit location is reserved.
MAR. 2005 Ver 0.2
29
MC80F0208/16/24
Preliminary
Bit 7
Address
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0C8H
0C9H
0CAH
0CBH
0CCH
0CDH
0CEH
0CFH
0D0H
Name
R0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R0 Port Data Register
R0 Port Direction Register
R1 Port Data Register
R1 Port Direction Register
Reserved
R0IO
R1
R1IO
Reserved
R3
R3 Port Data Register
R3 Port Direction Register
R4 Port Data Register
R4 Port Direction Register
R3IO
R4
R4IO
R5
-
-
-
-
-
-
R5 Port Data Register
R5IO
R6
R5 Port Direction Register
R6 Port Data Register
R6 Port Direction Register
Reserved
R6IO
Reserved
TM0
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T1CN
T0ST
T1ST
T0/TDR0/
CDR0
0D1H
Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register
0D2H
0D3H
0D4H
0D5H
0D6H
TM1
-
16BIT
-
CAP1
T1CK1
T1CK0
TDR1
Timer1 Data Register
T1/CDR1 Timer1 Register / Timer1 Capture Data Register
PWM1HR
TM2
-
-
-
-
-
Timer1 PWM High Register
-
CAP2
T2CK2
T2CK1
T2CK0
T2CN
T2ST
T3ST
T2/TDR2/
CDR2
0D7H
0D8H
0D9H
Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register
POL 16BIT PWM3E CAP3 T3CK1 T3CK0
Timer3 Data Register / Timer3 PWM Period Register
TM3
T3CN
TDR3/
T3PPR
T3/CDR3/
T3PDR
0DAH
Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register
0DBH
0DCH
PWM3HR
TM4
-
-
-
-
-
Timer3 PWM High Register
T4CK1 T4CK0 T4CN
-
CAP4
T4CK2
T4ST
T4L/
0DDH
TDR4L/
CDR4L
Timer4 Register Low / Timer4 Data Register Low / Timer4 Capture Data Register Low
Table 8-2 Control Register Function Description
30
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Bit 7
Timer4 Register High / Timer4 Data Register High / Timer4 Capture Data Register High
Address
Name
T4H/
TDR4H/
CDR4H
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0DEH
0DFH
0E0H
0E1H
0E2H
0E3H
0E4H
0E5H
0E6H
0E7H
0E8H
IFR
-
BUCK1
-
-
RX0IOF
BUR5
-
TX0IOF
BUR4
-
RX1IOF
BUR3
-
TX1IOF
BUR2
RPR2
SCK0
WTIOF
BUR1
RPR1
SIOST
WDTIOF
BUR0
BUZR
RPR
SIOM
SIOR
BUCK0
-
RPR0
POL
IOSW
SM1
SM0
SCK1
SIOSF
SIO Data Shift Register
Reserved
Reserved
ASIMR0
ASISR0
BRGCR0
RXR0
TXE0
RXE0
-
PS01
-
PS00
-
-
SL0
PE0
ISRM0
FE0
-
-
-
-
OVE0
MLD00
TPS02
TPS01
TPS00
MLD03
MLD02
MLD01
UART0 Receive Buffer Register
UART0 Transmit Shift Register
0E9H
TXR0
0EAH
0EBH
0ECH
0EDH
0EEH
0EFH
0F0H
0F1H
IENH
INT0E
T1E
INT1E
T2E
INT2E
T3E
INT3E
T4E
RXE
ADCE
RXIF
ADCIF
IED1H
ADS1
-
TXE
WDTE
TXIF
WDTIF
IED1L
ADS0
-
SIOE
WTE
T0E
BITE
T0IF
IENL
IRQH
INT0IF
T1IF
INT1IF
T2IF
INT2IF
T3IF
INT3IF
T4IF
IED2L
ADS2
-
SIOIF
WTIF
IED0H
ADST
IRQL
BITIF
IED0L
ADSF
IEDS
IED3H
ADEN
PSSEL1
IED3L
ADCK
PSSEL0
IED2H
ADS3
ADC8
ADCM
ADCRH
ADCRL
ADC Result Reg. High
ADC Result Register Low
Basic Interval Timer Data Register
BITR1
0F2H
CKCTLR1
ADRST
-
RCWDT
WDTON
BTCL
BTS2
BTS1
BTS0
0F3H
0F4H
Reserved
WDTR
WDTDR
SSCR
WTMR
PFDR
PSR0
WDTCL 7-bit Watchdog Timer Register
Watchdog Timer Data Register (Counter Register)
Stop & Sleep Mode Control Register
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
WTEN
-
-
-
-
-
-
WTIN2
WTIN1
-
WTIN0
PFDEN
INT2E
BUZO
WTCK1
PFDM
INT1E
-
WTCK0
PFDS
INT0E
-
-
EC1E
-
-
EC0E
-
PWM3O
-
INT3E
XTEN
PSR1
Reserved
Reserved
PU0
PU1
PU4
R0 Pull-up Selection Register
R1 Pull-up Selection Register
R4 Pull-up Selection Register
Table 8-2 Control Register Function Description
MAR. 2005 Ver 0.2
31
MC80F0208/16/24
Preliminary
Bit 7
Address
0FFH
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
EE6H2
EE7H2
EE8H2
ASIMR1
ASISR1
TXE1
RXE1
-
PS11
-
PS10
-
-
SL1
PE1
ISRM1
FE1
-
-
-
-
OVE1
MLD10
BRGCR1
RXR1
TPS12
TPS11
TPS10
MLD13
MLD12
MLD11
UART1 Receive Buffer Register
UART1 Transmit Shift Register
EE9H2
TXR1
Table 8-2 Control Register Function Description
1. The register BITR and CKCTLR are located at same address. Address F2H is read as BITR, written to CKCTLR.
Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be
accessed by register operation instruction such as "LDM dp,#imm".
2. The UART1 control register ASIMR1,ASISR1, BRGCR1,RXR1 and TXR1 are located at EE6H ~ EE9H address.
These address must be accessed(read and written) by absolute addressing manipulation instruction.
8.4 Addressing Mode
The MC800 series MCU uses six addressing modes;
• Register addressing
When G-flag is 1, then RAM address is defined by 16-bit address
which is composed of 8-bit RAM paging register (RPR) and 8-bit
immediate data.
• Immediate addressing
Example: G=1
• Direct page addressing
• Absolute addressing
E45535 LDM
35H,#55H
• Indexed addressing
• Register-indirect addressing
data
0135H
data ← 55H
~
~
~
~
8.4.1 Register Addressing
➊
➊
0F100H
0F101H
0F102H
E4
55
35
Register addressing accesses the A, X, Y, C and PSW.
8.4.2 Immediate Addressing → #imm
In this mode, second byte (operand) is accessed as a data imme-
diately.
Example:
8.4.3 Direct Page Addressing → dp
In this mode, a address is specified within direct page.
Example; G=0
0435
ADC
#35H
MEMORY
04
35
A+35H+C → A
32
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
C535
LDA
35H
;A ←RAM[35H]
983501 INC
!0135H
;A ←ROM[135H]
35H
data
135H
data
➊
➊
➊
~
~
~
~
~
~
~
data → A
~
data+1 → data
➊
0E550H
0E551H
C5
35
0F100H
0F101H
0F102H
98
35
01
➊
address: 0135
8.4.5 Indexed Addressing
8.4.4 Absolute Addressing → !abs
Absolute addressing sets corresponding memory data to Data, i.e.
second byte (Operand I) of command becomes lower level ad-
dress and third byte (Operand II) becomes upper level address.
With 3 bytes command, it is possible to access to whole memory
area.
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H, G=1
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR,
SBC, STA, STX, STY
D4
LDA
{X}
;ACC←RAM[X].
Example;
0735F0 ADC
!0F035H
;A ←ROM[0F035H]
115H
data
➊
data → A
~
~
~
0F035H
data
~
➊
➊
~
~
~
~
A+data+C → A
D4
0E550H
➊
0F100H
0F101H
0F102H
07
35
F0
address: 0F035
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by the X
register and the content of X is increased by 1.
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
LDA, STA
Example; Addressing accesses the address 0135H regardless of
G-flag.
Example; G=0, X=35H
DB
LDA
{X}+
MAR. 2005 Ver 0.2
33
MC80F0208/16/24
Preliminary
D500FA LDA
!0FA00H+Y
35H
data
➊
0F100H
0F101H
0F102H
D5
00
FA
data → A
36H → X
➊
~
~
~
~
➊
0FA00H+55H=0FA55H
DB
~
~
~
~
➊
0FA55H
data
data → A
➊
X indexed direct page (8 bit offset) → dp+X
8.4.6 Indirect Addressing
Direct page indirect → [dp]
This address value is the second byte (Operand) of command plus
the data of X-register. And it assigns the memory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY,
XMA, ASL, DEC, INC, LSR, ROL, ROR
Assigns data address to use for accomplishing command which
sets memory data (or pair memory) by Operand.
Also index can be used with Index register X,Y.
Example; G=0, X=0F5H
C645
LDA
45H+X
JMP, CALL
Example; G=0
3F35
JMP
[35H]
3AH
data
➊
35H
36H
0A
E3
~
~
~
data → A
➊
~
0E550H
0E551H
C6
45
➊
➊
~
~
~
~
45H+0F5H=13AH
➊
0E30AH
0FA00H
NEXT
jump to
address 0E30AH
~
~
~
~
3F
35
Y indexed direct page (8 bit offset) → dp+Y
This address value is the second byte (Operand) of command plus
the data of Y-register, which assigns Memory in Direct page.
This is same with above (2). Use Y register instead of X.
X indexed indirect → [dp+X]
Processes memory data as Data, assigned by 16-bit pair memory
which is determined by pair data [dp+X+1][dp+X] Operand plus
X-register data in Direct page.
Y indexed absolute → !abs+Y
Sets the value of 16-bit absolute address plus Y-register data as
Memory.This addressing mode can specify memory in whole ar-
ea.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, X=10H
Example; Y=55H
34
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
1625
ADC
[25H+X]
Absolute indirect → [!abs]
The program jumps to address specified by 16-bit absolute ad-
dress.
35H
05
JMP
36H
E0
Example; G=0
➊0E005H
~
~
~
~
1F25E0 JMP
[!0C025H]
➊
25 + X(10) = 35H
0E005H
data
~
~
~
~
PROGRAM MEMORY
0FA00H
16
25
0E025H
0E026H
25
➊ A + data + C → A
E7
➊
~
~
~
~
jump to
address 0E30AH
Y indexed indirect → [dp]+Y
0E725H
0FA00H
NEXT
➊
Processes memory data as Data, assigned by the data [dp+1][dp]
of 16-bit pair memory paired by Operand in Direct page plus Y-
register data.
~
~
~
~
1F
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; G=0, Y=10H
25
E0
1725
ADC
[25H]+Y
25H
26H
05
E0
➊
~
~
~
~
➊
0E005H + Y(10)
= 0E015H
0E015H
0FA00H
data
~
~
~
~
17
25
➊
A + data + C → A
MAR. 2005 Ver 0.2
35
MC80F0208/16/24
9. I/O PORTS
Preliminary
The MC80F0208/16/24 has six ports (R0, R1, R3, R4, R5 and
R6). These ports pins may be multiplexed with an alternate func-
tion for the peripheral features on the device. R3 port can drive
maximum 20mA of high current in output low state, so it can di-
rectly drive LED device.
ADDRESS: 0C0
RESET VALUE: 00
H
R0 Data Register
H
R07 R06 R05 R04 R03 R02 R01 R00
Input / Output data
R0
All pins have data direction registers which can define these ports
as output or input. A “1” in the port direction register configure
the corresponding port pin as output. Conversely, write “0” to the
corresponding bit to specify it as input pin. For example, to use
the even numbered bit of R0 as output ports and the odd num-
bered bits as input ports, write “55H” to address 0C1H (R0 port
direction register) during initial setting as shown in Figure 9-1.
ADDRESS: 0C1
RESET VALUE: 00
H
R0 Direction Register
R0IO
H
All the port direction registers in the MC80F0208/16/24 have 0
written to them by reset function. On the other hand, its initial sta-
tus is input.
Port Direction
0: Input
1: Output
R0 Pull-up
Selection Register
ADDRESS: 0FC
RESET VALUE: 00
H
H
WRITE “55 ” TO PORT R0 DIRECTION REGISTER
H
PU0
0C0
0C1
0C2
0C3
BIT
R0 data
R0 direction
R1 data
0 1 0 1 0 1 0 1
7 6 5 4 3 2 1 0
H
H
Pull-up Resister Selection
H
H
0: Disable
1: Enable
R1 direction
I
O I O I O I O PORT
7 6 5 4 3 2 1 0
I: INPUT PORT
O: OUTPUT PORT
R1 and R1IO register: R1 is an 5-bit CMOS bidirectional I/O
port (address 0C2H). Each I/O pin can independently used as an
input or an output through the R1IO register (address 0C3H). The
on-chip pull-up resistor can be connected to them in 1-bit units
with a pull-up selection register 1 (PU1).
Figure 9-1 Example of port I/O assignment
R0 and R0IO register: R0 is an 8-bit CMOS bidirectional I/O
port (address 0C0H). Each I/O pin can independently used as an
input or an output through the R0IO register (address 0C1H). The
on-chip pull-up resistor can be connected to them in 1-bit units
with a pull-up selection register 0 (PU0).
In addition, Port R1 is multiplexed with various special features.
The control register PSR0 (address 0F8H) and PSR1 (address
0F9H) controls the selection of alternate function. After reset, this
value is “0”, port may be used as normal I/O port.
To use alternate function such as external interrupt, event counter
input or timer clock output, write “1” in the corresponding bit of
PSR0 or PSR1. Regardless of the direction register R1IO, PSR0
or PSR1 is selected to use as alternate functions, port pin can be
used as a corresponding alternate features.
Port Pin
Alternate Function
R10
R11
R12
R13
R15
INT0 (External Interrupt 0)
INT1 (External Interrupt 1)
INT2 (External Interrupt 2)
BUZO (Square-wave output for buzzer)
EC0 (Event counter input to Counter 0)
36
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
port (address 0C6H). Each I/O pin can independently used as an
input or an output through the R3IO register (address 0C7H).
In addition, Port R3 is multiplexed with various special features.
After reset, this value is “0”, port may be used as normal I/O port.
ADDRESS: 0C2
RESET VALUE: 00
H
R1 Data Register
H
-
-
R15
-
R13 R12 R11 R10
R1
Input / Output data
Port Pin
Alternate Function
R30
R31
R32
R33
-
ACLK1 (UART1 clock input)
RxD1 (UART1 data input)
TxD1(UART1 data output)
ADDRESS: 0C3
RESET VALUE: 00
H
R1 Direction Register
H
-
-
-
R1IO
Port Direction
0: Input
1: Output
ADDRESS: 0C6
RESET VALUE: 00
H
R3 Data Register
H
R1 Pull-up
Selection Register
ADDRESS: 0FD
RESET VALUE: 00
H
-
-
-
-
R33 R32 R31 R30
R3
H
-
-
-
PU1
Input / Output data
Pull-up Resister Selection
0: Disable
1: Enable
ADDRESS: 0C7
RESET VALUE: 00
H
R3 Direction Register
H
-
-
-
-
R3IO
ADDRESS: 0F8
H
RESET VALUE: 0-00 0000
B
Port Direction
0: Input
PWM3O
EC1E EC0E
INT3E
INT1E INT0E
INT2E
-
PSR0
1: Output
Port / INT Selection
0: R10, R11,R12, R50
1: INT0, INT1,INT2, INT3
R4 and R4IO register: R4 is an 8-bit CMOS bidirectional I/O
port (address 0C8H). Each I/O pin can independently used as an
input or an output through the R4IO register (address 0C9H). The
on-chip pull-up resistor can be connected to them in 1-bit units
with a pull-up selection register 4 (PU4).
Port / EC Selection
0: R15, R51
1: EC0, EC1
Port / PWM3 Selection
0: R54
1: PWM3O/T3O port
In addition, Port R4 is multiplexed with various special features.
After reset, this value is “0”, port may be used as normal I/O port.
ADDRESS: 0F9
H
RESET VALUE: ---- -0--
B
-
-
-
-
-
-
-
BUZO
Port Pin
Alternate Function
PSR1
R40
R41
R42
R43
R44
R45
R46
R47
-
-
R13/BUZO Selection
0: R13 port (Turn off buzzer)
1: BUZO port (Turn on buzzer)
SCK (SIO clock input/output)
SI (SIO data input)
SO (Serial1 data output)
ACLK0 (UART0 clock input)
RxD0 (UART0 data input)
TxD0 (UART0 data output)
R3 and R3IO register: R3 is an 4-bit CMOS bidirectional I/O
MAR. 2005 Ver 0.2
37
MC80F0208/16/24
Preliminary
ADDRESS: 0CA
RESET VALUE: ---00000
ADDRESS: 0C8
RESET VALUE: 00
H
H
R5 Data Register
R4 Data Register
B
H
-
-
-
R54
-
-
R51 R50
R47 R46 R45 R44 R43 R42 R41 R40
Input / Output data
R5
R4
Input / Output data
ADDRESS: 0CB
ADDRESS: 0C9
H
H
R5 Direction Register
R4 Direction Register
R4IO
RESET VALUE: ---00000
RESET VALUE: 00
B
H
-
-
-
- -
R5IO
Port Direction
0: Input
1: Output
Port Direction
0: Input
1: Output
ADDRESS: 0F8
RESET VALUE: 0-00 0000
H
R4 Pull-up
ADDRESS: 0FE
RESET VALUE: 00
H
B
Selection Register
H
PWM3O
EC1E EC0E
INT2E INT1E INT0E
INT3E
-
PSR0
PU4
Port / INT Selection
Pull-up Resister Selection
0: R10, R11, R12, R50
1: INT0, INT1, INT2, INT3
0: Disable
1: Enable
Port / EC Selection
0: R15, R51
1: EC0, EC1
R5 and R5IO register: R5 is an 3-bit CMOS bidirectional I/O
port (address 0CAH). Each I/O pin can independently used as an
input or an output through the R5IO register (address 0CBH).
Port / PWM3 Selection
0: R54
1: PWM3O/T3O port
In addition, Port R5 is multiplexed with various special features.
The control register PSR0 (address 0F8H) and PSR1 (address
0F9H) controls the selection of alternate function. After reset, this
value is “0”, port may be used as normal I/O port.
R6 and R6IO register: R6 is an 8-bit CMOS bidirectional I/O
port (address 0CCH). Each I/O pin can independently used as an
input or an output through the R6IO register (address 0CDH).
To use alternate function such as external interrupt, event counter
input, timer clock output or PWM output, write “1” in the corre-
sponding bit of PSR0 or PSR1. Regardless of the direction regis-
ter R5IO, PSR0 or PSR1 is selected to use as alternate functions,
port pin can be used as a corresponding alternate features.
In addition, Port R6 is multiplexed with AD converter analog in-
put AN0~AN7.
Port Pin
Alternate Function
Port Pin
Alternate Function
R60
R61
R62
R63
R64
R65
R66
R67
AN0 (ADC input channel 0)
AN1 (ADC input channel 1)
AN2 (ADC input channel 2)
AN3 (ADC input channel 3)
AN4 (ADC input channel 4)
AN5 (ADC input channel 5)
AN6 (ADC input channel 6)
AN7 (ADC input channel 7)
R50
R51
R54
INT3 (External Interrupt 3)
EC1 (Event counter input to Counter 2)
PWM3O (PWM3/T3O output)
R6IO (address CDH) controls the direction of the R6 pins, except
when they are being used as analog input channels. The user don’t
have to keep the pins configured as inputs when using them as an-
alog input channels, because the analog input mode is activated
by the setting of ADC enable bit of ADCM register and ADC
38
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
channel selection
.
ADDRESS: 0CC
RESET VALUE: 00
H
R6 Data Register
H
R67 R66 R65 R64 R63 R62 R61 R60
Input / Output data
R6
ADDRESS: 0CD
RESET VALUE: 00
H
R6 Direction Register
R6IO
H
Port Direction
0: Input
1: Output
MAR. 2005 Ver 0.2
39
MC80F0208/16/24
Preliminary
10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the basic
clock pulses which provide the system clock to be supplied to the
CPU and the peripheral hardware. It contains main-frequency
clock oscillator. The system clock operation can be easily ob-
tained by attaching a crystal or a ceramic resonator between the
XIN and XOUT pin, respectively. The system clock can also be ob-
tained from the external oscillator. In this case, it is necessary to
input a external clock signal to the XIN pin and open the XOUT
pin. There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must be observed.
To the peripheral block, the clock among the not-divided original
clock, clocks divided by 1, 2, 4,..., up to 4096 can be provided.
Peripheral clock is enabled or disabled by STOP instruction. The
peripheral clock is controlled by clock control register
(CKCTLR). See "11. BASIC INTERVAL TIMER" on page 41
for details.
STOP
SLEEP
Main OSC
Stop
Clock Pulse
Internal
fEX
XIN
Generator
OSC
Circuit
system clock
(÷2)
XOUT
PRESCALER
PS11 PS12
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
÷1
÷2
÷4
÷8
÷16
÷32
÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096
Peripheral clock
fEX (Hz)
PS0
4M
PS1
2M
PS2
1M
1u
PS3
PS4
PS5
PS6
PS7
PS8
PS9
7.183K 3.906K
128u 256u
PS10
PS11
1.953K
512u
PS12
976
Frequency
period
500K
2u
250K
4u
125K
8u
62.5K
16u
31.25K 15.63K
4M
1.024m
250n
500n
32u
64u
Figure 10-1 Block Diagram of Clock Generator
40
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
11. BASIC INTERVAL TIMER
The MC80F0208/16/24 has one 8-bit Basic Interval Timer that is
free-run and can not stop. Block diagram is shown in Figure 11-
1. In addition, the Basic Interval Timer generates the time base
for watchdog timer counting. It also provides a Basic interval tim-
er interrupt (BITIF).
cleared to "0" and restart to count-up. The bit BTCL becomes "0"
after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit RCWDT
of CKCTLR, it goes into the internal RC oscillated watchdog tim-
er mode. In this mode, all of the block is halted except the internal
RC oscillator, Basic Interval Timer and Watchdog Timer. More
detail informations are explained in Power Saving Function. The
bit WDTON decides Watchdog Timer or the normal 7-bit timer.
Source clock can be selected by lower 3 bits of CKCTLR.
The 8-bit Basic interval timer register (BITR) is increased every
internal count pulse which is divided by prescaler. Since prescal-
er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024
of the oscillator frequency. As the count overflow from FFH to
00H, this overflow causes the interrupt to be generated. The Basic
Interval Timer is controlled by the clock control register
(CKCTLR) shown in Figure 10-2.
BITR and CKCTLR are located at same address, and address
0F2H is read as a BITR, and written to CKCTLR.
When write "1" to bit BTCL of CKCTLR, BITR register is
Internal RC OSC
RCWDT
÷8
8-bit up-counter
Basic Interval
source
clock
÷16
1
0
Timer Interrupt
overflow
÷32
BITIF
BITR
÷64
MUX
÷128
÷256
÷512
÷1024
[0F2 ]
H
To Watchdog timer (WDTCK)
XIN PIN
clear
3
Select Input clock
BTS[2:0]
RCWDT
BTCL
[0F2 ]
H
CKCTLR
Basic Interval Timer
clock control register
Read
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Interrupt (overflow) Period (ms)
CKCTLR
[2:0]
Source clock
XIN÷8
@ fXIN = 8MHz
f
f
f
f
f
f
f
f
000
001
010
011
100
101
110
111
0.256
0.512
1.024
2.048
4.096
8.192
16.384
32.768
XIN÷16
XIN÷32
XIN÷64
XIN÷128
XIN÷256
XIN÷512
XIN÷1024
Table 11-1 Basic Interval Timer Interrupt Period
MAR. 2005 Ver 0.2
41
MC80F0208/16/24
Preliminary
7
ADRST
6
-
5
4
3
2
1
0
ADDRESS: 0F2
INITIAL VALUE: 0-01 0111
H
WDTON
RCWDT
BTCL BTS2 BTS1 BTS0
CKCTLR
B
Basic Interval Timer source clock select
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
÷ 8
XIN
XIN
XIN
XIN
XIN
XIN
XIN
XIN
÷ 16
÷ 32
÷ 64
÷ 128
÷ 256
÷ 512
÷ 1024
Clear bit
0: Normal operation (free-run)
1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically
after one machine cycle, and starts counting.
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
Watchdog timer Enable bit
0: Operate as 7-bit Timer
1: Enable Watchdog Timer operation
See the section “Watchdog Timer”.
RC Watchdog Selection bit
0: Disable Internal RC Watchdog Timer
1: Enable Internal RC Watchdog Timer
Address Trap Reset Selection
0: Enable Address Fail Reset
1: Disable Address Fail Reset
7
6
5
4
3
2
1
0
ADDRESS: 0F2
INITIAL VALUE: Undefined
H
BITR
8-BIT FREE-RUN BINARY COUNTER
Figure 11-2 BITR: Basic Interval Timer Mode Register
Example 1:
Example 2:
Interrupt request flag is generated every 8.192ms at 4MHz.
Interrupt request flag is generated every 8.192ms at 8MHz.
:
:
LDM
CKCTLR,#1BH
LDM
CKCTLR,#1CH
SET1 BITE
EI
:
SET1 BITE
EI
:
42
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
12. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction such as
endless looping caused by noise or the like, and resumes the CPU
to the normal state. The watchdog timer signal for detecting mal-
function can be selected either a reset CPU or a interrupt request.
The RC oscillated watchdog timer is activated by setting the bit
RCWDT as shown below.
LDM
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH; enable the RC-OSC WDT
WDTR,#0FFH ; set the WDT period
SSCR, #5AH ;ready for STOP mode
; enter the STOP mode
When the watchdog timer is not being used for malfunction de-
tection, it can be used as a timer to generate an interrupt at fixed
intervals.
; RC-OSC WDT running
The watchdog timer has two types of clock source. The first type
is an on-chip RC oscillator which does not require any external
components. This RC oscillator is separate from the external os-
cillator of the XIN pin. It means that the watchdog timer will run,
even if the clock on the XIN pin of the device has been stopped,
for example, by entering the STOP mode. The other type is a
prescaled system clock.
The RC-WDT oscillation period is vary with temperature, VDD
and process variations from part to part (approximately,
33~100uS). The following equation shows the RCWDT oscillat-
ed watchdog timer time-out.
The watchdog timer consists of 7-bit binary counter and the
watchdog timer data register. When the value of 7-bit binary
counter is equal to the lower 7 bits of WDTR, the interrupt re-
quest flag is generated. This can be used as Watchdog timer inter-
rupt or reset the CPU in accordance with the bit WDTON.
TRCWDT=CLKRCWDT×28×WDTR + (CLKRCWDT×28)/2
where, CLKRCWDT = 33~100uS
In addition, this watchdog timer can be used as a simple 7-bit tim-
er by interrupt WDTIF. The interval of watchdog timer interrupt
is decided by Basic Interval Timer. Interval equation is as below.
Note: Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer, after the bit WDTON set to
"1", maximum error of timer is depend on prescaler ratio of
Basic Interval Timer. The 7-bit binary counter is cleared by
setting WDTCL(bit7 of WDTR) and the WDTCL is cleared
automatically after 1 machine cycle.
T
WDT = (WDTR+1) × Interval of BIT
clear
Watchdog
Counter (7-bit)
clear
BASIC INTERVAL TIMER
OVERFLOW
Count
source
“0”
to reset CPU
“1”
comparator
enable
WDTON in CKCTLR [0F2 ]
H
7-bit compare data
WDTCL
WDTIF
7
Watchdog Timer interrupt
Watchdog Timer
Register
WDTR
[0F4 ]
H
Internal bus line
Figure 12-1 Block Diagram of Watchdog Timer
MAR. 2005 Ver 0.2
43
MC80F0208/16/24
Preliminary
counters unless the binary counter is cleared. At this time, when
Watchdog Timer Control
WDTON=1, a reset is generated, which drives the RESET pin to
low to reset the internal hardware. When WDTON=0, a watchdog
timer interrupt (WDTIF) is generated. The WDTON bit is in reg-
ister CLKCTLR.
Figure 12-2 shows the watchdog timer control register. The
watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the detection
time, selecting of output, and clearing of the binary counter.
Clearing the binary counter is repeated within the detection time.
The watchdog timer temporarily stops counting in the STOP
mode, and when the STOP mode is released, it automatically re-
starts (continues counting).
If the malfunction occurs for any cause, the watchdog timer out-
put will become active at the rising overflow from the binary
W
7
WDTCL
W
6
W
5
W
4
W
3
W
2
W
1
W
0
ADDRESS: 0F4
INITIAL VALUE: 0111 1111
H
WDTR
B
7-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
Figure 12-2 WDTR: Watchdog Timer Control Register
Example: Sets the watchdog timer detection time to 1 sec. at 4.194304MHz
LDM
LDM
CKCTLR,#3FH
WDTR,#08FH
;Select 1/1024 clock source, WDTON ← 1, Clear Counter
;Clear counter
LDM
:
WDTR,#08FH
WDTR,#08FH
WDTR,#08FH
:
Within WDT
detection time
:
:
LDM
:
;Clear counter
;Clear counter
:
Within WDT
detection time
:
:
LDM
Enable and Disable Watchdog
Watchdog Timer Interrupt
Watchdog timer is enabled by setting WDTON (bit 4 in
CKCTLR) to “1”. WDTON is initialized to “0” during reset and
it should be set to “1” to operate after reset is released.
The watchdog timer can be also used as a simple 7-bit timer by
clearing bit4 of CKCTLR to “0”. The interval of watchdog timer
interrupt is decided by Basic Interval Timer. Interval equation is
shown as below.
Example: Enables watchdog timer for Reset
TWDT = (WDTR+1) × Interval of BIT
:
LDM
:
CKCTLR,#xxx1_xxxxB;WDTON ← 1
:
The stack pointer (SP) should be initialized before using the
watchdog timer output as an interrupt source.
The watchdog timer is disabled by clearing bit 4 (WDTON) of
CKCTLR. The watchdog timer is halted in STOP mode and re-
starts automatically after STOP mode is released.
Example: 7-bit timer interrupt set up.
LDM
LDM
CKCTLR,#xxx0_xxxxB;WDTON ←0
WDTR,#8FH
;WDTCL ←1
:
44
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Source clock
BIT overflow
3
3
0
2
0
1
2
1
Binary-counter
Counter
Clear
Counter
Clear
3
n
WDTR
Match
Detect
WDTIF interrupt
WDTR ← “1000_0011B”
WDT reset
reset
Figure 12-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is generated,
which drives the RESET pin low to reset the internal hardware.
reset is generated in sub clock mode.
The WDTIF bit of IFR register is set when watchdog timer inter-
rupt is generated. (Refer to Figure 12-4)
The main clock oscillator also turns on when a watchdog timer
R/W R/W
R/W R/W
R/W R/W
ADDRESS: 0DF
INITIAL VALUE: --00 0000
H
-
-
RX0IOF TX0IOF RX1IOF TX1IOF WTIOF WDTIOF
IFR
B
LSB
MSB
NOTE1
WDT interrupt occurred flag
NOTE1
WT interrupt occurred flag
NOTE2
NOTE2
UART1 Tx interrupt occurred flag
UART1 Rx interrupt occurred flag
UART0 Tx interrupt occurred flag
UART0 Rx interrupt occurred flag
NOTE3
NOTE3
NOTE1 :
In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR
in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and
Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after
reading this register.
NOTE2 :
NOTE3 :
In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
Figure 12-4 IFR(Interrupt Flag Register)
MAR. 2005 Ver 0.2
45
MC80F0208/16/24
Preliminary
13. WATCH TIMER
The watch timer generates interrupt for watch operation. The
watch timer consists of the clock selector, 15-bit binary counter,
interval selector and watch timer mode register. It is a multi-pur-
pose timer. It is generally used for watch design.
nized. In fXIN÷27 clock source, if the CPU enters into stop mode,
the main-clock is stopped and then watch timer is also stopped.
The watch timer counter can output with period of max 1 seconds
at sub-clock. The bit 2, 3, 4 of WTMR select the interrupt interval
divide ratio selection of watch timer among 16, 64, 256, 1024,
4096, 8192, 16384 or 32768.
The bit 0,1 of WTMR select the clock source of watch timer
among fXIN÷2, fXIN÷27 and main-clock(fXIN). The fXIN of main-
clock is used usually for watch timer test, so generally it is not
used for the clock source of watch timer. The fXIN÷27 of main-
clock(4.194MHz) is used when the single clock system is orga-
The WTIF bit of IFR register is set when watch timer interrupt is
generated. (Refer to Figure 12-4)
WTMR (Watch Timer Mode Register)
W
7
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
6
-
5
-
ADDRESS: 0F6
INITIAL VALUE:0--0 0000
H
WTEN
WTIN2
WTIN1 WTIN0 WTCK1 WTCK0
B
Watch Timer Clock Source selection
WTEN (Watch Timer Enable)
0: Watch Timer disable
1: Watch Timer Enable
00: -
01: f
10: f
÷ 128
÷ 2
XIN
XIN
11: f
XIN
Watch Timer Interrupt Interval selection
000: Clock Source ÷ 32768
001: Clock Source ÷ 16384
010: Clock Source ÷ 8192
011: Clock Source ÷ 4096
100: Clock Source ÷ 1024
101: Clock Source ÷ 256
110: Clock Source ÷ 64
111: Clock Source ÷ 16
Figure 13-1 Watch Timer Mode Register
WTIN[2:0]
WTCK[1:0]
÷32768
÷16384
÷8192
÷4096
01
f
f
f
XIN÷128
10
11
Watch Timer interrupt
MUX
MUX
XIN
÷1024
÷256
÷64
XIN÷2
Clock Source
Selector
WTEN
Clear
÷16
If WTEN=0
interval
selector
Figure 13-2 Watch Timer Block Diagram
46
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
14. TIMER/EVENT COUNTER
The MC80F0208/16/24 has five Timer/Counter registers. Each
module can generate an interrupt to indicate that an event has oc-
curred (i.e. timer match).
external clock edge input, the count register is captured into cap-
ture data register CDRx.
Timer 0 and Timer 1 has four operating modes: "8-bit timer/
counter", "16-bit timer/counter", "8-bit capture" and "16-bit cap-
ture" which are selected by bit in Timer mode register TM0 and
TM1 as shown in Table 14-1, Figure 14-1.
Timer 0 and Timer 1 are can be used either two 8-bit Timer/
Counter or one 16-bit Timer/Counter with combine them. Also
Timer 2 and Timer 3 are same. Timer 4 is 16-bit Timer/Counter.
In the “timer” function, the register is increased every internal
clock input. Thus, one can think of it as counting internal clock
input. Since a least clock consists of 2 and most clock consists of
2048 oscillator periods, the count rate is 1/2 to 1/2048 of the os-
cillator frequency.
Timer 2 and Timer 3 is shared with "PWM" function and
"Compare output" function. It has six operating modes: "8-
bit timer/counter", "16-bit timer/counter", "8-bit capture",
"16-bit capture", "8-bit compare output", and "10-bit
PWM" which are selected by bit in Timer mode register
TM2 and TM3 as shown in Table 14-2, Figure 14-2.
In the “counter” function, the register is increased in response to
a 0-to-1 (rising edge) transition at its corresponding external input
pin, EC0 or EC1.
Timer 4 has two operating modes: "16-bit timer/counter" and
"16-bit capture" which are selected by bit in Timer mode register
TM4 as shown inTable 14-3, and Figure 14-3.
In addition the “capture” function, the register is increased in re-
sponse external or internal clock sources same with timer or
counter function. When external clock edge input, the count reg-
ister is captured into Timer data register correspondingly. When
T0CK T1CK
16BIT CAP0 CAP1
TIMER 0
8-bit Timer
TIMER 1
8-bit Timer
[2:0]
XXX
111
[1:0]
XX
XX
XX
11
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
0
1
8-bit Event counter
8-bit Capture
8-bit Timer
XXX
XXX
111
8-bit Capture (internal clock)
16-bit Timer
11
16-bit Event counter
16-bit Capture (internal clock)
XXX
11
Table 14-1 Operating Modes of Timer 0, 1
1. X means the value of “0” or “1” corresponds to user operation.
T2CK
[2:0]
T3CK
[1:0]
16BIT CAP2 CAP3 PWM3E
PWM3O
TIMER 2
TIMER 3
0
0
0
0
1
1
1
0
0
1
X
0
0
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
XXX
111
XX
XX
XX
XX
11
0
0
1
1
0
0
0
8-bit Timer
8-bit Event counter
8-bit Capture (internal clock) 8-bit Compare Output
8-bit Timer
8-bit Capture
XXX
XXX
XXX
111
8-bit Timer/Counter
16-bit Timer
10-bit PWM
11
16-bit Event counter
16-bit Capture (internal clock)
XXX
11
Table 14-2 Operating Modes of Timer 2, 3
MAR. 2005 Ver 0.2
47
MC80F0208/16/24
Preliminary
CAP4
T4CK[2:0]
XXX
TIMER 4
0
1
16-bit Timer
XXX
16-bit Capture (internal clock)
Table 14-3 Operating Modes of Timer 4
48
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
R/W R/W R/W R/W R/W R/W
5
4
3
2
1
0
ADDRESS: 0D0
INITIAL VALUE: --00 0000
H
TM0
-
-
CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST
B
Bit Name
Bit Position
Description
CAP0
TM0.5
0: Timer/Counter mode
1: Capture mode selection flag
T0CK2
T0CK1
T0CK0
TM0.4
TM0.3
TM0.2
000: 8-bit Timer, Clock source is f
001: 8-bit Timer, Clock source is f
010: 8-bit Timer, Clock source is f
011: 8-bit Timer, Clock source is f
100: 8-bit Timer, Clock source is f
101: 8-bit Timer, Clock source is f
110: 8-bit Timer, Clock source is f
111: EC0 (External clock)
÷ 2
XIN
XIN
XIN
XIN
XIN
XIN
XIN
÷ 4
÷ 8
÷ 32
÷ 128
÷ 512
÷ 2048
T0CN
T0ST
TM0.1
TM0.0
0: Timer count pause
1: Timer count start
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
-
7
R/W
6
-
5
R/W R/W R/W R/W R/W
4
3
2
1
0
ADDRESS: 0D2
INITIAL VALUE: -0-0 0000
H
TM1
-
16BIT
-
CAP1 T1CK1 T1CK0 T1CN T1ST
B
Bit Name
Bit Position
Description
16BIT
TM1.6
0: 8-bit Mode
1: 16-bit Mode
CAP1
TM1.4
0: Timer/Counter mode
1: Capture mode selection flag
T1CK1
T1CK0
TM1.3
TM1.2
00: 8-bit Timer, Clock source is f
01: 8-bit Timer, Clock source is f
10: 8-bit Timer, Clock source is f
XIN
XIN
XIN
÷ 2
÷ 8
11: 8-bit Timer, Clock source is Using the Timer 0 Clock
T1CN
T1ST
TM1.1
TM1.0
0: Timer count pause
1: Timer count start
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D1
INITIAL VALUE: 0FF
H
TDR0
TDR1
H
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D3
H
INITIAL VALUE: 0FF
H
Read: Count value read
Write: Compare data write
Figure 14-1 TM0, TM1 Registers
MAR. 2005 Ver 0.2
49
MC80F0208/16/24
Preliminary
R/W R/W R/W R/W R/W R/W
5
4
3
2
1
0
ADDRESS: 0D6
INITIAL VALUE: --00 0000
H
TM2
-
-
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST
B
Bit Name
Bit Position
Description
CAP2
TM2.5
0: Timer/Counter mode
1: Capture mode selection flag
T2CK2
T2CK1
T2CK0
TM2.4
TM2.3
TM2.2
000: 8-bit Timer, Clock source is f
001: 8-bit Timer, Clock source is f
010: 8-bit Timer, Clock source is f
011: 8-bit Timer, Clock source is f
100: 8-bit Timer, Clock source is f
101: 8-bit Timer, Clock source is f
110: 8-bit Timer, Clock source is f
111: EC1 (External clock)
÷ 2
XIN
XIN
XIN
XIN
XIN
XIN
XIN
÷ 4
÷ 8
÷ 16
÷ 64
÷ 256
÷ 1024
T2CN
T2ST
TM2.1
TM2.0
0: Timer count pause
1: Timer count start
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D8
INITIAL VALUE: 00
H
TM3
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST
H
Bit Name
Bit Position
Description
POL
TM3.7
0: PWM Duty Active Low
1: PWM Duty Active High
16BIT
TM3.6
TM3.5
TM3.4
0: 8-bit Mode
1: 16-bit Mode
PWM3E
CAP3
0: Disable PWM
1: Enable PWM
0: Timer/Counter mode
1: Capture mode selection flag
T3CK1
T3CK0
TM3.3
TM3.2
00: 8-bit Timer, Clock source is f
01: 8-bit Timer, Clock source is f
10: 8-bit Timer, Clock source is f
XIN
XIN
XIN
÷ 4
÷ 16
11: 8-bit Timer, Clock source is Using the Timer 2 Clock
T3CN
T3ST
TM3.1
TM3.0
0: Timer count pause
1: Timer count start
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D7
INITIAL VALUE: 0FF
H
TDR2
TDR3
H
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D9
H
INITIAL VALUE: 0FF
H
Read: Count value read
Write: Compare data write
Figure 14-2 TM2, TM3 Registers
50
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
R/W R/W R/W R/W R/W R/W
5
4
3
2
1
0
ADDRESS: 0DC
INITIAL VALUE: --00 0000
H
TM4
-
-
CAP4 T4CK2 T4CK1 T4CK0 T4CN T4ST
B
Bit Name
Bit Position
Description
CAP4
TM4.5
0: Timer/Counter mode
1: Capture mode selection flag
T4CK2
T4CK1
T4CK0
TM4.4
TM4.3
TM4.2
000: 8-bit Timer, Clock source is f
001: 8-bit Timer, Clock source is f
010: 8-bit Timer, Clock source is f
011: 8-bit Timer, Clock source is f
100: 8-bit Timer, Clock source is f
101: 8-bit Timer, Clock source is f
110: 8-bit Timer, Clock source is f
111: 8-bit Timer, Clock source is f
÷ 2
XIN
XIN
XIN
XIN
XIN
XIN
XIN
XIN
÷ 4
÷ 8
÷ 16
÷ 64
÷ 256
÷ 1024
÷ 2048
T4CN
T4ST
TM4.1
TM4.0
0: Timer count pause
1: Timer count start
0: When cleared, stop the counting.
1: When set, Timer 0 Count Register is cleared and start again.
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0DD
INITIAL VALUE: 0FF
H
TDR4H
TDR4L
H
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0DE
H
INITIAL VALUE: 0FF
H
Figure 14-3 TM4 Register
14.1 8-bit Timer / Counter Mode
The MC80F0208/16/24 has four 8-bit Timer/Counters, Timer 0,
Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown in
Figure 14-4 and Timer 2, Timer 3 are shown in Figure 14-5.
be cleared to "0"(Figure 14-4). These timers have each 8-bit
count register and data register. The count register is increased by
every internal or external clock input. The internal clock has a
prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256,
512, 1024, 2048 or external clock (selected by control bits
TxCK0, TxCK1, TxCK2 of register TMx).
The “timer” or “counter” function is selected by control registers
TM0, TM1, TM2, TM3 as shown in Figure 14-1. To use as an 8-
bit timer/counter mode, bit CAP0, CAP1, CAP2, or CAP3 of
TMx should be cleared to “0” and 16BIT of TM1 or TM3 should
MAR. 2005 Ver 0.2
51
MC80F0208/16/24
Preliminary
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D0
INITIAL VALUE: --00 0000
H
TM0
TM1
CAP0 T0CK2T0CK1 T0CK0 T0CN T0ST
B
0
X
-
-
X
X
X
X
X means don’t care
7
-
6
5
-
4
3
2
1
0
ADDRESS: 0D2
H
16BIT
CAP1 T1CK1 T1CK0 T1CN T1ST
INITIAL VALUE: -0-0 0000
B
-
0
-
0
X
X
X
X
X means don’t care
T0CK[2:0]
EDGE
DETECTOR
EC0 PIN
XIN PIN
111
000
T0ST
0: Stop
1: Clear and start
÷ 2
÷ 4
001
010
011
÷ 8
T0 (8-bit)
÷ 32
÷ 128
÷ 512
clear
100
101
TIMER 0
INTERRUPT
T0CN
T0IF
Comparator
÷ 2048
110
TIMER 0
TDR0 (8-bit)
MUX
T1CK[1:0]
11
T1ST
0: Stop
1: Clear and start
÷ 1
÷ 2
÷ 8
00
01
10
T1 (8-bit)
clear
TIMER 1
INTERRUPT
T1CN
T1IF
MUX
Comparator
TIMER 1
TDR1 (8-bit)
Figure 14-4 8-bit Timer/Counter 0, 1
52
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D6
INITIAL VALUE: --000000
H
TM2
TM3
CAP2 T2CK2T2CK1 T2CK0 T2CN T2ST
B
0
X
-
-
X
X
X
X
X means don’t care
7
6
5
4
3
2
1
0
ADDRESS: 0D8
H
POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST
INITIAL VALUE: 00
H
0
0
X
0
X
X
X
X
X means don’t care
T2CK[2:0]
EDGE
DETECTOR
EC1 PIN
XIN PIN
111
000
T2ST
0: Stop
1: Clear and start
÷ 2
÷ 4
001
010
011
÷ 8
T2 (8-bit)
÷ 16
÷ 64
÷ 256
clear
100
101
TIMER 2
INTERRUPT
T2CN
T2IF
Comparator
÷ 1024
110
TIMER 2
TDR2 (8-bit)
MUX
T3CK[1:0]
11
T3ST
0: Stop
1: Clear and start
÷ 1
÷ 4
00
01
10
T3 (8-bit)
clear
÷ 16
TIMER 3
INTERRUPT
T3CN
T3IF
F/F
MUX
Comparator
TIMER 3
TDR3 (8-bit)
R54/PWM3O/T3O
Figure 14-5 8-bit Timer/Counter 2, 3
MAR. 2005 Ver 0.2
53
MC80F0208/16/24
Preliminary
Example 1:
These timers have each 8-bit count register and data register. The
count register is increased by every internal or external clock in-
put. The internal clock has a prescaler divide ratio option of 2, 4,
8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of reg-
ister TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register
TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits
T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits
T3CK[1:0] of register TM3. In the Timer 0, timer register T0 in-
creases from 00H until it matches TDR0 and then reset to 00H.
The match output of Timer 0 generates Timer 0 interrupt (latched
in T0IF bit).
Timer0 = 2ms 8-bit timer mode at 4MHz
Timer1 = 0.5ms 8-bit timer mode at 4MHz
Timer2 = 1ms 8-bit timer mode at 4MHz
Timer3 = 1ms 8-bit timer mode at 4MHz
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
TDR0,#249
TDR1,#249
TDR2,#249
TDR3,#249
TM0,#0000_1111B
TM1,#0000_1011B
TM2,#0000_1111B
TM3,#0000_1011B
In counter function, the counter is increased every 0-to-1(1-to-0)
(rising & falling edge) transition of EC0 pin. In order to use
counter function, the bit EC0 of the Port Selection Regis-
ter(PSR0.4) is set to "1". The Timer 0 can be used as a counter by
pin EC0 input, but Timer 1 can not. Likewise, In order to use
Timer2 as counter function, the bit EC1 of the Port Selection
Register(PSR0.5) is set to "1". The Timer 2 can be used as a
counter by pin EC1 input, but Timer 3 can not.
SET1 T0E
SET1 T1E
SET1 T2E
SET1 T3E
EI
Example 2:
Timer0 = 8-bit event counter mode
Timer1 = 0.5ms 8-bit timer mode at 4MHz
Timer2 = 8-bit event counter mode
Timer3 = 1ms 8-bit timer mode at 4MHz
14.1.1 8-bit Timer Mode
In the timer mode, the internal clock is used for counting up.
Thus, you can think of it as counting internal clock input. The
contents of TDRn are compared with the contents of up-counter,
Tn. If match is found, a timer n interrupt (TnIF) is generated and
the up-counter is cleared to 0. Counting up is resumed after the
up-counter is cleared.
LDM
LDM
LDM
LDM
LDM
LDM
LDM
LDM
SET1 T0E
SET1 T1E
SET1 T2E
SET1 T3E
EI
TDR0,#249
TDR1,#249
TDR2,#249
TDR3,#249
TM0,#0001_1111B
TM1,#0000_1011B
TM2,#0001_1111B
TM3,#0000_1011B
As the value of TDRn is changeable by software, time interval is
set as you want.
Start count
Source clock
Up-counter
2
3
n-2
n-1
n
1
4
2
3
0
1
0
n
TDR1
Match
Detect
Counter
Clear
T1IF interrupt
Figure 14-6 Timer Mode Timing Chart
54
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
Example: Make 1ms interrupt using by Timer0 at 4MHz
LDM
LDM
TM0,#0FH
; divide by 32
TDR0,#124
; 8us x (124+1)= 1ms
; Enable Timer 0 Interrupt
; Enable Master Interrupt
SET1 T0E
EI
When
TM0 = 0000 1111 (8-bit Timer mode, Prescaler divide ratio = 32)
B
TDR0 = 124 = 7C
D
H
f
= 4 MHz
XIN
1
INTERRUPT PERIOD =
TDR0
× 32 × (124+1) = 1 ms
6
4 × 10 Hz
MATCH
Count Pulse
Period
(TDR0 = T0)
7C
7B
7C
7A
8 µs
6
5
4
3
2
1
0
0
TIME
Interrupt period
= 8 µs x (124+1)
Timer 0 (T0IF)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 14-7 Timer Count Example
In order to use event counter function, the bit 4, 5 of the Port Se-
lection Register PSR0(address 0F8H) is required to be set to “1”.
14.1.2 8-bit Event Counter Mode
In this mode, counting up is started by an external trigger. This
trigger means rising edge of the EC0 or EC1 pin input. Source
clock is used as an internal clock selected with timer mode regis-
ter TM0 or TM2. The contents of timer data register TDRn (n =
0,1,2,3) are compared with the contents of the up-counter Tn. If a
match is found, an timer interrupt request flag TnIF is generated,
and the counter is cleared to “0”. The counter is restart and count
up continuously by every falling edge of the EC0 or EC1 pin in-
put. The maximum frequency applied to the EC0 or EC1 pin is
fXIN/2 [Hz].
After reset, the value of timer data register TDRn is initialized to
"0", The interval period of Timer is calculated as below equation.
1
----------
Period (sec) =
× 2 × Divide Ratio × (TDRn+1)
f
XIN
Start count
ECn pin input
1
1
2
Up-counter
0
2
n-1
n
0
TDR1
n
T1IF interrupt
Figure 14-8 Event Counter Mode Timing Chart
MAR. 2005 Ver 0.2
55
MC80F0208/16/24
Preliminary
TDR1
enable
disable
clear & start
stop
TIME
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
T1ST
Start & Stop
T1ST = 1
T1ST = 0
T1CN
T1CN = 1
Control count
T1CN = 0
Figure 14-9 Count Operation of Timer / Event counter
56
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
14.2 16-bit Timer / Counter Mode
The Timer register is being run with all 16 bits. A 16-bit timer/
counter register T0, T1 are incremented from 0000H until it
matches TDR0, TDR1 and then resets to 0000H. The match out-
put generates Timer 0 interrupt.
T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively
as shown in Figure 14-11.
Even if the Timer 0 (including Timer 1) is used as a 16-bit timer,
the Timer 2 and Timer 3 can still be used as either two 8-bit timer
or one 16-bit timer by setting the TM2. Reversely, even if the
Timer 2 (including Timer 3) is used as a 16-bit timer, the Timer
0 and Timer 1 can still be used as 8-bit timer independently.
The clock source of the Timer 0 is selected either internal or ex-
ternal clock by bit T0CK[2:0]. In 16-bit mode, the bits
T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively
as shown in Figure 14-10.
A 16-bit timer/counter 4 register T4H, T4L are increased from
0000H until it matches TDR4H, TDR4L and then resets to 0000H.
The match output generates Timer 4 interrupt. Timer/Counter 4
is 16 bit mode as shown in Figure 14-12.
Likewise, A 16-bit timer/counter register T2, T3 are incremented
from 0000H until it matches TDR2, TDR3 and then resets to
0000H. The match output generates Timer 2 interrupt.
The clock source of the Timer 2 is selected either internal or ex-
ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D0
INITIAL VALUE: --00 0000
H
TM0
TM1
CAP0 T0CK2 T0CK1T0CK0 T0CN T0ST
B
0
X
-
-
X
X
X
X
X means don’t care
7
-
6
5
-
4
3
2
1
0
ADDRESS: 0D2
H
16BIT
CAP1 T1CK1T1CK0 T1CN T1ST
INITIAL VALUE: -0-0 0000
B
-
0
-
1
1
1
X
X
X means don’t care
T0CK[2:0]
EDGE
DETECTOR
EC0 PIN
XIN PIN
111
000
T0ST
÷ 2
0: Stop
1: Clear and start
÷ 4
001
010
011
÷ 8
T1 + T0
(16-bit)
clear
÷ 32
÷ 128
÷ 512
÷ 2048
100
101
110
TIMER 0
INTERRUPT
T0CN
T0IF
Comparator
(Not Timer 1 interrupt)
MUX
TDR1 + TDR0
(16-bit)
Lower byte
Higher byte
COMPARE DATA
TIMER 0 + TIMER 1 → TIMER 0 (16-bit)
Figure 14-10 16-bit Timer/Counter for Timer 0, 1
MAR. 2005 Ver 0.2
57
MC80F0208/16/24
Preliminary
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D6
INITIAL VALUE: --000000
H
TM2
CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST
B
0
X
-
-
X
X
X
X
X means don’t care
7
6
5
4
3
2
1
0
ADDRESS: 0D8
INITIAL VALUE: 00
H
TM3
POL 16BIT PWM3E CAP3 T3CK1T3CK0 T3CN T3ST
H
0
0
X
1
1
1
X
X
X means don’t care
T2CK[2:0]
EDGE
DETECTOR
EC1 PIN
XIN PIN
111
000
T2ST
÷ 2
0: Stop
1: Clear and start
÷ 4
÷ 8
001
010
011
T3 + T2
(16-bit)
clear
÷ 16
÷ 64
100
101
110
TIMER 2
INTERRUPT
T2CN
÷ 256
T2IF
÷ 1024
Comparator
(Not Timer 3 interrupt)
MUX
TDR3 + TDR2
(16-bit)
Lower byte
Higher byte
COMPARE DATA
TIMER 2 + TIMER 3 → TIMER 2 (16-bit)
Figure 14-11 16-bit Timer/Counter for Timer 2, 3
14.3 8-bit Compare Output (16-bit)
The MC80F0208/16/24 has a function of Timer Compare Output.
To pulse out, the timer match can goes to port pin( T3O) as shown
in Figure 14-5 . Thus, pulse out is generated by the timer match.
These operation is implemented to pin, PWM3O/T3O.
nal having a 50 : 50 duty square wave, and output frequency is
same as below equation.
Oscillation Frequency
f
= ---------------------------------------------------------------------------------
COMP
2 × Prescaler Value × (TDR + 1 )
In this mode, the bit PWM3O/T3O of R5 Port Selection register0
(PSR0.7) should be set to "1", and the bit PWM3E of timer3
mode register (TM3) should be set to "0". This pin output the sig-
58
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0DC
INITIAL VALUE: 00
H
TM4
CAP4 T4CK2 T4CK1T4CK0 T4CN T4ST
H
0
X
X
X
T4CK[2:0]
000
X
X
X
X
X means don’t care
÷ 2
÷ 4
÷ 8
T4ST
XIN PIN
001
010
011
0: Stop
1: Clear and start
÷ 16
÷ 64
T4H + T4L
(16-bit)
100
101
110
111
clear
÷ 256
÷ 1024
÷ 2048
TIMER 4
INTERRUPT
T4CN
T4IF
Comparator
TDR4H + TDR4L
(16-bit)
MUX
Lower byte
Higher byte
COMPARE DATA
Figure 14-12 Timer 4 for only 16 bit mode
14.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode reg-
ister TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as
shown in Figure 14-13. Likewise, the Timer 2 capture mode is set
by bit CAP2 of timer mode register TM2 (bit CAP3 of timer
mode register TM3 for Timer 3) as shown in Figure 14-14.
than wanted value. It can be obtained correct value by counting
the number of timer overflow occurrence.
Timer/Counter still does the above, but with the added feature
that a edge transition at external input INTx pin causes the current
value in the Timer x register (T0,T1,T2,T3), to be captured into
registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. Af-
ter captured, Timer x register is cleared and restarts by hardware.
It has three transition modes: "falling edge", "rising edge", "both
edge" which are selected by interrupt edge selection register
IEDS. Refer to “19.5 External Interrupt” on page 92. In addition,
the transition at INTn pin generate an interrupt.
The Timer/Counter register is increased in response internal or
external input. This counting function is same with normal timer
mode, and Timer interrupt is generated when timer register T0
(T1, T2, T3) increases and matches TDR0 (TDR1, TDR2,
TDR3).
This timer interrupt in capture mode is very useful when the pulse
width of captured signal is more wider than the maximum period
of Timer.
Note: The CDRn and TDRn are in same address.In the
capture mode, reading operation is read the CDRn, not
TDRn because path is opened to the CDRn.
For example, in Figure 14-16, the pulse width of captured signal
is wider than the timer data value (FFH) over 2 times. When ex-
ternal interrupt is occurred, the captured value (13H) is more little
MAR. 2005 Ver 0.2
59
MC80F0208/16/24
Preliminary
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D0
INITIAL VALUE: --00 0000
H
TM0
TM1
CAP0 T0CK2 T0CK1T0CK0 T0CN T0ST
B
1
X
-
-
X
X
X
X
X means don’t care
7
-
6
5
-
4
3
2
1
0
ADDRESS: 0D2
H
16BIT
CAP1 T1CK1T1CK0 T1CN T1ST
INITIAL VALUE: -0-0 0000
B
-
1
-
0
X
X
X
X
X means don’t care
T0CK[2:0]
Edge
Detector
EC0 PIN
XIN PIN
111
000
T0ST
0: Stop
1: Clear and start
÷ 2
÷ 4
÷ 8
001
010
011
T0 (8-bit)
÷ 32
clear
Capture
CDR0 (8-bit)
÷ 128
÷ 512
100
101
T0CN
÷ 2048
110
MUX
IEDS[1:0]
“01”
“10”
INT0
INTERRUPT
INT0IF
INT0 PIN
T1CK[1:0]
11
“11”
T1ST
0: Stop
1: Clear and start
÷ 1
÷ 2
÷ 8
00
01
10
T1 (8-bit)
clear
Capture
CDR1 (8-bit)
T1CN
MUX
IEDS[3:2]
“01”
“10”
INT1
INTERRUPT
INT1IF
INT1 PIN
“11”
Figure 14-13 8-bit Capture Mode for Timer 0, 1
60
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D6
INITIAL VALUE: --00 0000
H
TM2
TM3
CAP2 T2CK2 T2CK1T2CK0 T2CN T2ST
B
1
X
-
-
X
X
X
X
X means don’t care
7
6
5
4
3
2
1
0
ADDRESS: 0D8
H
POL 16BIT PWM3E CAP3 T3CK1T3CK0 T3CN T3ST
INITIAL VALUE: 00
H
0
1
X
0
X
X
X
X
X means don’t care
T2CK[2:0]
Edge
Detector
EC1 PIN
XIN PIN
111
000
T2ST
0: Stop
1: Clear and start
÷ 2
÷ 4
001
010
011
÷ 8
T2 (8-bit)
÷ 16
÷ 64
÷ 256
clear
Capture
CDR2 (8-bit)
100
101
T2CN
÷ 1024
110
MUX
IEDS[5:4]
“01”
“10”
INT2
INTERRUPT
INT2IF
INT2 PIN
T3CK[1:0]
11
“11”
T3ST
0: Stop
1: Clear and start
÷ 1
÷ 4
00
01
10
T3 (8-bit)
÷ 16
clear
Capture
CDR3 (8-bit)
T3CN
MUX
IEDS[7:6]
“01”
“10”
INT3
INTERRUPT
INT3IF
INT3 PIN
“11”
Figure 14-14 8-bit Capture Mode for Timer 2, 3
MAR. 2005 Ver 0.2
61
MC80F0208/16/24
Preliminary
This value is loaded to CDR0
n
T0
n-1
9
8
7
6
5
4
3
2
1
0
TIME
Ext. INT0 Pin
Interrupt Request
( INT0IF )
Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request
( INT0IF )
20nS
5nS
Delay
Clear & Start
Capture
( Timer Stop )
Figure 14-15 Input Capture Operation of Timer 0 Capture mode
Ext. INT0 Pin
Interrupt Request
( INT0IF )
Interrupt Interval Period=01H+FFH +01H+FFH +01H+13H=214H
Interrupt Request
( T0IF )
FFH
FFH
T0
13H
00H
00H
Figure 14-16 Excess Timer Overflow in Capture Mode
62
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
14.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the
Timer register is being run will 16 bits. The clock source of the
Timer 0 is selected either internal or external clock by bit
T0CK[2:0]. In 16-bit mode, the bits T1CK1, T1CK0, CAP1 and
16BIT of TM1 should be set to "1" respectively as shown in Fig-
ure 14-17.
ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits
T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1" re-
spectively as shown in Figure 14-18.
The clock source of the Timer 4 is selected either internal or ex-
ternal clock by bit T4CK[2:0] as shown in Figure 14-18.
The clock source of the Timer 2 is selected either internal or ex-
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D0
INITIAL VALUE: --00 0000
H
TM0
TM1
CAP0 T0CK2 T0CK1T0CK0 T0CN T0ST
B
1
X
-
-
X
X
X
X
X means don’t care
7
-
6
5
-
4
3
2
1
0
ADDRESS: 0D2
H
16BIT
CAP1 T1CK1T1CK0 T1CN T1ST
INITIAL VALUE: -0-0 0000
B
-
1
-
1
1
1
X
X
X means don’t care
T0CK[2:0]
Edge
Detector
EC0 PIN
XIN PIN
111
000
T0ST
÷ 2
0: Stop
1: Clear and start
÷ 4
001
010
011
TDR1 + TDR0
(16-bit)
÷ 8
÷ 32
÷ 128
÷ 512
clear
Capture
100
101
T0CN
÷ 2048
110
CDR1 + CDR0
(16-bit)
MUX
IEDS[1:0]
Lower byte
Higher byte
CAPTURE DATA
“01”
“10”
INT0
INTERRUPT
INT0IF
INT0 PIN
“11”
Figure 14-17 16-bit Capture Mode of Timer 0, 1
MAR. 2005 Ver 0.2
63
MC80F0208/16/24
Preliminary
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D6
INITIAL VALUE: --000000
H
TM2
TM3
CAP2 T2CK2T2CK1 T2CK0 T2CN T2ST
B
1
X
-
-
X
X
X
X
X means don’t care
7
6
5
4
3
2
1
0
ADDRESS: 0D8
H
POL 16BIT PWM3E CAP3 T3CK1T3CK0 T3CN T3ST
INITIAL VALUE: 00
H
0
1
X
1
1
1
X
X
X means don’t care
T2CK[2:0]
Edge
Detector
EC1 PIN
XIN PIN
111
000
T2ST
÷ 2
÷ 4
÷ 8
0: Stop
1: Clear and start
001
010
011
TDR3 + TDR2
(16-bit)
÷ 16
÷ 64
÷ 256
clear
Capture
100
101
110
T2CN
÷ 1024
CDR3 + CDR2
(16-bit)
MUX
IEDS[5:4]
Lower byte
Higher byte
CAPTURE DATA
“01”
“10”
INT2
INTERRUPT
INT2IF
INT2 PIN
“11”
Figure 14-18 16-bit Capture Mode of Timer 2, 3
64
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0DC
INITIAL VALUE: 00
H
TM4
CAP4 T4CK2 T4CK1T4CK0 T4CN T4ST
H
1
X
X
X
X
X
X
X
X means don’t care
T4CK[2:0]
000
÷ 2
T4ST
÷ 4
XIN PIN
001
010
011
÷ 8
0: Stop
1: Clear and start
÷ 16
÷ 64
÷ 256
TDR4H + TDR4L
(16-bit)
100
101
110
111
clear
Capture
÷ 1024
÷ 2048
T4CN
CDR4H + CDR4L
(16-bit)
MUX
IEDS[1:0]
Lower byte
Higher byte
CAPTURE DATA
“01”
“10”
INT3
INTERRUPT
INT3IF
INT3 PIN
“11”
Figure 14-19 16-bit Capture Mode of Timer 4
Example 1:
Timer0 = 16-bit timer mode, 0.5s at 4MHz
Example 3:
Timer0 = 16-bit capture mode
LDM
LDM
LDM
LDM
TM0,#0000_1111B;8uS
LDM
LDM
LDM
LDM
LDM
LDM
PSR0,#0000_0001B;INT0 set
TM0,#0010_1111B;CaptureMode
TM1,#0100_1100B;16bit Mode
TM1,#0100_1100B;16bit Mode
TDR0,#<62499
TDR1,#>62499
;8uS X 62500
;=0.5s
TDR0,#<0FFH
TDR1,#>0FFH
;
;
SET1 T0E
EI
:
:
IEDS,#01H;Falling Edge
SET1 T0E
EI
:
:
Example 2:
Timer0 = 16-bit event counter mode
LDM
LDM
LDM
LDM
LDM
PSR0,#0001_0000B;EC0 Set
TM0,#0001_1111B;CounterMode
TM1,#0100_1100B;16bit Mode
TDR0,#<0FFH
TDR1,#>0FFH
;
;
SET1 T0E
EI
:
:
MAR. 2005 Ver 0.2
65
MC80F0208/16/24
14.6 PWM Mode
Preliminary
The MC80F0208/16/24 has a high speed PWM (Pulse Width
Modulation) functions which shared with Timer3.
The bit POL of TM3 decides the polarity of duty cycle.
If the duty value is set same to the period value, the PWM output
is determined by the bit POL (1: High, 0: Low). And if the duty
value is set to "00H", the PWM output is determined by the bit
POL (1: Low, 0: High).
In PWM mode, pin R54/PWM3O outputs up to a 10-bit resolu-
tion PWM output. This pin should be configured as a PWM out-
put by setting "1" bit PWM3O in PSR0 register.
The period of the PWM3 output is determined by the T3PPR (T3
PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM
High Register) and the duty of the PWM output is determined by
the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0
of T3 PWM High Register).
It can be changed duty value when the PWM output. However the
changed duty value is output after the current period is over. And
it can be maintained the duty value at present output when
changed only period value shown as Figure 14-22. As it were, the
absolute duty time is not changed in varying frequency. But the
changed period value must greater than the duty value.
The user writes the lower 8-bit period value to the T3PPR and the
higher 2-bit period value to the T3PWHR[3:2]. And writes duty
value to the T3PDR and the T3PWHR[1:0] same way.
Note: If changing the Timer3 to PWM function, it should be
stop the timer clock firstly, and then set period and duty reg-
ister value. If user writes register values while timer is in op-
eration, these register could be set with certain values.
The T3PDR is configured as a double buffering for glitchless
PWM output. In Figure 14-20, the duty data is transferred from
the master to the slave when the period data matched to the count-
ed value. (i.e. at the beginning of next duty cycle)
Ex) Sample Program @4MHz 4uS
PWM3 Period = [PWM3HR[3:2]T3PPR] X Source Clock
PWM3 Duty = [PWM3HR[1:0]T3PDR] X Source Clock
LDM TM3,#1010_1000b ; Set Clock & PWM3E
LDM T3PPR,#199
LDM T3PDR,#99
LDM PWM3HR,00H
; Period :800uS=4uSX(199+1)
; Duty:400uS=4uSX(99+1)
The relation of frequency and resolution is in inverse proportion.
Table 14-4 shows the relation of PWM frequency vs. resolution.
LDM TM3,#1010_1011b ; Start timer3
If it needed more higher frequency of PWM, it should be reduced
resolution.
Frequency
Resolution
T3CK[1:0]
T3CK[1:0]
= 01(1uS)
T3CK[1:0]
= 10(4uS)
= 00(250nS)
10-bit
9-bit
8-bit
7-bit
3.9kHz
7.8kHz
1.95kHz
3.90kHz
7.81kHz
15.6kHz
0.97kHz
1.95kHz
3.90kHz
7.8kHz
15.6kHz
31.2kHz
Table 14-4 PWM Frequency vs. Resolution at 4MHz
66
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0D8
INITIAL VALUE: 00
H
TM3
POL 16BIT PWM3E CAP3 T3CK1T3CK0 T3CN T3ST
H
1
0
X
0
X
X
X
X
X:The value "0" or "1" corresponding your operation.
-
7
-
6
-
5
-
4
W
3
W
2
W
1
W
0
ADDRESS: 0DB
INITIAL VALUE: ---- 0000
H
T3PWHR
-
-
-
-
-
-
-
T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0
B
-
Bit Manipulation Not Available
X
X
X
X
X:The value "0" or "1" corresponding your operation.
Period High
Duty High
W
7
W
6
W
5
W
4
W
3
W
2
W
1
W
0
ADDRESS: 0D9
INITIAL VALUE: 0FF
H
T3PPR
T3PDR
H
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0DA
INITIAL VALUE: 00
H
H
1
0
X
0
X
X
X
X
T3PWHR[1:0]
PWM3O
[PSR0.7]
T2 clock source
[T2CK]
T3CK[1:0]
T3PPR(8-bit)
T3ST
0 : Stop
1 : Clear and Start
S
R
Q
Comparator
11
00
Clear
÷ 1
÷ 4
R53/PWM3O/T3O PIN
2-bit
T3(8-bit)
01
10
XIN PIN
÷ 16
POL
T3CN
Comparator
MUX
Slave
T3PDR(8-bit)
T3PWHR[1:0]
Master
T3PDR(8-bit)
Figure 14-20 PWM3 Mode
MAR. 2005 Ver 0.2
67
MC80F0208/16/24
Preliminary
Source
clock
00
01
02
03
04
7E
7F
80
3FF
00
01
02
T3
PWM3E
T3ST
T3CN
PWM3O
[POL=1]
PWM3O
[POL=0]
Duty Cycle [ (1+7Fh) x 250nS = 32uS ]
Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ]
T3CK[1:0] = 00 ( XIN )
T3PWHR = 0CH
T3PPR (8-bit)
T3PWHR3 T3PWHR2
Period
Duty
1
1
FFH
T3PPR = FFH
T3PDR = 7FH
T3PDR (8-bit)
7FH
T3PWHR1 T3PWHR0
0
0
Figure 14-21 Example of PWM at 4MHz
T3CK[1:0] = 10 ( 2us )
PWM3HR = 00H
T3PPR = 0DH
T3PDR = 04H
Write T3PPR to 09H
Source
clock
T3
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04
PWM3O
POL=1
Duty Cycle
[ (04h+1) x 2uS = 10uS ]
Duty Cycle
[ (04h+1) x 2uS = 10uS ]
Duty Cycle
[ (04h+1) x 2uS = 10uS ]
Period Cycle [ (1+0Dh) x 2uS = 28uS, 35.5KHz ]
Period Cycle [ (1+09h) x 2uS = 20uS, 50KHz ]
Figure 14-22 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
68
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
15. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an
analog input signal to a corresponding 10-bit digital value. The A/
D module has sixteen analog inputs, which are multiplexed into
one sample and hold. The output of the sample and hold is the in-
put into the converter, which generates the result via successive
approximation. The analog supply voltage is connected to AVDD
of Sample & Hold logic of A/D module. The AVDD was separat-
ed with VDD in order to minimize the degradation of operation
characteristic by power supply noise.
ADCRH and ADCRL contains the results of the A/D conversion.
When the conversion is completed, the result is loaded into the
ADCRH and ADCRL, the A/D conversion status bit ADSF is set
to “1”, and the A/D interrupt flag ADCIF is set. See Figure 15-1
for operation flow.
The block diagram of the A/D module is shown in Figure 15-3.
The A/D status bit ADSF is set automatically when A/D conver-
sion is completed, cleared when A/D conversion is in process.
The conversion time takes 7 times of conversion source clock.
The period of actual A/D conversion clock should be minimally
1µs
The A/D module has three registers which are the control register
ADCM and A/D result register ADCRH and ADCRL. The AD-
CRH[7:6] is used as ADC clock source selection bits too. The
register ADCM, shown in Figure 15-4, controls the operation of
the A/D converter module. The port pins can be configured as an-
alog inputs or digital I/O.
Analog
Input
AN0~AN7
It is selected for the corresponding channel to be converted by
setting ADS[3:0]. The A/D port is set to analog input port by
ADEN and ADS[3:0] regardless of port I/O direction register.
The port unselected by ADS[3:0] operates as normal port.
0~1000pF
User Selectable
Figure 15-2 Analog Input Pin Connecting Capacitor
Enable A/D Converter
A/D Converter Cautions
A/D Input Channel Select
(1) Input range of AN0 to AN7
The input voltage of AN0 to AN7 should be within the specifica-
tion range. In particular, if a voltage above AVDD or below AVSS
is input (even if within the absolute maximum rating range), the
conversion value for that channel can not be indeterminate. The
conversion values of the other channels may also be affected.
Conversion Source Clock Select
(2) Noise countermeasures
A/D Start (ADST = 1)
In order to maintain 10-bit resolution, attention must be paid to
noise on pins AVDD and AN0 to AN7. Since the effect increases
in proportion to the output impedance of the analog input source,
it is recommended in some cases that a capacitor be connected ex-
ternally as shown in Figure 15-2 in order to reduce noise. The ca-
pacitance is user-selectable and appropriately determined
according to the target system.
NOP
ADSF = 1
NO
(3) Pins AN0/R60 to AN7/R67
YES
The analog input pins AN0 to AN7 also function as input/output
port (PORT R6) pins. When A/D conversion is performed with
any of pins AN0 to AN15 selected, be sure not to execute a PORT
input instruction while conversion is in progress, as this may re-
duce the conversion resolution.
Read ADCR
Also, if digital pulses are applied to a pin adjacent to the pin in the
process of A/D conversion, the expected A/D conversion value
may not be obtainable due to coupling noise. Therefore, avoid ap-
plying pulses to pins adjacent to the pin undergoing A/D conver-
sion.
Figure 15-1 A/D Converter Operation Flow
How to Use A/D Converter
The processing of conversion is start when the start bit ADST is
set to “1”. After one cycle, it is cleared by hardware. The register
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
(4) AVDD pin input impedance
parallel connection to the series resistor string between the AVDD
pin and the AVSS pin, and there will be a large analog supply volt-
age error.
A series resistor string of approximately 5KΩ is connected be-
tween the AVDD pin and the AVSS pin. Therefore, if the output
impedance of the analog power source is high, this will result in
ADEN
AVDD
Resistor Ladder Circuit
AVSS
8-bit ADC
R60/AN0
R61/AN1
Successive
ADC
INTERRUPT
ADCIF
Approximation
Circuit
Sample & Hold
MUX
R66/AN6
R67/AN7
ADC8
0
1
10-bit Mode
9 8
8-bit Mode
3 2
ADS[4:2]
9 8
10-bit ADCR
10-bit ADCR
0 0
1 0
ADCRH
ADCRH
ADCRL (8-bit)
ADCRL (8-bit)
1 0
ADC Result Register
ADC Result Register
Figure 15-3 A/D Block Diagram
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
R/W R/W
-
R/W R/W R/W R/W
R
0
7
6
5
4
3
2
1
ADDRESS: 0EF
INITIAL VALUE: 00-0 0001
H
ADCM
ADS2 ADS1 ADS0
ADEN ADCK
-
ADST ADSF
B
A/D status bit
0: A/D conversion is in progress
1: A/D conversion is completed
A/D start bit
Setting this bit starts an A/D conversion.
After one cycle, bit is cleared to “0” by hardware.
Analog input channel select
000: Channel 0 (AN0)
001: Channel 1 (AN1)
010: Channel 2 (AN2)
011: Channel 3 (AN3)
100: Channel 4 (AN4)
101: Channel 5 (AN5)
110: Channel 6 (AN6)
111: Channel 7 (AN7)
A/D converter Clock Source Devide Ratio Selection bit
0: Clock Source f ÷ 4
PS
1: Clock Source f ÷ 8
PS
A/D converter Enable bit
0: A/D converter module turn off and current is not flow.
1: Enable A/D converter
W
7
W
6
R
1
R
0
W
5
4
-
3
2
-
ADDRESS: 0F0
INITIAL VALUE: 010- ----
H
ADCRH
-
PSSEL0
PSSEL1
ADC8
B
A/D Conversion High Data
ADC 8-bit Mode select bit
0: 10-bit Mode
1: 8-bit Mode
A/D Conversion Clock (f ) Source Selection
PS
00: f
01: f
10: f
11: f
XIN
XIN
XIN
XIN
÷ 2
÷ 4
÷ 8
R
5
R
4
R
3
R
2
R
1
R
0
R
7
R
6
ADDRESS: 0F1
INITIAL VALUE: Undefined
H
ADCRL
A/D Conversion Low Data
ADCK
PSSEL1
PSSEL0
PS Clock Selection
0
0
0
PS = f
PS = f
PS = f
PS = f
PS = f
PS = f
PS = f
PS = f
÷ 4
XIN
XIN
XIN
XIN
XIN
XIN
XIN
XIN
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷ 8
÷ 16
÷ 32
÷ 8
÷ 16
÷ 32
÷ 64
PS : Conversion Clock
Figure 15-4 A/D Converter Control & Result Register
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Preliminary
16. SERIAL INPUT/OUTPUT (SIO)
The serial Input/Output is used to transmit/receive 8-bit data se-
rially. The Serial Input/Output(SIO) module is a serial interface
useful for communicating with other peripheral of microcontrol-
ler devices. These peripheral devices may be serial EEPROMs,
shift registers, display drivers, A/D converters, etc. This SIO is 8-
bit clock synchronous type and consists of serial I/O data register,
serial I/O mode register, clock selection circuit, octal counter and
control circuit as illustrated in Figure 16-1. The SO pin is de-
signed to input and output. So the Serial I/O(SIO) can be operated
with minimum two pin. Pin R42/SCK, R43/SI, and R44/SO pins
are controlled by the Serial Mode Register. The contents of the
Serial I/O data register can be written into or read out by software.
The data in the Serial Data Register can be shifted synchronously
with the transfer clock signal.
SIOST
SIOSF
clear
SCK[1:0]
POL
Start
Complete
÷ 4
overflow
00
XIN PIN
SIO
CONTROL
CIRCUIT
÷ 16
“0”
“1”
01
Clock
Timer0
Overflow
Octal
Counter
(3-bit)
10
SIOIF
Clock
11
Serial communication
Interrupt
“11”
MUX
SCK PIN
not “11”
SCK[1:0]
IOSW
SM0
SOUT
SO PIN
SI PIN
IOSW
1
0
Input shift register
Shift
SIOR
Internal Bus
Figure 16-1 SIO Block Diagram
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Serial I/O Mode Register(SIOM) controls serial I/O function. Ac-
cording to SCK1 and SCK0, the internal clock or external clock
can be selected.
Serial I/O Data Register(SIOR) is an 8-bit shift register. First
LSB is send or is received.
R/W R/W
R/W R/W R/W R/W R/W
R
7
6
5
4
3
2
1
0
ADDRESS: 0E2
INITIAL VALUE: 0000 0001
H
SIOM
POL IOSW SM1 SM0 SCK1 SCK0
SIOST SIOSF
B
Serial transmission status bit
0: Serial transmission is in progress
1: Serial transmission is completed
Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to “0” by hardware.
Serial transmission Clock selection
00: f
01: f
÷ 4
÷ 16
XIN
XIN
10: TMR0OV(Timer0 Overflow)
11: External Clock
Serial transmission Operation Mode
00: Normal Port(R42,R43,R44)
01: Sending Mode(SCK,R43,SO)
10: Receiving Mode(SCK,SI,R44)
11: Sending & Receiving Mode(SCK,SI,SO)
Serial Input Pin Selection bit
0: SI Pin Selection
1: SO Pin Selection
Serial Clock Polarity Selection bit
0: Data Transmission at Falling Edge
Received Data Latch at Rising Edge
1: Data Transmission at Rising Edge
Received Data Latch at Falling Edge
R/W R/W R/W R/W R/W R/W R/W
R/W
7
6
5
4
3
2
1
0
ADDRESS: 0E3
INITIAL VALUE: Undefined
H
SIOR
Sending Data at Sending Mode
Receiving Data at Receiving Mode
Figure 16-2 SIO Control Register
16.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of SIOM)
to “1”. After one cycle of SCK, SIOST is cleared automatically
to “0”. At the default state of POL bit clear, the serial output data
from 8-bit shift register is output at falling edge of SCLK, and in-
put data is latched at rising edge of SCLK pin (Refer to Figure 16-
3). When transmission clock is counted 8 times, serial I/O counter
is cleared as ‘0”. Transmission clock is halted in “H” state and se-
rial I/O interrupt(SIOIF) occurred.
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Preliminary
SIOST
SCK [R42]
(POL=0)
D0
D1
D2
D3
D4
D5
D6
D7
SO [P44]
D0
D1
D2
D3
D4
D5
D6
D7
SI [R43]
(IOSW=0)
IOSWIN [P44]
(IOSW=1)
D0
D1
D2
D3
D4
D5
D6
D7
SIOSF
(SIO Status)
SIOIF
(SIO Int. Req)
Figure 16-3 Serial I/O Timing Diagram at POL=0
SIOST
SCK [R42]
(POL=1)
D0
D1
D2
D3
D4
D5
D6
D7
SO [R44]
SI [R43]
D0
D1
D2
D3
D4
D5
D6
D6
D7
D7
(IOSW=0)
IOSWIN [R44]
(IOSW=1)
D0
D1
D2
D3
D4
D5
SIOSF
(SIO Status)
SIOIF
(SIO Int. Req)
Figure 16-4 Serial I/O Timing Diagram at POL=1
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Preliminary
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16.2 The method of Serial I/O
1. Select transmission/receiving mode.
LDM
LDM
NOP
LDM
SIOR,#0AAh
;set tx data
2. In case of sending mode, write data to be send to SIOR.
3. Set SIOST to “1” to start serial transmission.
SIOM,#0011_1100b ;set SIO mode
SIOM,#0011_1110b ;SIO Start
4. The SIO interrupt is generated at the completion of SIO
and SIOIF is set to “1”. In SIO interrupt service routine,
correct transmission should be tested.
Note: When external clock is used, the frequency should
be less than 1MHz and recommended duty is 50%. If both
transmission mode is selected and transmission is per-
formed simultaneously, error will be made.
5. In case of receiving mode, the received data is acquired
by reading the SIOR.
16.3 The Method to Test Correct Transmission
Serial I/O Interrupt
Service Routine
0
SIOSF
1
Abnormal
SIOE = 0
Write SIOM
0
SIOIF
1
Overrun Error
Normal Operation
- SIOE: Interrupt Enable Register High IENH(Bit3)
- SIOIF: Interrupt Request Flag Register High IRQH(Bit3)
Figure 16-5 Serial IO Method to Test Transmission
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Preliminary
17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)
17.1 UART Serial Interface Functions
The Universal Asynchronous Receiver/Transmitter(UART) en-
Note: The UART1 control register ASIMR1,ASISR1,
ables full-duplex operation wherein one byte of data after the start
bit is transmitted and received. The on-chip baud rate generator
dedicated to UART enables communications using a wide range
of selectable baud rates. In addition, a baud rate can also be de-
fined by dividing clocks input to the ACLK pin.
BRGCR1, RXR1 and TXR1 are located at EE6H ~ EE9H
address. These address must be accessed(read and writ-
ten) by absolute addressing manipulation instruction.
The UART driver consists of RXR, TXR, ASIMR, ASISR and
BRGCR register. Clock asynchronous serial I/O mode (UART)
can be selected by ASIMR register. Figure 17-1 shows a block di-
agram of the UART driver.
Internal Data Bus
Receive Buffer Register
(RXR)
RxE
Receive Shift Register
(RX)
Transmit Shift Register
(TXR)
RxD PIN
TxD PIN
2
1
0
(ASISR)
PE
FE OVE
TxE
Transmit Controller
(Parity Addition)
TXxIOF
UARTxIF
(UARTx interrupt)
Receive Controller
(Parity Check)
RXxIOF
ACLK PIN
Baud Rate
Generator
7
f
/2 ~ f /2
XIN
XIN
Figure 17-1 UART Block Diagram
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
RECEIVE
RxE
ACLK PIN
5-bit counter
MUX
7
f
/2 ~ f /2
XIN
XIN
match
1/2
(Divider)
Tx_Clock
Decoder
match
1/2
(Divider)
Rx_Clock
-
TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
(BRGCR)
5-bit counter
TxE
Internal Data Bus
SEND
Figure 17-2 Baud Rate Generator Block Diagram
R/W R/W
R/W R/W
R/W R/W
ADDRESS: 0DF
INITIAL VALUE: --00 0000
H
-
-
RX0IOF TX0IOF RX1IOF TX1IOF WTIOF WDTIOF
IFR
B
LSB
MSB
NOTE1
NOTE1
WDT interrupt occurred flag
WT interrupt occurred flag
NOTE2
UART1 Tx interrupt occurred flag
UART1 Rx interrupt occurred flag
NOTE2
NOTE3
UART0 Tx interrupt occurred flag
UART0 Rx interrupt occurred flag
NOTE3
NOTE1 :
In case of using interrupts of Watchdog Timer and Watch Timer together, it is
necessary to check IFR in interrupt service routine to find out which interrupt is
occurred, because the Watchdog timer and Watch timer is shared with interrupt
vector address. These flag bits must be cleared by software after reading this
register.
NOTE2 :
NOTE3 :
In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary
to check IFR in interrupt service routine to find out which interrupt is occurred,
because the UART1 Tx and UART1 Rx is shared with interrupt vector address.
These flag bits must be cleared by software after reading this register.
In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary
to check IFR in interrupt service routine to find out which interrupt is occurred,
because the UART0 Tx and UART0 Rx is shared with interrupt vector address.
These flag bits must be cleared by software after reading this register.
Figure 17-3 IFR : Interrupt Flag Register
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Preliminary
17.2 Serial Interface Configuration
The UART interface consists of the following hardware.
receive shift register (RXSR). When the data length is set as 7
bits, receive data is sent to bits 0 to 6 of RXR0. In this case, the
MSB of RXR always becomes 0.
RXR can be read by an 8 bit memory manipulation instruction. It
cannot be written. The RESET input sets RXR0 to 00H.
Item
Configuration
Transmit shift register (TXR)
Receive buffer register (RXR)
Receive shift register
Register
Note: The same address is assigned to RXR and the
transmit shift register (TXR). During a write operation, val-
ues are written to TXR.
Serial interface mode register (ASIMR)
Serial interface status register (ASISR)
Baudrate generator control register (BRGCR)
Control
register
Receive shift register
Table 17-1 Serial Interface Configuration
This register converts serial data input via the RxD pin to paral-
leled data. When one byte of data is received at this register can-
not be manipulated directly by a program.
Transmit shift register (TXR)
This is the register for setting transmit data. Data written to TXR0
is transmitted as serial data. When the data length is set as 7 bit,
bit 0 to 6 of the data written to TX0 are transferred as transmit da-
ta. Writing data to TXR0 starts the transmit operation.
Asynchronous serial interface mode register
(ASIMR)
TXR0 can be written by an 8 bit memory manipulation instruc-
tion. It cannot be read. The RESET input sets TXR0 to 0FFH.
This is an 8 bit register that controls UART serial transfer opera-
tion. ASIMR is set by a 1 bit or 8 bit memory manipulation in-
truction. The RESET input sets ASIMR to 0000_-00-B. Table 17-
4 shows the format of ASIMR.
Note: Do not write to TXR during a transmit operation. The
same address is assigned to TXR and the receive buffer
register (RXR). A read operation reads values from RXR.
Note: Do not switch the operation mode until the current
serial transmit/receive operation has stopped.
Receive buffer register (RXR)
.
This register is used to hold receive data. When one byte of data
is received, one byte of new receive data is transferred from the
R/W R/W
R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0E6
INITIAL VALUE: 0000 -00-
H
ASIMR0
-
TXE0 RXE0 PS01 PS00
SL0
ISRM0
-
B
UART0 Receive interrupt request is issued when an error occurs bit
0: Receive Completion Interrupt Control When Error occurs
1: Receive completion interrupt request is not issued when an error occur
UART0 Stop Bit Length for Specification for Transmit Data bit
0: 1 bit
1: 2 bit
UART0 Parity Bit Specification bit
00: No parity
01: Zero parity always added during transmission.
No parity detection during reception (parity errors do not occur)
10: Odd parity
11: Even parity
UART0 Tx/Rx Enable bit
00: Not used UART0 (R46, R47)
01: UART0 Receive only Mode(RxD, R47)
10: UART0 Transmit only Mode(R46, TxD)
11: UART0 Receive & Transmit Mode(RxD, TxD)
Figure 17-4 Asynchronous Serial Interface Mode register (ASIMR0) Format
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MAR. 2005 Ver 0.2
Preliminary
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Asynchronous serial interface status register0 (ASISR)
When a receive error occurs during UART mode, this register in-
dicates the type of error. ASISR can be read by an 8 bit memory
manipulation instruction. The RESET input sets ASISR0 to -----
000B. Figure 17-5 shows the format of ASISR.
.
R
R
1
R
7
-
6
-
5
-
4
3
2
0
ADDRESS: 0E7
INITIAL VALUE: ---- -000
H
ASISR0
-
-
PE0
FE0 OVE0
B
UART0 Parity Error Flag
0: No parity error
1: Parity error (Transmit data parity not matched)
UART0 Frame Error Flag
0: No Frame error
Note1
1: Framing error
(stop bit not detected)
UART0 Overrun Error Flag
0: No overrun error
Note2
1: Overrun error
(Next receive operation was completed before data was read
from receive buffer register (RXR))
Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in
ASIMR, stop bit detection during a recive operation only applies
to a stop bit length of 1bit.
2. Be sure to read the contents of the receive buffer register(RXR)
when an overrun error has occurred.
Until the contents of RXR are read, futher overrun errors will
occur when receiving data.
Figure 17-5 Asynchronous Serial Interface Status Register (ASISR) Format
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Preliminary
Baud rate generator control register (BRGCR)
This register sets the serial clock for serial interface. BRGCR is
set by an 8 bit memory manipulation instruction. The RESET in-
put sets BRGCR to -001_0000B.
Figure 17-6 shows the format of BRGCR.
.
R
R
1
R
7
-
6
5
4
3
2
0
ADDRESS: 0E8
INITIAL VALUE: -001 0000
H
BRGCR0
TPS02 TPS01 TPS00 MDL03MDL02
MDL01MDL00
B
UART0 Input Clock Selection
0000: f
0001: f
0010: f
0011: f
0100: f
0101: f
0110: f
0111: f
1000: f
1001: f
1010: f
1011: f
1100: f
1101: f
1110: f
/ 16
/ 17
/ 18
/ 19
/ 20
/ 21
/ 22
/ 23
/ 24
/ 25
/ 26
/ 27
/ 28
/ 29
/ 30
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
1111: Setting prohibited
UART0 Source Clock Selection for 5 bit count
000: ACLK/R45
001: f
010: f
011: f
100: f
101: f
110: f
111: f
/ 2
/ 4
/ 8
/ 16
/ 32
/ 64
/ 128
XIN
XIN
XIN
XIN
XIN
XIN
XIN
Writing to BRGCR0 during a communication operation may cause abnormal output from the baud rate generator and
disable further communication operations. Therefore, do not write to BRGCR0 during a communication operation.
Caution
Remarks 1. f
: Source clock for 5 bit counter
SCK
2. n : Value set via TPS0 to TPS2 ( 0 ≤ n ≤ 7 )
3. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 )
Figure 17-6 Baud Rate Generator Control Register0(BRGCR) Format
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Preliminary
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17.3 Communication operation
The transmit operation is enabled when bit 7 (TXE0) of the asyn-
chronous serial interface mode register (ASIMR) is set to 1. The
transmit operation is started when transmit data is written to the
transmit shift register (TXR). The timing of the transmit comple-
tion interrupt request is shown in Figure 17-8.
UART0(UART1)
Interrupt Request
The receive operation is enabled when bit 6 (RXE0) of the asyn-
chronous serial interface mode register (ASIMR) is set to 1, and
input via the RxD pin is sampled. The serial clock specified by
ASIMR is used to sample the RxD pin. Once reception of one
data frame is completed, a receive completion interrupt request
(INT_RX0) occurs. Even if an error has occurred, the receive
data in which the error occurred is still transferred to RXR. When
ASIMR bit 1 (ISRM0) is cleared to 0 upon occurrence of an error,
and INT_RX0 occurs. When ISRM bit is set to 1, INT_RX0 does
not occur in case of error occurrence. Figure 17-8 shows the tim-
ing of the asynchronous serial interface receive completion inter-
rupt request.
=0
Tx0IOF(Tx1IOF)
=1
Tx0(Tx1) Interrupt
Routine
Clear Tx0IOF(Tx1IOF)
=0
Rx0IOF(Rx1IOF)
=1
In case of using interrupts of UART0 Tx and UART0 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART0 Tx and
UART0 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register.
Rx0(Rx1) Interrupt
Routine
Clear Rx0IOF(Rx1IOF)
RETI
In case of using interrupts of UART1 Tx and UART1 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART1 Tx and
UART1 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register.
Figure 17-7 Shared Interrupt Vector of UART
Each processing step is determined by IFR as shown in Figure 17-
7.
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Preliminary
1. Stop bit Length : 1 bit
1 data frame
TxD
RxD
Start
Parity
Stop
D0
D1
D2
D3
D4
D5
D6
D7
character bits
TX
INTERRUPT
RX
INTERRUPT
2. Stop bit Length : 2 bit
1 data frame
TxD
RxD
Start
Parity
Stop
D0
D1
D2
D3
D4
D5
D6
D7
character bits
TX
INTERRUPT
RX
INTERRUPT
3. Stop bit Length : 1 bit, No parity
1 data frame
TxD
RxD
Start
Stop
D0
D1
D2
D3
D4
D5
D6
D7
character bits
TX
INTERRUPT
RX
INTERRUPT
1 data frame consists of following bits.
- Start bit : 1 bit
- Character bits : 8 bits
- Parity bit : Even parity, Odd parity, Zero parity, No parity
- Stop bit(s) : 1 bit or 2 bits
Figure 17-8 UART data format and interrupt timing diagram
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17.4 Relationship between main clock and baud rate
The transmit/receive clock that is used to generate the baud rate
is obtained by dividing the main system clock. Transmit/Receive
clock generation for baud rate is made by using main system
clock which is divided. The baud rate generated from the main
system clock is determined according to the following formula.
f
=11.0592M
ERR
f
=10.0M
f
=8.0M
f
=6.0M
f
=4.0M
f
=2.0M
XIN
XIN
XIN
XIN
XIN
XIN
Baud Rate
(bps)
ERR
(%)
ERR
(%)
ERR
(%)
ERR
(%)
ERR
(%)
BRGCR
BRGCR
BRGCR
BRGCR
BRGCR
BRGCR
(%)
600
1200
-
-
-
-
-
-
-
-
7AH
6AH
5AH
4AH
3AH
2AH
20H
1AH
11H
-
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
2.12
-
6AH
5AH
4AH
3AH
2AH
1AH
10H
-
0.16
0.16
0.16
0.16
0.16
0.16
0.00
-
-
-
-
-
7AH
6AH
5AH
4AH
3AH
30H
2AH
21H
1AH
11H
0.16
0.16
0.16
0.16
0.16
0.00
0.16
2.11
0.16
2.12
74H
64H
54H
44H
34H
28H
24H
1AH
14H
-
2.34
2.34
2.34
2.34
2.34
0.00
2.34
0.16
2.34
-
2400
72H
62H
52H
42H
36H
32H
28H
22H
18H
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
0.00
70H
60H
50H
40H
34H
30H
26H
20H
16H
1.73
1.73
1.73
1.73
0.00
1.73
1.35
1.73
1.36
4800
9600
19200
31250
38400
57600
76800
115200
-
-
-
-
-
-
-
-
n+1
Baud Rate = f
/ ( 2 (k+16) )
XIN
Remarks 1. f
: Main system clock oscillation frequency
XIN
When ACLK is selected as the source clock of the 5-bit counter,
substitute the input clock frequency to ACLK pin for in the above expression.
2. f
: Source clock for 5 bit counter
SCK
3. n : Value set via TPS00 to TPS02 ( 0 ≤ n ≤ 7 )
4. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 )
Figure 17-9 Relationship between main clock and Baud Rate
MAR. 2005 Ver 0.2
83
MC80F0208/16/24
Preliminary
18. BUZZER FUNCTION
The buzzer driver block consists of 6-bit binary counter, buzzer
register BUZR, and clock source selector. It generates square-
wave which has very wide range frequency (488Hz ~ 250kHz at
The bit 0 to 5 of BUZR determines output frequency for buzzer
driving.
Equation of frequency calculation is shown below.
f
XIN= 4MHz) by user software.
f
XIN
A 50% duty pulse can be output to R13/BUZO pin to use for pi-
ezo-electric buzzer drive. Pin R13 is assigned for output port of
Buzzer driver by setting the bit 2 of PSR1(address 0F9H) to “1”.
For PSR1 register, refer to Figure 18-2.
f
= ---------------------------------------------------------------------------
BUZ
2 × DivideRatio × (BUR + 1)
f
f
: Buzzer frequency
BUZ
: Oscillator frequency
Example: 5kHz output at 4MHz.
XIN
Divide Ratio: Prescaler divide ratio by BUCK[1:0]
LDM
LDM
BUZR,#0011_0001B
PSR1,#XXXX_X1XXB
BUR: Lower 6-bit value of BUZR. Buzzer period value.
The frequency of output signal is controlled by the buzzer control
register BUZR. The bit 0 to bit 5 of BUZR determine output fre-
quency for buzzer driving.
X means don’t care
R13 port data
÷ 8
6-BIT BINARY
COUNTER
00
÷ 16
MUX
01
XIN PIN
÷ 32
0
10
R13/BUZO PIN
F/F
1
÷ 64
11
Comparator
MUX
2
Compare data
BUZO
6
Port selection register 1
PSR1
BUR
[0F9 ]
H
[0E0 ]
H
Internal bus line
Figure 18-1 Block Diagram of Buzzer Driver
ADDRESS: 0E0
H
RESET VALUE: 0FF
ADDRESS: 0F9
H
H
RESET VALUE: ---- -0--
B
W
W
W
W
W
W
W
W
-
-
-
-
-
-
-
BUZO
BUCK1
BUCK0
PSR1
BUZR
BUR[5:0]
Buzzer Period Data
R13/BUZO Selection
0: R13 port (Turn off buzzer)
1: BUZO port (Turn on buzzer)
Source clock select
00: f
01: f
10: f
11: f
÷ 8
XIN
XIN
XIN
XIN
÷ 16
÷ 32
÷ 64
Figure 18-2 Buzzer Register & PSR1
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
The 6-bit counter is cleared and starts the counting by writing sig-
nal at BUZR register. It is incremental from 00H until it matches
6-bit BUR value.
When main-frequency is 4MHz, buzzer frequency is shown as
below Table 18-1.
BUR[7:6]
BUR
BUR[7:6]
BUR
[5:0]
[5:0]
00
01
10
11
00
01
10
11
00
01
02
03
04
05
06
07
250.000
125.000
83.333
62.500
50.000
41.667
35.714
31.250
125.000
62.500
41.667
31.250
25.000
20.833
17.857
15.625
62.500
31.250
20.833
15.625
12.500
10.417
8.929
31.250
15.625
10.417
7.813
6.250
5.208
4.464
3.906
20
21
22
23
24
25
26
27
7.576
7.353
7.143
6.944
6.757
6.579
6.410
6.250
3.788
3.676
3.571
3.472
3.378
3.289
3.205
3.125
1.894
1.838
1.786
1.736
1.689
1.645
1.603
1.563
0.947
0.919
0.893
0.868
0.845
0.822
0.801
0.781
7.813
08
09
0A
0B
0C
0D
0E
0F
27.778
25.000
22.727
20.833
19.231
17.857
16.667
15.625
13.889
12.500
11.364
10.417
9.615
8.929
8.333
7.813
6.944
6.250
5.682
5.208
4.808
4.464
4.167
3.906
3.472
3.125
2.841
2.604
2.404
2.232
2.083
1.953
28
29
2A
2B
2C
2D
2E
2F
6.098
5.952
5.814
5.682
5.556
5.435
5.319
5.208
3.049
2.976
2.907
2.841
2.778
2.717
2.660
2.604
1.524
1.488
1.453
1.420
1.389
1.359
1.330
1.302
0.762
0.744
0.727
0.710
0.694
0.679
0.665
0.651
10
11
12
13
14
15
16
17
14.706
13.889
13.158
12.500
11.905
11.364
10.870
10.417
7.353
6.944
6.579
6.250
5.952
5.682
5.435
5.208
3.676
3.472
3.289
3.125
2.976
2.841
2.717
2.604
1.838
1.736
1.645
1.563
1.488
1.420
1.359
1.302
30
31
32
33
34
35
36
37
5.102
5.000
4.902
4.808
4.717
4.630
4.545
4.464
2.551
2.500
2.451
2.404
2.358
2.315
2.273
2.232
1.276
1.250
1.225
1.202
1.179
1.157
1.136
1.116
0.638
0.625
0.613
0.601
0.590
0.579
0.568
0.558
18
19
1A
1B
1C
1D
1E
1F
10.000
9.615
9.259
8.929
8.621
8.333
8.065
7.813
5.000
4.808
4.630
4.464
4.310
4.167
4.032
3.906
2.500
2.404
2.315
2.232
2.155
2.083
2.016
1.953
1.250
1.202
1.157
1.116
1.078
1.042
1.008
0.977
38
39
3A
3B
3C
3D
3E
3F
4.386
4.310
4.237
4.167
4.098
4.032
3.968
3.907
2.193
2.155
2.119
2.083
2.049
2.016
1.984
1.953
1.096
1.078
1.059
1.042
1.025
1.008
0.992
0.977
0.548
0.539
0.530
0.521
0.512
0.504
0.496
0.488
Table 18-1 buzzer frequency (kHz unit)
MAR. 2005 Ver 0.2
85
MC80F0208/16/24
19. INTERRUPTS
Preliminary
The MC80F0208/16/24 interrupt circuits consist of Interrupt en-
able register (IENH, IENL), Interrupt request flags of IRQH,
IRQL, Priority circuit, and Master enable flag (“I” flag of PSW).
Fifteen interrupt sources are provided. The configuration of inter-
rupt circuit is shown in Figure 19-1 and interrupt priority is
shown in Table 19-1.
The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF,
T2IF, T3IF and T4IF which is set by a match in their respective
timer/counter register.
The Basic Interval Timer Interrupt is generated by BITIF which
is set by an overflow in the timer register.
The AD converter Interrupt is generated by ADCIF which is set
by finishing the analog to digital conversion.
The External Interrupts INT0 ~ INT3 each can be transition-acti-
vated (1-to-0 or 0-to-1 transition) by selection IEDS register.
The flags that actually generate these interrupts are bit INT0IF,
INT1IF, INT2IF and INT3IF in register IRQH. When an external
interrupt is generated, the generated flag is cleared by the hard-
ware when the service routine is vectored to only if the interrupt
was transition-activated.
The Watchdog timer and Watch Timer Interrupt is generated by
WDTIF and WTIF which is set by a match in Watchdog timer
register or Watch timer register. The IFR(Interrupt Flag Register)
is used for discrimination of the interrupt source among these two
Watchdog timer and Watch Timer Interrupt.
Internal bus line
[0EA ]
H
I-flag is in PSW, it is cleared by “DI”, set by
Interrupt Enable
Register (Higher byte)
“EI” instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
IENH
IRQH
[0EC ]
H
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
INT0IF
INT1IF
INT2IF
INT3IF
UART0IF
UART1IF
SIOIF
INT0
INT1
INT2
INT3
Release STOP/SLEEP
UART0 Tx/Rx
UART1 Tx/Rx
To CPU
Serial
Communication
I-flag
Timer 0
T0IF
Interrupt Master
Enable Flag
IRQL
[0ED ]
H
Timer 1
Timer 2
Timer 3
T1IF
T2IF
Interrupt
Vector
Address
Generator
T3IF
Timer 3
T4IF
A/D Converter
Watchdog Timer
Watch Timer
ADCIF
WDTIF
WTIF
BITIF
BIT
Interrupt Enable
Register (Lower byte)
IENL
[0EB ]
H
Internal bus line
Figure 19-1 Block Diagram of Interrupt
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
The Basic Interval Timer Interrupt is generated by BITIF which
is set by a overflow in the timer counter register.
The UART0 receive/transmit interrupt is generated by UART0IF
is set by completion of UART0 data reception or transmission.
The IFR(Interrupt Flag Register) is used for discrimination of the
interrupt source among these two UART0 receive and UART0
transmit Interrupt.
Reset/Interrupt
Hardware Reset
Symbol
Priority
RESET
INT0
INT1
INT2
INT3
UART0
UART1
SIO
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
ADC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
UART0 Rx/Tx Interrupt
UART1 Rx/Tx Interrupt
Serial Input/Output
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
Timer/Counter 4
The SIO interrupt is generated by SIOIF which is set by comple-
tion of SIO data reception or transmission.
The interrupts are controlled by the interrupt master enable flag
I-flag (bit 2 of PSW on Figure 8-3), the interrupt enable register
(IENH, IENL), and the interrupt request flags (in IRQH and
IRQL) except Power-on reset and software BRK interrupt. The
Table 19-1 shows the Interrupt priority.
Vector addresses are shown in Figure 8-6. Interrupt enable regis-
ters are shown in Figure 19-2. These registers are composed of in-
terrupt enable flags of each interrupt source and these flags
determines whether an interrupt will be accepted or not. When
enable flag is “0”, a corresponding interrupt source is prohibited.
Note that PSW contains also a master enable bit, I-flag, which
disables all interrupts at once.
ADC Interrupt
Watchdog/Watch Timer
Basic Interval Timer
WDT_WT
BIT
Table 19-1 Interrupt Priority
R/W R/W
R/W R/W R/W R/W R/W R/W
ADDRESS: 0EA
INITIAL VALUE: 0000 0000
H
INT0E INT1E INT2E INT3E UART0E UART1E
SIOE T0E
IENH
B
MSB
LSB
Timer/Counter 0 interrupt enable flag
Serial Communication interrupt enable flag
UART1 Tx/Rx interrupt enable flag
UART0 Tx/Rx interrupt enable flag
External interrupt 0 enable flag
External interrupt 1 enable flag
External interrupt 2 enable flag
External interrupt 3 enable flag
R/W R/W
T1E T2E T3E T4E ADCE WDTE WTE BITE
LSB
R/W R/W
R/W R/W
R/W R/W
ADDRESS: 0EB
INITIAL VALUE: 0000 0000
H
IENL
B
MSB
Basic Interval Timer interrupt enable flag
Watch timer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Converter interrupt enable flag
Timer/Counter 4 interrupt enable flag
Timer/Counter 3 interrupt enable flag
Timer/Counter 2 interrupt enable flag
Timer/Counter 1 interrupt enable flag
Figure 19-2 Interrupt Enable Flag Register
MAR. 2005 Ver 0.2
87
MC80F0208/16/24
Preliminary
R/W R/W
R/W R/W R/W R/W R/W R/W
ADDRESS: 0EC
INITIAL VALUE: 0000 0000
H
UART0IF UART1IF
INT0IF INT1IF INT2IF INT3IF
SIOIF
T0IF
LSB
IRQH
B
MSB
Timer/Counter 0 interrupt request flag
Serial Communication interrupt request flag
UART1Tx/Rx interrupt request flag
UART0 Tx/Rx interrupt request flag
External interrupt 3 request flag
External interrupt 2 request flag
External interrupt 1 request flag
External interrupt 0 request flag
R/W R/W
R/W R/W
R/W R/W
R/W R/W
ADDRESS: 0ED
INITIAL VALUE: 0000 0000
H
T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF
LSB
IRQL
B
MSB
Basic Interval Timer interrupt request flag
Watch timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
Timer/Counter 4 interrupt request flag
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
R/W R/W
R/W R/W
R/W R/W
ADDRESS: 0DF
INITIAL VALUE: --00 0000
H
-
-
RX0IOF TX0IOF RX1IOF TX1IOF WTIOF WDTIOF
IFR
B
LSB
MSB
NOTE1
WDT interrupt occurred flag
NOTE1
WT interrupt occurred flag
NOTE2
NOTE2
UART1 Tx interrupt occurred flag
UART1 Rx interrupt occurred flag
UART0 Tx interrupt occurred flag
UART0 Rx interrupt occurred flag
NOTE3
NOTE3
NOTE1 :
In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in
interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch
timer is shared with interrupt vector address. These flag bits must be cleared by software after read-
ing this register.
NOTE2 :
NOTE3 :
In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt
service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared
with interrupt vector address. These flag bits must be cleared by software after reading this register.
Figure 19-3 Interrupt Request Flag Register & Interrupt Flag Register
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to “0” by a reset or an instruction. Inter-
rupt acceptance sequence requires 8 cycles of fXIN (2µs at fX-
IN=4MHz) after the completion of the current instruction
execution. The interrupt service task is terminated upon execu-
tion of an interrupt return instruction [RETI].
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
19.1.1 Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
3. The contents of the program counter (return address)
System clock
Instruction Fetch
SP-2
PSW
V.L.
V.H.
New PC
OP code
SP
SP-1
PC
Address Bus
Data Bus
Not used
PCH
PCL
V.L.
ADL
ADH
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 19-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
A interrupt request is not accepted until the I-flag is set to “1”
Basic Interval Timer
Vector Table Address
even if a requested interrupt has higher priority than that of the
current interrupt being serviced.
Entry Address
When nested interrupt service is required, the I-flag should be set
to “1” by “EI” instruction in the interrupt service program. In this
case, acceptable interrupt sources are selectively enabled by the
individual interrupt enable flags.
012
0FFE0
0FFE1
H
H
0E
H
0E312
0E313
H
0E3
H
H
2E
H
H
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
19.1.2 Saving/Restoring General-purpose Register
During interrupt acceptance processing, the program counter and
the program status word are automatically saved on the stack, but
accumulator and other registers are not saved itself. These regis-
ters are saved by the software if necessary. Also, when multiple
interrupt services are nested, it is necessary to avoid using the
same data memory area for saving registers.
registers.
Example: Register save using push and pop instructions
INTxx: PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
PUSH
The following method is used to save/restore the general-purpose
MAR. 2005 Ver 0.2
89
MC80F0208/16/24
Preliminary
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
main task
acceptance of
interrupt
interrupt
service task
saving
registers
General-purpose register save/restore using push and pop instruc-
tions;
restoring
registers
interrupt return
19.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
=0
B-FLAG
=1
BRK
INTERRUPT
ROUTINE
BRK or
TCALL0
Each processing step is determined by B-flag as shown in Figure
19-5.
TCALL0
ROUTINE
RETI
RET
Figure 19-5 Execution of BRK/TCALL0
19.3 Shared Interrupt Vector
In case of using interrupts of Watchdog Timer and Watch Timer
together, it is necessary to check IFR in interrupt service routine
to find out which interrupt is occurred, because the Watchdog
timer and Watch timer is shared with interrupt vector address.
These flag bits must be cleared by software after reading this reg-
ister.
out which interrupt is occurred, because the UART0 Tx and
UART0 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register.
In case of using interrupts of UART1 Tx and UART1 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART1 Tx and
UART1 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register. Each
In case of using interrupts of UART0 Tx and UART0 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
processing step is determined by IFR as shown in Figure 19-6.
UART0(UART1)
Interrupt Request
WDT or WT
Interrupt Request
=0
Tx0IOF(Tx1IOF)
=1
Tx0(Tx1) Interrupt
Routine
=0
=0
WDTIF
=1
WTIF
=1
Clear Tx0IOF(Tx1IOF)
WDT Interrupt
Routine
WDT Interrupt
Routine
=0
Clear WDTIF
Clear WTIF
Rx0IOF(Rx1IOF)
=1
Rx0(Rx1) Interrupt
Routine
RETI
Clear Rx0IOF(Rx1IOF)
RETI
Figure 19-6 Software Flowchart of Shared Interrupt Vector
19.4 Multi Interrupt
If two requests of different priority levels are received simulta-
neously, the request of higher priority level is serviced. If re-
quests of the interrupt are received at the same time
simultaneously, an internal polling sequence determines by hard-
ware which request is serviced. However, multiple processing
through software for special features is possible. Generally when
an interrupt is accepted, the I-flag is cleared to disable any further
interrupt. But as user sets I-flag in interrupt routine, some further
interrupt can be serviced even if certain interrupt is in progress.
Main Program
service
TIMER 1
service
INT0
service
enable INT0
disable other
EI
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Occur
TIMER1 interrupt
Occur
INT0
enable INT0
enable other
Figure 19-7 Execution of Multi Interrupt
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
Example: During Timer1 interrupt is in progress, INT0 interrupt
:
serviced without any suspend.
:
TIMER1: PUSH
A
:
PUSH
PUSH
LDM
LDM
EI
X
:
Y
LDM
LDM
POP
POP
POP
RETI
IENH,#0FFH ;Enable all interrupts
IENL,#0FFH
Y
X
A
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other int.
;Enable Interrupt
:
:
19.5 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins are
edge triggered depending on the edge selection register IEDS (ad-
dress 0EEH) as shown in Figure 19-8.
The edge detection of external interrupt has three transition acti-
vated mode: rising edge, falling edge, and both edge.
01
10
INT0 pin
INT0IF
INT0 INTERRUPT
INT1 INTERRUPT
11
01
INT1 pin
INT1IF
10
11
01
INT2 pin
INT2IF
INT3IF
10
INT2 INTERRUPT
INT3 INTERRUPT
11
01
INT3 pin
10
11
2
2
2
2
Edge selection
Register
IEDS
[0EEH]
Figure 19-8 External Interrupt Block Diagram
INT0 ~ INT3 are multiplexed with general I/O ports (R10, R11,
Response Time
R12, R50). To use as an external interrupt pin, the bit of port se-
lection register PSR0 should be set to “1” correspondingly.
The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every
machine cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and conditions
are right for it to be acknowledged, a hardware subroutine call to
the requested service routine will be the next instruction to be ex-
ecuted. The DIV itself takes twelve cycles. Thus, a minimum of
twelve complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution of the
first instruction of the service routine.
Example: To use as an INT0 and INT2
:
;**** Set external interrupt port as pull-up state.
LDM
;
PU1,#0000_0101B
;**** Set port as an external interrupt port
LDM
;
PSR0,#0000_0101B
Figure 19-9 shows interrupt response timings.
;**** Set Falling-edge Detection
LDM
:
IEDS,#0001_0001B
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
max. 12 f
8 f
XIN
XIN
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
Figure 19-9 Interrupt Response Timing Diagram
MSB
W
LSB
W
W
W
W
W
W
W
ADDRESS: 0EE
INITIAL VALUE: 00
H
IEDS
IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L
INT3 INT2 INT1 INT0
H
Edge selection register
00: Reserved
01: Falling (1-to-0 transition)
10: Rising (0-to-1 transition)
11: Both (Rising & Falling)
W
W
-
W
W
W
W
W
W
ADDRESS: 0F8
INITIAL VALUE: 0-00 0000
H
PSR0
PWM3O
EC1E EC0E INT3E INT2E INT1E INT0E
LSB
0: R10
B
MSB
0: R54
1: PWM3O/T3O
1: INT0
0: R11
1: INT1
0: R12
1: INT2
0: R51
1: EC1
0: R50
1: INT3
0: R15
1: EC0
Figure 19-10 IEDS register and Port Selection Register PSR0
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
20. OPERATION MODE
The system clock controller starts or stops the main-frequency
clock oscillator. The operating mode is generally divided into the
main active mode. Figure 20-1 shows the operating mode transi-
tion diagram.
SLEEP Mode
In this mode, the CPU clock stops while peripherals and the os-
cillation source continues to operate normally.
System clock control is performed by the system clock mode reg-
ister, SCMR. During reset, this register is initialized to “0” so that
the main-clock operating mode is selected.
STOP Mode
In this mode, the system operations are all stopped, holding the
internal states valid immediately before the stop at the low power
consumption level. The main oscillation source stops, but the sub
clock oscillation and watch timer by sub clock and RC-oscillated
watchdog timer don’t stop.
Main Active Mode
This mode is fast-frequency operating mode. The CPU and the
peripheral hardware are operated on the high-frequency clock. At
reset release, this mode is invoked.
* Note1 : Stop released by Reset,
Watch Timer, Watchdog Timer
Timer(event counter), External interrupt,
SIO (External clock), UART0, UART1
* Note2 : Sleep released by
Reset, or All interrupts
* Note3
Main Active
Mode
Stop / Sleep
Mode
* Note3 :
1) Stop mode Admission
LDM SSCR, #5AH
* Note1 / * Note2
STOP
NOP
NOP
Main : Oscillation or Stop
Sub : Oscillation
System Clock : Stop
Main : Oscillation
Sub : Oscillation or stop
System Clock : Main
2) Sleep mode Admission
LDM SSCR, #0FH
Figure 20-1 Operating Mode
20.1 Operation Mode Switching
In the Main active mode, only the high-frequency clock oscillator
is used. In the Sub active mode, the low-frequency clock oscilla-
tion is used, so the low power voltage operation or the low power
consumption operation can be enabled. Instruction execution
does not stop during the change of operation mode. In this case,
some peripheral hardware capabilities may be affected. For de-
tails, refer to the description of the relevant operation.
The following describes the switching between the Main active
mode and the Sub active mode. During reset, the system clock
mode register is initialized at the Main active mode. It must be set
to the Sub active mode for reducing the power consumption.
Shifting from the Normal operation to the SLEEP mode
If the CPU clock stops and the SLEEP mode is invoked, the CPU
stops while other peripherals are operate normally.
to low and all available interrupts. For more detail, See "21.
POWER SAVING OPERATION" on page 95.
The ways of release from this mode are by setting the RESET pin
Shifting from the Normal operation to the STOP mode
If the main-frequency clock oscillation stops and the STOP mode
is invoked, the CPU stops and other peripherals are stop too. But
sub-frequency clock oscillation operate continuously if enabled
previously. After the STOP operation is released by reset, the op-
eration mode is changed to Main active mode.
The methods of release from this mode are Reset, Watch Timer,
Timer/Event counter, SIO(External clock), UART, and External
Interrupt.
Note: In the STOP and SLEEP operating modes, the pow-
er consumption by the oscillator and the internal hardware
is reduced. However, the power for the pin interface (de-
pending on external circuitry and program) is not directly
associated with the low-power consumption operation. This
must be considered in system design as well as interface
circuit design.
For more details, see "21. POWER SAVING OPERATION" on
page 95.
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
21. POWER SAVING OPERATION
The MC80F0208/16/24 has two power-down modes. In power-
down mode, power consumption is reduced considerably. For ap-
plications where power consumption is a critical factor, device
provides two kinds of power saving functions, STOP mode and
SLEEP mode. Table 21-1 shows the status of each Power Saving
Mode. SLEEP mode is entered by the SSCR register to “0Fh”.,
and STOP mode is entered by STOP instruction after the SSCR
register to “5Ah”.
21.1 Sleep Mode
In this mode, the internal oscillation circuits remain active.
Oscillation continues and peripherals are operate normally but
CPU stops. Movement of all peripherals is shown in Table 21-1.
SLEEP mode is entered by setting the SSCR register to “0Fh”. It
is released by Reset or interrupt. To be released by interrupt, in-
terrupt should be enabled before SLEEP mode.
W
7
W
6
W
5
W
4
W
3
W
2
W
W
0
1
ADDRESS: 0F5
H
SSCR
INITIAL VALUE: 0000 0000
B
Power Down Control
5A : STOP mode
H
0F : SLEEP mode
H
NOTE :
To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution.
At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released.
To get into SLEEP mode, SSCR must be set to 0FH.
Figure 21-1 STOP and SLEEP Control Register
When exit from SLEEP mode by reset, enough oscillation stabi-
lization time is required to normal operation. Figure 21-3 shows
the timing diagram. When released from the SLEEP mode, the
Basic interval timer is activated on wake-up. It is increased from
00H until FFH. The count overflow is set to start normal opera-
tion. Therefore, before SLEEP instruction, user must be set its
relevant prescaler divide ratio to have long enough time (more
than 20msec). This guarantees that oscillator has started and sta-
bilized. By interrupts, exit from SLEEP mode is shown in Figure
21-2. By reset, exit from SLEEP mode is shown in Figure 21-3.
Release the SLEEP mode
The exit from SLEEP mode is hardware reset or all interrupts.
Reset re-defines all the Control registers but does not change the
on-chip RAM. Interrupts allow both on-chip RAM and Control
registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If I-flag =
0, the chip will resume execution starting with the instruction fol-
lowing the SLEEP instruction. It will not vector to interrupt serv-
ice routine. (refer to Figure 21-4)
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
.
Oscillator
(XIN pin)
Internal Clock
External Interrupt
SLEEP Instruction
Executed
Normal Operation
SLEEP Operation
Normal Operation
Figure 21-2 SLEEP Mode Release Timing by External Interrupt
Oscillator
(XIN pin)
CPU
Clock
RESET
Internal
RESET
SLEEP Instruction
Execution
Stabilization Time
= 65.5mS @4MHz
t
ST
Normal Operation
Normal Operation
SLEEP Operation
Figure 21-3 Timing of SLEEP Mode Release by Reset
21.2 Stop Mode
In the Stop mode, the main oscillator, system clock and peripher-
al clock is stopped, but the sub clock oscillation and Watch Timer
by sub clock and RC-oscillated watchdog timer continue to oper-
ate. With the clock frozen, all functions are stopped, but the on-
chip RAM and Control registers are held. The port pins out the
values held by their respective port data register, port direction
registers. Oscillator stops and the systems internal operations are
all held up.
"STOP" which starts the STOP operating mode.
Note: The Stop mode is activated by execution of STOP
instruction after setting the SSCR to “5AH”. (This register
should be written by byte operation. If this register is set by
bit manipulation instruction, for example "set1" or "clr1" in-
struction, it may be undesired operation)
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
In the Stop mode of operation, VDD can be reduced to minimize
power consumption. Care must be taken, however, to ensure that
VDD is not reduced before the Stop mode is invoked, and that
VDD is restored to its normal operating level, before the Stop
mode is terminated.
• The program counter stop the address of the
instruction to be executed after the instruction
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
The reset should not be activated before VDD is restored to its
normal operating level, and must be held active long enough to
allow the oscillator to restart and stabilize.
with the oscillator and the internal hardware is lowered; however,
the power dissipation associated with the pin interface (depend-
ing on the external circuitry and program) is not directly deter-
mined by the hardware operation of the STOP feature. This point
should be little current flows when the input level is stable at the
power voltage level (VDD/VSS); however, when the input level
gets higher than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the out-
put transistor at an I/O port puts the pin signal into the high-im-
pedance state, a current flow across the ports input transistor,
requiring to fix the level by pull-up or other means.
Note: After STOP instruction, at least two or more NOP in-
struction should be written.
Ex)
LDM CKCTLR,#0FH ;more than 20ms
LDM SSCR,#5AH
STOP
NOP ;for stabilization time
NOP ;for stabilization time
In the STOP operation, the dissipation of the power associated
Peripheral
CPU
STOP Mode
SLEEP Mode
Stop
Stop
RAM
Retain
Halted
Retain
Basic Interval Timer
Watchdog Timer
Watch Timer
Operates Continuously
Stop (Only operates in RC-WDT mode)
Stop
Stop
Stop
Halted(Only when the event counter mode is
enabled, timer operates normally)
Timer/Counter
Operates Continuously
Buzzer, ADC
SIO
Stop
Stop
Only operate with external clock
Only operate with external clock
Stop(XIN=L, XOUT=H)
Only operate with external clock
UART
Only operate with external clock
Oscillator
Oscillation
Oscillation
Retain
Sub Oscillator
I/O Ports
Oscillation
Retain
Control Registers
Internal Circuit
Prescaler
Retain
Retain
Stop mode
Retain
Sleep mode
Active
Address Data Bus
Retain
Retain
Reset, Timer(EC0,1), SIO, UART0(using
ACLK0), UART1(using ACLK1)
Watch Timer( RC-WDT mode),
Watchdog Timer( RC-WDT mode),
External Interrupt
Release Source
Reset, All Interrupts
Table 21-1 Peripheral Operation During Power Saving Mode
0, the chip will resume execution starting with the instruction fol-
Release the STOP mode
lowing the STOP instruction. It will not vector to interrupt service
routine. (refer to Figure 21-4)
The source for exit from STOP mode is hardware reset, external
interrupt, Timer(EC0,1), Watch Timer, WDT, SIO or UART. Re-
set re-defines all the Control registers but does not change the on-
chip RAM. External interrupts allow both on-chip RAM and
Control registers to retain their values.
When exit from Stop mode by external interrupt, enough oscilla-
tion stabilization time is required to normal operation. Figure 21-
5 shows the timing diagram. When released from the Stop mode,
the Basic interval timer is activated on wake-up. It is increased
from 00H until FFH. The count overflow is set to start normal op-
If I-flag = 1, the normal interrupt response takes place. If I-flag =
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
eration. Therefore, before STOP instruction, user must be set its
relevant prescaler divide ratio to have long enough time (more
than 20msec). This guarantees that oscillator has started and sta-
bilized.
By reset, exit from Stop mode is shown in Figure 21-6.
STOP
INSTRUCTION
STOP Mode
Interrupt Request
=0
Corresponding Interrupt
Enable Bit (IENH, IENL)
IENH or IENL ?
=1
STOP Mode Release
=0
Master Interrupt
Enable Bit PSW[2]
I-FLAG
=1
Interrupt Service Routine
Next
INSTRUCTION
Figure 21-4 STOP Releasing Flow by Interrupts
.
Oscillator
(XIN pin)
Internal Clock
External Interrupt
STOP Instruction
Executed
BIT Counter
n
n+1 n+2
n+3
1
0
FE
0
1
2
FF
Clear
Normal Operation
Stop Operation
Stabilization Time
> 20ms
Normal Operation
t
ST
by software
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 21-5 STOP Mode Release Timing by External Interrupt
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
STOP Mode
Oscillator
(XI pin)
Internal
Clock
RESET
Internal
RESET
STOP Instruction Execution
Time can not be control by software
Stabilization Time
= 65.5mS @4MHz
t
ST
Figure 21-6 Timing of STOP Mode Release by Reset
21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the on-chip
oscillator is stopped. But internal RC oscillation circuit is oscil-
lated in this mode. The on-chip RAM and Control registers are
held. The port pins out the values held by their respective port
data register, port direction registers.
(at RC-watchdog timer mode). Reset re-defines all the Control
registers but does not change the on-chip RAM. External inter-
rupts allow both on-chip RAM and Control registers to retain
their values.
If I-flag = 1, the normal interrupt response takes place. In this
case, if the bit WDTON of CKCTLR is set to "0" and the bit
WDTE of IENH is set to "1", the device will execute the watch-
dog timer interrupt service routine(Figure 8-6). However, if the
bit WDTON of CKCTLR is set to "1", the device will generate
the internal Reset signal and execute the reset processing(Figure
21-8). If I-flag = 0, the chip will resume execution starting with
the instruction following the STOP instruction. It will not vector
to interrupt service routine.(refer to Figure 21-4)
The Internal RC-Oscillated Watchdog Timer mode is activated
by execution of STOP instruction after setting the bit RCWDT of
CKCTLR to "1". (This register should be written by byte opera-
tion. If this register is set by bit manipulation instruction, for ex-
ample "set1" or "clr1" instruction, it may be undesired operation)
Note: Caution: After STOP instruction, at least two or more
NOP instruction should be written
When exit from Stop mode at Internal RC-Oscillated Watchdog
Timer mode by external interrupt, the oscillation stabilization
time is required to normal operation. Figure 21-7 shows the tim-
ing diagram. When release the Internal RC-Oscillated Watchdog
Timer mode, the basic interval timer is activated on wake-up. It
is increased from 00H until FFH. The count overflow is set to start
normal operation. Therefore, before STOP instruction, user must
be set its relevant prescaler divide ratio to have long enough time
(more than 20msec). This guarantees that oscillator has started
and stabilized. By reset, exit from internal RC-Oscillated Watch-
dog Timer mode is shown in Figure 21-8.
Ex)
LDM WDTR,#1111_1111B
LDM CKCTLR,#0010_1110B
LDM SSCR,#0101_1010B
STOP
NOP
NOP
;for stabilization time
;for stabilization time
The exit from Internal RC-Oscillated Watchdog Timer mode is
hardware reset or external interrupt or watchdog timer interrupt
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
Oscillator
(XIN pin)
Internal
RC Clock
Internal
Clock
External
Interrupt
( or WDT Interrupt )
Clear Basic Interval Timer
STOP Instruction Execution
BIT
N-2
N-1
N
N+1
N+2
00
01
FE FF 00
00
Counter
Normal Operation
Stabilization Time
> 20mS
STOP mode
at RC-WDT Mode
Normal Operation
t
ST
Figure 21-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt
RCWDT Mode
Oscillator
(XIN pin)
Internal
RC Clock
Internal
Clock
RESET
RESET by WDT
Internal
RESET
STOP Instruction Execution
Stabilization Time
= 65.5mS @4MHz
Time can not be control by software
t
ST
Figure 21-8 Internal RC-WDT Mode Releasing by Reset
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MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
21.4 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption. To
minimize current drawn during Stop mode, the user should turn-
off output drivers that are sourcing or sinking current, if it is prac-
tical.
V
DD
INPUT PIN
INPUT PIN
V
V
DD
DD
internal
pull-up
i=0
V
DD
OPEN
O
i
O
i
Very weak current flows
V
DD
GND
i=0
X
GND
X
OPEN
O
Weak pull-up current flows
O
When port is configured as an input, input level should
be closed to 0V or 5V to avoid power consumption.
Figure 21-9 Application Example of Unused Input Port
OUTPUT PIN
OUTPUT PIN
ON
V
ON
V
DD
DD
OPEN
L
L
OFF
ON
OFF
ON
O
i=0
OFF
OFF
i
i
V
GND
DD
GND
GND
ON
X
O
X
OFF
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port .
O
In the left case, much current flows from port to GND.
Figure 21-10 Application Example of Unused Output Port
than the power voltage level (by approximately 0.3V), a cur-
rent begins to flow. Therefore, if cutting off the output tran-
sistor at an I/O port puts the pin signal into the high-
impedance state, a current flow across the ports input tran-
sistor, requiring it to fix the level by pull-up or other means.
Note: In the STOP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current flows
when the input level is stable at the power voltage level
(VDD/VSS); however, when the input level becomes higher
It should be set properly in order that current flow through port
doesn't exist.
First consider the port setting to input mode. Be sure that there is
MAR. 2005 Ver 0.2
101
MC80F0208/16/24
Preliminary
no current flow after considering its relationship with external
circuit. In input mode, the pin impedance viewing from external
MCU is very high that the current doesn’t flow.
If it is not appropriate to set as an input mode, then set to output
mode considering there is no current flow. The port setting to
High or Low is decided by considering its relationship with exter-
nal circuit. For example, if there is external pull-up resistor then
it is set to output mode, i.e. to High, and if there is external pull-
down register, it is set to low.
But input voltage level should be VSS or VDD. Be careful that if
unspecified voltage, i.e. if uncertain voltage level (not VSS or
VDD) is applied to input pin, there can be little current (max. 1mA
at around 2V) flow.
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Preliminary
MC80F0208/16/24
22. OSCILLATOR CIRCUIT
The MC80F0208/16/24 have oscillation circuits internally. XIN
and XOUT are input and output for frequency. Respectively, in-
verting amplifier which can be configured for being used as an
on-chip oscillator, as shown in Figure 22-1.
C1
X
OUT
C2
8MHz
Open
X
X
X
V
OUT
IN
SS
External Clock
IN
Recommended
Crystal Oscillator
Ceramic Resonator
C1,C2 = 20pF ± 10pF
C1,C2 = 20pF ± 10pF
External Oscillator
Crystal or Ceramic Oscillator
Figure 22-1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic
resonator or crystal oscillator. Since each crystal and ceramic res-
onator have their own characteristics, the user should consult the
crystal manufacturer for appropriate values of external compo-
nents.
In addition, see Figure 22-2 for the layout of the crystal.
X
X
OUT
Note: Minimize the wiring length. Do not allow the wiring to
intersect with other signal conductors. Do not allow the wir-
ing to come near changing high current. Set the potential of
the grounding position of the oscillator capacitor to that of
VSS. Do not ground it to any ground pattern where high cur-
rent is present. Do not fetch signals from the oscillator.
IN
Figure 22-2 Layout of Oscillator PCB circuit
MAR. 2005 Ver 0.2
103
MC80F0208/16/24
23. RESET
Preliminary
The MC80F0208/16/24 have four types of reset generation pro-
cedures; they are an external reset input, a watch-dog timer reset,
power fail processor reset, and address fail reset. Table 23-1
shows on-chip hardware initialization by reset action.
On-chip Hardware
Initial Value
On-chip Hardware
Peripheral clock
Initial Value
(FFFFH) - (FFFEH)
Program counter
(PC)
(RPR)
(G)
Off
Disable
RAM page register
G-flag
0
Watchdog timer
Control registers
Power fail detector
0
Refer to Table 8-1 on page 27
Disable
Operation mode
Main-frequency clock
Table 23-1 Initializing Internal Status by Reset Action
External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt
Trigger. A reset in accomplished by holding the RESET pin low
for at least 8 oscillator periods, within the operating voltage range
and oscillation stable, it is applied, and the internal state is initial-
ized. After reset, 65.5ms (at 4 MHz) add with 7 oscillator periods
are required to start execution as shown in Figure 23-2.
V
CC
10kΩ
to the RESET pin
7036P
+
10uF
Internal RAM is not affected by reset. When VDD is turned on,
the RAM content is indeterminate. Therefore, this RAM should
be initialized before read or tested it.
When the RESET pin input goes to high, the reset operation is re-
leased and the program execution starts at the vector address
stored at addresses FFFEH - FFFFH.
Figure 23-1 Simple Power-on-Reset Circuit
A connection for simple power-on-reset is shown in Figure 23-1.
1
2
3
4
5
6
7
Oscillator
(XIN pin)
RESET
ADDRESS
FFFE FFFF Start
?
?
?
?
BUS
DATA
BUS
OP
?
ADH
FE
ADL
?
?
?
MAIN PROGRAM
Reset Process Step
1
Stabilization Time
=65.5mS at 4MHz
t
ST
t
=
x 256
ST
f
÷1024
XIN
Figure 23-2 Timing Diagram after Reset
not be returned to normal operation and would become malfunc-
tion state. If the CPU tries to fetch the instruction from ineffective
code area or RAM area, the address fail reset is occurred. Please
refer to Figure 11-2 for setting address fail option.
Address Fail Reset
The Address Fail Reset is the function to reset the system by
checking code access of abnormal and unwished address caused
by erroneous program code itself or external noise, which could
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MC80F0208/16/24
24. POWER FAIL PROCESSOR
The MC80F0208/16/24 has an on-chip power fail detection cir-
cuitry to immunize against power noise. A configuration register,
PFDR, can enable or disable the power fail detect circuitry.
Whenever VDD falls close to or below power fail voltage for
100ns, the power fail situation may reset or freeze MCU accord-
ing to PFDM bit of PFDR. Refer to “Figure 24-1 Power Fail Volt-
age Detector Register” on page 105.
Note: If power fail voltage is selected to 2.4V or 2.7V on
below 3V operation, MCU is freezed at all the times.
Power Fail Function
FLASH
MASK
In the in-circuit emulator, power fail function is not implemented
and user can not experiment with it. Therefore, after final devel-
opment of user program, this function may be experimented or
evaluated.
Enable/Disable
PFDEN flag
PFDEN flag
PFS0 bit
PFS1 bit
Level Selection
Mask option
Table 24-1 Power fail processor
Note: User can select power fail voltage level according to
PFS0, PFS1 bit of CONFIG register(703FH) at the FLASH
(MC80F0208/16/24) but must select the power fail voltage
level to define PFD option of "Mask Order & Verification
Sheet" at the mask chip(MC80C0208/16/24), because the
power fail voltage level of mask chip (MC80C0208/16/24) is
determined according to mask option.
R/W R/W R/W
7
-
6
-
5
-
4
-
3
-
2
1
0
ADDRESS: 0F7
INITIAL VALUE: ---- -000
H
PFDR
PFDEN
PFDM PFDS
B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
PFD Operation Mode
0 : MCU will be frozen by power fail detection
1 : MCU will be reset by power fail detection
PFD Enable Bit
0: Power fail detection disable
1: Power fail detection enable
* Cautions :
Be sure to set bits 3 through 7 to “0”.
Figure 24-1 Power Fail Voltage Detector Register
MAR. 2005 Ver 0.2
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MC80F0208/16/24
Preliminary
RESET VECTOR
YES
PFDS =1
NO
RAM Clear
Initialize RAM Data
PFDS = 0
Skip the
initial routine
Initialize All Ports
Initialize Registers
Function
Execution
Figure 24-2 Example S/W of Reset flow by Power fail
VDD
VPFDMAX
PFDMIN
V
65.5mS
Internal
RESET
VDD
V
V
PFDMAX
PFDMIN
When PFDM = 1
65.5mS
Internal
RESET
t < 65.5mS
VDD
VPFDMAX
PFDMIN
V
65.5mS
Internal
RESET
Figure 24-3 Power Fail Processor Situations (at 4MHz operation)
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MC80F0208/16/24
25. FLASH PROGRAMMING
The Device Configuration Area can be programmed or left un-
programmed to select device configuration such as security bit.
This area is not accessible during normal execution but is read-
able and writable during FLASH program / verify mode. The De-
vice Configuration Area register is located at the address 20FFH.
7
-
6
5
4
3
-
2
1
0
ADDRESS: 20FF
INITIAL VALUE: 00
H
-
-
-
PFS1 PFS0 LOCK
CONFIG
H
Code Protect (Available FLASH version)
0 : Lock Disable
1 : Lock Enable (main cell read protection)
PFD Level Selection
00: PFD = 2.7V
01: PFD = 2.7V
10: PFD = 3.0V
11: PFD = 2.4V
Figure 25-1 Device Configuration Area
25.1 Lock bit
The lock bit exists in Device Configuration Area register. If lock
bit is programmed and user tries to read FLASH memory cell, the
output data from the data port is 5AH that means the normal pro-
tection operation of user program data.Once the lock bit is pro-
grammed, the user can't modify and read the data of user program
area.
25.2 Power Fail Detector
The power fail detection provides 3 level of detection, 2.4V, 2.7V
and 3.0V. The default level of detection is 2.7V and this level is
applied if user does not select the specific level in FLASH pro-
gramming S/W tools. For more information, Refer to “24. POW-
ER FAIL PROCESSOR” on page 105.
MAR. 2005 Ver 0.2
107
MC80F0208/16/24
Preliminary
26. Emulator EVA. Board Setting
➊
➊
➊
➊
➊
➊
➊
108
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
DIP Switch and VR Setting
Before execute the user program, keep in your mind the below configuration
DIP S/W
Description
ON/OFF Setting
-
-
This connector is only used for a device over 32 PIN.
This connector is only used for a device under 32 PIN.
For the MC80F0208/16/24.
For the MC80F0204.
➊
Must be ON position.
ON
1
ON : For the MC80F0208/16/24.
OFF : For the MC80F0204.
Eva. select switch
ON
OFF
ON
These switches select the AVDD source.
2
3
OFF
ON & OFF : Use Eva. VDD
OFF & ON : Use User AVDD
Use Eva. V
Use User’s AV
DD
DD
AVDD pin select switch
➊
SW2
Normally OFF.
EVA. chip can be reset by external user tar-
get board.
ON : Reset is available by either user target
system board or Emulator RESET switch.
OFF : Reset the MCU by Emulator RESET
switch. Does not work from user target
board.
4
5
This switch select the /Reset source.
Normally OFF.
MCU XOUT pin is disconnected internally
in the Emulator. Some circumstance user
may connect this circuit.
This switch select the Xout signal on/off.
ON : Output XOUT signal
OFF : Disconnect circuit
This switch select Eva. B/D Power supply source.
MDS
MDS
➊
Normally MDS.
This switch select Eva. B/D Power supply
source.
SW3
1
USER
USER
Use MDS Power
Use User’s Power
These switchs select the Normal I/O
port(off) or Sub-Clock (on).
It is reserved for the MC80F0448.
ON : SXOUT, SXIN
➊
1
2
This switch select the R22 or SXOUT
This switch select the R21 or SXIN.
.
SW4
OFF : R22, R21
Don’t care (MC80F0208/16/24).
MAR. 2005 Ver 0.2
109
MC80F0208/16/24
Preliminary
DIP S/W
Description
ON/OFF Setting
1
2
This switch select the Normal I/O
port(on&off) or special function
select(off&on).
It is reserved for the MC80F0204.
ON & OFF : R33,R34,R35 Port selected.
OFF & ON : XOUT, XIN , /Reset selected.
Don’t care (MC80F0208/16/24).
These switches select the R33 or XIN
➊
3
4
These switches select the R34 or XOUT
These switches select the R35 or /Reset
This is External oscillation socket(CAN Type. OSC)
SW5
5
6
This is for External Clock(CAN Type.
OSC).
-
➊
110
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
27. IN-SYSTEM PROGRAMMING (ISP)
27.1 Getting Started / Installation
The following section details the procedure for accomplishing the
installation procedure.
3. Turn your target B/D power switch ON. Your target B/
D must be configured to enter the ISP mode.
1. Connect the serial(RS-232C) cable between a target
board and the COM port of your PC.
4. Run the MagnaChip ISP software.
5. Press the Reset Button in the ISP S/W. If the status win-
dows shows a message as "Connected", all the condi-
tions for ISP are provided.
2. Configure the COM port of your PC as following.
Baudrate
Data bit
115,200
8
Parity
No
1
Stop bit
Flow control
No
27.2 Basic ISP S/W Information
MAR. 2005 Ver 0.2
111
MC80F0208/16/24
Preliminary
Function
Load HEX File
Save HEX File
Description
Load the data from the selected file storage into the memory buffer.
Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX
format.
Erase
Erase the data in your target MCU before programming it.
Blank Check
Program
Read
Verify whether or not a device is in an erased or unprogrammed state.
This button enables you to place new data from the memory buffer into the target device.
Read the data in the target MCU into the buffer for examination. The checksum will be displayed
on the checksum box.
Verify
Assures that data in the device matches data in the memory buffer. If your device is secured, a
verification error is detected.
Option Write
Option
Progam the configuration data of target MCU. The security locking is performed with this button.
Set the configuration data of target MCU. The security locking is set with this button.
Erase & Program & Verify.
AUTO
Auto Option Write
Edit Buffer
If selected with check mark, the option write is performed after erasure and write.
Modify the data in the selected address in your buffer memory
Fill the selected area with a data.
Fill Buffer
Goto
Display the selected page.
OSC. ______ MHz
Start ______
End ______
Checksum
Com Port
Enter your target system’s oscillator value with discarding below point.
Starting address
End address
Display the checksum(Hexdecimal) after reading the target device.
Select serial port.
Baud Rate
Select Device
Page Up Key
Page Down Key
Select UART baud rate.
Select target device.
Display the previous page of your memory buffer.
Display the higher page than the current location.
Table 1. ISP Function Description
112
MAR. 2005 Ver 0.2
Preliminary
MC80F0208/16/24
27.3 Hardware Conditions to Enter the ISP Mode
The In-System Programming (ISP) is performed without remov-
ing the microcontroller from the target system. The In-System
Programming(ISP) facility consists of a series of internal hard-
ware resources coupled with internal firmware through the serial
port. The In-System Programming (ISP) facility has made in-cir-
cuit programming in an embedded application possible with a
minimum of additional expense in components and circuit board
area. The boot loader can be executed by holding ALEB high,
RST/VPP as +9V, and ACLK0 with the OSC. 1.8432MHz. The
ISP function uses five pins: TxD0, RxD0, ALEB, ACLK0 and
RST/VPP
.
V
(+5V)
DD
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DD
R47 / TxD0
R46 / RxD0
R45 / ACLK0
Tx_Data
Rx_Data
1.8432MHz
+9V
RST/V
RESET
PP
X
OUT
ALEB
R30
IN
V
DD
X
V
SS
X-TAL
2MHz~12MHz
ISP Configuration
Figure 27-1 ISP Configuration
Note: Considerations to implement ISP function in a user
target board
• The ACLK0 must be connected to the specifed
oscillator.
• Connect the +9V to RST/Vpp pin directly.
• The ALEB pin must be pulled high.
• The main clk must be higher than 2MHz.
MAR. 2005 Ver 0.2
113
MC80F0208/16/24
Preliminary
27.4 Reference ISP Circuit diagram
The ISP S/W and H/W circuit diagram are provided at
department. The following circuit diagram is for reference use.
www.magnachipmcu.com . To get a ISP B/D, contact to sales
2N2907
100Ω
V
(+5V)
DD
MAX232
T1OUT
V
(+5V)
DD
CON1
Female DB9
14
7
11
10
T1IN
T2IN
+
1
6
2
7
3
8
4
9
5
T2OUT
13
8
12
9
R1IN
R2IN
R1OUT
R2OUT
J2
RxD
TxD
RESET/V
V
1
2
3
4
5
6
PP
2
1
+
V
V
SS
V+
C1+
C1-
SS
DD
+
+
1uF
V
1uF
16
6
SS
3
4
5
VCC
V-
ACLK_CLK
MCU_TxD
MCU_RxD
DTR
GND
22Ω
22Ω
+
C2+
1uF
1uF
15
GND
C2-
V
V
V
SS
SS
SS
V
V
SS
SS
V
(+5V)
V
(+5V)
DD
DD
J3
X1
22Ω
* V : +4.5 ~ +5.5V
DD
V
V
+
DD
SS
Vcc
Out
Gnd
* V : V + 4V
PP
DD
OSC
1.8432MHz
V
SS
V
V
SS
SS
External V
DD
The ragne of VDD must be from 5.5V to 4.5 and the minimum operation frequency is 2MHz.
If the user supplied VDD is out of range, the external power is needed instead of the target system VDD
.
For the ISP operation, power consumption required is less than 30mA.
Figure 27-2 Reference ISP Circuit Diagram
Figure 27-3 MagnaChip supplied ISP Board
114
MAR. 2005 Ver 0.2
APPENDIX
GMS800 Series
A. INSTRUCTION
A.1 Terminology List
Terminology
Description
A
X
Accumulator
X - register
Y
Y - register
PSW
#imm
dp
Program Status Word
8-bit Immediate data
Direct Page Offset Address
Absolute Address
Indirect expression
Register Indirect expression
!abs
[ ]
{ }
{ }+
.bit
Register Indirect expression, after that, Register auto-increment
Bit Position
A.bit
dp.bit
M.bit
rel
Bit Position of Accumulator
Bit Position of Direct Page Memory
Bit Position of Memory Data (000H~0FFFH)
Relative Addressing Data
U-page (0FF00H~0FFFFH) Offset Address
Table CALL Number (0~15)
upage
n
+
Addition
Upper Nibble Expression in Opcode
0
x
y
Bit Position
Bit Position
Upper Nibble Expression in Opcode
1
−
×
Subtraction
Multiplication
/
Division
( )
∧
Contents Expression
AND
∨
OR
⊕
~
Exclusive OR
NOT
←
→
↔
=
Assignment / Transfer / Shift Left
Shift Right
Exchange
Equal
≠
Not Equal
MAR. 2005
i
GMS800 Series
A.2 Instruction Map
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
LOW
HIGH
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
SET1
BBS
BBS
ADC
ADC
dp
ADC
dp+X
ADC
!abs
ASL
A
ASL
dp
TCALL SETA1
.bit
BIT
dp
POP
A
PUSH
A
000
-
BRK
dp.bit A.bit,rel dp.bit,rel #imm
0
SBC
#imm
SBC
dp
SBC
dp+X
SBC
!abs
ROL
A
ROL
dp
TCALL CLRA1 COM
POP
X
PUSH
X
BRA
rel
001
010
011
100
101
110
111
CLRC
CLRG
DI
2
.bit
dp
CMP
#imm
CMP
dp
CMP
dp+X
CMP
!abs
LSR
A
LSR
dp
TCALL NOT1
TST
dp
POP
Y
PUSH PCALL
Y
4
M.bit
Upage
OR
#imm
OR
dp
OR
dp+X
OR
!abs
ROR
A
ROR TCALL
dp
OR1
OR1B
CMPX
dp
POP
PSW
PUSH
PSW
RET
6
AND
#imm
AND
dp
AND
dp+X
AND
!abs
INC
A
INC
dp
TCALL AND1 CMPY CBNE
INC
X
CLRV
SETC
SETG
EI
TXSP
TSPX
XCN
8
AND1B
dp
dp+X
EOR
#imm
EOR
dp
EOR
dp+X
EOR
!abs
DEC
A
DEC
dp
TCALL EOR1 DBNE
XMA
dp+X
DEC
X
10
EOR1B
dp
LDA
#imm
LDA
dp
LDA
dp+X
LDA
!abs
LDY
dp
TCALL
12
LDC
LDCB
LDX
dp
LDX
dp+Y
TXA
TAX
DAS
LDM
dp,#imm
STA
dp
STA
dp+X
STA
!abs
STY
dp
TCALL
14
STC
M.bit
STX
dp
STX
dp+Y
XAX
STOP
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011
11100
1C
11101
1D
11110
1E
11111
1F
LOW
HIGH
10
11
12
13
14
15
16
17
18
19
1A
1B
BPL
rel
ADC
{X}
ADC
ADC
ADC
ASL
!abs
ASL
dp+X
TCALL
1
JMP
!abs
BIT
!abs
ADDW
dp
LDX
#imm
JMP
[!abs]
CLR1
dp.bit
BBC
BBC
000
001
010
011
100
101
110
111
A.bit,rel dp.bit,rel
!abs+Y [dp+X] [dp]+Y
BVC
rel
SBC
{X}
SBC
SBC
SBC
ROL
!abs
ROL
dp+X
TCALL CALL
3
TEST SUBW
!abs dp
LDY
#imm
JMP
[dp]
!abs+Y [dp+X] [dp]+Y
!abs
BCC
rel
CMP
{X}
CMP
CMP
CMP
LSR
!abs
LSR
dp+X
TCALL
5
TCLR1 CMPW CMPX CALL
!abs
MUL
!abs+Y [dp+X] [dp]+Y
dp
#imm
[dp]
BNE
rel
OR
{X}
OR
OR
OR
ROR
!abs
ROR TCALL DBNE CMPX LDYA CMPY
dp+X
RETI
!abs+Y [dp+X] [dp]+Y
7
Y
!abs
dp
#imm
BMI
rel
AND
{X}
AND
AND
AND
INC
!abs
INC
dp+X
TCALL
9
CMPY INCW
!abs
INC
Y
DIV
TAY
TYA
DAA
NOP
!abs+Y [dp+X] [dp]+Y
dp
BVS
rel
EOR
{X}
EOR
EOR
EOR
DEC
!abs
DEC
dp+X
TCALL
11
XMA
{X}
XMA
dp
DECW
dp
DEC
Y
!abs+Y [dp+X] [dp]+Y
BCS
rel
LDA
{X}
LDA
LDA
LDA
LDY
!abs
LDY
dp+X
TCALL
13
LDA
{X}+
LDX
!abs
STYA
dp
XAY
XYX
!abs+Y [dp+X] [dp]+Y
BEQ
rel
STA
{X}
STA
STA
STA
STY
!abs
STY
dp+X
TCALL
15
STA
{X}+
STX
!abs
CBNE
dp
!abs+Y [dp+X] [dp]+Y
ii
MAR. 2005
GMS800 Series
A.3 Instruction Set
Arithmetic / Logic Operation
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
Mnemonic
Operation
1
ADC #imm
04
05
06
07
15
16
17
14
84
85
86
87
95
96
97
94
08
09
19
18
44
45
46
47
55
56
57
54
5E
6C
7C
7E
8C
9C
2C
DF
CF
A8
A9
B9
B8
AF
BE
2
2
2
3
3
2
2
1
2
2
2
3
3
2
2
1
1
2
2
3
2
2
2
3
3
2
2
1
2
2
3
2
2
3
2
1
1
1
2
2
3
1
1
2
3
4
4
5
6
6
3
2
3
4
4
5
6
6
3
2
4
5
5
2
3
4
4
5
6
6
3
2
3
4
2
3
4
4
3
3
2
4
5
5
2
2
Add with carry.
2
ADC dp
A ← ( A ) + ( M ) + C
3
ADC dp + X
ADC !abs
ADC !abs + Y
ADC [ dp + X ]
ADC [ dp ] + Y
ADC { X }
AND #imm
AND dp
4
NV--H-ZC
5
6
7
8
9
Logical AND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A ← ( A ) ∧ ( M )
AND dp + X
AND !abs
AND !abs + Y
AND [ dp + X ]
AND [ dp ] + Y
AND { X }
ASL A
N-----Z-
N-----ZC
Arithmetic shift left
ASL dp
7
6 5 4 3 2 1 0
C
←
← ← ← ← ← ← ← ← ← “0”
ASL dp + X
ASL !abs
CMP #imm
CMP dp
CMP dp + X
CMP !abs
CMP !abs + Y
CMP [ dp + X ]
CMP [ dp ] + Y
CMP { X }
CMPX #imm
CMPX dp
CMPX !abs
CMPY #imm
CMPY dp
CMPY !abs
COM dp
N-----ZC
Compare accumulator contents with memory contents
( A ) - ( M )
Compare X contents with memory contents
( X ) - ( M )
N-----ZC
N-----ZC
Compare Y contents with memory contents
( Y ) - ( M )
1’S Complement : ( dp ) ← ~( dp )
Decimal adjust for addition
Decimal adjust for subtraction
Decrement
N-----Z-
N-----ZC
N-----ZC
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
DAA
DAS
DEC A
DEC dp
M ← ( M ) - 1
DEC dp + X
DEC !abs
DEC X
DEC Y
MAR. 2005
iii
GMS800 Series
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
Mnemonic
Operation
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
DIV
9B
A4
A5
A6
A7
B5
B6
B7
B4
88
89
99
98
8F
9E
48
49
59
58
5B
64
65
66
67
75
76
77
74
28
29
39
38
68
69
79
78
24
25
26
27
35
36
37
34
4C
1
2
2
2
3
3
2
2
1
1
2
2
3
1
1
1
2
2
3
1
2
2
2
3
3
2
2
1
1
2
2
3
1
2
2
3
2
2
2
3
3
2
2
1
2
12
2
3
4
4
5
6
6
3
2
4
5
5
2
2
2
4
5
5
9
2
3
4
4
5
6
6
3
2
4
5
5
2
4
5
5
2
3
4
4
5
6
6
3
3
Divide : YA / X Q: A, R: Y
NV--H-Z-
EOR #imm
EOR dp
Exclusive OR
A ← ( A ) ⊕ ( M )
EOR dp + X
EOR !abs
EOR !abs + Y
EOR [ dp + X ]
EOR [ dp ] + Y
EOR { X }
INC A
N-----Z-
Increment
N-----ZC
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
INC dp
M ← ( M ) + 1
INC dp + X
INC !abs
INC X
INC Y
LSR A
Logical shift right
LSR dp
N-----ZC
N-----Z-
7
6 5 4 3 2 1 0
C
“0” → → → → → → → → →
→
LSR dp + X
LSR !abs
MUL
Multiply : YA ← Y × A
Logical OR
OR #imm
OR dp
A ← ( A ) ∨ ( M )
OR dp + X
OR !abs
N-----Z-
OR !abs + Y
OR [ dp + X ]
OR [ dp ] + Y
OR { X }
ROL A
Rotate left through Carry
ROL dp
N-----ZC
N-----ZC
7
6 5 4 3 2 1 0
C
← ← ← ← ← ← ← ←
ROL dp + X
ROL !abs
ROR A
Rotate right through Carry
ROR dp
7
6 5 4 3 2 1 0
C
→ → → → → → → →
ROR dp + X
ROR !abs
SBC #imm
SBC dp
Subtract with Carry
A ← ( A ) - ( M ) - ~( C )
SBC dp + X
SBC !abs
SBC !abs + Y
SBC [ dp + X ]
SBC [ dp ] + Y
SBC { X }
TST dp
NV--HZC
Test memory contents for negative or zero, ( dp ) - 00H
N-----Z-
N-----Z-
Exchange nibbles within the accumulator
A7~A4 ↔ A3~A0
89
XCN
CE
1
5
iv
MAR. 2005
GMS800 Series
Register / Memory Operation
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
Mnemonic
Operation
1
LDA #imm
C4
C5
C6
C7
D5
D6
D7
D4
DB
E4
1E
CC
CD
DC
3E
C9
D9
D8
E5
E6
E7
F5
2
2
2
3
3
2
2
1
1
3
2
2
2
3
2
2
2
3
2
2
3
3
2
2
1
1
2
2
3
2
2
3
1
1
1
1
1
1
1
1
2
2
1
1
2
3
4
4
5
6
6
3
4
5
2
3
4
4
2
3
4
4
4
5
5
6
7
7
4
4
4
5
5
4
5
5
2
2
2
2
2
2
4
4
5
6
5
4
Load accumulator
2
LDA dp
A ← ( M )
3
LDA dp + X
LDA !abs
LDA !abs + Y
LDA [ dp + X ]
LDA [ dp ] + Y
LDA { X }
LDA { X }+
LDM dp,#imm
LDX #imm
LDX dp
4
5
N-----Z-
6
7
8
9
X- register auto-increment : A ← ( M ) , X ← X + 1
Load memory with immediate data : ( M ) ← imm
Load X-register
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
--------
N-----Z-
X ← ( M )
LDX dp + Y
LDX !abs
LDY #imm
LDY dp
Load Y-register
Y ← ( M )
N-----Z-
--------
LDY dp + X
LDY !abs
STA dp
Store accumulator contents in memory
STA dp + X
STA !abs
STA !abs + Y
STA [ dp + X ]
STA [ dp ] + Y
STA { X }
STA { X }+
STX dp
( M ) ← A
F6
F7
F4
FB
EC
ED
FC
E9
F9
X- register auto-increment : ( M ) ← A, X ← X + 1
Store X-register contents in memory
( M ) ← X
STX dp + Y
STX !abs
STY dp
--------
--------
Store Y-register contents in memory
STY dp + X
STY !abs
TAX
( M ) ← Y
F8
E8
9F
AE
C8
8E
BF
EE
DE
BC
AD
BB
FE
Transfer accumulator contents to X-register : X ← A
Transfer accumulator contents to Y-register : Y ← A
Transfer stack-pointer contents to X-register : X ← sp
Transfer X-register contents to accumulator: A ← X
Transfer X-register contents to stack-pointer: sp ← X
Transfer Y-register contents to accumulator: A ← Y
Exchange X-register contents with accumulator :X ↔ A
Exchange Y-register contents with accumulator :Y ↔ A
Exchange memory contents with accumulator
( M ) ↔ A
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
N-----Z-
--------
--------
TAY
TSPX
TXA
TXSP
TYA
XAX
XAY
XMA dp
XMA dp+X
XMA {X}
XYX
N-----Z-
--------
Exchange X-register contents with Y-register : X ↔ Y
MAR. 2005
v
GMS800 Series
16-BIT operation
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
1
Mnemonic
Operation
16-Bits add without Carry
YA ← ( YA ) + ( dp +1 ) ( dp )
ADDW dp
CMPW dp
DECW dp
INCW dp
LDYA dp
STYA dp
SUBW dp
1D
5D
BD
9D
7D
DD
3D
2
2
2
2
2
2
2
5
4
6
6
5
5
5
NV--H-ZC
N-----ZC
N-----Z-
N-----Z-
N-----Z-
--------
NV--H-ZC
Compare YA contents with memory pair contents :
2
(YA) − (dp+1)(dp)
Decrement memory pair
( dp+1)( dp) ← ( dp+1) ( dp) - 1
3
Increment memory pair
( dp+1) ( dp) ← ( dp+1) ( dp ) + 1
4
Load YA
YA ← ( dp +1 ) ( dp )
5
Store YA
( dp +1 ) ( dp ) ← YA
6
16-Bits subtract without carry
YA ← ( YA ) - ( dp +1) ( dp)
7
Bit Manipulation
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
Mnemonic
Operation
1
2
AND1 M.bit
AND1B M.bit
BIT dp
8B
8B
0C
1C
y1
3
3
2
3
2
2
1
1
1
3
3
3
3
3
3
3
2
2
1
1
3
4
4
4
5
4
2
2
2
2
5
5
4
4
5
5
5
4
2
2
2
6
Bit AND C-flag : C ← ( C ) ∧ ( M .bit )
Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )
Bit test A with memory :
-------C
-------C
MM----Z-
3
Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )
Clear bit : ( M.bit ) ← “0”
4
BIT !abs
5
CLR1 dp.bit
CLRA1 A.bit
CLRC
--------
--------
-------0
--0-----
-0--0---
-------C
-------C
-------C
-------C
--------
-------C
-------C
--------
--------
-------1
--1-----
--------
6
2B
20
Clear A bit : ( A.bit ) ← “0”
7
Clear C-flag : C ← “0”
8
CLRG
40
Clear G-flag : G ← “0”
9
CLRV
80
Clear V-flag : V ← “0”
10
11
12
13
14
15
16
17
18
19
20
21
EOR1 M.bit
EOR1B M.bit
LDC M.bit
LDCB M.bit
NOT1 M.bit
OR1 M.bit
OR1B M.bit
SET1 dp.bit
SETA1 A.bit
SETC
AB
AB
CB
CB
4B
6B
6B
x1
Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit )
Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit)
Load C-flag : C ← ( M .bit )
Load C-flag with NOT : C ← ~( M .bit )
Bit complement : ( M .bit ) ← ~( M .bit )
Bit OR C-flag : C ← ( C ) ∨ ( M .bit )
Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit )
Set bit : ( M.bit ) ← “1”
0B
A0
C0
EB
Set A bit : ( A.bit ) ← “1”
Set C-flag : C ← “1”
SETG
Set G-flag : G ← “1”
STC M.bit
Store C-flag : ( M .bit ) ← C
Test and clear bits with A :
A - ( M ) , ( M ) ← ( M ) ∧ ~( A )
22
23
TCLR1 !abs
TSET1 !abs
5C
3C
3
3
6
6
N-----Z-
N-----Z-
Test and set bits with A :
A - ( M ) , ( M ) ← ( M ) ∨ ( A )
vi
MAR. 2005
GMS800 Series
Branch / Jump Operation
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
Mnemonic
Operation
1
2
3
4
BBC A.bit,rel
BBC dp.bit,rel
BBS A.bit,rel
BBS dp.bit,rel
y2
y3
x2
x3
2
3
2
3
4/6
5/7
4/6
5/7
Branch if bit clear :
--------
--------
if ( bit ) = 0 , then pc ← ( pc ) + rel
Branch if bit set :
if ( bit ) = 1 , then pc ← ( pc ) + rel
Branch if carry bit clear
if ( C ) = 0 , then pc ← ( pc ) + rel
5
6
BCC rel
BCS rel
BEQ rel
BMI rel
BNE rel
BPL rel
BRA rel
BVC rel
50
D0
F0
90
70
10
2F
30
2
2
2
2
2
2
2
2
2/4
2/4
2/4
2/4
2/4
2/4
4
--------
--------
--------
--------
--------
--------
--------
--------
--------
Branch if carry bit set
if ( C ) = 1 , then pc ← ( pc ) + rel
Branch if equal
if ( Z ) = 1 , then pc ← ( pc ) + rel
7
Branch if minus
if ( N ) = 1 , then pc ← ( pc ) + rel
8
Branch if not equal
if ( Z ) = 0 , then pc ← ( pc ) + rel
9
Branch if minus
if ( N ) = 0 , then pc ← ( pc ) + rel
10
11
12
Branch always
pc ← ( pc ) + rel
Branch if overflow bit clear
if (V) = 0 , then pc ← ( pc) + rel
2/4
Branch if overflow bit set
if (V) = 1 , then pc ← ( pc ) + rel
13
14
15
BVS rel
B0
3B
5F
2
3
2
2/4
8
CALL !abs
CALL [dp]
Subroutine call
M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1,
if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) .
8
--------
--------
16
17
18
19
20
21
22
CBNE dp,rel
CBNE dp+X,rel
DBNE dp,rel
DBNE Y,rel
JMP !abs
FD
8D
AC
7B
1B
1F
3F
3
3
3
2
3
3
2
5/7
6/8
5/7
4/6
3
Compare and branch if not equal :
if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.
Decrement and branch if not equal :
if ( M ) ≠ 0 , then pc ← ( pc ) + rel.
Unconditional jump
--------
--------
JMP [!abs]
JMP [dp]
5
pc ← jump address
4
U-page call
M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ),
sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” .
23
24
PCALL upage
TCALL n
4F
nA
2
1
6
8
--------
--------
Table call : (sp) ←( pcH ), sp ← sp - 1,
M(sp) ← ( pcL ),sp ← sp - 1,
pcL ← (Table vector L), pcH ← (Table vector H)
MAR. 2005
vii
GMS800 Series
Control Operation & Etc.
Op
Code
Byte
No
Cycle
No
Flag
NVGBHIZC
No.
1
Mnemonic
Operation
Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1,
M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,
pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) .
BRK
0F
1
8
---1-0--
2
3
DI
EI
60
E0
FF
0D
2D
4D
6D
0E
2E
4E
6E
1
1
1
1
1
1
1
1
1
1
1
3
3
2
4
4
4
4
4
4
4
4
Disable all interrupts : I ← “0”
Enable all interrupt : I ← “1”
No operation
-----0--
-----1--
--------
4
NOP
5
POP A
sp ← sp + 1, A ← M( sp )
sp ← sp + 1, X ← M( sp )
sp ← sp + 1, Y ← M( sp )
sp ← sp + 1, PSW ← M( sp )
M( sp ) ← A , sp ← sp - 1
M( sp ) ← X , sp ← sp - 1
M( sp ) ← Y , sp ← sp - 1
M( sp ) ← PSW , sp ← sp - 1
6
POP X
--------
restored
--------
7
POP Y
8
POP PSW
PUSH A
PUSH X
PUSH Y
PUSH PSW
9
10
11
12
Return from subroutine
sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp )
13
RET
6F
1
5
--------
Return from interrupt
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp )
14
15
RETI
7F
EF
1
1
6
3
restored
--------
STOP
Stop mode ( halt CPU, stop oscillator )
viii
MAR. 2005
B. MASK ORDER SHEET
Mask Order & Verification Sheet
MC80C02
- MC
Customer should write inside thick line box.
2. Device Information
1. Customer Information
Company Name
Application
Package
File Name
ROM Size (bytes)
44MQFP
42SDIP
(
) .OTP
24K
16K
)
8K
YYYY
MM
DD
Order Date
Check Sum
(
Tel:
Fax:
Set “00H” in blanked area
* PFD Option
(24K)
(16K)
(8K)
A000 H
C000 H
E000 H
E-mail address:
3.0V
.OTP file
2.7V
Name &
Signature:
2.4V
FFFFH
Not use
(Please check mark√ into
)
3. Marking Specification
08 or 16 or 24
Customer’s logo
Customer logo is not required.
MC80C02XX-MC
MC80C02XX-MC
YYWW
YYWW
KOREA
KOREA
If the customer logo must be used in the special mark, please submit a clean original of the logo.
Customer’s part number
4. Delivery Schedule
Date
Quantity
MagnaChip Confirmation
YYYY
YYYY
MM
MM
DD
DD
Customer sample
Risk order
pcs
pcs
5. ROM Code Verification
Please confirm out verification data.
YYYY
YYYY
MM
DD
MM
DD
Approval date:
Verification date:
Check sum:
I agree with your verification data and confirm you to
make mask set.
Tel:
Fax:
Tel:
Fax:
E-mail address:
E-mail address:
Name &
Signature:
Name &
Signature:
相关型号：
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