MC80C0448L_技术文档

MAGNACHIP SEMICONDUCTOR LTD.

8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0424/0432/0448

MC80C0424/0432/0448

User’s Manual (Ver. 0.2)

Version History

Ver 0.2 (MAR, 2005) this book

FLASH memory feature is included.

Ver 0.1 (MAR, 2005)

First release version.

Version 0.2

Published by

MCU Application Team

Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distributors and Representatives.

MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way re-

sponsible for any violations of patents or other rights of the third party generated by the use of this manual.

Preliminary

MC80F0424/0432/0448

CONTENTS

1. OVERVIEW .................................................................................................................................................... 1

1.1 Description .............................................................................................................................................. 1

1.2 Features .................................................................................................................................................. 1

1.3 Development Tools ................................................................................................................................. 2

1.4 Ordering Information .........................................................................................................................3

2. BLOCK DIAGRAM ........................................................................................................................................ 4

3. PIN ASSIGNMENT ........................................................................................................................................ 5

4. PACKAGE DIAGRAM ................................................................................................................................... 7

5. PIN FUNCTION .............................................................................................................................................. 9

5.1 MC80F0424/0432/0448 Pin Description ............................................................................................... 10

6. PORT STRUCTURES .................................................................................................................................. 13

7. ELECTRICAL CHARACTERISTICS ........................................................................................................... 17

7.1 Absolute Maximum Ratings .................................................................................................................. 17

7.2 Recommended Operating Conditions ................................................................................................... 17

7.3 A/D Converter Characteristics .............................................................................................................. 17

7.4 DC Electrical Characteristics ................................................................................................................ 18

7.5 AC Characteristics ................................................................................................................................ 19

7.6 Serial Interface Timing Characteristics ................................................................................................. 20

7.7 Typical Characteristic Curves ............................................................................................................... 21

8. MEMORY ORGANIZATION ........................................................................................................................ 24

8.1 Registers ............................................................................................................................................... 24

8.2 Program Memory .................................................................................................................................. 26

8.3 Data Memory ........................................................................................................................................ 30

8.4 Addressing Mode .................................................................................................................................. 36

9. I/O PORTS ................................................................................................................................................... 40

10. CLOCK GENERATOR .............................................................................................................................. 44

11. BASIC INTERVAL TIMER ......................................................................................................................... 46

12. WATCHDOG TIMER ................................................................................................................................. 48

13. WATCH TIMER .......................................................................................................................................... 51

14. TIMER/EVENT COUNTER ........................................................................................................................ 52

14.1 8-bit Timer / Counter Mode ................................................................................................................. 56

14.2 16-bit Timer / Counter Mode ............................................................................................................... 62

14.3 8-bit Compare Output (16-bit) ............................................................................................................. 63

14.4 8-bit Capture Mode ............................................................................................................................. 64

14.5 16-bit Capture Mode ........................................................................................................................... 68

14.6 PWM Mode ......................................................................................................................................... 71

15. ANALOG TO DIGITAL CONVERTER ....................................................................................................... 75

MAR. 2005 Ver 0.2

MC80F0424/0432/0448

Preliminary

16. SERIAL INPUT/OUTPUT (SIO) ................................................................................................................. 78

16.1 Transmission/Receiving Timing .......................................................................................................... 79

16.2 The method of Serial I/O ..................................................................................................................... 81

16.3 The Method to Test Correct Transmission .......................................................................................... 81

17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ................................................... 82

17.1 UART Serial Interface Functions ........................................................................................................ 82

17.2 Serial Interface Configuration ............................................................................................................. 83

17.3 Communication operation ................................................................................................................... 85

17.4 Relationship between main clock and baud rate ................................................................................ 86

17.5 Communication operation ................................................................................................................... 87

18. BUZZER FUNCTION ................................................................................................................................. 88

19. INTERRUPTS ............................................................................................................................................ 90

19.1 Interrupt Sequence ............................................................................................................................. 92

19.2 BRK Interrupt ...................................................................................................................................... 94

19.3 Shared Interrupt Vector ....................................................................................................................... 94

19.4 Multi Interrupt ...................................................................................................................................... 95

19.5 External Interrupt ................................................................................................................................ 96

20. OPERATION MODE .................................................................................................................................. 98

20.1 Operation Mode Switching .................................................................................................................. 99

21. POWER SAVING OPERATION .............................................................................................................. 101

21.1 Sleep Mode ....................................................................................................................................... 101

21.2 Stop Mode ......................................................................................................................................... 102

21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode ........................................................... 105

21.4 Minimizing Current Consumption ...................................................................................................... 107

22. OSCILLATOR CIRCUIT .......................................................................................................................... 109

23. RESET ..................................................................................................................................................... 110

24. POWER FAIL PROCESSOR ................................................................................................................... 111

25. FLASH PROGRAMMING ........................................................................................................................ 113

25.1 Lock bit .............................................................................................................................................. 113

25.2 Power Fail Detection level ................................................................................................................ 113

26. Emulator EVA. Board Setting .............................................................................................................. 114

27. IN-SYSTEM PROGRAMMING (ISP) ....................................................................................................... 117

27.1 Getting Started / Installation .............................................................................................................. 117

27.2 Basic ISP S/W Information ................................................................................................................ 117

27.3 Hardware Conditions to Enter the ISP Mode .................................................................................... 119

27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board .............................................. 120

INSTRUCTION MAP........................................................................................................................................... i

INSTRUCTION SET........................................................................................................................................... ii

MASK ORDER SHEET................................................................................................................................... viii

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

MC80C0424/0432/0448

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH 10-BIT A/D CONVERTER AND UART

1. OVERVIEW

1.1 Description

The MC80F0424/0432/0448 is advanced CMOS 8-bit microcontroller with 48K/32K/24K bytes of ROM(FLASH). This is a powerful mi-

crocontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the fol-

lowing standard features : 24K/32K/48K bytes of ROM(FLASH), 1.5K bytes of RAM, 8/16-bit timer/counter, watchdog timer, watch

timer, 10-bit A/D converter, 8-bit Serial Input/Output, UART, 6-bit buzzer driving port, 10-bit PWM output and on-chip oscillator and

clock circuitry. It also has 8 high current I/O pins with typical 20mA. In addition, the MC80F0424/0432/0448 supports power saving modes

to reduce power consumption.

FLASH MCU

MC80F0424

MC80F0432

MC80F0448

MASK MCU

MC80C0424

MC80C0432

MC80C0448

ROM

RAM

ADC

PWM

I/O PORT

Package

24KB 1.5KB

64SDIP, 64MQFP

64LQFP

32KB 1.5KB 16 channel 2 channel

48KB 1.5KB

57 port

1.2 Features

• 24/32K/48K Bytes On-chip ROM

• 16 channel 10-bit A/D converter

• Four External Interrupt input ports

• FLASH memory

- Endurance : 100 cycles

- Data retention time : 10 years

• Fifteen Interrupt sources

- Basic Interval Timer(1), External input(4)

- Timer/Event counter(5), ADC(1)

• 1.5K Bytes of On-chip Data RAM

(Included stack memory)

- Serial Interface(3), WDT and Watch Timer(1)

• Minimum Instruction Execution Time

- 333ns at 12MHz (NOP instruction)

• Built in Noise Immunity Circuit

- Noise filter

- 3-level Power fail detector [3.0V, 2.7V, 2.4V]

• 57 I/O Ports at 64 pin

• Power Down Mode

- Stop, Sleep, Sub active, Sub sleep mode

• One 8-bit Basic Interval Timer

• Four 8-bit and one 16-bit Timer/Event counter

(or three 16-bit Timer/Event counter)

• Wide Operating Voltage Range

- 2.7V to 5.5V @ (0.4~4MHz)

- 4.5V to 5.5V @ (0.4~12MHz)

• One Watchdog timer

• One Watch timer

• Two 10-bit PWM

• 0.4 ~ 12MHz Wide Operating Frequency Range

• 64SDIP, 64MQFP, 64LQFP type

• Three 8-bit Serial Communication Interface

- One SIO and two UART

• Operating Temperature : -40°C ~ 85°C

• Oscillator Type

- Crystal, Ceramic resonator, External clock

• One Buzzer Driving port

- 488Hz ~ 250kHz@4MHz

• Sub-clock : 32.768kHz crystal oscillator

MAR. 2005 Ver 0.2

1

MC80F0424/0432/0448

1.3 Development Tools

Preliminary

The MC80F0424/0432/0448 is supported by a full-featured mac-

ro assembler, an in-circuit emulator CHOICE-Dr.^TMand OTP

programmers. There are two different type of programmers such

as single type and gang type. For mode detail, Refer to “25.

FLASH PROGRAMMING” on page 113. Macro assembler op-

erates under the MS-Windows 95 and upversioned Windows OS.

Please contact sales part of MagnaChip semiconductor.

- MS-Windows based assembler

Software

- MS-Windows based Debugger

- HMS800 C compiler

Hardware

(Emulator)

- CHOICE-Dr.

- CHOICE-Dr. EVA 80C0x B/D

- CHOICE - SIGMA I/II(Single writer)

FLASH Writer - PGM Plus I/II/III(Single writer)

- Standalone GANG4 I/II(Gang writer)

Figure 1-2 PGM-Plus (Single writer)

Figure 1-1 Choice-Dr (Emulator)

Figure 1-3 Standalone GANG4 (Gang writer)

2

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

1.4 Ordering Information

Device name

ROM Size

RAM size

Package

MC80C0424K

MC80C0424Q

MC80C0424L

24K bytes

MC80C0432K

MC80C0432Q

MC80C0432L

Mask version

32K bytes

48K bytes

24K bytes

32K bytes

48K bytes

MC80C0448K

MC80C0448Q

MC80C0448L

K : 64SDIP

1.5K bytes Q : 64QFP

L : 64LQFP

MC80F0424K

MC80F0424Q

MC80F0424L

MC80F0432K

MC80F0432Q

MC80F0432L

FLASH version

MC80F0448K

MC80F0448Q

MC80F0448L

Table 1-1 Ordering Information of MC80F0424/0432/0448

MAR. 2005 Ver 0.2

3

MC80F0424/0432/0448

2. BLOCK DIAGRAM

Preliminary

R30

R31 / ACLK1

R32 / RxD1

R33 / TxD1

R34

Power

Supply

ADC Power

Supply

R35

R36

R37

R00~R07

R20~R23

R0

R2

R3

PSW

A

PC

X

Y

SP

ALU

Data

Memory

UART1

(1.5K bytes)

Program

Memory

Interrupt Controller

Data Table

8-bit Basic

Interval

Timer

System controller

System

Clock Controller

8-bit

Watch/

Watchdog

Timer

8-bit serial

Interface

SIO/UART0

Instruction

Decoder

10-bit

PWM

10-bit

ADC

Sub System

Timer/

Clock Controller

Counter

Timing Generator

Clock

Generator

Driver

Buzzer

R1

R5

R4

R6

R7

R10 / INT0

R11 / INT1

R12 / INT2

R50 / INT3

R51 / EC1

R52 / T2O

R40

R60 / AN0

R61 / AN1

R62 / AN2

R63 / AN3

R64 / AN4

R65 / AN5

R66 / AN6

R67 / AN7

R70 / AN8

R71 / AN9

R72 / AN10

R73 / AN11

R74 / AN12

R75 / AN13

R76 / AN14

R77 / AN15

R41

R42 / SCK

R43 / SI

R44 / SO

R45 / ACLK0

R46 / RxD0

R47 / TxD0

R13 / BUZO R53 / PWM1O / T1O

R14 / T0O

R15 / EC0

R16

R54 / PWM3O / T3O

R17

4

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

3. PIN ASSIGNMENT

V

AN8 / R70

AN9 / R71

AN10 / R72

AN11 / R73

AN12 / R74

AN13 / R75

AN14 / R76

AN15 / R77

R00

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DD

64SDIP

(Top View)

R67 / AN7

R66 / AN6

R65 / AN5

R64 / AN4

R63 / AN3

R62 / AN2

R61 / AN1

R60 / AN0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

R01

AV

DD

SS

R02

R03

R04

R05

R06

R07

R54 / PWM3O / T3O

R53 / PWM1O / T1O

R52 / T2O

R51 / EC1

R50 / INT3

R47 / TxD0

R46 / RxD0

R45 / ACLK0

R44 / SO

R43 / SI

R42 / SCK

R41

R40

R37

R36

R35

R34

R33 / TxD1

R32 / RxD1

R31 / ACLK1

R30

INT0 / R10

INT1 / R11

INT2 / R12

BUZO / R13

T0O /R14

EC0 / R15

R16

R17

R20

SX / R21

IN

OUT

SX

/ R22

R23

RESET

X

OUT

IN

X

V

SS

64MQFP

(Top View)

R35

32

AN2 / R62

AN3 / R63

AN4 / R64

AN5 / R65

AN6 / R66

AN7 / R67

52

R34

31

53

54

55

56

57

58

59

60

61

62

63

64

R33 / TxD1

R32 / RxD1

30

29

28

27

26

25

24

23

22

21

20

R31 / ACLK1

R30

V

MC80F0424/0432/0448Q

SS

DD

X

AN8 / R70

AN9 / R71

AN10 / R72

AN11 / R73

AN12 / R74

AN13 / R75

OUT

IN

RESET

R23

R22 / SX

OUT

R21 / SX

IN

MAR. 2005 Ver 0.2

5

MC80F0424/0432/0448

Preliminary

64LQFP

(Top View)

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

AN1 / R61

AN2 / R62

AN3 / R63

AN4 / R64

AN5 / R65

AN7 / R67

R37

R36

R35

R34

R33 / TxD1

R32 / RxD1

R31 / ACLK1

R30

V

DD

MC80F0424/0432/0448L

V

AN8 / R70

SS

OUT

IN

X

AN9 / R71

X

AN10 / R72

AN11 / R73

AN12 / R74

AN13 / R75

AN14 / R76

AN15 / R77

RESET

R23

R22 / SX^OUT

R21/ SX^IN

R20

6

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

4. PACKAGE DIAGRAM

64SDIP

UNIT: INCH

2.280

2.260

0.750 Typ.

0.680

0.660

0.070 BSC

0.050

0.030

0.022

0.016

0-15°

64MQFP

24.15

23.65

20.10

19.90

UNIT: MM

0-7°

SEE DETAIL “A”

1.03

0.73

3.18 max.

1.95

REF

1.00 BSC

0.50

0.35

DETAIL “A”

MAR. 2005 Ver 0.2

7

MC80F0424/0432/0448

Preliminary

64LQFP

12.00 BSC

10.00 BSC

UNIT: MM

0-7°

SEE DETAIL "A"

0.75

0.45

1.60 max.

1.00

REF

0.50 BSC

0.38

0.22

DETAIL "A"

8

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

5. PIN FUNCTION

V_DD: Supply voltage.

port with typical 20mA at low level output.

In addition, R3 serves the functions of the various following spe-

cial features such as ACLK1 (UART1 Asynchronous serial clock

input), RxD1 (UART1 data input), TxD1 (UART1 data output)

V_SS: Circuit ground.

AV_DD: Supply voltage to the ladder resistor of ADC circuit.

AV_SS: ADC circuit ground.

R40~R47: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins

with 1 or 0 written to the R4 Port Direction Register R4IO can be

used as outputs or inputs. The internal pull-up resistor can be con-

nected by using the pull-up selection register 4 (PU4).

In addition, R4 serves the functions of the various following spe-

cial features such as SCK (Serial clock), SI (Serial data input), SO

(Serial data output), ACLK0 (UART0 Asynchronous serial clock

input), RxD0 (UART0 data input), TxD0 (UART0 data output).

RESET: Reset the MCU.

X_IN: Input to the inverting oscillator amplifier and input to the in-

ternal main clock operating circuit.

X_OUT: Output from the inverting oscillator amplifier.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins

with 1 or 0 written to the R0 Port Direction Register R0IO can be

used as outputs or inputs. The internal pull-up resistor can be con-

nected by using the pull-up selection register 0 (PU0).

R50~R54: R5 is an 5-bit CMOS bidirectional I/O port. R5 pins

with 1 or 0 written to the R5 Port Direction Register R5IO can be

used as outputs or inputs.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins

with 1 or 0 written to the R1 Port Direction Register R1IO can be

used as outputs or inputs. The internal pull-up resistor can be con-

nected by using the pull-up selection register 1 (PU1).

In addition, R1 serves the functions of the various following spe-

cial features such as INT0 (External interrupt 0), INT1 (External

interrupt 1), INT2 (External interrupt 2), BUZO (Buzzer driver

output), T0O (Timer 0 output), EC0 (Event counter input 0).

In addition, R5 serves the functions of the various following spe-

cial features such as INT3 (External interrupt 3), EC1 (Event

counter input 1), T2O (Timer 2 output), PWM1O (PWM 1 out-

put) / T1O (Timer 1 compare output), PWM3O (PWM 3 output)

/ T3O (Timer 3 compare output).

R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins

with 1 or 0 written to the R6 Port Direction Register R6IO can be

used as outputs or inputs.

In addition, R6 serves the functions of the ADC analog input port

AN[7:0].

R20~R23: R2 is an 4-bit CMOS bidirectional I/O port. R2 pins

with 1 or 0 written to the R2 Port Direction Register R2IO can be

used as outputs or inputs.

R70~R77: R7 is an 8-bit CMOS bidirectional I/O port. R7 pins

with 1 or 0 written to the R7 Port Direction Register R7IO can be

used as outputs or inputs. The internal pull-up resistor can be con-

nected by using the pull-up selection register 7 (PU7).

In addition, R7 serves the functions of the ADC analog input port

AN[15:8].

In addition, R2 serves the functions of the various following spe-

cial features such as SX_IN(Sub clock input), SX_OUT(Sub clock

output).

R30~R37: R3 is an 8-bit CMOS bidirectional I/O port. R3 pins

with 1 or 0 written to the R3 Port Direction Register R3IO can be

used as outputs or inputs. R3 operates as the high current output

MAR. 2005 Ver 0.2

9

MC80F0424/0432/0448

Preliminary

5.1 MC80F0424/0432/0448 Pin Description

5.1.1 MC80F0424/0432/0448 Pin Description

Initial

state

Alternate

Function

PIN NAME In/Out

Function

Port 0.

8-bit I/O port.

Can be set as input or output mode in 1-bit units.

Internal pull-up resistor PU0 can be used via software.

R00~R07

I/O

Input

-

R10

R11

R12

R13

R14

R15

R16

R17

R20

R21

INT0

INT1

INT2

BUZO

T0O

EC0

-

Port 1.

8-bit I/O port.

Input

Can be set as input or output mode in 1-bit units.

Internal pull-up resistor PU1 can be used via software.

-

Port 2.

4-bit I/O port.

SX_IN

I/O

Input

Can be set in input or output mode in 1-bit units.

Crystal(32.768KHz) connecting pins(R21,R22)

SX_OUT

-

R22

R23

P30

P31

P32

P33

P34

P35

P36

P37

R40

R41

R42

R43

R44

R45

R46

R47

R50

R51

R52

R53

R54

ACLK1

RxD1

TxD1

Port 3.

8-bit I/O port.

Can be set in input or output mode in 1-bit units.

Operates as high current output port with typical 20mA at low level

output.

-

SCK

Port 4.

8-bit I/O port.

SI

I/O

Input

Can be set in input or output mode in 1-bit units.

Internal pull-up resistor PU4 can be used via software.

SO

ACLK0

RxD0

TxD0

INT3

EC1

Port 5.

5-bit I/O port.

Can be set in input or output mode in 1-bit units.

I/O

Input

T2O

PWM1O/T1O

PWM3O/T3O

Table 5-1 MC80F0424/0432/0448 Pin Description

10

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Initial

state

Alternate

Function

PIN NAME In/Out

Function

Port 6.

R60~R67

R70~R77

I/O

8-bit I/O port.

Can be set in input or output mode in 1-bit units.

Input

AN0~AN7

Port 7.

8-bit I/O port.

Input

AN8~AN15

Can be set in input or output mode in 1-bit units.

Internal pull-up resistor PU7 can be used via software.

RESET

X_IN

I

System reset input.

Input

-

Crystal connection for main system clock oscillation.

X_OUT

AV_DD

O

Output

Analog power/reference voltage input to A/D converter.

Set the same potential as VDD.

-

AV_SS

V_DD

V_SS

Ground potential for A/D converter. Set the same potential as V_SS

.

-

Positive power supply.

Ground potential.

Table 5-1 MC80F0424/0432/0448 Pin Description

MAR. 2005 Ver 0.2

11

MC80F0424/0432/0448

Preliminary

5.1.2 MC80F0424/0432/0448 Alternate Function Pin Description

Initial

state

Shared

PIN NAME

In/Out

Function

INT0

INT1

INT2

INT3

BUZO

T0O

R10

R11

R12

R50

R13

R14

R52

R15

R51

R21

Valid edges(rising, falling, or both rising and falling) can be spec-

ified. External Interrupt request Input.

I

Input

O

I

Buzzer Output

Input

Timer0 Output

T2O

Timer2 Output

EC0

Timer0 Event Counter Input

Timer2 Event Counter Input

EC1

I

SX_IN

I

Resonator connecting pins (32.768KHz)

SX_OUT

O

I

Input

R22

R31

ACLK1

RxD1

UART1 Asynchronous serial interface serial clock input.

UART1 Asynchronous serial interface serial data input.

UART1 Asynchronous serial interface serial data output.

Serial clock input/output of serial interface.

I

R32

TxD1

O

I/O

I

R33

SCK

R42

SI

Serial data input of serial interface.

R43

SO

O

I

Serial data output of serial interface.

R44

ACLK0

RxD0

UART0 Asynchronous serial interface serial clock input.

UART0 Asynchronous serial interface serial data input.

UART0 Asynchronous serial interface serial data output.

Timer1 PWM Output / Timer 1 Compare Output

Timer3 PWM Output / Timer 1 Compare Output

Analog input Channel 0 ~ 7 for A/D converter.

Analog input Channel 8 ~ 15 for A/D converter.

R45

I

R46

TxD0

O

I

R47

PWM1O/T1O

PWM3O/T3O

AN0~AN7

AN8~AN15

R53

R54

R60~R67

R70~R77

I

Table 5-2 MC80F0424/0432/0448 Alternate Function Pin Description

12

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

6. PORT STRUCTURES

R00~R07, R16, R17, R40, R41

R50(INT3),R51(EC1)

V

DD

V

DD

Data Reg.

V

DD

Direction

Reg.

Pull-up

Tr.

Pull-up

Reg.

V

DD

V

SS

DD

Data Reg.

Data Bus

MUX

Direction

Reg.

RD

V

SS

V

SS

Noise

Filter

INT3,EC1

Data Bus

MUX

INT3_EN,EC1_EN

RD

R33(TxD1)

TxD1

V

DD

V

DD

R10(INT0), R11(INT1), R12(INT2), R15(EC0),

R43(SI),R45(ACLK0),R46(RxD0)

MUX

Data Reg.

V

Direction

Reg.

DD

Pull-up

Tr.

Pull-up

Reg.

V

SS

V

SS

TxD1_EN

V

DD

V

DD

Data Reg.

MUX

Data Bus

Direction

Reg.

RD

V

SS

V

SS

Data Bus

MUX

RD

Noise

Filter

INT,EC,SI,

ACLK0,RxD0

INT_EN,SI_EN,ACLK0_EN,

EC_EN,RxD_EN

MAR. 2005 Ver 0.2

13

MC80F0424/0432/0448

Preliminary

R31(ACLK1), R32(RxD1)

R52(T2O), R53(PWM1O), R54(PWM3O)

V

DD

V

DD

T2O,PWM1O,PWM3O

V

DD

Data Reg.

V

DD

MUX

Data Reg.

Direction

Reg.

Direction

Reg.

V

SS

V

SS

V

SS

PWM1_EN,T2O_EN

PWM3_EN

Data Bus

MUX

RD

Data Bus

RD

Noise

Filter

ACLK1,RxD1

ACLK1_EN, RxD1_EN

R13(BUZO), R14(T0O), R47(TxD0)

R20, R23, R30~R37

V

DD

V

DD

V

DD

Data Reg.

Pull-up

Tr.

Pull-up

Reg.

Direction

Reg.

V

BUZO,T0O,TxD0

DD

V

DD

V

SS

V

SS

MUX

Data Reg.

Data Bus

Direction

Reg.

MUX

V

SS

V

SS

BUZO_EN, T0O_EN

TxD0_EN

RD

MUX

RD

Data Bus

14

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

R42(SCK)

R60~R67(AN0~AN7)

V

DD

V

DD

V

DD

Pull-up

Tr.

Data Reg.

Pull-up

Reg.

V

SCK

Direction

Reg.

DD

V

DD

MUX

Data Reg.

V

SS

V

SS

Direction

Reg.

Data Bus

MUX

RD

V

SS

SCKO_EN

Data Bus

V

SS

MUX

RD

AN[7:0]

ADC_EN & CH_SEL

SCKI_EN

SCK

Noise

Filter

R70~R77(AN8~AN15)

V

DD

Pull-up

Tr.

R44(SO, IOSWIN(SI))

Pull-up

Reg.

V

DD

V

DD

V

DD

Pull-up

Tr.

Data Reg.

Pull-up

Reg.

V

Direction

Reg.

SO

DD

V

DD

Data Reg.

MUX

V

SS

V

SS

Direction

Reg.

Data Bus

MUX

RD

V

SS

V

SS

SO_EN

Data Bus

MUX

RD

AN[15:0]

IOSWIN_EN

SI

ADC_EN & CH_SEL

Noise

Filter

IOSWIN_EN(SI)

MAR. 2005 Ver 0.2

15

MC80F0424/0432/0448

RESET

Preliminary

X_IN, X_OUT

V

DD

V

DD

Mask only

X

IN

Internal Reset

STOP

V

SS

V

SS

V

SS

V

DD

MAIN

CLOCK

X

OUT

R21(SX ), R22(SX

)

OUT

IN

V

DD

SS

V

DD

Data Reg.

Direction

Reg.

SX

IN

V

SS

V

SS

Data Bus

MUX

RD

XT_EN

V

DD

V

DD

Data Reg.

Direction

Reg.

SX

OUT

V

SS

V

SS

Data Bus

MUX

RD

16

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage........................................................-0.3 to +6.5 V

Storage Temperature .............................................-40 to +125 °C

Maximum current (ΣI_OL) .................................................160 mA

Maximum current (ΣI_OH)...................................................80 mA

Voltage on any pin with respect to Ground (V_SS

)

Note: Stresses above those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of

the device at any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

..........................................................................-0.3 to V_DD+0.3V

Maximum current out of V_SSpin.....................................200 mA

Maximum current into V_DDpin.......................................100 mA

Maximum current sunk by (I_OLper I/O Pin) .....................20 mA

Maximum output current sourced by (I_OHper I/O Pin)

............................................................................................10 mA

7.2 Recommended Operating Conditions

Specifications

Unit

Parameter

Symbol

Condition

f_XIN=0.4~12MHz

Min.

Max.

4.5

2.7

5.5

V_DD

Supply Voltage

V

f_XIN=0.4~4MHz

V_DD=4.5~5.5V

V_DD=2.7~5.5V

0.4

12

4

f_XIN

Operating Frequency

MHz

T_OPR

Operating Temperature

-40

85

°C

7.3 A/D Converter Characteristics

(T_a=-40~85°C, V_SS=0V, V_DD=2.7~5.5V @Conversion Clock of 1MHz)

Parameter

Resolution

Symbol

Conditions

Min.

Typ.

Max.

Unit

BIT

LSB

µS

-

±10

-

±3

N_ACC

N_NLE

N_DNLE

N_FSE

N_ZOE

N_NLE

T_CONV

V_AIN

Overall Accuracy

Non Linearity Error

Differential Non Linearity Error

Full Scale Error

-

±3

-

±3

-

±3

Zero Offset Error

-

±3

Gain Error

-

±3

f_XIN

Conversion Time

Analog Input Voltage

Analog Power Supply

Analog Ground

13

-

AV_SS

AV_DD

V_DD

V_SS+0.3

-

V

AV_DD

AV_SS

I_AVDD

-

V

V_SS

-

V

AV_DD=V_DD=5.12V

Analog Block Current

-

2.5

3

mA

MAR. 2005 Ver 0.2

17

MC80F0424/0432/0448

Preliminary

7.4 DC Electrical Characteristics

(T_A=-40~85°C, V_DD=5.0V±10%, V_SS=0V, f_XIN=8MHz)

Parameter

Symbol

Pin/Condition

Min.

Typ.

Max.

Unit

INT0, INT1, INT2, INT3, EC0, EC1,

SI, SCK, ACLK0, RxD0, ACLK1,

RxD1, RESET

V_IH1

0.8V_DD

V_DD+0.3

-

V

Input High Voltage

V_IH2

V_IH3

0.7V_DD

0.8V_DD

V_DD+0.3

R0, R1, R2, R3, R4, R5, R6, R7

X_IN, SX_IN

-

V

INT0, INT1, INT2, INT3, EC0, EC1,

SI, SCK, ACLK0, RxD0, ACLK1,

RxD1, RESET

V_IL1

0.2V_DD

-0.3

-

V

Input Low Voltage

V_IL2

V_IL3

0.3V_DD

0.2V_DD

R0, R1, R2, R3, R4, R5, R6, R7

X_IN, SX_IN

-0.3

-

V

R0, R1, R2, R3, R4, R5, R6, R7

(I_OH=-0.7mA)

V_OH1

V_DD-0.4

-

V

Output High Voltage

V_OH2

V_OH3

X_OUT(I_OH=-50µA)

SX_OUT(I_OH=-5µA)

V_DD-0.5

-

V

R0, R1, R2, R3, R4, R5, R6, R7

(I_OL=1.6mA)

V_OL1

-

0.4

V

Output Low Voltage

High Current

V_OL2

V_OL3

I_OL

X_OUT(I_OL=50µA)

SX_OUT(I_OL=5µA)

R3 (V_OL=1V)

-

0.5

20

V

mA

Input High Leakage

Current

I_IH

I_IL

R0, R1, R2, R3, R4, R5, R6, R7

-

1

-

µA

Input Low

Leakage Current

-1

RPU

R_X

10

0.45

8

100

4.5

18

Pull-up Resistor

R0, R1, R4, R7

X_IN, X_OUT

-

kΩ

MΩ

OSC Feedback Resistor

R_SX

SX_IN, SX_OUT

Internal RC WDT Period

(RCWDT)

I_IL

V_DD=4.5V

33

-

100

0.8

µS

INT0, INT1, INT2, INT3, EC0, EC1,

SI, SCK, ACLK, RxD

V_T

Hysteresis

0.3

V

2.2

2.5

1.9

-

2.7

3.0

2.4

-

3.2

3.5

2.9

15

V

Power Fail Detect

Voltage

V_PFD

V

I_DD1

I_DD2

Active Mode, X =8MHz

mA

IN

Sub_Active Mode, SX =0.32MHz

160

-

µA

mA

µA

IN

I_SLEEP1Sleep Mode, X =8MHz

Power Supply Current

-

6

20

5

IN

I_SLEEP2Sub_Sleep Mode, SX =0.32MHz

IN

Stop Mode, Oscillator Stop, X =4MHz

I_STOP

IN

18

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7.5 AC Characteristics

(T_A=-40~85°C, V_DD=5V±10%, V_SS=0V)

Specifications

Parameter

Symbol

Pins

Unit

Min.

Typ.

Max.

f_XIN

X_IN

-

Operating Frequency

0.4

-

12

MHz

nS

System Clock Cycle

Time

t_SYS

166

-

5000

20

-

Oscillation Stabilizing

Time (4MHz)

t_ST

X_IN, X_OUT

X_IN

-

35

-

mS

nS

External Clock Pulse

Width

t_CPW

External Clock Transi-

tion Time

t

_RCP,t_FCP

X_IN

20

t_IW

t_SYS

Interrupt Pulse Width

RESET Input Width

INT0, INT1, INT2, INT3

RESET

2

8

-

t_RST

Event Counter Input

Pulse Width

t_ECW

t_SYS

nS

EC0, EC1

2

-

Event Counter Transi-

tion Time

t_{REC, FEC}

t

20

t

= 1/f

t

CPW

SYS

XIN

CPW

0.9V

DD

X_IN

0.1V

DD

t

RCP

FCP

t

IW

0.8V

DD

INT0~INT3

RESET

0.2V

DD

t

RST

0.2V

DD

t

ECW

0.8V

DD

EC0, EC1

0.2V

DD

t

REC

FEC

Figure 7-1 Timing Chart

MAR. 2005 Ver 0.2

19

MC80F0424/0432/0448

Preliminary

7.6 Serial Interface Timing Characteristics

(T_A=-40~+85°C, V_DD=5V±10%, V_SS=0V, f_XIN=8MHz)

Specifications

Parameter

Serial Input Clock Pulse

Symbol

Pins

Unit

Min.

Typ.

Max.

t_SCYC

t_SCKW

t_FSCK

t_RSCK

t_FSIN

t_RSIN

t_SUS

2t_SYS+200

t_SYS+70

SCK

-

nS

Serial Input Clock Pulse Width

Serial Input Clock Pulse Transition Time

SCK

SI

-

30

nS

Serial Input Pulse Transition Time

30

-

Serial Input Setup Time (External SCK)

Serial Input Setup Time (Internal SCK)

Serial Input Hold Time

SI

100

200

-

nS

t_HS

t_SYS+70

4t_SYS

SI

t_SCYC

t_SCKW

t_FSCK

t_RSCK

16t_SYS

Serial Output Clock Cycle Time

Serial Output Clock Pulse Width

SCK

t_SYS-30

Serial Output Clock Pulse Transition Time

Serial Output Delay Time

SCK

SO

30

nS

s_OUT

100

t

SCYC

t

RSCK

FSCK

t

SCKW

0.8V

0.2V

DD

SCLK

t

SUS

HS

0.8V

DD

SI

0.2V

t

FSIN

RSIN

t

DS

SO

0.8V

0.2V

DD

Figure 7-2 Serial I/O Timing Chart

20

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7.7 Typical Characteristic Curves

This graphs and tables provided in this section are for design

guidance only and are not tested or guaranteed.

The data presented in this section is a statistical summary of data

collected on units from different lots over a period of time. “Typ-

ical” represents the mean of the distribution while “max” or

“min” represents (mean + 3σ) and (mean − 3σ) respectively

where σ is standard deviation

In some graphs or tables the data presented are out-

side specified operating range (e.g. outside specified

V_DDrange). This is for information only and devices

are guaranteed to operate properly only within the

specified range.

I

−V

I

−V

R0~R7 pins

OH

OH OH

I

OH

V

=5.0V

V

=3.0V

DD

T =25°C

(mA)

DD

T =25°C

A

-12

-9

-6

-9

-6

-3

0

-3

0

(V)

V -V

DD OH

0.5 1.0

V

-V

0.5 1.0

1.5 2.0 2.5

1.5 2.0

(V)

DD OH

−V

I

−V

OL1

R0~R2, R4~R7 pins

OL

OL1

R0~R2, R4~R7 pins

OL

I

OL

V

=3.0V

V

=5.0V

DD

(mA)

DD

(mA)

T =25°C

A

20

40

15

10

30

20

5

0

10

0

V

(V)

OL

0.5 1.0

1.5 2.0

R3 pin

V

0.5 1.0

2.5

1.5 2.0

(V)

OL

−V

I

−V

OL2

OL

V

OL2

R3 pin

OL

I

OL

=3.0V

V

=5.0V

DD

(mA)

DD

(mA)

T =25°C

A

20

40

15

10

30

20

5

0

10

0

(V)

V

OL

0.5 1.0

1.5 2.0

0.5 1.0

2.5

(V)

V

OL

1.5 2.0

MAR. 2005 Ver 0.2

21

MC80F0424/0432/0448

Preliminary

I

−V

DD

I

−V

I

−V

DD

Main Active Mode

SLEEP

DD

Main Active Mode

STOP DD

Main Active Mode

I

DD

(mA)

(µA)

T =25°C

A

10

4

7.5

5

3

2

3

f

= 12MHz

XIN

8MHz

2

8MHz

V

f

= 12MHz

XIN

f

= 12MHz, 8MHz, 4MHz

XIN

2.5

0

1

0

1

0

4MHz

5

4MHz

5

V

DD

(V)

2

3

6

(V)

6

4

2

3

(V)

6

4

2

3

4

5

I

−V

DD

I

−V

DD

Sub Active Mode1

SLEEP

Sub Active Mode1

I

DD

T =25°C

(mA)

A

T =25°C

A

4

2

f

= 12MHz, 8MHz, 4MHz

XIN

3

2

1.5

1

f

= 12MHz, 8MHz, 4MHz

XIN

1

0

0.5

0

V

DD

(V)

2

3

6

(V)

6

4

5

2

3

4

5

I

−V

I

−V

DD

SLEEP

DD

Sub Active Mode2

DD

Sub Active Mode2

I

DD

(µA)

T =25°C

A

20

500

f

= 12MHz, 8MHz, 4MHz

XIN

15

10

175

250

5

0

125

0

V

(V)

6

V

(V)

6

DD

2

3

4

5

2

3

4

5

* Main Active mode : System clock(Main)

* Sub Active mode1 : System clock(Sub) (at main clock ON, sub clock ON)

* Sub Active mode2 : System clock(Sub) (at main clock OFF, sub clock ON)

22

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Operating Area

f

XIN

(MHz)

T = -40~85°C

A

16

Actual Operating Area

2.2~6.5V @ (0.1~8MHz)

3.0~6.5V @ (0.1~16MHz)

14

12

10

8

Spec Operating Area

2.7~5.5V @ (0.4~8MHz)

4.5~5.5V @ (0.4~12MHz)

6

4

2

0

V

(V)

1

2

3

6

4

5

7

DD

MAR. 2005 Ver 0.2

23

MC80F0424/0432/0448

Preliminary

8. MEMORY ORGANIZATION

The MC80F0424/0432/0448 has separate address spaces for Pro-

gram memory and Data Memory. Program memory can only be

read, not written to. It can be up to 48K bytes of Program memo-

ry. Data memory can be read and written to up to 1024 bytes in-

cluding the stack area.

8.1 Registers

This device has six registers that are the Program Counter (PC),

a Accumulator (A), two index registers (X, Y), the Stack Pointer

(SP), and the Program Status Word (PSW). The Program Counter

consists of 16-bit register.

executed or an interrupt is accepted. However, if it is used in ex-

cess of the stack area permitted by the data memory allocating

configuration, the user-processed data may be lost.

The stack can be located at any position within 100_Hto 1FF_Hof

the internal data memory. The SP is not initialized by hardware,

requiring to write the initial value (the location with which the use

of the stack starts) by using the initialization routine. Normally,

the initial value of “FF_H” is used.

A

X

ACCUMULATOR

X REGISTER

Y REGISTER

Y

Stack Address (100 ~ 1FF )

H

STACK POINTER

SP

Bit 15

8 7

Bit 0

01

SP

H

PROGRAM COUNTER

PCH

PCL

00 ~FF

H

PSW

PROGRAM STATUS WORD

Hardware fixed

Figure 8-1 Configuration of Registers

Note: The Stack Pointer must be initialized by software be-

cause its value is undefined after Reset.

Accumulator: The Accumulator is the 8-bit general purpose reg-

ister, used for data operation such as transfer, temporary saving,

and conditional judgement, etc.

Example: To initialize the SP

The Accumulator can be used as a 16-bit register with Y Register

as shown below.

LDX

#0FFH

TXSP

; SP ← FFH

Y

Program Counter: The Program Counter is a 16-bit wide which

consists of two 8-bit registers, PCH and PCL. This counter indi-

cates the address of the next instruction to be executed. In reset

state, the program counter has reset routine address (PC_H:0FF_H,

PC_L:0FE_H).

Y

A

Two 8-bit Registers can be used as a “YA” 16-bit Register

Program Status Word: The Program Status Word (PSW) con-

tains several bits that reflect the current state of the CPU. The

PSW is described in Figure 8-3. It contains the Negative flag, the

Overflow flag, the Break flag the Half Carry (for BCD opera-

tion), the Interrupt enable flag, the Zero flag, and the Carry flag.

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers: In the addressing mode which uses these index

registers, the register contents are added to the specified address,

which becomes the actual address. These modes are extremely ef-

fective for referencing subroutine tables and memory tables. The

index registers also have increment, decrement, comparison and

data transfer functions, and they can be used as simple accumula-

tors.

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU after

an arithmetic operation and is also changed by the Shift Instruc-

tion or Rotate Instruction.

[Zero flag Z]

Stack Pointer: The Stack Pointer is an 8-bit register used for oc-

currence interrupts and calling out subroutines. Stack Pointer

identifies the location in the stack to be accessed (save or restore).

This flag is set when the result of an arithmetic operation or data

transfer is “0” and is cleared by any other result.

Generally, SP is automatically updated when a subroutine call is

24

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

MSB

N

LSB

C

V

G

B

H

I

Z

RESET VALUE: 00

PSW

NEGATIVE FLAG

H

CARRY FLAG RECEIVES

CARRY OUT

OVERFLOW FLAG

ZERO FLAG

SELECT DIRECT PAGE

when G=1, page is selected to “page 1”

INTERRUPT ENABLE FLAG

HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF

ADDITION OPERLANDS

BRK FLAG

Figure 8-3 PSW (Program Status Word) Register

This flag assigns RAM page for direct addressing mode. In the di-

[Interrupt disable flag I]

rect addressing mode, addressing area is from zero page 00_Hto

0FF_Hwhen this flag is "0". If it is set to "1", addressing area is

assigned 100_Hto 1FF_H. It is set by SETG instruction and cleared

by CLRG.

This flag enables/disables all interrupts except interrupt caused

by Reset or software BRK instruction. All interrupts are disabled

when cleared to “0”. This flag immediately becomes “0” when an

interrupt is served. It is set by the EI instruction and cleared by

the DI instruction.

[Overflow flag V]

[Half carry flag H]

This flag is set to “1” when an overflow occurs as the result of an

arithmetic operation involving signs. An overflow occurs when

the result of an addition or subtraction exceeds +127(7F_H) or -

128(80_H). The CLRV instruction clears the overflow flag. There

is no set instruction. When the BIT instruction is executed, bit 6

of memory is copied to this flag.

After operation, this is set when there is a carry from bit 3 of ALU

or there is no borrow from bit 4 of ALU. This bit can not be set

or cleared except CLRV instruction with Overflow flag (V).

[Break flag B]

This flag is set by software BRK instruction to distinguish BRK

from TCALL instruction with the same vector address.

[Negative flag N]

This flag is set to match the sign bit (bit 7) status of the result of

a data or arithmetic operation. When the BIT instruction is exe-

cuted, bit 7 of memory is copied to this flag.

[Direct page flag G]

MAR. 2005 Ver 0.2

25

MC80F0424/0432/0448

Preliminary

At execution of

a CALL/TCALL/PCALL

At acceptance

of interrupt

At execution

of RET instruction

At execution

of RET instruction

Push

down

01FF

01FE

01FD

01FC

PCH

PCL

01FF

01FE

01FD

PCH

PCL

PSW

01FF

01FE

01FD

PCH

01FF

01FE

01FD

PCH

Pop

up

Push

down

Pop

up

PCL

PSW

01FC

SP before

execution

01FF

01FD

01FF

01FC

01FD

01FF

01FC

01FF

SP after

execution

At execution

of PUSH instruction

PUSH A (X,Y,PSW)

of POP instruction

POP A (X,Y,PSW)

Push

down

Pop

up

01FF

01FE

01FF

01FE

A

0100H

Stack

depth

01FD

01FC

01FD

01FC

01FFH

SP before

01FF

01FE

01FF

execution

SP after

execution

Figure 8-4 Stack Operation

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K

bytes, but this device has 24/32/48K bytes program memory

space only physically implemented. Accessing a location above

FFFF_Hwill cause a wrap-around to 0000_H.

CPU begins execution from reset vector which is stored in ad-

dress FFFE_Hand FFFF_Has shown in Figure 8-6.

As shown in Figure 8-5, each area is assigned a fixed location in

Program Memory. Program Memory area contains the user pro-

gram

Figure 8-5, shows a map of Program Memory. After reset, the

26

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

.

Example: Usage of TCALL

LDA

#5

TCALL 0FH

;

1BYTE INSTRUCTION

INSTEAD OF 3 BYTES

NORMAL CALL

:

4000

H

;

;TABLE CALL ROUTINE

;

8000

H

FUNC_A: LDA

LRG0

RET

;

A000

H

FUNC_B: LDA

LRG1

2

1

RET

;

;TABLE CALL ADD. AREA

;

FEFF

ORG

DW

0FFC0H

FUNC_A

FUNC_B

;TCALL ADDRESS AREA

H

FF00

H

FFC0

TCALL area

FFDF

H

FFE0

Interrupt

Vector Area

FFFF

H

The interrupt causes the CPU to jump to specific location, where

it commences the execution of the service routine. The External

interrupt 0, for example, is assigned to location 0FFFC_H. The in-

terrupt service locations spaces 2-byte interval: 0FFFA_Hand

0FFFB_Hfor External Interrupt 1, 0FFFC_Hand 0FFFD_Hfor Ex-

ternal Interrupt 0, etc.

Figure 8-5 Program Memory Map

Page Call (PCALL) area contains subroutine program to reduce

program byte length by using 2 bytes PCALL instead of 3 bytes

CALL instruction. If it is frequently called, it is more useful to

save program byte length.

Any area from 0FF00_Hto 0FFFF_H, if it is not going to be used,

its service location is available as general purpose Program Mem-

ory.

Table Call (TCALL) causes the CPU to jump to each TCALL ad-

dress, where it commences the execution of the service routine.

The Table Call service area spaces 2-byte for every TCALL:

0FFC0_Hfor TCALL15, 0FFC2_Hfor TCALL14, etc., as shown in

Figure 8-7.

Address

Vector Area Memory

Basic Interval Timer

0FFE0

H

E2

E4

E6

E8

Watch / Watchdog Timer Interrupt

A/D Converter

Timer/Counter 4 Interrupt

Timer/Counter 3 Interrupt

Timer/Counter 2 Interrupt

Timer/Counter 1 Interrupt

Timer/Counter 0 Interrupt

Serial Input/Output (SIO)

UART1

EA

EC

EE

F0

F2

F4

F6

F8

FA

FC

FE

UART0

External Interrupt 3

External Interrupt 2

External Interrupt 1

External Interrupt 0

RESET

Figure 8-6 Interrupt Vector Area

MAR. 2005 Ver 0.2

27

MC80F0424/0432/0448

Preliminary

Address

Program Memory

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

PCALL Area Memory

Address

0FFC0

0FF00

H

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

TCALL 8

PCALL Area

(256 Bytes)

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

0FFFF

H

NOTE:

* means that the BRK software interrupt is using

same address with TCALL0.

Figure 8-7 PCALL and TCALL Memory Area

PCALL→ rel

TCALL→ n

4F35

PCALL 35H

4A

TCALL 4

4A

01001010

4F

35

Reverse

➊

~

PC: 11111111 11010110

FH FH DH 6H

H

0FF00

H

➊

0FF00

➊

0FF35

H

0FFD6

0FFD7

25

H

D1

0FFFF

H

28

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Example: The usage software example of Vector address for MC80F0448.

;Interrupt Vector Table

ORG

DW

0FFE0H

BIT_TIMER

WATCH_WDT

ADC

TIMER4

TIMER3

TIMER2

TIMER1

TIMER0

SIO

; BIT

; WDT & WT

; AD Converter

; Timer-4

; Timer-3

; Timer-2

; Timer-1

; Timer-0

; Serial Interface

; UART1 Rx/Tx

; UART0 Rx/Tx

; Ext Int.3

; Ext Int.2

; Ext Int.1

; Ext Int.0

; Reset

UART1

UART0

INT3

INT2

INT1

INT0

RESET

ORG

04000H

; 48K bytes ROM Start address

;*******************************************

;

MAIN

PROGRAM

*

;*******************************************

RESET:

DI

;Disable All Interrupt

RAMCLEAR:

LDX

LDY

#00H

#0

;USER RAM START ADDRESS LOAD !

RAMCLR1:

LDA

STA

#00H

;Page0 Ram Clear(0000h ~ 00BFh)

{X}+

;

CMPX #0C0H

BNE

RAMCLR1

INC

Y

!RPR

;

STY

;Page1 Ram Select

;G-FLAG SET !

SETG

LDX

#00H

RAMCLR2:

LDA

STA

#00H

{X}+

CMPX #00H

BNE

RAMCLR2

INC

Y

CMPY #6

BCS

RAMCLR3

;Page1 ~ Page5 Clear(0100h ~ 04FFh)

STY

SETG

!RPR

BRA

RAMCLR2

RAMCLR3:

STY

SETG

LDA

STA

!RPR

;Page6 Clear(0600h ~ 063Fh)

#00H

{X}+

;A <-- #0

;

CMPX #40H

BNE

RAMCLR3

CLRG

;G-FLAG CLEAR !

LDX

TXSP

#0FFH

;Initial Stack Point (01FFh)

MAR. 2005 Ver 0.2

29

MC80F0424/0432/0448

8.3 Data Memory

Preliminary

Figure 8-8 shows the internal Data Memory space available. Data

Memory is divided into three groups, a user RAM, control regis-

ters, and Stack memory.

Control Registers

The control registers are used by the CPU and Peripheral function

blocks for controlling the desired operation of the device. There-

fore these registers contain control and status bits for the interrupt

system, the timer/ counters, analog to digital converters and I/O

ports. The control registers are in address range of 0C0_Hto 0FF_H.

0000

H

User Memory

(192Bytes)

PAGE0

00BF

00C0

H

(When “G-flag=0”,

this page0 is selected)

Control

Registers (64Bytes)

Note that unoccupied addresses may not be implemented on the

chip. Read accesses to these addresses will in general return ran-

dom data, and write accesses will have an indeterminate effect.

00FF

0100

H

User Memory

or Stack Area

(256Bytes)

PAGE1

PAGE2

PAGE3

PAGE4

01FF

0200

H

More detailed informations of each register are explained in each

peripheral section.

User Memory

(256Bytes)

02FF

0300

H

Note: Write only registers can not be accessed by bit ma-

nipulation instruction. Do not use read-modify-write instruc-

tion. Use byte manipulation instruction, for example “LDM”.

User Memory

(256Bytes)

03FF

0400

H

User Memory

(256Bytes)

Example; To write at CKCTLR

04FF

0500

H

LDM

CLCTLR,#0AH;Divide ratio(÷32)

User Memory

(256Bytes)

PAGE5

PAGE6

05FF

0600

H

User Memory

(64Bytes)

063F

0640

H

Stack Area

H

Not Used

The stack provides the area where the return address is saved be-

fore a jump is performed during the processing routine at the ex-

ecution of a subroutine call instruction or the acceptance of an

interrupt.

0EBF

0EC0

H

Extended SFR

(64Bytes)

0EFF

H

When returning from the processing routine, executing the sub-

routine return instruction [RET] restores the contents of the pro-

gram counter from the stack; executing the interrupt return

instruction [RETI] restores the contents of the program counter

and flags.

Figure 8-8 Data Memory Map

User Memory

The MC80F0424/0432/0448 has 1.5kbytes for the user memory

(RAM). RAM pages are selected by RPR (See Figure 8-9).

The save/restore locations in the stack are determined by the

stack pointed (SP). The SP is automatically decreased after the

saving, and increased before the restoring. This means the value

of the SP indicates the stack location number for the next save.

Refer to Figure 8-4 on page 26.

Note: After setting RPR(RAM Page Select Register), be

sure to execute SETG instruction. When executing CLRG

instruction, be selected PAGE0 regardless of RPR.

R/W R/W R/W

7

-

6

-

5

4

-

3

-

2

1

0

ADDRESS: 0E1

INITIAL VALUE: -----000

H

-

RPR2 RPR1 RPR0

RPR

B

000 : PAGE0

001 : PAGE1

010 : PAGE2

011 : PAGE3

100 : PAGE4

101 : PAGE5

110 : PAGE6

RAM page select

Figure 8-9 RPR(RAM Page Select Register)

30

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Initial Value

Address

Register Name

R0 port data register

Symbol

R/W

Addressing mode

7

6 5 4 3 2 1 0

byte, bit¹

00C0

R0

R/W 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

byte²

byte, bit

byte

00C1

00C2

00C3

00C4

00C5

00C6

00C7

00C8

00C9

00CA

00CB

00CC

00CD

00CE

00CF

00D0

R0 port I/O direction register

R1 port data register

R0IO

R1

W

R1 port I/O direction register

R2 port data register

R1IO

R2

W

R/W

W

0 0 0 0 0 0 0 0

-

- 0 0 0 0

byte, bit

byte

R2 port I/O direction register

R3 port data register

R2IO

R3

R/W 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

byte, bit

byte

R3 port I/O direction register

R4 port data register

R3IO

R4

W

byte, bit

byte

R4 port I/O direction register

R5 port data register

R4IO

R5

W

R/W

W

0 0 0 0 0 0 0 0

-

- 0 0 0 0 0

byte, bit

byte

R5 port I/O direction register

R6 port data register

R5IO

R6

R/W 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

byte, bit

byte

R6 port I/O direction register

R7 port data register

R6IO

R7

W

byte, bit

byte

R7 port I/O direction register

Timer 0 mode control register

Timer 0 register

R7IO

TM0

T0

W

R/W

R

0 0 0 0 0 0 0 0

- 0 0 0 0 0 0

-

byte, bit

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

00D1

Timer 0 data register

TDR0

CDR0

TM1

TDR1

T1PPR

T1

W

byte

Timer 0 capture data register

Timer 1 mode control register

Timer 1 data register

R

00D2

00D3

R/W 0 0 0 0 0 0 0 0

byte, bit

byte

W

R

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

Timer 1 PWM period register

Timer 1 register

00D4

Timer 1 PWM duty register

Timer 1 capture data register

Timer 1 PWM high register

Timer 2 mode control register

Timer 2 register

T1PDR

CDR1

T1PWHR

TM2

T2

R/W 0 0 0 0 0 0 0 0

byte

R

W

0 0 0 0 0 0 0 0

00D5

00D6

-

- 0 0 0 0

byte

R/W

R

- 0 0 0 0 0 0

byte, bit

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

00D7

00D8

Timer 2 data register

TDR2

CDR2

TM3

W

byte

Timer 2 capture data register

Timer 3 mode control register

R

R/W 0 0 0 0 0 0 0 0

byte, bit

Table 8-1 Control Registers

MAR. 2005 Ver 0.2

31

MC80F0424/0432/0448

Preliminary

Initial Value

Address

Register Name

Symbol

R/W

Addressing mode

7

6 5 4 3 2 1 0

Timer 3 data register

TDR3

T3PPR

T3

W

R

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

00D9

byte

Timer 3 PWM period register

Timer 3 register

00DA

Timer 3 PWM duty register

Timer 3 capture data register

Timer 3 PWM high register

Timer 4 mode control register

Timer 4 low register

T3PDR

CDR3

R/W 0 0 0 0 0 0 0 0

byte

R

W

0 0 0 0 0 0 0 0

00DB

00DC

T3PWHR

TM4

-

- 0 0 0 0

byte

R/W

R

- 0 0 0 0 0 0

byte, bit

T4L

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

00DD

00DE

Timer 4 low data register

Timer 4 capture low data register

Timer 4 high register

TDR4L

CDR4L

T4H

W

byte

R

Timer 4 high data register

Timer 4 capture high data register

Interrupt flag register

TDR4H

CDR4H

IFR

W

R

00DF

00E0

00E1

00E2

00E3

00E4

00E5

00E6

00E7

00E8

R/W

W

-

- 0 0 0 0 0 0

1 1 1 1 1 1 1 1

- 0 0 0

byte, bit

byte

Buzzer driver register

BUZR

RAM page selection register

SIO mode control register

SIO data shift register

RPR

R/W

-

byte, bit

SIOM

R/W 0 0 0 0 0 0 0 1

R/W Undefined

SIOR

Reserved

ASIMR

ASISR

UART0 mode register

UART0 status register

R/W 0 0 0 0 - 0 0 -

- 0 0 0

R/W - 0 0 1 0 0 0 0

byte, bit

byte

R

- - - -

UART0 Baud rate generator control register

UART0 Receive buffer register

UART0 Transmit shift register

Interrupt enable register high

BRGCR

RXR

byte, bit

R

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

00E9

byte

TXR

W

00EA

00EB

00EC

00ED

00EE

00EF

00F0

00F1

IENH

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 1

byte, bit

byte

Interrupt enable register low

IENL

Interrupt request register high

Interrupt request register low

IRQH

IRQL

Interrupt edge selection register

A/D converter mode control register

A/D converter result high register

A/D converter result low register

IEDS

ADCM

ADCRH

ADCRL

R

0 1 1 Undefined

Undefined

byte

Table 8-1 Control Registers

32

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Initial Value

Address

Register Name

Symbol

R/W

Addressing mode

7

6 5 4 3 2 1 0

Basic interval timer register

Clock control register

BITR

CKCTLR

SCMR

WDTR

WDTDR

SSCR

R

W

Undefined

0 - 0 1 0 1 1 1

- 0 0 0

00F2

00F3

00F4

byte

byte, bit

byte

System clock mode register

Watch dog timer register

Watch dog timer data register

Stop & sleep mode control register

Watch timer mode register

PFD control register

R/W

W

- - - -

0 1 1 1 1 1 1 1

Undefined

R

00F5

00F6

00F7

00F8

00F9

00FA

00FB

00FC

00FD

00FE

00FF

0EE6

0EE7

0EE8

W

0 0 0 0 0 0 0 0

byte

byte, bit

byte

WTMR

PFDR

R/W 0 - - 0 0 0 0 0

R/W

W

-

- 0 0 0

0 0 0 0 0 0 0 0

- 0 0 0 0

Port selection register 0

Port selection register 1

PSR0

PSR1

W

-

byte

Reserved

PU0

Pull-up selection register 0

Pull-up selection register 1

Pull-up selection register 4

Pull-up selection register 7

UART1 mode register

W

0 0 0 0 0 0 0 0

byte

PU1

PU4

byte

PU7

byte

ASIMR1

ASISR1

R/W 0 0 0 0 - 0 0 -

- 0 0 0

byte, bit

byte

UART1 status register

R

- - - -

UART1 Baud rate generator control register

UART1 Receive buffer register

BRGCR1 R/W - 0 0 1 0 0 0 0

byte, bit

RXR1

TXR1

R

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

0EE9

byte

UART1 Transmit shift register

W

Table 8-1 Control Registers

1.

2.

The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction.

Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated.

The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation

instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,

content of other seven bits are may varied to unwanted value.

*The mark of ‘-’ means this bit location is reserved.

MAR. 2005 Ver 0.2

33

MC80F0424/0432/0448

Preliminary

Bit 7

Address

C0H

C1H

C2H

C3H

C4H

C5H

C6H

C7H

C8H

C9H

CAH

CBH

CCH

CDH

CEH

CFH

D0H

Name

R0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

R0 Port Data Register

R0 Port Direction Register

R1 Port Data Register

R1 Port Direction Register

R0IO

R1

R1IO

R2

-

R2 Port Data Register

R2IO

R3

R2 Port Direction Register

R3 Port Data Register

R3 Port Direction Register

R4 Port Data Register

R4 Port Direction Register

R3IO

R4

R4IO

R5

-

R5 Port Data Register

R5IO

R6

R5 Port Direction Register

R6 Port Data Register

R6 Port Direction Register

R7 Port Data Register

R7 Port Direction Register

R6IO

R7

R7IO

TM0

-

CAP0

T0CK2

T0CK1

T0CK0

T0CN

T1CN

T0ST

T1ST

T0/TDR0/

CDR0

D1H

D2H

D3H

Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register

POL 16BIT PWM1E CAP1 T1CK1 T1CK0

Timer1 Data Register / Timer1 PWM Period Register

TM1

TDR1/

T1PPR

T1/CDR1/

T1PDR

D4H

Timer1 Register / Timer1 Capture Data Register / Timer1 PWM Duty Register

-

D5H

D6H

PWM1HR

TM2

-

Timer1 PWM High Register

-

CAP2

T2CK2

T2CK1

T2CK0

T2CN

T3CN

T2ST

T3ST

T2/TDR2/

CDR2

D7H

D8H

D9H

Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register

POL 16BIT PWM3E CAP3 T3CK1 T3CK0

Timer3 Data Register / Timer3 PWM Period Register

TM3

TDR3/

T3PPR

T3/CDR3/

T3PDR

DAH

Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register

-

DBH

DCH

PWM3HR

TM4

-

Timer3 PWM High Register

T4CK1 T4CK0

-

CAP4

T4CK2

T4CN

T4ST

T4L/

DDH

TDR4L/

CDR4L

Timer4 Register Low / Timer4 Data Register Low / Timer4 Capture Data Register Low

Table 8-2 Control Register Function Description

34

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Bit 7

Timer4 Register High / Timer4 Data Register High / Timer4 Capture Data Register High

Address

Name

T4H/

TDR4H/

CDR4H

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DEH

DFH

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

IFR

-

BUCK1

-

IFRX0

BUR5

-

IFTX0

BUR4

-

IFRX1

BUR3

-

IFTX1

BUR2

RPR2

SCK0

IFWT

BUR1

RPR1

SIOST

IFWDT

BUR0

RPR0

SIOSF

BUZR

RPR

SIOM

SIOR

BUCK0

-

POL

IOSW

SM1

SM0

SCK1

SIO Data Shift Register

Reserved

ASIMR

ASISR

BRGCR

RXR

TXE

RXE

-

PS1

-

PS0

-

SL

PE

ISRM

FE

-

OVE

MLD0

TPS2

TPS1

TPS0

MLD3

MLD2

MLD1

UART0 Receive Buffer Register

UART0 Transmit Shift Register

E9H

TXR

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

IENH

INT0E

T1E

INT1E

T2E

INT2E

T3E

INT3E

T4E

UART0E

ADCE

UART1E

WDTE

SIOE

WTE

T0E

BITE

T0IF

IENL

IRQH

IRQL

INT0IF

T1IF

INT1IF

T2IF

INT2IF

T3IF

INT3IF

T4IF

IED2L

ADS2

-

UART0IF UART1IF

SIOIF

WTIF

IED0H

ADST

ADCIF

IED1H

ADS1

-

WDTIF

IED1L

ADS0

-

BITIF

IED0L

ADSF

IEDS

IED3H

ADEN

PSSEL1

IED3L

ADCK

PSSEL0

IED2H

ADS3

ADC8

ADCM

ADCRH

ADCRL

ADC Result Reg. High

ADC Result Register Low

Basic Interval Timer Data Register

BITR¹

F2H

CKCTLR¹

SCMR

WDTR

WDTDR

SSCR

ADRST

-

RCWDT

-

WDTON

-

BTCL

-

BTS2

MCC

BTS1

CS1

BTS0

CS0

F3H

F4H

WDTCL 7-bit Watchdog Timer Register

Watchdog Timer Data Register (Counter Register)

Stop & Sleep Mode Control Register

F5H

F6H

F7H

F8H

F9H

FAH

FBH

FCH

FDH

FEH

WTMR

PFDR

WTEN

-

WTIN2

WTIN1

-

WTIN0

PFDEN

INT2E

BUZO

WTCK1

PFDM

INT1E

T2O

WTCK0

PFDS

INT0E

T0O

-

EC1E

-

EC0E

-

PSR0

PWM3O

-

PWM1O

-

INT3E

XTEN

PSR1

Reserved

PU0

PU1

PU4

R0 Pull-up Selection Register

R1 Pull-up Selection Register

R4 Pull-up Selection Register

Table 8-2 Control Register Function Description

MAR. 2005 Ver 0.2

35

MC80F0424/0432/0448

Preliminary

Bit 7

R4 Pull-up Selection Register

Address

FEH

Name

PU4

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EE6H

EE7H

EE8H

ASIMR1

ASISR1

BRGCR1

RXR1

TXE

RXE

-

PS1

-

PS0

-

SL

PE

ISRM

FE

-

OVE

MLD0

TPS2

TPS1

TPS0

MLD3

MLD2

MLD1

UART1 Receive Buffer Register

UART1 Transmit Shift Register

EE9H

TXR1

Table 8-2 Control Register Function Description

1. The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.

Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be

accessed by register operation instruction such as "LDM dp,#imm".

8.4 Addressing Mode

The MC800 series MCU uses six addressing modes;

• Register addressing

When G-flag is 1, then RAM address is defined by 16-bit address

which is composed of 8-bit RAM paging register (RPR) and 8-bit

immediate data.

• Immediate addressing

Example: G=1

• Direct page addressing

• Absolute addressing

E45535 LDM

35H,#55H

• Indexed addressing

• Register-indirect addressing

0135H

data

data ← 55H

~

8.4.1 Register Addressing

➊

0F100H

0F101H

0F102H

E4

55

35

Register addressing accesses the A, X, Y, C and PSW.

8.4.2 Immediate Addressing → #imm

In this mode, second byte (operand) is accessed as a data imme-

diately.

Example:

8.4.3 Direct Page Addressing → dp

In this mode, a address is specified within direct page.

Example; G=0

0435

ADC

#35H

MEMORY

04

35

A+35H+C → A

36

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

C535

LDA

35H

;A ←RAM[35H]

983501 INC

!0135H

;A ←ROM[135H]

35H

data

135H

data

➊

~

data → A

~

data+1 → data

➊

0E550H

0E551H

C5

35

0F100H

0F101H

0F102H

98

35

01

➊

address: 0135

8.4.5 Indexed Addressing

8.4.4 Absolute Addressing → !abs

Absolute addressing sets corresponding memory data to Data, i.e.

second byte (Operand I) of command becomes lower level ad-

dress and third byte (Operand II) becomes upper level address.

With 3 bytes command, it is possible to access to whole memory

area.

X indexed direct page (no offset) → {X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15_H, G=1

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR,

SBC, STA, STX, STY

D4

LDA

{X}

;ACC←RAM[X].

Example;

0735F0 ADC

!0F035H

;A ←ROM[0F035H]

115H

data

➊

data → A

~

0F035H

data

~

➊

~

A+data+C → A

D4

0E550H

➊

0F100H

0F101H

0F102H

07

35

F0

address: 0F035

X indexed direct page, auto increment→ {X}+

In this mode, a address is specified within direct page by the X

register and the content of X is increased by 1.

The operation within data memory (RAM)

ASL, BIT, DEC, INC, LSR, ROL, ROR

LDA, STA

Example; Addressing accesses the address 0135_Hregardless of

G-flag.

Example; G=0, X=35_H

DB

LDA

{X}+

MAR. 2005 Ver 0.2

37

MC80F0424/0432/0448

Preliminary

D500FA LDA

!0FA00H+Y

35H

data

➊

0F100H

0F101H

0F102H

D5

00

FA

data → A

36H → X

➊

~

➊

0FA00H+55H=0FA55H

DB

~

➊

0FA55H

data

data → A

➊

X indexed direct page (8 bit offset) → dp+X

8.4.6 Indirect Addressing

Direct page indirect → [dp]

This address value is the second byte (Operand) of command plus

the data of X-register. And it assigns the memory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY,

XMA, ASL, DEC, INC, LSR, ROL, ROR

Assigns data address to use for accomplishing command which

sets memory data (or pair memory) by Operand.

Also index can be used with Index register X,Y.

Example; G=0, X=0F5_H

C645

LDA

45H+X

JMP, CALL

Example; G=0

3F35

JMP

[35H]

3AH

data

➊

35H

36H

0A

E3

~

data → A

➊

~

0E550H

0E551H

C6

45

➊

~

45H+0F5H=13AH

➊

0E30AH

0FA00H

address 0E30AH

~

3F

35

Y indexed direct page (8 bit offset) → dp+Y

This address value is the second byte (Operand) of command plus

the data of Y-register, which assigns Memory in Direct page.

This is same with above (2). Use Y register instead of X.

X indexed indirect → [dp+X]

Processes memory data as Data, assigned by 16-bit pair memory

which is determined by pair data [dp+X+1][dp+X] Operand plus

X-register data in Direct page.

Y indexed absolute → !abs+Y

Sets the value of 16-bit absolute address plus Y-register data as

Memory.This addressing mode can specify memory in whole ar-

ea.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10_H

Example; Y=55_H

38

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

1625

ADC

[25H+X]

Absolute indirect → [!abs]

The program jumps to address specified by 16-bit absolute ad-

dress.

35H

05

JMP

36H

E0

Example; G=0

➊ 0E005H

~

1F25E0 JMP

[!0C025H]

➊

25 + X(10) = 35H

0E005H

data

~

PROGRAM MEMORY

0FA00H

16

25

0E025H

0E026H

25

➊ A + data + C → A

E7

➊

~

jump to

address 0E30AH

Y indexed indirect → [dp]+Y

0E725H

0FA00H

Processes memory data as Data, assigned by the data [dp+1][dp]

of 16-bit pair memory paired by Operand in Direct page plus Y-

register data.

~

1F

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, Y=10_H

25

E0

1725

ADC

[25H]+Y

25H

26H

05

E0

➊

~

➊

0E005H + Y(10)

= 0E015H

0E015H

0FA00H

data

~

17

25

➊

A + data + C → A

MAR. 2005 Ver 0.2

39

MC80F0424/0432/0448

9. I/O PORTS

Preliminary

The MC80F0424/0432/0448 has eight ports (R0, R1, R2, R3, R4,

R5, R6 and R7). These ports pins may be multiplexed with an al-

ternate function for the peripheral features on the device. R3 port

can drive maximum 20mA of high current in output low state, so

it can directly drive LED device.

ADDRESS: 0C0

RESET VALUE: 00

H

R0 Data Register

H

R07 R06 R05 R04 R03 R02 R01 R00

Input / Output data

R0

All pins have data direction registers which can define these ports

as output or input. A “1” in the port direction register configure

the corresponding port pin as output. Conversely, write “0” to the

corresponding bit to specify it as input pin. For example, to use

the even numbered bit of R0 as output ports and the odd num-

bered bits as input ports, write “55_H” to address 0C1_H(R0 port

direction register) during initial setting as shown in Figure 9-1.

ADDRESS: 0C1

RESET VALUE: 00

H

R0 Direction Register

R0IO

H

All the port direction registers in the MC80F0424/0432/0448

have 0 written to them by reset function. On the other hand, its in-

itial status is input.

Port Direction

0: Input

1: Output

R0 Pull-up

Selection Register

ADDRESS: 0FC

RESET VALUE: 00

H

WRITE “55 ” TO PORT R0 DIRECTION REGISTER

H

PU0

0C0

0C1

0C2

0C3

BIT

R0 data

0 1 0 1 0 1 0 1

7 6 5 4 3 2 1 0

H

R0 direction

Pull-up Resister Selection

R1 data

H

0: Disable

1: Enable

R1 direction

I

O I O I O I O PORT

7 6 5 4 3 2 1 0

I: INPUT PORT

O: OUTPUT PORT

R1 and R1IO register: R1 is an 8-bit CMOS bidirectional I/O

port (address 0C2_H). Each I/O pin can independently used as an

input or an output through the R1IO register (address 0C3_H). The

on-chip pull-up resistor can be connected to them in 1-bit units

with a pull-up selection register 1 (PU1).

Figure 9-1 Example of port I/O assignment

R0 and R0IO register: R0 is an 8-bit CMOS bidirectional I/O

port (address 0C0_H). Each I/O pin can independently used as an

input or an output through the R0IO register (address 0C1_H). The

on-chip pull-up resistor can be connected to them in 1-bit units

with a pull-up selection register 0 (PU0).

In addition, Port R1 is multiplexed with various special features.

The control register PSR0 (address 0F8_H) and PSR1 (address

0F9_H) controls the selection of alternate function. After reset, this

value is “0”, port may be used as normal I/O port.

To use alternate function such as external interrupt, event counter

input or timer clock output, write “1” in the corresponding bit of

PSR0 or PSR1. Regardless of the direction register R1IO, PSR0

or PSR1 is selected to use as alternate functions, port pin can be

used as a corresponding alternate features.

Port Pin

Alternate Function

R10

R11

R12

R13

R14

R15

R16

R17

INT0 (External Interrupt 0)

INT1 (External Interrupt 1)

INT2 (External Interrupt 2)

BUZO (Square-wave output for buzzer)

T0O (Timer 0 Clock-out)

EC0 (Event counter input to Counter 0)

-

40

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

R2 and R2IO register: R2 is an 4-bit CMOS bidirectional I/O

port (address 0C4_H). Each I/O pin can independently used as an

input or an output through the R2IO register (address 0C5_H).

ADDRESS: 0C2

RESET VALUE: 00

H

R1 Data Register

H

In addition, Port R2 is multiplexed with various special features.

The control register PSR1 (address 0F9_H) controls the selection

of alternate function. After reset, this value is “0”, port may be

used as normal I/O port.

R17 R16 R15 R14 R13 R12 R11 R10

Input / Output data

R1

To use alternate function such as sub clock input and sub clock

output, write “1” in the corresponding bit of PSR1.

ADDRESS: 0C3

H

R1 Direction Register

R1IO

RESET VALUE: 00

H

Port Pin

Alternate Function

-

R20

R21

R22

R23

Port Direction

0: Input

1: Output

SX_IN(sub clock input)

SX_OUT(sub clock output)

-

R1 Pull-up

Selection Register

ADDRESS: 0FD

RESET VALUE: 00

H

PU1

ADDRESS: 0C4

RESET VALUE: ----0000

H

R2 Data Register

B

Pull-up Resister Selection

-

R23 R22 R21 R20

R2

0: Disable

1: Enable

Input / Output data

ADDRESS: 0F8

H

RESET VALUE: 0000 0000

B

PWM3

EC1E EC0E

INT3E

INT1E INT0E

INT2E

PWM1

PSR0

ADDRESS: 0C5

RESET VALUE: ----0000

H

R2 Direction Register

B

-

R2IO

Port / INT Selection

0: R10, R11,R12, R50

1: INT0, INT1,INT2, INT3

Port Direction

0: Input

Port / EC Selection

0: R15, R51

1: Output

1: EC0, EC1

Port / PWM3(1) Selection

0: R54 (P53)

1: PWM3O/T3O port (PWM1O/T1O port)

R3 and R3IO register: R3 is an 8-bit CMOS bidirectional I/O

port (address 0C6_H). Each I/O pin can independently used as an

input or an output through the R3IO register (address 0C7_H).

ADDRESS: 0F9

RESET VALUE: ---- 0000

H

In addition, Port R3 is multiplexed with various special features.

After reset, this value is "0", port may be used as normal I/O port.

To use alternate function, write “1” in the corresponding bit of

ASIMR1 and BRGCR1 register.

B

-

BUZO

XTEN

T2O T0O

PSR1

Timer2/0 Output

0 : R52/R514 Port

1 : Timer2/0 Output

Port Pin

Alternate Function

R13/BUZO Selection

0: R13 port (Turn off buzzer)

1: BUZO port (Turn on buzzer)

R30

R31

R32

R33

R37

-

ACLK1 (UART1 clock input)

RxD1 (UART1 data input)

TxD1(UART1 data output)-

Sub Clock Selection

0: R21,R22 Port

1: SXin, SXout Port

-

MAR. 2005 Ver 0.2

41

MC80F0424/0432/0448

Preliminary

ADDRESS: 0C8

RESET VALUE: 00

ADDRESS: 0C6

RESET VALUE: 00

H

R4 Data Register

R3 Data Register

H

R47 R46 R45 R44 R43 R42 R41 R40

Input / Output data

R37 R36 R35 R34 R33 R32 R31 R30

Input / Output data

R4

R3

ADDRESS: 0C9

H

RESET VALUE: 00

ADDRESS: 0C7

RESET VALUE: 00

H

R4 Direction Register

R4IO

R3 Direction Register

R3IO

H

Port Direction

0: Input

1: Output

Port Direction

0: Input

1: Output

R4 Pull-up

Selection Register

ADDRESS: 0FE

RESET VALUE: 00

H

R4 and R4IO register: R4 is an 8-bit CMOS bidirectional I/O

port (address 0C8_H). Each I/O pin can independently used as an

input or an output through the R4IO register (address 0C9_H). The

on-chip pull-up resistor can be connected to them in 1-bit units

with a pull-up selection register 4 (PU4).

H

PU4

Pull-up Resister Selection

0: Disable

1: Enable

In addition, Port R4 is multiplexed with various special features.

After reset, this value is “0”, port may be used as normal I/O port.

To use alternate function, write “1” in the corresponding bit of

ASIMR and BRGCR register.

Port Pin

Alternate Function

Port Pin

Alternate Function

R50

R51

R52

R53

R54

INT3 (External Interrupt 3)

EC1 (Event counter input to Counter 2)

T2O (Timer 2 Clock-out)

PWM1O (PWM1 output) / T1O

PWM3O (PWM3 output) / T3O

R40

R41

R42

R43

R44

R45

R46

R47

-

SCK (SIO clock input/output)

SI (SIO data input)

SO (Serial1 data output)

ACLK (Asynchronous serial clock input)

RxD (Asynchronous serialdata input)

TxD (Asynchronous serial data output)

ADDRESS: 0CA

RESET VALUE: ---00000

H

R5 Data Register

B

-

R54 R53 R52 R51 R50

R5

R5 and R5IO register: R5 is an 5-bit CMOS bidirectional I/O

port (address 0CA_H). Each I/O pin can independently used as an

input or an output through the R5IO register (address 0CB_H).

Input / Output data

In addition, Port R5 is multiplexed with various special features.

The control register PSR0 (address 0F8_H) and PSR1 (address

0F9_H) controls the selection of alternate function. After reset, this

value is “0”, port may be used as normal I/O port.

ADDRESS: 0CB

RESET VALUE: ---00000

H

R5 Direction Register

B

-

R5IO

To use alternate function such as external interrupt, event counter

input, timer clock output or PWM output, write “1” in the corre-

sponding bit of PSR0 or PSR1. Regardless of the direction regis-

ter R5IO, PSR0 or PSR1 is selected to use as alternate functions,

port pin can be used as a corresponding alternate features.

Port Direction

0: Input

1: Output

42

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

R6 and R6IO register: R6 is an 8-bit CMOS bidirectional I/O

port (address 0CC_H). Each I/O pin can independently used as an

input or an output through the R6IO register (address 0CD_H).

Port Pin

Alternate Function

In addition, Port R6 is multiplexed with AD converter analog in-

put AN0~AN7.

R70

R71

R72

R73

R74

R75

R76

R77

AN8 (ADC input channel 8)

AN9 (ADC input channel 9)

AN10 (ADC input channel 10)

AN11 (ADC input channel 11)

AN12 (ADC input channel 12)

AN13 (ADC input channel 13)

AN14 (ADC input channel 14)

AN15 (ADC input channel 15)

Port Pin

Alternate Function

R60

R61

R62

R63

R64

R65

R66

R67

AN0 (ADC input channel 0)

AN1 (ADC input channel 1)

AN2 (ADC input channel 2)

AN3 (ADC input channel 3)

AN4 (ADC input channel 4)

AN5 (ADC input channel 5)

AN6 (ADC input channel 6)

AN7 (ADC input channel 7)

R7IO (address CF_H) controls the direction of the R7 pins, except

when they are being used as analog input channels. The user don’t

have to keep the pins configured as inputs when using them as an-

alog input channels, because the analog input mode is activated

by the setting of ADC enable bit of ADCM register and ADC

channel selection.

R6IO (address CD_H) controls the direction of the R6 pins, except

when they are being used as analog input channels. The user don’t

have to keep the pins configured as inputs when using them as an-

alog input channels, because the analog input mode is activated

by the setting of ADC enable bit of ADCM register and ADC

channel selection.

ADDRESS: 0CE

RESET VALUE: 00

H

R7 Data Register

H

ADDRESS: 0CC

RESET VALUE: 00

H

R6 Data Register

R77 R76 R75 R74 R73 R72 R71 R70

R7

H

R67 R66 R65 R64 R63 R62 R61 R60

Input / Output data

R6

Input / Output data

ADDRESS: 0CF

RESET VALUE: 00

H

R7 Direction Register

R7IO

H

ADDRESS: 0CD

RESET VALUE: 00

H

R6 Direction Register

R6IO

H

Port Direction

0: Input

1: Output

Port Direction

0: Input

1: Output

R7 Pull-up

Selection Register

ADDRESS: 0FF

RESET VALUE: 00

H

R7 and R7IO register: R7 is an 8-bit CMOS bidirectional I/O

port (address 0CE_H). Each I/O pin can independently used as an

input or an output through the R7IO register (address 0CF_H). The

on-chip pull-up resistor can be connected to them in 1-bit units

with a R7 pull-up selection register (PU7).

PU7

Pull-up Resister Selection

0: Disable

1: Enable

In addition, Port R7 is multiplexed with AD converter analog in-

put channel AN8~AN15.

MAR. 2005 Ver 0.2

43

MC80F0424/0432/0448

Preliminary

10. CLOCK GENERATOR

As shown in Figure 10-1, the clock generator produces the basic

clock pulses which provide the system clock to be supplied to the

CPU and the peripheral hardware. It contains two oscillators

which are main-frequency clock oscillator and a sub-frequency

clock oscillator. The system clock operation can be easily ob-

tained by attaching a crystal or a ceramic resonator between the

X_INand X_OUTpin and the SX_INand SX_OUTpin, respectively.

The system clock can also be obtained from the external oscilla-

tor. In this case, it is necessary to input a external clock signal to

the X_INpin and open the X_OUTpin. There are no requirements on

the duty cycle of the external clock signal, since the input to the

internal clocking circuitry is through a divide-by-two flip-flop,

but minimum and maximum high and low times specified on the

data sheet must be observed.

system clock control register (SCMR). The registers are shown in

Figure 10-2. In case of selecting sub clock, to oscillate or stop the

main clock is decided by MCC bit (SCMR.2).

On the initial reset, internal system clock is PS1 which is the fast-

est and other clock can be provided by bit0 and bit1 of SCMR.

The clock among the not-divided original clock and clocks divid-

ed by 1, 2, 4,..., up to 4096 can be provided to the peripheral

block, Peripheral clock is enabled or disabled by STOP instruc-

tion. The peripheral clock is controlled by clock control register

(CKCTLR). See "11. BASIC INTERVAL TIMER" on page 46

for details.

The subclock oscillation connected to SXIN and SXOUT pin is

enabled by the set of corresponding XTEN bit of PSR1 register

(See Figure 10-3).

The internal system clock can be selected by bit0 and bit1 of the

STOP

MCC

SLEEP

Main OSC

Stop

CS1 CS0

MUX

X_IN

OSC

Circuit

Clock Pulse

Internal

f_EX

Generator

X_OUT

system clock

(÷2)

SX_IN

SX_OUT

Sub OSC

Circuit

Sub OSC

Run

PRESCALER

XTEN

(PSR1 reg.)

PS11 PS12

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

PS10

÷1

÷2

÷4

÷8

÷16

÷32

÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096

*MCC, CS1, CS0 are described

in next figure.

Peripheral clock

f_EX(Hz)

PS0

4M

PS1

2M

PS2

PS3

PS4

PS5

PS6

PS7

PS8

PS9

7.183K 3.906K

128u 256u

PS10

PS11

1.953K

512u

PS12

976

Frequency

period

1M

1u

500K

2u

250K

4u

125K

8u

62.5K

16u

31.25K 15.63K

4M

1.024m

250n

500n

32u

64u

Figure 10-1 Block Diagram of Clock Generator

44

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

SCMR (System Clock Mode Register)

R/W R/W R/W

MCC CS1 CS0

ADDRESS: 0F3

INITIAL VALUE: ----_-000B

H

-

CS[1:0] (System clock control)

00: main clock on

01: main clock on

10: sub clock on

11: Setting prohibited

MCC (Main System Clock Oscillation Control)

0: Oscillation possible

1: Oscillation stop

Note 1. When the CPU is operating on the subsystem clock, MCC should be used to stop the main system oscillation.

A STOP instruction should not be used.

Figure 10-2 System Clock Mode Registers

ADDRESS: 0F9

H

RESET VALUE: ----_0000

B

W

-

XTEN BUZO T2O T0O

PSR1

R14/T0O Selection

0: R14 port (Timer0 output disable)

1: T0O port (Timer0 output enable)

R52/T2O Selection

0: R52 port (Timer2 output disable)

1: T2O port (Timer2 output enable)

R13/BUZO Selection

0: R13 port (Turn off buzzer)

1: BUZO port (Turn on buzzer)

R21,R22/Sub Clock Selection

0: Sub clock (SX , SX

) oscillation stop

IN

OUT

1: Sub clock (SX , SX

) oscillation enable

IN

OUT

Figure 10-3 Port Selection Register PSR1

MAR. 2005 Ver 0.2

45

MC80F0424/0432/0448

Preliminary

11. BASIC INTERVAL TIMER

The MC80F0424/0432/0448 has one 8-bit Basic Interval Timer

that is free-run and can not stop. Block diagram is shown in Fig-

ure 11-1. In addition, the Basic Interval Timer generates the time

base for watchdog timer counting. It also provides a Basic inter-

val timer interrupt (BITIF).

The 8-bit Basic interval timer register (BITR) is increased every

internal count pulse which is divided by prescaler. Since prescal-

er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024

of the oscillator frequency. As the count overflow from FFH to

00H, this overflow causes the interrupt to be generated. The Basic

Interval Timer is controlled by the clock control register

(CKCTLR) shown in Figure 10-2.

after one machine cycle by hardware.

If the STOP instruction executed after writing "1" to bit RCWDT

of CKCTLR, it goes into the internal RC oscillated watchdog tim-

er mode. In this mode, all of the block is halted except the internal

RC oscillator, Basic Interval Timer and RC Watchdog Timer.

More detail informations are explained in Power Saving Func-

tion. The bit WDTON decides Watchdog Timer or the normal 7-

bit timer.

Source clock can be selected by lower 3 bits of CKCTLR.

BITR and CKCTLR are located at same address, and address

0F2_His read as a BITR, and written to CKCTLR.

When write "1" to bit BTCL of CKCTLR, BITR register is

cleared to "0" and restart to count-up. The bit BTCL becomes "0"

Internal RC OSC

RCWDT

÷8

8-bit up-counter

Basic Interval

source

clock

÷16

1

0

Timer Interrupt

overflow

÷32

BITIF

BITR

÷64

X

IN

MUX

÷128

÷256

÷512

÷1024

[0F2 ]

H

clear

Watchdog timer

(WDTCK)

0

1

3

Select Input clock

BTS[2:0]

RCWDT

BTCL

[0F2 ]

H

CKCTLR

Basic Interval Timer

clock control register

Read

RCWDT

Internal bus line

Figure 11-1 Block Diagram of Basic Interval Timer

Interrupt (overflow) Period (ms)

@ f_XIN= 8MHz

CKCTLR

[2:0]

Source clock

_XIN÷8

f

000

001

010

011

100

101

110

111

0.256

0.512

1.024

2.048

4.096

8.192

16.384

32.768

_XIN÷16

_XIN÷32

_XIN÷64

_XIN÷128

_XIN÷256

_XIN÷512

_XIN÷1024

Table 11-1 Basic Interval Timer Interrupt Period

46

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7

ADRST

6

-

5

RCWDT

4

3

2

1

0

ADDRESS: 0F2

INITIAL VALUE: 0-010111

H

_WDTONBTCL

BTCL BTS2 BTS1 BTS0

CKCTLR

B

Basic Interval Timer source clock select

000: f

001: f

010: f

011: f

100: f

101: f

110: f

111: f

÷ 8

XIN

÷ 16

÷ 32

÷ 64

÷ 128

÷ 256

÷ 512

÷ 1024

Caution:

Both register are in same address,

when write, to be a CKCTLR,

when read, to be a BITR.

Clear bit

0: Normal operation (free-run)

1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically

after one machine cycle, and starts counting.

Watchdog timer Enable bit

0: Operate as 7-bit Timer

1: Enable Watchdog Timer operation

See the section “Watchdog Timer”.

RC Watchdog Selection bit

0: Disable Internal RC Watchdog Timer

1: Enable Internal RC Watchdog Timer

Address Fail Reset Selection

0: Enable Address Fail Reset

1: Disable Address Fail Reset

7

6

5

4

3

2

1

0

ADDRESS: 0F2

INITIAL VALUE: Undefined

H

BTCL

BITR

8-BIT FREE-RUN BINARY COUNTER

Figure 11-2 BITR: Basic Interval Timer Mode Register

Example 1:

Interrupt request flag is generated every 8.192ms at 4MHz.

:

LDM

CKCTLR,#1BH

SET1 BITE

EI

:

Example 2:

Interrupt request flag is generated every 8.192ms at 8MHz.

:

LDM

CKCTLR,#1CH

SET1 BITE

EI

:

MAR. 2005 Ver 0.2

47

MC80F0424/0432/0448

Preliminary

12. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction such as

endless looping caused by noise or the like, and resumes the CPU

to the normal state. The watchdog timer signal for detecting mal-

function can be selected either a reset CPU or a interrupt request.

The RC oscillated watchdog timer is activated by setting the bit

RCWDT as shown below.

LDM

STOP

NOP

:

CKCTLR,#3FH; enable the RC-OSC WDT

WDTR,#0FFH ; set the WDT period

SSCR, #5AH ;ready for STOP mode

; enter the STOP mode

When the watchdog timer is not being used for malfunction de-

tection, it can be used as a timer to generate an interrupt at fixed

intervals.

The watchdog timer has two types of clock source. The first type

is an on-chip RC oscillator which does not require any external

components. This RC oscillator is separated from the external os-

cillator of the X_INpin. It means that the watchdog timer will run,

even if the clock on the X_INpin of the device has been stopped,

for example, by entering the STOP mode. The other type is a

prescaler system clock.

; RC-OSC WDT running

The RC-WDT oscillation period is vary with temperature, V_DD

and process variations from part to part (approximately,

33~100uS). The following equation shows the RCWDT oscillat-

ed watchdog timer time-out.

The watchdog timer consists of 7-bit binary counter and the

watchdog timer data register. When the value of 7-bit binary

counter is equal to the lower 7 bits of WDTR, the interrupt re-

quest flag is generated. This can be used as Watchdog timer inter-

rupt or reset the CPU in accordance with the bit WDTON.

T_RCWDT=CLK_RCWDT×2⁸×WDTR + (CLK_RCWDT×2⁸⁾/2

where, CLK_RCWDT= 33~100uS

In addition, this watchdog timer can be used as a simple 7-bit tim-

er by interrupt WDTIF. The interval of watchdog timer interrupt

is decided by Basic Interval Timer. Interval equation is as below.

Note: Because the watchdog timer counter is enabled af-

ter clearing Basic Interval Timer, after the bit WDTON set to

"1", maximum error of timer is depend on prescaler ratio of

Basic Interval Timer. The 7-bit binary counter is cleared by

setting WDTCL(bit7 of WDTR) and the WDTCL is cleared

automatically after 1 machine cycle.

T

_WDT= (WDTR+1) × Interval of BIT

clear

Watchdog

Counter (7-bit)

clear

BASIC INTERVAL TIMER

OVERFLOW

Count

source

“0”

to reset CPU

“1”

comparator

enable

WDTON in CKCTLR [0F2 ]

H

7-bit compare data

WDTCL

WDTIF

7

Watchdog Timer interrupt

Watchdog Timer

Register

WDTR

[0F4 ]

H

Internal bus line

Figure 12-1 Block Diagram of Watchdog Timer

48

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

counters unless the binary counter is cleared. At this time, when

WDTON=1, a reset is generated, which drives the RESET pin to

low to reset the internal hardware. When WDTON=0, a watchdog

timer interrupt (WDTIF) is generated. The WDTON bit is in reg-

ister CLKCTLR.

Watchdog Timer Control

Figure 12-2 shows the watchdog timer control register. The

watchdog timer is automatically disabled after reset.

The CPU malfunction is detected during setting of the detection

time, selecting of output, and clearing of the binary counter.

Clearing the binary counter is repeated within the detection time.

The watchdog timer temporarily stops counting in the STOP

mode, and when the STOP mode is released, it automatically re-

starts (continues counting).

If the malfunction occurs for any cause, the watchdog timer out-

put will become active at the rising overflow from the binary

W

7

WDTCL

W

6

W

5

W

4

W

3

W

2

W

1

W

0

ADDRESS: 0F4

INITIAL VALUE: 0111_1111

H

WDTR

B

7-bit compare data

Clear count flag

0: Free-run count

1: When the WDTCL is set to “1”, binary counter

is cleared to “0”. And the WDTCL becomes “0” automatically

after one machine cycle. Counter count up again.

Figure 12-2 WDTR: Watchdog Timer Control Register

Example: Sets the watchdog timer detection time to 1 sec. at 4.194304MHz

LDM

CKCTLR,#3FH

WDTR,#08FH

;Select 1/1024 clock source, WDTON ← 1, Clear Counter

;Clear counter

LDM

:

WDTR,#08FH

:

Within WDT

detection time

:

LDM

:

;Clear counter

:

Within WDT

detection time

:

LDM

Enable and Disable Watchdog

Watchdog Timer Interrupt

Watchdog timer is enabled by setting WDTON (bit 4 in

CKCTLR) to “1”. WDTON is initialized to “0” during reset and

it should be set to “1” to operate after reset is released.

The watchdog timer can be also used as a simple 7-bit timer by

clearing bit4 of CKCTLR to “0”. The interval of watchdog timer

interrupt is decided by Basic Interval Timer. Interval equation is

shown as below.

Example: Enables watchdog timer for Reset

T_WDT= (WDTR+1) × Interval of BIT

:

LDM

:

CKCTLR,#xxx1_xxxxB;WDTON ← 1

:

The stack pointer (SP) should be initialized before using the

watchdog timer output as an interrupt source.

The watchdog timer is disabled by clearing bit 4 (WDTON) of

CKCTLR. The watchdog timer is halted in STOP mode and re-

starts automatically after STOP mode is released.

Example: 7-bit timer interrupt set up.

LDM

CKCTLR,#xxx0_xxxxB;WDTON ←0

WDTR,#8FH ;WDTCL ←1

:

MAR. 2005 Ver 0.2

49

MC80F0424/0432/0448

Preliminary

Source clock

BIT overflow

3

0

2

0

1

2

1

Binary-counter

Counter

Clear

Counter

Clear

3

n

WDTR

Match

Detect

WDTIF interrupt

WDTR ← “1000_0011_B”

WDT reset

reset

Figure 12-3 Watchdog timer Timing

If the watchdog timer output becomes active, a reset is generated,

which drives the RESET pin low to reset the internal hardware.

reset is generated in sub clock mode.

The IFWDT bit of IFR register is set when watchdog timer inter-

rupt is generated. (Refer to Figure 12-4)

The main clock oscillator also turns on when a watchdog timer

R/W R_-/W

R/W R/W

-

ADDRESS: 0DF

INITIAL VALUE: --00_0000

H

-

IFRX0

IFTX0

IFRX1

IFTX1

IFWT

IFWDT

IFR

B

LSB

MSB

NOTE1

WDT interrupt occurred flag

NOTE1

WT interrupt occurred flag

NOTE2

UART1 Tx interrupt occurred flag

UART1 Rx interrupt occurred flag

NOTE2

NOTE3

UART0 Tx interrupt occurred flag

UART0 Rx interrupt occurred flag

NOTE3

NOTE1 :

In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR

in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and

Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after

reading this register.

NOTE2 :

NOTE3 :

In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt

service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared

with interrupt vector address. These flag bits must be cleared by software after reading this register.

In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt

service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared

with interrupt vector address. These flag bits must be cleared by software after reading this register.

Figure 12-4 IFR : Interrupt Flag Register

50

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

13. WATCH TIMER

The watch timer generates interrupt for watch operation. The

watch timer consists of the clock selector, 15-bit binary counter,

interval selector and watch timer mode register. It is a multi-pur-

pose timer. It is generally used for watch design.

into stop mode, the main-clock is stopped and then watch timer is

also stopped. If the sub clock’s oscillation is enabled by XTEN

bit(PSR1 register), the watch timer by sub clock continues to op-

erate even when the CPU is in the STOP mode. The watch timer

counter can output with period of max 1 seconds at sub-clock.

The bit 2, 3, 4 of WTMR select the interrupt interval divide ratio

selection of watch timer among 16, 64, 256, 1024, 4096, 8192,

16384 or 32768.

The bit 0,1 of WTMR select the clock source of watch timer

among sub-clock(32.768kHz), f_XIN÷2, f_XIN÷128 and main-

clock(f_XIN). The f_XINof main-clock is used usually for watch

timer test, so generally it is not used for the clock source of watch

timer. The f_XIN÷128 of main-clock is used when the single clock

system is organized. In f_XIN÷128 clock source, if the CPU enters

The IFWT bit of IFR register is set when watch timer interrupt is

generated. (Refer to Figure 12-4)

WTMR (Watch Timer Mode Register)

W

7

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Bit :

6

-

5

-

ADDRESS: 0F6

INITIAL VALUE:0--00000

H

WTEN

WTIN2

WTIN1 WTIN0 WTCK1 WTCK0

B

Watch Timer Clock Source selection

WTEN (Watch Timer Enable)

0: Watch Timer disable

1: Watch Timer Enable

00: f

01: f

10: f

SUB

XIN

÷ 128

÷ 2

11: f

XIN

Watch Timer Interrupt Interval selection

000: Clock Source ÷ 32768

001: Clock Source ÷ 16384

010: Clock Source ÷ 8192

011: Clock Source ÷ 4096

100: Clock Source ÷ 1024

101: Clock Source ÷ 256

110: Clock Source ÷ 64

111: Clock Source ÷ 16

Figure 13-1 Watch Timer Mode Register

WTIN[2:0]

WTCK[1:0]

÷32768

÷16384

÷8192

÷4096

f

SUB

_XIN÷128

Watch Timer interrupt

MUX

XIN

÷1024

÷256

÷64

_XIN÷2

Clock Source

Selector

WTEN

Clear

÷16

If WTEN=0

interval

selector

Figure 13-2 Watch Timer Block Diagram

MAR. 2005 Ver 0.2

51

MC80F0424/0432/0448

Preliminary

14. TIMER/EVENT COUNTER

The MC80F0424/0432/0448 has five Timer/Counter registers.

Each module can generate an interrupt to indicate that an event

has occurred (i.e. timer match).

counter function. When external interrupt edge input, the count

register is captured into capture data register CDRx.

It has seven operating modes: "8-bit timer/counter", "16-bit tim-

er/counter", "8-bit capture", "16-bit capture", "8-bit compare out-

put", "16-bit compare output" and "10-bit PWM" which are

selected by bit in Timer mode register TMx as shown in Table 14-

1, Table 14-2, Table 14-3, Figure 14-10, Figure 14-2 and Figure

14-3.

Timer 0 and Timer 1 are can be used either two 8-bit Timer/

Counter or one 16-bit Timer/Counter with combine them. Also

Timer 2 and Timer 3 are same. Timer 4 is 16-bit Timer/Counter.

In the “timer” function, the register is increased every internal

clock input. Thus, one can think of it as counting internal clock

input. Since a least clock consists of 2 and most clock consists of

2048 oscillator periods, the count rate is 1/2 to 1/2048 of the os-

cillator frequency.

In 8/16 Timer mode, pin R14/T0O and R52/T2O can output

Timer0 or Timer2 output by setting "1" respectively to bit T0O

and T2O in PSR0 register.

In the “counter” function, the register is increased in response to

a 0-to-1 (rising edge) transition at its corresponding external input

pin, EC0(Timer 0) or EC1(Timer 2).

In operation of Timer 2 and Timer 3, their operations are same as

Timer 0 and Timer 1, respectively as shown in Table 14-2.

In addition the “capture” function, the register is increased in re-

sponse external or internal clock sources same with timer or

T0CK T1CK

16BIT CAP0 CAP1 PWM1E

PWM1O

TIMER 0

8-bit Timer

TIMER 1

8-bit Timer

[2:0]

XXX

111

[1:0]

XX

11

0

1

0

1

0

1

0

1

0

1

0

1

8-bit Event counter

8-bit Capture

X¹

0

XXX

111

8-bit Compare Output

10-bit PWM

8-bit Timer/Counter

16-bit Timer

0

11

16-bit Event counter

16-bit Capture

1

XXX

11

0

11

16-bit Compare Output

Table 14-1 Operating Modes of Timer 0, 1

1. X: The value “0” or “1” corresponding to user operation.

T2CK

[2:0]

T3CK

[1:0]

16BIT CAP2 CAP3 PWM3E

PWM3O

TIMER 2

8-bit Timer

TIMER 3

0

1

0

1

0

1

0

1

0

1

0

XXX

111

XX

11

0

1

0

1

8-bit Timer

8-bit Event counter

8-bit Capture

8-bit Compare Output

10-bit PWM

XXX

111

X¹

0

8-bit Timer/Counter

16-bit Timer

0

11

16-bit Event counter

16-bit Capture

1

XXX

11

0

11

16-bit Compare Output

Table 14-2 Operating Modes of Timer 2, 3

1. X: The value “0” or “1” corresponding to user operation.

52

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

CAP4

T4CK[2:0]

TIMER 4

XXX¹

XXX

0

1

16-bit Timer

16-bit Capture

Table 14-3 Operating Modes of Timer 4

1. X: The value “0” or “1” corresponding to user operation.

MAR. 2005 Ver 0.2

53

MC80F0424/0432/0448

Preliminary

R/W R/W R/W R/W R/W R/W

5

4

3

2

1

0

ADDRESS: 0D0

INITIAL VALUE: --000000

H

TM0

-

CAP0 T0CK2 TB0TCCKL1 T0CK0 T0CN T0ST

B

Bit Name

Bit Position

Description

CAP0

TM0.5

0: Timer/Counter mode

1: Capture mode selection flag

T0CK2

T0CK1

T0CK0

TM0.4

TM0.3

TM0.2

000: 8-bit Timer, Clock source is f

001: 8-bit Timer, Clock source is f

010: 8-bit Timer, Clock source is f

011: 8-bit Timer, Clock source is f

100: 8-bit Timer, Clock source is f

101: 8-bit Timer, Clock source is f

110: 8-bit Timer, Clock source is f

111: EC0 (External clock)

÷ 2

XIN

÷ 4

÷ 8

÷ 32

÷ 128

÷ 512

÷ 2048

T0CN

T0ST

TM0.1

TM0.0

0: Timer count pause

1: Timer count start

0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D2

INITIAL VALUE: 00

H

TM1

POL 16BIT PWM1E CAP1 TB1TCCKL1 T1CK0 T1CN T1ST

H

Bit Name

Bit Position

Description

POL

TM1.7

0: PWM Duty Active Low

1: PWM Duty Active High

16BIT

PWMIE

CAP1

TM1.6

TM1.5

TM1.4

0: 8-bit Mode

1: 16-bit Mode

0: Disable PWM

1: Enable PWM

0: Timer/Counter mode

1: Capture mode selection flag

T1CK1

T1CK0

TM1.3

TM1.2

00: 8-bit Timer, Clock source is f

01: 8-bit Timer, Clock source is f

10: 8-bit Timer, Clock source is f

XIN

÷ 2

÷ 8

11: 8-bit Timer, Clock source is Using the Timer 0 Clock

T1CN

T1ST

TM1.1

TM1.0

0: Timer count pause

1: Timer count start

0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D1

INITIAL VALUE: 0FF

H

TDR0

TDR1

H

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D3

H

INITIAL VALUE: 0FF

H

Read: Count value read

Write: Compare data write

Figure 14-1 TM0, TM1 Registers

54

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

R/W R/W R/W R/W R/W R/W

5

4

3

2

1

0

ADDRESS: 0D6

INITIAL VALUE: --000000

H

TM2

-

CAP2 T2CK2 TB2TCCKL1 T2CK0 T2CN T2ST

B

Bit Name

Bit Position

Description

CAP2

TM2.5

0: Timer/Counter mode

1: Capture mode selection flag

T2CK2

T2CK1

T2CK0

TM2.4

TM2.3

TM2.2

000: 8-bit Timer, Clock source is f

001: 8-bit Timer, Clock source is f

010: 8-bit Timer, Clock source is f

011: 8-bit Timer, Clock source is f

100: 8-bit Timer, Clock source is f

101: 8-bit Timer, Clock source is f

110: 8-bit Timer, Clock source is f

111: EC1 (External clock)

÷ 2

XIN

÷ 4

÷ 8

÷ 16

÷ 64

÷ 256

÷ 1024

T2CN

T2ST

TM2.1

TM2.0

0: Timer count pause

1: Timer count start

0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D8

INITIAL VALUE: 00

H

TM3

POL 16BIT PWM3E CAP3 TB3TCCKL1 T3CK0 T3CN T3ST

H

Bit Name

Bit Position

Description

POL

TM3.7

0: PWM Duty Active Low

1: PWM Duty Active High

16BIT

TM3.6

TM3.5

TM3.4

0: 8-bit Mode

1: 16-bit Mode

PWM3E

CAP3

0: Disable PWM

1: Enable PWM

0: Timer/Counter mode

1: Capture mode selection flag

T3CK1

T3CK0

TM3.3

TM3.2

00: 8-bit Timer, Clock source is f

01: 8-bit Timer, Clock source is f

10: 8-bit Timer, Clock source is f

XIN

÷ 4

÷ 16

11: 8-bit Timer, Clock source is Using the Timer 2 Clock

T3CN

T3ST

TM3.1

TM3.0

0: Timer count pause

1: Timer count start

0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D7

INITIAL VALUE: 0FF

H

TDR2

TDR3

H

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D9

H

INITIAL VALUE: 0FF

H

Read: Count value read

Write: Compare data write

Figure 14-2 TM2, TM3 Registers

MAR. 2005 Ver 0.2

55

MC80F0424/0432/0448

Preliminary

R/W R/W R/W R/W R/W R/W

5

4

3

2

1

0

ADDRESS: 0DC

INITIAL VALUE: --000000

H

TM4

-

CAP4 T4CK2 TB4TCCKL1 T4CK0 T4CN T4ST

B

Bit Name

Bit Position

Description

CAP4

TM4.5

0: Timer/Counter mode

1: Capture mode selection flag

T4CK2

T4CK1

T4CK0

TM4.4

TM4.3

TM4.2

000: 8-bit Timer, Clock source is f

001: 8-bit Timer, Clock source is f

010: 8-bit Timer, Clock source is f

011: 8-bit Timer, Clock source is f

100: 8-bit Timer, Clock source is f

101: 8-bit Timer, Clock source is f

110: 8-bit Timer, Clock source is f

111: 8-bit Timer, Clock source is f

÷ 2

XIN

÷ 4

÷ 8

÷ 16

÷ 64

÷ 256

÷ 1024

÷ 2048

T4CN

T4ST

TM4.1

TM4.0

0: Timer count pause

1: Timer count start

0: When cleared, stop the counting.

1: When set, Timer 0 Count Register is cleared and start again.

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0DD

INITIAL VALUE: 0FF

H

TDR4H

TDR4L

H

R/W R/W R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0DE

H

INITIAL VALUE: 0FF

H

Figure 14-3 TM4 Registers

14.1 8-bit Timer / Counter Mode

The MC80F0424/0432/0448 has four 8-bit Timer/Counters, Tim-

er 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown

in Figure 14-4 and Timer 2, Timer 3 are shown in Figure 14-5.

be cleared to "0"(Figure 14-4). These timers have each 8-bit

count register and data register. The count register is increased by

every internal or external clock input. The internal clock has a

prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256,

512, 1024, 2048 or external clock (selected by control bits

TxCK0, TxCK1, TxCK2 of register TMx).

The “timer” or “counter” function is selected by control registers

TM0, TM1, TM2, TM3 as shown in Figure 14-1. To use as an 8-

bit timer/counter mode, bit CAP0, CAP1, CAP2, or CAP3 of

TMx should be cleared to “0” and 16BIT of TM1 or TM3 should

56

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0D0

INITIAL VALUE: --000000

H

TM0

TM1

CAP0 T0CK2TB0TCCKL1 T0CK0 T0CN T0ST

B

0

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D2

H

POL 16BIT PWM1E CAP1 TB1TCCKL1 T1CK0 T1CN T1ST

INITIAL VALUE: 00

H

0

X

0

X

T0CK[2:0]

RISING EDGE

DETECTOR

EC0 PIN

X_INPIN

111

000

T0ST

0: Stop

1: Clear and start

÷ 2

÷ 4

001

010

011

÷ 8

T0 (8-bit)

÷ 32

÷ 128

÷ 512

clear

100

101

TIMER 0

INTERRUPT

T0CN

T0IF

Comparator

÷ 2048

110

TIMER 0

TDR0 (8-bit)

MUX

F/F

R14/T0O

T1CK[1:0]

11

T1ST

0: Stop

1: Clear and start

÷ 1

÷ 2

÷ 8

00

01

10

T1 (8-bit)

clear

TIMER 1

INTERRUPT

T1CN

T1IF

F/F

MUX

Comparator

TIMER 1

TDR1 (8-bit)

R53/PWM1O/T1O

Figure 14-4 8-bit Timer/Counter 0, 1

MAR. 2005 Ver 0.2

57

MC80F0424/0432/0448

Preliminary

7

6

-

5

4

3

2

1

0

ADDRESS: 0D6

INITIAL VALUE: --000000

H

TM2

TM3

-

CAP2 T2CK2TB2TCCKL1 T2CK0 T2CN T2ST

B

0

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D8

INITIAL VALUE: 00

H

POL 16BIT PWM3E CAP3 TB3TCCKL1 T3CK0 T3CN T3ST

H

0

X

0

X

T2CK[2:0]

RISING EDGE

DETECTOR

EC1 PIN

X_INPIN

111

000

T2ST

0: Stop

1: Clear and start

÷ 2

÷ 4

001

010

011

÷ 8

T2 (8-bit)

÷ 16

÷ 64

÷ 256

clear

100

101

TIMER 2

INTERRUPT

T2CN

T2IF

Comparator

÷ 1024

110

TIMER 2

TDR2 (8-bit)

MUX

F/F

R52/T2O

T3CK[1:0]

11

T3ST

0: Stop

1: Clear and start

÷ 1

÷ 4

00

01

10

T3 (8-bit)

clear

÷ 16

TIMER 3

INTERRUPT

T3CN

T3IF

F/F

MUX

Comparator

TIMER 3

TDR3 (8-bit)

R54/PWM3O/T3O

Figure 14-5 8-bit Timer/Counter 2, 3

58

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Example 1:

These timers have each 8-bit count register and data register. The

count register is increased by every internal or external clock in-

put. The internal clock has a prescaler divide ratio option of 2, 4,

8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of reg-

ister TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register

TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits

T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits

T3CK[1:0] of register TM3. In the Timer 0, timer register T0 in-

creases from 00_Huntil it matches TDR0 and then reset to 00_H.

The match output of Timer 0 generates Timer 0 interrupt (latched

in T0IF bit).

Timer0 = 2ms 8-bit timer mode at 4MHz

Timer1 = 0.5ms 8-bit timer mode at 4MHz

Timer2 = 1ms 8-bit timer mode at 4MHz

Timer3 = 1ms 8-bit timer mode at 4MHz

LDM

SET1 T0E

SET1 T1E

SET1 T2E

SET1 T3E

EI

TDR0,#249

TDR1,#249

TDR2,#249

TDR3,#249

TM0,#0000_1111B

TM1,#0000_1011B

TM2,#0000_1111B

TM3,#0000_1011B

In counter function, the counter is increased every 0-to-1(1-to-0)

(rising & falling edge) transition of EC0 pin. In order to use

counter function, the bit EC0 of the Port Selection Regis-

ter(PSR0.4) is set to "1". The Timer 0 can be used as a counter by

pin EC0 input, but Timer 1 can not. Likewise, In order to use

Timer2 as counter function, the bit EC1 of the Port Selection

Register(PSR0.5) is set to "1". The Timer 2 can be used as a

counter by pin EC1 input, but Timer 3 can not.

Example 2:

Timer0 = 8-bit event counter mode

Timer1 = 0.5ms 8-bit timer mode at 4MHz

Timer2 = 8-bit event counter mode

Timer3 = 1ms 8-bit timer mode at 4MHz

14.1.1 8-bit Timer Mode

LDM

TDR0,#249

In the timer mode, the internal clock is used for counting up.

Thus, you can think of it as counting internal clock input. The

contents of TDRn are compared with the contents of up-counter,

Tn. If match is found, a timer n interrupt (TnIF) is generated and

the up-counter is cleared to 0. Counting up is resumed after the

up-counter is cleared.

TDR1,#249

TDR2,#249

TDR3,#249

TM0,#0001_1111B

TM1,#0000_1011B

TM2,#0001_1111B

TM3,#0000_1011B

SET1 T0E

SET1 T1E

SET1 T2E

SET1 T3E

EI

As the value of TDRn is changeable by software, time interval is

set as you want.

Start count

Source clock

Up-counter

2

3

n-2

n-1

n

1

4

2

3

0

1

0

n

TDR1

Match

Detect

Counter

Clear

T1IF interrupt

Figure 14-6 Timer Mode Timing Chart

MAR. 2005 Ver 0.2

59

MC80F0424/0432/0448

Preliminary

Example: Make 1ms interrupt using by Timer0 at 4MHz

LDM

TM0,#0FH

; divide by 32

TDR0,#124

; 8us x (124+1)= 1ms

; Enable Timer 0 Interrupt

; Enable Master Interrupt

SET1 T0E

EI

When

TM0 = 0000 1111 (8-bit Timer mode, Prescaler divide ratio = 32)

B

TDR0 = 124 = 7C

D

H

f

= 4 MHz

XIN

1

INTERRUPT PERIOD =

TDR0

× 32 × (124+1) = 1 ms

6

4 × 10 Hz

MATCH

Count Pulse

Period

(TDR0 = T0)

7C

7B

7C

7A

8 µs

6

5

4

3

2

1

0

TIME

Interrupt period

= 8 µs x (124+1)

Timer 0 (T0IF)

Interrupt

Occur interrupt

Figure 14-7 Timer Count Example

In order to use event counter function, the bit 4, 5 of the Port Se-

lection Register PSR0(address 0F8_H) is required to be set to “1”.

14.1.2 8-bit Event Counter Mode

In this mode, counting up is started by an external trigger. This

trigger means rising edge of the EC0 or EC1 pin input. Source

clock is used as an internal clock selected with timer mode regis-

ter TM0 or TM2. The contents of timer data register TDRn (n =

0,1,2,3) are compared with the contents of the up-counter Tn. If a

match is found, an timer interrupt request flag TnIF is generated,

and the counter is cleared to “0”. The counter is restart and count

up continuously by every rising edge of the EC0 or EC1 pin input.

After reset, the value of timer data register TDRn is initialized to

"0", The interval period of Timer is calculated as below equation.

1

----------

Period (sec) =

× 2 × Divide Ratio × (TDRn+1)

f

XIN

The maximum frequency applied to the EC0 or EC1 pin is f_XIN

2 [Hz].

/

Start count

ECn pin input

1

2

Up-counter

0

2

n-1

n

0

TDR1

n

T1IF interrupt

Figure 14-8 Event Counter Mode Timing Chart

60

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

TDR1

enable

disable

clear & start

stop

TIME

Timer 1 (T1IF)

Interrupt

Occur interrupt

T1ST

Start & Stop

T1ST = 1

T1ST = 0

T1CN

T1CN = 1

Control count

T1CN = 0

Figure 14-9 Count Operation of Timer / Event counter

MAR. 2005 Ver 0.2

61

MC80F0424/0432/0448

Preliminary

14.2 16-bit Timer / Counter Mode

The Timer register is being run with all 16 bits. A 16-bit timer/

counter register T0, T1 are incremented from 0000_Huntil it

matches TDR0, TDR1 and then resets to 0000_H. The match out-

put generates Timer 0 interrupt.

T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively

as shown in Figure 14-11.

Even if the Timer 0 (including Timer 1) is used as a 16-bit timer,

the Timer 2 and Timer 3 can still be used as either two 8-bit timer

or one 16-bit timer by setting the TM2. Reversely, even if the

Timer 2 (including Timer 3) is used as a 16-bit timer, the Timer

0 and Timer 1 can still be used as 8-bit timer independently.

The clock source of the Timer 0 is selected either internal or ex-

ternal clock by bit T0CK[2:0]. In 16-bit mode, the bits

T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively

as shown in Figure 14-10.

A 16-bit timer/counter 4 register T4H, T4L are increased from

0000_Huntil it matches TDR4H, TDR4L and then resets to 0000_H.

The match output generates Timer 4 interrupt. Timer/Counter 4

is 16 bit mode as shown in Figure 14-12.

Likewise, A 16-bit timer/counter register T2, T3 are incremented

from 0000_Huntil it matches TDR2, TDR3 and then resets to

0000_H. The match output generates Timer 2 interrupt.

The clock source of the Timer 2 is selected either internal or ex-

ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0D0

INITIAL VALUE: --000000

H

TM0

TM1

CAP0 T0CK2 TB0TCCKL1T0CK0 T0CN T0ST

B

0

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D2

H

POL 16BIT PWM1E CAP1 TB1TCCKL1T1CK0 T1CN T1ST

INITIAL VALUE: 00

H

0

X

1

X

T0CK[2:0]

RISING EDGE

DETECTOR

EC0 PIN

X_INPIN

111

000

T0ST

÷ 2

0: Stop

1: Clear and start

÷ 4

001

010

011

÷ 8

T1 + T0

(16-bit)

clear

÷ 32

÷ 128

÷ 512

÷ 2048

100

101

110

TIMER 0

INTERRUPT

T0CN

T0IF

Comparator

(Not Timer 1 interrupt)

MUX

TDR1 + TDR0

(16-bit)

F/F

R14/T0O

Lower byte

Higher byte

COMPARE DATA

TIMER 0 + TIMER 1 → TIMER 0 (16-bit)

Figure 14-10 16-bit Timer/Counter for Timer 0, 1

62

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0D6

INITIAL VALUE: --000000

H

TM2

TM3

CAP2 T2CK2 TB2TCCKL1 T2CK0 T2CN T2ST

B

0

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D8

H

POL 16BIT PWM3E CAP3 TB3TCCKL1T3CK0 T3CN T3ST

INITIAL VALUE: 00

H

0

X

1

X

T2CK[2:0]

RISING EDGE

DETECTOR

EC1 PIN

X_INPIN

111

000

T2ST

÷ 2

0: Stop

1: Clear and start

÷ 4

001

010

011

÷ 8

T3 + T2

(16-bit)

clear

÷ 16

÷ 64

100

101

110

TIMER 2

INTERRUPT

T2CN

÷ 256

T2IF

÷ 1024

Comparator

(Not Timer 3 interrupt)

MUX

TDR3 + TDR2

(16-bit)

F/F

R52/T2O

Lower byte

Higher byte

COMPARE DATA

TIMER 2 + TIMER 3 → TIMER 2 (16-bit)

Figure 14-11 16-bit Timer/Counter for Timer 2, 3

14.3 8-bit Compare Output (16-bit)

The MC80F0424/0432/0448 has a function of Timer Compare

Output. To pulse out, the timer match can goes to port pin(T0O,

PWM1O, T2O, PWM3O) as shown in Figure 14-4, Figure 14-5

and Figure 14-12. In this mode, the bit PWM1O and PWM3O of

PSR0 register should be set to “1”, and the bit PWM1E/PWM3E

of timer1/timer3 mode register (TM1/TM3) should be set to “0”.

These Compare output pins output the signal having a 50:50 duty

square wave, and output frequency is same as below equation.

Oscillation Frequency

f

= ---------------------------------------------------------------------------------

COMP

2 × Prescaler Value × (TDR + 1 )

MAR. 2005 Ver 0.2

63

MC80F0424/0432/0448

Preliminary

In addition, 16-bit Compare output mode is available, also.

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0DC

INITIAL VALUE: 00

H

TM4

CAP4 T4CK2 TB4TCCKL1T4CK0 T4CN T4ST

H

0

X

T4CK[2:0]

000

X

X means the value of "0" or "1" corresponding to user operation

÷ 2

÷ 4

T4ST

X_INPIN

001

010

011

0: Stop

1: Clear and start

÷ 8

÷ 16

÷ 64

T4H + T4L

(16-bit)

100

101

110

111

clear

÷ 256

÷ 1024

÷ 2048

TIMER 4

INTERRUPT

T4CN

T4IF

Comparator

TDR4H + TDR4L

(16-bit)

MUX

Lower byte

Higher byte

COMPARE DATA

Figure 14-12 Timer 4 for only 16 bit mode

14.4 8-bit Capture Mode

The Timer 0 capture mode is set by bit CAP0 of timer mode reg-

ister TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as

shown in Figure 14-13. Likewise, the Timer 2 capture mode is set

by bit CAP2 of timer mode register TM2 (bit CAP3 of timer

mode register TM3 for Timer 3) as shown in Figure 14-14.

than wanted value. It can be obtained correct value by counting

the number of timer overflow occurrence.

Timer/Counter still does the above, but with the added feature

that a edge transition at external input INTx pin causes the current

value in the Timer x register (T0,T1,T2,T3), to be captured into

registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. Af-

ter captured, Timer x register is cleared and restarts by hardware.

It has three transition modes: "falling edge", "rising edge", "both

edge" which are selected by interrupt edge selection register

IEDS. Refer to “19.5 External Interrupt” on page 96. In addition,

the transition at INTn pin generate an interrupt.

The Timer/Counter register is increased in response internal or

external input. This counting function is same with normal timer

mode, and Timer interrupt is generated when timer register T0

(T1, T2, T3) increases and matches TDR0 (TDR1, TDR2,

TDR3).

This timer interrupt in capture mode is very useful when the pulse

width of captured signal is more wider than the maximum period

of Timer.

Note: The CDRn and TDRn are in same address.In the

capture mode, reading operation is read the CDRn, not

TDRn because path is opened to the CDRn.

For example, in Figure 14-16, the pulse width of captured signal

is wider than the timer data value (FF_H) over 2 times. When ex-

ternal interrupt is occurred, the captured value (13_H) is more little

64

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0D0

INITIAL VALUE: --000000

H

TM0

TM1

CAP0 T0CK2 TB0TCCKL1T0CK0 T0CN T0ST

B

1

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D2

H

POL 16BIT PWM1E CAP1 TB1TCCKL1T1CK0 T1CN T1ST

INITIAL VALUE: 00

H

0

1

X

0

X

T0CK[2:0]

Rising Edge

Detector

EC0 PIN

X_INPIN

111

000

T0ST

0: Stop

1: Clear and start

÷ 2

÷ 4

001

010

011

÷ 8

T0 (8-bit)

÷ 32

÷ 128

÷ 512

clear

100

101

T0CN

Capture

CDR0 (8-bit)

÷ 2048

110

MUX

IEDS[1:0]

“01”

“10”

INT0

INTERRUPT

INT0IF

INT0 PIN

T1CK[1:0]

11

“11”

T1ST

0: Stop

1: Clear and start

÷ 1

÷ 2

÷ 8

00

01

10

T1 (8-bit)

clear

T1CN

MUX

Capture

CDR1 (8-bit)

IEDS[3:2]

“01”

“10”

INT1

INTERRUPT

INT1IF

INT1 PIN

“11”

Figure 14-13 8-bit Capture Mode for Timer 0, 1

MAR. 2005 Ver 0.2

65

MC80F0424/0432/0448

Preliminary

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0D6

INITIAL VALUE: --000000

H

TM2

TM3

CAP2 T2CK2 TB2TCCKL1T2CK0 T2CN T2ST

B

1

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D8

H

POL 16BIT PWM3E CAP3 TB3TCCKL1T3CK0 T3CN T3ST

INITIAL VALUE: 00

H

0

1

X

0

X

T2CK[2:0]

Rising Edge

Detector

EC1 PIN

X_INPIN

111

000

T2ST

0: Stop

1: Clear and start

÷ 2

÷ 4

001

010

011

÷ 8

T2 (8-bit)

÷ 16

÷ 64

÷ 256

clear

100

101

T2CN

Capture

CDR2 (8-bit)

÷ 1024

110

MUX

IEDS[5:4]

“01”

“10”

INT2

INTERRUPT

INT2IF

INT2 PIN

T3CK[1:0]

11

“11”

T3ST

0: Stop

1: Clear and start

÷ 1

÷ 4

00

01

10

T3 (8-bit)

÷ 16

clear

T3CN

MUX

Capture

CDR3 (8-bit)

IEDS[7:6]

“01”

“10”

INT3

INTERRUPT

INT3IF

INT3 PIN

“11”

Figure 14-14 8-bit Capture Mode for Timer 2, 3

66

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

This value is loaded to CDR0

n

T0

n-1

9

8

7

6

5

4

3

2

1

0

TIME

Ext. INT0 Pin

Interrupt Request

( INT0IF )

Interrupt Interval Period

Ext. INT0 Pin

Interrupt Request

( INT0IF )

20nS

5nS

Delay

Clear & Start

Capture

( Timer Stop )

Figure 14-15 Input Capture Operation of Timer 0 Capture mode

Ext. INT0 Pin

Interrupt Request

( INT0IF )

Interrupt Interval Period=01_H+FF_H+01_H+FF_H+01_H+13_H=214_H

Interrupt Request

( T0IF )

FF_H

T0

13_H

00_H

Figure 14-16 Excess Timer Overflow in Capture Mode

MAR. 2005 Ver 0.2

67

MC80F0424/0432/0448

Preliminary

14.5 16-bit Capture Mode

16-bit capture mode is the same as 8-bit capture, except that the

Timer register is being run will 16 bits. The clock source of the

Timer 0 is selected either internal or external clock by bit

T0CK[2:0]. In 16-bit mode, the bits T1CK1, T1CK0, CAP1 and

16BIT of TM1 should be set to "1" respectively as shown in Fig-

ure 14-17.

ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits

T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1" re-

spectively as shown in Figure 14-18.

The clock source of the Timer 4 is selected either internal or ex-

ternal clock by bit T4CK[2:0] as shown in Figure 14-18.

The clock source of the Timer 2 is selected either internal or ex-

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0D0

INITIAL VALUE: --000000

H

TM0

TM1

CAP0 T0CK2 TB0TCCKL1T0CK0 T0CN T0ST

B

1

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D2

H

POL 16BIT PWM1E CAP1 TB1TCCKL1T1CK0 T1CN T1ST

INITIAL VALUE: 00

H

0

1

X

1

X

T0CK[2:0]

Rising Edge

Detector

EC0 PIN

X_INPIN

111

000

T0ST

0: Stop

1: Clear and start

÷ 2

÷ 4

÷ 8

001

010

011

TDR1 + TDR0

(16-bit)

÷ 32

clear

÷ 128

÷ 512

100

101

110

T0CN

Capture

÷ 2048

CDR1 + CDR0

(16-bit)

MUX

IEDS[1:0]

Lower byte

Higher byte

CAPTURE DATA

“01”

“10”

INT0

INTERRUPT

INT0IF

INT0 PIN

“11”

Figure 14-17 16-bit Capture Mode of Timer 0, 1

68

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0D6

INITIAL VALUE: --000000

H

TM2

TM3

CAP2 T2CK2TB2TCCKL1 T2CK0 T2CN T2ST

B

1

X

-

X

X means the value of "0" or "1" corresponding to user operation

7

6

5

4

3

2

1

0

ADDRESS: 0D8

H

POL 16BIT PWM3E CAP3 TB3TCCKL1T3CK0 T3CN T3ST

INITIAL VALUE: 00

H

0

X

1

X

T2CK[2:0]

Rising Edge

Detector

EC1 PIN

X_INPIN

111

000

T2ST

0: Stop

1: Clear and start

÷ 2

÷ 4

÷ 8

001

010

011

TDR3 + TDR2

(16-bit)

÷ 16

÷ 64

÷ 256

clear

100

101

110

T2CN

Capture

÷ 1024

CDR3 + CDR2

(16-bit)

MUX

IEDS[5:4]

Lower byte

Higher byte

CAPTURE DATA

“01”

“10”

INT2

INTERRUPT

INT2IF

INT2 PIN

“11”

Figure 14-18 16-bit Capture Mode of Timer 2, 3

MAR. 2005 Ver 0.2

69

MC80F0424/0432/0448

Preliminary

7

-

6

-

5

4

3

2

1

0

ADDRESS: 0DC

INITIAL VALUE: 00

H

TM4

CAP4 T4CK2 TB4TCCKL1T4CK0 T4CN T4ST

H

1

X

X means the value of "0" or "1" corresponding to user operation

T4CK[2:0]

000

÷ 2

T4ST

÷ 4

X_INPIN

001

010

011

÷ 8

0: Stop

1: Clear and start

÷ 16

÷ 64

÷ 256

TDR4H + TDR4L

(16-bit)

100

101

110

111

clear

÷ 1024

÷ 2048

T4CN

Capture

CDR4H + CDR4L

(16-bit)

MUX

IEDS[1:0]

Lower byte

Higher byte

CAPTURE DATA

“01”

“10”

INT3

INTERRUPT

INT3IF

INT3 PIN

“11”

Figure 14-19 16-bit Capture Mode of Timer 4

Example 1:

EI

:

Timer0 = 16-bit timer mode, 0.5s at 4MHz

LDM

TM0,#0000_1111B;8uS

TM1,#0100_1100B;16bit Mode

Example 3:

Timer0 = 16-bit capture mode

TDR0,#<62499

TDR1,#>62499

;8uS X 62500

;=0.5s

SET1 T0E

LDM

PSR0,#0000_0001B;INT0 set

TM0,#0010_1111B;CaptureMode

TM1,#0100_1100B;16bit Mode

EI

:

TDR0,#<0FFFFH

TDR1,#>0FFFFH

;

Example 2:

Timer0 = 16-bit event counter mode

IEDS,#01H

SET1 T0E

;Falling Edge

SET1 INT0E

EI

:

LDM

PSR0,#0001_0000B;EC0 Set

TM0,#0001_1111B;CounterMode

TM1,#0100_1100B;16bit Mode

:

TDR0,#<0FFFFH

TDR1,#>0FFFFH

;

SET1 T0E

70

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

14.6 PWM Mode

The MC80F0424/0432/0448 has a high speed PWM (Pulse

Width Modulation) functions which shared with Timer1 and

Timer3.

Table 14-4 shows the relation of PWM frequency vs. resolution.

If it needed more higher frequency of PWM, it should be reduced

resolution.

In PWM mode, pin R53/PWM1O and R54/PWM3O outputs up

to a 10-bit resolution PWM output. This pin should be configured

as a PWM output by setting "1" to bit PWM1O and PWM3O in

PSR0 register.

Frequency

Resolution

T1CK[1:0]

= 10(2uS)

= 00(250nS) = 01(500nS)

The period of the PWM1 output is determined by the T1PPR (T1

PWM Period Register) and T1PWHR[3:2] (bit3,2 of T1 PWM

High Register) and the duty of the PWM1 output is determined

by the T1PDR (T1 PWM Duty Register) and T1PWHR[1:0]

(bit1,0 of T1 PWM High Register).

10-bit

9-bit

8-bit

7-bit

3.9kHz

7.8kHz

0.98kHz

1.95kHz

3.90kHz

7.81kHz

0.49kHz

0.97kHz

1.95kHz

3.90kHz

15.6kHz

31.2kHz

The user writes the lower 8-bit period value to the T1PPR and the

higher 2-bit period value to the T1PWHR[3:2]. And writes duty

value to the T1PDR and the T1PWHR[1:0] same way.

Table 14-4 PWM Frequency vs. Resolution at 4MHz

The T1PDR is configured as a double buffering for glitch less

PWM output. In Figure 14-1, the duty data is transferred from the

master to the slave when the period data matched to the counted

value. (i.e. at the beginning of next duty cycle)

The bit POL of TM1 decides the polarity of duty cycle.

If the duty value is set same to the period value, the PWM output

is determined by the bit POL (1: High, 0: Low). And if the duty

value is set to "00_H", the PWM output is determined by the bit

POL (1: Low, 0: High).

PWM1 Period = [PWM1HR[3:2]T1PPR] X Source Clock

PWM1 Duty = [PWM1HR[1:0]T1PDR] X Source Clock

It can be changed duty value when the PWM output. However the

changed duty value is output after the current period is over. And

it can be maintained the duty value at present output when

changed only period value shown as Figure 14-23. As it were, the

absolute duty time is not changed in varying frequency. But the

changed period value must greater than the duty value.

Likewise, the period of the PWM3 output is determined by the

T3PPR (T3 PWM Period Register) and T3PWHR[3:2] (bit3,2 of

T3 PWM High Register) and the duty of the PWM output is de-

termined by the T3PDR (T3 PWM Duty Register) and

T3PWHR[1:0] (bit1,0 of T3 PWM High Register).

Note: If changing the Timer1 to PWM function, it should be

stopped with the timer clock uncounted firstly, and then set

period and duty register value. If user writes register values

while timer is in operation, these register could be set with

certain values.

The user writes the lower 8-bit period value to the T3PPR and the

higher 2-bit period value to the T3PWHR[3:2]. And writes duty

value to the T3PDR and the T3PWHR[1:0] same way.

The T3PDR is configured as a double buffering for glitch less

PWM output. In Figure 14-21, the duty data is transferred from

the master to the slave when the period data matched to the count-

ed value. (i.e. at the beginning of next duty cycle)

Ex) Sample Program @4MHz 2uS

LDM TM1,#1010_1000b ; Set Clock & PWM1E

PWM3 Period = [PWM3HR[3:2]T3PPR] X Source Clock

PWM3 Duty = [PWM3HR[1:0]T3PDR] X Source Clock

LDM T1PPR,#199

LDM T1PDR,#99

LDM PWM1HR,00H

; Period :400uS=2uSX(199+1)

; Duty:200uS=2uSX(99+1)

LDM TM1,#1010_1011b ; Start timer1

The relation of frequency and resolution is in inverse proportion.

MAR. 2005 Ver 0.2

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MC80F0424/0432/0448

Preliminary

R/W

7

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

6

ADDRESS : D2

RESET VALUE : 00000000

H

POL

16BIT

PWM1E

CAP1

T1CK1

X

T1CK0

X

T1CN

X

T1ST

X

TM1

X

0

1

0

-

7

-

6

-

W

3

W

2

W

1

W

0

5

4

ADDRESS : D5

RESET VALUE : ----0000

Bit Manipulation Not Available

H

-

T1PWHR3 T1PWHR2 T1PWHR1 T1PWHR0

T1PWHR

B

-

X

Period High

Duty High

X : The value "0" or "1" corresponding to user operation.

W

5

W

4

W

3

W

1

W

0

W

7

W

6

2

ADDRESS : D3

RESET VALUE : 0FF

H

T1PPR

T1PDR

H

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

R/W

7

R/W

6

ADDRESS : D4

RESET VALUE : 00

H

T1PWHR[3:2]

T1ST

T1PPR(8-bit)

T0 clock source

[T0CK]

0 : Stop

1 : Clear and Start

R53/PWM1O

COMPARATOR

CLEAR

S

Q

1

R

MUX

(2-bit)

T1 ( 8-bit )

PWM1O

[PSR0.6]

÷

1

2

8

POL

X_IN

COMPARATOR

T1CN

Slave

T1CK[1:0]

T1PDR(8-bit)

T1PWHR[1:0]

Master

T1PDR(8-bit)

Figure 14-20 PWM1 Mode

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MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

R/W

7

R/W

6

ADDRESS : D8H

RESET VALUE : 00000000

POL

16BIT

0

PWM3E

1

CAP3

0

T3CK1

X

T3CK0

X

T3CN

X

T3ST

X

TM3

X

-

W

3

W

2

W

1

W

0

-

7

-

6

5

4

ADDRESS : DBH

RESET VALUE : ----0000

Bit Manipulation Not Available

-

T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0

T3PWHR

-

X

Period High

Duty High

X : The value "0" or "1" corresponding to user operation.

W

5

W

4

W

3

W

1

W

0

W

7

W

6

2

ADDRESS : D9

RESET VALUE : 0FF

H

T3PPR

T3PDR

H

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

R/W

7

R/W

6

ADDRESS : DA

RESET VALUE : 00

H

T3PWHR[3:2]

T3ST

T3PPR(8-bit)

T2 clock source

[T2CK]

0 : Stop

1 : Clear and Start

R54/PWM3O

COMPARATOR

CLEAR

S

Q

1

R

MUX

(2-bit)

T3 ( 8-bit )

PWM3O

[PSR0.7]

÷

1

POL

4

X_IN

COMPARATOR

16

T3CN

Slave

T3CK[1:0]

T3PDR(8-bit)

T1PWHR[1:0]

Master

T3PDR(8-bit)

Figure 14-21 PWM3 Mode

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Preliminary

Source

clock

00

01

02

03

04

7E

7F

80

3FF

00

01

02

T1

PWM1E

T1ST

T1CN

PWM1O

[POL=1]

PWM1O

[POL=0]

Duty Cycle [ (1+7Fh) x 250nS = 32uS ]

Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ]

T1CK[1:0] = 00 ( XIN )

T1PWHR = 0CH

T1PPR (8-bit)

T1PWHR3 T1PWHR2

Period

Duty

1

FFH

T1PPR = FFH

T1PDR = 7FH

T1PDR (8-bit)

7FH

T1PWHR1 T1PWHR0

0

Figure 14-22 Example of PWM at 4MHz

T1CK[1:0] = 10 ( 2us )

PWM1HR = 00H

T1PPR = 0DH

T1PDR = 04H

Write T1PPR to 09H

Source

clock

T1

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04

PWM1O

POL=1

Duty Cycle

[ (04h+1) x 2uS = 10uS ]

Duty Cycle

[ (04h+1) x 2uS = 10uS ]

Duty Cycle

[ (04h+1) x 2uS = 10uS ]

Period Cycle [ (1+0Dh) x 2uS = 28uS, 35.5KHz ]

Period Cycle [ (1+09h) x 2uS = 20uS, 50KHz ]

Figure 14-23 Example of Changing the Period in Absolute Duty Cycle (@4MHz)

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MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

15. ANALOG TO DIGITAL CONVERTER

The analog-to-digital converter (A/D) allows conversion of an

analog input signal to a corresponding 10-bit digital value. The A/

D module has sixteen analog inputs, which are multiplexed into

one sample and hold. The output of the sample and hold is the in-

put into the converter, which generates the result via successive

approximation. The analog supply voltage is connected to AV_DD

of Sample & Hold logic of A/D module. The AV_DDwas separat-

ed with V_DDin order to minimize the degradation of operation

characteristic by power supply noise.

ADCRH and ADCRL contains the results of the A/D conversion.

When the conversion is completed, the result is loaded into the

ADCRH and ADCRL, the A/D conversion status bit ADSF is set

to “1”, and the A/D interrupt flag ADCIF is set. See Figure 15-1

for operation flow.

The block diagram of the A/D module is shown in Figure 15-3.

The A/D status bit ADSF is set automatically when A/D conver-

sion is completed, cleared when A/D conversion is in process.

The conversion time takes 12 times of conversion source clock.

The period of actual A/D conversion clock should be minimally

1µs

The A/D module has three registers which are the control register

ADCM and A/D result register ADCRH and ADCRL. The AD-

CRH[7:6] is used as ADC clock source selection bits too. The

register ADCM, shown in Figure 15-4, controls the operation of

the A/D converter module. The port pins can be configured as an-

alog inputs or digital I/O.

Analog

Input

AN0~AN15

It is selected for the corresponding channel to be converted by

setting ADS[3:0]. The A/D port is set to analog input port by

ADEN and ADS[3:0] regardless of port I/O direction register.

The port deselected by ADS[3:0] operates as normal port.

0~1000pF

User Selectable

Figure 15-2 Analog Input Pin Connecting Capacitor

Enable A/D Converter

A/D Converter Cautions

A/D Input Channel Select

(1) Input range of AN0 to AN15

The input voltage of AN0 to AN15 should be within the specifi-

cation range. In particular, if a voltage above AV_DDor below

AV_SSis input (even if within the absolute maximum rating

range), the conversion value for that channel can not be indeter-

minate. The conversion values of the other channels may also be

affected.

Conversion Source Clock Select

A/D Start (ADST = 1)

(2) Noise countermeasures

In order to maintain 10-bit resolution, attention must be paid to

noise on pins AV_DDand AN0 to AN15. Since the effect increases

in proportion to the output impedance of the analog input source,

it is recommended in some cases that a capacitor be connected ex-

ternally as shown in Figure 15-2 in order to reduce noise. The ca-

pacitance is user-selectable and appropriately determined

according to the target system.

NOP

ADSF = 1

NO

(3) Pins AN0/R60 to AN15/R77

YES

The analog input pins AN0 to AN15 also function as input/output

port (PORT R6 and R7) pins. When A/D conversion is performed

with any of pins AN0 to AN15 selected, be sure not to execute a

PORT input instruction while conversion is in progress, as this

may reduce the conversion resolution.

Read ADCRH, ADCRL

Figure 15-1 A/D Converter Operation Flow

How to Use A/D Converter

Also, if digital pulses are applied to a pin adjacent to the pin in the

process of A/D conversion, the expected A/D conversion value

may not be obtainable due to coupling noise. Therefore, avoid ap-

plying pulses to pins adjacent to the pin undergoing A/D conver-

sion.

The processing of conversion is start when the start bit ADST is

set to “1”. After one cycle, it is cleared by hardware. The register

MAR. 2005 Ver 0.2

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MC80F0424/0432/0448

Preliminary

(4) AV_DDpin input impedance

parallel connection to the series resistor string between the AV_DD

pin and the AV_SSpin, and there will be a large analog supply volt-

age error.

A series resistor string of approximately 5KΩ is connected be-

tween the AV_DDpin and the AV_SSpin. Therefore, if the output

impedance of the analog power source is high, this will result in

ADEN

AV_DD

Resistor Ladder Circuit

AV_SS

8-bit ADC

R60/AN0

R61/AN1

Successive

ADC

INTERRUPT

ADCIF

Approximation

Circuit

Sample & Hold

MUX

R76/AN14

R77/AN15

ADC8

0

1

10-bit Mode

8-bit Mode

... 3 2

ADS[5:2]

9 8 ...

... 1 0

9 8 ...

ADCR (10-bit)

10-bit ADCR

0 0

1 0

ADCRH

ADCRL (8-bit)

1 0

ADC Result Register

Figure 15-3 A/D Block Diagram

76

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

R/W R/W

-

R/W R/W R/W R/W

R

0

7

6

5

4

3

2

1

ADDRESS: 0EF

INITIAL VALUE: 00-0 0001

H

ADCM

BTCL

ADEN ADCK ADS2 ADS2 ADS1 ADS0

ADST ADSF

B

A/D status bit

0: A/D conversion is in progress

1: A/D conversion is completed

A/D start bit

Setting this bit starts an A/D conversion.

After one cycle, bit is cleared to “0” by hardware.

Analog input channel select

0000: Channel 0 (AN0)

0001: Channel 1 (AN1)

0010: Channel 2 (AN2)

0011: Channel 3 (AN3)

0100: Channel 4 (AN4)

0101: Channel 5 (AN5)

0110: Channel 6 (AN6)

0111: Channel 7 (AN7)

1000: Channel 8 (AN8)

1001: Channel 9 (AN9)

1010: Channel 10 (AN10)

1011: Channel 11 (AN11)

1100: Channel 12 (AN12)

1101: Channel 13 (AN13)

1110: Channel 14 (AN14)

1111: Channel 15 (AN15)

A/D converter Clock Source Divide Ratio Selection bit

0: Clock Source f ÷ 4

PS

1: Clock Source f ÷ 8

PS

A/D converter Enable bit

0: A/D converter module turn off and current is not flow.

1: Enable A/D converter

W

7

W

6

R

1

R

0

W

5

4

-

3

2

-

ADDRESS: 0F0

INITIAL VALUE: 010- ----

H

ADCRH

BTCL

-

PSSEL0

PSSEL1

ADC8

B

A/D Conversion High Data (for 10-bit mode)

ADC 8-bit Mode select bit

0: 10-bit Mode

1: 8-bit Mode

A/D Conversion Clock (f ) Source Selection

PS

00: f

01: f

10: f

11: f

XIN

÷ 2

÷ 4

÷ 8

R

5

R

4

R

3

R

2

R

1

R

0

R

7

R

6

ADDRESS: 0F1

INITIAL VALUE: Undefined

BTCL

H

ADCRL

A/D Conversion Low Data

Figure 15-4 A/D Converter Control & Result Register

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Preliminary

16. SERIAL INPUT/OUTPUT (SIO)

The serial Input/Output is used to transmit/receive 8-bit data se-

rially. The Serial Input/Output(SIO) module is a serial interface

useful for communicating with other peripheral of microcontrol-

ler devices. These peripheral devices may be serial EEPROMs,

shift registers, display drivers, A/D converters, etc. This SIO is 8-

bit clock synchronous type and consists of serial I/O data register,

serial I/O mode register, clock selection circuit, octal counter and

control circuit as illustrated in Figure 16-1. The SO pin is de-

signed to input and output. So the Serial I/O(SIO) can be operated

with minimum two pin. Pin R42/SCK, R43/SI, and R44/SO pins

are controlled by the Serial Mode Register. The contents of the

Serial I/O data register can be written into or read out by software.

The data in the Serial Data Register can be shifted synchronously

with the transfer clock signal.

SIOST

SIOSF

clear

SCK[1:0]

POL

Start

Complete

÷ 4

overflow

00

X_INPIN

SIO

CONTROL

CIRCUIT

÷ 16

“0”

“1”

01

Clock

Timer0

Overflow

Octal

Counter

(3-bit)

10

SIOIF

Clock

11

Serial communication

Interrupt

“11”

MUX

SCK PIN

not “11”

SCK[1:0]

IOSW

SM0

SOUT

SO PIN

SI PIN

IOSW

1

0

Input shift register

Shift

SIOR

Internal Bus

Figure 16-1 SIO Block Diagram

78

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Serial I/O Mode Register(SIOM) controls serial I/O function. Ac-

cording to SCK1 and SCK0, the internal clock or external clock

can be selected.

Serial I/O Data Register(SIOR) is an 8-bit shift register. First

LSB is send or is received.

R/W R/W

R/W R/W R/W R/W R/W

R

7

6

5

4

3

2

1

0

ADDRESS: 0E2

INITIAL VALUE: 0000 0001

H

SIOM

BTCL

POL IOSW SM1 SM0 SCK1 SCK0

SIOST SIOSF

B

Serial transmission status bit

0: Serial transmission is in progress

1: Serial transmission is completed

Serial transmission start bit

Setting this bit starts an Serial transmission.

After one cycle, bit is cleared to “0” by hardware.

Serial transmission Clock selection

00: f

01: f

÷ 4

÷ 16

XIN

10: TMR0OV(Timer0 Overflow)

11: External Clock

Serial transmission Operation Mode

00: Normal Port(R42,R43,R44)

01: Sending Mode(SCK,R43,SO)

10: Receiving Mode(SCK,SI,R44)

11: Sending & Receiving Mode(SCK,SI,SO)

Serial Input Pin Selection bit

0: SI Pin Selection

1: SO Pin Selection

Serial Clock Polarity Selection bit

0: Data Transmission at Falling Edge

Received Data Latch at Rising Edge

1: Data Transmission at Rising Edge

Received Data Latch at Falling Edge

R/W R/W R/W R/W R/W R/W R/W

R/W

7

6

5

4

3

2

1

0

ADDRESS: 0E3

INITIAL VALUE: Undefined

H

BTCL

SIOR

Sending Data at Sending Mode

Receiving Data at Receiving Mode

Figure 16-2 SIO Control Register

16.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of SIOM)

to “1”. After one cycle of SCK, SIOST is cleared automatically

to “0”. At the default state of POL bit clear, the serial output data

from 8-bit shift register is output at falling edge of SCLK, and in-

put data is latched at rising edge of SCLK pin (Refer to Figure 16-

3). When transmission clock is counted 8 times, serial I/O counter

is cleared as ‘0”. Transmission clock is halted in “H” state and se-

rial I/O interrupt(SIOIF) occurred.

MAR. 2005 Ver 0.2

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Preliminary

SIOST

SCK [R42]

(POL=0)

D0

D1

D2

D3

D4

D5

D6

D7

SO [P44]

SI [R43]

(IOSW=0)

D0

D1

D2

D3

D4

D5

D6

D7

IOSWIN [P44]

(IOSW=1)

D0

D1

D2

D3

D4

D5

D6

D7

SIOSF

(SIO Status)

SIOIF

(SIO Int. Req)

Figure 16-3 Serial I/O Timing Diagram at POL=0

SIOST

SCK [R42]

(POL=1)

D0

D1

D2

D3

D4

D5

D6

D7

SO [R44]

SI [R43]

D0

D1

D2

D3

D4

D5

D6

D7

(IOSW=0)

D0

D1

D2

D3

D4

D5

IOSWIN [R44]

(IOSW=1)

SIOSF

(SIO Status)

SIOIF

(SIO Int. Req)

Figure 16-4 Serial I/O Timing Diagram at POL=1

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MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

16.2 The method of Serial I/O

1. Select transmission/receiving mode.

LDM

NOP

LDM

SIOR,#0AAh

;set tx data

2. In case of sending mode, write data to be send to SIOR.

3. Set SIOST to “1” to start serial transmission.

SIOM,#0011_1100b ;set SIO mode

SIOM,#0011_1110b ;SIO Start

4. The SIO interrupt is generated at the completion of SIO

and SIOIF is set to “1”. In SIO interrupt service routine,

correct transmission should be tested.

Note: When external clock is used, the frequency should

be less than 1MHz and recommended duty is 50%. If both

transmission mode is selected and transmission is per-

formed simultaneously, error will be made.

5. In case of receiving mode, the received data is acquired

by reading the SIOR.

16.3 The Method to Test Correct Transmission

Serial I/O Interrupt

Service Routine

0

SIOSF

1

Abnormal

SIOE = 0

Write SIOM

0

SIOIF

1

Overrun Error

Normal Operation

- SIOE: Interrupt Enable Register High IENH(Bit3)

- SIOIF: Interrupt Request Flag Register High IRQH(Bit3)

Figure 16-5 Serial IO Method to Test Transmission

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Preliminary

17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

17.1 UART Serial Interface Functions

The Universal Asynchronous Receiver/Transmitter(UART) en-

ables full-duplex operation wherein one byte of data after the start

bit is transmitted and received. The on-chip baud rate generator

dedicated to UART enables communications using a wide range

of selectable baud rates. In addition, a baud rate can also be de-

fined by dividing clocks input to the ACLK pin.

In operation of UART0 and UART1, their operations are same as

UART0 and UART1

Note: The UART1 control register ASIMR1,ASISR1,

BRGCR1, RXR1 and TXR1 are located at EE6H ~ EE9H

address. These address must be controlled (read and writ-

ten) by absolute addressing manipulation instruction.

The UART driver consists of RXR, TXR, ASIMR, ASISR and

BRGCR register. Clock asynchronous serial I/O mode (UART)

can be selected by ASIMR register. Figure 17-1 shows a block di-

agram of the UART driver.

Internal Data Bus

Receive Buffer Register

(RXR / RXR1)

RXE

RxD0 PIN /

RxD1 PIN

Receive Shift Register

(RXSR)

Transmit Shift Register

(TXR / TXR1)

2

1

0

(ASISR /

ASISR1)

PE

FE OVE

TXE

TxD0 PIN /

TxD1 PIN

Transmit Controller

(Parity Addition)

IFTX0 / IFTX1

UART0IF /

UART1IF

Receive Controller

(Parity Check)

IFRX0 / IFRX1

(UART0/1 interrupt)

ACLK0 PIN /

ACLK1 PIN

Baud Rate

Generator

f

/2 ~ f /128

XIN

Figure 17-1 UART Block Diagram

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MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

RECEIVE

RXE

ACLK0 PIN /

ACLK1 PIN

5-bit counter

MUX

f

/2 ~ f /128

XIN

match

1/2

(Divider)

Tx_Clock

Decoder

match

1/2

Rx_Clock

(Divider)

-

TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0

(BRGCR / BRGCR1)

5-bit counter

TXE

Internal Data Bus

SEND

Figure 17-2 Baud Rate Generator Block Diagram

17.2 Serial Interface Configuration

The UART interface consists of the following hardware.

same address is assigned to TXR and the receive buffer

register (RXR). A read operation reads values from RXR.

Item

Configuration

Receive buffer register (RXR)

Transmit shift register (TXR)

Receive buffer register (RXR)

Receive shift register

Register

This register is used to hold receive data. When one byte of data

is received, one byte of new receive data is transferred from the

receive shift register (RXSR). When the data length is set as 7

bits, receive data is sent to bits 0 to 6 of RXR. In this case, the

MSB of RXR always becomes 0.

Serial interface mode register (ASIMR)

Serial interface status register (ASISR)

Baudrate generator control register (BRGCR)

Control

register

RXR can be read by an 8 bit memory manipulation instruction. It

cannot be written. The RESET input sets RXR to 00H.

Table 17-1 Serial Interface Configuration

Transmit shift register (TXR)

Note: The same address is assigned to RXR and the

transmit shift register (TXR). During a write operation, val-

ues are written to TXR.

This is the register for setting transmit data. Data written to TXR

is transmitted as serial data. When the data length is set as 7 bit,

bit 0 to 6 of the data written to TX are transferred as transmit data.

Writing data to TXR starts the transmit operation.

TXR can be written by an 8 bit memory manipulation instruction.

It cannot be read. The RESET input sets TXR to 0FFH.

Receive shift register

This register converts serial data input via the RxD pin to paral-

leled data. When one byte of data is received at this register can-

not be manipulated directly by a program.

Note: Do not write to TXR during a transmit operation. The

MAR. 2005 Ver 0.2

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Preliminary

Asynchronous serial interface mode register

(ASIMR)

Asynchronous serial interface status register

(ASISR)

This is an 8 bit register that controls UART serial transfer opera-

tion. ASIMR is set by a 1 bit or 8 bit memory manipulation in-

truction. The RESET input sets ASIMR to 0000_-00-B. Table 17-

2 shows the format of ASIMR.

When a receive error occurs during UART mode, this register in-

dicates the type of error. ASISR can be read by an 8 bit memory

manipulation instruction. The RESET input sets ASISR to -----

000B. Table 17-3 shows the format of ASISR.

Address : 0E6H / EE6H

Reset value : 0000-00-B

Address : 0E7H / EE7H

Reset value : -----000B

ASIMR /

ASIMR1

TXE RXE PS1 PS0

-

SL ISRM

ASISR /

ASISR1

-

PE

FE OVE

RXE Operation Mode RxD Pin Func.

TxD Pin Func.

TXE

0

1

Operation stop Port function(R46)

PE

Parity Error Flag

0

UART mode

Serial function

(RxD0)

Port

function(R47)

0

1

No parity error

(Receive only)

Parity error (Transmit data parity not matched)

0

1

UART mode

(Transmit only)

Port function

(R46)

1

Serial function

(TxD0)

FE

0

Frame Error Flag

UART mode

( RX & TX )

Serial function

(RxD0)

No Frame error

Note1

1

Framing error

(stop bit not detected)

PS1 PS0

Parity Bit Specification

No parity

0

1

OVE

Overrun Error Flag

Zero parity always added during transmission.

No parity detection during reception (parity errors do not

occur)

Odd parity

Even parity

0

1

No overrun error

Note2

Overrun error

(Next receive operation was completed before data was read

from receive buffer register (RXR)

1

0

1

Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in

ASIMR, stop bit detection during a recive operation only applies

to a stop bit length of 1bit.

SL

0

Stop Bit Length for Specification for Transmit Data

1 bit

2 bit

2. Be sure to read the contents of the receive buffer register(RXR)

when an overrun error has occurred.

1

Until the contents of RXR are read, futher overrun errors will

occur when receiving data.

ISRM

Receive interrupt request is issued when an error occurs

0

1

Receive Completion Interrupt Control When Error Occurs

Table 17-3 Asynchronous Serial Interface Status

Register (ASISR) Format

Receive completion interrupt request is not issued when an error

occurs

Baud rate generator control register (BRGCR)

Table 17-2 Asynchronous Serial Interface Mode

register (ASIMR) format

This register sets the serial clock for serial interface. BRGCR is

set by an 8 bit memory manipulation instruction. The RESET in-

put sets BRGCR to -001_0000B.

Note: Do not switch the operation mode until the current

Table 17-4 shows the format of BRGCR.

serial transmit/receive operation has stopped.

84

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

Address : 0E8H / EE8H

Reset value : -0010000B

BRGCR /

BRGCR1

-

TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0

TPS2 TPS1

Source Clock Selection for 5 Bit count

n

k

TPS0

Input Clock Selection

MDL3 MDL2 MDL1

MDL0

0

1

0

1

0

1

0

ACLK0 / ACLK1

0

f

/ 16

/ 17

/ 18

/ 19

/ 20

/ 21

/ 22

/ 23

/ 24

/ 25

0

1

0

1

SCK

f

/ 2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

XIN

2

/ 4

2

3

/ 8

3

4

/ 16

/ 32

/ 64

/ 128

4

5

6

7

0

1

0

1

0

1

0

1

0

1

5

6

7

8

9

Writing to BRGCR/BRGXR1 during a communication operation may

cause abnormal output from the baud rate generator and

disable further communication operations. Therefore, do not

write to BRGCR/BRGCR1 during a communication operation.

Caution

f

/ 26

/ 27

1

0

1

0

1

0

1

0

1

0

1

10

11

12

13

SCK

f

/ 28

/ 29

/ 30

SCK

Remarks 1. f

: Source clock for 5 bit counter

SCK

14

-

2. n : Value set via TPS0 to TPS2 ( 0 ≤ n ≤ 7 )

3. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 )

Setting prohibited

Table 17-4 Baud Rate Generator Control Register (BRGCR / BRGCR1) Format

17.3 Communication operation

1 data frame

TxD

RxD

Start

Parity

Stop

D0

D1

D2

D3

D4

D5

D6

D7

character bits

TX

(In case of 1 stop bit)

INTERRUPT

RX

INTERRUPT

1 data frame consists of following bits.

- Start bit : 1 bit

- Character bits : 8 bits

- Parity bit : Even parity, Odd parity, Zero parity, No parity

- Stop bit(s) : 1 bit or 2 bits

Figure 17-3 UART data format and interrupt timing diagram

The transmit operation is enabled when bit 7 (TXE) of the asyn-

chronous serial interface mode register (ASIMR/ASIMR1) is set

to 1. The transmit operation is started when transmit data is writ-

ten to the transmit shift register (TXR). The timing of the transmit

completion interrupt request is shown in Figure 17-3.

chronous serial interface mode register (ASIMR/ASIMR1) is set

to 1, and input via the RxD0 pin is sampled. The serial clock spec-

ified by ASIMR/ASIMR1 is used to sample the RxD0/RxD1 pin.

Once reception of one data frame is completed, a receive comple-

tion interrupt request (UART0IF/UART1IF) occurs. Even if an

error has occurred, the receive data in which the error occurred is

The receive operation is enabled when bit 6 (RXE) of the asyn-

MAR. 2005 Ver 0.2

85

MC80F0424/0432/0448

Preliminary

still transferred to RXR. When bit 1 (ISRM) of

ASIMR(ASIMR1) is cleared to 0 upon occurrence of an error, in-

terrupt by Rx occurs. When ISRM bit is set to 1, interrupt by Rx

does not occur in case of error occurrence. Figure 17-3 shows the

timing of the asynchronous serial interface receive completion in-

terrupt request.

17.4 Relationship between main clock and baud rate

n+1

The transmit/receive clock that is used to generate the baud rate

is obtained by dividing the main system clock or ACLK0/ACLK1

pin clock. The baud rate generated from the main system clock or

ACLK0/ACLK1 pin clock is determined according to the follow-

ing formula. If the high 4 bits of BRGCR/BRGCR1 is 0, ACLK0/

ACLK1 pin clock is used for source clock of baud rate generator.

Baud Rate = f

/ ( 2 (k+16) )

XIN

- f_XIN: Main system clock oscillation frequency

When ACLK0/ACLK1 is selected as the source clock of

the 5-bit counter, substitute the input clock frequency to

ACLK0/ACLK1 pin clock for in the above expression.

- n : Value set via TPS0 to TPS2 (0 ≤ n ≤ 7)

- k : Value set via MDL0 to MDL3 (0 ≤ k ≤ 14)

f

=12M

f

=11.0592M

ERR

f

=10.0M

f

=8.0M

f

=6.0M

f

=5.0M

f

=4.0M

XIN

Baud Rate

(bps)

ERR

(%)

ERR

(%)

ERR

(%)

ERR

(%)

ERR

(%)

ERR

(%)

BRGCR

(%)

600

1200

-

7AH

6AH

5AH

4AH

3AH

2AH

20H

1AH

11H

-

0.16

0.00

0.16

2.12

-

7AH

6AH

5AH

4AH

3AH

30H

2AH

21H

1AH

11H

0.16

0.00

0.16

2.11

0.16

2.12

74H

64H

54H

44H

34H

28H

24H

1AH

14H

-

2.34

0.00

2.34

0.16

2.34

-

70H

60H

50H

40H

30H

24H

20H

16H

10H

-

1.73

0.00

1.73

1.36

1.73

-

2400

74H

64H

54H

44H

38H

34H

2AH

24H

1AH

2.34

0.00

2.34

0.16

2.34

0.16

72H

62H

52H

42H

36H

32H

28H

22H

18H

0.00

0.53

0.00

70H

60H

50H

40H

34H

30H

26H

20H

16H

1.73

0.00

1.73

1.35

1.73

1.36

4800

9600

19200

31250

38400

57600

76800

115200

-

Table 17-5 Relationship between main clock and Baud Rate

86

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

17.5 Communication operation

The transmit operation is enabled when bit 7 (TXE) of the asyn-

chronous serial interface mode register (ASIMR/ASIMR1) is set

to 1. The transmit operation is started when transmit data is writ-

ten to the transmit shift register (TXR/TXR1). The timing of the

transmit completion interrupt request is shown in Figure 17-3.

The receive operation is enabled when bit 6 (RXE) of the asyn-

chronous serial interface mode register (ASIMR/ASIMR1) is set

to 1, and input via the RxD0/RxD1 pin is sampled. The serial

clock specified by ASIMR/ASIMR1 is used to sample the RxD0/

RxD1 pin. Once reception of one data frame is completed, a re-

ceive completion interrupt request (UART0IF/UART1IF) oc-

curs. Even if an error has occurred, the receive data in which the

error occurred is still transferred to RXR/RXR1. When ASIMR

bit 1 (ISRM) is cleared to 0 upon occurrence of an error, UART0/

UART1 interrupt occurs. When ISRM bit is set to 1, UART0/

UART1 interrupt does not occur in case of error occurrence. Fig-

ure 17-3 shows the timing of the asynchronous serial interface re-

ceive completion interrupt request.

in Figure 17-1.

UART0(UART1)

Interrupt Request

=0

IFTX0(IFTX1)

=1

TX0(TX1) Interrupt

Routine

Clear IFTX0(IFTX1)

=0

IFRX0(IFRX1)

=1

In case of using interrupts of UART0 Tx and UART0 Rx togeth-

er, it is necessary to check IFR in interrupt service routine to find

out which interrupt is occurred, because the UART0 Tx and

UART0 Rx is shared with interrupt vector address.

RX0(RX1) Interrupt

Routine

Clear IFRX0(IFRX1)

RETI

In case of using interrupts of UART1 Tx and UART1 Rx togeth-

er, it is necessary to check IFR in interrupt service routine to find

out which interrupt is occurred, because the UART1 Tx and

UART1 Rx is shared with interrupt vector address.

These flag bits must be cleared by software after reading this reg-

ister. These flag bits must be cleared by software after reading

this register. Each processing step is determined by IFR as shown

Figure 17-1 Shared Interrupt Vector of UART

MAR. 2005 Ver 0.2

87

MC80F0424/0432/0448

Preliminary

18. BUZZER FUNCTION

The buzzer driver block consists of 6-bit binary counter, buzzer

register BUZR, and clock source selector. It generates square-

wave which has very wide range frequency (488Hz ~ 250kHz at

The bit 0 to 5 of BUZR determines output frequency for buzzer

driving.

Equation of frequency calculation is shown below.

f

_XIN= 4MHz) by user software.

f

XIN

A 50% duty pulse can be output to R13/BUZO pin to use for pi-

ezo-electric buzzer drive. Pin R13 is assigned for output port of

Buzzer driver by setting the bit 2 of PSR1(address 0F9_H) to “1”.

For PSR1 register, refer to Figure 10-3.

f

= ---------------------------------------------------------------------------

BUZ

2 × DivideRatio × (BUR + 1)

f

: Buzzer frequency

BUZ

: Oscillator frequency

XIN

Example: 5kHz output at 4MHz.

Divide Ratio: Prescaler divide ratio by BUCK[1:0]

BUR: Lower 6-bit value of BUZR. Buzzer period value.

LDM

BUZR,#0011_0001B

PSR1,#XXXX_X1XXB

The frequency of output signal is controlled by the buzzer control

register BUZR. The bit 0 to bit 5 of BUZR determine output fre-

quency for buzzer driving.

X means don’t care

R13 port data

÷ 8

6-BIT BINARY

COUNTER

00

÷ 16

MUX

01

X_INPIN

÷ 32

0

10

R13/BUZO PIN

F/F

1

÷ 64

11

Comparator

MUX

2

Compare data

BUZO

6

Port selection register 1

PSR1

[0F9 ]

BUR

H

[0E0 ]

H

Internal bus line

Figure 18-1 Block Diagram of Buzzer Driver

ADDRESS: 0E0

H

Reset VALUE: 0FF

H

W

BUCK1 BUCK0

BUZR

BUR[5:0]

Buzzer Period Data

Source clock select

00: f

01: f

10: f

11: f

÷ 8

XIN

÷ 16

÷ 32

÷ 64

Figure 18-2 Buzzer Register

88

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

The 6-bit counter is cleared and starts the counting by writing sig-

nal at BUZR register. It is incremental from 00_Huntil it matches

6-bit BUR value.

When main-frequency is 4MHz, buzzer frequency is shown as

below Table 18-1.

BUR[7:6]

BUR

BUR[7:6]

BUR

[5:0]

00

01

10

11

00

01

10

11

00

01

02

03

04

05

06

07

250.000

125.000

83.333

62.500

50.000

41.667

35.714

31.250

125.000

62.500

41.667

31.250

25.000

20.833

17.857

15.625

62.500

31.250

20.833

15.625

12.500

10.417

8.929

31.250

15.625

10.417

7.813

6.250

5.208

4.464

3.906

20

21

22

23

24

25

26

27

7.576

7.353

7.143

6.944

6.757

6.579

6.410

6.250

3.788

3.676

3.571

3.472

3.378

3.289

3.205

3.125

1.894

1.838

1.786

1.736

1.689

1.645

1.603

1.563

0.947

0.919

0.893

0.868

0.845

0.822

0.801

0.781

7.813

08

09

0A

0B

0C

0D

0E

0F

27.778

25.000

22.727

20.833

19.231

17.857

16.667

15.625

13.889

12.500

11.364

10.417

9.615

8.929

8.333

7.813

6.944

6.250

5.682

5.208

4.808

4.464

4.167

3.906

3.472

3.125

2.841

2.604

2.404

2.232

2.083

1.953

28

29

2A

2B

2C

2D

2E

2F

6.098

5.952

5.814

5.682

5.556

5.435

5.319

5.208

3.049

2.976

2.907

2.841

2.778

2.717

2.660

2.604

1.524

1.488

1.453

1.420

1.389

1.359

1.330

1.302

0.762

0.744

0.727

0.710

0.694

0.679

0.665

0.651

10

11

12

13

14

15

16

17

14.706

13.889

13.158

12.500

11.905

11.364

10.870

10.417

7.353

6.944

6.579

6.250

5.952

5.682

5.435

5.208

3.676

3.472

3.289

3.125

2.976

2.841

2.717

2.604

1.838

1.736

1.645

1.563

1.488

1.420

1.359

1.302

30

31

32

33

34

35

36

37

5.102

5.000

4.902

4.808

4.717

4.630

4.545

4.464

2.551

2.500

2.451

2.404

2.358

2.315

2.273

2.232

1.276

1.250

1.225

1.202

1.179

1.157

1.136

1.116

0.638

0.625

0.613

0.601

0.590

0.579

0.568

0.558

18

19

1A

1B

1C

1D

1E

1F

10.000

9.615

9.259

8.929

8.621

8.333

8.065

7.813

5.000

4.808

4.630

4.464

4.310

4.167

4.032

3.906

2.500

2.404

2.315

2.232

2.155

2.083

2.016

1.953

1.250

1.202

1.157

1.116

1.078

1.042

1.008

0.977

38

39

3A

3B

3C

3D

3E

3F

4.386

4.310

4.237

4.167

4.098

4.032

3.968

3.907

2.193

2.155

2.119

2.083

2.049

2.016

1.984

1.953

1.096

1.078

1.059

1.042

1.025

1.008

0.992

0.977

0.548

0.539

0.530

0.521

0.512

0.504

0.496

0.488

Table 18-1 buzzer frequency (kHz unit)

MAR. 2005 Ver 0.2

89

MC80F0424/0432/0448

19. INTERRUPTS

Preliminary

The MC80F0424/0432/0448 interrupt circuits consist of Interrupt

enable register (IENH, IENL), Interrupt request flags of IRQH,

IRQL, Priority circuit, and Master enable flag (“I” flag of PSW).

Fifteen interrupt sources are provided. The configuration of inter-

rupt circuit is shown in Figure 19-1 and interrupt priority is

shown in Table 19-1.

T2IF, T3IF and T4IF which is set by a match in their respective

timer/counter register.

The Basic Interval Timer Interrupt is generated by BITIF which

is set by an overflow in the timer register.

The AD converter Interrupt is generated by ADCIF which is set

by finishing the analog to digital conversion.

The External Interrupts INT0 ~ INT3 each can be transition-acti-

vated (1-to-0 or 0-to-1 transition) by selection IEDS register.

The flags that actually generate these interrupts are bit INT0IF,

INT1IF, INT2IF and INT3IF in register IRQH. When an external

interrupt is generated, the generated flag is cleared by the hard-

ware when the service routine is vectored to only if the interrupt

was transition-activated.

The Watchdog timer and Watch Timer Interrupt is generated by

WDTIF and WTIF which is set by a match in Watchdog timer

register or Watch timer register. The IFR(Interrupt Flag Register)

is used for discrimination of the interrupt source among these two

Watchdog timer and Watch Timer Interrupt.

The Basic Interval Timer Interrupt is generated by BITIF which

is set by a overflow in the timer counter register.

The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF,

Internal bus line

[0EA ]

H

I-flag is in PSW, it is cleared by “DI”, set by

Interrupt Enable

Register (Higher byte)

“EI” instruction. When it goes interrupt service,

I-flag is cleared by hardware, thus any other

IENH

IRQH

[0EC ]

H

interrupt are inhibited. When interrupt service is

completed by “RETI” instruction, I-flag is set to

“1” by hardware.

INT0IF

INT1IF

INT2IF

INT3IF

UART0IF

UART1IF

SIOIF

INT0

INT1

INT2

INT3

Release STOP/SLEEP

UART0 Tx/Rx

UART1 Tx/Rxt

To CPU

Serial

Communication

I-flag

Timer 0

T0IF

Interrupt Master

Enable Flag

IRQL

[0ED ]

H

Timer 1

Timer 2

Timer 3

T1IF

T2IF

Interrupt

Vector

Address

Generator

T3IF

Timer 3

T4IF

A/D Converter

Watchdog Timer

Watch Timer

ADCIF

WDTIF

WTIF

BITIF

BIT

Interrupt Enable

Register (Lower byte)

IENL

[0EB ]

H

Internal bus line

Figure 19-1 Block Diagram of Interrupt

90

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

The UART receive/transmit interrupt is generated by UART0IF

and UART1IF which are set by completion of UART data recep-

tion or transmission.

Reset/Interrupt

Hardware Reset

Symbol

Priority

The SIO interrupt is generated by SIOIF which is set by comple-

tion of SIO data reception or transmission.

RESET

INT0

INT1

INT2

INT3

UART0

UART1

SIO

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

ADC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

UART0 Rx/Tx Interrupt

UART1 Rx/Tx Interrupt

Serial Input/Output

Timer/Counter 0

Timer/Counter 1

Timer/Counter 2

Timer/Counter 3

Timer/Counter 4

The interrupts are controlled by the interrupt master enable flag

I-flag (bit 2 of PSW on Figure 8-3), the interrupt enable register

(IENH, IENL), and the interrupt request flags (in IRQH and

IRQL) except Power-on reset and software BRK interrupt. The

Table 19-1 shows the Interrupt priority.

Vector addresses are shown in Figure 8-6. Interrupt enable regis-

ters are shown in Figure 19-2. These registers are composed of in-

terrupt enable flags of each interrupt source and these flags

determines whether an interrupt will be accepted or not. When

enable flag is “0”, a corresponding interrupt source is prohibited.

Note that PSW contains also a master enable bit, I-flag, which

disables all interrupts at once.

ADC Interrupt

Watchdog/Watch Timer

Basic Interval Timer

WDT_WT

BIT

Table 19-1 Interrupt Priority

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 0EA

INITIAL VALUE: 0000 0000

H

UART0E UART1E

INT0E INT1E INT2E INT3E

SIOE T0E

IENH

B

MSB

LSB

Timer/Counter 0 interrupt enable flag

Serial Communication interrupt enable flag

UART1 Tx/Rx interrupt enable flag

UART0 Tx/Rx interrupt enable flag

External interrupt 0 enable flag

External interrupt 1 enable flag

External interrupt 2 enable flag

External interrupt 3 enable flag

R/W R/W

T1E

MSB

R/W R/W

ADDRESS: 0EB

INITIAL VALUE: 0000 0000

H

T2E T3E T4E ADCE WDTE WTE BITE

LSB

IENL

B

Basic Interval Timer interrupt enable flag

Watch timer interrupt enable flag

Watchdog timer interrupt enable flag

A/D Converter interrupt enable flag

Timer/Counter 4 interrupt enable flag

Timer/Counter 3 interrupt enable flag

Timer/Counter 2 interrupt enable flag

Timer/Counter 1 interrupt enable flag

Figure 19-2 Interrupt Enable Flag Register

MAR. 2005 Ver 0.2

91

MC80F0424/0432/0448

Preliminary

R/W R/W

R/W R/W R/W R/W R/W R/W

ADDRESS: 0EC

INITIAL VALUE: 0000 0000

H

UART0IF UART1IF

INT0IF INT1IF INT2IF INT3IF

MSB

SIOIF

T0IF

LSB

IRQH

B

Timer/Counter 0 interrupt request flag

Serial Communication interrupt request flag

UART1Tx/Rx interrupt request flag

UART0 Tx/Rx interrupt request flag

External interrupt 3 request flag

External interrupt 2 request flag

External interrupt 1 request flag

External interrupt 0 request flag

R/W R/W

ADDRESS: 0ED

INITIAL VALUE: 0000 0000

H

T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF

LSB

IRQL

B

MSB

Basic Interval Timer interrupt request flag

Watch timer interrupt request flag

Watchdog timer interrupt request flag

A/D Converter interrupt request flag

Timer/Counter 4 interrupt request flag

Timer/Counter 3 interrupt request flag

Timer/Counter 2 interrupt request flag

Timer/Counter 1 interrupt request flag

R/W R/W

ADDRESS: 0DF

INITIAL VALUE: --00 0000

H

-

IFRX0 IFTX0 IFRX1 IFTX1

IFWT IFWDT

IFR

B

LSB

MSB

NOTE1

WDT interrupt occurred flag

NOTE1

WT interrupt occurred flag

NOTE2

UART1 Tx interrupt occurred flag

UART1 Rx interrupt occurred flag

NOTE3

UART0 Tx interrupt occurred flag

UART0 Rx interrupt occurred flag

NOTE3

NOTE1 :

In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in

interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch

timer is shared with interrupt vector address. These flag bits must be cleared by software after read-

ing this register.

NOTE2 :

NOTE3 :

In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt

service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared

with interrupt vector address. These flag bits must be cleared by software after reading this register.

In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt

service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared

with interrupt vector address. These flag bits must be cleared by software after reading this register.

Figure 19-3 Interrupt Request Flag Register

19.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the

interrupt latch is cleared to “0” by a reset or an instruction. Inter-

rupt acceptance sequence requires 8 cycles of f_XIN(2µs at f_X-

_IN=4MHz) after the completion of the current instruction

execution. The interrupt service task is terminated upon execu-

tion of an interrupt return instruction [RETI].

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19.1.1 Interrupt acceptance

and the program status word are saved (pushed) onto the

stack area. The stack pointer decreases 3 times.

1. The interrupt master enable flag (I-flag) is cleared to

“0” to temporarily disable the acceptance of any follow-

ing maskable interrupts. When a non-maskable inter-

rupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

4. The entry address of the interrupt service program is

read from the vector table address and the entry address

is loaded to the program counter.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

2. Interrupt request flag for the interrupt source accepted is

cleared to “0”.

3. The contents of the program counter (return address)

System clock

Instruction Fetch

SP-2

PSW

V.L.

V.H.

New PC

OP code

SP

SP-1

PC

Address Bus

Data Bus

Not used

PCH

PCL

V.L.

ADL

ADH

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.

ADL and ADH are start addresses of interrupt service routine as vector contents.

Figure 19-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

19.1.2 Saving/Restoring General-purpose Regis-

Basic Interval Timer

Vector Table Address

ter

Entry Address

During interrupt acceptance processing, the program counter and

the program status word are automatically saved on the stack, but

accumulator and other registers are not saved itself. These regis-

ters are saved by the software if necessary. Also, when multiple

interrupt services are nested, it is necessary to avoid using the

same data memory area for saving registers.

012

0FFE0

0FFE1

H

0E

H

0E312

0E313

H

0E3

H

2E

H

Correspondence between vector table address for BIT interrupt

and the entry address of the interrupt service program.

The following method is used to save/restore the general-purpose

registers.

Example: Register save using push and pop instructions

A interrupt request is not accepted until the I-flag is set to “1”

even if a requested interrupt has higher priority than that of the

current interrupt being serviced.

INTxx: PUSH

PUSH

A

X

Y

;SAVE ACC.

;SAVE X REG.

;SAVE Y REG.

PUSH

When nested interrupt service is required, the I-flag should be set

to “1” by “EI” instruction in the interrupt service program. In this

case, acceptable interrupt sources are selectively enabled by the

individual interrupt enable flags.

interrupt processing

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Preliminary

POP

RETI

Y

X

A

;RESTORE Y REG.

;RESTORE X REG.

;RESTORE ACC.

;RETURN

main task

acceptance of

interrupt

service task

saving

registers

General-purpose register save/restore using push and pop instruc-

tions;

restoring

registers

interrupt return

19.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has

the lowest priority order.

Interrupt vector address of BRK is shared with the vector of

TCALL 0 (Refer to Program Memory Section). When BRK inter-

rupt is generated, B-flag of PSW is set to distinguish BRK from

TCALL 0.

=0

B-FLAG

=1

BRK

INTERRUPT

ROUTINE

BRK or

TCALL0

Each processing step is determined by B-flag as shown in Figure

19-5.

TCALL0

ROUTINE

RETI

RET

Figure 19-5 Execution of BRK/TCALL0

19.3 Shared Interrupt Vector

In case of using interrupts of Watchdog Timer and Watch Timer

together, it is necessary to check IFR in interrupt service routine

to find out which interrupt is occurred, because the Watchdog

timer and Watch timer is shared with interrupt vector address.

These flag bits must be cleared by software after reading this reg-

ister.

UART0 Rx is shared with interrupt vector address. These flag

bits must be cleared by software after reading this register.

In case of using interrupts of UART1 Tx and UART1 Rx togeth-

er, it is necessary to check IFR in interrupt service routine to find

out which interrupt is occurred, because the UART1 Tx and

UART1 Rx is shared with interrupt vector address. These flag

bits must be cleared by software after reading this register. Each

processing step is determined by IFR as shown in Figure 19-6.

In case of using interrupts of UART0 Tx and UART0 Rx togeth-

er, it is necessary to check IFR in interrupt service routine to find

out which interrupt is occurred, because the UART0 Tx and

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UART0(UART1)

Interrupt Request

=0

WDT or WT

Interrupt Request

IFTX0(IFTX1)

=1

TX0(TX1) Interrupt

Routine

=0

IFWDT

=1

IFWT

=1

Clear IFTX0(IFTX1)

WDT Interrupt

Routine

WT Interrupt

Routine

=0

IFRX0(IFRX1)

=1

Clear IFWDT

Clear IFWT

RX0(RX1) Interrupt

Routine

RETI

Clear IFRX0(IFRX1)

RETI

Figure 19-6 Software Flowchart of Shared Interrupt Vector

19.4 Multi Interrupt

If two interrupt requests of different priority level are received si-

multaneously, the request of higher priority level is serviced. If

interrupt requests of of equal priority level are received at the

same time simultaneously, an internal polling sequence deter-

mines by hardware which request is serviced.

PUSH

LDM

EI

:

Y

IENH,#80H

IENL,#0

;Enable INT0 only

;Disable other int.

;Enable Interrupt

:

However, multiple processing through software for special fea-

tures is possible. Generally when an interrupt is accepted, the I-

flag is cleared to disable any further interrupt. But as user sets I-

flag in interrupt routine, some further interrupt can be serviced

even if certain interrupt is in progress. Refer to Figure 19-7.

:

LDM

POP

RETI

IENH,#0FFH ;Enable all interrupts

IENL,#0FFH

Y

X

A

Example: During Timer1 interrupt is in progress, INT0 interrupt

serviced without any suspend.

TIMER1: PUSH

PUSH

A

X

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Main Program

service

TIMER 1

service

INT0

service

enable INT0

disable other

EI

Occur

TIMER1 interrupt

Occur

INT0

enable INT0

enable other

In this example, the INT0 interrupt can be serviced without any

pending, even TIMER1 is in progress.

Because of re-setting the interrupt enable registers IENH,IENL

and master enable “EI” in the TIMER1 routine.

Figure 19-7 Execution of Multi Interrupt

19.5 External Interrupt

The external interrupt on INT0, INT1, INT2 and INT3 pins are

edge triggered depending on the edge selection register IEDS (ad-

dress 0EE_H) as shown in Figure 19-8.

INT0 pin

INT1 pin

INT0IF

The edge detection of external interrupt has three transition acti-

vated mode: rising edge, falling edge, and both edge.

INT0 INTERRUPT

INT0 ~ INT3 are multiplexed with general I/O ports (R10, R11,

R12, R50). To use as an external interrupt pin, the bit of port se-

lection register PSR0 should be set to “1” correspondingly.

INT1IF

Example: To use as an INT0 and INT2

INT1 INTERRUPT

:

INT2 pin

INT3 pin

INT2IF

;**** Set external interrupt port as pull-up state.

LDM

;

PU1,#0000_0101B

INT2 INTERRUPT

;**** Set port as an external interrupt port

LDM

;

PSR0,#0000_0101B

INT3IF

;**** Set Falling-edge Detection

LDM

:

IEDS,#0001_0001B

INT3 INTERRUPT

2

Edge selection

Register

IEDS

[0EEH]

Figure 19-8 External Interrupt Block Diagram

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twelve complete machine cycles elapse between activation of an

external interrupt request and the beginning of execution of the

first instruction of the service routine.

Response Time

The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every

machine cycle. The values are not actually polled by the circuitry

until the next machine cycle. If a request is active and conditions

are right for it to be acknowledged, a hardware subroutine call to

the requested service routine will be the next instruction to be ex-

ecuted. The DIV itself takes twelve cycles. Thus, a minimum of

Figure 19-9 shows interrupt response timings.

max. 12 f

8 f

XIN

Interrupt

goes

active

Interrupt

latched

Interrupt

processing

Interrupt

routine

Figure 19-9 Interrupt Response Timing Diagram

MSB

W

LSB

W

ADDRESS: 0EE

INITIAL VALUE: 00

H

IEDS

IED3H IED3L IED2H IED2L IBETDC1LH IED1L IED0H IED0L

INT3 INT2 INT1 INT0

H

Edge selection register

00: Reserved

01: Falling (1-to-0 transition)

10: Rising (0-to-1 transition)

11: Both (Rising & Falling)

W

ADDRESS: 0F8

INITIAL VALUE: 00

H

PSR0

PWM3O PWM1O EC1E EC0E IBNTTC3LE INT2E INT1E INT0E

MSB LSB

0: R10

H

0: R54

1: PWM3O

1: INT0

0: R11

1: INT1

0: R53

1: PWM1O

0: R12

1: INT2

0: R51

1: EC1

0: R50

1: INT3

0: R15

1: EC0

Figure 19-10 IEDS register and Port Selection Register PSR0

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Preliminary

20. OPERATION MODE

The system clock controller starts or stops the main-frequency

clock oscillator and switches between the main and sub frequency

clock. The operating mode is generally divided into the main ac-

tive mode, the sub active mode 1 and sub active mode 2, which

are controlled by System clock control register (SCMR). Figure

20-1 shows the operating mode transition diagram.

Sub Active mode

This mode is low-frequency operating mode. In this mode, the

CPU and the peripheral hardware clock are provided by low-fre-

quency clock oscillation, so power consumption can be reduced.

SLEEP mode

System clock control is performed by the system clock mode reg-

ister, SCMR. During reset, this register is initialized to “0” so that

the main-clock operating mode is selected.

In this mode, the CPU clock stops while peripherals and the os-

cillation source continues to operate normally.

STOP mode

Main Active mode

In this mode, the system operations are all stopped, holding the

internal states valid immediately before the stop at the low power

consumption level. The main oscillation source stops, but the sub

clock oscillation and watch timer by sub clock and RC-oscillated

watchdog timer don’t stop.

This mode is fast-frequency operating mode. The CPU and the

peripheral hardware are operated on the high-frequency clock. At

reset release, this mode is invoked.

Main : Oscillation

Sub : Oscillation

System Clock : Sub

Sub : Oscillation or stop

System Clock : Main

LDM SCMR, #02H

Main Active

Sub Active

Mode 1

Mode

* Note1 : Stop released by Reset,

Watch Timer, Watchdog Timer

Timer(event counter),

LDM SCMR, #01H

SIO (External clock), UART

External interrupt

* Note2 : Sleep released by

Reset, or All interrupts

* Note3 : List of instruction is

CLR1 SCMR.2 ;Main OSC ON

NOP ;for Oscillation stabilization time

LDM SCMR, #01H

* Note4 :

1) Stop mode Admission

LDM SSCR, #5AH

* Note1 / Note2

Stop / Sleep

STOP

NOP

Sub Active

Mode 2

Mode

* Note4

2) Sleep mode Admission

LDM SSCR, #0FH

Main : Stop

Sub : Oscillation

System Clock : Sub

Stop : System Clock Oscillation stop

Sleep : System Clock Oscillation run

(CPU stops, Peripherals operate)

- Sub clock cannot be stopped by STOP instruction.

Figure 20-1 Operating Mode

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20.1 Operation Mode Switching

In the Main active mode, only the high-frequency clock oscillator

is used. In the Sub active mode, the low-frequency clock oscilla-

tion is used, so the low power voltage operation or the low power

consumption operation can be enabled. Instruction execution

does not stop during the change of operation mode. In this case,

some peripheral hardware capabilities may be affected. For de-

tails, refer to the description of the relevant operation.

with the length of two or more NOP instruction. Sub active mode

can also be released by setting the RESET pin to low, which im-

mediately performs the reset operation. After reset, the

MC80F0424/0432/0448 is placed in Main active mode.

Example:

CLR1 SCMR.2 ;Turn on main-clock

NOP ;for OSC stabilization time

The following describes the switching between the Main active

mode and the Sub active mode. During reset, the system clock

mode register is initialized at the Main active mode. It must be set

to the Sub active mode for reducing the power consumption.

NOP

LDM

;for OSC stabilization time

SCMR,#01h

;Move to main active

Returning from Sub active 2 to Sub active 1

Switching from Main active to Sub active 1

First, clear SCMR.2 to switch the main system clock to the sub-

frequency clock of Sub Active mode 2.

Example:

First, write “02_H”into SCMR to switch the main system clock to

the sub-frequency clock of Sub Active mode 1.

Example:

CLR1

SCMR.2 ;Switch to sub active1

LDM

SCMR,#02_H;Switch to sub active1

Shifting from the Normal operation to the SLEEP

mode

Switching from Main active to Sub active 2

If the SLEEP mode is invoked, the external clock oscillation does

not stops but the CPU clock stops while other peripherals are op-

erate normally.

First, write “06_H”into SCMR to switch the main system clock to

the sub-frequency clock of Sub Active mode 2.

Example:

The ways of release from this mode are by setting the RESET pin

to low and all available interrupts. For more detail, See "21.

POWER SAVING OPERATION" on page 101.

LDM

SCMR,#06_H;Switch to sub active2

Returning from Sub active 1 to Main active

Shifting from the Normal operation to the STOP

mode

First, write “01_H”into SCMR to turn on the main-frequency os-

cillation. Sub active mode can also be released by setting the RE-

SET pin to low, which immediately performs the reset operation.

After reset, the MC80F0424/0432/0448 is placed in Main active

mode.

If the STOP mode is invoked, the main-frequency clock oscilla-

tion stops and the CPU clock stops and other peripherals are stop

too. But sub-frequency clock oscillation operate continuously if

enabled previously. After the STOP operation is released by re-

set, the operation mode is changed to Main active mode.

The methods of release from this mode are Reset, Watch Timer,

RC watchdog timer, Event counter, SIO(External clock), UART,

and External Interrupt.

Example:

LDM

SCMR,#01_H;Switch to main-clock

For more details, see "21. POWER SAVING OPERATION" on

page 101.

Switching from Sub active 1 to Sub active 2

First, set SCMR.2 to switch the main system clock to the sub-fre-

quency clock of Sub Active mode 2.

Example:

Note: In the STOP and SLEEP operating modes, the pow-

er consumption by the oscillator and the internal hardware

is reduced. However, the power for the pin interface (de-

pending on external circuitry and program) is not directly

associated with the low-power consumption operation. This

must be considered in system design as well as interface

circuit design.

SET1

SCMR.2 ;Switch to sub active2

Returning from Sub active 2 to Main active

First, set the SCMR.2 bit clear, and wait for a while for oscillation

stabilization time. Secondly, write “01_H”into the SCMR to turn

on the main-frequency oscillation. This time, the stabilization

(warm-up) time needs to be taken by the software delay routine

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Preliminary

Main freq. clock

(X_INpin)

Sub freq. clock

(SX_INpin)

Operation clock

Main-clock operation

Sub-clock operation

Changed to the Sub-clock

SCMR ← XXXX X010

B

Turn off main clock

SCMR.2 bit HIGH

(a) Main active mode → Sub active mode 1 → Sub active mode 2

Main freq. clock

(X_INpin)

Stabilizing Time > 20ms

Sub freq. clock

(SX_INpin)

Operation clock

Sub-clock operation

Main-clock operation

Changed to the Transition

SCMR.2 bit LOW

Changed to the Main-clock

SCMR ← XXXX X000

B

or XXXX X001

(b) Sub active mode 2 → Sub active mode 1 → Main active mode

Figure 20-2 System Clock Switching Timing

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21. POWER SAVING OPERATION

The MC80F0424/0432/0448 has two power-down modes. In

power-down mode, power consumption is reduced considerably.

For applications where power consumption is a critical factor, de-

vice provides two kinds of power saving functions, STOP mode

and SLEEP mode. Table 21-1 shows the status of each Power

Saving Mode. SLEEP mode is entered by the SSCR register to

“0Fh”., and STOP mode is entered by STOP instruction after the

SSCR register to “5Ah”.

21.1 Sleep Mode

In this mode, the internal oscillation circuits remain active and

oscillation continues and peripherals are operate normally, but

CPU stops. Movement of all peripherals is shown in Table 21-1.

SLEEP mode is entered by setting the SSCR register to “0Fh”. It

is released by Reset or interrupt. To be released by interrupt, in-

terrupt should be enabled before SLEEP mode.

W

7

W

6

W

5

W

4

W

3

W

2

W

0

1

ADDRESS: 0F5

H

SSCR

INITIAL VALUE: 0000 0000

B

Power Down Control

5A : STOP mode

H

0F : SLEEP mode

H

1. To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution.

At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released.

2. To get into SLEEP mode, SSCR must be set to 0FH.

Figure 21-1 STOP and SLEEP Control Register

When exit from SLEEP mode by reset, enough oscillation stabi-

lization time is required to normal operation. Figure 21-3 shows

the timing diagram. his guarantees that oscillator has started and

stabilized. By interrupts, exit from SLEEP mode is shown in Fig-

ure 21-2. By reset, exit from SLEEP mode is shown in Figure 21-

3.

Release the SLEEP mode

The exit from SLEEP mode is hardware reset or all interrupts.

Reset re-defines all the Control registers but does not change the

on-chip RAM. Interrupts allow both on-chip RAM and Control

registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. If I-flag =

0, the chip will resume execution starting with the instruction fol-

lowing the SLEEP instruction. It will not vector to interrupt serv-

ice routine. (refer to Figure 21-4)

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.

Oscillator

(X_INpin)

CPU

Clock

External Interrupt

SLEEP Instruction

Executed

Normal Operation

SLEEP Operation

Normal Operation

Figure 21-2 SLEEP Mode Release Timing by External Interrupt

Oscillator

(X_INpin)

CPU

Clock

RESET

Internal

RESET

SLEEP Instruction

Execution

Stabilization Time

= 65.5mS @4MHz

t

ST

Normal Operation

SLEEP Operation

Figure 21-3 Timing of SLEEP Mode Release by Reset

21.2 Stop Mode

In the Stop mode, the main oscillator, system clock and peripher-

al clock is stopped, but the sub clock oscillation and Watch Timer

by sub clock and RC-oscillated watchdog timer continue to oper-

ate. With the clock frozen, all functions are stopped, but the on-

chip RAM and Control registers are held. The port pins out the

values held by their respective port data register, port direction

registers. Oscillator stops and the systems internal operations are

all held up.

"STOP" which starts the STOP operating mode.

Note: The Stop mode is activated by execution of STOP

instruction after setting the SSCR to “5A_H”. (This register

should be written by byte operation. If this register is set by

bit manipulation instruction, for example "set1" or "clr1" in-

struction, it may be undesired operation)

• The states of the RAM, registers, and latches valid

immediately before the system is put in the STOP

state are all held.

In the Stop mode of operation, V_DDcan be reduced to minimize

power consumption. Care must be taken, however, to ensure that

V_DDis not reduced before the Stop mode is invoked, and that

V_DDis restored to its normal operating level, before the Stop

mode is terminated.

• The program counter stop the address of the

instruction to be executed after the instruction

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The reset should not be activated before V_DDis restored to its

normal operating level, and must be held active long enough to

allow the oscillator to restart and stabilize.

with the oscillator and the internal hardware is lowered; however,

the power dissipation associated with the pin interface (depend-

ing on the external circuitry and program) is not directly deter-

mined by the hardware operation of the STOP feature. This point

should be little current flows when the input level is stable at the

power voltage level (V_DD/V_SS); however, when the input level

gets higher than the power voltage level (by approximately 0.3 to

0.5V), a current begins to flow. Therefore, if cutting off the out-

put transistor at an I/O port puts the pin signal into the high-im-

pedance state, a current flow across the ports input transistor,

requiring to fix the level by pull-up or other means.

Note: After STOP instruction, at least two or more NOP in-

struction should be written.

Ex)

LDM CKCTLR,#0FH ;more than 20ms

LDM SSCR,#5AH

STOP

NOP ;for stabilization time

In the STOP operation, the dissipation of the power associated

Peripheral

CPU

STOP Mode

SLEEP Mode

Stop

RAM

Retain

Basic Interval Timer

Watchdog Timer

Watch Timer

Halted (Only operates in RC-WDT mode)

Stop (Only operates in RC-WDT mode)

Stop (Only operates in Subclock mode)

Operates Continuously

Stop

Halted(Only when the event counter mode is

enabled, timer operates normally)

Timer/Counter

Operates Continuously

Buzzer, ADC

SIO

Stop

Only operate with external clock

Stop(X_IN=L, X_OUT=H)

Only operate with external clock

UART

Only operate with external clock

Oscillator

Oscillation

Retain

Sub Oscillator

I/O Ports

Oscillation

Retain

Control Registers

Internal Circuit

Prescaler

Retain

Stop mode

Retain

Sleep mode

Active

Address Data Bus

Retain

Reset, Timer(EC0, EC1),

Release Source

RC WDT Timer, Watch Timer(Subclock),

SIO(ext. clock), UART, External Interrupt

Reset, All Interrupts

Table 21-1 Peripheral Operation During Power Saving Mode

lowing the STOP instruction. It will not vector to interrupt service

Release the STOP mode

routine. (refer to Figure 21-4)

The source for exit from STOP mode is hardware reset, external

interrupt, Timer(Event Counter), Watchdog Timer(RCWDT),

Watch Timer(by subclock), SIO(by external clock) or UART.

Reset re-defines all the Control registers but does not change the

on-chip RAM. External interrupts allow both on-chip RAM and

Control registers to retain their values.

When exit from Stop mode by external interrupt, enough oscilla-

tion stabilization time is required to normal operation. Figure 21-

5 shows the timing diagram. When released from the Stop mode,

the Basic interval timer is activated on wake-up. It is increased

from 00_Huntil FF_H. The count overflow is set to start normal op-

eration. Therefore, before STOP instruction, user must set its rel-

evant prescaler divide ratio to have long enough time (more than

If I-flag = 1, the normal interrupt response takes place. If I-flag =

0, the chip will resume execution starting with the instruction fol-

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Preliminary

20msec). This guarantees that oscillator has started and stabi-

lized.

By reset, exit from Stop mode is shown in Figure 21-6.

STOP

INSTRUCTION

STOP Mode

Interrupt Request

=0

Corresponding Interrupt

Enable Bit (IENH, IENL)

IENH or IENL ?

=1

STOP Mode Release

=0

Master Interrupt

Enable Bit PSW[2]

I-FLAG

=1

Interrupt Service Routine

Figure 21-4 STOP Releasing Flow by Interrupts

.

Oscillator

(X_INpin)

internal system Clock

External Interrupt

STOP Instruction

Executed

BIT Counter

n

n+1 n+2

n+3

1

0

FE

0

1

2

FF

Clear

Stabilization Time

> 20ms

Normal Operation

Stop Operation

Normal Operation

t

ST

by software

Before executing Stop instruction, Basic Interval Timer must be set

properly by software to get stabilization time which is longer than 20ms.

Figure 21-5 STOP Mode Release Timing by External Interrupt

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STOP Mode

Oscillator

(XI pin)

Internal

Clock

RESET

Internal

RESET

STOP Instruction Execution

Time can not be control by software

Stabilization Time

= 65.5mS @4MHz

t

ST

Figure 21-6 Timing of STOP Mode Release by Reset

21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the on-chip

oscillator is stopped. But internal RC oscillation circuit is oscil-

lated in this mode. The on-chip RAM and Control registers are

held. The port pins out the values held by their respective port

data register, port direction registers.

er. Reset re-defines all the Control registers but does not change

the on-chip RAM. External interrupts allow both on-chip RAM

and Control registers to retain their values.

If I-flag = 1, the normal interrupt response takes place. In this

case, if the bit WDTON of CKCTLR is set to "0" and the bit

WDTE of IENH is set to "1", the device will execute the watch-

dog timer interrupt service routine(Figure 8-6). However, if the

bit WDTON of CKCTLR is set to "1", the device will generate

the internal Reset signal and execute the reset processing(Figure

21-8). If I-flag = 0, the chip will resume execution starting with

the instruction following the STOP instruction. It will not vector

to interrupt service routine.(refer to Figure 21-4)

The Internal RC-Oscillated Watchdog Timer mode is activated

by execution of STOP instruction after setting the bit RCWDT of

CKCTLR to "1". (This register should be written by byte opera-

tion. If this register is set by bit manipulation instruction, for ex-

ample "set1" or "clr1" instruction, it may be undesired operation)

Note: Caution: After STOP instruction, at least two or more

When exit from Stop mode at Internal RC-Oscillated Watchdog

Timer mode by external interrupt, the oscillation stabilization

time is required to normal operation. Figure 21-7 shows the tim-

ing diagram. When release the Internal RC-Oscillated Watchdog

Timer mode, the basic interval timer is activated on wake-up. It

is increased from 00_Huntil FF_H. The count overflow is set to start

normal operation. Therefore, before STOP instruction, user must

be set its relevant prescaler divide ratio to have long enough time

(more than 20msec). This guarantees that oscillator has started

and stabilized. By reset, exit from internal RC-Oscillated Watch-

dog Timer mode is shown in Figure 21-8.

NOP instruction should be written

Ex)

LDM WDTR,#1111_1111B

LDM CKCTLR,#0010_1110B

LDM SSCR,#0101_1010B

STOP

NOP

;for stabilization time

The exit from Internal RC-Oscillated Watchdog Timer mode is

hardware reset or external interrupt including RC watchdog tim-

MAR. 2005 Ver 0.2

105

MC80F0424/0432/0448

Preliminary

Oscillator

(X_INpin)

Internal

RC Clock

Internal

Clock

External

Interrupt

( or WDT Interrupt )

Clear Basic Interval Timer

STOP Instruction Execution

BIT

Counter

N-1

N

N+1

N+2

N-2

00

01

FE FF 00

00

Normal Operation

Stabilization Time

> 20mS

STOP mode

at RC-WDT Mode

Normal Operation

t

ST

Figure 21-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt

RCWDT Mode

Oscillator

(X_INpin)

Internal

RC Clock

Internal

Clock

RESET

RESET by WDT

Internal

RESET

STOP Instruction Execution

Stabilization Time

= 65.5mS @4MHz

Time can not be control by software

t

ST

Figure 21-8 Internal RC-WDT Mode Releasing by Reset

106

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

21.4 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption. To

minimize current drawn during Stop mode, the user should turn-

off output drivers that are sourcing or sinking current, if it is prac-

tical.

V

DD

INPUT PIN

V

DD

internal

pull-up

i=0

V

DD

OPEN

O

i

O

i

Very weak current flows

V

DD

GND

i=0

X

GND

X

OPEN

O

Weak pull-up current flows

O

When port is configured as an input, input level should

be closed to 0V or 5V to avoid power consumption.

Figure 21-9 Application Example of Unused Input Port

OUTPUT PIN

ON

V

ON

V

DD

OPEN

L

OFF

ON

OFF

ON

O

i=0

OFF

i

V

GND

DD

GND

ON

X

O

X

OFF

In the left case, Tr. base current flows from port to GND.

To avoid power consumption, there should be low output

to the port .

O

In the left case, much current flows from port to GND.

Figure 21-10 Application Example of Unused Output Port

than the power voltage level (by approximately 0.3V), a cur-

rent begins to flow. Therefore, if cutting off the output tran-

sistor at an I/O port puts the pin signal into the high-

impedance state, a current flow across the ports input tran-

sistor, requiring it to fix the level by pull-up or other means.

Note: In the STOP operation, the power dissipation asso-

ciated with the oscillator and the internal hardware is low-

ered; however, the power dissipation associated with the

pin interface (depending on the external circuitry and pro-

gram) is not directly determined by the hardware operation

of the STOP feature. This point should be little current flows

when the input level is stable at the power voltage level

(V_DD/V_SS); however, when the input level becomes higher

It should be set properly in order that current flow through port

doesn't exist.

First consider the port setting to input mode. Be sure that there is

MAR. 2005 Ver 0.2

107

MC80F0424/0432/0448

Preliminary

no current flow after considering its relationship with external

circuit. In input mode, the pin impedance viewing from external

MCU is very high that the current doesn’t flow.

If it is not appropriate to set as an input mode, then set to output

mode considering there is no current flow. The port setting to

High or Low is decided by considering its relationship with exter-

nal circuit. For example, if there is external pull-up resistor then

it is set to output mode, i.e. to High, and if there is external pull-

down register, it is set to low.

But input voltage level should be V_SSor V_DD. Be careful that if

unspecified voltage, i.e. if uncertain voltage level (not V_SSor

V_DD) is applied to input pin, there can be little current (max. 1mA

at around 2V) flow.

108

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

22. OSCILLATOR CIRCUIT

The MC80F0424/0432/0448 has two oscillation circuits internal-

ly. X_INand X_OUTare input and output for frequency, and SX_IN

and SX_OUTare input and output for sub frequency, respectively,

inverting amplifier which can be configured for being used as an

on-chip oscillator, as shown in Figure 22-1.

Note: When using the sub clock oscillation, connect a re-

sistor in series with R which is shown as below Figure 22-

1. In order to reduce the power consumption, the sub clock

oscillator employs a low amplification factor circuit. Be-

cause of this, the sub clock oscillator is more sensitive to

noise than the main system clock oscillator.

C1

SX

OUT

IN

X

OUT

R

C2

8MHz

X

V

IN

32.768kHz

V

SS

Recommend

Recommended

C1,C2 = 30pF ~ 90pF

R = 5.7kΩ (if necessary)

Crystal Oscillator

Ceramic Resonator

C1,C2 = 20pF ± 10pF

Crystal or Ceramic Oscillator

Open

X

OUT

External Clock

IN

External Oscillator

Figure 22-1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ceramic

resonator or crystal oscillator. Since each crystal and ceramic res-

onator have their own characteristics, the user should consult the

crystal manufacturer for appropriate values of external compo-

nents.

In addition, see Figure 22-2 for the layout of the crystal.

X

OUT

Note: Minimize the wiring length. Do not allow the wiring to

intersect with other signal conductors. Do not allow the wir-

ing to come near changing high current. Set the potential of

the grounding position of the oscillator capacitor to that of

V^SS. Do not ground it to any ground pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

IN

Figure 22-2 Layout of Oscillator PCB circuit

MAR. 2005 Ver 0.2

109

MC80F0424/0432/0448

23. RESET

Preliminary

The MC80F0424/0432/0448 have four types of reset generation

procedures; they are an external reset input, a watch-dog timer re-

set, power fail processor reset, and address fail reset. Table 23-1

shows on-chip hardware initialization by reset action.

On-chip Hardware

Initial Value

On-chip Hardware

Peripheral clock

Initial Value

(FFFF_H) - (FFFE_H)

Program counter

(PC)

(RPR)

(G)

Off

Disable

RAM page register

G-flag

0

Watchdog timer

Control registers

Power fail detector

0

Refer to Table 8-1

Disable

Operation mode

Main-frequency clock

Table 23-1 Initializing Internal Status by Reset Action

External Reset Input

The reset input is the RESET pin, which is the input to a Schmitt

Trigger. A reset in accomplished by holding the RESET pin low

for at least 8 oscillator periods, within the operating voltage range

and oscillation stable, it is applied, and the internal state is initial-

ized. After reset, 65.5ms (at 4 MHz) add with 7 oscillator periods

are required to start execution as shown in Figure 23-2.

V

CC

10kΩ

to the RESET pin

7036P

+

10uF

Internal RAM is not affected by reset. When V_DDis turned on,

the RAM content is indeterminate. Therefore, this RAM should

be initialized before read or tested it.

When the RESET pin input goes to high, the reset operation is re-

leased and the program execution starts at the vector address

stored at addresses FFFE_H- FFFF_H.

Figure 23-1 Simple Power-on-Reset Circuit

A connection for simple power-on-reset is shown in Figure 23-1.

1

2

3

4

5

6

7

Oscillator

(X_INpin)

RESET

ADDRESS

FFFE FFFF Start

?

BUS

DATA

BUS

OP

?

ADH

?

FE

ADL

MAIN PROGRAM

Reset Process Step

1

Stabilization Time

=65.5mS at 4MHz

t

ST

t

=

x 256

ST

f

÷1024

XIN

Figure 23-2 Timing Diagram after Reset

not be returned to normal operation and would become malfunc-

tion state. If the CPU tries to fetch the instruction from ineffective

code area or RAM area, the address fail reset is occurred. Please

refer to Figure 11-2 for setting address fail option.

Address Fail Reset

The Address Fail Reset is the function to reset the system by

checking code access of abnormal and unwished address caused

by erroneous program code itself or external noise, which could

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MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

24. POWER FAIL PROCESSOR

The MC80F0424/0432/0448 has an on-chip power fail detection

circuitry to immunize against power noise. A configuration reg-

ister, PFDR, can enable or disable the power fail detect circuitry.

Whenever V_DDfalls close to or below power fail voltage for

100ns, the power fail situation may reset or freeze MCU accord-

ing to PFDM bit of PFDR. Refer to “Figure 24-1 Power Fail Volt-

age Detector Register” on page 111.

Note: If power fail voltage is selected to 2.4V or 2.7V on

below 3V operation, MCU is freezed at all the times.

Power Fail Function

OTP

MASK

In the in-circuit emulator, power fail function is not implemented

and user can not experiment with it. Therefore, after final devel-

opment of user program, this function may be experimented or

evaluated.

Enable/Disable

PFDEN flag

PFS0 bit

PFS1 bit

Level Selection

Mask option

Table 24-1 Power fail processor

Note: User can select power fail voltage level according to

CONFIG register(20FFH) at the FLASH MCU(MC80F0424/

0432/0448) but must select the power fail voltage level to

define PFD option of "Mask Order & Verification Sheet" at

the mask chip(MC80C0424/0432/0448), because the pow-

er fail voltage level of mask chip is determined according to

mask option.

R/W R/W R/W

7

-

6

-

5

-

4

-

3

-

2

1

0

ADDRESS: 0F7

INITIAL VALUE: -----000

H

PFDEN

PFDR

PFDM

PFDS

B

Power Fail Status

0: Normal operate

1: Set to “1” if power fail is detected

PFD Operation Mode

0 : MCU will be freezed by power fail detection

1 : MCU will be reset by power fail detection

PFD Enable Bit

0: Power fail detection disable

1: Power fail detection enable

* Cautions :

Be sure to set bits 3 through 7 to “0”.

Figure 24-1 Power Fail Voltage Detector Register

MAR. 2005 Ver 0.2

111

MC80F0424/0432/0448

Preliminary

RESET VECTOR

YES

PFDS =1

NO

RAM Clear

Initialize RAM Data

PFDS = 0

Skip the

initial routine

Initialize All Ports

Initialize Registers

Function

Execution

Figure 24-2 Example S/W of Reset flow by Power fail

V_DD

V_PFDMAX

_PFDMIN

V

65.5mS

Internal

RESET

V_DD

V

_PFDMAX

_PFDMIN

When PFDM = 1

Internal

65.5mS

t <65.5mS

RESET

V_DD

V

_PFDMAX

V_PFDMIN

65.5mS

Internal

RESET

Figure 24-3 Power Fail Processor Situations (at 4MHz operation)

112

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

25. FLASH PROGRAMMING

The Device Configuration Area can be programmed or left un-

programmed to select device configuration such as security bit.

This area is not accessible during normal execution but is reada-

ble and writable during FLASH program / verify mode. The De-

vice Configuration Area register is located at the address 20FFH.

7

-

6

5

4

3

-

2

1

0

ADDRESS: 20FF

INITIAL VALUE: 00

H

-

PFS1 PFS0 LOCK

CONFIG

H

Code Protect (Available FLASH version)

0 : Lock Disable

1 : Lock Enable (main cell read protection)

PFD Level Selection

00: PFD = 2.7V

01: PFD = 2.7V

10: PFD = 3.0V

11: PFD = 2.4V

Figure 25-1 Device Configuration Area Register

25.1 Lock bit

The lock bit exists in Device Configuration Area register. If lock

bit is programmed and user tries to read FLASH memory cell, the

output data from the data port is 5AH that means the normal pro-

tection operation of user program data. Once the lock bit is pro-

grammed, the user can’t modify and read the data of user program

area.

25.2 Power Fail Detection level

The power fail detection provides 3 level of detection, 2.4V, 2.7V

and 3.0V. The default level of detection is 2.7V and this level is

applied if user does not select the specific level in FLASH pro-

gramming S/W tools. For more information, refer to "24. POW-

ER FAIL PROCESSOR" on page 111

MAR. 2005 Ver 0.2

113

MC80F0424/0432/0448

Preliminary

26. Emulator EVA. Board Setting

➊

þ“ Ã ÃÕŒœ–—

➊

114

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

DIP Switch and VR Setting

Before executing the user program, set up the EVA board according to the below configuration.

DIP S/W

Description

ON/OFF Setting

-

This connector is only used for a device over 32 PIN.

This connector is only used for a device under 32 PIN.

Used for the MC80F0424/0432/0448.

Not used for the MC80F0424/0432/0448.

➊

Must be ON position.

ON

1

ON : MC80F0424/0432/0448 selection

OFF : other MCU selection

Eva. select switch

ON

OFF

ON

These switches select the AV_DDsource.

2

3

OFF

ON & OFF : Use Eva. V_DD

OFF & ON : Use User AV_DD

Use Eva. V

Use User’s AV

DD

AV_DDpin select switch

➊

SW2

Normally OFF.

EVA. chip can be reset by external user tar-

get board.

ON : Reset is available by either user target

system board or Emulator RESET switch.

OFF : Reset the MCU by Emulator RESET

switch. Does not work from user target

board.

4

5

This switch select the /Reset source.

Normally OFF.

MCU X_OUTpin is disconnected internally in

the Emulator. Some circumstance user

may connect this circuit.

This switch select the X_OUTsignal on/off.

ON : Output X_OUTsignal

OFF : Disconnect circuit

This switch select Eva. B/D Power supply source.

MDS

➊

Normally MDS.

This switch select Eva. B/D Power supply

source.

SW3

1

USER

Use MDS Power

Use User’s Power

These switchs select the Normal I/O

port(off) or Sub-Clock (on).

ON : SX_OUT, SX_INselection

OFF : R22, R21 selection

➊

1

2

This switch select the R22 or SX_OUT

This switch select the R21 or SX_IN.

.

SW4

MAR. 2005 Ver 0.2

115

MC80F0424/0432/0448

Preliminary

DIP S/W

Description

ON/OFF Setting

1

2

These switches select the R33 or X_IN

This switch select the Normal I/O

port(on&off) or special function

select(off&on).

It is not used for the MC80F0424/0432/

0448.

➊

3

4

SW5

These switches select the R34 or X_OUT

These switches select the R35 or /Reset

This is External oscillation socket(CAN Type. OSC)

5

6

This is for External Clock(CAN Type.

OSC).

-

➊

116

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

27. IN-SYSTEM PROGRAMMING (ISP)

27.1 Getting Started / Installation

The following section details the procedure for accomplishing the

installation procedure.

3. Turn your target B/D power switch ON. Your target B/

D must be configured to enter the ISP mode.

1. Connect the serial(RS-232C) cable between a target

board and the COM port of your PC.

4. Run the MagnaChip ISP software.

5. Press the Reset Button in the ISP S/W. If the status win-

dows shows a message as "Connected", all the condi-

tions for ISP are provided.

2. Configure the COM port of your PC as following.

Baudrate

Data bit

115,200

8

Parity

No

1

Stop bit

Flow control

No

27.2 Basic ISP S/W Information

MAR. 2005 Ver 0.2

117

MC80F0424/0432/0448

Preliminary

Function

Description

Load HEX File

Save HEX File

Load the data from the selected file storage into the memory buffer.

Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX

format.

Erase

Erase the data in your target MCU before programming it.

Blank Check

Program

Read

Verify whether or not a device is in an erased or unprogrammed state.

This button enables you to place new data from the memory buffer into the target device.

Read the data in the target MCU into the buffer for examination. The checksum will be displayed

on the checksum box.

Verify

Assures that data in the device matches data in the memory buffer. If your device is secured, a

verification error is detected.

Option Write

Option

Progam the configuration data of target MCU. The security locking is performed with this button.

Set the configuration data of target MCU. The security locking is set with this button.

Erase & Program & Verify.

AUTO

Auto Option Write

Edit Buffer

If selected with check mark, the option write is performed after erasure and write.

Modify the data in the selected address in your buffer memory

Fill the selected area with a data.

Fill Buffer

Goto

Display the selected page.

OSC. ______ MHz

Start ______

End ______

Checksum

Com Port

Enter your target system’s oscillator value with discarding below point.

Starting address

End address

Display the checksum(Hexdecimal) after reading the target device.

Select serial port.

Baud Rate

Select Device

Page Up Key

Page Down Key

Select UART baud rate.

Select target device.

Display the previous page of your memory buffer.

Display the higher page than the current location.

Table 27-1 ISP Function Description

118

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

27.3 Hardware Conditions to Enter the ISP Mode

The In-System Programming (ISP) is performed without remov-

ing the microcontroller from the target system. The In-System

Programming(ISP) facility consists of a series of internal hard-

ware resources coupled with internal firmware through the serial

port. The In-System Programming (ISP) facility has made in-cir-

cuit programming in an embedded application possible with a

minimum of additional expense in components and circuit board

area. The boot loader can be executed by holding ALEB high,

RST/V_PPas +9V, and ACLK0 with the OSC. 1.8432MHz. The

ISP function uses five pins: TxD0, RxD0, ALEB, ACLK0 and

RST/V_PP

.

V

(+5V)

DD

V

1

2

42

DD

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

R47 / TxD0

R46 / RxD0

R45 / ACLK0

Tx Data

Rx Data

1.8432MHz

+9V

RST/V

RESET

PP

X

ALE

R30

IN

V

DD

X

V

OUT

SS

X-TAL

2MHz~12MHz

Figure 27-1 ISP Configuration

Note: Considerations to implement ISP function in a user

target board

• The ACLK0 must be connected to the specifed

oscillator.

• Connect the +9V to RESET/Vpp pin directly.

• The ALEB pin must be pulled high.

• The main clk must be higher than 2MHz.

MAR. 2005 Ver 0.2

119

MC80F0424/0432/0448

Preliminary

27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board

The ISP software and hardware circuit diagram are provided at

partment. The following circuit diagram is for reference use..

www.magnachipmcu.com . To get a ISP B/D, contact to sales de-

2N2907

100Ω

V

(+5V)

DD

MAX232

T1OUT

V

(+5V)

DD

CON1

Female DB9

14

7

11

10

T1IN

T2IN

+

1

6

2

7

T2OUT

13

8

12

9

R1IN

R2IN

R1OUT

R2OUT

J2

RxD

TxD

RESET/V

V

1

2

3

4

5

6

PP

2

1

+

V

SS

V+

C1+

C1-

SS

DD

+

3

8

4

9

5

1uF

V

1uF

16

6

SS

3

4

5

VCC

V-

ACLK_CLK

MCU_TxD

MCU_RxD

DTR

GND

22Ω

+

C2+

+

1uF

15

GND

C2-

V

SS

V

SS

V

(+5V)

V

(+5V)

DD

J3

X1

22Ω

* V : +4.5 ~ +5.5V

DD

V

+

DD

SS

Vcc

Out

* V : V + 4V

PP

DD

Gnd

OSC

1.8432MHz

V

SS

V

SS

External V

DD

The ragne of V_DDmust be from 4.5 to 5.5V and ISP function is not supported under 2MHz system clock.

If the user supplied V_DDis out of range, the external power is needed instead of the target system V_DD

.

For the ISP operation, power consumption required is minimum 30mA.

Figure 27-2 Reference ISP Circuit Diagram

Figure 27-3 MagnaChip supplied ISP Board

120

MAR. 2005 Ver 0.2

Preliminary

MC80F0424/0432/0448

APPENDIX

MAR. 2005 Ver 0.2

MC80F0424/0432/0448

A. INSTRUCTION MAP

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111

LOW

HIGH

00

01

02

03

04

05

06

07

08

09

0A

TCALL SETA1

.bit

0B

0C

0D

0E

0F

SET1

BBS

ADC

dp

ADC

dp+X

ADC

!abs

ASL

A

ASL

dp

BIT

dp

POP

A

PUSH

A

000

-

BRK

dp.bit A.bit,rel dp.bit,rel #imm

0

SBC

#imm

SBC

dp

SBC

dp+X

SBC

!abs

ROL

A

ROL

dp

TCALL CLRA1 COM

POP

X

PUSH

X

BRA

rel

001

010

011

100

101

110

111

CLRC

CLRG

DI

“

2

.bit

dp

CMP

#imm

CMP

dp

CMP

dp+X

CMP

!abs

LSR

A

LSR

dp

TCALL NOT1

TST

dp

POP

Y

PUSH PCALL

Y

4

M.bit

Upage

OR

#imm

OR

dp

OR

dp+X

OR

!abs

ROR

A

ROR TCALL

dp

OR1

OR1B

CMPX

dp

POP

PSW

PUSH

PSW

RET

6

AND

#imm

AND

dp

AND

dp+X

AND

!abs

INC

A

INC

dp

TCALL AND1 CMPY CBNE

INC

X

CLRV

SETC

SETG

EI

TXSP

TSPX

XCN

8

AND1B

dp

dp+X

EOR

#imm

EOR

dp

EOR

dp+X

EOR

!abs

DEC

A

DEC

dp

TCALL EOR1 DBNE

XMA

dp+X

DEC

X

10

EOR1B

dp

LDA

#imm

LDA

dp

LDA

dp+X

LDA

!abs

LDY

dp

TCALL

12

LDC

LDCB

LDX

dp

LDX

dp+Y

TXA

TAX

DAS

LDM

dp,#imm

STA

dp

STA

dp+X

STA

!abs

STY

dp

TCALL

14

STC

M.bit

STX

dp

STX

dp+Y

XAX

STOP

10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011

11100

1C

11101

1D

11110

1E

11111

1F

LOW

HIGH

10

11

12

13

14

15

16

17

18

19

1A

1B

BPL

rel

ADC

{X}

ADC

ASL

!abs

ASL

dp+X

TCALL

1

JMP

!abs

BIT

!abs

ADDW

dp

LDX

#imm

JMP

[!abs]

CLR1

dp.bit

BBC

000

001

010

011

100

101

110

111

A.bit,rel dp.bit,rel

!abs+Y [dp+X] [dp]+Y

BVC

rel

SBC

{X}

SBC SBC SBC

ROL

!abs

ROL

dp+X

TCALL CALL

3

TEST SUBW

!abs dp

LDY

#imm

JMP

[dp]

“

!abs+Y [dp+X] [dp]+Y

CMP CMP CMP

!abs

BCC

rel

CMP

{X}

LSR

!abs

LSR

dp+X

TCALL

5

TCLR1 CMPW CMPX CALL

!abs

MUL

!abs+Y [dp+X] [dp]+Y

dp

#imm

[dp]

BNE

rel

OR

{X}

OR OR OR

ROR

!abs

ROR TCALL DBNE CMPX LDYA CMPY

dp+X

RETI

!abs+Y [dp+X] [dp]+Y

AND AND AND

7

Y

!abs

dp

#imm

BMI

rel

AND

{X}

INC

!abs

INC

dp+X

TCALL

9

CMPY INCW

!abs

INC

Y

DIV

TAY

TYA

DAA

NOP

!abs+Y [dp+X] [dp]+Y

dp

BVS

rel

EOR

{X}

EOR EOR EOR

DEC

!abs

DEC

dp+X

TCALL

11

XMA

{X}

XMA

dp

DECW

dp

DEC

Y

!abs+Y [dp+X] [dp]+Y

LDA LDA LDA

BCS

rel

LDA

{X}

LDY

!abs

LDY

dp+X

TCALL

13

LDA

{X}+

LDX

!abs

STYA

dp

XAY

XYX

!abs+Y [dp+X] [dp]+Y

BEQ

rel

STA

{X}

STA STA STA

!abs+Y [dp+X] [dp]+Y

STY

!abs

STY

dp+X

TCALL

15

STA

{X}+

STX

!abs

CBNE

dp

MAR. 2005 Ver 0.2

i

MC80F0424/0432/0448

B. INSTRUCTION SET

1. ARITHMETIC/ LOGIC OPERATION

OP BYTE CYCLE

FLAG

NO.

MNEMONIC

ADC #imm

OPERATION

NVGBHIZC

CODE NO

NO

1

2

04

05

06

07

15

16

17

14

84

85

86

87

95

96

97

94

08

2

3

2

1

2

3

2

1

2

Add with carry.

ADC dp

3

4

5

6

3

2

3

4

5

6

3

2

A ← ( A ) + ( M ) + C

3

ADC dp + X

ADC !abs

NV--H-ZC

4

5

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

6

7

8

9

AND #imm

AND dp

Logical AND

10

11

12

13

14

15

16

17

A ← ( A ) ∧ ( M )

AND dp + X

AND !abs

N-----Z-

N-----ZC

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL A

Arithmetic shift left

C

7

6

5

4

3

2

1

0

18

19

ASL dp

09

19

2

4

5

“0”

ASL dp + X

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

ASL !abs

CMP #imm

CMP dp

18

44

45

46

47

55

56

57

54

5E

6C

7C

7E

8C

9C

2C

DF

CF

A8

A9

B9

B8

AF

BE

9B

3

2

3

2

1

2

3

2

3

2

1

2

3

1

5

2

3

4

5

6

3

2

3

4

2

3

4

3

2

4

5

2

12

Compare accumulator contents with memory contents

( A ) - ( M )

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

CMPX dp

CMPX !abs

CMPY #imm

CMPY dp

CMPY !abs

COM dp

Compare X contents with memory contents

( X ) - ( M )

N-----ZC

Compare Y contents with memory contents

( Y ) - ( M )

1’S Complement : ( dp ) ← ~( dp )

Decimal adjust for addition

Decimal adjust for subtraction

Decrement

N-----Z-

N-----ZC

N-----Z-

DAA

DAS

DEC A

DEC dp

M ← ( M ) - 1

DEC dp + X

DEC !abs

DEC X

N-----Z-

DEC Y

DIV

Divide : YA / X Q: A, R: Y

NV--H-Z-

ii

MAR. 2005 Ver 0.2

MC80F0424/0432/0448

OP BYTE CYCLE

FLAG

NVGBHIZC

NO.

MNEMONIC

EOR #imm

OPERATION

CODE NO

NO

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

A4

A5

A6

A7

B5

B6

B7

B4

88

89

99

98

8F

9E

48

49

59

58

5B

64

65

66

67

75

76

77

74

28

29

39

38

68

69

79

78

24

25

26

27

35

36

37

34

2

3

2

1

2

3

1

2

3

1

2

3

2

1

2

3

1

2

3

2

3

2

1

2

Exclusive OR

EOR dp

3

4

5

6

3

2

4

5

2

4

5

9

2

3

4

5

6

3

2

4

5

2

4

5

2

3

4

5

6

3

A ← ( A ) ⊕ ( M )

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC A

N-----Z-

N-----ZC

N-----Z-

Increment

INC dp

M ← ( M ) + 1

INC dp + X

INC !abs

INC X

INC Y

LSR A

Logical shift right

LSR dp

N-----ZC

N-----Z-

7

6

5

4

3

2

1

0

C

LSR dp + X

LSR !abs

MUL

“0”

Multiply : YA ← Y × A

Logical OR

OR #imm

OR dp

A ← ( A ) ∨ ( M )

OR dp + X

OR !abs

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL A

Rotate left through carry

C

7

6

5

4

3

2

1

0

ROL dp

N-----ZC

ROL dp + X

ROL !abs

ROR A

Rotate right through carry

ROR dp

7

6

5

4

3

2

1

0

C

ROR dp + X

ROR !abs

SBC #imm

SBC dp

Subtract with carry

A ← ( A ) - ( M ) - ~( C )

SBC dp + X

SBC !abs

SBC !abs + Y

SBC [ dp + X ]

SBC [ dp ] + Y

SBC { X }

NV--HZC

Test memory contents for negative or zero

( dp ) - 00_H

88

89

TST dp

XCN

4C

CE

2

1

3

5

N-----Z-

Exchange nibbles within the accumulator

A₇~A₄↔ A₃~A₀

MAR. 2005 Ver 0.2

iii

MC80F0424/0432/0448

2. REGISTER / MEMORY OPERATION

OP

BYTE CYCLE

FLAG

NVGBHIZC

NO.

MNEMONIC

LDA #imm

OPERATION

CODE NO

NO

2

1

C4

C5

C6

C7

D5

D6

D7

D4

DB

E4

1E

CC

CD

DC

3E

C9

D9

D8

E5

E6

E7

F5

F6

F7

F4

FB

EC

ED

FC

E9

F9

F8

E8

9F

AE

C8

8E

BF

EE

DE

BC

AD

BB

FE

2

3

2

1

3

2

3

2

3

2

3

2

1

2

3

2

3

1

2

1

Load accumulator

2

LDA dp

3

4

5

6

3

4

5

2

3

4

2

3

4

5

6

7

4

5

4

5

2

4

5

6

5

4

A ← ( M )

3

LDA dp + X

LDA !abs

LDA !abs + Y

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

LDM dp,#imm

LDX #imm

LDX dp

4

5

N-----Z-

6

7

8

9

X- register auto-increment : A ← ( M ) , X ← X + 1

Load memory with immediate data : ( M ) ← imm

Load X-register

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

--------

N-----Z-

X ← ( M )

LDX dp + Y

LDX !abs

LDY #imm

LDY dp

Load Y-register

N-----Z-

--------

Y ← ( M )

LDY dp + X

LDY !abs

STA dp

Store accumulator contents in memory

STA dp + X

STA !abs

STA !abs + Y

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

STA { X }+

STX dp

( M ) ← A

X- register auto-increment : ( M ) ← A, X ← X + 1

Store X-register contents in memory

( M ) ← X

STX dp + Y

STX !abs

STY dp

--------

Store Y-register contents in memory

STY dp + X

STY !abs

TAX

( M ) ← Y

N-----Z-

--------

Transfer accumulator contents to X-register : X ← A

Transfer accumulator contents to Y-register : Y ← A

Transfer stack-pointer contents to X-register : X ← sp

Transfer X-register contents to accumulator: A ← X

Transfer X-register contents to stack-pointer: sp ← X

Transfer Y-register contents to accumulator: A ← Y

Exchange X-register contents with accumulator :X ↔ A

Exchange Y-register contents with accumulator :Y ↔ A

Exchange memory contents with accumulator

( M ) ↔ A

TAY

TSPX

TXA

TXSP

TYA

XAX

XAY

XMA dp

XMA dp+X

XMA {X}

XYX

N-----Z-

--------

Exchange X-register contents with Y-register : X ↔ Y

iv

MAR. 2005 Ver 0.2

MC80F0424/0432/0448

3. 16-BIT OPERATION

FLAG

OP BYTE CYCLE

NO.

1

MNEMONIC

ADDW dp

OPERATION

16-Bits add without carry

NVGBHIZC

CODE NO

NO

1D

5D

BD

9D

7D

DD

3D

2

5

NV--H-ZC

YA ← ( YA ) + ( dp +1 ) ( dp )

Compare YA contents with memory pair contents :

(YA) − (dp+1)(dp)

2

3

4

5

6

7

CMPW dp

DECW dp

INCW dp

LDYA dp

STYA dp

SUBW dp

4

6

5

N-----ZC

N-----Z-

--------

NV--H-ZC

Decrement memory pair

( dp+1)( dp) ← ( dp+1) ( dp) - 1

Increment memory pair

( dp+1) ( dp) ← ( dp+1) ( dp ) + 1

Load YA

YA ← ( dp +1 ) ( dp )

Store YA

( dp +1 ) ( dp ) ← YA

16-Bits substact without carry

YA ← ( YA ) - ( dp +1) ( dp)

4. BIT MANIPULATION

OP BYTE CYCLE

FLAG

NO.

MNEMONIC

AND1 M.bit

OPERATION

NVGBHIZC

CODE NO

NO

1

2

8B

0C

1C

y1

3

2

3

2

1

3

2

1

3

4

Bit AND C-flag : C ← ( C ) ∧ ( M .bit )

Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit )

Bit test A with memory :

-------C

MM----Z-

4

5

4

2

5

4

5

4

2

6

AND1B M.bit

BIT dp

3

Z ← ( A ) ∧ ( M ) , N ← ( M₇) , V ← ( M₆)

Clear bit : ( M.bit ) ← “0”

4

BIT !abs

5

--------

-------0

--0-----

-0--0---

-------C

--------

-------C

--------

-------1

--1-----

--------

CLR1 dp.bit

CLRA1 A.bit

CLRC

6

2B

20

Clear A bit : ( A.bit )← “0”

7

Clear C-flag : C ← “0”

8

40

Clear G-flag : G ← “0”

CLRG

9

80

Clear V-flag : V ← “0”

CLRV

10

11

12

13

14

15

16

17

18

19

20

21

AB

CB

4B

6B

x1

Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit )

Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit)

Load C-flag : C ← ( M .bit )

EOR1 M.bit

EOR1B M.bit

LDC M.bit

LDCB M.bit

NOT1 M.bit

OR1 M.bit

OR1B M.bit

SET1 dp.bit

SETA1 A.bit

SETC

Load C-flag with NOT : C ← ~( M .bit )

Bit complement : ( M .bit ) ← ~( M .bit )

Bit OR C-flag : C ← ( C ) ∨ ( M .bit )

Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit )

Set bit : ( M.bit ) ← “1”

0B

A0

C0

EB

Set A bit : ( A.bit ) ← “1”

Set C-flag : C ← “1”

Set G-flag : G ← “1”

SETG

Store C-flag : ( M .bit ) ←

C

STC M.bit

Test and clear bits with A :

A - ( M ) , ( M ) ← ( M ) ∧ ~( A )

22

23

5C

3C

3

6

N-----Z-

TCLR1 !abs

TSET1 !abs

Test and set bits with A :

A - ( M ) , ( M ) ← ( M ) ∨ ( A )

MAR. 2005 Ver 0.2

v

MC80F0424/0432/0448

5. BRANCH / JUMP OPERATION

OP BYTE CYCLE

FLAG

NO.

MNEMONIC

BBC A.bit,rel

OPERATION

NVGBHIZC

CODE NO

NO

1

2

3

4

y2

y3

x2

x3

2

3

2

3

4/6

--------

Branch if bit clear :

5/7

4/6

5/7

BBC dp.bit,rel

BBS A.bit,rel

BBS dp.bit,rel

if ( bit ) = 0 , then pc ← ( pc ) + rel

Branch if bit set :

--------

if ( bit ) = 1 , then pc ← ( pc ) + rel

Branch if carry bit clear

if ( C ) = 0 , then pc ← ( pc ) + rel

5

6

50

D0

F0

90

70

10

2F

30

2

2/4

4

--------

BCC rel

BCS rel

BEQ rel

BMI rel

BNE rel

BPL rel

BRA rel

BVC rel

Branch if carry bit set

if ( C ) = 1 , then pc ← ( pc ) + rel

Branch if equal

if ( Z ) = 1 , then pc ← ( pc ) + rel

7

Branch if minus

if ( N ) = 1 , then pc ← ( pc ) + rel

8

Branch if not equal

if ( Z ) = 0 , then pc ← ( pc ) + rel

9

Branch if minus

if ( N ) = 0 , then pc ← ( pc ) + rel

10

11

12

Branch always

pc ← ( pc ) + rel

Branch if overflow bit clear

if (V) = 0 , then pc ← ( pc) + rel

2/4

Branch if overflow bit set

if (V) = 1 , then pc ← ( pc ) + rel

13

14

15

B0

3B

5F

2

3

2

2/4

8

BVS rel

CALL !abs

CALL [dp]

Subroutine call

M( sp)←( pc_H), sp←sp - 1, M(sp)← (pc_L), sp ←sp - 1,

if !abs, pc← abs ; if [dp], pc_L← ( dp ), pc_H← ( dp+1 ) .

8

--------

16

17

18

19

20

21

22

FD

8D

AC

7B

1B

1F

3F

3

2

3

2

5/7

6/8

5/7

4/6

3

CBNE dp,rel

CBNE dp+X,rel

DBNE dp,rel

DBNE Y,rel

JMP !abs

Compare and branch if not equal :

if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.

Decrement and branch if not equal :

if ( M ) ≠ 0 , then pc ← ( pc ) + rel.

Unconditional jump

--------

5

JMP [!abs]

JMP [dp]

pc ← jump address

4

U-page call

23

24

4F

nA

2

1

6

8

M(sp) ←( pc_H), sp ←sp - 1, M(sp) ← ( pc_L),

sp ← sp - 1, pc_L← ( upage ), pc_H← ”0FF_H” .

--------

PCALL upage

TCALL n

Table call : (sp) ←( pc_H), sp ← sp - 1,

M(sp) ← ( pc_L),sp ← sp - 1,

pc_L← (Table vector L), pc_H← (Table vector H)

vi

MAR. 2005 Ver 0.2

MC80F0424/0432/0448

6. CONTROL OPERATION & etc.

OP BYTE CYCLE

FLAG

NO.

1

MNEMONIC

OPERATION

NVGBHIZC

CODE NO

NO

Software interrupt : B ← ”1”, M(sp) ← (pc_H), sp ←sp-1,

M(s) ← (pc_L), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,

pc_L← ( 0FFDE_H) , pc_H← ( 0FFDF_H) .

0F

1

8

---1-0--

BRK

2

3

60

E0

FF

0D

2D

4D

6D

0E

2E

4E

6E

1

3

2

4

-----0--

-----1--

--------

DI

Disable interrupts : I ← “0”

Enable interrupts : I ← “1”

No operation

EI

4

NOP

5

POP A

POP X

POP Y

POP PSW

PUSH A

PUSH X

PUSH Y

PUSH PSW

sp ← sp + 1, A ← M( sp )

sp ← sp + 1, X ← M( sp )

sp ← sp + 1, Y ← M( sp )

sp ← sp + 1, PSW ← M( sp )

M( sp ) ← A , sp ← sp - 1

M( sp ) ← X , sp ← sp - 1

M( sp ) ← Y , sp ← sp - 1

M( sp ) ← PSW , sp ← sp - 1

6

--------

restored

--------

7

8

9

10

11

12

Return from subroutine

sp ← sp +1, pc_L← M( sp ), sp ← sp +1, pc_H← M( sp )

13

6F

1

5

--------

RET

Return from interrupt

sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,

pc_L← M( sp ), sp ← sp + 1, pc_H← M( sp )

14

15

7F

EF

1

6

3

restored

--------

RETI

STOP

Stop mode ( halt CPU, stop oscillator )

MAR. 2005 Ver 0.2

vii

MC80F0424/0432/0448

C. MASK ORDER SHEET

Refer to next page.

viii

MAR. 2005 Ver 0.2

Mask Order & Verification Sheet

MC80C04

- MD

K : 64SDIP

Q : 64MQFP

L : 64LQFP

48 : 48K

32 : 32K

24 : 24K

Customer should write inside thick line box.

2. Device Information

1. Customer Information

Company Name

Package

File Name

ROM Size (bytes)

64MQFP

64LQFP

24K

64SDIP

) .OTP

(

Application

32K

)

48K

YYYY

MM

DD

Order Date

Check Sum

(

Tel:

Fax:

Set “00_H” in blanked area

* PFD Option

(48K)

(32K)

(24K)

4000

8000

C000

H

E-mail address:

2.7V

3.0V

2.4V

.OTP file

H

Name &

Signature:

FFFF

H

(Please check mark√ into

)

3. Marking Specification

24 or 32 or 48

Customer’s logo

Customer logo is not required.

MC80C04XXX-MD

YYWW

KOREA

If the customer logo must be used in the special mark, please submit a clean original of the logo.

Customer’s part number

4. Delivery Schedule

Date

Quantity

MagnaChip Confirmation

YYYY

MM

DD

Customer sample

Risk order

pcs

5. ROM Code Verification

Please confirm out verification data.

YYYY

MM

DD

MM

DD

Approval date:

Verification date:

Check sum:

I agree with your verification data and confirm you to

make mask set.

Tel:

Fax:

Tel:

Fax:

E-mail address:

Name &

Signature:

Name &

Signature:


型号：	MC80C0448L
厂家：	ETC
描述：	8-BIT SINGLE-CHIP MICROCONTROLLERS 8位单芯片微控制器微控制器
文件：	总135页 (文件大小：1726K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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