ML22Q563-NNNMB [ETC]
4-Channel Mixing Speech Synthesis LSI;
| 型号： | ML22Q563-NNNMB |
| 厂家： | 
ETC |
| 描述： | 4-Channel Mixing Speech Synthesis LSI 有原始数据的样本ROM CD ISM频段 光电二极管 商用集成电路 |
| 文件： | 总66页 (文件大小：1186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL2256X-06
Issue Date: Apr. 25, 2013
ML22Q563-NNNMB/ML22Q563-xxxMB/ML2256X-xxxMB
4-Channel Mixing Speech Synthesis LSI with Built-in FLASH/MASK ROM
GENERAL DESCRIPTION
The ML22Q563-NNN, ML22Q563-xxx and ML2256X-xxx are 4-channel mixing speech synthesis LSIs with
built-in FLASH/MASK ROM for voice data. These LSIs incorporate into them an HQ-ADPCM decoder that
enables high sound quality, 16-bit D/A converter, low-pass filter, and 1.0 W monaural speaker amplifier for
driving speakers. Since functions necessary for voice output are all integrated into a single chip, a system can
be upgraded with audio features by only using one of these LSIs.
• Capacity of internal memory and the maximum voice production time (when HQ-ADPCM※1 method used)
Maximum voice production time (sec)
Product name
ROM capacity
fsam = 8.0 kHz
fsam = 16.0 kHz
fsam = 32.0 kHz
ML22Q563-NNN
ML22Q563-xxx
ML22563-xxx
4 Mbits
2 Mbits
161
79
80
39
40
19
ML22562-xxx
FEATURES
• Speech synthesis method:
Can be specified for each phrase.
HQ-ADPCM / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
Can be specified for each phrase.
• Sampling frequency:
12.0/24.0/48.0 kHz, 8.0 / 16.0/32.0 kHz, 6.4/12.8/25.6 kHz
• Built-in low-pass filter and 16-bit D/A converter
• Built-in speaker driver amplifier:
1.0 W, 8Ω (at DVDD = 5 V)
• External analog voice input (built-in analog mixing function)
• CPU command interface:
• Maximum number of phrases:
• Edit ROM
Clock synchronous serial interface
1024 phrases, from 000h to 3FFh
• Volume control:
CVOL command: Adjustable through 32 levels (including OFF)
AVOL command: Adjustable through 50 levels (including OFF)
• Repeat function:
• Channeｌ mixing function:
LOOP command
4channels
• Power supply voltage detection function: Can be controlled at six levels from 2.7 to 4.0 V (including the
OFF setting)
• Source oscillation frequency:
• Power supply voltage:
• Operating temperature range:
• Package:
4.096 MHz
2.7 to 5.5 V
2
–40°C to +85°C※
30-pin plastic SSOP(P-SSOP30-56-0.65-6K-MC)
ML22Q563-NNNMB/ML22Q563-xxxMB
ML22563-xxxMB/ML22562-xxxMB
•Product name:
(“xxx” denotes ROM code number)
HQ-ADPCM is a high sound quality audio compression technology of "Ky's".
“Ky’s” is a Registered trademark of National Universities corporate Kyushu
Institute of Technology
※1
※2 The limitation on the operation time changes by the using condition. (Refer to Page62)
1/66
FEDL2256X-06
ML22Q563/ML2256X
The table below summarizes the differences between the exsisting speech synthesis LSIs (ML225X and
ML2282X) and the ML22Q563/ML2256X.
Item
CPU interface
ROM type
ML225X
Parallel/Serial
MASK
ML2282X
Serial/I2C
P2ROM
ML22Q563
Serial
FLASH
4 Mbits
ML2256X
←
MASK
2/4 Mbits
ROM capacity
3/4/6 Mbits
4/8/16 Mbits
2-bit ADPCM2
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM
16-bit straight PCM
4-bit ADPCM2
8-bit straight PCM
8-bit non-linear PCM 8-bit non-linear PCM 8-bit non-linear PCM
16-bit straight PCM
1024
HQ-ADPCM
8-bit straight PCM
HQ-ADPCM
8-bit straight PCM
Playback method
16-bit straight PCM 16-bit straight PCM
Maximum number of
phrases
256
←
←
←
4.0/5.3/6.4/8.0/
10.7/12.0/12.8/
16.0/21.3/24.0/
25.6/32.0/48.0
6.4/8.0/12.0/
12.8/16.0/24.0/
25.6/32.0/48.0
Sampling frequency
(kHz)
←
4.096 MHz (has a
crystal oscillator
circuit built-in)
Clock frequency
D/A converter
←
←
←
←
14-bit voltage-type
16-bit voltage-type
←
FIR interpolation
filter
(High-pass
interpolation)
Built-in
FIR interpolation
filter
FIR interpolation
filter
Low-pass filter
←
(SRC)
Built-in
0.7 W
(8Ω, DVDD = 5 V)
Speaker driving
amplifier
No
1.0 W
(8Ω, DVDD = 5 V)
←
←
Simultaneous sound
production function
(mixing function)
Edit ROM
4-channel
←
←
Yes
29 levels
20 to 1024 ms
(4 ms steps)
Yes
←
←
←
←
←
Volume control
32 levels
Silence insertion
←
←
←
←
←
←
←
←
Repeat function
External analog
input
No
Yes
External speech
data input
Yes
No
←
←
←
←
←
←
←
←
Interval at which a
seam is silent during
continuous playback
Power supply
voltage
No
2.7 V to 5.5 V
Ambient
temperature
Package
−40°C to +105°C
−40°C to +85°C
←
←
←
←
44-pin QFP
30-pin SSOP
2/66
FEDL2256X-06
ML22Q563/ML2256X
BLOCK DIAGRAM
The block diagrams of the ML22Q563-NNN/ML22Q563-xxx/ML2256X-xxx are shown below.
DVDD
JTAG
Interface
Address Controller
18/19bit
DGND
VDDL
Cmd
Analyzer
VDDR
4Mbit FLASH
RESETB
CSB
PCM Synthesizer
LPF(CVOL)
SCK
Timing
Controller
SI
I/O
SO
Interface
CBUSYB
STATUS
ERR
16bit DAC
PLL
DIPH
TESTI1
VPP
SP-AMP
(AVOL)
OSC
SPVDD
SPGND
XT XTB
SPM SPP
AIN SG
Block Diagram of ML22Q563-NNN/ML22Q563-xxx
DVDD
DGND
VDDL
Cmd
Analyzer
2/4-Mbit ROM
Address Controller
18/19 bits
RESETB
CSB
PCM Synthesizer
LPF (CVOL)
16-bit DAC
SCK
SI
Timing
Controller
I/O
SO
Interface
CBUSYB
STATUS
ERR
PLL
DIPH
TESTI1
SP-AMP
(AVOL)
OSC
SPVDD
SPGND
XT XTB
SPM SPP
AIN SG
Block Diagram of ML2256X-xxx
3/66
FEDL2256X-06
ML22Q563/ML2256X
PIN CONFIGURATION (TOP VIEW)
● ML22Q563-NNN/ML22Q563-xxx
1
2
3
4
5
6
7
30 SPVDD
29 SPGND
28 SPP
AIN
SG
VDDR
DVDD
DGND
VDDL
27 SPM
26 TESTO
25 TESTI4
24 TESTI3
23 TESTI2
22 TESTI1
21 TESTI0
20 RESETB
19 VPP
DIPH
STATUS 8
ERR 9
CSB 10
SCK 11
SI 12
SO 13
18 DVDD
CBUSYB 14
17 XT
15
16 XTB
DGND
30-Pin Plastic SSOP
NC：Unused pin
●
ML2256X -xxx
1
30 SPVDD
29 SPGND
28 SPP
27 SPM
26 TESTO
25 NC
AIN
SG 2
NC 3
4
DVDD
DGND 5
VDDL
DIPH
STATUS
6
7
8
24 NC
23 NC
ERR 9
22 TESTI1
21 TESTI0
20 RESETB
19 NC
10
11
CSB
SCK
SI 12
13
14
18 DVDD
17 XT
SO
CBUSYB
DGND 15
16 XTB
NC：Unused pin
30-Pin Plastic SSOP
4/66
FEDL2256X-06
ML22Q563/ML2256X
PIN DESCRIPTION (1)
Initial
Attribute
Symbol
AIN
Attribute
—
Pin
1
I/O
I
Description
Speaker amplifier input pin.
Built-in speaker amplifier’s reference voltage output pin.
value
analog
0
2
SG
O
O
—
—
Connect a capacitor of 0.1 μF or more between this pin and analog
DGND.
2.5 V regulator output pin.
Acts as an internal power supply (for ROM). Connect a analog
capacitor of 10 μF or more between this pin and DGND.
Digital power supply pin.
0
3*2
VDDR
0
4,18
5,15
6
DVDD
DGND
VDDL
—
—
O
—
—
—
Connect a bypass capacitor of 10μF or more between this power
pin and DGND.
—
—
0
gnd
Digital ground pin
2.5 V regulator output pin.
Acts as an internal power supply (for logic). Connect a power
capacitor of 10 μF or more between this pin and DGND.
Serial interface switching pin.
Pin for choosing between rising edges and falling edges as
to the edges of the SCK pulses used for shifting serial data
input to the SI pin into the inside of the LSI.
When this pin is at a “L” level, SI input data is shifted into the
LSI on the rising edges of the SCK clock pulses and a status
signal is output from the SO pin on the falling edges of the
7
DIPH
I
Positive
digital
0
SCK clock pulses.
When this pin is at a “H” level, SI input data is shifted into the
LSI on the falling edges of the SCK clock pulses and a status
signal is output from the SO pin on the rising edges of the
SCK clock pulses.
Channel status output pin.
8
9
STATUS
ERR
O
O
Positive
Positive
digital
digital
1
0
Outputs the BUSYB or NCR signal for each channel by
inputting the OUTSTAT command.
Error output pin.
Outputs a “H” level if an error occurs.
Chip select pin.
A “L” level on this pin accepts the SCK or SI inputs. When
this pin is at a “H” level, neither the SCK nor SI signal is input
to the LSI.
10
11
CSB
SCK
I
I
Negative
Positive
digital
clk
1
0
Synchronous serial clock input pin.
Synchronous serial data input pin.
When the DIPH pin is at a “L” level, data is shifted in on the
rising edges of the SCK clock pulses.
12
SI
I
—
digital
0
When the DIPH pin is at a “H” level, data is shifted in on the
falling edges of the SCK clock pulses.
Channel status serial output pin.
Outputs a status signal on the falling edges of the SCK clock
pulses when the DIPH pin is at a ”L” level; outputs a status
signal on the rising edges of the SCK clock pulses when the
DIPH pin is at a ”H” level.
13
SO
O
Positive
digital
Hi-Z
When the CSB pin is at a ”L” level, the status of each channel
is output serially in sync with the SCK clock. When the CSB
pin is at a ”H” level, this pin goes into a high impedance state.
5/66
FEDL2256X-06
ML22Q563/ML2256X
PIN DESCRIPTION (2)
Initial
Attribute
Pin
Symbol I/O Attribute
Description
value(*1)
Command processing status signal output pin.
This pin outputs a “L” level during command processing.
Be sure to enter commands with the CBUSYB pin driven
at a “H” level.
Connects to a crystal or a ceramic resonator.
When using an external clock, leave this pin open.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
14 CBUSYB
O
O
Negative
Negative
digital
clk
0(*1)
16
XTB
1
Connects to a crystal or a ceramic resonator.
A feedback resistor of around 1 MΩ is built in between this
XT pin and the XTB pin. When using an external clock,
input the clock from this pin.
If a crystal or a ceramic resonator is used, connect it as
close to the LSI as possible.
17
XT
I
I
Positive
—
clk
0
0
Pin for FLASH analysis.
Should be connected to DGND.
19*2
VPP
analog
Reset input pin.
At “L” level input, the LSI enters the initial state. After a
reset input, the entire circuit is stopped and enters a
power down state. Upon power-on, input a “L” level to
this pin. After the power supply voltage is stabilized,
drive this pin at a “H” level.
20
21
RESETB
I
Negative
digital
0(*1)
This pin has a pull-up resistor built in.
Input pin for testing. Also acts as a Flash rewrite enable
TESTI0
(MODE)
I
Positive pin.
Has a pull-down resistor built in.
digital
0
Used as either an input pin for testing or a reset input pin
for Flash rewriting. Has a pull-down resistor built in.
TESTI1
(nTRST)
22
I
I
Negative
Positive
digital
digital
0
1
Used as either an input pin for testing or a state transition
pin for Flash rewriting. Has a pull-up resistor built in.
TESTI2
(TMS)
23*2
TESTI3
(TDI)
Used as either an input pin for testing or a data input pin
for Flash rewriting. Has a pull-up resistor built in.
Used as either an input pin for testing or a clock input pin
for Flash rewriting. Has a pull-up resistor built in.
Used as either an output pin for testing or a data output
pin for Flash rewriting.
24*2
25*2
I
I
Positive
Positive
digital
digital
1
0
TESTI4
(TCK)
TESTO
(TSO)
SPM
26*2
27
O
O
Positive
—
digital
Hi-Z
Hi-Z
Output pin of the built-in speaker amplifier.
Output pin of the built-in speaker amplifier.
analog
28
29
30
SPP
O
—
—
—
—
—
Can be configured as an AOUT amplifier output by analog
command setting.
0
SPGND
SPVDD
gnd
—
—
Speaker amplifier ground pin.
Speaker amplifier power supply pin.
Connect a bypass capacitor of 10μF or more between this power
pin and SPGND.
*1: Indicates the initial value at reset input or during power down.
*2: These are NC pins in the ML2256X.
6/66
FEDL2256X-06
ML22Q563/ML2256X
ABSOLUTE MAXIMUM RATINGS
DGND = SPGND = 0 V, Ta = 25°C
Parameter
Power supply voltage
Input voltage
Symbol
DVDD
SPVDD
Condition
Rating
Unit
—
−0.3 to +7.0
V
VIN
PD
—
−0.3 to DVDD+0.3
V
When the LSI is mounted on
JEDEC 4-layer board.
When SPVDD = 5V
1000
mW
Power dissipation
Applies to all pins except
SPM, SPP, VDDL, and VDDR
10
mA
.
IOS
Output short-circuit current
Storage temperature
Applies to SPM and SPP pins.
Applies to VDDL and VDDR pins.
—
500
50
−55 to +150
mA
mA
°C
TSTG
RECOMMENDED OPERATING CONDITIONS
DGND = SPGND = 0 V
Parameter
DVDD, SPVDD
Power supply voltage
Symbol
Condition
—
Range
Unit
DVDD
SPVDD
2.7 to 5.5
V
Operating temperature
Top
—
—
−40 to +85
Typ.
4.096
°C
Min.
3.5
Max.
4.5
Master clock frequency
fOSC
MHz
FLASH Conditions
DGND = SPGND = 0 V
Unit
Parameter
Symbol
TOP
Condition
Range
At write/erase
0 to +70
°C
Operating temperature
At read
―
°C
−40 to +85
Maximum rewrite count
Data retention period
CEP
YDR
10
10
times
years
―
7/66
FEDL2256X-06
ML22Q563/ML2256X
ELECTRICAL CHARACTERISTICS
DC Characteristics (3 V)
DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
“H” input voltage
“L” input voltage
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
“L” output voltage 2 (*1)
Symbol
VIH
VIL
VOH1
VOH2
VOL1
VOL2
IOOH
IOOL
IIH1
Condition
Min.
0.86×DVDD
Typ.
—
—
—
—
—
—
—
Max.
DVDD
0.14×DVDD
—
Unit
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
—
—
0
IOH = −1 mA
IOH = −50 µA
IOL = 2 mA
IOL = 50 µA
DVDD − 0.4
DVDD − 0.4
—
0.4
0.4
10
—
10
15
200
—
—
—
—
−10
—
0.3
2
−10
−15
−200
VOH = DVDD (CSB=“H”)
VOL = DGND(CSB=“H”)
VIH = DVDD
Output leakage current(*2)
—
—
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
“L” input current 2 (*3)
“L” input current 3 (*5)
IIH2
IIH3
IIL1
IIL2
VIH = DVDD
VIH = DVDD
VIL = DGND
VIL = DGND
2.0
30
—
−2.0
–30
−0.3
–2
IIL3
VIL = DGND
fOSC = 4.096 MHz
fs=48kHz, f=1kHz,
When 16bitPCM
Playback
Supply current during
playback 1
IDD1
—
—
41
mA
No output load
fOSC = 4.096 MHz
During silence playback
No output load
Ta = −40 to +55°C
Ta = −40 to +85°C
Ta = −40 to +55°C
Ta = −40 to +85°C
Supply current during
playback 2
IDD2
—
—
38
mA
Power-down supply
current (*6)
Power-down supply
current (*7)
—
—
—
—
—
—
—
—
10
20
50
µA
µA
µA
µA
IDDS1
IDDS1
100
*1: Applies to the XTB pin.
*2: Applies to the SO and TESTO pins.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 and TESTI1 pins.
*5: Applies to the RESETB, TEST2, TEST3 and TEST4 pins.
*6: Applies to the ML2256X.
*7: Applies to the ML22Q563.
8/66
FEDL2256X-06
ML22Q563/ML2256X
DC Characteristics (5 V)
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
“H” input voltage
“L” input voltage
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
Symbol
VIH
VIL
VOH1
VOH2
VOL1
IOOH
Condition
Min.
0.8×DVDD
0
DVDD−0.4
DVDD−0.4
—
Typ.
—
—
—
—
—
Max.
DVDD
0.2×DVDD
—
Unit
V
V
V
V
V
—
—
IOH = −1 mA
IOH = −50 µA
IOL = 2 mA
VOH = DVDD (CSB=“H”)
—
0.4
—
—
10
µA
Output leakage
current(*2)
IOOL
VOL2
IIH1
IIH2
IIH3
IIL1
VOL = DGND (CSB=“H”)
−10
—
—
0.8
20
–10
–20
–400
—
—
—
5
100
—
—
0.4
10
20
400
—
µA
V
“L” output voltage 2 (*1)
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
IOL = 50 µA
VIH = DVDD
VIH = DVDD
VIH = DVDD
VIL = DGND
µA
µA
µA
µA
µA
µA
“L” input current 2 (*3)
“L” input current 3 (*5)
IIL2
IIL3
VIL = DGND
VIL = DGND
−5.0
–100
−0.8
–20
fOSC = 4.096 MHz
fs=48kHz, f=1kHz,
When 16bitPCM
Playback
Supply current during
playback 1
IDD1
—
—
55
mA
No output load
fOSC = 4.096 MHz
During silence playback
No output load
Ta = −40 to +55°C
Ta = −40 to +85°C
Ta = −40 to +55°C
Ta = −40 to +85°C
Supply current during
playback 3
IDD3
—
—
48
mA
Power-down supply
current (*6)
Power-down supply
current (*7)
—
—
—
—
—
—
—
—
10
20
50
µA
µA
µA
µA
IDDS1
IDDS1
100
*1: Applies to the XTB pin.
*2: Applies to the SO and TESTO pins.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 and TESTI1 pins.
*5: Applies to the RESETB, TEST2, TEST3 and TEST4 pins.
*6: Applies to the ML2256X.
*7: Applies to the ML22Q563.
9/66
FEDL2256X-06
ML22Q563/ML2256X
Analog Section Characteristics (3 V)
DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
AIN input resistance
AIN input voltage range
Line output resistance
LINE output load
Symbol
RAIN
VAIN
Condition
Input gain: 0 dB
Min.
10
—
—
Typ.
20
—
—
Max.
30
SPVDD×2/3 Vp-p
Unit
kΩ
RLA
At 1/2SPVDD output
100
Ω
RLA
VAO
At SPGND10kΩ load
10
—
—
—
kΩ
resistance
LINE output voltage range
SPVDD
5/6
×
At SPGND10kΩ load
SPVDD/6
V
SG output voltage
SG output resistance
SPM, SPP output load
resistance
Speaker amplifier output
power
VSG
RSG
—
—
0.95×DVDD/2
DVDD/2
96
1.05×DVDD/2
V
kΩ
57
135
RLSP
PSPO
—
6
8
—
—
Ω
SPVDD = 3.3V, f = 1 kHz
RSPO = 8Ω, THD≦ 10%
100
300
mW
Output offset voltage
between SPM and SPP
with no signal present
Regulator output voltage
SPIN–SPM gain = 0 dB
VOF
−50
—
+50
mV
V
With a load of 8Ω
VDDL
VDDR
Output load current =
2.25
2.5
2.75
−35 mA
10/66
FEDL2256X-06
ML22Q563/ML2256X
Analog Section Characteristics (5 V)
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
AIN input resistance
Symbol
RAIN
Condition
Min.
Typ.
Max.
Unit
Input gain: 0 dB
10
20
30
kΩ
SPVDD
×
AIN input voltage range
VAIN
RLA
RLA
—
—
10
—
—
—
Vp-p
Ω
2/3
Line output resistance
LINE output load
resistance
At 1/2SPVDD output
100
At SPGND10kΩ load
—
kΩ
LINE output voltage range
SPVDD
×
At SPGND10kΩ load
VAO
SPVDD /6
—
V
5/6
SG output voltage
0.95x
SPVDD /2
57
1.05x
SPVDD /2
135
VSG
RSG
RLSP
—
SPVDD /2
V
kΩ
Ω
SG output resistance
—
96
8
SPM, SPP output load
resistance
Speaker amplifier output
power
—
6
—
—
SPVDD = 5.0V, f = 1 kHz
SPO = 8Ω, THD≦ 10%
PSPO
800
1000
—
mW
mV
V
R
Output offset voltage
between SPM and SPP
with no signal present
Regulator output voltage
SPIN–SPM gain = 0 dB
VOF
−50
+50
With a load of 8Ω
VDDL
VDDR
Output load current =
2.25
2.5
2.75
−35 mA
11/66
FEDL2256X-06
ML22Q563/ML2256X
AC Characteristics (1)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
Symbol
fduty
Condition
Min.
40
Typ.
50
Max.
60
Unit
%
Master clock duty cycle
—
—
RESETB input pulse width
Reset noise rejection pulse width
tRST
10
—
—
μs
μs
tNRST
RESETB pin
—
—
0.1
Noise
width
rejection
pulse
tNINP CSB, SCK, and SI pins
—
—
5
ns
fOSC = 4.096 MHz
At STOP/SLOOP/CLOOP/
Command input interval time1
tINT
10
—
—
μs
VOL command input
After status read
fOSC = 4.096 MHz
After input first command at
two-time command input
Command input interval time2
Command input enable time
tINTC
0
—
—
μs
mode
fOSC = 4.096 MHz
tcm
During continuous playback
At SLOOP input
4.096 MHz
—
—
—
—
10
4
ms
ms
At PUP command input
CBUSYB “L” level output time
tPUP
At external clock input
4.096 MHz
At external clock input
POP = “0”
DAEN = “0”→”1”
or SPEN = “0”→”1”
4.096 MHz
At AMODE command input
CBUSYB “L” level output time（*3）
tPUPA1
39
72
41
74
43
76
ms
ms
At external clock input
POP = “1”
At AMODE command input
CBUSYB “L” level output time
tPUPA2
DAEN = “0”→”1”
(SPEN = “0”)
4.096 MHz
At external clock input
POP = “0”
At AMODE command input
CBUSYB “L” level output time
tPUPA3
32
—
34
—
36
10
ms
μs
DAEN = “0”→”1”
(SPEN = “0”)
At PDWN command input
CBUSYB “L” level output time
tPD
fOSC = 4.096 MHz
4.096 MHz
At external clock input
POP = “0”
DAEN = “1”→”0”
or SPEN = “1”→”0”
4.096 MHz
At AMODE command input
CBUSYB “L” level output time（*3）
tPDA1
106
108
110
ms
At external clock input
POP = “1”
At AMODE command input
CBUSYB “L” level output time
tPDA2
143
145
147
ms
DAEN = “1”→”0”
(SPEN = “0”)
12/66
FEDL2256X-06
ML22Q563/ML2256X
4.096 MHz
At external clock input
POP = “0”
At AMODE command input
CBUSYB “L” level output time
tPDA3
103
105
107
ms
DAEN = “1”→”0”
(SPEN = “0”)
CBUSYB “L” level output time 1 (*1)
CBUSYB “L” level output time 2 (*2)
CBUSYB “L” level output time 3 (*4)
tCB1
tCB2
tCB3
fOSC = 4.096 MHz
fOSC = 4.096 MHz
fOSC = 4.096 MHz
—
—
—
—
—
—
10
2
μs
ms
μs
200
Note: Output pin load capacitance = 45 pF (Max.)
*1: Applies to cases where a command is input, except after the PUP, PDWN, PLAY, START or AMODE
command input.
*2: Applies to cases where the PLAY or START command is input.
*3: When FAD3-0 is initial value (8h)
*4: Applies to cases where the STOP command is input.
13/66
FEDL2256X-06
ML22Q563/ML2256X
AC Characteristics (2) (3V)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
SCK input enable time from CSB fall
SCK hold time from CSB rise
Symbol
tESCK
tCSH
Condition
—
Min.
200
200
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
Data floating time from CSB rise
Data setup time from SCK rise
tDOZ
RL = 3 kΩ
DIPH = “L”
DIPH = “L”
DIPH = “L”
DIPH = “H”
DIPH = “H”
DIPH = “H”
—
180
—
tDIS1
50
Data hold time from SCK rise
tDIH1
50
—
Data output delay time from SCK rise
Data setup time from SCK fall
tDOD1
tDIS2
—
180
—
50
Data hold time from SCK fall
tDIH2
50
—
Data output delay time from SCK rise
SCK “H” level pulse width
tDOD2
tSCKH
tSCKL
tDBSY1
tDBSY2
—
180
—
200
200
—
SCK “L” level pulse width
—
—
CBUSYB output delay time from SCK rise
CBUSYB output delay time from SCK fall
Note: Output pin load capacitance = 45 pF (Max.)
DIPH = “L”
DIPH = “H”
180
180
—
AC Characteristics (2) (5V)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = −40 to +85°C
Parameter
SCK input enable time from CSB fall
SCK hold time from CSB rise
Symbol
tESCK
tCSH
Condition
—
Min.
100
100
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
Data floating time from CSB rise
Data setup time from SCK rise
tDOZ
RL = 3 kΩ
DIPH = “L”
DIPH = “L”
RL = 3 kΩ
DIPH = “H”
DIPH = “H”
RL = 3 kΩ
—
100
—
tDIS1
50
Data hold time from SCK rise
tDIH1
50
—
Data output delay time from SCK rise
Data setup time from SCK fall
tDOD1
tDIS2
—
90
—
50
Data hold time from SCK fall
tDIH2
50
—
Data output delay time from SCK rise
SCK “H” level pulse width
tDOD2
tSCKH
tSCKL
tDBSY1
tDBSY2
—
90
—
100
100
—
SCK “L” level pulse width
—
—
CBUSYB output delay time from SCK rise
CBUSYB output delay time from SCK fall
Note: Output pin load capacitance = 45 pF (Max.)
DIPH = “L”
DIPH = “H”
90
90
—
14/66
FEDL2256X-06
ML22Q563/ML2256X
TIMING DIAGRAMS
Serial Interface Data Input Timing (When DIPH = “L”)
VIH
CSB
VIL
tCSH
tES CK
tSCKH
VIH
VIL
SCK
tDIS1
tDIH1
tSCKL
VIH
VIL
SI
tDBSY1
VOH
VOL
CBUSYB
Serial Interface Data Input Timing (When DIPH = “H”)
VIH
CSB
VIL
tCSH
tESCK
tSCKL
VIH
VIL
SCK
SI
tDIS2
tDIH2
tSC KH
VIH
VIL
tDBSY2
CBUSYB VO H
VOL
Serial Interface Data Output Timing (When DIPH = “L”)
VIH
CSB
VIL
tCSH
tES CK
tSCKH
VIH
VIL
SCK
tSCKL
tDOD1
tDOZ
VIH
SO VIL
tDBSY1
VOH
CBUSYB
VOL
Serial Interface Data Output Timing (When DIPH = “H”)
VIH
CSB
VIL
tCSH
tESCK
tSCKL
VIH
VIL
SCK
tSC KH
tDOD2
tDOZ
VIH
SO VIL
tDBSY2
CBUSYB VOH
VOL
15/66
FEDL2256X-06
ML22Q563/ML2256X
Power-On Timing (for the power down state, see the section on “5. PDWN command” described later.)
5V
SPVDD
5V
DVDD
tRST
VIH
RESETB
VIL
Power down
Status
Oscillation is stopped after power-on.
Be sure to set “L”level the RESETB pin before the first command input.
Power-Up Timing
CSB
SCK
SI
tPUP
CBUSYB VOH
VOL
VOH
NCRn
(internal)
VOL
VOH
BUSYBn
(internal)
VOL
Oscillation stopped
Power down
Oscillating
XTxXTB
Performing reset
processing
Oscillation stabilized
Awaiting command
Status
16/66
FEDL2256X-06
ML22Q563/ML2256X
Power-Down Timing
CSB
SCK
SI
tPD
CBUSYBVOH
VO L
VOH
NCRn
(internal)VO L
BUSYBnVOH
(internal) VO L
Oscillation
stopped
Oscillating
XTxXTB
Command is being
processed
Awaiting command
Power down
Status
Reset Input Timing
RESETB
tRS T
Oscillating
Oscillation stopped
XTxXTB
V
DDLxSG
GND
SPM
Hi-Z
GND
SPP
Playing
Power down
Status
Note: The same timing applies in cases where the Reset signal is input during waiting for command.
17/66
FEDL2256X-06
ML22Q563/ML2256X
Playback Start Timing by the PLAY Command
PLAY command
1st byte
PLAY command
2nd byte
CSB
SCK
SI
tCB1
tCB2
CBUSYB VOH
VOL
VOH
NCRn
(internal)
VOL
(*1)
VOH
BUSYBn
(internal)
VOL
1/2VDD
SPM
1/2VDD
SPP
Address is being
controlled
Command standby
Awaiting command
Playing
Awaiting c ommand
Status
Command is being processed
*1:
Length of the “L” interval of BUSYBn is = tCB2 + voice production time length.
Playback Stop Timing
STOP command
CSB
SCK
SI
tCB3
VOH
CBUSYB
VOL
VOH
NCRn
(internal)
VOL
VOH
BUSYBn
(internal)
VOL
1/2VDD
SPM
1/2VDD
SPP
Playing
Awaiting command
Status
Command is being processed
18/66
FEDL2256X-06
ML22Q563/ML2256X
Continuous Playback Timing by the PLAY Command
PLAY command
2nd byte
PLAY command PLAY command
st byte 2nd byte
1
CSB
SCK
SI
tcm
tCB1
tCB1
tCB2
CBUSYBVO H
VO L
VO H
NCRn
(internal)VO L
BUSYBn
(internal)
1/2VD D
SPM
1/2VD D
SPP
Awaiting command
Playing phrase 1
Playing phrase 2
Status
Address is being
controlled
Silence Insertion Timing by the MUON Command
PLAY command
MUON commandMUON command
PLAY command PLAY command
1st byte 2nd byte
2nd byte
1st byte 2nd byte
CSB
SCK
SI
tcm
tCB1
tCB1
tCB1
tCB1
tCB2
CBUSYB VOH
VOL
VOH
NCRn
(internal)
(*1)
(*1)
VOL
BUSYBn
(internal)
1/2VDD
SPM
1/2VDD
SPP
Awaiting command
Playing
Silence is being inserted
Waiting for silence insertion to be finished
Playing
Status
Address is being
controlled
*1: The “L” level period of the NCR pin during playback or silence insertion operation varies depending on the
timing at which the MUON command is input.
19/66
FEDL2256X-06
ML22Q563/ML2256X
Repeat Playback Set/Release Timing by the SLOOP and CLOOP Commands
SLOOP command
CLOOP command
PLAY command
2nd byte
VIH
VIL
CSB
SCK
SI
tINT
tcm
tCB2
VOH
VOL
CBUSYB
VO H
VOL
NCRn
(internal)
BUSYBn
(internal)
1/2VDD
SPM
1/2VDD
SPP
Awaiting command
Playing
Playing
Awaiting command
Status
Address is being
controlled
Address is being
controlled
Command is being processed
Timing of Volume Change by the CVOL Command
CVOL command
st byte
CVOL command
nd byte
1
2
CSB
SCK
SI
tCB1
tCB1
CBUSYBVOH
VOL
VOH
NCRn
(internal)
VOL
BUSYBn VOH
VOL
(internal)
Awaiting command
Awaiting command
Awaiting command
Status
Command is being
processed
Command is being
processed
20/66
FEDL2256X-06
ML22Q563/ML2256X
FUNCTIONAL DESCRIPTION
Synchronous Serial Interface
The CSB, SCK, SI, and SO pins are used to input various commands or read the status of the device.
For command input, after inputting a “L” level to the CSB pin, input data through the SI pin with MSB first in
sync with the SCK clock signal. The data input through the SI pin is shifted into the LSI in sync with the SCK
clock signal, then the command is executed at the eighth pulse of the rising or falling edge of the SCK clock.
For status reading, after a “L” level is input to the CSB pin, stauts is output from the SO pin in sync with the
SCK clock signal.
Choosing between rising edges and falling edges of the clock pulses input through the SCK pin is determined by
the signal input through the DIPH pin:
- When the DIPH pin is at a “L” level, the data input through the SI pin is shifted into the LSI on the rising edges
of the SCK clock pulses and a status signal is output from the SO pin on the falling edges of the SCK clock
pulses.
- When the DIPH pin is at a “H” level, the data input through the SI pin is shifted into the LSI on the falling
edges of the SCK clock pulses and a status signal is output from the SO pin on the rising edges of the SCK clock
pulses.
It is possible to input commands even with the CSB pin tied to a “L” level. However, if unexpected pulses
caused by noise etc. are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a
failure in normal input of command. In addition, the serial interface can be brought back to its initial state by
driving the CSB pin at a “H” level.
When the CSB pin is at ta “L” level, the status of each channel is output serially in sync with the SCK clock.
When the CSB pin is at a ”H” level, the SO pin goes into a high impedance state.
• Command Input Timing: SCK rising edge operation (when DIPH pin = “L” level)
CSB
SCK
D7
(MSB)
D6
D5
D4
D3
D2 D1
D0
(LSB )
SI
• Command Input Timing: SCK falling edge operation (when DIPH pin = “H” level)
CSB
SCK
D7
(MSB)
D6
D5
D4
D3
D2 D1
D0
(LSB )
SI
• Command Output Timing: SCK falling edge operation (when DIPH pin = “L” level)
CSB
SCK
(MSB)
D7
(LSB )
D2 D1 D0
D6
D5
D4
D3
SO
Command Output Timing: SCK rising edge operation (when DIPH pin = “H” level)
CSB
SCK
(MSB)
D7
(LSB )
D2 D1 D0
D6
D5
D4
D3
SO
21/66
FEDL2256X-06
ML22Q563/ML2256X
To prevent malfunction caused by serial interface pin noise, the ML22Q563/ML2256X is provided with the
two-time command input mode, where the user inputs one command two times. Use the PUP command to set
the two-time command input mode. For the method of setting the two-time command input mode, see the the
section on “1. PUP command” described later.
In two-time command input mode, input one command two times in succession. Then, the command becomes
valid only when the data input first matches the data input second. After the first data input, if a data mismatch
occurs when the second data is input, a ”H” level is output from the ERR pin. An error, if occurred, can be
cleared by the ERCL command.
PLAY command
1st byte
PLAY command
1st byte
PLAY command
2nd byte
PLAY command
2nd byte
CSB
SCK
SI
tCB1
tCB2
CBUSYB VOH
VOL
VOH
NCRn
(internal)
VOL
VOH
BUSYBn
(internal)
VOL
1/2VDD
SPM
1/2VDD
SPP
Address is being
controlled
Awaiting command
Awaiting command
Awaiting command
Command is being
Awaiting command
Playing
Awaiting command
Status
Command is being
processed
Command is being
processed
processed
22/66
FEDL2256X-06
ML22Q563/ML2256X
Voice Synthesis Algorithm (Common to ML22Q563 and ML2256X)
The ML22Q563/ML2256X contains four algorithm types to match the characteristic of playback voice:
HQ-ADPCM algorithm, 8-bit straight PCM algorithm, 8-bit non-linear PCM algorithm, and 16-bit straight PCM
algorithm.
Key feature of each algorithm is described in the table below.
Voice synthesis
Feature
algorithm
Algorithm that enables high sound quality and high
HQ-ADPCM
compression, which have been achieved by the improved
4-bit ADPCM that uses variable bit-length coding.
Algorithm that plays back mid-range of waveform as 10-bit
equivalent voice quality.
8-bit Nonlinear PCM
8-bit PCM
Normal 8-bit PCM algorithm
16-bit PCM
Normal 16-bit PCM algorithm
23/66
FEDL2256X-06
ML22Q563/ML2256X
Memory Allocation and Creating Voice Data
The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM
area.
The voice control area manages the ROM’s voice data. It contains data for controlling the start/stop addresses
of voice data for 1024 phrases, use/non-use of the edit ROM function and so on.
The test area contains data for testing.
The voice area contains actual waveform data.
The edit ROM area contains data for effective use of voice data. For the details, refer to the section on “Edit
ROM Function.”
No edit ROM area is available unless the edit ROM is used.
The ROM data is created using a dedicated tool.
Configuration of ROM data (for ML22Q563/ML22563)
0x00000
Voice control area
(Fixed 64 Kbits)
0x01FFF
0x02000
Test area
0x0206F
0x02070
Voice area
max: 0x7FEBF
Edit ROM area
Depends on creation
of ROM data.
max: 0x7FEBF
0x7FEC0
Filter area
max: 0x7FFFF
Playback Time and Memory Capacity
The playback time depends on the memory capacity, sampling frequency, and playback method.
The equation showing the relationship is given below.
The equation below gives the playback time when the edit ROM function is not used.
1.024 × (Memory capacity − 64) (Kbits)
Playback time =
(sec)
Sampling frequency (kHz) × Bit length
Example: Let the sampling frequency be 16 kHz and HQ-ADPCM algorithm. Then the playback time is
approx. 80 seconds, as shown below.
1.024 × (4096 − 64) (Kbits)
Playback time =
≅ 80 (sec)
16 (kHz) × 3.2 (bits) (average)
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FEDL2256X-06
ML22Q563/ML2256X
Edit ROM Function
With the edit ROM function, multiple phrases can be played in succession. The following functions can be
configured using the edit ROM function:
x Continuous playback:
There is no limit to the continuous playback count that can be specified. It
depends on the memory capacity only.
x Silence insertion: 20 to 1024 ms
Using the edit ROM function enables an effective use of the memory capacity of voice ROM.
Below is an example of the ROM configuration in the case of using the edit ROM function.
Examples of Phrases Using the Edit ROM Function
A
A
E
E
A
B
C
D
D
Phrase 1
Phrase 2
Phrase 3
Phrase 4
Phrase 5
B
C
D
D
B
D
Silence
E
B
D
Example of ROM Data Where the Contents Above Are Stored in ROM
Address control
area
A
B
C
D
E
Editing area
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FEDL2256X-06
ML22Q563/ML2256X
Mixing Function
The ML22Q563/ML2256X can perform simultaneous mixing of four channels. It is possible to specify FADR,
PLAY, STOP, and CVOL for each channel separately.
• Precautions for Waveform Clamp at the Time of Channel Mixing
If channel mixing is done, the possibility of an occurrence of a clamp increases from the mixing calculation point
of view. If it is known beforehand that a clamp will occur, then adjust the sound volume of each channel using
the VOL command.
• Mixing of Different Sampling Frequency
It is not possible to perform channel mixing by a different sampling frequency group.
When performing channel mixing, the sampling frequency group of the first playback channel is selected.
Therefore, note that if channel mixing is performed by a sampling frequency group other than the selected
sampling frequency group, then the playback will not be of constant speed: some times faster and at other times
slower.
The available sampling groups for channel mixing by a different sampling frequency are listed below.
8.0 kHz, 16.0 Hz, 32.0 kHz
12.0 kHz, 24.0 kHz, 48 kHz
6.4 kHz, 12.8 kHz, 25.6 kHz
… (Group 1)
… (Group 2)
… (Group 3)
Figures below show cases where a phrase is played at a sampling frequency belonging to a different sampling
frequency group.
fs＝16.0kHz（Invalid、Will be played as fs＝12.8kHz）
fs＝16.0kHz
Channel 0
Channel 1
fs＝25.6kHz
Figure 1 Case where a phrase is played at a sampling frequency belonging to a different
sampling frequency group during playback on channels 0 and 1
Played normally if not being played by
other channel.
fs = 16.0 kHz
Channel 0
Channel 1
fs = 25.6 kHz (Valid)
End of channel 1
Figure 2 Case where a phrase is played at a sampling frequency belonging to a different
sampling frequency group after playback is finished at the other channel
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FEDL2256X-06
ML22Q563/ML2256X
Command List
Each command is configured in 1-byte (8-bit) units. Each of the AMODE, AVOL FADR, PLAY, MUON, and
CVOL commands forms one command by two bytes. Be sure to input the following commands only.
Input each command with CBUSYB set to a ”H” level.
Command D7
D6
D5
D4
D3
D2
D1
D0
Description
Shifts the device currently
powered down to a command
PUP
0
0
0
0
0
0
0
WCM wait state. Also the two-time
command input mode is set
by this command.
Analog section control
command.
Configures settings for
power-up operation and
0
0
0
0
0
0
1
HPF1
SPEN
HPF0
AMODE
AVOL
DAG1 DAG0 AIG1 AIG0
DAEN
POP
analog input/output.
Selects the type of HPF.
Analog mixing signal volume
setting command. Use the
data of the 2nd byte to
specify volume.
0
—
0
0
—
0
0
AV5
0
0
AV4
0
1
AV3
1
0
AV2
1
0
AV1
0
0
AV0
Sets the fade-in time in cases
where the speaker amplifier
is enabled by the AMODE
command.
0
FAD
0
0
0
0
FAD3
FAD2
FAD1
FAD0
Shifts the device from a
PDWN
FADR
0
0
1
0
0
0
0
0
command wait state to a
power-down state.
Playback phrase specification
command.
Can be specified for each
channel.
0
F7
0
0
F6
1
1
F5
0
1
F4
0
C1
F3
C1
C0
F2
C0
F9
F1
F9
F8
F0
F8
Playback start command.
Use the data of the 2nd byte
to specify a phrase number.
Can be specified for each
channel.
PLAY
F7
F6
F5
F4
F3
F2
F1
F0
Playback start command
without phrase specification.
Used to start playback on
multiple channels at the same
time after phrases are
START
0
0
1
1
0
1
1
0
CH3
CH3
CH2
CH2
CH1
CH1
CH0 specified with the FADR
command. After a phrase is
played with the PLAY
command, the same phrase
can be played with this
command.
Playback stop command.
CH0 Can be specified for each
channel.
STOP
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FEDL2256X-06
ML22Q563/ML2256X
Command D7
0
D6
1
D5
1
D4
1
D3
D2
D1
D0
Description
Silence insertion command.
Use the data of the 2nd byte
to specify the length of
silence. Can be specified
for each channel.
CH3
CH2
CH1
CH0
MUON
M7
M6
M5
M4
M3
M2
M1
M0
Repeat playback mode
setting command. The
setting is enabled during
playback.
Can be specified for each
channel.
SLOOP
CLOOP
1
1
0
0
0
CH3
CH2
CH1
CH0
Repeat playback mode
release command. When
the STOP command is input,
0
0
1
CH3
CH2
CH1
CH0 repeat playback mode is
released automatically. Can
be specified for each
channel.
Volume setting command.
Use the data of the 2nd byte
to specify volume. Can be
specified for each channel.
Status serial read command.
This command reads the
command status and the
status of the fail safe function
for each channel.
1
0
1
0
CH3
CV3
CH2
CV2
CH1
CV1
CH0
CVOL
—
—
—
CV4
CV0
ERR
C0
RDSTAT
1
0
1
1
0
0
0
Status output command.
This command outputs the
command status of each
channel from the STATUS
pin.
0
0
BUSY/NCR
C1
OUTSTAT
1
1
1
1
0
0
0
1
Fail safe setting command.
Sets settings for power
supply voltage detection,
temperature detection, and
monitoring time.
0
0
0
SAFE
ERCL
TM2 TM1
TM0 TSD1 TSD0
BLD2
BLD1
BLD0
This command clears error
while the fail safe function is
operating.
1
1
1
1
1
1
1
1
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Description of Command Functions
1. PUP command
x command
0
0
0
0
0
0
0
WCM
The PUP command is used to shift the ML22Q563/ML2256X from a power down state to a command waiting
state.
The ML22Q563/ML2256X can only accept the PUP command while it is in a power down state. Therefore, in
a power down state, the device will ignore any other command if entered.
The ML22Q563/ML2256X enters a power down state under any of the following conditions:
1) When power is turned on
2) At RESETB input
3) When CBUSYB go to a “H” level after inputting the power down command
CS B
S C K
tP UP
SI
C B U S Y B
O scillatio n sto pp ed
O sc illating
X T xXT B
R eset bein g
processed
S tat us
P ow er d ow n
A wa itin g co mm and
O sc illatio n sta bilized
The WCM bit is used to set the two-time command input mode. When set to ”1”, the command input thereafter
will be processed in two-time command input mode and becomes valid only when the first data input matches
the second one.
WCM Two-time command input mode
0
1
No (initial value)
Yes
The regulator starts operating after the PUP command is entered. Any command will be ignored if entered
while oscillation is stabilized. However, if a “L” level is input to the RESETB pin, the LSI enters a power
down state immediately.
Neither line output nor speaker output is enabled by the PUP command. Power up the analog section by the
AMODE command.
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2. AMODE command
x command
0
0
0
0
0
0
1
HPF1
HPF0
POP
1st byte
2nd byte
DAG1 DAG0 AIG1 AIG0 DAEN SPEN
The AMODE command is used to configure various settings for the analog section.
If the PDWN command is input while the analog section is in the power-up state, the analog section enters a
power down state under the setting conditions that were in effect when the analog section was powered up by the
AMODE command. To perform a power-down operation using different conditions from those used at analog
section power-up, set settings by the AMODE command.
To change the setting of DAEN/SPEN while the analog section is in the power-up state, first put the analog
section into the power-down state and then put the analog section into the power-up state again by the AMODE
command.
The detailed command settings are shown below.
Each setting is initialized upon reset release or by the PUP command.
Don’t input the STOP command during the AMODE command is being proccessed (CBUSYB=”L”).
Input the AMODE command for analog section into the power-down state before the PDWN command is input.
The HPF1/HPF0 bits set the cut-off frequency of the HPF.
HPF1
HPF0
Cut-off frequency
Off (initial value)
200 Hz
300 Hz
400 Hz
0
0
1
1
0
1
0
1
The POP bit specifies whether to suppress generation of “pop” noise.
- If the bit is “0” (no pop noise suppression) and the DAEN bit is “1”, the LINE output rises from the DGND
level to the SG level in about 35 ms, at which time the analog section enters the power-up state. If the DAEN
bit is “0”, the LINE output falls from the SG level to the DGND level in about 110 ms, at which time the
analog section enters the power down state.
- If the bit is “1” (with pop noise suppression) and the DAEN bit is “1”, the LINE output rises from the DGND
level to the SG level in about 90 ms, at which time the analog section enters the power-up state. If the DAEN
bit is “0”, the LINE output falls from the SG level to the DGND level in about 140 ms, at which time the
analog section enters the power down state.
POP
Pop noise suppression
0
1
No (initial value)
Yes
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x When powering up the speaker amplifier and line amplifier (without pop noise suppression)
Setting values: POP bit = “0”, DAEN and SPEN bits = “0” → “1”
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB1
tPUPA1
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
LINE output GN D
(internal)
1/2SPVDD
1/2SPVDD
Hi-Z
SPM
GN D
SPP
Command is being
processed
Status
Awaiting command
Awaiting command
Awaiting command
Command is being
processed
x When powering up the line amplifier (with pop noise suppression)
Setting values: POP bit = “1”, DAEN bit = “0” → “1” (SPEN bit = “0”)
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB 1
tPUPA2
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
1V
SPP
GND
(LINE output)
Awaiting command
POP noise suppressed
Status
Awaiting command
Awaiting command
Command is being
processed
Command is being
processed
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x When putting the line amplifier into the power down state (without pop noise suppression) and putting the
speaker amplifier into the power down state
Setting values: PUP bit = “0”, DAEN and SPEN bits = “1” → “0”
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB1
tPDA1
VO H
VOL
CBUSYB
VO H
VOL
NCR
(internal)
VO H
VOL
BUSYB
(internal)
1V
LINE output
SPM
GND
Hi-Z
1/ 2VDD
1/ 2VDD
SPP
GND
Command is being
processed
Status
Awaiting command
Awaiting command
Awaiting command
Command is being
processed
x When putting the line amplifier into the power down state (with pop noise suppression)
Setting values: POP bit = “1”, DAEN bit = “1” → “0” (SPEN bit = “0”)
AMODE command
1st byte
AMODE command
2nd byte
CSB
SCK
SI
tCB1
tPDA2
VOH
VOL
CBUSYB
VOH
VOL
NCR
(internal)
VOH
VOL
BUSYB
(internal)
1V
SPP
GND
(LINE output)
Awaiting command
POP noise suppressed
Status
Awai ting command
Awaiting command
Command is being
processed
Command is being
processed
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The DAG1,0 bits are used to set the gain of the internal DAC signal. The AIG1,0 bits are used to set the gain
of an analog signal from the AIN pin. DAG1,0 and AIG1,0 are only enabled when the speaker amplifier is
used.
DAG1 DAG0
Volume
0
0
1
1
0
1
0
1
Input OFF
Input ON (–6 dB)
Input ON (0 dB) (initial value)
Input ON (0 dB) (Setting prohibited)
AIG1
AIG0
Volume
0
0
1
1
0
1
0
1
Input OFF (initial value)
Input ON (–6 dB)
Input ON (0 dB)
Input ON (0 dB) (Setting prohibited)
Input the analog signal from the AIN pin after the AMODE command (CBUSYB=”H”).
The DAEN bit takes power-up and power-down control of the DAC section.
DAEN
Status of the DAC section
0
1
Power-down state (initial value)
Power-up state
The SPEN bit takes power-up and power-down control of the speaker section.
When the SPEN bit = “0”, the SPP pin is configured as a LINE output.
SPEN
Status of the speaker section
0
1
Power-down state (initial value)
Power-up state
Relationship between DAEN, SPEN, and POP signals and the analog section
DAEN
SPEN POP
Mode
Status
At speaker output
Power-down (initial value)
0
0
0
Power-down (without pop noise
suppression)
At LINE output
Power-down
Power-down (with pop noise
suppression)
At speaker output
At LINE output
0
0
1
DAC/speaker power-up
―
1
0
―
Speaker output
LINE output
DAC power-up (without pop noise
suppression)
1
0
DAC power-up (with pop noise
suppression)
1
0
1
LINE output
Pin status during power down
The status of each output pin during power down by the AMODE command is shown below.
Analog output pin
State
DGND
DGND
DGND
Hi-Z
VDDL
VDDR
SG
SPM
SPP
DGND
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3. AVOL command
x command
0
0
0
0
0
0
1
0
0
0
1st byte
2nd byte
AV5 AV4 AV3 AV2 AV1
AV0
The AVOL command is used to adjust the volume of the speaker amplifier. It is possible to input the AVOL
command regardless of the status of the NCR signal.
The command enables 50-level adjustment of volume, as shown in the table below. When the PUP or AMODE
command is input, the value set by the AVOL command is initialized (0 dB).
AV5–0
3F
3E
3D
3C
3B
3A
39
38
37
36
35
34
33
32
31
30
2F
2E
2D
2C
2B
2A
29
28
27
26
25
24
23
22
21
20
Volume
+12dB
AV5–0
1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
11
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
00
01
00
Volume
−8.0
−9.0
+11.5
+11.0
+10.5
+10.0
+9.5
+9.0
+8.5
+8.0
+7.5
+7.0
+6.5
+6.0
+5.5
+5.0
+4.5
+4.0
+3.5
+3.0
+2.5
+2.0
+1.5
+1.0
+0.5
+0.0 (initial value)
−1.0
−2.0
−3.0
−4.0
−5.0
−6.0
−10.0
−11.0
−12.0
−13.0
−14.0
−16.0
−18.0
−20.0
−22.0
−24.0
−26.0
−28.0
−30.0
−32.0
−34.0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
−7.0
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4. FAD command
x command
0
0
0
0
0
0
0
0
1
1
0
0
1st byte
2nd byte
FAD3
FAD2
FAD1
FAD0
The FAD command is used to set the fade-in time for the speaker amplifier.
The fade-in time cna be adjusted through 16 levels, as shown in the table below. The initial value after reset is
298 μs. When the PUP command is input, the value set by the FAD command is initialized (298 μs).
FAD3–0 Fade-in time (μs)
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
442
422
401
381
360
340
319
298 (initial value)
278
257
237
216
195
175
154
134
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5. PDWN command
x command
0
0
1
0
0
0
0
0
The PDWN command is used to shift the ML22Q563/ML2256X from a command waiting state to the power
down state. However, since every setting will be initialized after entering the power down state, initial settings
need to be set after power-up. This command is invalid during playback.
To resume playback after the ML22Q563/ML2256X has shifted to the power down state, first input the PUP and
AMODE commands and then input the PLAY command.
CSB
SCK
SI
CBUSYB
NCR
(internal)
BUSYB
(internal)
Oscillation
Oscillating
stopped
XT•XTB
Command is being
processed
Status
Awaiting command
Power down
Oscillation stops after a lapse of command processing time after the PDWN command is input. The regulator
stops operation after a lapse of command processing time after the PDWN command is input. At this time, the
SPM output of the speaker amplifier goes into a Hi-Z state to prevent generation of pop noise.
Initial stauts at reset input and status during power down
The status of each output pin is as follows:
Analog output pin
State
DGND
DGND
DGND
Hi-Z
VDDL
VDDR
SG
SPM
SPP
DGND
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6. FADR command
x command
0
0
1
1
C1
F3
C0
F2
F9
F1
F8
F0
1st byte
2nd byte
F7
F6
F5
F4
The FADR command is used to specify a phrase to be played. A playback channel and a playback phrase are
set by this command. The FADR command can be set for each channel; however, the command cannot be
input for multiple channels simultaneously. Input the FADR command with each NCR set to a ”H” level.
When a playback phrase is specified for each channel, use the START command to start playback.
Since it is possible to specify a playback phrase (F9–F0) at the time of creating a ROM that stores voice data,
specify the phrase that was specified when the ROM was created.
Channel settings
C1
0
C0
0
Channel
Channel 0
Channel 1
Channel 2
Channel 3
0
1
1
0
1
1
The diagram below shows the timing for specifying (F9–F0) = 02H as the phrase to play on channel 1.
FADR
FADR
command
command
1st byte
2nd byte
CSB
SCK
SI
CBUSYB
NCR
(internal)
BUSYB
(internal)
Awaiting command
Awaiting command
Awaiting command
Status
Command is being
processed
Command is being
processed
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7. PLAY command
x command
0
1
0
0
C1
F3
C0
F2
F9
F1
F8
F0
1st byte
2nd byte
F7
F6
F5
F4
The PLAY command is used to start playback with phrase specified. This command can be input when the
NCR signal on the target channel is at a “H” level.
Since it is possible to specify a playback phrase (F9–F0) at the time of creating a ROM that stores voice data,
specify the phrase that was specified when the ROM was created.
The figure below shows the timing of phrase (F9–F0 = 01H) playback.
PLAY command
1st byte
PLAY command
2nd byte
CSB
SCK
SI
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2VDD
SPM
1/2VDD
SPP
Address is being
controlled
Awaiting command
Awaiting command
Playing
Awaiting command
Status
Command is being processed
When the 1st byte of the PLAY command is input, the device enters a state awaiting input of the 2nd byte of the
PLAY command after a lapse of command processing time. When the 2nd byte of PLAY command is input,
after a lapse of command processing time, the device starts reading from the ROM the address information of the
phrase to be played. Thereafter, playback operation starts, the playback is performed up to the specified ROM
address, and then the playback terminates automatically.
The NCR signal is at a “L” level during address control, and goes “H” when the address control is finished and
playback starts. When the NCR signal on the target channel goes “H”, it is possible to input the PLAY
command for the next playback phrase.
During address control, the BUSYB signal is at a “L” level during playback and goes “H” when playback is
finished. Whether the playback is going on can be known by the BUSYB signal.
Channel settings
C1
0
C0
0
Channel
Channel 0
Channel 1
Channel 2
Channel 3
0
1
1
0
1
1
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PLAY Command Input Timing for Continuous Playback
The diagram below shows the PLAY command input timing in cases where one phrase is played and then the
next phrase is played in succession.
PLAY command
2nd byte
PLAY command PLAY command
1st byte 2nd byte
CSB
SCK
SI
tcm
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2VDD
SPM
1/2VDD
SPP
Awaiting command
Playing phrase 1
Playing phrase 2
Status
Address is being controlled
Address is being controlled
As shown in the diagram above, if performing continuous playback, input the PLAY command for the second
phrase within 10 ms (tcm) after the NCR signal on the target channel goes “H”. Doing so will start playing the
second phrase immediately after the playback of the first phrase finishes. Phrases can thus be played
continuously without silence being inserted between phrases.
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8. START command
x command
0
1
0
1
CH3 CH2 CH1 CH0
The START command is a channel synchronization start (i.e., starts phrase playback on multiple channels
simultaenously) command. It is necessary to specify playback phrases using the FADR command before
inputting the START command. Setting any bit(s) from CH0 to CH3 to “1” starts playback on the
corresponding channel(s). Input the START command with each NCR set to a ”H” level.
The figure below shows the timing when starting playback on channel 0 and channel 1 simultaneously.
Channel settings
Channel
CH0
CH1
CH2
CH3
Setting this bit to “1” starts playback on channel 0.
Setting this bit to “1” starts playback on channel 1.
Setting this bit to “1” starts playback on channel 2.
Setting this bit to “1” starts playback on channel 3.
Be sure to set the channel setting bits( CH0-CH3).
START command
CSB
SCK
SI
tcB2
CBUSYB
NCR0
(internal)
NCR1
(internal)
BUSYB0
(internal)
BUSYB1
(internal)
SPP output
Address is
being controlled
Awaiting
command
Awaiting
command
Playing
Status
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9. STOP command
x command
0
1
1
0
CH3 CH2 CH1 CH0
The STOP command is used to stop playback. It can be set for each channel. Setting any bit(s) from CH0 to
CH3 to “1” stops playback on the corresponding channel(s). If the speech synthesis processing for all channels
stops, the AOUT output goes to the VSG level and the NCR and BUSYB signals go to a “H” level.
Although it is possible to input the STOP command regardless of the status of NCR during playback, a
prescribed command interval time needs taking.
STOPcommand
CSB
SCK
SI
CBUSYB
NCR
fs×29cycle
(internal)
BUSYB
(internal)
1/2VDD
SPM
1/2VDD
SPP
Command is being
processed
Playing
Awaiting
Status
Channel settings
Channel
CH0
Setting this bit to “1” stops playback on channel 0.
Setting this bit to “1” stops playback on channel 1.
Setting this bit to “1” stops playback on channel 2.
Setting this bit to “1” stops playback on channel 3.
CH1
CH2
CH3
Be sure to set the channel setting bits( CH0- CH3).
The STOP command allows specifying multiple channels at one time.
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10. MUON command
x command
0
1
1
1
CH3 CH2 CH1 CH0
M3 M2 M1 M0
1st byte
2nd byte
M7
M6
M5
M4
The MUON command allows inserting a silence between two playback phrases. The command can be input
when the NCR signal on the target channel is at a “H” level.
Set the silence time length after inputting this command. It can be set for each channel. The MUON
command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1” plays
silence on the corresponding channel(s).
Channel settings
Channel
CH0
CH1
CH2
CH3
Setting this bit to “1” inserts a silence on channel 0.
Setting this bit to “1” inserts a silence on channel 1.
Setting this bit to “1” inserts a silence on channel 2.
Setting this bit to “1” inserts a silence on channel 3.
Be sure to set the channel setting bits( CH0- CH3).
As the silence length (M7–M0), a value between 20 ms and 1024 ms can be set at 4 ms intervals (252 steps in
total).
The equation to set the silence time length is shown below.
The silence length (M7–M0) must be set to 04h or higher.
tmu=(27×(M7)+26×(M6)+25×(M5)+24×(M4)+23×(M3)+22×(M2)+21×(M1)+20×(M0)+1)×4ms
The figure below shows the timing of inserting a silence of 20 ms between the repetitions of a phrase of (F7–F0)
= 01h.
PLAY command
2nd byte
MUON command MUON command
1st byte 2nd byte
PLAY command PLAY command
1st byte 2nd byte
CSB
SCK
SI
tcm
tcm
CBUSYB
NCR
(internal)
BUSYB
(internal)
1/2VDD
SPM
1/2VDD
SPP
Awaiting command
Playing
Silence is being inserted
Playing
Status
Waiting for silence insertion
to be finished
Address is being controlled
Waiting for playback to be finished
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When the PLAY command is input, the address control over phrase 1 ends, the phrase playback starts, and the
CBUSYB and NCR signals go to a “H” level. Input the MUON command after this CBUSYB signal changes
to a “H” level. After the MUON command input, the NCR signal remains “L” until the end of phrase 1
playback, and the device enters a state waiting for the phrase 1 playback to terminate.
When the phrase 1 playback is terminated, the silence playback starts and the NCR signal goes to a “H” level.
After the NCR signal has gone to a “H” level, re-input the PLAY command in order to play phrase 1.
After the PLAY command input, the NCR signal once again goes to a “L” level and the device enters a state
waiting for the termination of silence playback.
When the silence playback is terminated and then the phrase 1 playback starts, the NCR signal goes “H”, and the
device enters a state where it is possible to input the next PLAY or MUON command.
The BUSYB signal remains “L” until the end of a series of playback.
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11. SLOOP command
x command
1
0
0
0
CH3 CH2 CH1 CH0
The SLOOP command is used to set repeat playback mode. The command can be input for each channel.
The SLOOP command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to
“1” repeats playback on the corresponding channel(s). Input the SLOOP command with each NCR set to a ”H”
level.
Channel settings
Channel
CH0
CH1
CH2
CH3
Setting this bit to “1” repeats playback on channel 0.
Setting this bit to “1” repeats playback on channel 1.
Setting this bit to “1” repeats playback on channel 2.
Setting this bit to “1” repeats playback on channel 3.
Be sure to set the channel setting bits( CH0- CH3).
Once repeat playback mode is set, the current phrase is repeatedly played until the repeat playback setting is
released by the SLOOP command or until playback is stopped by the STOP command. In the case of a phrase
that was edited using the edit function, the edited phrase is repeatedly played. Following shows the SLOOP
command input timing.
PLAY command
2nd byte
SLOOP command
CLOOP command
CSB
SCK
SI
CBUSYB
NCR
(internal)
tcm
BUSYB
(internal)
1/2VDD
SPM
1/2VDD
SPP
Awaiting command
Playi ng
Playing
Awaiting command
Status
Address is being controlled
Address is being controlled
Command is being processed
Effective Range of SLOOP Command Input
The SLOOP command is only enabled during playback. After the PLAY command is input, input the SLOOP
command within 10 ms (tcm) after the NCR signal on the target channel goes “H”. This will enable the SLOOP
command, so that repeat playback will be carried out. The NCR signal remains “L” during repeat playback
mode.
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12. CLOOP command
x command
1
0
0
1
CH3 CH2 CH1 CH0
The CLOOP command releases repeat playback mode. The command can be input for each channel. The
CLOOP command allows specifying multiple channels at one time. Setting any bit(s) from CH0 to CH3 to “1”
releases repeat playback on the corresponding channel(s). When repeat playback mode is released, the NCR
signal goes “H”.
It is possible to input the CLOOP command regardless of the status of the NCR signal during playback, but a
prescribed command interval needs taking.
Channel settings
Channel
CH0
CH1
CH2
CH3
Setting this bit to “1” releases repeat playback on channel 0.
Setting this bit to “1” releases repeat playback on channel 1.
Setting this bit to “1” releases repeat playback on channel 2.
Setting this bit to “1” releases repeat playback on channel 3.
Be sure to set the channel setting bits( CH0- CH3).
PLAY command
2nd byte
SLOOP command
CLOOP command
CSB
SCK
SI
CBUSYB
NCR
(internal)
tcm
BUSYB
(internal)
1/2VDD
SPM
1/2VDD
SPP
Awaiting command
Playing
Playing
Awaiting command
Status
Address being
controlled
Command being
processed
Command being
processed
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13. CVOL command
x command
1
0
0
0
1
0
0
CH3 CH2 CH1 CH0
1st byte
2nd byte
CV4 CV 3 CV 2 CV 1 CV 0
The CVOL command is used to adjust the playback volume on each channel. It is possible to input the VOL
command regardless of the status of the NCR signal.
The CVOL command can be set for each channel. The CVOL command allows specifying multiple channels at
one time. Setting any bit(s) from CH0 to CH3 to “1” sets the playback volume on the corresponding channel(s).
The volume setting is initialized by the AMODE command.
Channel settings
Channel
CH0
CH1
CH2
CH3
Setting this bit to “1” sets the volume on channel 0.
Setting this bit to “1” sets the volume on channel 1.
Setting this bit to “1” sets the volume on channel 2.
Setting this bit to “1” sets the volume on channel 3.
Be sure to set the channel setting bits( CH0- CH3).
The command enables 32-level adjustment of volume, as shown in the table below. The initial value after reset
release is set to 0 dB. Upon reset release or when the PUP command is input, the values set by the CVOL
command are initialized.
CV4–0
1F
1E
1D
1C
1B
1A
19
18
17
16
15
Volume
0 dB (initial value)
−0.28
CV4–0
0F
0E
0D
0C
0B
0A
09
08
07
06
05
Volume
−6.31
−6.90
−7.55
−8.24
−0.58
−0.88
−1.20
−1.53
−1.87
−2.22
−2.59
−2.98
−3.38
−3.81
−4.25
−4.72
−5.22
−5.74
−9.00
−9.83
−10.74
−11.77
−12.93
−14.26
−15.85
−17.79
−20.28
−23.81
−29.83
OFF
14
13
12
11
04
03
02
01
10
00
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14. RDSTAT command
x command
1
0
1
1
0
0
0
ERR
The RDSTAT command enables reading the status of internal operation. It is possible to input the RDSTAT
command regardless of the status of the NCR signal during playback, but a prescribed command interval needs
taking.
The ERR bit selects reading the playback status for each channel or reading the status of the fail-safe function.
Keep the SI pin to “L” when read the status.
ERR
Content of data to read
0
1
NCR and BUSYB signals for each channel (Initial value)
Status of the fail-safe function
If the ERR bit is set to ”0”, the following status will be read:
Output bit
Output
data
D7
D6
D5
D4
D3
-
D2
-
D1
D0
-
-
BUSYB1
BUSYB0
NCR1
NCR0
When the ERR bit = ”0”, the NCR and BUSYB signals of each channel are read. The NCR signal outputs a
“L” level while this LSI is performing command processing and goes to a “H” level when the LSI enters a
command waiting state. The BUSY signal outputs a “L” level during voice playback.
The table below shows the contents of each data output at a status read.
Output status signal
BUSY1
BUSY0
NCR1
NCR0
Channel 1 BUSYB output
Channel 0 BUSYB output
Channel 1 NCR output
Channel 0 NCR output
If the ERR bit is set to ”1”, the following status will be read:
Output bit
D7
0
D6
0
D5
0
D4
0
D3
0
D2
D1
D0
Output data
TSDERR
BLDERR
WCMERR
When the ERR bit = ”1”, the status of each fail-safe function is read. If any of the following three fail-safe
functions is activated, the ERR pin is set to a “H” level and the corresponding error bit is set to “1”. If the ERR
pinis set to a “H” level, check the error contents using the RDSTAT command and take appropriate measures.
Error signal
Error contents
High temperature error bit.
TSDERR
This bit is set to “1” if the temperature of the LSI reaches or exceeds the temperature set by the
SAFE command. For details see the section on the SAFE command.
Power supply voltage error bit.
BLDERR
This bit is set to “1” if the power supply voltage level reaches or falls below the voltage set by
the SAFE command. For details see the section on the SAFE command.
Command tansfer errro bit.
WCMERR
This bit is set to “1” if a transfer error occurs in two-time command input mode.
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15. OUTSTAT command
x command
1
1
0
0
0
BUSY/NCR
C1
C0
The OUTSTAT command is used to output the BUSYB or NCR signal on the specified channel from the
STATUS pin. It is possible to input the OUTSTAT command regardless of the status of the NCR signal during
playback, but a prescribed command interval needs taking.
OUTSTAT command
OUTSTAT command
CSB
SCK
CSB
SCK
SI
SI
CBUSYB
CBUSYB
NCR
(internal)
NCR
(internal)
BUSYB
(internal)
BUSYB
(internal)
STATUS
STATUS
BUSY/NCR
STATUS pin status
Outputs the NCR signal on the specified channel.
Outputs the BUSYB signal on the specified channel.
0
1
Channel settings
C1
C0
Channel
Channel 0 (initial value)
Channel 1
0
0
1
1
0
1
0
1
Channel 2
Channel 3
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16. SAFE command
x command
1
1
0
1
0
0
0
0
TM2 TM1 TM0 TSD1 TSD0 BLD2 BLD1 BLD0
The SAFE command is sets the settings for the low-voltage detection and temperature detection functions.
The BLD2–0 bits are used to set the power supply voltage detection level. The judgment voltage can be
selected from among six levels from 2.7 to 4.0 V. The power supply voltage is monitored each time it reaches
the value set by TM2–0, and if the power supply voltage reaches or falls below the set detection voltage two
times or more, the ERR pin outputs a ”H” level and the RDSTAT command’s BLDERR bit is set to ”1”.
If the ERR pin is set to a ”H” level, check the error contents using the RDSTAT command. If the BLDERR bit
is at ”1”, it is possibly a power supply related failure.
BLD2 BLD1 BLD0 Judgment power supply voltage
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OFF
2.7V±5% (initial value)
3.0V±5%
3.3V±5%
3.6V±5%
4.0V±5%
(4.0V±5%)
(4.0V±5%)
The TSD1–0 bits are used to set the temperature detection level. Tj=140°C or OFF can be selected as the
judgment temperature. The temperature is monitored each time it reaches the value set by TM2–0, and if the
temperature reaches or exceeds the set value two times or more, the ERR pin outputs a ”H” level and the
RDSTAT command’s TSDERR bit is set to ”1”.
If the ERR pin is set to a ”H” level, check the error contents using the RDSTAT command. If the TSDERR bit
is at ”1”, reduce the volume using the AVOL command or put the analog section into the power down state
using the AMODE command.
TSD1 TSD0
Judgment temperature (Tj)
0
0
1
1
0
1
0
1
OFF
Setting prohibited
Setting prohibited
140±10°C (initial valle,)
The TM2–0 bits are used to set the monitor interval to detect a low voltage or temperature.
TM2 TM1 TM0
Monitor interval
Constantly monitors
2 ms (initial value)
4 ms
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8 ms
16 ms
32 ms
64 ms
128 ms
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17. ERCL command
x command
1
1
1
1
1
1
1
1
The ERCL command is used to clear an error if it occurs.
If an error occurs, a “H” level is output from the ERR pin. When the ERCL command is input, the ERR pin
outputs a ”L” level.
However, in the case of an error other than a transfer error indicated by the WCMERR bit of the RDSTAT
command, the ERR pin outputs a ”H” level and does not output a “L” level even if the ERCL command is input,
until the error state is cleared.
Timing diagram for when an error occurs at the time of setting the two-time command input mode
START command
2nd times
ERCL command
1st time
ERCL command
2nd times
VIH
VIL
CSB
SCK
SI
tINTC
tCB1
VOH
VOL
CBUSYB
VOH
VOL
NCRn
(internal)
BUSYBn
(internal)
ERR
RDSTAT
ERR register
(internal)
00h
01h
00h
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If a power supply voltage error occurs and then the power supply voltage is returned (when the SAFE
command’s BLD2–0 bits = 001h)
ERCL command
CSB
SCK
SI
tCB1
VOH
CBUSYB
VOL
RDSTAT
ERR register
00h
02h
00h
(internal)
ERR
3.0V
2.6V
3.0V
DVDD
If a power supply voltage error occurs but the power supply voltage is not returned
ERCL command
CSB
SCK
SI
tCB1
VOH
CBUSYB
VOL
RDSTAT
ERR register
00h
02h
(internal)
ERR
3.0V
2.6V
DVDD
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Command Flow Charts
1-Byte Command Input Flow (applied to the PUP, PDWN, START, STOP, SLOOP, CLOOP, OUTSTAT, and
ERCL commands)
Start
CBUSYB “H”?
N
Y
Input command
CBUSYB “H”?
N
Y
End
2-Byte Command Input Flow (applied to the AMODE, AVOL, FAD, FADR, PLAY, MUON, CVOL, and SAFE
commands)
Start
CBUSYB “H”?
N
Y
Input the 1st byte of command
CBUSYB “H”?
N
Y
Input the 2nd byte of command
CBUSYB “H”?
N
Y
End
Status Read Flow
RDSTAT command
CBUSYB “H”?
N
Y
Read status (SI=”L”)
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Power-On Flow
Apply power, Drive RESETB “L”
Waited for
10 μs?
N
Y
Drive RESETB “H”
Example of Power-Up Flow
Power-down state
PUP command
AMODE command
Example of Playback Start Flow
Power-up state
Single-channel playback
PLAY command
Multi-channel playback
FADR command
START command
Example of Playback Stop Flow
Playing
STOP command
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Loop Start Flow
Playing
SLOOP command
Loop Stop Flow
Looping
Stop after playback is finished all the
way through the phrase
Stop playback forcibly
CLOOP command
STOP command
Power-Down Flow
Power-up state
PDWN command
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Detailed Flow of “Power-Up ⇒ Playback ⇒ Power-Down”
Power-down state
A
CBUSYB “H”?
N
CBUSYB “H”?
N
Y
Y
PUP command
RDSTAT command
CBUSYB “H”?
N
CBUSYB “H”?
Y
N
Y
1st byte of AMODE command
Read status
CBUSYB “H”?
N
Y
BUSYB “H”?
Y
N
2nd byte of AMODE command
1st byte of AMODE command
CBUSYB “H”?
N
Y
CBUSYB “H”?
N
1st byte of PLAY command
Y
2nd byte of AMODE command
CBUSYB “H”?
N
Y
CBUSYB “H”?
Y
N
2nd byte of PLAY command
A
PDWN command
CBUSYB “H”?
N
Y
Power-down state
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1-Byte Command input flow of two-time command input mode
（applied to the PDWN,STOP,SLOOP,CLOOP,RDSTAT,OUTSTAT,and ERCL commands）
One-time command input
One-time ERCL command input
Two-time command input
Two-time ERCL command input
N
ERR ”L”
Y
N
N
ERR ”L”
N
CBUSYB ”H”
Y
Y
End
CBUSYB ”H”
Y
One-time command input(Re-input)
Two-time command input(Re-input)
N
ERR ”L”
N
CBUSYB ”H”
Y
End
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2-Byte Command input flow of two-time command input mode
（applied to the AMODE,AVOL,FAD,FADR,PLAY,MUON,CVOL, and SAFEcommands）
One-time command input (1Byte)
Two-time command input (1Byte)
One-time ERCL command input
Two-time ERCL command input
N
ERR ”L”
Y
N
N
ERR ”L”
N
CBUSYB ”H”
Y
Y
CBUSYB ”H”
Y
One-time command input(1Byte)(Re-input)
Two-time command input(1Byte) (Re-input)
N
ERR ”L”
N
CBUSYB ”H”
Y
One-time command input (2Byte)
Two-time command input (2Byte)
N
ERR ”L”
One-time ERCLcommand input
Two-time ERCLcommand input
Y
N
CBUSYB ”H”
N
Y
ERR ”L”
End
Y
N
CBUSYB ”H”
Y
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Handling of the SG Pin
The SG pin is the signal ground pin for the built-in speaker amplifier. Connect a capacitor between this pin and
the analog ground so that this pin will not carry noise.
The recommended capacitance value is shown below; however, it is recommended that the user determine the
capacitance value after evaluation.
Always start playback after each output voltage is stabilized.
Recommended
capacitance value
Pin
SG
Remarks
The larger the connection capacitance, the longer the speaker
amplifier output pin (SPM and SPP) voltage stabilization time.
0.1 μF ±20%
Handling of the VDDL and VDDR Pins
The VDDL and VDDR pins are the power supply pins for the internal circuits. Connect a capacitor between each
of these pins and the ground in order to prevent noise generation and power fluctuation.
The recommended capacitance value is shown below; however, it is recommended that the user determine the
capacitance value after evaluation.
Always start the next operation after each output voltage is stabilized.
Recommended
capacitance value
Pin
Remarks
The larger the connection capacitance, the longer the
stabilization time.
VDDL, VDDR
10 μF ±20%
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Power Supply Wiring
The power supplies of this LSI are divided into the following two:
• Digital power supply (DVDD) and Digital ground(DGND)
• Speaker amplifier power supply (SPVDD) and Speaker amplifier ground(SPGND)
As shown in the figure below, be sure to diverge the wiring of DVDD and SPVDD from the root of the same
power supply. DGND/SPGND is similar, too.
DVDD
DGND
5V
SPVDD
SPGND
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APPLICATION CIRCUIT
At using internal speaker amplifier (speaker output) ( VDDR is only ML22Q563 )
RESETB
MCU
CSB
SPM
SPP
SCK
SI
speaker
SO
CBUSYB
ERR
STATUS
0.1μF
0.1μF
SG
AIN
DIPH
VPP
TESTI1
VDDL
VDDR
10μF
10μF
DVDD
SPVDD
15pF
XT
10μF
0.1μF
0.1μF
10μF
4.096MHz
5V
DGND
XTB
15pF
SPGND
At using external speaker amplifier (line output) ( VDDR is only ML22Q563 )
RESETB
MCU
CSB
SPM
SPP
0.1μF
SP-AMP
SCK
SI
SO
speaker
CBUSYB
ERR
0.1μF
0.1μF
STATUS
SG
AIN
DIPH
VPP
TESTI1
VDDL
VDDR
DVDD
10μF
10μF
10μF
SPVDD
15pF
XT
10μF
0.1μF
4.096MHz
5V
XTB
DGND
0.1μF
15pF
SPGND
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RECOMMENDED CERAMIC OSCILLATION
Recommended ceramic resonators for oscillation and conditions are shown below for reference.
KYOCERA Corporation
Optimal load capacity
Freq [Hz]
Type
C1
C2
Rf
Rd Supply voltage Operating Temperature
[pF]
[pF] [Ohm] [Ohm]
Range [V]
Range [°C]
4.096M PBRV4.096MR50Y000
15(internal)
---
--
2.7 to 5.5
-40 to +125
MURATA Corporation
Optimal load capacity
Rd Supply voltage Operating Temperature
Freq [Hz]
Type
C1
C2
Rf
[pF]
[pF] [Ohm] [Ohm]
Range [V]
Range [°C]
4M
CSTCR4M00G55B-R0
CSTCR4M09G55B-R0
39(internal)
---
--
2.7 to 5.5
-40 to +125
4.096M
Circuit diagram
VDD
DVDD/SPVDD
DGND/
SPGND
GND
XT XTB
C2
C1
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LIMITATION ON THE OPERATION TIME (PLAY-BACK TIME)
ML22Q563/ML22563’s operating temperature is 85℃. But the average ambient temperature at 1W play-back
(8ohm drive) during 10 years in the reliability design is Ta=55℃. (max ( the package heat resistance θ
ja=42.51[℃/W]) )
When ML22Q563/ML22563 operates 1W play-back(8ohm drive) consecutively, the product life changes by the
package temperature rise by the consumption. This limitation does not matter in the state that a speaker amplifier
does not play.
The factor to decide the operation time ( play-back time ) is the average ambient temperature( Ta ), play-back
Watts( at the speaker drive mode), the soldering area ratio*1, and so on. In addition, the limitation on the
operation time changes by the heat designs of the board.
PACKAGE HEAT RESISTANCE VALUE (REFERENCE VALUE)
The following table is the package heat resistance value θja (reference value).
This value changes the condition of the board (size, layer number, and so on)
The board
JEDEC 4layers
θja
The condition
42.51[℃/W]
（W/L/t＝76.2/114.5/1.6（mm））
JEDEC 2layers
No wind (0m/sec)
the soldering area ratio*1：100%
55.37[℃/W]
（W/L/t＝76.2/114.5/1.6（mm））
*1 : The soldering area ratio is the ratio that the heat sink area of ML22Q563/ML22563 and a land pattern on
the board are soldered. 100% mean that the heat sink area of ML22Q563/ML22563 is completely soldered
to the land pattern on the board. About the land pattern on the board, be sure to refer to the next clause
(PACKAGE DIMENSIONS).
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PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
Notes for heat sink type Package
This LSI adopts a heat sink type package to raise a radiation of heat characteristic. Be sure to design the land
pattern corresponding to the heat sink area of the LSI on a board, and solder each other. The heat sink area of the
LSI solder open or GND on the board. Be sure to refer to the next clause reference data ( Mounting area for
package lead soldering to PC boards ).
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[Unit:mm]
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Revision History
Page
Previous
Edition
Document No.
Date
Description
Current
Edition
FEDL2256XFULL-01 Apr. 12, 2010
FEDL2256XFULL-02 Apr. 28, 2010
–
–
Formally edition 1
12
1
12
Change “DACEN” to “DAEN”
ML22Q563-NNN/-xxx
↓
FEDL2256XFULL-03 Jun. 03, 2010
1
ML22Q563-NNN
ML22Q563-xxx
FEDL2256XFULL-04 Feb. 09, 2011
FEDL2256XFULL-05 May.28, 2012
60
-
60
-
Change capacitance(delete +/-).
Change mixing channel to 4ch.
Add tCB3.
13
18
13
18
FEDL2256X-06
Apr. 25, 2013
Change Playback Stop Timing.
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NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall
bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility
whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction
manual.
The Products are not designed or manufactured to be used with any equipment, device or system which requires
an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human
life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace
machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is
intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the
Law.
Copyright 2010-2013 LAPIS Semiconductor Co., Ltd.
66/66
相关型号：
ML22Q623
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
ML22Q624
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
ML22Q625
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
ML22Q626
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
ML22Q663
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
ML22Q664
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
ML22Q665
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
ML22Q666
ML226xx系列是内置有4Mbit～32Mbit Flash存储器的语音合成LSI。由于内置了大容量存储器，因此非常适用于语音操作指导等需要长时间播放语音的应用。此外，该系列产品还支持通过微控制器改写Flash存储器。产品采用实现高音质的HQ-ADPCM、16位D/A转换器和低通滤波器，并内置用来直接驱动扬声器的1.0W单声道扬声器放大器。语音输出所需的功能已经全部集成于1枚芯片中，因此仅需增加本LSI，即可轻松实现语音功能。
ROHM
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