MT7697D_技术文档

MT7697D DATASHEET

Version:

1.01

Release date: 2016-05-10

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permission for any material that is owned by third parties. You may only use or reproduce this document if you have agreed to and been

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MT7697D

Internet-of-Things Wireless Connectivity

Document Revision History

Revision

1.00

Date

Description

2016-01-12

Initial version.

1. Modify table 4.2 for wider termperature specification

2. Modify table 5.8 for wider termperature specification

1.01

2016-05-10

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MT7697D

Internet-of-Things Wireless Connectivity

Table of Contents

Document Revision History............................................................................................................. 2

Table of Contents............................................................................................................................ 3

List of Tables................................................................................................................................... 6

List of Figures.................................................................................................................................. 7

1

System Overview................................................................................................................... 9

1.1 General Description.............................................................................................................. 9

1.2 Features................................................................................................................................ 9

1.2.1

1.2.2

1.2.3

1.2.4

1.2.5

1.2.6

Technology and package...................................................................................... 9

Power management and clock source................................................................. 9

Platform ............................................................................................................... 9

WLAN ................................................................................................................. 10

Bluetooth ........................................................................................................... 10

Miscellaneous .................................................................................................... 10

1.3 Applications........................................................................................................................ 10

1.4 Block Diagram..................................................................................................................... 11

2

Functional Description......................................................................................................... 12

2.1 Overview............................................................................................................................. 12

2.2 Power Management Unit................................................................................................... 12

2.2.1

2.2.2

2.2.3

PMU Architecture .............................................................................................. 12

Chip Power Plan ................................................................................................. 13

Digital Power Domain and Power States ...........................................................13

2.3 Clock and Reset Generation ............................................................................................... 17

2.3.1

2.3.2

Clock................................................................................................................... 17

Reset................................................................................................................... 20

2.4 Application Processor Subsystem ...................................................................................... 20

2.4.1

2.4.2

2.4.3

2.4.4

2.4.5

CPU..................................................................................................................... 20

Cache and Tightly Coupled Memory..................................................................21

Bus Fabric........................................................................................................... 22

Serial Flash Controller ........................................................................................ 23

DMA ................................................................................................................... 23

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2.4.6

General Purpose Timer ...................................................................................... 25

Watchdog Timer................................................................................................. 26

Efuse................................................................................................................... 27

Interrupt Controller............................................................................................ 27

Power-on Sequence ........................................................................................... 30

Memory Map ..................................................................................................... 32

SYSRAM_CM4..................................................................................................... 38

Crypto engine..................................................................................................... 38

2.4.7

2.4.8

2.4.9

2.4.10

2.4.11

2.4.12

2.4.13

2.5 Peripherals.......................................................................................................................... 38

2.5.1

2.5.2

2.5.3

2.5.4

2.5.5

2.5.6

2.5.7

2.5.8

2.5.9

GPIO Interface.................................................................................................... 38

UART Interface ................................................................................................... 42

I2C Serial Interface ............................................................................................. 43

Auxiliary ADC function ....................................................................................... 43

SPI Master Interface........................................................................................... 44

SPI Slave Interface.............................................................................................. 45

I2S Interface ....................................................................................................... 45

Pulse Width Modulation (PWM)........................................................................ 47

IrDA .................................................................................................................... 48

2.6 Radio MCU Subsystem ....................................................................................................... 48

2.6.1

2.6.2

2.6.3

2.6.4

2.6.5

CPU..................................................................................................................... 48

RAM/ROM.......................................................................................................... 48

Memory map...................................................................................................... 48

N9 Bus Fabric...................................................................................................... 51

CIRQ.................................................................................................................... 52

2.7 Wi-Fi Subsystem ................................................................................................................. 54

2.7.1

2.7.2

2.7.3

Wi-Fi MAC .......................................................................................................... 54

WLAN Baseband................................................................................................. 54

WLAN RF............................................................................................................. 54

2.8 Bluetooth Subsystem ......................................................................................................... 55

2.9 RTC...................................................................................................................................... 55

3

Radio Characteristics ........................................................................................................... 56

3.1 Wi-Fi Radio Characteristics................................................................................................. 56

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3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

Wi-Fi RF Block Diagram ...................................................................................... 56

Wi-Fi 2.4GHz Band RF Receiver Specifications...................................................57

Wi-Fi 2.4GHz Band RF Transmitter Specifications .............................................58

Wi-Fi 5GHz Band RF Receiver Specifications......................................................59

Wi-Fi 5GHz Band RF Transmitter Specifications.................................................61

3.2 Bluetooth Radio Characteristics......................................................................................... 62

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.2.7

Bluetooth RF block diagram............................................................................... 62

Basic Rate Receiver Specifications .....................................................................62

Basic Rate Transmitter Specifications................................................................63

Enhanced Data Rate Receiver Specifications.....................................................64

Enhanced Data Rate Transmitter Specifications................................................65

Bluetooth LE Receiver Specifications.................................................................66

Bluetooth LE Transmitter Specifications............................................................67

4

Electrical Characteristics ...................................................................................................... 68

4.1 Absolute Maximum Rating................................................................................................. 68

4.2 Recommended Operating Range ....................................................................................... 68

4.3 DC Characteristics............................................................................................................... 68

4.4 XTAL Oscillator.................................................................................................................... 69

4.5 PMU Characteristics ........................................................................................................... 69

4.6 Auxiliary ADC Characteristics ............................................................................................. 70

4.7 Thermal Characteristics...................................................................................................... 72

5

Package Specifications......................................................................................................... 73

5.1 Pin Layout........................................................................................................................... 73

5.2 Pin Description ................................................................................................................... 74

5.3 Pin Multiplexing.................................................................................................................. 76

5.4 Bootstrap............................................................................................................................ 81

5.5 Package information .......................................................................................................... 83

5.6 Ordering information ......................................................................................................... 83

5.7 Top Marking ....................................................................................................................... 84

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List of Tables

Table 2-1. MTCMOS Power Domain...................................................................................................... 13

Table 2-2. Power States for CM4 Subsystem......................................................................................... 15

Table 2-3. Power States for N9 Subsystem............................................................................................ 15

Table 2-4. Power State Transition Scenarios for N9 ..............................................................................16

Table 2-5. Power State Transition Scenarios for CM4 ...........................................................................16

Table 2-6. Cortex-M4 Clock Rate........................................................................................................... 18

Table 2-7. N9 Clock Rate ....................................................................................................................... 18

Table 2-8. Peripheral Clock Rate............................................................................................................ 18

Table 2-9. TCM and Cache Configuration.............................................................................................. 21

Table 2-10. Flash Controller Support Read Mode .................................................................................23

Table 2-11. DMA Use for Hardware Functions......................................................................................24

Table 2-12. General Purpose Timer Types............................................................................................. 26

Table 2-13. CM4 NVIC Interrupt Source................................................................................................ 27

Table 2-14. CM4 External Interrupt De-Bounce Period.........................................................................29

Table 2-15. CM4 Memory Map ............................................................................................................. 34

Table 2-16. Functional Description of AGPIO........................................................................................ 41

Table 2-17. SPI Pin Description.............................................................................................................. 45

Table 2-18. I2S Pin Description.............................................................................................................. 46

Table 2-19. I2S Slave Mode ................................................................................................................... 46

Table 2-20. PWM Modes....................................................................................................................... 47

Table 2-21. N9 Memory Map ................................................................................................................ 48

Table 3-1. 2.4GHz RF Receiver Specification ......................................................................................... 57

Table 3-2. 2.4GHz RF Transmitter Specifications...................................................................................58

Table 3-3. 5GHz RF Receiver Specifications........................................................................................... 59

Table 3-4. 5GHz RF Transmitter Specifications......................................................................................61

Table 3-5. Basic Rate Transmitter Specifications...................................................................................63

Table 3-6. Enhanced Data Rate Receiver Specifications........................................................................64

Table 3-7. Bluetooth LE Receiver Specifications ...................................................................................66

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Table 3-8. Bluetooth LE Transmitter Specifications...............................................................................67

Table 4-1 Absolute Maximum Rating .................................................................................................... 68

Table 4-2. Recommended Operating Range ......................................................................................... 68

Table 4-3. DC Characteristics................................................................................................................. 68

Table 4-4. XTAL Oscillator Requirements .............................................................................................. 69

Table 4-5. PMU Electrical Characteristics.............................................................................................. 69

Table 4-6. Auxiliary ADC Specifications ................................................................................................ 70

Table 4-7. Thermal Characteristics........................................................................................................ 72

Table 5-1. Pin Map ................................................................................................................................ 73

Table 5-2. Pin Descriptions.................................................................................................................... 74

Table 5-3. Pin Multiplexing.................................................................................................................... 77

Table 5-4. Boostrap Option– Flash Access Mode..................................................................................82

Table 5-5. Bootstrap Option – XTAL Clock Mode ..................................................................................82

Table 5-6. Bootstrap Option – 32KHz Clock Mode................................................................................82

Table 5-7. Bookstrap Option — Chip Mode .......................................................................................... 82

Table 5-8. Ordering Information ........................................................................................................... 83

List of Figures

Figure 1-1. System-on-Chip Block Diagram........................................................................................... 11

Figure 2-1. Chip Power Block Diagram.................................................................................................. 12

Figure 2-2. MT7697D Power State ........................................................................................................ 15

Figure 2-3. Clock Generation Block Diagram......................................................................................... 17

Figure 2-4. Clock Domains in N9 and CM4 Peripherals.........................................................................19

Figure 2-5. Reset Structure ................................................................................................................... 20

Figure 2-6. CM4 Subsystem – Bus Fabric .............................................................................................. 22

Figure 2-7. Virtual FIFO Concept ........................................................................................................... 24

Figure 2-8. PMU Power-on Sequence ................................................................................................... 30

Figure 2-9. WDT Structure .................................................................................................................... 31

Figure 2-10. Sleep/Wakeup Sequence ................................................................................................. 32

Figure 2-11. AGPIO/GPIO Block Diagram (Left: AGPIO; Right: GPIO)....................................................39

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Figure 2-12. AGPIO Configured as Output Multiplexing ......................................................................40

Figure 2-13. AGPIO Configured as Input Multiplexing ..........................................................................41

Figure 2-14. AGPIO Configured as Input, Output, or Analog Mode......................................................42

Figure 2-15. GPIO Configured as Open Drain Mode .............................................................................42

Figure 2-16. Auxiliary ADC Block Diagram (Analog Part) ......................................................................43

Figure 2-17. Auxiliary ADC Block Diagram ............................................................................................ 44

Figure 2-18. Auxiliary ADC Clock Timing Diagram.................................................................................44

Figure 2-19. SPI Timing Diagram ........................................................................................................... 45

Figure 2-20. I2S Signal Waveform ......................................................................................................... 47

Figure 2-21. N9 Bus Fabric .................................................................................................................... 51

Figure 2-22. N9 interrupt controller...................................................................................................... 52

Figure 3-1. 2.4/5GHz RF Block Diagram ............................................................................................... 56

Figure 3-2. Wi-Fi/Bluetooth RF Block Diagram .....................................................................................62

Figure 3-3. Basic Rate Receiver Specifications ......................................................................................62

Figure 5-1. Package Outline Drawing .................................................................................................... 83

Figure 5-2. Top Marking ........................................................................................................................ 84

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MT7697D

Internet-of-Things Wireless Connectivity

1

System Overview

1.1

General Description

MT7697D is a highly integrated single chip which features an application processor, a low power 1x1

11n dual-band Wi-Fi subsystem, a Bluetooth subsystem, and a Power Management Unit. The

application processor subsystem contains an ARM Cortex-M4 with floating point MCU. It also

includes many peripherals, including UART, I2C, SPI, I2S, PWM, IrDA, and auxiliary ADC. It also

includes embedded SRAM/ROM .

The Wi-Fi subsystem contains the 802.11a/b/g/n radio, baseband, and MAC that are designed to

meet both the low power and high throughput application. It also contains a 32-bit RISC CPU that

could fully offload the application processor.

The Bluetooth subsystem contains the Bluetooth radio, baseband, link controller. It also uses the

same 32-bit RISC CPU for the Bluetooth protocols.

1.2

Features

1.2.1

Technology and package

.

8mm x 8mm 68-pin QFN package.

1.2.2

1.2.3

Power management and clock source

.

Integrate high efficiency power management unit with single 3.3V power supply

input

40/26/52MHz source crystal clock support with low power operation in idle mode

Platform

.

ARM Cortex-M4 MCU with FPU with up to 192MHz clock speed

Embedded 352KB SRAM and 64KB boot ROM

Supports external serial flash with Quad Peripheral Interface (QPI) mode

Supports eXecute In Place (XIP) on flash

32KB cache in XIP mode

Hardware crypto engines including AES, DES/3DES, SHA2 for network security

28 General Purpose IOs multiplexed with other interfaces

Two UART interfaces with hardware flow control and one UART for debug, all

multiplexed with GPIO

.

One SPI master interface multiplexed with GPIO

One SPI slave interface multiplexed with GPIO

Two I2C master interface multiplexed with GPIO

One I2S interface multiplexed with GPIO

Four channel 12-bit ADC multiplexed with GPIO

28 PWM multiplexed with GPIO

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MT7697D

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.

25 channels DMA

Low power RTC mode with 32KHz crystal support

1.2.4

WLAN

.

Dedicated high-performance 32-bit RISC CPU N9 up to 160MHz clock speed

IEEE 802.11 a/b/g/n compliant

Supports 20MHz, 40MHz bandwidth in 2.4GHz band 5GHz band

Dual-band 1T1R mode with data rate up to 150Mbps

Supports STBC, LDPC

Greenfield, mixed mode, legacy modes support

IEEE 802.11e support

Security support for WFA WPA/WPA2 personal, WPS2.0

Supports 802.11w protected managed frames

QoS support of WFA WMM

Integrated LNA, PA, and T/R switch

Optional external LNA and PA support.

RX diversity support with additional RX input

1.2.5

Bluetooth

.

Bluetooth 4.2 Low Energy (LE)

Integrated BALUN and PA

Support SCO and eSCO link with re-transmission

Channel assessment for AFH

1.2.6

Miscellaneous

.

Integrates 4Kbit efuse to store device specific information and RF calibration data.

Advanced Wi-Fi/Bluetooth coexistence scheme

1.3

Applications

MT7697D is designed for Internet-of-Things based on the Mediatek’s low power technology, Wi-Fi

and Bluetooth design.

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1.4

Block Diagram

SPI flash

Bluetooth RF

SPI Flash

controller

Clock

generation

UART x 1

40/26/52MHz XTAL

Bluetooth

baseband

25 channel

Generic DMA

PMU

EFUSE

(4Kb)

TCM / Cache

(96KB)

Bluetooth link

controller

IrDA

CM4 SYSRAM

(256KB)

UART x 2

Debug

Bluetooth

audio CODEC

ILM/DLM

SRAM/ROM

ARM Cortex

M4F

UART x 2

GPIO/PWM x 28

Wi-Fi dual-band

RF

N9 CPU

Wi-Fi RF

UART x 2

I2C x 2

Crypto Engine

SYSRAM

Wi-Fi baseband

Wi-Fi MAC

Watch Dog

Timer

4 channel

Auxiliary ADC

General

Purpose Timer

SPI

I2S

Wi-Fi PSE

RTC

N9 subsystem

M4 subsystem

32KHz XTAL

Figure 1-1. System-on-Chip Block Diagram

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2

Functional Description

2.1

2.2

Overview

Power Management Unit

A single regulated 3.3V power supply is required for the MT7697D. It could be from DC-DC converter

to convert higher voltage supply to 3.3V or boost from a lower voltage supply to 3.3V.

The Power Management Unit (PMU) contains Under-Voltage Lockout (UVLO) circuit, several Low

Drop-out Regulators (LDOs), a highly efficient buck converter, and a reference band-gap circuit. The

circuits are optimized for low quiescent current, low drop-out voltage, efficient line/load regulation,

high ripple rejection, and low output noise.

AVDD45_BUCK

AVDD45_MISC

1.15V

LXBK

AVDD16_CLDO

1.6V

BUCK/SLDOH

(3.3V)

AVDD12_VCORE

CLDO/SLDOL

(1.6V)

3.3V

Digital core

(1.15V)

DVDD11

RF(3.3V)

AVDD33_WF0_A_TX

VSS

AVDD33_WF0_A_PA

AVDD33_WF0_G_TX

AVDD33_WF0_G_PA

AVDD33_BT

RF LDO/RF

core (1.6V)

ALDO

(3.3V)

AVDD16_WF0_AFE

AVDD16_XO

AVDD16_BT

DVDDIO

VSS

AVDD25_ALDO_OUT

IO (3.3V)

2.5V

ELDO

(3.3V to 2.5V)

ADC

(2.5V)

PMU_DIO33_OUT

AVSS45_BUCK

VSS

AVDD25_AUXADC

3.3V

AVSS25_AUXADC

Figure 2-1. Chip Power Block Diagram

2.2.1

PMU Architecture

The PMU integrates 5 LDOs and one buck converter.

The four LDOs are CLDO, ALDO, high-voltage SLDO (SLDO-H) and low-voltage SLDO (SLDO-L). SLDO

stands for sleep mode LDO, and CLDO stands for digital core LDO. The buck converter converts

1.6~1.8V output to other subsystems in MT7697D. It can be operated in PFM mode or PWM mode.

Through an external on-board LC filter (2.2uH inductor and 10uF cap), it outputs a low ripple

1.6~1.8V to Wi-Fi RF system, Bluetooth RF system, and CLDO. CLDO is under BUCK domain, and then

it outputs 1.15V for whole chip digital logics used. ALDO is also from 3.3V chip supply input and

generates 2.5V for the auxiliary ADC. The two SLDOs have 1.8V and 0.85V output voltage respectively.

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They are used to keep BUCK and CLDO output voltage while MT7697D is in sleep mode to reduce

current consumption.

Once MT7697D goes into deep sleep mode, BUCK, ALDO, and CLDO can be shut down. BUCK output

voltage will be kept by SLDO-H, and CLDO output will be kept by SLDO-L.

PMU also integrated the ELDO (Efuse LDO). It provides 2.5V output voltage to the internal Efuse

macro in programming mode.

2.2.2

Chip Power Plan

The 3.3V power source is directly supplied to the switching regulator, digital I/Os, and RF-related

circuit. It is converted to 2.5V by the LDO for ADC analog circuit. It is converted to 1.6V by the buck

converter for low voltage circuits. The built-in digital LDOs and RF LDOs converts 1.6V to 1.15V for

digital, RF, and BBPLL core circuits.

2.2.3

Digital Power Domain and Power States

The digital circuit is separated into five power domains. They are TOP_AON, TOP_OFF(N9), WF_OFF,

BT_OFF, and CM4_SYS. Except TOP_AON, each power domain can be turned on and off individually.

Table 2-1. MTCMOS Power Domain

Domain

Description

Circuit Included

OFF Condition

TOP_AON

Always-on power domain,

which keeps the minimum

circuit powered to wake up

from the sleep mode upon

receiving a wake-up event.

It includes:

N/A

Chip level configuration

register.

Sleep mode controller;

External interrupt controller;

Part of the Wi-Fi MAC that

handles the beacon filtering.

Sustain and backup memory

that stores the RAM code

and the register values that

need to be kept during sleep

mode.

TOP_OFF(N9) The power domain can be

power gated in Wi-Fi power

The whole N9 subsystem, N9 N9 is in sleep mode

peripherals, and part of the

Wi-Fi MAC circuit are

and no DMA functions

are enabled.

save mode and Bluetooth

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Domain

Description

Circuit Included

OFF Condition

power save mode.

included.

WF_OFF

The power domain can be

power gated when Wi-Fi is

The whole Wi-Fi baseband

and part of the MAC

Wi-Fi is disabled.

N9 is in standby mode

or in sleep mode.

not used and in Wi-Fi power subsystem are included.

save mode.

BT_OFF

The power domain can be

power gated when

Bluetooth is not used and in

Bluetooth power save

mode.

The whole Bluetooth

subsystem is included.

Bluetooth is disabled.

N9 is in standby mode

or in sleep mode.

CM4_OFF

The power domain is not

powered gated when

Cortex-M4 is used.

The whole Cortex-M4

subsystem and Cortex-M4

peripherals are included.

N/A

The MT7697D power state diagram is illustrated below. There are two sleep mode controllers,

controlled by N9 and CM4, respectively.

The N9 power state and CM4 power state operates independently. When both enter the sleep mode,

the XTAL and PMU can be changed to the low power mode to further lower the current consumption.

N9 active

CM4 active

PLL Clock

Wi-Fi ON

PLL clock

CM4 standby

XTAL 26MHz

N9 standby

XTAL 26MHz

MCU idle

Wi-Fi ON

PLL clock

CM4 sleep

XTAL 32KHz

N9 sleep

XTAL 32KHz

When both CM4 and N9

are in sleep mode, XTAL

and PMU is changed

to low power mode.

PMU sleep

XTAL/PMU in low

power mode

PMU sleep

XTAL/PMU in low

power mode

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Figure 2-2. MT7697D Power State

Table 2-2. Power States for CM4 Subsystem

MCU mode

Description

Wake-up time

Power

CM4 active

MCU executing code at PLL clock

n/a

CM4

MCU subsystem clocks are gated off and the state of the entire

subsystem is retained. PLL is off.

TBD

standby

CM4 sleep

MCU subsystem clocks are gated off and the state of the entire

subsystem is retained. Only 32KHz clock from XTAL is active. MCU

is configured to wake up on the expiry of the internal timer and

external wake-up events.

TBD

1mA

PMU sleep

CM4_OFF is power gated. XTAL and PMU operate in low power

mode. MCU is configured to wake up on the expiry of the internal

timer and external wake-up events.

0.3mA

Table 2-3. Power States for N9 Subsystem

Description

MCU mode

N9 active

MCU idle

Wake-up time

Power

MCU executing code at PLL clock.

n/a

MCU clock is gated off, while MCU subsystem clocks are on to

maintain the operation of Wi-Fi function, like listening to beacon.

PLL is on.

TBD

N9 standby

N9 sleep

MCU subsystem clocks are gated off and the state of the entire

subsystem is retained. PLL is off.

TBD

MCU subsystem clocks are gated off and the state of the entire

subsystem is retained. Only 32KHz clock from XTAL is active. MCU

is configured to wake up on the expiry of the internal timer,

external wake-up events, or the wake-up events from Wi-Fi radio

or Bluetooth ratio.

1mA

PMU sleep

TOP_OFF (N9) and WF_OFF are power gated. XTAL and PMU

operate in low power mode. The state information is retained in

back-up buffer (sleep-mode memory) and can be restored when

TBD

0.3mA

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MCU mode

Description

Wake-up time

Power

wake-up. MCU is configured to wake up on the expiry of the

internal timer, external wake-up events, or the wake-up events

from Wi-Fi radio or Bluetooth ratio.

The typical scenarios which N9 operates in and the power state transition are summarized in the

following table.

Table 2-4. Power State Transition Scenarios for N9

Scenario

Description

State transition

1

All functions are idle and the N9 firmware triggers to enter the

sleep mode.

Active à Standby à Sleep

2

3

Wi-Fi DTIM timer is expired and the hardware wakes up to listen

to beacon and then goes to sleep again when It is not necessary

to wake up N9 to process the data.

Sleep à MCU idle (Wi-Fi ON) à

sleep

Wi-Fi DTIM timer is expired and the hardware wakes up to listen

to beacon and then wake up N9 to process the data.

Sleep à MCU idle (Wi-Fi ON) à

Active

The typical scenarios which CM4 operates in and the power state transition are summarized in the

following table.

Table 2-5. Power State Transition Scenarios for CM4

Scenario

Description

State transition

1

All functions are idle and the CM4 firmware triggers to enter the

sleep mode.

Active à Standby à Sleep

2

The wake-up event (wake-up event from N9 or other sources)

triggers CM4 to wake up.

Sleep à Standby à Active

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2.3

Clock and Reset Generation

2.3.1

Clock

MT7697D connects to the XTAL or external clock source as the single clock source of the whole

system. The XTAL oscillator can support the XTAL frequencies from among 40, 26, and 52MHz.

XTAL CLOCK

WF RF

RF PLL

XTAL

RF power domain

AON power domain

CM4 power domain

PMU power domain

oscillator

PLL1

f = 40/

64MHz

81021170[12:8]

DIV

26/52MHz

832MHz

640MHz

1

0

2

80021114[21:20]

1-32 step 1

DIV

830081B4[7:3]

830081B4[14:13]

FLASH CLOCK

32MHz

DIV

PLL2

960MHz

DIV 12

DIV 1

80MHz

WF_RXADC_CLK

WF_TXDAC_CLK

960MHz

BGCLK

(25KHz)

PMU

81021100[17:16]

320MHz

DIV 3

DIV 8

WF_DIG_CLK

0

F32K CLOCK

DIV 794

81021100[31:21]

2

830081B4[23:19]

81021100[15:14]

2-32 step 0.5

1

3

0

DIV 5

81021100[9:4]

4

160MHz

1-160MHz

N9 CLOCK

0

1

81021100[2:0]

830081B0[15:14]

2-32 step 0.5

1

3

0

DIV 5

4

192MHz

1-192MHz

CM4 CLOCK

830081B0[9:4]

830081B0[2:0]

0

1

DIV options:

480, 240, 120, 60,

30, 20, 15, 12, 10

120MHz

DIV

SPI CLOCK

250, 500KHz

1, 2, 4, 6, 8, 10, 12MHz

24000028[27:16]

830081B4[17]

830B0000[27:24]

1

2

16MHz

I2S_MCLK

16MHz

DIV

XPLL (Audio Frac-N)

±1% (0.01% granularity)

DIV 2

8300A600[2:1]

0

2

1

PWM CLOCK

2MHz

DIV 13

830081B4[12:8]

AUXADC CLOCK

I2C CLOCK

DIV options: 520,260,130,65

DIV

83090244[15:0] 83090248[15:0]

50, 100, 200, 400KHz

DIV options: 2708,1354,677,226

DIV

UART CLOCK

830A0244[15:0]830A0248[15:0]

9.6, 19.2, 38.4, 115.2KHz

Figure 2-3. Clock Generation Block Diagram

.

PLL1 is used to generate the clock sources for Bluetooth and PLL2.

PLL2 is used to generate the clock sources for Wi-Fi, N9 core, Cortex-M4 core, and bus fabric.

XPLL is used to generate the clock sources for I2S (for external audio CODEC).

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The options of clock rate for MCU are listed below.

Table 2-6. Cortex-M4 Clock Rate

MCU Clock MCU Clock

Reference Clock

(MHz)

(MHz, XTAL mode) (MHz, PLL mode)

40

26

52

40

30, 32, 40, 48, 60, 80,

26

96, 120, 160, 192.

52

Table 2-7. N9 Clock Rate

MCU Clock

Reference Clock (MHz)

(MHz, XTAL mode)

(MHz, PLL mode)

40

26

52

30, 32, 40, 48, 60, 80,

96, 120, 160, 192.

26

52

Table 2-8. Peripheral Clock Rate

Peripheral Clock Rate

Support SPEC

PWM

UART

XTAL clock with DIV13 (Default)

200Hz at minimum.

XTAL clock

F32K clock

XTAL clock with DIV

9.6, 19.2, 38.4, 115.2K

I2C

SPI

XTAL clock with DIV

50, 100, 200, 400KHz

4, 6, 8, 10, 12MHz

XTAL clock with DIV (Default)

Flash

XTAL clock with DIV (Default)

BT_DIG_CLK (64MHz) with DIV

64MHz.

CM4 clock with DIV

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CM4 CLOCK

INT

WDT

GPT

CM4

TCM

Cache

MTK

SYSRAM GDMA

Security

I2S

AHB

HIF SYS

WF/BT

Flash

CTRL

I2C

x2

UART PWM

ASYNC

Bridge

x2

ADC

SPI

x2

x40

ADC

CLOCK

FLASH

CLOCK

I2C

UART

CLOCK

PWM

CLOCK

N9 CLOCK

CLOCK CLOCK

Figure 2-4. Clock Domains in N9 and CM4 Peripherals

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2.3.2

Reset

MT7697D has three global resets: XRESETN, CM4_RESETN, and N9_RESETN. The figure below shows

the module that the reset signals are applied to.

XRESETN Reset Tree

(1)CM4 WDT and GPT module

(2)CM4 WIC module

Chip Cold Reset Event

(3)N9 WDT and GPT module

(4)N9 interrupt module

(5)AON module (top MISC logic always on during sleep)

Chip Cold Reset Event

Or

CM4 Host Reset Event

CM4_RESETN Reset Tree

CM4 MCU and all modules on CM4 bus other than XRESETN reset

tree

Chip Cold Reset Event

Or

N9 Host Reset Event

N9_RESETN Reset Tree

N9 MCU and all modules on N9 bus other than XRESETN reset

tree

Figure 2-5. Reset Structure

2.4

Application Processor Subsystem

The MCU subsystem consists of a 32-bit MCU, the AHB/APB bus matrix, internal RAM/ROM with

ROM patch function, the flash controller, and the system peripherals including Direct Memory Access

(DMA) engine and the General Purpose Timer (GPT).

2.4.1

CPU

MT7697D features an ARM Cortex-M4 processor, which is the most energy efficient ARM processor

available. It supports the clock rates from 1MHz up to 192MHz.

The MCU executes the Thump-2 instruction set for optimal performance and code size, including

hardware division, single cycle multiplication, and bit-field manipulation.

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MT7697D includes the memory protection unit (MPU) in Cortex-M4 MCU that provides memory

protection features. It can be used to detect unexpected memory access.

MT7697D also includes floating point unit (FPU) in Corxex-M4 process to support DSP related

function.

2.4.2

Cache and Tightly Coupled Memory

MT7697D has a cache for Cortex-M4 to improve the efficiency of the code and data fetch from the

external flash. The only cacheable memory region is the external flash.

MT7697D also has a Tightly-Coupled-Memory (TCM), a zero-wait-state memory which is dedicated

for Cortex-M4 and can be accessed by Cortex-M4 exclusively. It is a memory space for the critical

code such as interrupt service routines which needs to be executed with minimum latency. The DMA

engines on AHB bus can’t access TCM.

The total size of memory of the cache and the TCM is 96KB. Four software-configurable options differ

in the size of cache, the size of TCM, and the cache associativity. The user can select the option which

maximizes the performance.

The cache system has the following features:

.

Configurable 1/2/4-way set associative (8KB/16KB/32KB)

Each way has 256 cache lines with 8-word link size

20-bit tag memory: 19-bit high address and 1-bit valid bit

2-bit dirty memory: each dirty bit identifies the dirtiness of half cache line

The size of SRAM is 96KB. It can be configured to the following configuration

.

96KB TCM, no cache

88KB TCM, 8KB cache (1 way, direct mapped)

80KB TCM, 16KB cache (2 way set-associative)

64KB TCM, 32KB cache (4 way set-associative)

The configuration setting and the memory configuration are shown in the following table.

Table 2-9. TCM and Cache Configuration

0x0153_0000[9:8]

Functional Description

96KB TCM, no cache

Start Address

0x0010_0000

End Address

0x0011_7FFF

0x0011_5FFF

0x0011_3FFF

0x0010_FFFF

00b

01b

10b

11b

88KB TCM, 8KB cache, direct mapped

80KB TCM, 16KB cache, 2-way set-associative

64KB TCM, 32KB cache, 4-way set associative

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The cache controller provides the user ways to perform cache operations including invalidate

single/all cache lines as well as flush one/all cache lines.

To facilitate tuning the system performance, the cache controller can record the statistics of the

cache hit count and the number of cacheable memory access. Cache hit rate can be obtained by

dividing the cache hit count by the number of memory access.

2.4.3

Bus Fabric

MT7697D implements AHB/APB bus fabric to connect the MCU, memory, IO peripherals, and the

radio subsystem.

.

ILM/DLM: Instruction Local Memory / Data Local Memory, the zero-wait-state local

memory for Radio MCU.

.

Wi-Fi HIF: The data interface to Wi-Fi Packet switch engine.

BT FIFO I/F: The control/data interface to Bluetooth subsystem.

ARM Cortex M4

N9

ILM/DLM

SYSTEM DCODE ICODE

TCM ROM

AHB mux

Asyncrhrous AHB-2-

AHB bridge

(N9 bus to CM4 bus)

Crypto

Engine

Cache

Controller

TCM/Cache

(96KB)

Generic DMA

XIP

CM4 AHB bus

Asyncrhrous AHB-2-

AHB bridge

(CM4 bus to N9 bus)

APB

bridge

I2S

SYSRAM_

CM4

SPI flash

Wi-Fi HIF

(256KB)

N9 AHB bus

APB2 bus

APB

bridge

APB

bridge

UART1

UART2

I2C-1

I2C-2

SPI-M

PWM

TOP &

CM4

CONFIG

APB1 bus

APB0 bus

BT FIFO

I/F

AUX

ADC

GDMA

CONFIG

GPT

WDT

Interface to radio subsystem

Indium peripherals

Figure 2-6. CM4 Subsystem – Bus Fabric

The AHB bus arbitration adopts round-robin scheme.

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The N9 subsystem and Cortex-M4 subsystem are in different clock domains, so the asynchronous

bridges are inserted in the bus fabric. N9 has the ability to (but would be rarely used) all the M4

peripherals.

2.4.4

Serial Flash Controller

MT7697D features a serial flash controller that can support the serial flash with the read mode of

(JEDEC) standard SPI mode, SPI-Quad mode, QPI (Quad Peripheral Interface) mode, Dual IO mode,

and Dual-Output mode.

The frequency of the serial clock rate is up to 64MHz. That provides 256Mbps equivalent throughput

on flash when SPI-quad mode or QPI mode is used.

Table 2-10. Flash Controller Support Read Mode

Read Mode

SPI

Description

1xIO for receiving command and address, 1xIO for output data

1xIO for receiving command, 4xIO for address, 4xIO for output data

4xIO for receiving command/address and output data

1xIO for command, 2xIO for address and output data

1xIO for receiving command, 2xIO for address and output data

SPI-Quad

QPI

Dual-IO

Dual-Output

The Serial Flash Controller Supports Two Operation Modes:

.

Direct read mode, which supports a high-throughput direct-access through AHB bus

Macro access mode, which supports flash access with arbitrary command and is through APB

bus.

2.4.5

DMA

Direct memory access (DMA) is used to transfer data between memory ↔ memory as well as

memory ↔ peripherals without MCU intervention.

2.4.5.1

DMA Functional Description

There are three types of DMA channels supported in MT7697D.

.

Full-size DMA: Both the source address and the destination address are programmable. It is

normally used for memory copy.

Half-size DMA: Either the source address or the destination address is programmable. It is

normally used for data movement between memory and peripherals.

Virtual FIFO DMA (VFF DMA): It is a half-size DMA with an additional FIFO control engine. It is

used to provide the buffering capacity for peripherals including UART.

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2.4.5.1.1 Virtual FIFO

Virtual FIFO DMA is designed to offload the control of the serial interface. The difference between

the virtual FIFO DMA and the full-size/half-size DMA is that the virtual DMA contains an additional

FIFO controller.

The figure below illustrates the operations of virtual FIFO DMA used for UART RX.

.

READ: DMA controller reads data from UART and increments the WRITE pointer of the FIFO

controller.

WRITE; DMA controller writes data that was area from UART to SRAM in the area defined

before enabling the virtual FIFO.

READ: MCU reads data when FIFO is not empty and the amount of data is over a pre-defined

threshold. The read transaction will be finished only when DMA controller reads back the

data from SRAM.

.

READ: DMA controller reads data from SRAM and increments the READ pointer of the FIFO

controller.

Destination Address

MCU

DMA

READ pointer

(MCU)

(1) READ

FIFO size

memory

(3) READ

(4) READ

(2) WRITE

WRITE pointer

(UART RX)

SRAM

UART

Figure 2-7. Virtual FIFO Concept

DMA Channels and Priority Control

2.4.5.2

There are two full-size DMA channels, 10 half- size DMA channels, and 13 virtual FIFO DMA channels

in MT7697D.

Table 2-11. DMA Use for Hardware Functions

Hardware Function

DMA Type

Radio (Bluetooth)

Virtual FIFO DMA x 2

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Hardware Function

Radio (Wi-Fi)

UART (x2)

I2S

DMA Type

Half size DMA x 1

Virtual FIFO DMA x 4

Virtual FIFO DMA x 2

Virtual FIFO DMA x 1

Half size DMA x 4

Half size DMA x 2

Full size DMA x 1

ADC

I2C (x2)

SPI-M

Secure boot

Reserved

Full size DMA x 1, half size DMA x 3 and virtual FIFO DMA x 4.

The DMA provides two levels of scheduling scheme among all channels.

The 1^stlevel scheduling follows the strict-priority scheme. All channels can be grouped into four

priority groups. Group one gets the highest priority, then group two, and so on.

The 2^ndlevel scheduling follows the round-robin scheme. Every channel in the same priority group

has equal opportunity to use the bandwidth and was served sequentially.

The arbitration is done per AHB transaction. When one AHB transaction is finished, the scheduler will

follow the above mechanism to select the next DMA channel to serve.

2.4.6

General Purpose Timer

MT7697D includes the General Purpose Timer (GPT).

Five independent timers are included. Timer 0, 1, and 3 are interrupt-based timers, while timer 2 and

timer 4 are free-run timers.

Two modes are defined in interrupt-based timers:

.

One-shot mode—the timer stops when the timer counts down to 0.

Auto-repeat mode—the timer re-starts when the timer counts down to 0.

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Table 2-12. General Purpose Timer Types

Mode

Clock speed

Interrupt Source

GPT0

GPT1

GPT2

GPT3

GPT4

Interrupt-based

Free-run

1KHz or 32KHz

GPT

1KHz or 32KHz

n/a

Interrupt based

Free-run

26MHz (oscillator clock)

Bus clock or bus clock / 2

GPT3

n/a

2.4.7

Watchdog Timer

MT7697D features the watchdog timer for CM4, which is used to recover the system to the initial

status when the system hangs due to some malfunction.

WDT provides two ways to generate the WDT event:

.

Triggered by the time-out event (by configuring WDT_MODE:0x83080030 and

WDT_LENGTH:0x83080034). The WDT has an 11-bit counter and it uses the 32 KHz clock.

The software regularly restarts the timer to prevent it from expiring. If it fails to restart the

WDT, the timer would expire and generate a WDT event.

.

Triggered by software programming (WDT_SWRST:0x83080044).

WDT provides the following options when a WDT event is generated:

.

0x83080030[3]=0: Reset mode

- 0x8300917C[16] = 1: WDT whole chip mode. Reset the whole chip including CM4 and N9

subsystems.

- 0x8300917C[16] = 0: WDT MCU mode. Reset CM4 subsystem only.

0x83080030[3]=1: Interrupt mode

.

-Issue an interrupt to CM4 instead of resetting whole chip or CM4 subsystem.

The WDT module can only be reset by the external reset (SYS_RST_N) and the PMU reset. Some WDT

control registers feature a key protection mechanism such that an unintentional access would be

prevented.

WDT also provides the capability for CM4 software to interrupt N9 or reset N9 (by configuring

WDT_DUAL_CORE:0x83080080).

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2.4.8

Efuse

MT7697D uses embedded Efuse to store device specific configuration information such as MAC

addresses, and power control settings.

The major fields defined in the Efuse:

.

Wi-Fi MAC addresses

Wi-Fi country code

Wi-Fi TSSI parameters, TX power level

Wi-Fi NIC configuration: RF front-end configuration, LED mode, baseband configuration

Bluetooth MAC address

Bluetooth TX power level.

2.4.9

Interrupt Controller

MT7697D integrates the Nested Vectored Interrupt Controller (NVIC) for Cortex-M4. The NVIC

supports

.

Level and pulse detection of interrupt signals

Configurable priority

Wake-up interrupt controller (WIC) providing ultra-low power sleep mode support

2.4.9.1

Interrupt Sources

The table below listed the NVIC and WIC interrupt sources. In total, there are 49 NVICs, while 23 of

them are external interrupts multiplexed with GPIO functions.

The power domain/subsystem lists the power domain and the subsystem from which the interrupt is

generated.

Table 2-13. CM4 NVIC Interrupt Source

NVIC

No.

Interrupt

source

Power domain

/subsystem

External

interrupt

Wake-up

capability

(1)

De-bounce

Description

INT0

INT1

INT2

INT3

INT4

INT5

INT6

INT7

INT8

UART1

CM4_OFF/MCUSYS_CM4

TOP_AON/HIFSYS

UART 1

DMA_CM4

HIF_CM4

I2C1

Generic DMA in CM4 subsystem

Wi-Fi host interface for CM4

I2C 1

V

CM4_OFF/MCUSYS_CM4

I2C2

I2C 2

UART2

CRYPTO

SF

UART 2

Crypto engine

Serial flash controller, for debug

BTIF_N9_WA

KE

TOP_OFF(N9)/MCUSYS_N

9

V

Bluetooth interface in N9

subsystem to

wake up CM4

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NVIC

No.

Interrupt

source

Power domain

/subsystem

External

interrupt

Wake-up

capability

(1)

De-bounce

Description

INT9

BTIF

CM4_OFF/MCUSYS_CM4

TOP_AON/MCUSYS_CM4

TOP_AON/MCUSYS_N9

Bluetooth interface in CM4

subsystem

INT10

INT11

WDT_CM4

V

Watchdog timer in CM4

subsystem

N9_TO_CM4

_SW1

V

N9 software interrupt to CM4

INT12

INT13

INT14

INT15

INT16

INT17

INT18

INT19

INT20

INT21

INT22

INT23

SPI_S

CM4_OFF/MCUSYS_CM4

TOP_AON/MCUSYS_N9

CM4_OFF/MCUSYS_CM4

SPI slave

WDT_N9

ADC

Watchdog timer in N9 subsystem

Auxiliary ADC FIFO

IrDA TX

IRTX

IRRX

IrDA RX

(Reserved)

RTC_TIMER

GPT3

RTC

V

RTC timer interrupt

GPT3 time-out

CM4_OFF/MCUSYS_CM4

RTC

RTC_ALARM

(Reserved)

RTC alarm interrupt

N9_TO_CM4

_SW2

TOP_AON/MCUSYS_N9

V

N9 software interrupt to CM4

INT24

INT25

INT26

INT27

INT28

INT29

INT30

INT31

INT32

INT33

INT34

INT35

GPT

TOP_CON/MCUSYS_CM4

TOP_AON

V

GPT0 or GPT1 time-out

ADC comparison mode

ADC_COMP

(Reserved)

SPI

CM4_OFF/MCUSYS_CM4

SPI transaction

(Reserved)

WIC

TOP_AON/MCUSYS_CM4

TOP_AON

V ⁽²⁾

V

WIC WAKEUP interrupt CM4

GPIO[2]

SWD_CLK

I2C1_DATA

I2C0_CLK

WIC[0]

WIC[1]

WIC[2]

WIC[3]

Available

TOP_AON

V

GPIO[25]

TOP_AON

V

GPIO[27]

I2S_MCLK_S

PI_MOSI

TOP_AON

V

GPIO[29]

INT36

I2S_BCLK_S

PI_CS

TOP_AON

WIC[4]

V

Available

GPIO[32]

INT37

INT38

INT39

INT40

INT41

ANT_SEL0

ANT_SEL1

GPIO17

ADC0

TOP_AON

WIC[5]

WIC[6]

WIC[7]

WIC[8]

WIC[9]

V

Available

GPIO[33]

GPIO[34]

GPIO[36]

GPIO[57]

GPIO[58]

ADC1

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NVIC

No.

Interrupt

source

Power domain

/subsystem

External

interrupt

Wake-up

capability

(1)

De-bounce

Description

INT42

INT43

INT56

INT57

INT58

INT59

INT60

INT61

INT62

INT75

INT76

INT77

INT78

ADC2

TOP_AON

WIC[10]

WIC[11]

EINT[0]

EINT[1]

EINT[2]

EINT[3]

EINT[4]

EINT[5]

EINT[6]

EINT[19]

EINT[20]

EINT[21]

EINT[22]

V

Available

GPIO[59]

GPIO[60]

GPIO[0]

GPIO[1]

GPIO[3]

GPIO[4]

GPIO[5]

GPIO[6]

GPIO[7]

GPIO[35]

GPIO[37]

GPIO[38]

GPIO[39]

ADC3

TOP_AON

V

PWM0

PWM1

SWD_DIO

GPIO0

GPIO1

GPIO2

GPIO3

GPIO16

GPIO18

GPIO19

GPIO20

Note 1: Capable to wake up CM4 when CM4 is in sleep mode.

Note 2: This interrupt is associated with other wake-up interrupts for CM4 to differentiate wake-up interrupts

from non wake-up interrupts.

2.4.9.2

External Interrupt

MT7697D has the optionally enabled hardware de-bouncing circuit for each interrupt source.

Table 2-14. CM4 External Interrupt De-Bounce Period

Reference clock rate for

de-bounce counter (KHz)

Minimum de-bounce

period (ms)

Maximum de-bounce

period (ms)

3-bit prescaler

000

001

010

011

100

101

8

4

0.13

0.25

0.5

1

2

4

2

8

1

16

32

64

0.5

0.25

2

4

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Reference clock rate for

de-bounce counter (KHz)

Minimum de-bounce

Maximum de-bounce

period (ms)

3-bit prescaler

period (ms)

110

111

0.125

8

128

256

0.0625

16

2.4.10

Power-on Sequence

The power-on control sequence diagram shows how the code reset (PMU_RESET_N) is generated on

chip.

Figure 2-8. PMU Power-on Sequence

2.4.10.1 Power-on Reset (Cold Reset)

The power on reset sequence after chip power on is shown below.

Step 1: N9 reset is de-asserted and boot from ROM (CM4 reset state is still asserted)

Step 2: N9 sets up top configuration registers (such as PLL) and then de-asserts CM4 reset

Step 3: CM4 boots from ROM while N9 polls the PDA (Patch Decryption Accelerator) status

Step 4: CM4 fetch flash header (N9 FW download length information)

Step 5: CM4 setup PDA and PDA address generator

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Step 6: PDA loads firmware from the flash to N9 IDLM

Step 7: N9 executes from IDLM after PDA completes and CM4 executes from Cache/Flash or

TCM.

2.4.10.2 Watchdog Reset

Watchdog reset WDT_N9 is the watchdog timer for N9, and WDT_CM4 is the watchdog timer for

CM4.

When the WDT event of WDT_N9 occurs, WDT_N9 has the capability to

.

Reset N9 or issue an interrupt to N9.

Issue an interrupt to CM4 (can be masked by CM4 if it is not required to be received).

When the WDT event of WDT_CM4 occurs, WDT_CM4 has the capability to

.

Reset whole chip or reset CM4 only or issue an interrupt to CM4.

Issue an interrupt to N9 (can be masked by N9 if it’s not required to be received).

For both WDT_N9 and WDT_CM4, the WDT events can be triggered by time-out and software

programming.

For both WDT_N9 and WDT_CM4, the WDT has the capability to reset the other CPU or issue an

interrupt to the other CPU.

CM4_SW_RST_B

81080080[0]

D12: SYS_RST_N

N9 RELEASE CM4

81020018[0]

CM4_OFF

RELEASE_CM4_RST_B

SEL: 8300917C[16]

CM4_AON_XRESET_RST_B

CM4

peripherals

WDT_N9 interrupt

CM4_AON_

HRESET_RST_B

R16: AVDD45_BUCK

POR_XRESET_RST_B

ARM CM4

PMU_RST_B

PMU

CM4_RGU_HRESET_RST_B

N9_WDT_RST_BàINT13

INT13

CM4_HW_RST_B

NVIC

INT10

INT23

CM4 MTCMOS

power CTRL

Y

N9_TO_CM4_SW2 ingterrupt: 81080080[31:30]

WDT_DUAL_CORE_SW_INTàINT23

CM4_WDT_RST_B

83080030[3]

=1?

N

WDT_CM4

WIC

WDT_N9

AON_XRESET_RST_B

CM4 to N9 interrupt: 83080080[31:30]

WDT_DUAL_CORE_SW_INTàCIRQ EINT 3

Legend:

Reset:

Interrupt:

N9_SW_RST_B

83080080[0]

^C^C^I^I^R^R^Q^Q^E^IN^IN^T^T²³²CIRQ

N9

peripherals

CIRQ INT10

RGU_HRESET_RST_B

N9

N9 MTCMOS

power CTRL

Note:

N9_HW_RST_B

PMU_RST_B: power-on or over-current protection

CM4_WDT_RST_B: CM4 WDT reset

TOP_OFF (N9)

N9_WDT_RST_B: N9 WDT reset

Y

N9_WDT_RST_B

81080030[3]

=1?

N

Figure 2-9. WDT Structure

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2.4.10.3 Reset Scenarios

The definitions of the cold reset and the warm reset are shown below:

.

Cold Reset: Power on reset and both RAM or peripheral devices will be initialized by

firmware.

.

Warm Reset: CPU is reset but RAM content is still retained (without firmware re-

download). It’s triggered by

o

Software reset: Software set WDT reset control register to reset CPU.

WDT reset: WDT expiration cause CPU to reset if enabled, otherwise interrupt.

Core reset: Reset by the other CPU (e.g. N9 to reset CM4 or CM4 to reset N9).

Wake-up from deep sleep mode: Reset by the MTCMOS power control.

2.4.10.4 Sleep/Wakeup sequence

The sleep/wakeup control sequence is shown in the diagram below.

Figure 2-10. Sleep/Wakeup Sequence

2.4.11

Memory Map

The table below describes how the peripherals are mapped to the CM4 memory.

When the MCU performs a read transaction to an undefined address, the bus returns 0. When the

MCU performs a write transaction to an undefined address, the bus regards it as an invalid

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transaction and does nothing. The memory space of 0x5040_0000 to 0x5FFF_FFFF is an undefined

region and shall not be accessed.

The power domain is identified in the table. The hardware clock gating is associated with the power

control. When the CPU power domain is in power-off mode, it implies that the clock is also gated.

The software clock gating control, identified in the table below, provides the way to disable the

function and lower its power consumption when the function is not used.

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Table 2-15. CM4 Memory Map

Start address

0x0000_0000

0x0010_0000

End address

0x0000_FFFF

0x0010_FFFF

Function

Power Domain

Software Clock

gating control

Description

TCM ROM

TCM RAM0

CM4_OFF

Tightly Coupled

ROM for CM4

CM4_OFF

Tightly Coupled

RAM for CM4

(64KB)

0x0011_0000

0x0011_2000

0x0011_4000

0x0011_6000

0x1000_0000

0x2000_0000

0x0011_1FFF

0x0011_3FFF

0x0011_5FFF

0x0011_7FFF

0x1FFF_FFFF

0x2003_FFFF

TCM RAM1

CM4_OFF

Tightly Coupled

RAM for CM4 (8KB)

TCM RAM2

Tightly Coupled

RAM for CM4 (8KB)

TCM RAM3

Tightly Coupled

RAM for CM4 (8KB)

TCM RAM4

Tightly Coupled

RAM for CM4 (8KB)

Serial Flash CM4

SYSRAM_CM4

Serial flash of CM4

System RAM for

CM4, 256Kbytes

0x2100_0000

0x2200_0000

0x2400_0000

0x2500_0000

0x2100_FFFF

0x2200_FFFF

0x2400_FFFF

0x2500_CFFF

SPI-S

CM4_OFF

TOP_OFF(N9)

0x8300_0200[21]

0x8300_0200[14]

0x8300_0200[22]

SPI slave

I2S

I2S/Audio

SPI-M

SPI master

SYSRAM_N9

System RAM for N9,

52Kbytes

0x3000_0000

0x5000_0000

0x5020_0000

0x3FFF_FFFF

0x501F_FFFF

0x502F_FFFF

Serial Flash CM4

HIF_device

CM4_OFF

Serial flash of CM4

through system bus

TOP_OFF(N9)

TOP_AON

Host interface

device controller

HIF_host_CM4

Host interface host

controller of Wi-Fi

radio

0x5040_0000

0x6000_0000

0x7000_0000

0x5FFF_FFFF

0x6FFF_FFFF

0x70FF_FFFF

(Undefined)

WIFISYS

TOP_OFF(N9)

0x8000_0100[5]

Wi-Fi subsystem

PDA DMA port

Patch Decryption

Accelerator DMA

slave

Virtual FIFO access

ports of N9 DMA

0x7800_0000

0x7800_FFFF

VFF access port

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Start address

0x7900_0000

0x8000_0000

0x8001_0000

0x8002_0000

End address

0x7900_FFFF

0x800C_FFFF

0x8000_FFFF

0x8001_FFFF

0x8002_FFFF

Function

Power Domain

CM4_OFF

Software Clock

gating control

Description

VFF_CM4 access

port

0x8300_0200[3]

Virtual FIFO access

ports of CM4 DMA

APB0

TOP_OFF(N9)

APB bridge 0

(synchronous to N9)

CONFG

N9 subsystem

configuration

DMA

Generic DMA

engine for N9

TOP_CFG_OFF

TOP_OFF(N9)

power domain chip

level configuration

(GPIO, PINMUX, RF,

CLK control)

0x8003_0000

0x8005_0000

0x8003_FFFF

0x8005_FFFF

UART/BTIF

UART_PTA

TOP_OFF(N9)

0x8000_0100[6]

0x8000_0100[11]

UART or Bluetooth

host interface for

N9

Inter-chip

communication for

PTA

0x8008_0000

0x8009_0000

0x8008_FFFF

0x8009_FFFF

AHB_MON

ACCLR

TOP_OFF(N9)

0x8000_0100[10]

0x8000_0100[13]

AHB bus monitor

Bluetooth audio

Packet Loss

Concealment

accelerator

0x800A_0000

0x800B_0000

0x800A_FFFF

0x800B_FFFF

UART_DSN

SEC

TOP_OFF(N9)

0x8000_0100[7]

UART for N9 debug

Secure boot

configuration

0x800C_0000

0x8100_0000

0x800C_FFFF

0x810C_FFFF

HIF

TOP_OFF(N9)

Host interface

configuration

APB1

APB bridge 1

(synchronous to N9)

0x8100_0000

0x8102_0000

0x8100_FFFF

0x8102_FFFF

BTSYS

TOP_OFF(N9)

TOP_AON

0x8000_0100[24]

Bluetooth

subsystem

TOP_AON power

domain chip level

configuration (RGU,

PINMUX, PLL, PMU,

XTAL, CLK control)

TOP_CFG_AON

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Start address

0x8103_0000

0x8104_0000

0x8105_8000

0x8106_0000

End address

0x8103_FFFF

0x8104_FFFF

0x8105_FFFF

0x8106_FFFF

Function

DBG_CIRQ

CIRQ

Power Domain

TOP_AON

Software Clock

gating control

Description

Debug interrupt

controller for N9

TOP_AON

Interrupt controller

for N9

GPT

TOP_AON

General Purpose

Timer for N9

PTA

TOP_OFF(N9)

0x8000_0100[14]

0x8000_0100[12]

Packet Traffic

Arbitrator for Wi-

Fi/Bluetooth

coexistence

0x8107_0000

0x8108_0000

0x8107_FFFF

0x8108_FFFF

EFUSE_MAC

WDT

TOP_OFF(N9)

TOP_AON

Efuse controller

Watchdog Timer for

N9

0x8109_0000

0x8109_FFFF

PDA

TOP_OFF(N9)

Patch Decryption

Accelerator

0x810A_0000

0x810B_0000

0x810A_FFFF

0x810B_FFFF

RDD

TOP_OFF(N9)

0x8000_0100[23]

0x8000_0100[15]

Wi-Fi debug

BTSBC

Bluetooth SBC

accelerator

0x810C_0000

0x8300_0000

0x810C_FFFF

RBIST

APB2

TOP_OFF(N9)

CM4_OFF

RF BIST

configuration

APB bridge 1

(synchronous to

CM4)

0x8300_0000

0x8300_7FFF

CONFG_CM4

CM4_OFF

TOP_AON

System

configuration for

CM4

TOP_AON

configuration

0x8300_8000

0x8300_C000

0x8300_BFFF

0x8300_EFFF

TOP_CFG_AON_C

M4

CONFG_CM4_AON TOP_AON

System

configuration for

CM4 in TOP_AON

domain

0x8300_F000

0x8301_0000

0x8302_0000

0x8300_FFFF

0x8301_FFFF

0x8302_FFFF

SEC_TOP_CM4

DMA_CM4

CM4_OFF

0x8300_0200[0]

0x8300_0200[3]

0x8300_0200[4]

JTAG Secure for

CM4

Generic DMA

engine for CM4

UART_DSN

UART for CM4

debug

0x8303_0000

0x8304_0000

0x8303_FFFF

0x8304_FFFF

UART1

UART2

CM4_OFF

0x8300_0200[5]

0x8300_0200[6]

UART 1 for CM4

UART 2 for CM4

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Start address

0x8305_0000

0x8306_0000

0x8307_0000

0x8308_0000

0x8309_0000

0x830A_0000

End address

0x8305_FFFF

0x8306_FFFF

0x8307_FFFF

0x8308_FFFF

0x8309_FFFF

0x830A_FFFF

Function

GPT_CM4

IrDA

Power Domain

TOP_AON

CM4_OFF

TOP_AON

CM4_OFF

Software Clock

gating control

Description

General Purpose

Timer for CM4

0x8300_0200[8]

0x8300_0200[9]

0x8300_0200[10]

IrDA

Serial flash

WDT_CM4

I2C_1

Serial flash macro

access

Watchdog Timer for

CM4

0x8300_0200[12]

0x8300_0200[23]

0x8300_0200[13]

0x8300_0200[24]

0x8300_0200[14]

I2C 1

I2C_2

I2C 2

0x830B_0000

0x830C_0000

0x830B_0FFF

0x830C_FFFF

I2S

CM4_OFF

RTC

I2S configuration

Real time clock

RTC

0x830D_0000 0x830D_FFFF

AUXADC

CM4_OFF

0x8300_0200[16]

0x8300_0200[17]

0x8300_0200[18]

Auxiliary ADC

configuration

0x830E_0000

0x830E_FFFF

BTIF

CM4_OFF

Host Interface for

Bluetooth radio

0x830F_0000

0xA000_0000

0x830F_FFFF

0xAFFF_FFFF

Crypto

PSE

CM4_OFF

Crypto engine

Packet switch

engine memory

0xE000_E000

0xE000_EFFF

NVIC, SYSTICK, FPU CM4_OFF

Nested vectored

interrupt controller

System Control

Space (SYSTICK)

Floating-point unit

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2.4.12

SYSRAM_CM4

SYSRAM, the internal SRAM, is mapped on the system bus interface of Cortex-M4. M4 can carry out

instruction fetches and data accesses to the SYSRAM.

SYSRAM is the internal SRAM that the DMA engine can access. It can be used as a GDMA or VFIFO

buffer, the source and the destination of GDMA controller, for memory-to-memory transfer as well

the transfer between memory and peripherals.

2.4.13

Crypto engine

The crypto engine supports

.

AES, DES, and 3DES encryption and decryption engine.

SHA256, SHA512 and MD5 hash engines.

2.5

Peripherals

Several peripheral are multiplexed GPIOs. MT7697D has two dedicated UART interfaces with flow

control, one dedicated I2C interface, and one dedicated IrDA interface.

MT7697D also has the 2^ndI2C interface, the SPI slave interface, the I2S interface, and the SPI master

interface, but only 2 of the above interfaces can be effective at a time.

The section describes the function of all the peripherals.

2.5.1

GPIO Interface

GPIO Function

2.5.1.1

There are two types of GPIO (General purpose IO) designs in MT7697D: GPIO and AGPIO.

Floating-well design is used in GPIO and AGPIO. It prevents potential leakage problem when the

DVDD33 power supply is not enabled but the pin input is pulled up to 3.3V source.

MT7697D offers GPIO, each with the following configuration options:

.

Input / Output mode

Slew rate control

Schmitt trigger hysteresis control

Input mode: Floating (Hi-Z), pull-up, or pull-down

Output mode: Active driving, or open drain

Pull up/down control. The pull-up and pull-down resistance is 75KΩ with ±20% variation

over PVT condition

.

Driving strength: 4mA, 8mA, 12mA, 16mA

Input and output duty cycle tuning

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AGPIO Function Table

G E Function

=============================

0 0 Analog Function (IO <- -> AIO)

0 1 Analog Function (IO <- -> AIO)

---------------------------------------------------

1 0 Digital Function (IO -----> O)

1 1 Digital Function (IO <- -- I)

(4 – 16 mA Driving)

Floating Well

4 – 16 mA

Floating Well

4 – 16 mA

IO

I

IO

I

E

G

Logic 1 -> Switch on

PU

PD

PU

O

PD

AIO_ANALOG_DONT_TOUCH

AGPIO

GPIO

Figure 2-11. AGPIO/GPIO Block Diagram (Left: AGPIO; Right: GPIO)

The digital IO AGPIO function is equivalent to GPIO as shown above. A dedicated internal control

signal is used to select between the digital and analog functions. The IOs are multiplexed with 16

channels ADC.

Output Signal Multiplexing

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Function-[9:1]-AON and Function-[9:0] can all be output to PINX by setting pinx_pinmux_aon_sel and

pinx_pinmux_off_sel, as shown in Figure 2-12 below. Function-[9:1]-AON signals are part of

TOP_AON domain and Function-[9:0] signals are part of TOP_OFF (N9) domain. The output of the

pad is enabled through E and G pad controls which require 2’b11 for digital output mode.

For a specific pin there could be only a limited number of functions available, these functions are

mapped anywhere to the different inputs of the muxes (not always in an incremental scheme).

TOP_AON domain means the circuit is always powered on when PMU supplies the power. TOP_OFF

(N9) domain means the N9 related circuit is powered off in some scenarios when PMU supplies the

power.

pinx_pinmux_aon_sel

pinx_pinmux_off_sel

Function 0 (O)

Function 1 (O)

Function 2 (O)

0

1

PINX

IO

I

PAD_PINX

0

1

2

ISO

Function 1 AON (O)

Function 2 AON (O)

2

E

1'b1

9

Function 9 (O)

G

TOP_OFF(N9) domain

9

Function 9 AON (O)

Logic 1

->Switch on

PU

PD

O

TOP_AON domain

AIO_ANALOG_DONT_TOUCH

Figure 2-12. AGPIO Configured as Output Multiplexing

Input Signal Multiplexing

Figure 2-13 below shows that PINX is the source of Function-AON-0, while PINX and PINY can both

be the input source for Function-1. The (E, G) setting for both IO is 2’b01 for digital input mode.

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PINX

IO

I

pinx_pinmux_aon_sel

E

1'b0

1'b1

1'b0

0

1

G

Function AON 0

PINX

Logic 1

->Switch on

PU

PD

O

pinx_pinmux_aon_sel

1

pinx_pinmux_sel

1

0

Function 1

AIO_ANALOG_DONT_TOUCH

1'b0

0

piny_pinmux_aon_sel

PINY

IO

I

1

0

1'b0

E

1'b0

1'b1

TOP_AON domain

TOP_OFF domain

G

Logic 1

->Switch on

PU

PD

O

AIO_ANALOG_DONT_TOUCH

Figure 2-13. AGPIO Configured as Input Multiplexing

Input / Output / Analog Signal Multiplexing

This figure below shows how function-0, function-1 and Analog-function share the same IO (PINX) by

configuring (E, G) pair internally. G is controlled in off domain.

Table 2-16. Functional Description of AGPIO

(G,E) value

2’b11

2’b10

2’b0x

Function

PINX=Function-0

(output mode)

Function-1=PINX

(input mode)

Analog-function=PINX

(analog mode)

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PINX

IO

I

Function 0

E

G

Logic 1

->Switch on

PU

PD

O

Function 1

Analog function

AIO_ANALOG_DONT_TOUCH

Figure 2-14. AGPIO Configured as Input, Output, or Analog Mode

Open Drain Mode

The GPIO can be configured as open drain mode by assigning I=1’b0, G=1’b1 and E=Function-0.

PINX

1'b0

IO

I

E

Function 0

1'b1

G

Logic 1

->Switch on

PU

PD

O

AIO_ANALOG_DONT_TOUCH

Figure 2-15. GPIO Configured as Open Drain Mode

2.5.2

UART Interface

MT7697D has two UART interfaces. The UART has M16C450 and M16550A modes of operation,

which are compatible with a range of standard software drivers.MT7697D supports UART with

configurable BAUD rates from 9.6Kbps, 19.2Kbps, 38.4Kbps, 115.2Kbps, and 921.6Kbps.

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2.5.3

I2C Serial Interface

MT7697D features two I2C serial interface master controllers. The two signals of I2C channel 0 are

I2C0_CLK and I2C0_DATA.

.

I2C0_CLK is a clock signal that is driven by the master.

I2C0_DATA is a bi-directional data signal that can be driven by either the master or the slave.

It supports the clock rate of 50, 100, 200, and 400 KHz.

.

I2C channel 1 supports the same feature as channel 0.

2.5.4

Auxiliary ADC function

MT7697D features one auxiliary ADC function. The ADC function contains a 4-channel analog switch,

a single-end input asynchronous 12-bit SAR (Successive Approximation Register) ADC, and a digital

averaging function. The digital averaging function can perform on-the-fly averaging function of

1/2/4/8/16/32/64 points. The ADC features the dithering function to enhance the DNL performance.

The ADC uses an external VREF20 as a reference voltage.

AUXADC_MUX[3:0]

CDAC

AUXADC0

Vin

Vref

Vin

MUX

0

AUXADC3

SAR

12

Vin

Digital

Output

CMP

Control

Logic

Vref

Vref=1.8V

0

VREF20

Vin

Vrdac

0

CLK

(2MHz)

Vcm buf

VCM

Figure 2-16. Auxiliary ADC Block Diagram (Analog Part)

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Digital averaging

ADC IP (Analog)

CLKOUT(2MS/s)

12

1/2/4/8/16/32/64

average

4-to-1

MUX

ADC

12

Bus

Memory

interface

hclk_ck

MCU

Interrupt

AUXADC_MUX[3:0]

ADC_EN

CLK(2MS/s)

REG_AVG_MODE[2:0]

Figure 2-17. Auxiliary ADC Block Diagram

0.5 uS

ADC sampling

Sample #3

ADC bit-cycling

ADC sampling

Sample #4

ADC bit-cycling

ADC sampling

Sample #5

ADC bit-cycling

2MHz Clock

Internal asyn. Clock

AUXADC_DOUT

DOUT #1

DOUT #2

DOUT #3

Figure 2-18. Auxiliary ADC Clock Timing Diagram

Auxiliary ADC Features:

.

Input channel number: 4 channels

Sampling and output data rate: 2MS/s

DNL without dithering and averaging: <±2LSB

DNL with dithering and averaging: <±1LSB

Dithering function: 16 levels with step size of 4LSB.

2.5.5

SPI Master Interface

MT7697D features one SPI master controller. It is used as an extension interface to control the

peripheral device on expansion port. The SPI master controller supports the clock rates of 0.25, 0.5, 1,

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2, 4, 6, 8, 10, and 12MHz. It supports two options of clock polarity (CPOL) and two options of initial

clock phase (CPHA). SPI pins are multiplexed with I2S pins.

Table 2-17. SPI Pin Description

Signal Name Signal Description

Direction

Output

Input

CS

Chip select

SCK

Serial clock

MISO

MOSI

Master in, Slave out

Master out, Slave in

Output

CS_N

idle time

Data Transmission

CS_N

CS_N setup time

CS_N hold time

SCK

(CPOL=0)

SCK Edge

Number

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCK

(CPOL=1)

SAMPLE MOSI/MISO

(CPHA=0)

SAMPLE MOSI/MISO

(CPHA=1)

Figure 2-19. SPI Timing Diagram

2.5.6

2.5.7

SPI Slave Interface

I2S Interface

MT7697D features one I2S interface, which is used to connect to an external audio codec. The I2S

interface can support the I2S slave mode only. The five I2S signals are shown below. The I2S_MLK

clock frequency is 16MHz.

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Table 2-18. I2S Pin Description

Signal Name

I2S_MCLK

Signal Description

Direction (Slave Mode)

The base clock of the function.

The bit clock of the interface

Output

Input

I2S_BCLK

I2S_FS (LRCLK)

The left/right word select line

of the interface

Input

I2S_TX

I2S_RX

Digital audio output

Digital audio input

Output

Input

MT7697D supplies the MCLK of 16MHz. The external CODEC generates BCLK and LRCLK from MCLK.

When configured as the I2S slave mode, the I2S interface can support two modes.

Table 2-19. I2S Slave Mode

Slave Mode Bit Width

Input Sample (Uplink) Output Sample

(Downlink)

BCLK

(Input)

FS (Input)

Mode 1

Mode 2

16b

16KHz, mono

512KHz

16KHz

24KHz

24KHz, mono

768KHz

The mono data is transferred across the I2S bus as left channel information.

In all of the modes above, when the input data is mono, the data of interest is transferred across the

I2S bus on the left channel.

The I2S pins are multiplexed with SPI pins.

The signal waveform of I2S is shown below.

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1/SR

…

I2S_BCLK

I2S_FS

1T delay

…

R[0]

L[15] L[14] L[13]

L[2]

L[1]

L[0]

R[15] R[14]

R[2]

R[1]

R[0]

R[13]

I2S_TX/RX

Left channel

Right channel

Figure 2-20. I2S Signal Waveform

2.5.8

Pulse Width Modulation (PWM)

MT7697D features 28 generic PWMs to generate pulse sequences with programmable frequency and

duration for LCD, vibrators, and other devices. The PMU features three configurable pattern options.

Table 2-20. PWM Modes

Mode

Description

Basic PWM:

Waveform

1

LED ON

LED OFF

LED ON time (duration) and LED

OFF time (duration) are

configurable.

LED ON

Time

LED OFF

Time

2

3

Two-State PWM:

S0

S1

There are two configurable states

(S0 and S1) for PWM LED.

S0 Lastingtime

Two-State replay mode:

replay

User can set replay mode with

specified S1_Lasting_Time. PWM

LED would act as

S0

S0 Lastingtime

S1

S0

S0 Lastingtime

S1 Lastingtime

[S0àS1àS0àS1àS0…] with

period time of (S0_Lasting_Time +

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Mode

Description

S1_Lasting_Time)

Waveform

2.5.9

IrDA

IrDA TX module supports consumer IR protocols including NEC, RC-5, RC-6, and the software-based

pulse-width mode. IrDA RX module supports protocols including RC-5 and pulse-width detection

mode.

2.6

Radio MCU Subsystem

2.6.1

CPU

MT7697D features 32-bit CPU N9, with the following features:

.

5-stage pipeline with extensive clock-gating

Dynamic branch prediction with BTB

16/32-bit mixed instruction format

Multiply-accumulate and multiply-subtract instructions

Instructions optimized for audio applications

Instruction and data local memory

JTAG based debug interface

Programmable data endian control

2.6.2

RAM/ROM

The Radio MCU subsystem features ILM (Instruction Local Memory), DLM (Data Local Memory), and

the SYSRAM. The ROM code is in ILM.

2.6.3

Memory map

The table below describes how the peripherals are mapped to the memory space in Radio MCU

subsystem.

When the MCU performs a read transaction to an undefined address, the bus returns 0. When the

MCU performs a write transaction to an undefined address, the bus regards it as an invalid

transaction and does nothing.

Table 2-21. N9 Memory Map

Start address

End address

Function

Description

0x0000_0000

0x000C_FFFF

ILM ROM

Instruction local memory ROM

for N9

0x000D_0000

0x0011_FFFF

ILM RAM

Instruction local memory RAM

for N9

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Start address

0x0200_0000

0x0209_0000

0x0040_0000

0x2000_0000

0x2100_0000

0x2200_0000

0x2400_0000

0x3000_0000

End address

0x0200_021C

0x020C_1FFF

0x0040_CFFF

0x2003_FFFF

0x2100_FFFF

0x2200_FFFF

0x2400_FFFF

0x3FFF_FFFF

Function

Description

Patch & CR

DLM RAM

SYSRAM N9

SYSRAM CM4

SPI-S

I2S/Audio

(Reserved)

Serial Flash CM4

N9 ROM patch engine

Data local memory for N9

System RAM for N9

System RAM for CM4 (256KB)

SPI slave

I2S

Serial flash controller of CM4

Host interface device controller

0x5000_0000

0x5020_0000

0x501F_FFFF

0x502F_FFFF

HIF_device

HIF_host_CM4

Host interface host controller

of Wi-Fi radio

0x6000_0000

0x7000_0000

0x6FFF_FFFF

0x70FF_FFFF

WIFISYS

PDA DMA port

Wi-Fi subsystem

Patch Decryption Accelerator

DMA slave

0x7800_0000

0x7800_0100

0x7900_0000

0x8000_0000

0x7800_0000

0x7800_0100

0x7900_FFFF

0x800C_FFFF

VFF access port0

VFF access port1

Virtual FIFO access port 0 of N9

DMA

Virtual FIFO access port 1 of N9

DMA

Virtual FIFO access ports of

CM4 DMA

APB bridge 0 (synchronous to

N9)

VFF_CM4 access

port

APB0

0x8000_0000

0x8001_0000

0x8002_0000

0x8000_FFFF

0x8001_FFFF

0x8002_FFFF

CONFG

DMA

TOP_CFG_OFF

N9 subsystem configuration

Generic DMA engine for N9

TOP_OFF(N9) power domain

chip level configuration (GPIO,

PINMUX, RF, PLL, CLK control)

0x8003_0000

0x8005_0000

0x8003_FFFF

0x8005_FFFF

UART/BTIF

UART_PTA

UART or Bluetooth host

interface for N9

Inter-chip communication for

PTA

0x8008_0000

0x8009_0000

0x8008_FFFF

0x8009_FFFF

AHB_MON

ACCLR

AHB bus monitor

Bluetooth audio Packet Loss

Concealment accelerator

0x800A_0000

0x800B_0000

0x800C_0000

0x800A_FFFF

0x800B_FFFF

0x800C_FFFF

UART_DSN

SEC

HIF

UART for N9 debug

Secure boot configuration

Host interface configuration

0x8100_0000

0x810C_FFFF

0x8100_FFFF

APB1

APB bridge 1 (synchronous to

N9)

Bluetooth subsystem

BTSYS

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Start address

End address

Function

Description

0x8102_0000

0x8102_FFFF

TOP_CFG_AON

TOP_AON power domain chip

level configuration (RGU,

PINMUX, PMU, XTAL, CLK

control)

0x8103_0000

0x8103_FFFF

DBG_CIRQ

Debug interrupt controller for

N9

0x8104_0000

0x8105_8000

0x8104_FFFF

0x8105_FFFF

CIRQ

GPT

Interrupt controller for N9

General Purpose Timer for N9

0x8106_0000

0x8106_FFFF

PTA

Packet Traffic Arbitrator for Wi-

Fi/Bluetooth coexistence

0x8107_0000

0x8108_0000

0x8109_0000

0x8107_FFFF

0x8108_FFFF

0x8109_FFFF

EFUSE

WDT

PDA

Efuse controller

Watchdog Timer for N9

Patch Decryption Accelerator

0x810A_0000

0x810B_0000

0x810C_0000

0x8300_0000

0x810A_FFFF

0x810B_FFFF

0x810C_FFFF

RDD

Wi-Fi debug

BTSBC

RBIST

APB2

Bluetooth SBC accelerator

RF BIST configuration

APB bridge 1 (synchronous to

CM4)

0x8300_0000

0x8301_0000

0x8300_FFFF

0x8301_FFFF

CONFG_CM4

DMA_CM4

System configuration for CM4

Generic DMA engine for CM4

0x8302_0000

0x8303_0000

0x8304_0000

0x8305_0000

0x8302_FFFF

0x8303_FFFF

0x8304_FFFF

0x8305_FFFF

UART_DSN

UART1

UART2

UART for CM4 debug

UART 1 for CM4

UART 2 for CM4

General Purpose Timer for

CM4

GPT_CM4

0x8306_0000

0x8307_0000

0x8308_0000

0x8309_0000

0x830A_0000

0x830B_0000

0x830D_0000

0x830E_0000

0x8306_FFFF

0x8307_FFFF

0x8308_FFFF

0x8309_FFFF

0x830A_FFFF

0x830B_FFFF

0x830D_FFFF

0x830E_FFFF

IrDA

Serial flash

WDT_CM4

I2C_1

I2C_2

I2S

Serial flash macro access

Watchdog Timer for CM4

I2C 1

I2C 2

I2S configuration

Auxiliary ADC configuration

Host Interface for Bluetooth

radio

AUXADC

BTIF

0x830F_0000

0xA000_0000

0x830F_FFFF

0xAFFF_FFFF

Crypto

PSE

Crypto engine

Packet switch engine memory

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2.6.4

N9 Bus Fabric

CM4

SYSTEM BUS

Command Batch

(low power data

retention)

ILM ROM (832KB)

ILM RAM (320KB)

N9

Generic DMA

Asyncrhrous AHB-2-

AHB bridge

DLM RAM (200KB)

(CM4 bus to N9 bus)

N9 AHB bus

Asyncrhrous AHB-2-

AHB bridge

(N9 bus to CM4 bus)

APB

bridge

APB

bridge

WiFi HIF

PSE

SYSRAM_N9

(52KB)

WIFI MAC

CM4 AHB bus

WIFI Baseband

WIFI RF

APB1 bus

APB0 bus

GDMA

CONFIG

UART_D

SN

UART_P

TA

TOP

CONFIG

BTSYS

GPT

CIRQ

PDA

WDT

EFUSE

MAC

HIF

CONFIG

UART

/BTIF

N9

CONFIG

RDD

BT_SBC

ACCLR

PTA

Interface to CM4 bus/peripheral

N9 peripheral

Figure 2-21. N9 Bus Fabric

Functional description:

.

Command batch: Used to save/restore the critical CR and memory data when entering

and leaving the low power mode.

.

Wi-Fi HIF: The host control and data interface from N9 to Wi-Fi subsystem.

Wi-Fi PSE: The Packet switch engine used to transfer packet from N9 to Wi-Fi MAC/Radio

or from CM4 to Wi-Fi MAC/Radio, and vice versa.

.

PDA: Packet Decryption Agent, used to download firmware and decipher the firmware

which is encrypted to avoid eavesdrop.

PTA: Packet Traffic Arbitration, used to do the traffic arbitration of Wi-Fi and Bluetooth

when the two radios are transmitting and receiving at the same time.

RDD: The Wi-Fi debug function.

BT_SBC: The hardware accelerating engine for Bluetooth audio codec.

EFUSE: The Efuse macro used for the configuration of Wi-Fi/Bluetooth MAC and Radio.

ACCLR: The hardware accelerating engine for Bluetooth Packet Loss Concealment.

.

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2.6.5

CIRQ

N9 subsystem uses the interrupt controller CIRQ to control the source selection, mask, edge/level

sensitivity, and software enabling for internal interrupts, as well as the mask and the edge/level

sensitivity for external interrupts.

CIRQ also integrates the de-bounce circuit for external interrupts.

FIQ control

Interrupt

De-bounce

select

External

interrupt

control

De-bounce

IRQ contro

De-bounce

Control register

Figure 2-22. N9 interrupt controller

2.6.5.1

Interrupt sources

The tables below lists the interrupt sources of internal and external interrupts.

There are totally 23 interrupts and 14 external interrupts.

The power domain/subsystem lists the power domain and the subsystem from which the interrupt is

generated.

Wake-up

IRQ

No.

Interrupt

source

Power domain

/subsystem

External

interrupt

De-

capability

(1)

Description

bounce

TOP_OFF(N9)/MCUSY

S

INT0

INT1

UART

DMA

UART/BTIF module

TOP_OFF(N9)/MCUSY

S

Generic DMA in N9 subsystem

INT2

INT3

INT4

INT5

INT6

HIFSYS

BT_TIMCON

THERM

TOP_AON/HIF

TOP_AON/BTSYS

TOP_OFF(N9)

WIFI_HIF(SDIO)

Bluetooth TIMCON module

Thermometer

(Reserved)

WIFI

WF_OFF

Wi-Fi subsystem

TOP_OFF(N9)/MCUSY

S

INT7

ICAP

Internal capture in RBIST module

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Wake-up

capability

(1)

IRQ

No.

Interrupt

source

Power domain

/subsystem

External

interrupt

De-

Description

bounce

INT8

INT9

INT10

EINT

TOP_AON/MCUSYS

External interrupt

(Reserved)

WDT_N9

TOP_AON/MCUSYS

TOP_OFF(N9)/MCUSY

S

Watch dog timer in N9 subsystem

AHB monitor

INT11

INT12

INT13

AHB_MONITOR

(Reserved)

TOP_OFF(N9)/MCUSY

S

PLC_ACCLR

Packet Loss Concealment accelerator

INT14

INT15

(Reserved)

PSE

WF_OFF/PSE

TOP_OFF(N9)/MCUSY

S

Packet switch engine

Bluetooth SBC CODEC accelerator

HIF subsystem

INT16

INT17

INT18

MSBC

HIFSYS

TOP_OFF(N9)/HIFSYS

TOP_OFF(N9)/MCUSY

S

UART_PTA *

UART_PTA module

TOP_OFF(N9)/MCUSY

S

INT19

PTA *

PTA module

INT20

INT21

CMBT

GPT3

TOP_OFF(N9)

TOP_AON/MCUSYS

TOP_AON/MCUSYS_C

M4

Command batch module

General purpose timer module

INT22

WDT_CM4

CM4 WDT interrupt N9

EINT0

EINT1

EINT2

UART_RX

(Reserved)

HIFSYS

TOP_AON

V

Available

Wake up from UART

TOP_AON/HIF

TOP_AON/MCUSYS_C

M4

WIFI_HIF (SDIO)

CM4_TO_N9_S

W

CM4 SW interrupt N9

83080080[31:30] SW_INT

Wake up from Bluetooth

Wake up from PCIe

General purpose timer module (GPT0

timer and GPT1 timer)

External interrupt

EINT3

V

Available

EINT4

EINT5

Bluetooth

PCIE *

TOP_AON/BTSYS

TOP_OFF(N9)/HIFSYS

V

Available

EINT6

EINT7

EINT8

GPT

TOP_AON/MCUSYS

TOP_AON

V

Available

External interrupt

Pin: GPIO58

External interrupt

TOP_AON

Pin: GPIO57

External interrupt

EINT9

External interrupt

(Reserved)

TOP_AON

V

Available

Pin: GPIO30

EINT10

EINT11

External interrupt

Pin: GPIO38

External interrupt

TOP_AON

External interrupt

EINT12

EINT13

External interrupt

V

Available

Pin: GPIO39

CM4_TO_N9_B

TIF_WAKEUP

CM4 to N9 BTIF wake-up

830E0064[0] BTIF_WAK

*: Not used for MT7697D

Note 1; Capable to wake up N9 when N9 is in sleep mode.

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2.7

Wi-Fi Subsystem

2.7.1

Wi-Fi MAC

MT7697D MAC supports the following features:

.

Supports all data rates of 802.11a/g including 6, 9, 12, 18, 24, 36, 48, and 54Mbps

Supports short GI and all data rates of 802.11n including MCS0 to MCS7

802.11 to 802.3 header translation offload

RX TCP/UDP/IP checksum offload

Supports multiple concurrent clients as an access point

Supports multiple concurrent clients as a repeater

Aggregate MPDU RX (de-aggregation) and TX (aggregation) support

Transmits beamforming as a beamformee

Transmits rate adaptation

Transmits power control

Security

64-bit WEP (WEP-40) and 128-bit WEP (WEP-104) encryption with hardware TKIP and

CKIP processing

.

AES-CCMP hardware processing

SMS4-WPI (WAPI) hardware processing

2.7.2

WLAN Baseband

MT7697D baseband supports the following features:

.

20 and 40MHz channels

MCS0-7 (BPSK, r=1/2 through 64QAM, r=5/6)

Short Guard Interval

STBC support

Low Density Parity check (LDPC) coding

Support digital pre-distortion to enhance PA performance

Smoothing (channel estimation) extension to MIMO case

2.7.3

WLAN RF

MT7697D RF supports the following features:

.

Integrated 2.4GHz/5GHz PA and LNA, and T/R switch

Integrated 5GHz Balun

Support frequency band

2400-2497MHz

5150-5350MHz

5470-5725MHz

5725-5850MHz

5850-5925MHz

Support RX antenna diversity for both 2.4GHz/5GHz band to eliminate the requirement

of an external SPDT

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2.8

Bluetooth Subsystem

MT7697D Bluetooth supports the following features:

.

Bluetooth v4.2 + LE compliance

Bluetooth and Bluetooth low energy dual mode

Single-ended, RF port with integrated Balun and T/R switch

Integrated high efficiency PA

Baseband and radio BDR and EDR packet types: 1Mbps (GFSK), 2Mbps (π/4-DQPSK), and

3Mbps (8PSK).

.

Fully functional Bluetooth baseband: AFH, forward error correction, header error control,

access code correlation, CRC, whitening.

.

Standard pairing, authentication, link key, and encryption operation.

Standard power saving mechanisms: sniff mode and sniff-subrating.

Interlaced scan for faster connection setup

Full master and slave piconet support

Up to seven simultaneous active ACL connections with background inquiry and page scan

Scatternet support

Channel quality driven data rate control

2.9

RTC

MT7697D features one RTC (Real Time Clock) module. The clock source is the 32.768 KHz Crystal or

an external clock source. RTC has built in an accurate timer to wake up the system when it expires.

RTC uses a different power rail from PMU. In the hibernate mode, the PMU is turned off while the

RTC module is remained powered on. The RTC module only consumes 3uA in hibernate mode.

RTC has a dedicated PMU control pin PMU_EN_RTC (pin 23) used to turn on the power to the chip

when the RTC timer expires and turn off the power to the chip when it intends to enter the hibernate

mode.

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3

Radio Characteristics

3.1

Wi-Fi Radio Characteristics

3.1.1

Wi-Fi RF Block Diagram

Front-end loss with external Balun (2.4GHz band) and diplexer: 2.4GHz band insertion loss is 2dB,

and 5GHz band insertion loss 1.6dB.

WF0_A_RFIO

M

WF0_G_RFIOP

Antenna port

WF0_G_RFION

TRX

M

Note:

is matching circuits for 50ohm impedance tuning.

Figure 3-1. 2.4/5GHz RF Block Diagram

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3.1.2

Wi-Fi 2.4GHz Band RF Receiver Specifications

The specifications noted in the table below is measured at the antenna port, which includes the

front-end loss.

Table 3-1. 2.4GHz RF Receiver Specification

Parameter

Description

Performance

MIN

TYP

MAX

Unit

MHz

dBm

Frequency range

RX sensitivity

Center channel frequency

1 Mbps CCK

2412

2484

-

-96.4

-93.4

-91.4

-88.4

-93.4

-91.1

-90.3

-87.9

-84.6

-81.2

-77.0

-75.7

-92.7

-89.5

-87.1

-84.1

-80.6

-76.2

-74.8

-73.6

-89.6

-86.8

-84.3

-80.8

-77.7

-

2 Mbps CCK

5.5 Mbps CCK

11 Mbps CCK

RX sensitivity

BPSK rate 1/2, 6 Mbps OFDM

BPSK rate 3/4, 9 Mbps OFDM

QPSK rate 1/2, 12 Mbps OFDM

QPSK rate 3/4, 18 Mbps OFDM

16QAM rate 1/2, 24 Mbps OFDM

16QAM rate 3/4, 36 Mbps OFDM

64QAM rate 1/2, 48 Mbps OFDM

64QAM rate 3/4, 54 Mbps OFDM

MCS 0, BPSK rate 1/2

RX Sensitivity

BW=20MHz

Mixed mode

MCS 1, QPSK rate 1/2

MCS 2, QPSK rate 3/4

800ns Guard

Interval

MCS 3, 16QAM rate 1/2

MCS 4, 16QAM rate 3/4

MCS 5, 64QAM rate 2/3

MCS 6, 64QAM rate 3/4

MCS 7, 64QAM rate 5/6

MCS 0, BPSK rate 1/2

Non-STBC

RX Sensitivity

BW=40MHz

Mixed mode

MCS 1, QPSK rate 1/2

MCS 2, QPSK rate 3/4

800ns Guard

Interval

MCS 3, 16QAM rate 1/2

MCS 4, 16QAM rate 3/4

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Parameter

Non-STBC

Description

Performance

MIN

TYP

-73.1

-71.8

-70.6

-10

-20

40

MAX

Unit

dBm

MCS 5, 64QAM rate 2/3

MCS 6, 64QAM rate 3/4

MCS 7, 64QAM rate 5/6

6 Mbps OFDM

-

Maximum Receive

Level

54 Mbps OFDM

MCS0

MCS7

Receive Adjacent

Channel Rejection

1 Mbps CCK

11 Mbps CCK

40

BPSK rate 1/2, 6 Mbps OFDM

64QAM rate 3/4, 54 Mbps OFDM

HT20, MCS 0, BPSK rate 1/2

HT20, MCS 7, 64QAM rate 5/6

HT40, MCS 0, BPSK rate 1/2

HT40, MCS 7, 64QAM rate 5/6

34

22

33

15

29

9

3.1.3

Wi-Fi 2.4GHz Band RF Transmitter Specifications

The specifications in table are measured at the antenna port, which includes the front-end loss.

Table 3-2. 2.4GHz RF Transmitter Specifications

Parameter

Description

Performance

MIN

TYP

MAX

Unit

MHz

dBm

Frequency range

2412

-

2484

Output power with

spectral mask and

EVM compliance

1 Mbps CCK

-

21

19

18

17.5

17

-

11 Mbps CCK

6 Mbps OFDM

54 Mbps OFDM

HT20, MCS 0

HT20, MCS 7

HT40, MCS 0

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Parameter

TX EVM

Description

Performance

MIN

TYP

MAX

-

Unit

dBm

dB

HT40, MCS 7

6 Mbps OFDM

54 Mbps OFDM

HT20, MCS 0

HT20, MCS 7

HT40, MCS 0

HT40, MCS 7

-

16.5

-

-5

-

-25

-5

dB

-

dB

-

-28

-5

dB

-

dB

-

-28

1.5

dB

Output power

variation⁽¹⁾

TSSI closed-loop control across all temperature

range and channels and VSWR ≦ 1.5:1.

-1.5

dB

Carrier suppression

-

-30

-43

dBc

Harmonic Output

Power

2nd Harmonic

3nd Harmonic

-45

dBm/MHz

Note 1: VDD33 voltage is within ±5% of typical value.

3.1.4

Wi-Fi 5GHz Band RF Receiver Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

Table 3-3. 5GHz RF Receiver Specifications

Parameter

Description

Performance

TYP

MIN

MAX

Unit

MHz

dBm

Frequency range

RX sensitivity

Center channel frequency

5180

-

5825

BPSK rate 1/2, 6 Mbps OFDM

BPSK rate 3/4, 9 Mbps OFDM

QPSK rate 1/2, 12 Mbps OFDM

QPSK rate 3/4, 18 Mbps OFDM

16QAM rate 1/2, 24 Mbps OFDM

16QAM rate 3/4, 36 Mbps OFDM

64QAM rate 1/2, 48 Mbps OFDM

64QAM rate 3/4, 54 Mbps OFDM

MCS 0, BPSK rate 1/2

-

-92.8

-90.5

-89.8

-87.3

-84.1

-80.8

-76.4

-75.0

-92.1

-

RX Sensitivity

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Parameter

Description

Performance

MIN

TYP

MAX

Unit

dBm

BW=20MHz HT

Mixed mode

MCS 1, QPSK rate 1/2

MCS 2, QPSK rate 3/4

MCS 3, 16QAM rate 1/2

MCS 4, 16QAM rate 3/4

MCS 5, 64QAM rate 2/3

MCS 6, 64QAM rate 3/4

MCS 7, 64QAM rate 5/6

MCS 0, BPSK rate 1/2

MCS 1, QPSK rate 1/2

MCS 2, QPSK rate 3/4

MCS 3, 16QAM rate 1/2

MCS 4, 16QAM rate 3/4

MCS 5, 64QAM rate 2/3

MCS 6, 64QAM rate 3/4

MCS 7, 64QAM rate 5/6

6 Mbps OFDM

-

-89.1

-86.6

-83.6

-80.1

-75.6

-74.2

-73.0

-89.1

-85.9

-83.5

-80.2

-76.9

-72.6

-71.2

-70.1

-10

-

800ns Guard

Interval

Non-STBC

RX Sensitivity

BW=40MHz HT

Mixed mode

800ns Guard

Interval

Non-STBC

Maximum Receive

Level

54 Mbps OFDM

-20

MCS0

-15

MCS7

-20

Receive Adjacent

Channel Rejection

BPSK rate 1/2, 6 Mbps OFDM

64QAM rate 3/4, 54 Mbps OFDM

HT20, MCS 0, BPSK rate 1/2

HT20, MCS 7, 64QAM rate 5/6

HT40, MCS 0, BPSK rate 1/2

HT40, MCS 7, 64QAM rate 5/6

25

7

24

3

24

3

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3.1.5

Wi-Fi 5GHz Band RF Transmitter Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

Table 3-4. 5GHz RF Transmitter Specifications

Parameter

Description

Performance

MIN

TYP

MAX

Unit

MHz

dBm

dB

Frequency range

5180

-

5825

-

Output power

with spectral

mask and EVM

compliance

6 Mbps OFDM

54 Mbps OFDM

HT20, MCS 0

HT20, MCS 7

HT40, MCS 0

HT40, MCS 7

6 Mbps OFDM

54 Mbps OFDM

HT20, MCS 0

HT20, MCS 7

HT40, MCS 0

HT40, MCS 7

-

16.9

-

16.9

-

16.9

-

15.9

-

15.9

-

15.9

-

TX EVM

-

-5

-25

-5

-28

-5

-28

1.5

-

dB

-

dB

-

dB

-

dB

-

dB

Output power

variation⁽¹⁾

TSSI closed-loop control across all temperature

range and channels and VSWR ≦1.5:1.

-1.5

dB

Carrier

-

-30

dBc

suppression

Harmonic

Output Power

2nd Harmonic

3nd Harmonic

-

-45

-43

dBm/MHz

Note 1: VDD33 voltage is within ±5% of typical value.

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3.2

Bluetooth Radio Characteristics

3.2.1

Bluetooth RF block diagram

Front-end loss with external Balun and diplexer: 2.4GHz insertion loss 2dB.

WF0_A_RFIO

M

WF0_G_RFIOP

Antenna port

WF0_G_RFION

TRX

M

Note:

is matching circuits for 50ohm impedance tuning.

Figure 3-2. Wi-Fi/Bluetooth RF Block Diagram

3.2.2

Basic Rate Receiver Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

Figure 3-3. Basic Rate Receiver Specifications

PARAMETER

DESCRIPTION

PERFORMANCE

MIN

TYP

MAX

2480

UNIT

MHz

Frequency range

2402

-

Receiver sensitivity¹

BER<0.1%

-

-92

-

dBm

dB

Maximum usable signal

C/I co-channel (BER<0.1%)

BER<0.1%

-5

6

-

Co channel selectivity

11

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PARAMETER

DESCRIPTION

PERFORMANCE

MIN

TYP

MAX

UNIT

C/I 1MHz (BER<0.1%)

C/I 2MHz (BER<0.1%)

C/I≥3MHz (BER<0.1%)

Adjacent channel selectivity

2^ndadjacent channel selectivity

3^rdadjacent channel selectivity

Image channel selectivity

-

-7

0

dB

-40

-43

-20

-30

-40

-9

C/I Image channel

(BER<0.1%)

C/I Image 1MHz

(BER<0.1%)

1MHz adjacent to image channel

selectivity

-

-35

-20

dB

Inter-modulation

-39

-10

-30

-

dBm

-

Out-of-band blocking

30MHz to 2000MHz

2000MHz to 2399MHz

2498MHz to 3000MHz

3000MHz to 12.75GHz

-27

-10

-

dBm

Note 1: The receiver sensitivity is measured at the antenna port.

3.2.3

Basic Rate Transmitter Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

Table 3-5. Basic Rate Transmitter Specifications

PARAMETER

DESCRIPTION

PERFORMANCE

MIN

TYP

MAX

UNIT

Frequency range

2402

-

2480

-

MHz

dBm

Maximum transmit

power¹

At maximum power output level

10

Gain step

2

4

8

dB

Modulation

∆f1avg

140

115

0.8

-75

-25

-40

157

121

0.85

±20

±15

175

-

KHz

characteristics

∆f2max (For at least 99.9% of all ∆f2max)

∆f1avg /∆f2avg

-

ICFT

Initial carrier frequency tolerance

One slot packet (DH1)

Two slot packet (DH3)

+75

+25

+40

Carrier frequency

drift

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PARAMETER

DESCRIPTION

PERFORMANCE

MIN

TYP

MAX

UNIT

Five slot packet (DH5)

Max drift rate

-40

±15

-

+40

20

KHz

-20

KHz/50μs

KHz

TX output spectrum 20dB bandwidth

-

1000

-20

-40

In-Band spurious

emission

±2MHz offset

±3MHz offset

>±3MHz offset

-40

-45

dBm

Note 1: The output power is measured at the antenna port.

3.2.4

Enhanced Data Rate Receiver Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

Table 3-6. Enhanced Data Rate Receiver Specifications

PARAMETER

DESCRIPTION

PERFORMANCE

MIN

TYP

MAX

UNIT

FREQUENCY RANGE

2402

-

2480

-

MHZ

DBM

DB

RECEIVER SENSITIVITY

(BER<0.01%)

Π/4 DQPSK

8PSK

-

-91

-85

-5

-

MAXIMUM USABLE SIGNAL

(BER<0.1%)

Π/4 DQPSK

8PSK

-

-5

-

C/I CO-CHANNEL (BER<0.1%)

Π/4 DQPSK

8PSK

9

13

21

0

15

-5

DB

C/I 1MHZ (BER<0.1%)

Π/4 DQPSK

8PSK

DB

-5

5

DB

C/I 2MHZ (BER<0.1%)

Π/4 DQPSK

8PSK

9

-30

-25

-40

-33

-7

0

DB

15

-12

-6

DB

C/I≥3MHZ (BER<0.1%)

Π/4 DQPSK

8PSK

DB

C/I IMAGE CHANNEL (BER<0.1%)

Π/4 DQPSK

8PSK

-40

-36

DB

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C/I IMAGE 1MHZ (BER<0.1%)

Π/4 DQPSK

-

-43

-40

-20

-13

DB

8PSK

3.2.5

Enhanced Data Rate Transmitter Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

PARAMETER

DESCRIPTION

PERFORMANCE

MIN

TYP

MAX

UNIT

Frequency range

2402

-

2480

-

MHz

dBm

dB

Maximum transmit

power¹

π/4 DQPSK

8PSK

7

-

7

-

Relative transmit

power

π/4 DQPSK

8PSK

-4

-1.5

± 4

1

-4

1

dB

Frequency stability

maximum carrier frequency

π/4 DQPSK

8PSK

-10

-75

-20

-13

-30

-20

-35

-25

-

10

75

30

20

-

KHz

%

stability, ωo

± 4

maximum carrier frequency

π/4 DQPSK

8PSK

± 20

± 9

stability, ωi

maximum carrier frequency

π/4 DQPSK

8PSK

stability, |ωo + ωi|

Modulation

accuracy

RMS DEVM

99% DEVM

Peak DEVM

π/4 DQPSK

8PSK

± 9

%

π/4 DQPSK

8PSK

± 15

± 12

± 28

± 21

-30

%

-

%

π/4 DQPSK

8PSK

35

25

-26

%

In-Band

±1MHz offset

π/4 DQPSK

8PSK

dB

-

dB

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PARAMETER

DESCRIPTION

PERFORMANCE

MIN

TYP

MAX

UNIT

spurious emission

±2MHz offset

±3MHz offset

π/4 DQPSK

8PSK

-

-27

-20

-40

dBm

-27

π/4 DQPSK

8PSK

-42.5

Note 1: The output power is measured at the antenna port.

3.2.6

Bluetooth LE Receiver Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

Table 3-7. Bluetooth LE Receiver Specifications

Parameter

Description

PER < 30.8%

Min.

2402

-

Typ.

-

Max.

2480

-

Unit

Frequency Range

MHz

dBm

Receiver Sensitivity

(*)

-95

Max. Usable Signal

C/I Co-channel

C/I 1MHz

PER < 30.8%

-10

-5

6

-

dBm

dB

Co-channel selectivity (PER < 30.8%)

-

21

15

Adjacent channel selectivity (PER <

30.8%)

-7

dB

C/I 2MHz

2nd adjacent channel selectivity (PER

< 30.8%)

-

-30

-33

-17

-27

dB

C/I ≧3MHz

3rd adjacent channel selectivity

(PER < 30.8%)

C/I Image channel

C/I Image 1MHz

Image channel selectivity (PER <

30.8%)

-

-20

-30

-9

dB

1MHz adjacent to image channel

selectivity (PER < 30.8%)

-15

-50

-30

-35

-30

-35

dBm

Inter-modulation

Out-of-band Blocking 30MHz to 2000MHz

2001MHz to 2339MHz

-

2501MHz to 3000MHz

3001MHz to 12.75GHz

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3.2.7

Bluetooth LE Transmitter Specifications

The specifications in table below are measured at the antenna port, which includes the front-end

loss.

Table 3-8. Bluetooth LE Transmitter Specifications

Parameter

Description

Min.

2402

-20

-150

-50

-20

225

185

0.8

-

Typ.

Max.

2480

10

Unit

MHz

dBm

kHz

Frequency Range

Output Power (*)

-

At max power output level

Frequency offset

Frequency drift

6

-

150

50

Carrier Frequency

Offset and Drift

-

kHz

Max. drift rate

-

20

Hz/us

kHz

△f1_avg

-

275

-

Modulation

Characteristic

△f2_max(For at least 99% of all △f2_max

△f2_avg/△f1_avg

)

-

kHz

0.94

-

Hz/Hz

dBm

±2M offset

-

-20

-30

In-band

Spurious Emission

>±3MHz offset

-

Note 1: The output power is measured at the antenna port.

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4

Electrical Characteristics

4.1

Absolute Maximum Rating

Table 4-1 Absolute Maximum Rating

Symbol

Parameters

Maximum rating

Unit

VDD33

T_STG

3.3V Supply Voltage

Storage Temperature

ESD protection (HBM)

-0.3 to 3.63

-40 to +125

2000

V

°C

V

VESD

4.2

Recommended Operating Range

Table 4-2. Recommended Operating Range

Symbol

Supply Voltage

Source

Min

2.97

1.6

Typ Max Unit

AVDD45 AVDD45_BUCK, AVDD45_MISC

To be connected to external 3.3V supply

To be connected to external supply

3.3 3.63

3.63

V

RTC_3V3 RTC_3V3

AVDD33

AVDD33_WF0_A_PA,

AVDD33_WF0_G_PA,

AVDD33_WF0_A_TX,

AVDD33_WF0_G_TX, AVDD33_BT To be connected to external 3.3V supply

2.97

3.3 3.63

V

DVDDIO

DVDDIO_D, DVDDIO_L,

DVDDIO_R

AVDD25 AVDD25_AUXADC

To be connected to PMU_DIO33_OUT

To be connected to PMU ALDO output

To be connected to PMU BUCK output

2.3

1.6

2.5

1.7

2.7

1.8

AVDD16

AVDD16_CLDO, AVDD16_BT,

AVDD16_XO, AVDD16_WF0_AFE

V

C

DVDD11 DVDD11

To be connected to PMU CLDO output

MT7697DN

0.86 1.15 1.3

Ta

Operating Ambient Temperature

-30

-40

-30

-40

85

MT7697IDN

Tj

Operating Junction Temperature

MT7697DN

125

MT7697IDN

4.3

DC Characteristics

Table 4-3. DC Characteristics

Symbol Parameter

Conditions

MIN

MAX

Unit

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Symbol Parameter

Conditions

MIN

-0.28

2

MAX

0.8

Unit

V

V_IL

Input Low Voltage

LVTTL

V_IH

Input High Voltage

3.63

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

|I_OL| = 4~16 mA

|I_OH| = 4~16 mA

-0.28

2.4

0.4

V

VDD33+0.33

R_PU

R_PD

Input Pull-Up Resistance

PU=high, PD=low 40

PU=low, PD=high 40

190

KΩ

Input Pull-Down Resistance

4.4

XTAL Oscillator

The table below lists the XTAL requirements for the XTAL.

Table 4-4. XTAL Oscillator Requirements

Parameter Value

Frequency 26, 40, 52MHz.

Frequency stability

Aging

±10 ppm @ 25℃

±3 ppm/year

4.5

PMU Characteristics

Table 4-5. PMU Electrical Characteristics

Parameter

Switching regulator (BUCK)

Reference

Conditions

Min

Typ

Max

Unit

Vin

Vout

Input Voltage

Output Voltage

AVDD45_BUCK

LXBK

2.97

1.6

3.3

1.7

3.63

1.8

V

Switching operation

Deep Sleep mode, SLDO-H

enabled

1.8

V

Iout

Output Current

Switching operation

Deep Sleep mode, SLDO-H

enabled

800

mA

10

4000

mA

Over-current shutdown

960

1600

.

Quiescent

Current

Iq

DC/DC

Iload < 1mA

150

85

uA

%

Line Regulation

Load regulation

Efficiency

Iload = 0mA

1

Iload = 200-400mA

Vin = 3.3V, Iload = 400mA

0.05

mV/mA

%

80

Core LDO (CLDO)

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Parameter

Reference

Conditions

Min

1.6

Typ

1.7

Max

1.8

Unit

V

Vin

Vout

Input

Output Voltage

AVDD16_CLDO

AVDD12_VCORE

Normal operation

Deep Sleep mode, SLDO-L

enabled

0.86

1.15

1.3

V

0.85

V

Iout

Output Current

Normal operation

Deep Sleep mode, SLDO-L

enabled

420

10

mA

uA

Quiescent

Current

Iq

40

50

Analog LDO (ALDO)

Vin

Input Voltage

2.97

2.3

3.3

3.63

2.7

V

Vout

Output Voltage

AVDD25_ALDO

Normal operation

Deep Sleep mode, OFF

Normal operation

2.5

0

V

Iout

Iq

Output Current

Quiescent

Current

50

mA

25

uA

V

PMU

Vin

Input Voltage

2.97

3.3

3.63

50

AVDD45, AVDD33

and DVDDIO

Quiescent

Current

Iq

In Deep Sleep State

uA

4.6

Auxiliary ADC Characteristics

This section specifies the electrical characteristics of the auxiliary ADC.

Table 4-6. Auxiliary ADC Specifications

Symbol

N

Parameter

Min

Typical Max

Unit

Resolution

-

12

2

-

Bit

MSPS

V

FS

Sampling Rate @ N-Bit⁽¹⁾

Input Swing⁽²⁾

Input voltage⁽³⁾

-

VPP

VIN

-

1.8

0

-

V

Input Impedance:

Unselected channel

Selected channel

RIN

400M

-

Ohm

10K

Differential Nonlinearity without dithering and

averaging

DNL

INL

-

± 1

± 2

± 4

LSB

Integral Nonlinearity without dithering and averaging -

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Symbol

Parameter

Min

Typical Max

Unit

Differential Nonlinearity with dithering and

averaging

DNL_{dither+average}

-

± 0.5

± 1

LSB

INL_{dither+average}

Integral Nonlinearity with dithering and averaging

Offset Error

-

± 2

± 10

± 50

66

LSB

mV

dB

OE

-

FSE

SNR

Full Swing Error

-

Signal to Noise Ratio⁽²⁾

Current Consumption

Power-Down Current

60

-

63

-

400

1

μA

-

μA

Note 1: Given that FS=2MHz

Note 2: At 1K Hz Input Frequency

Note 3: 1.77V when dithering is on.

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4.7

Thermal Characteristics

Θ_JCassumes that all the heat is dissipated through the top of the package, while Ψ_Jtassumes that the

heat is dissipated through the top, sides, and the bottom of the package. Thus it is suggested to use

Ψ_Jtto estimate the junction temperature.

Table 4-7. Thermal Characteristics

Performance

Symbol Description

Typical

125

Unit

°C

T_J

Maximum Junction Temperature (Plastic Package)

Junction to ambient temperature thermal resistance^[1]

Junction to case temperature thermal resistance

Junction to the package thermal resistance^[2]

Θ_JA

Θ_JC

Ψ_Jt

19.21

7.33

°C/W

1.65

Note 1: JEDEC 51-7 system FR4 PCB size: 76.2mm x 114.3mm

Note 2: 8mm x 8mm QFN-68 package

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5

Package Specifications

5.1

Pin Layout

MT7697D uses 8mm x 8mm QFN package of 68-pin with 0.4mm pitch.

Table 5-1. Pin Map

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

1

2

AVDD33_WF0_A_PA

AVDD16_WF0_AFE

AVDD16_XO

XO

SYSRST_B

GPIO39

51

50

49

48

47

46

45

44

3

DVDD11

DVDDIO_L

GPIO57

4

5

GPIO0

6

GPIO1

GPIO58

7

GPIO2

GPIO59

8

GPIO3

GPIO60

9

GPIO4

VSS

AVDD25_AUXADC 43

AVSS25_AUXADC 42

AVSS45_BUCK 41

10

11

12

13

14

15

16

17

GPIO5

GPIO6

GPIO7

LXBK

40

DVDDIO_R

DVDD11

GPIO24

AVDD45_BUCK 39

AVDD15_V2P5NA 38

AVDD16_CLDO 37

AVDD12_VCORE 36

DVDDIO_D

DVDD11

PMU_TEST

35

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Page 73 of 84

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697D

Internet-of-Things Wireless Connectivity

5.2

Pin Description

The section describes the pin functionality of MT7697D chip.

Table 5-2. Pin Descriptions

QFN Pin Name

Reset and Clocks

Pin description

PU/PD I/O

Supply domain

51

4

SYSRST_B

XO

External system reset active low

Crystal input or external clock input

RF 1.6V power supply

PU

Input

DVDDIO

N/A

Input

AVDD16_XO

3

AVDD16_XO

Power

Programmable I/O

5

6

7

8

GPIO0

GPIO1

GPIO2

GPIO3

Programmable input/output

PU/PD In/out DVDDIO

9

GPIO4

Programmable input/output

PU/PD In/out DVDDIO

10

11

12

15

18

19

26

28

29

27

25

24

57

56

55

GPIO5

GPIO6

GPIO7

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

GPIO35

Page 74 of 84

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697D

Internet-of-Things Wireless Connectivity

QFN Pin Name

Pin description

PU/PD I/O

Supply domain

54

53

52

50

47

46

45

GPIO36

GPIO37

GPIO38

GPIO39

GPIO57

GPIO58

GPIO59

GPIO60

Programmable input/output

PU/PD In/out DVDDIO

44

RTC

20

21

22

23

Power

N/A

VRTC

RTC domain power supply

32KHz crystal

Analog VRTC

N/A

RTC_32K_XO

RTC_32K_XI

PMU_EN_RTC

Analog VRTC

N/A

32KHz crystal

Output VRTC

N/A

PMU enable

WIFI Radio Interface

1

AVDD33_WF0_A_PA

RF 3.3v power supply

N/A

Power

62

67

65

2

AVDD33_WF0_G_PA

AVDD33_WF0_A_TX

AVDD33_WF0_G_TX

AVDD16_WF0_AFE

WF0_A_RFIO

RF 3.3v power supply

RF 1.6v power supply

RF a-band RF port

Power

Input

68

66

61

64

63

AVDD33_WF0_A

AVDD33_WF0_G

Input

In/out

WF0_RXA_AUX_IN

WF0_RXG_AUX_IN

WF0_G_RFIOP

RF a-band auxiliary RF LNA port

RF g-band auxiliary RF LNA port

RF g-band RF port

WF0_G_RFION

RF g-band RF port

In/out AVDD33_WF0_G

Bluetooth Radio Interface

59

60

58

AVDD33_BT

AVDD16_BT

BT_RFIO

RF 3.3v power supply

RF 1.6v power supply

RF Bluetooth port

N/A

Power

In/out AVDD33_BT

PMU/BUCK

BUCK ground

BUCK output

41

40

AVSS45_BUCK

LXBK

N/A

Ground

Output

Page 75 of 84

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697D

Internet-of-Things Wireless Connectivity

QFN Pin Name

Pin description

PU/PD I/O

Supply domain

39

38

37

36

34

31

AVDD45_BUCK

BUCK power supply

BUCK internal circuit output cap

CLDO supply

N/A

Input

AVDD15_V2P5NA

AVDD16_CLDO

Output

Input

AVDD12_VCORE

AVDD45_MISC

CLDO output

Output

Input

PMU supply

AVDD25_ALDO_OUT

2.5V ALDO output with external cap.

Output

This pin output is to provide 3.3V for all

DVDDIO.

30

PMU_DIO33_OUT

N/A

Output

And in OFF mode, this pin is 0V.

35

33

32

PMU_TEST

PMU test pin

N/A

Output

Input

Input 0V for non-RTC platform.

Input 3.3V for RTC platform.

ISO_INT_PMU_EN

PMU_EN_WF

External PMU enable

Input

Power Supplies

43

42

13

16

48

AVDD25_AUXADC

AVSS25_AUXADC

DVDDIO_R

Auxiliary ADC 2.5v power supply

Auxiliary ADC ground

N/A

Power

Ground

Power

Ground

Digital 3.3V input

Digital 1.15V input

Common Ground

DVDDIO_D

DVDDIO_L

14, 17, 30, 49 DVDD11

E-PAD VSS

5.3

Pin Multiplexing

The pin multiplexing could be controlled via the configuration register A (in TOP_AON domain) and

the configuration register B (in TOP_OFF/N9 domain). When configuration register A is set to 0, the

configuration register B determines the pin function. When configuration register A is not set to 0,

the configuration register A determines the pin function.

The default function of each pin is highlighted with blue background.

The driving strength of all pins is programmable: 4mA, 8mA, 12mA, and 16mA. The default setting

for all pins are 4mA.

Page 76 of 84

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697D

Internet-of-Things Wireless Connectivity

Table 5-3. Pin Multiplexing

Pinx_pinmux_aon_sel

Pinx_pinmux_off_sel

APGIO/

GPIO

Default

dir

Default

Pin alias

Name

Dir

Description

PU/PD

Address

Value

MCU_JTCK

ANTSEL[0]

I

O

I/O

O

I/O

I

PD

N9 JTAG debug port

RF control

0

-

0

1

3

5

-

UART0_RTS_CM4

GPIO_TOPOFF[0]

GPIO_TOPAON[0]

PWM[0]

UART0 RTS (CM4)

General purpose input output

Pulse-width-modulated output

External interrupt

7

-

0x8002_5100[3:0]

5

GPIO0

AGPIO

0x8102_3020[3:0]

(0x8102_3020[3:0]=0)

8

9

3

0

-

EINT[0]

-

MCU_JTMS

I

N9 JTAG debug port

RF control

0

1

3

5

-

ANTSEL[1]

O

I

UART0_CTS_CM4

GPIO_TOPOFF[1]

GPIO_TOPAON[1]

PWM[1]

UART0 CTS (CM4)

General purpose input output

Pulse-width-modulated output

External interrupt

7

-

0x8002_5100[7:4]

6

GPIO1

AGPIO

I/O

O

I

0x8102_3020[7:4]

(0x8102_3020[7:4]=0)

8

9

3

0

-

EINT[1]

-

MCU_JTDI

I

N9 JTAG debug port

RF control

0

1

2

3

4

5

-

ANTSEL[2]

O

I/O

I

MCU_AICE_TMSC

UART0_RX_CM4

SWD_CLK

N9 debug

-

UART0 RX (CM4)

7

4

-

0x8002_5100[11:8]

7

GPIO2

AGPIO

O

I/O

O

I

CM4 SWD debug port

General purpose input output

Pulse-width-modulated output

External interrupt

0x8102_3020[11:8]

(0x8102_3020[11:8]=0)

GPIO_TOPOFF[2]

GPIO_TOPAON[2]

PWM[23]

8

9

3

0

-

WIC[0]

-

MCU_JTRST_B

ANTSEL[3]

I

PD

N9 JTAG debug port

RF control

0

1

2

3

4

5

-

O

I

[Reserved]

-

UART0_TX_CM4

SWD_DIO

O

I/O

O

I

UART0 TX (CM4)

7

4

-

CM4 SWD debug port

General purpose input output

Pulse-width-modulated output

External interrupt

0x8002_5100[15:12]

8

GPIO3

AGPIO

0x8102_3020[15:12]

(0x8102_3020[15:12]=0)

GPIO_TOPOFF[3]

GPIO_TOPAON[3]

PWM[24]

8

9

3

2

0

-

EINT[2]

-

PULSE_CNT

MCU_DBGIN

ANTSEL[4]

I

Pulse counter

-

I

PD

N9 JTAG debug port

RF control

0

1

-

O

I

MCU_AICE_TCKC

SPI_DATA0_EXT *

GPIO_TOPOFF[4]

GPIO_TOPAON[4]

PWM[2]

N9 debug

-

I/O

O

I

External flash interface

General purpose input output

Pulse-width-modulated output

External interrupt

7

-

3

5

-

0x8002_5100[19:16]

9

GPIO4

GPIO

0x8102_3020[19:16]

(0x8102_3020[19:16]=0)

8

9

3

-

EINT[3]

-

O(Lo

w)

[Debug flag]

O

Debug monitor pin

0

ANTSEL[5]

SPI_DATA1_EXT *

GPIO_TOPOFF[5]

GPIO_TOPAON[5]

PWM[3]

O

RF control

-

1

3

5

-

External flash interface

General purpose input output

Pulse-width-modulated output

External interrupt

7

-

0x8002_5100[23:20]

10

GPIO5

GPIO

0x8102_3020[23:20]

I/O

O

I

(0x8102_3020[23:20]=0)

8

9

3

-

EINT[4]

I

-

Page 77 of 84

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697D

Internet-of-Things Wireless Connectivity

APGIO/

GPIO

Default

dir

Default

PU/PD

Pin alias

Name

Dir

Description

Pinx_pinmux_aon_sel

Pinx_pinmux_off_sel

MCU_DBGACKN

ANTSEL[6]

O

N9 JTAG debug port

RF control

0

-

0

1

3

5

-

SPI_CS_1_M_CM4

GPIO_TOPOFF[6]

GPIO_TOPAON[6]

PWM[4]

O

SPI master chip select 1

General purpose input output

Pulse-width-modulated output

External interrupt

7

-

0x8002_5100[27:24]

11

GPIO6

GPIO

I/O

O

0x8102_3020[27:24]

(0x8102_3020[27:24]=0)

8

9

3

-

EINT[5]

I

-

O(Lo

w)

MCU_JTDO

O

N9 JTAG debug port

0

ANTSEL[7]

SPI_CS_0_M_CM4

SPI_CS_EXT *

GPIO_TOPOFF[7]

GPIO_TOPAON[7]

PWM[5]

O

RF control

SPI master chip select 0

External flash interface

General purpose input output

Pulse-width-modulated output

External interrupt

-

1

2

3

5

-

6

7

-

0x8002_5100[31:28]

O

12

GPIO7

GPIO

0x8102_3020[31:28]

(0x8102_3020[31:28]=0)

I/O

8

9

3

-

O

I

-

EINT[6]

-

[Reserved]

0

1

2

3

4

5

-

UART_DSN_TXD_N9

SPI_MOSI_M_CM4

SPI_DATA2_EXT *

I2C1_CLK

O

UART_DSN TX (N9)

SPI master MOSI

-

6

7

4

-

I/O

O

External flash interface

I2C1 CLK

0x8002_510C[3:0]

15

GPIO24

GPIO

0x8102_302C[3:0]

(0x8102_302C[2:0]=0)

GPIO_TOPOFF[24]

GPIO_TOPAON[24]

PWM[25]

General purpose input output

Pulse width modulation

[Reserved]

8

9

1

2

-

[Reserved]

I

PU

-

[Reserved]

O

[Reserved]

-

[Reserved]

0

2

3

4

5

-

SPI_MISO_M_CM4

SPI_DATA3_EXT *

I2C1_DATA

I

SPI master MISO

-

I/O

O

External flash interface

I2C1 DATA

7

4

-

GPIO_TOPOFF[25]

GPIO_TOPAON[25]

PWM[26]

General purpose input output

Pulse width modulation

Default: Low.

0x8002_510C[7:4]

18

GPIO25

GPIO

0x8102_302C[7:4]

(0x8102_302C[7:4]=0)

8

9

1

2

3

-

[Reserved]

I/O

I

O

PU

-

FRAME_SYNC *

WIC[1]

3DD synchronization

External interrupt

-

I

-

[Reserved]

0

2

3

4

5

-

SPI_SCK_M_CM4

SPI_CLK_EXT *

I2S_TX

O

SPI master SCK

6

7

4

-

External flash interface

I2S TX

O

0x8002_510C[11:8]

19

GPIO26

GPIO

0x8102_302C[11:8]

(0x8102_302C[11:8]=0)

GPIO_TOPOFF[26]

GPIO_TOPAON[26]

PWM[27]

I/O

O

General purpose input output

Pulse width modulation

Default: Low.

8

9

1

5

4

-

[Reserved]

I/O

O

PU

-

SWD_DIO

CM4 SWD debug port

I2C0 CLK

1

3

5

-

I2C0_CLK

GPIO_TOPOFF[27]

GPIO_TOPAON[27]

PWM[28]

I/O

O

General purpose input output

Pulse width modulation

[Reserved]

8

9

1

2

3

5

-

0x8002_510C[15:12]

26

28

GPIO27

GPIO28

GPIO

0x8102_302C[15:12]

0x8102_302C[19:16]

(0x8102_302C[15:12]=0)

-

[Reserved]

I

-

PULSE_CNT

WIC[2]

I

Pulse counter input

External interrupt

-

I

-

SWD_CLK

I

CM4 SWD debug port

SPI

1

2

0x8002_510C[19:16]

(0x8102_302C[19:16]=0)

SPI_INT_S_N9

O

Page 78 of 84

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697D

Internet-of-Things Wireless Connectivity

APGIO/

GPIO

Default

dir

Default

PU/PD

Pin alias

Name

Dir

Description

Pinx_pinmux_aon_sel

Pinx_pinmux_off_sel

I2C0_DATA

GPIO_TOPOFF[28]

GPIO_TOPAON[28]

PWM[29]

O

I/O

O

I2C0 DATA

General purpose input output

Pulse width modulation

[Reserved]

4

0

8

9

1

-

3

5

-

[Reserved]

I/O

O

I

-

[Reserved]

0

1

2

3

4

5

-

SPI_MOSI_S_CM4

SPI_MOSI_S_N9

SPI_MOSI_M_CM4

I2S_MCLK

I

SPI slave MOSI (CM4)

SPI slave MOSI (N9)

SPI master MOSI

6

-

I

O

7

4

-

O

I2S MCLK master

0x8002_510C[23:20]

29

GPIO29

GPIO

GPIO_TOPOFF[29]

GPIO_TOPAON[29]

PWM[30]

I/O

O

General purpose input output

Pulse width modulation

[Reserved]

0x8102_302C[23:20]

(0x8102_302C[23:20]=0)

8

9

1

2

3

5

6

0

7

4

0

8

9

1

2

5

6

-

[Reserved]

I/O

O

I

-

HOST_ACK

-

WIC[3]

I

External interrupt

[Reserved]

-

[Reserved]

O

0

1

2

3

4

5

-

SPI_MISO_S_CM4

SPI_MISO_S_N9

SPI_MISO_M_CM4

I2S_FS

O

SPI slave MISO (CM4)

SPI slave MISO (N9)

SPI master MISO

O

I

I2S slave FS

0x8002_5108[27:24]

27

GPIO30

GPIO

0x8102_302C[27:24]

(0x8102_302C[27:24]=0)

GPIO_TOPOFF[30]

GPIO_TOPAON[30]

PWM[31]

I/O

O

General purpose input output

Pulse width modulation

[Reserved]

-

[Reserved]

I/O

I

-

HOST_EINT_B

I2S_TX

-

O

I2S TX

SPI slave SCK (CM4)

SPI slave SCK (N9)

SPI master SCK

0

1

2

3

4

5

-

SPI_SCK_S_CM4

SPI_SCK_S_N9

SPI_SCK_M

I

O

7

4

-

0x8002_510C[31:28]

25

GPIO31

GPIO

I2S_RX

I

I2S slave RX

0x8102_302C[31:28]

(0x8102_302C[31:28]=0)

GPIO_TOPOFF[31]

GPIO_TOPAON[31]

PWM[32]

I/O

O

General purpose input output

Pulse width modulation

[Reserved]

8

9

1

5

6

-

[Reserved]

I/O

O

I

-

[Reserved]

0

1

2

3

4

5

-

SPI_CS_0_S_CM4

SPI_CS_0_S_N9

SPI_CS_0_M

I2S_BCLK

I

SPI slave CS (CM4)

SPI slave CS (N9)

SPI master CS

I

O

7

4

-

I

I2S BCLK slave

0x8002_5110 [3:0]

24

GPIO32

GPIO

0x8102_3030[3:0]

(0x8102_3030[3:0]=0)

GPIO_TOPOFF[32]

GPIO_TOPAON[32]

PWM[33]

I/O

O

General purpose input output

Pulse width modulation

[Reserved]

8

9

1

3

0

-

[Reserved]

I/O

I

-

WIC[4]

External interrupt

-

WIFI_INT_B

I/O

O

PU

External interrupt

0

1

2

3

4

5

-

ALL_INT_B

External interrupt

SWD_DIO

CM4 SWD debug port

IrDA TX

6

7

4

-

IR_TX

0x8002_5110 [7:4]

57

GPIO33

AGPIO

0x8102_3030 [7:4]

(0x8102_3030 [7:4]=0)

ANTSEL[5]

O

RF control

GPIO_TOPOFF[33]

GPIO_TOPAON[33]

PWM[34]

I/O

O

General purpose input output

Pulse width modulation

8

9

-

Page 79 of 84

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

MT7697D

Internet-of-Things Wireless Connectivity

APGIO/

GPIO

Default

dir

Default

PU/PD

Pin alias

Name

Dir

Description

Pinx_pinmux_aon_sel

Pinx_pinmux_off_sel

PULSE_CNT

WF_LED_B

I

O

Pulse counter

LED output

1

2

3

0

-

WIC[5]

I

External interrupt

-

BT_INT_B

I/O

I

O

PU

0

1

2

3

4

5

-

ALL_INT_B

SWD_CLK

CM4 SWD debug port

IrDA RX

6

7

4

-

IR_RX

I

ANTSEL[6]

O

RF control

0x8002_5110 [11:8]

56

GPIO34

AGPIO

GPIO_TOPOFF[34]

GPIO_TOPAON[34]

PWM[35]

I/O

O

General purpose input output

Pulse width modulation

3DD synchronization

LED output

0x8102_3030 [11:8]

(0x8102_3030 [11:8]=0]

8

9

1

2

3

0

7

-

FRAME_SYNC *

BT_LED_B

I

-

I/O

I

-

WIC[6]

External interrupt

-

UART_DSN_TXD_N9

UART_DBG_CM4

GPIO_TOPOFF[35]

GPIO_TOPAON[35]

O

PD

UART DSN TX (N9)

UART DBG TX (CM4)

General purpose input output

0

3

5

-

O

I/O

0x8002_5110 [15:12]

55

GPIO35

GPIO

0x8102_3030 [15:12]

8

(0x8102_3030 [15:12]=0)

-

I2S_TX

PWM[18]

O

I2S TX

5

9

-

Pulse-width-modulated output

[Reserved]

-

0

1

3

5

-

[Reserved]

S2A_SPI_IN

I

SPI input

-

UART1_RX_CM4

GPIO_TOPOFF[36]

GPIO_TOPAON[36]

PWM[19]

UART1 RX (CM4)

7

-

I/O

O

I

General purpose input output

Pulse-width-modulated output

UART RX (N9)

0x8002_5110 [19:16]

54

GPIO36

GPIO

0x8102_3030 [19:16]

(0x8102_3030 [19:16]=0)

8

9

1

3

0

7

-

UART_RXD_N9

WIC[7]

I

PU

PD

-

I

External interrupt

-

UART_TXD_N9

UART1_TX_CM4

GPIO_TOPOFF[37]

GPIO_TOPAON]37]

PWM[20]

O

I/O

O

I

O

UART TX (N9)

0

3

5

-

UART1 TX (CM4)

General purpose input output

Pulse-width-modulated output

External interrupt

0x8002_5110 [23:20]

53

GPIO37

GPIO

0x8102_3030 [23:20]

(0x8102_3030 [23:20]=0)

8

9

3

0

-

EINT[20]

-

UART_RTS_N9

PTA_EINT_B

IDC_DATA_OUT

UART1_RTS_CM4

GPIO_TOPOFF[38]

GPIO_TOPAON[38]

PWM[21]

O

I

O

PD

UART RTS (N9)

0

1

2

3

5

-

Packet traffic arbitration

UART IDC TX (N9)

O

I/O

O

I/O

I

-

UART1 RTS (CM4)

7

-

General purpose input output

Pulse-width-modulated output

LED output

0x8002_5110 [27:24]

52

GPIO38

GPIO

0x8102_3030 [27:24]

(0x8102_3030 [26:24]=0)

8

9

2

3

6

0

-

WF_LED_B

-

EINT[21]

External interrupt

-

SWD_DIO

I/O

I

CM4 SWD debug port

UART CTS (N9)

-

UART_CTS_N9

PTA_EINT_B

IDC_DATA_IN

UART1_CTS_CM4

[Reserved]

I

PU

0

1

2

3

4

5

-

I

Packet traffic arbitration

UART IDC RX (N9)

I

-

O

UART1 CTS (CM4)

7

-

0x8002_5110[31:28]

50

GPIO39

GPIO

0x8102_3030 [31:28]

(0x8102_3030 [31:28]=0)

[Reserved]

GPIO_TOPOFF[39]

GPIO_TOPAON[39]

PWM[22]

I/O

O

General purpose input output

Pulse-width-modulated output

-

8

9

-

Page 80 of 84

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MT7697D

Internet-of-Things Wireless Connectivity

APGIO/

GPIO

Default

dir

Default

PU/PD

Pin alias

Name

Dir

Description

Pinx_pinmux_aon_sel

Pinx_pinmux_off_sel

PULSE_COUNT *

BT_LED_B

I

I/O

I

Pulse counter

LED output

1

2

3

6

-

EINT[22]

External interrupt

-

SWD_CLK

I

CM4 SWD debug port

PCM interface for Bluetooth

-

PCM_CLK

I/O

I

0

1

2

5

-

S2A_SPI_CK

MCU_AICE_TCKC

GPIO_TOPOFF[57]

GPIO_TOPAON[57]

PWM[36]

-

I

N9 debug

-

I/O

O

I

General purpose input output

Pulse-width-modulated output

[Reserved]

-

0x8002_511C [7:4]

0x8102_303C [7:4]

(0x8102_300C[6]=0)

47

46

45

44

GPIO57

GPIO58

GPIO59

GPIO60

AGPIO

8

9

1

3

1

-

(0x8102_303C [7:4]=0,

0x8102_300C[6]=0)

-

[Reserved]

I

PU

-

WIC[8]

I

External interrupt

-

ADC_IN0

I

Auxiliary ADC input

0x8102_300C[6]

-

PCM_SYNC

S2A_SPI_OUT

MCU_AICE_TMSC

GPIO_TOPOFF[58]

GPIO_TOPAON[58]

PWM[37]

I/O

O

I/O

O

I

PCM interface for Bluetooth

0

1

2

5

-

N9 debug

-

General purpose input output

Pulse-width-modulated output

[Reserved]

-

0x8102_303C[11:8]=0

(0x8102_300C[7]=0)

0x8002_511C [11:8]

8

9

1

3

1

-

(0x8102_303C[11:8]=0,

0x8102_300C[7]=0)

-

[Reserved]

I

PU

-

WIC[9]

I

External interrupt

-

ADC_IN1

I

Auxiliary ADC input

0x8102_300C[7]

-

PCM_OUT

O

I/O

O

I/O

I

PCM interface for Bluetooth

UART DSN TX (N9)

0

1

2

5

-

UART_DSN_TXD_N9

SWD_DIO

-

CM4 debug port

6

-

0x8002_511C [15:12]

GPIO_TOPOFF[59]

GPIO_TOPAON[59]

PWM[38]

General purpose input output

Pulse-width-modulated output

LED output

0x8102_303C [15:12]

(0x8102_300C[8]=0)

(0x8102_303C [15:12]=0,

0x8102_300C[8]=0)

8

9

1

3

1

-

WF_LED_B

-

WIC[10]

External interrupt

-

ADC_IN2

I

Auxiliary ADC input

0x8102_300C[8]

-

PCM_IN

I

PCM interface for Bluetooth

CM4 SWD debug port

General purpose input output

Pulse-width-modulated output

LED output

0

2

5

-

SWD_CLK

I

6

-

GPIO_TOPOFF[60]

GPIO_TOPAON[[60]

PWM[39]

I/O

O

I/O

I

0x8002_511C [19:16]

8

9

1

2

3

1

0x8102_303C [19:16]=0

(0x8102_300C[9]=0)

(0x8102_303C [19:16]=0,

0x8102_300C[9]=0)

-

BT_LED_B

-

PULSE_CNT

WIC[11]

Pulse counter input

-

I

External interrupt

-

ADC_IN3

I

Auxiliary ADC input

0x8102_300C[9]

-

Note: * not used in MT7697D

5.4

Bootstrap

The section describes the bootstrap function.

The chip modes are sensed from the device pin during power up. After chip reset, the pull

configuration are stored in a register and determine the device operation mode.

Page 81 of 84

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MT7697D

Internet-of-Things Wireless Connectivity

Table 5-4. Bootstrap Option– Flash Access Mode

Flash Access Mode

Normal mode

PIN53 (GPIO37)

Pull-down⁽¹⁾

Pull-up

Description

Firmware jumps to flash.

Recovery mode

Firmware does not jump to flash and wait for UART

command.

This mode is used for the firmware to jump to SYSRAM

after downloading code from UART.

Note 1: No external pull-down resistor is required because internal pull-down is active during power

up.

Table 5-5. Bootstrap Option – XTAL Clock Mode

XTAL Clock Mode

40MHz

PIN12 (GPIO7)

Pull-down

Pull-up

PIN52 (GPIO38)

Pull-up

Description

Uses 40MHz XTAL.

Uses 26MHz XTAL.

Uses 52MHz XTAL.

26MHz

Pull-down⁽¹⁾

52MHz

Pull-up

Note 1: No external pull-down resistor is required because internal pull-down is active during power

up.

Table 5-6. Bootstrap Option – 32KHz Clock Mode

32KHz clock mode

Internal 32KHz clock

External 32KHz clock

PIN11 (GPIO6)

Pull-down

Pull-up

Description

32KHz clock sources from 40/26/52MHz clock.

32KHz clock sources from external pin.

Table 5-7. Bootstrap Option — Chip Mode

Chip mode

PIN55

(GPIO35)

PIN10

(GPIO5)

PIN11

(GPIO6)

PIN12

(GPIO7)

PIN52

(GPIO38)

Description

Normal mode

Test mode

Pull-

Don’t care

32KHz clock

mode

control

XTAL clock mode control

Chip operates in normal

mode.

down⁽¹⁾

Pull-up

Chip operates in test

mode.

Note 1: No external pull-down resistor is required because internal pull-down is active during power

up.

Note 2: When in test mode, the XTAL input clock is 26MHz only.

Page 82 of 84

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MT7697D

Internet-of-Things Wireless Connectivity

Pins 10, 11, 12, 52, 53, and 55 are is used for bootstrap. The system design should follow the

following guideline:

.

Those pins shall not be used as input functions because the signals from another device

might affect the values sensed.

.

Those pins shall not be used as an open-drain function because the pull-up resistor

would affect the values sensed.

5.5

Package information

Figure 5-1. Package Outline Drawing

5.6

Ordering information

Table 5-8. Ordering Information

Page 83 of 84

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MT7697D

Internet-of-Things Wireless Connectivity

Part number

MT7697DN

MT7697DIN

Package

Operational temperature range

-30~85°C

8mm x 8mm x 0.8 mm QFN68

-40~85°C

5.7

Top Marking

MEDIATEK

ARM

MT7697DN: Part number

DDDD

####

: Date code

: Internal control code

MT7697DN

DDDD-####

BBBBBBB

FFFFFFFF

BBBBBBB : Main die lot number

FFFFFFF : Flash die lot number

Figure 5-2. Top Marking

Page 84 of 84

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Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.


型号：	MT7697D
厂家：	ETC
描述：	Internet-of-Things Wireless Connectivity 无线
文件：	总84页 (文件大小：1965K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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