MTD505 [ETC]

5 Port 10M/100M Ethernet Switch; 5端口10M / 100M以太网交换机


型号：	MTD505
厂家：	ETC
描述：	5 Port 10M/100M Ethernet Switch 5端口10M / 100M以太网交换机以太网
文件：	总19页 (文件大小：204K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MYSON

MTD505

TECHNOLOGY

(Preliminary)

5 Port 10M/100M Ethernet Switch

FEATURES

GENERAL DESCRIPTION

•

IEEE802.3 and IEEE802.3u compliant.

Provide 4 RMII and 1 MII/RMII ports.

Programmable 1K/8K MAC addresses filtering. is a non-blocking 5 port 10M/100M Ethernet

Store and forward switching function and bad

packet filtering function.

The MTD505 complies fully with the

IEEE802.3, 802.3u and 802.3x specifications and

switch device.

Support 4 RMII and 1 MII/RMII ports for

•

Optional back_pressure/802.3x flow control/

flooding control/broadcast control.

Optional EEPROM Interface for advanced

switch configurations.

1MB/2MB SGRAM/SDRAM flexible memory

interface.

10M/100M operation. 1MByte/2MBytes memory

interface provides maximum 1365 packet buffers

for Ethernet packet buffering. Up to 8192 address

entrys are provided by the MTD505, and the

MTD505 use full Ethernet address compare algo-

rithm to minimize hashing collision events.

•

Port VLAN/trunking.

Link/Rx activity, packet buffer utilization LED

display.

The MTD505 provides EEPROM interface

to config port trunking, port VLAN, static entry,

802.3x flow control threshold, flooding port,

•

50MHz for non-blocking for 5 ports switch oper- broadcast control threshold. Each MTD505 port

ation

support 10/100M auto-negotiation by MDC/MDIO

interface for connecting external PHY devices.

The MTD505 also provides 10 pins for

Link/RX activity, packet buffer utilization LED dis-

play function.

•

Build in internal/external memory test function.

128 pin PQFP package, 3.3V operation volt-

age.

BLOCK DIAGRAM

SDRAM/

SGRAM

Interface

Memory

Controller

RMII0

DMA0

MAC0

RMII1

RMII2

RMII3

DMA1

DMA2

DMA3

MAC1

MAC2

MAC3

Memory

Arbiter

RMII/MII4

DMA4

MAC4

Port

Switch

Logic

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification

without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of

the product.

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SYSTEM DIAGRAM

(**OPTION)

EEPROM

(**Programmable)

SGRAM

(256k32x1)

SGRAM

(512k32x1)

MTD505

LEDs

SGRAM

(256k32x2)

MII4

RMII0-3

QUAD

Single

PHYsceiver

MII management

QUAD

Single

Transformer

RJ45

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification

without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of

the product

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(Preliminary)

1.0 PIN CONNECTION

LEDDATA4

LEDDATA3

LEDDATA2

LEDDATA1

LEDDATA0

GNDI

64 VCCO

63 GNDO

62 AD5

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

61 AD6

60 AD7

59 AD8

CLK25M

VCCI

58 VCCI

57 MEMCLK

56 GNDI

55 DQ8

SDC

SDIO

EECLK

54 DQ9

EEDATA

RESETB

REFCLK

MDIO

53 DQ10

52 DQ11

51 DQ12

50 DQ13

49 DQ14

48 DQ15

47 DQ24

46 DQ25

45 DQ26

44 VCCO

43 GNDO

42 DQ27

41 DQ28

40 DQ29

39 DQ30

MTD505

MDC

CRSDV0

TXD0_1

TXD0_0

TXEN0

RXD0_0

RXD0_1

CRSDV1

TXD1_1

TXD1_0

TXEN1

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2.0 PIN DESCRIPTIONS

RMII/MII Port Interface Pins

Descriptions

Name

CRSDV0

Pin Number I/O

Port0 RMII receive interface signal, CRSDV0 is asserted high when

port0 media is non_idle.

119

RXD0_0

RXD0_1

TXEN0

Port0 RMII receive data bit_0.

Port0 RMII receive data bit_1.

Port0 RMII transmit enable signal.

Port0 RMII transmit data bit_0.

Port0 RMII transmit data bit_1.

123

124

122

TXD0_0

TXD0_1

CRSDV1

121

120

Port1 RMII receive interface signal, CRSDV1 is asserted high when

port1 media is non_idle.

125

RXD1_0

RXD1_1

TXEN1

Port1 RMII receive data bit_0.

Port1 RMII receive data bit_1.

Port1 RMII transmit enable signal.

Port1 RMII transmit data bit_0.

Port1 RMII transmit data bit_1.

128

TXD1_0

TXD1_1

CRSDV2

127

126

Port2 RMII receive interface signal, CRSDV2 is asserted high when

port2 media is non_idle.

RXD2_0

RXD2_1

TXEN2

Port2 RMII receive data bit_0.

Port2 RMII receive data bit_1.

Port2 RMII transmit enable signal.

Port2 RMII transmit data bit_0.

Port2 RMII transmit data bit_1.

TXD2_0

TXD2_1

CRSDV3

Port3 RMII receive interface signal, CRSDV0 is asserted high when

port3 media is non_idle.

RXD3_0

RXD3_1

TXEN3

Port3 RMII receive data bit_0.

Port3 RMII receive data bit_1.

Port3 RMII transmit enable signal.

Port3 RMII transmit data bit_0.

TXD3_0

TXD3_1

CRSDV4

Port3 RMII transmit data bit_1.

Port4 RMII/MII receive interface signal, CRSDV4 is asserted high when

port4 media is non_idle.

RXDV4

Port4 MII receive data valid.

In RMII mode, this pin don’t use.

RXCLK4

Port4 MII receive clock signal.

In RMII mode, this pin is not used.

Port4 MII receive data bit_3. In RMII mode, this pin don’t use.

Port4 MII receive data bit_2. In RMII mode, this pin don’t use.

Port4 RMII/MII receive data bit_0.

Port4 RMII/MII receive data bit_1.

Port4 RMII transmit enable signal.

Port4 RMII transmit clock signal.

RXD4_3

RXD4_2

RXD4_0

RXD4_1

TXEN4

TXCLK4

In RMII mode, this pin is not used.

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RMII/MII Port Interface Pins

Descriptions

Name

TXD4_3

Pin Number I/O

Port4 MII transmit data bit_3. In RMII mode, this pin don’t use.

Port4 MII transmit data bit_2. In RMII mode, this pin don’t use.

Port4 RMII/MII transmit data bit_0.

TXD4_2

TXD4_0

TXD4_1

COL4

Port4 RMII/MII transmit data bit_1.

Port4 MII collision input.

In RMII mode, this pin don’t use.

CLK25M

Port4 MII 25MHz clock output.

109

SGRAM/SDRAM Interface Pins

Name

Pin Number I/O

Descriptions

AD[8:0]

Memory row/column address bus outputs

59,60,61,62,

65,66,67,68,

AD[7:0] are row/column address [7:0].

AD[8] : This pin should connect to SGRAM/SDRAM MSB address bit.

DQ[31:0]

38~42,45~55 I/O Memory data bus

,78~80,

83~95

RASB

CASB

WEB

SGRAM/SDRAM row address select

SGRAM/SDRAM column address select

SGRAM/SDRAM write enable

SGRAM/SDRAM bank select

Memory chip select 0

CS0B

CS1B

MEMCLK

Memory chip select 1

Memory clock output.

Note: SGRAM/SDRAM access time: 10 ns (max)

LED Interface Pins

Name

Pin Number I/O

Descriptions

LEDDATA

I/O LED data output.

[7:0]

These LED pins report Port0~7 Link/Rx activity status using

LEDCLK1 strobe , and report packet buffer utilization status using

LEDCLK2 strobe.

LEDDATA [0] [1] [2] [3] [4] [5] [6] [7]

LEDCLK1 LR0 LR1 LR2 LR3 LR4 --- --- ---

LEDCLK2 Uti0 Uti1 Uti2 Uti3 Uti4 --- BFull MFail

note:

100,101,102,

103,104,105,

106,107

LRn: means per port’s Link_RxAct status.

Uti0: 5%, Uti1: 10%, Uti2: 20%, Uti3: 35%, Uti4: 50 above .

BFull: Buffer almost full alarm signal.

Mfail: External memory poer on test failure.

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LED Interface Pins

Name

LEDCLK1

LEDCLK2

Pin Number I/O

Descriptions

I/O LED strobe 1

I/O LED strobe 2

Miscellaneous Pins

Name

RESETB

SYSCLK

Pin Number I/O

Descriptions

115

System reset input, low active.

Switch core system clock input, using the same clock source with REF-

CLK.

REFCLK

MDC

116

118

117

111

112

114

113

RMII reference clock input, using 50Mhz.

I/O MII management clock inout

I/O MII management data inout

I/O MII register clock inout

I/O MII register data inout

I/O EEPROM data input

MDIO

SDC

SDIO

EEDATA

EECLK

VCC

I/O EEPROM clock output

08,28,34,37, PWR Power pins

44,58,64,72,

82,99,110

GND

02,27,33,35, GND Ground pins

43,56,63,71,

81,98,108

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Jummper Configuration After Power On Reset

Pin Number I/O Descriptions

Name

LEDDATA[0]

I/O During power on reset duration, these pins are jumper setting pins

(pull_hgih = 1, pull_low = 0).

LEDDATA[1]

LEDDATA[2]

LEDDATA[3]

LEDDATA[4]

LEDDATA[5]

LEDDATA[6]

LEDDATA[7]

LEDDATA[0] : select SGRAM/SDRAM interface ,

“1” means 256K32 x 1 or 512K32 x 1 is selected.

“0” means 256K32 x 2 is selected, default is “1”.

LEDDATA[1] : config packet buffer size,

“1” means 2 M bytes buffer size is selected.

“0” means 1 M byte buffer size is selected, default is “0”

LEDDATA[2] : enable memory test function,

“1” means enable.

‘0” means disable, default is “1”.

LEDDATA[3] : enable aging function,

“1” means enable.

“0” means disable, default is “1”.

LEDDATA[4] : enable MII polling(MDC/MDIO),

“1” means enable.

“0” means disable, default is “1”.

LEDDATA[5] : enable broadcast storm control,

“1” means enable.

“0” means disable, default is “1”.

LEDDATA[6] : enable backpressure function (in half mode),

“1” means enable.

“0” means disable, default is “1”.

LEDDATA[7] : enable 802.3x flow control function (in full mode) ,

“1” means enable.

“0” means disable, default is ”1”.

LEDCLK1

LEDCLK2

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

LEDCLK1 : select 1K or 8K address entry table,

“1” means 8K addres entry is selected.

“0” means 1K address entry is selected, default is “1”.

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

LEDCLK2 : enable EEPROM interface.

“1” means enable.

“0” means disable, default is “1”.

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Jummper Configuration After Power On Reset

Pin Number I/O Descriptions

Name

EEDATA

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

EEDATA : enable EEPROM auto_load configuration function while

EEPROM interface is enabled,

“1” means enable.

“0” means disable, default is “1”.

TXEN[2:0]

TXEN[3]

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

TXEN[2:0] : uplink port (flooding port) 0 ~7 selection; default is “000”.

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

TXEN[3] : enable flooding control,

“1” means enable.

“0” means disable, default is “0”.

TXEN[4]

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

TXEN[4] : enable VLAN tag 1522 bytes receiving,

“1” means enable.

“0” means disable, default is “0”.

SDC

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

SDC : Port4 MII/RMII interface selection,

“1” means Port4 MII interface is selected.

“0” means Port4 RMII interface is selected, default is “0”.

EECLK

MDC

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

EECLK : scan mode enable for debugging purpose,

“1” means scan mode enable.

“0” means scan mode disable, default is “0”.

I/O During power on reset duration, this pin is a jumper setting pin

(pull_hgh =1, pull_low = 0).

MDC : fast mode enable for testing purpose,

“1” means fast mode enable.

“0” means fast mode disable, default is “0”.

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3.0 FUNCTIONAL DESCRIPTIONS

The MTD505 is an 5 ports 10/100 Mbps fast Ethernet switch controller. It is a low cost solution for eight

ports fast Ethernet SOHO switch design. No CPU interface is required; After power on reset, MTD505

provide an auto load configuration setting function through a 2 wire serial EEPROM interface to acess

external EEPROM device, and MTD505 can easily be configured to support port_trunking, port_ VLAN,

static entry, 802.3X flow control threshold setting , flooding port assignment ...etc functions. The follow-

ing descriptions are MTD505’s major functional blocks overview.

3.1 Packet store and forwarding

The MTD505 use simple store and forward algorithm as packet switching method. Input packet from

ports will be stored to external memory first, while packet is good for forward (CRC chech ok, 64Bytes <

length < 1518Bytes, not local packets, in the same VLAN group ) , if this packet’s DA hits, than forward

this packet to the destination port, otherwise this packet will be broadcasted.

3.2 Learning and Routing

The MTD505 supports 1K or 8K MAC entries for switching. Dynamic address learning is performed by

each good unicast packet is completely received. The static address learning is achieved by EEPROM

configuration. On the other hand, the routing process is performed whenever the packet’s DA is cap-

tured. If the DA can not get a hit result, the packet is going to switch broadcast or forward to the dedi-

cated port according to the flooding control selction.

3.3 Aging

Only the dynamic address entries are scheduled in the aging machine. If one station does not transmit

any packet for a period of time, the belonging MAC address will be kicked out from the address table.

The aging out time can be program through the EEPROM auto load configuration. (Default value is 300

seconds)

3.4 Buffer Queue Management

The buffer queue manager is implemented to manage the external shared memory (use SDRAM/

SGRAM) for packet buffering. The main function of the buffer queue manager is to maintain the linked

list consists of buffer IDs, which is used to show the corresponding memory address for each incoming

packet. In addition, the buffer queue manager monitors the rested free spaces status of the external

memory, If the packet storage achieve the predefined threshold value, the buffer queue manager will

raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission ID

queue overflow happening. MTD505 provide 802.3x flow control in full duplex mode and back pressure

control in half duplex mode.

3.5 Full Duplex 802.3x Flow Control

In full duplex mode, MTD505 supports the standard flow control defined in IEEE802.3x standard. It

enables the stopping of remote node transmissions via a PAUSE frame information interactoin. When

the “802.3x flow control enable” bit is set during power on reset (LEDDATA[7] pin is external pull_high),

it enables MTD505 supporting 802.3x flow control function in full_duplex mode; When output port buffer

queue’s on_using value reach the initialization setting threshold value (recommended Xon_TH = 74’h

when using 2Mbytes external memory; Xon_TH = 2e’h when using 1Mbytes external memory),

MTD505 will send out a PAUSE packet with pause time equal to FFF to stop the remote node transmis-

sion; When the output port buffer queue’s on_using value reduce to the initialization threshold

value(recommended Xoff_TH = 30’h when using 2Mbytes external memory; Xoff_TH=18’h when using

1Mbytes external memory), MTD505 will also send a PAUSE packet with pause time equal to zero to

inform the remote node to retransmit packet.

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3.6 Half Duplex Back Pressure Control

In half duplex mode, MTD505 provide a back pressure control mechanism to avoid dropping packets

during network conjection situation. When the “back pressure control enable” bit is set during power on

reset (LEDDATA[6] pin is external pull_high), it enables MTD505 supporting back pressure function in

half_duplex mode; When output port buffer queue’s on_using value reach the initialization setting

threshold value (same with the Xon_TH value), MTD505 will send a JAM pattern in the input port when

it senses an incoming packet , thus force a collision to inform the remote node transmission back

off and will effectively avoid dropping packets. If the “back pressure control enable” bit is not set, and

there is no free buffer queue available for the incoming packets, the incoming packets will be dropped.

3.7 MII Polling

The MTD505 supports PHY management through the serial MDIO/MDC interface. After power on

reset, the MTD505 write related abilities to the advertisement register 4 of connected PHY devices and

restart the auto_negotiation prcedure via MDIO/MDC interface using the predefined PHY addresses

increasingly from “01000”b to “01100”b. The MTD505 will periodically and continuously poll and update

the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow control

capable status of the connected PHY devices through MDIO/MDC serial interface.

3.8 MAC and DMA engine

The MTD505’s MAC performs all the functions in IEEE802.3 protocol, such as frame formatting, frame

stripping, CRC checking, bad packet dropping, defering to line traffic, and collision handling. The MAC

Rx_engine checks incoming packets and drops the bad packet which include CRC error, alignment

error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the

“VLAN tag 1522 bytes receive enable” bit is set during power on reset). Before transmission, The MAC

Tx_engine will constantly monitor the line traffic using derfering precedure. Only if it has been idle for a

96 bits time (a minimum interpacket gap time, IPG time), actual transmmission can be started. For the

half duplex mode, MAc engine will detect collision; if a collision is detected, the MAC Tx_engine will

transmit a JAM pattern and then delay the re_transmission for a random time period determined by the

back_off algorithm (MTD505 implements the truncated exponential back_off algorithm defined in IEEE

802.3 standard). For the full duplex mode, collision signal is ignored.

The MTD505’s DMA engine performs the packets non_blocking transportation between MAC engine

and external memory according to a high speed switching procedure. The switching procedure is com-

pleted by address learning/routing process and buffer queue management operation.

3.9 EEPROM interface

MTD505 provide an auto load configuration setting function through a 2 wire serial EEPROM interface

to acess external EEPROM device(24C02) after power on reset . MTD505 can easily be configured to

support port_trunking, port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port

assignment ...etc functions. The following table is the EEPROM contents mapping:

Recommended

EEPROM

Name

EEPROM Content Description

Value Under

Address

Basic Operation

EOB

Last EEPROM content address value

Aging Time bit [7:0]

8’h13

8’h2c

8’h01

8’hfe

8’hfd

8’hfb

8’hf7

8’hef

AgeLow

AgeHigh

VLAN0

VLAN1

VLAN2

VLAN3

VLAN4

Aging Time bit [15:8]

Port0 VLAN register

Port1 VLAN register

Port2 VLAN register

Port3 VLAN register

Port4 VLAN register

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Recommended

Value Under

Basic Operation

EEPROM

Address

Name

EEPROM Content Description

Reserved

reserved

8’hdf

8’hbf

8’h7f

bit[7:4] --- the flooding port_no of Port1

bit[3:0] --- the flooding port_no of Port0

*ex1: bit[7:4] = “0011”b, means that if the incomin

packet of Port1 got the “un_routed” result, then

this incoming packet will be flooded to Port3.

UpLink10

UpLink32

8’h0f

*ex2: bit[3:0] = “0111”b, means that if the incomin

packet of Port0 got the “un_routed” result, then

this incoming packet will be flooded to Port7.

(note: set value “4’hf”, means flooding to all the

other ports; set value “4’h8”~“4’he” is forbidden)

bit[7:4] --- the flooding port_no of Port3

bit[3:0] --- the flooding port_no of Port2

8’h00

(note: set value “4’hf”, means flooding to all the

other ports; set value “4’h8”~“4’he” is forbidden)

bit[7:4] --- reserved

bit[3:0] --- the flooding port_no of Port4

UpLink54

Reserved

(note: value setting “f”, means flooding to all the

other ports; value setting “8” ~ “e” is forbidden)

reserved

Broadcast threshold

Xon threshold

8’h00

8’hff

Broadcast TH 0f

Xon TH

Xoff TH

DisPort

8’h74

8’h30

8’h00

Xoff threshold

Disable Port

System control byte :

System Control 13

bit[0] --- enhanced back pressure enable,

8’h00

bit[7:1] --- reserved.

none

Reserved

StaticSA1

14 ~1f

Address 26 bit[2:0] --- means Port ID

20 ~26

27 ~ 2d

Address 25 bit[7:0] ~ Address 20 bit[7:0] ---

means static SA[47:0]

Address 2d bit[2:0] --- means Port ID

StaticSA2

Address 2c bit[7:0] ~ Address 27 bit[7:0] ---

means static SA[47:0]

3.10 Port Based VLAN

The MTD505 supports VLAN configuration by port based methodology. One port select the certain

ports to form its VLAN group by configuring the VLAN register. The packet (including broadcast packet)

is not forwarding to the destination port whose VLAN group is different from the source port.

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3.11 Port Trunking

The port trunking function can also be implemented by VLAN registers. One trunk port isolates the

packet transmitting and receiving from the other trunk ports, which performs a logical trunk topology.

The non-trunk port should choose only one trunk port for transmitting, which can achieve the load bal-

ancing and maintain the packet sequences.

3.12 Memory Interface

Two kinds of external memory interface can be selected by user -- 1M byte memory (256K32 x 1) and 2

M bytes (256K32 x 2 or 512K32 x 1). Maximum 2M byte external memory can be used for packet buff-

ering. “-10 “ speed grade of SGRAM/SDRAM device is recommanded. The following table is the

SGRAM application pin connection :

Memory

Chip No

Memory Type

A[8]

CS0B

CS1B

256K32

512K32

x 1

CS0B

CS1B

x 2

x 1

3.13 Internal MII Registers Acess and Control

The MTD505 support 2 serial pins (SDIO/SDC) for internal registers acess and control; The detailed

registers informations are presented in Section4.0 (Internal MII Registers).

3.14 LED Display

The MTD505 use 10 pins to output 2 kinds of LED display -- LEDDATA[7:0], LEDCLK1, LEDCLK2.

Using LEDCLK1 rising edge, LEDDATA[7:0] report Port7~0 link/receive activity led status. Using

LEDCLK2 rising edge, LEDDATA[4:0] report packet buffer utilization rating, and LEDDATA[7] report

external memory test result(after power reset, MTD505 will test external SDRAM automatically), LED-

DATA[6] report the buffer almost full alarm signal .

4.0 Internal MII Registers

The MTD505 implements 10 MII global registers and 4 per port registers, define as following tables:

TABLE 1. MII registers

GLOBAL REGISTERS

REG

Bits

Name

R/W

Descriptions

Default

CtlReg0

CONTROL REGISTER 0

bit[0] = 1 --> switch to port 0 registers

bit[1] = 1 --> switch to port 1 registers

bit[2] = 1 --> switch to port 2 registers

bit[3] = 1 --> switch to port 3 registers

bit[4] = 1 --> switch to port 4 registers

bit[5] = reserved

8-0

9’h100

bit[6] = reserved

bit[7] = reserved

bit[8] = 1 --> switch to global registers

scan mode select 3-0

12-9

15-13

Scan port select

CtlReg1

R/W

CONTROL REGISTER 1

16’h3084

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TABLE 1. MII registers

GLOBAL REGISTERS

Descriptions

REG

Bits

Name

R/W

Default

7-0

XON

XON threshold.

XOFF threshold.

While EEPROM is enabled, this register’s content will

be updated by EEPROM read XON/XOFF threshold

data automatically. After EEPROM read is done, this

15-8

15-0

XOFF

default is 16’h3084(2M memory) or 16’h1838(1M mem-

ory)

CtlReg2

Aging

R/W

CONTROL REGISTER 2

16’d300

16’h000f

bit[15:0] can specify aging time.

While EEPROM is enabled, this register’s content will

be updated by EEPROM read Aging timer data auto-

matically. After EEPROM read is done, this register can

be read/write by management cmd.

CtlReg3

CONTROL REGISTER 3

bit[15:12] specify port 3’s uplink port ID.

bit[11:8] specify port 2’s uplink port ID.

bit[7:4] specify port 1’s uplink port ID.

bit[3:0] specify port 0’s uplink port ID.

default is 16’h000f.

15-0 Uplink reg0

CtlReg4

P.S this register’s write sequence is Jumper setting ==>

EEPROM content ==> MII management command.

R/W

CONTROL REGISTER 4

16’h0

bit[15:12] :reserved

bit[11:8] : reserved

bit[7:4] : reserved

15-0 Uplink reg1

bit[3:0] specify port 4’s uplink port ID.

default is 16’h0.

P.S this register’s write sequence is Jumper setting ==>

EEPROM content ==> MII management command.

CtlReg5

R/W

CONTROL REGISTER 5

bit[7:0] specify broadcast threshold.

bit[8] enable enhance backpressure.

Reserved.

16’hff

7-0

15-9

P.S this register can be writed by EEPROM content or

MII management command too.

RO/

StsReg0

STATUS REGISTER 0

bit[4:0] outputs port4-0 RXDMA fifofull, bit[7:5] :

reserved.

7-0

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(Preliminary)

TABLE 1. MII registers

GLOBAL REGISTERS

Descriptions

REG

Bits

Name

R/W

Default

bit[12:8] outputs port4-0 TXDMA TPUR(fifoempty),

bit[15:13] : reserved.

15-8

StsReg1

STATUS REGISTER 1

BufBistDone.

BufBistErr.

BufInitDone.

AddrTblBistDone.

AddrTblBistErr.

LthTblBistDone.

LthTblBistErr.

MemBistDone.

MemBistErr.

EEDone.

FreeCntIs0.

15-11 Reserved.

CONTROL REGISTER 7

CtlReg7

CtlReg8

R/W

bit[4:0] output mii polling port4-0 flow control informa-

tion, bit[7:5] : reserved

7-0

bit[12:8] output mii polling port4-0 link information,

bit[15:13] : reserved.

15-8

"1" means flow control enable or link good.

CONTROL REGISTER 8

bit[4:0] output mii polling port4-0 speed information,

bit[7:5] : reserved.

7-0

bit[12:8] output mii polling port4-0 full information,

bit[15:13] :reserved.

15-8

"1" means 100M or full duplex.

PORT REGISTERS

StsReg1

StsReg2

StsReg3

CtlReg1

STATUS REGISTER 1

bit[10:0] output Port Tx queue head value.

Reserved.

10-0

15-11

STATUS REGISTER 2

bit[10:0] output Port Tx queue tail value.

Reserved.

10-0

15-11

STATUS REGISTER 3

bit[10:0] output Port Tx queue count value.

Reserved.

10-0

15-11

R/W

CONTROL REGISTER 1

bit[7:0] select Port VLAN group.

Reserved.

7-0

15-8

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"R/W" means read/writable.

5.0 Electrical Characteristics

5.1 Absolute Maximum Ratings

Symbol

Parameter

Power Supply Voltage

Input Voltage

RATING

-0.3 to 3.6

Unit

V_CC

V_IN

-0.3 to Vcc+0.3

-55 to 150

V_OUT

T_STG

Output Voltage

^oC

Storage Temperature

5.2 Recommended Operating Conditions

Symbol

Parameter

Min.

3.0

Typ.

3.3

Max.

3.6

Unit

V_CC

Power Supply

Input Voltage

V_IN

Vcc

115

^oC

Commercial Junction Operating Temperature

Industrial Junction Operating Temperature

T_j

-40

125

5.3 DC Electrical Characteristics

Symbol

Parameter

Input Leakage Current

Tri-state Leakage Current

Input Capacitance

Conditions

Min.

Typ.

Max.

Unit

I_IL

no pull-up or down

-1

I_OZ

C_IN

2.8

C_OUT

C_BID3

V_IL

Output Capacitance

2.7

4.9

Bi-direction buffer Capacitance

Input Low Voltage

CMOS

0.3*Vcc

V_IH

Input High Voltage

CMOS

0.7*Vcc

2.4

V_OH

V_OL

R_I

I_OL=2,4,8,12,16,24mA

I_OH=2,4,8,12,16,24mA

V_IL=0V or V_IH=V_CC

Output High Voltage

Output Low Voltage

0.4

Input Pull-up/down resistance

KOhm

(Under recommended operating conditions and Vcc = 3.0 ~ 3.6V, Tj = 0 to +115 ^oC)

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5.4 Electrical Characteristics

FIGURE 1. RMII timing

REFCLK

CRSDV

RXD[1:0]

Valid

TXEN

TXD[1:0]

Valid

Symbol

Parameter

RMII input setup time

RMII input hold time

RMII output setup time

RMII output hold time

Min.

Typ.

Max.

Unit

Note

FIGURE 2. MII timing

RXCLK0

Valid

CRS0/RXDV0

RXD0[3:0]

TXCLK0

TXEN0

TXD0[3:0]

Valid

Symbol

Parameter

MII input setup time

Min.

Typ.

Max.

Unit

Note

MII input hold time

MII output setup time

MII output hold time

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FIGURE 3. Memory Write Timing

MEMCLK

RASB

CASB

WEB

T6 T7

AD[8:0]

Valid

T6 T7

DQ[31:0]

Valid

Symbol

Parameter

Memory clock cycle

Min.

Typ.

Max.

Unit

Note

Memory command/address/data

setup time

Memory command/address/data

hold time

Row active to burst write

CLK

FIGURE 4. Memory Read Timing

MEMCLK

RASB

CASB

WEB

T6 T7

AD[8:0]

Valid

T10

DQ[31:0]

Valid

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Symbol

T10

Parameter

Min.

Typ.

Max.

Unit

Note

Memory read data setup time

Memory ead data hold time

T11

FIGURE 5. EEPROM timing

T11

EECLK

T13

T12

EEDATA

Valid

Symbol

Parameter

Min.

Typ.

Max.

Unit

Note

T11

T12

T13

EEPROM clock cycle

EEDATA input setup time

EEDATA input hold time

FIGURE 6. LED Interface

LEDCLK1

LEDCLK2

LEDDATA

T14

T15

T16

Valid

Symbol

T14

Parameter

Min.

Typ.

Max.

Unit

Note

Led display strobe period

LEDCLK setup time

LEDCLK hold time

T15

T16

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(Preliminary)

6.0 128 pin PQFP Package Data

Dimension in inch

Min Norm Max

Dimension in mm

Symbol

Min Norm Max

0.134

3.40

0.010

0.25

102

0.107 0.112 0.117 2.73 2.85 2.97

0.007 0.009 0.011 0.17 0.22 0.27

103

0.004

0.008 0.09

0.20

0.906 0.913 0.921 23.00 23.20 23.40

0.783 0.787 0.791 19.90 20.00 20.10

0.669 0.677 0.685 17.00 17.20 17.40

0.547 0.551 0.555 13.90 14.00 14.10

0.020 BSC

0.50 BSC

0.029 0.035 0.041 0.73 0.88 1.03

0.063 BSC

1.60 BSC

128

0.004

0.10

Note:

1.Dimension D1 & E1 do not include mold protrusion.

But mold mismatch is included. Allowable protrusion is .25mm/.010” per side.

2.Dimension B does not include dambar protrusion. Allowable dambar protru-

sion .08mm/.003”. Total in excess of the B dimemsion at maximum material

condition. Dambar cannot be located on the lower radius or the foot.

3.Controlling dimension : Millimeter.

See Detail B

See Detail A

Seating Plane

With Plating

Gage Plane

Base Metal

Detail A

Detail B

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MTD505 Revision 1.2 14/04/2000

MTD505 [ETC]

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