MTD516 [ETC]
16 Port 10M/100M Ethernet Switch; 16端口10M / 100M以太网交换机
| 型号： | MTD516 |
| 厂家： | 
ETC |
| 描述： | 16 Port 10M/100M Ethernet Switch |
| 文件： | 总27页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MYSON
MTD516
TECHNOLOGY
(Preliminary)
16 Port 10M/100M Ethernet Switch
FEATURES
GENERAL DESCRIPTION
•
•
IEEE802.3 and IEEE802.3u compliant.
Provide 16 RMII (Reduced Media Independent
Interface) ports.
Programmable 1K/8K MAC addresses filtering
database.
Store and forward switching function and bad
packet filtering function.
Optional back_pressure/802.3x flow control/
flooding control/broadcast control.
Optional EEPROM Interface for advanced
switch configurations.
4MB/2MB packet buffer with SGRAM/SDRAM
flexible memory interface.
Port VLAN/trunking.
Link/Rx activity, packet buffer utilization LED
display.
The MTD516 complies fully with the
IEEE802.3, 802.3u and 802.3x specifications and
is a non-blocking 16 port 10M/100M Ethernet
switch device.
Support 16 RMII ports for 10M/100M oper-
ation. 4MB memory interface provides maximum
2730 packet buffers for Ethernet packet buffering.
Up to 8192 address entrys are provided by the
MTD516, and the MTD516 use full Ethernet
address compare algorithm to minimize hashing
collision events.
The MTD516 provides EEPROM interface
to config port trunking, port VLAN, static entry,
802.3x flow control threshold, flooding port,
broadcast control threshold. Each MTD516 ports
support 10M/100M auto-negotiation by MII man-
agement interface.
The MTD516 also provides 2 pins for Link/
RX activity, packet buffer utilization LED display
function.
•
•
•
•
•
•
•
•
•
•
83MHz for non-blocking 16 port switch.
Build in internal/external memory test function.
208 pin PQFP package, 3.3V operation volt-
age.
BLOCK DIAGRAM
SDRAM/
SGRAM
Interface
Memory
Controller
RMII0
DMA0
MAC0
RMII1
RMII2
RMII3
DMA1
DMA2
DMA3
MAC1
MAC2
MAC3
Memory
Arbiter
3~12
RMII12
DMA4
MAC4
RMII13
RMII14
RMII15
DMA13
DMA14
DMA15
MAC13
MAC14
MAC15
Port
Switch
Logic
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
1/27
MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
SYSTEM DIAGRAM
(**OPTION)
EEPROM
(**Programmable)
SGRAM
(512kx32x2)
MTD516
LEDs
SGRAM
(256kx32x2)
RMII11-15
RMII0-7
OCTAL
OCTAL
PHYsceiver
PHYsceiver
MII management
OCTAL
OCTAL
Transformer
Transformer
RJ45
RJ45
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
2/27
MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
1.0 PIN CONNECTION
DQ10
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
DQ42
DQ11
DQ41
GND
DQ40
VCC
DQ32
DQ12
DQ33
DQ13
DQ34
DQ14
DQ35
DQ15
DQ36
DQ24
DQ37
DQ25
VCC
DQ26
GND
DQ27
DQ38
DQ28
DQ39
DQ29
DQ48
DQ30
DQ49
DQ31
DQ50
LEDDATA
LEDCLK
EEDATA
EECLK
GND
DQ51
DQ52
DQ53
DQ54
DQ55
REFCLK
VCC
VCC
SYSCLK
GND
MTD516
RESETB
MDC
RXD15_1
RXD15_0
CRSDV15
TXEN15
TXD15_0
TXD15_1
RXD14_1
RXD14_0
CRSDV14
TXEN14
TXD14_0
TXD14_1
VCC
MDIO
TXD0_1
TXD0_0
TXEN0
CRSDV0
RXD0_0
RXD0_1
GND
VCC
TXD1_1
TXD1_0
TXEN1
CRSDV1
RXD1_0
RXD1_1
TXD2_1
TXD2_0
TXEN2
CRSDV2
RXD2_0
RXD2_1
TXD3_1
TXD3_0
TXEN3
CRSDV3
RXD3_0
RXD3_1
GND
RXD13_1
RXD13_0
CRSDV13
TXEN13
TXD13_0
TXD13_1
RXD12_1
RXD12_0
CRSDV12
TXEN12
TXD12_0
TXD12_1
RXD11_1
RXD11_0
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MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
2.0 PIN DESCRIPTIONS
RMII Port Interface Pins
Descriptions
Name
CRSDV0
Pin Number I/O
I
Port0 RMII receive interface signal, CRSDV0 is asserted high when
port0 media is non_idle.
186
RXD0_0
RXD0_1
TXEN0
I
I
Port0 RMII receive data bit_0.
Port0 RMII receive data bit_1.
Port0 RMII transmit enable signal.
Port0 RMII transmit data bit_0.
Port0 RMII transmit data bit_1.
187
188
O
O
O
I
185
TXD0_0
TXD0_1
CRSDV1
184
183
Port1 RMII receive interface signal, CRSDV1 is asserted high when
port1 media is non_idle.
194
RXD1_0
RXD1_1
TXEN1
I
I
Port1 RMII receive data bit_0.
Port1 RMII receive data bit_1.
Port1 RMII transmit enable signal.
Port1 RMII transmit data bit_0.
Port1 RMII transmit data bit_1.
195
196
O
O
O
I
193
TXD1_0
TXD1_1
CRSDV2
192
191
Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
200
RXD2_0
RXD2_1
TXEN2
I
I
Port2 RMII receive data bit_0.
Port2 RMII receive data bit_1.
Port2 RMII transmit enable signal.
Port2 RMII transmit data bit_0.
Port2 RMII transmit data bit_1.
201
202
O
O
O
I
199
TXD2_0
TXD2_1
CRSDV3
198
197
Port3 RMII receive interface signal, CRSDV0 is asserted high when
port3 media is non_idle.
206
RXD3_0
RXD3_1
TXEN3
I
I
Port3 RMII receive data bit_0.
207
208
Port3 RMII receive data bit_1.
O
O
O
I
Port3 RMII transmit enable signal.
Port3 RMII transmit data bit_0.
205
TXD3_0
TXD3_1
CRSDV4
204
203
Port3 RMII transmit data bit_1.
Port4 RMII/MII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
4
RXD4_0
RXD4_1
TXEN4
I
I
Port4 RMII/MII receive data bit_0.
Port4 RMII/MII receive data bit_1.
Port4 RMII transmit enable signal
Port4 RMII/MII transmit data bit_0.
Port4 RMII/MII transmit data bit_1.
5
6
O
O
O
I
3
TXD4_0
TXD4_1
CRSDV5
2
1
Port5 RMII receive interface signal, CRSDV5 is asserted high when
port5 media is non_idle.
12
RXD5_0
RXD5_1
TXEN5
I
Port5 RMII receive data bit_0.
Port5 RMII receive data bit_1.
Port5 RMII transmit enable signal.
Port5 RMII transmit data bit_0.
Port5 RMII transmit data bit_1.
13
14
I
O
O
O
9
TXD5_0
TXD5_1
8
7
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MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
RMII Port Interface Pins
Descriptions
Name
CRSDV6
Pin Number I/O
I
Port6 RMII receive interface signal, CRSDV6 is asserted high when
port6 media is non_idle.
18
RXD6_0
RXD6_1
TXEN6
I
I
Port6 RMII receive data bit_0.
Port6 RMII receive data bit_1.
Port6 RMII transmit enable signal.
Port6 RMII transmit data bit_0.
Port6 RMII transmit data bit_1.
19
20
O
O
O
I
17
TXD6_0
TXD6_1
CRSDV7
16
15
Port7 RMII receive interface signal, CRSDV7 is asserted high when
port7 media is non_idle.
24
RXD7_0
RXD7_1
TXEN7
I
I
Port7 RMII receive data bit_0.
Port7 RMII receive data bit_1.
Port7 RMII transmit enable signal.
Port7 RMII transmit data bit_0.
Port7 RMII transmit data bit_1.
25
26
O
O
O
I
23
TXD7_0
TXD7_1
CRSDV8
22
21
Port8 RMII receive interface signal, CRSDV8 is asserted high when
port8 media is non_idle.
32
RXD8_0
RXD8_1
TXEN8
I
I
Port8 RMII receive data bit_0.
Port8 RMII receive data bit_1.
Port8 RMII transmit enable signal.
Port8 RMII transmit data bit_0.
Port8 RMII transmit data bit_1.
33
34
O
O
O
I
31
TXD8_0
TXD8_1
CRSDV9
30
29
Port9 RMII receive interface signal, CRSDV9 is asserted high when
port9 media is non_idle.
38
RXD9_0
RXD9_1
TXEN9
I
I
Port9 RMII receive data bit_0.
Port9 RMII receive data bit_1.
Port9 RMII transmit enable signal.
Port9 RMII transmit data bit_0.
Port9 RMII transmit data bit_1.
39
40
O
O
O
I
37
TXD9_0
TXD9_1
CRSDV10
36
35
Port10 RMII receive interface signal, CRSDV10 is asserted high when
port10 media is non_idle.
46
RXD10_0
RXD10_1
TXEN10
I
I
Port10 RMII receive data bit_0.
Port10 RMII receive data bit_1.
Port10 RMII transmit enable signal.
Port10 RMII transmit data bit_0.
Port10 RMII transmit data bit_1.
47
48
O
O
O
I
45
TXD10_0
TXD10_1
CRSDV11
44
43
Port11 RMII receive interface signal, CRSDV11 is asserted high when
port11 media is non_idle.
52
RXD11_0
RXD11_1
TXEN11
TXD11_0
TXD11_1
I
Port11 RMII receive data bit_0.
Port11 RMII receive data bit_1.
Port11 RMII transmit enable signal.
Port11 RMII transmit data bit_0.
Port11 RMII transmit data bit_1.
53
54
I
O
O
O
51
50
49
5/27
MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
RMII Port Interface Pins
Descriptions
Name
Pin Number I/O
CRSDV12
I
Port12 RMII receive interface signal, CRSDV12 is asserted high when
port12 media is non_idle.
58
RXD12_0
RXD12_1
TXEN12
I
I
Port12 RMII receive data bit_0.
Port12 RMII receive data bit_1.
Port12 RMII transmit enable signal.
Port12 RMII transmit data bit_0.
Port12 RMII transmit data bit_1.
59
60
O
O
O
I
57
TXD12_0
TXD12_1
CRSDV13
56
55
Port13 RMII receive interface signal, CRSDV13 is asserted high when
port13 media is non_idle.
64
RXD13_0
RXD13_1
TXEN13
I
I
Port13 RMII receive data bit_0.
Port13 RMII receive data bit_1.
Port13 RMII transmit enable signal.
Port13 RMII transmit data bit_0.
Port13 RMII transmit data bit_1.
65
66
O
O
O
I
63
TXD13_0
TXD13_1
CRSDV14
62
61
Port14 RMII receive interface signal, CRSDV14 is asserted high when
port14 media is non_idle.
72
RXD14_0
RXD14_1
TXEN14
I
I
Port14 RMII receive data bit_0.
Port14 RMII receive data bit_1.
Port14 RMII transmit enable signal.
Port14 RMII transmit data bit_0.
Port14 RMII transmit data bit_1.
73
74
O
O
O
I
71
TXD14_0
TXD14_1
CRSDV15
70
69
Port15 RMII receive interface signal, CRSDV15 is asserted high when
port15 media is non_idle.
78
RXD15_0
RXD15_1
TXEN15
TXD15_0
TXD15_1
I
Port15 RMII receive data bit_0.
Port15 RMII receive data bit_1.
Port15 RMII transmit enable signal.
Port15 RMII transmit data bit_0.
Port15 RMII transmit data bit_1.
79
80
I
O
O
O
77
76
75
6/27
MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
Synchronous DRAM/GRAM Interface Pins
Name
AD[8:0]
Pin Number I/O
Descriptions
O
Memory row/column address bus outputs
123~131
AD[7:0] are row/column address [7:0].
AD[8] : This pin should connect to SGRAM/SDRAM MSB address bit.
DQ[63:0]
I/O Memory data bus DQ[63:56] : 119~112
DQ[55:48] : 84~91
119~112,
84~91,
111~108,
DQ[47:44] : 111~108
DQ[43:40] : 105~102
DQ[39:38] : 92~93
105~102,
92~93,
96~101,
172~165,
137~139,
142~146,
164~161,
158~155,
147~154
DQ[37:32] : 96~101
DQ[31:24] : 172~165
DQ[23:21] : 137~139
DQ[20:16] : 142~146
DQ[15:12] : 164~161
DQ[11:8] : 158~155
DQ[7:0] : 147~154
RASB
CASB
WEB
134
135
136
132
133
121
O
O
O
O
O
O
SGRAM/SDRAM row address select
SGRAM/SDRAM column address select
SGRAM/SDRAM write enable
SGRAM/SDRAM bank select
Memory chip select 0
BA
CS0B
MEMCLK
Memory clock output.
Note: SGRAM/SDRAM access time: 10 ns (max)
Miscellaneous Pins
Name
RESETB
Pin Number I/O
Descriptions
180
82
I
I
I
System reset input, low active.
Switch core system clock input
RMII reference clock input
SYSCLK
REFCLK
MDC
178
181
182
I/O MII management clock inout.
MDIO
I/O MII management data inout
EECLK/
I/O After ResetB deassert to ? ms , this pin indicate EECLK,
176
175
SDC
After 150 ms, it indicate SDC.
EEDATA/
I/O After ResetB deassert to ? ms , this pin be indicated EEDATA,
SDIO
After 150 ms, it indicate SDIO.
I/O LED Clock.
LEDCLK
Using bursted clock for latching 32 display informations (one clock
latch one information) , per burst have 32 continuous clocks (clock
period = 320 ns); and the time between burst to burst is 655 us.
174
7/27
MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
Miscellaneous Pins
Name
Pin Number I/O
Descriptions
LEDDATA
I/O LED Data (high_active).
The serial output display informations using bursted styling ,per burst
have 32 informations, as following:
LEDCLK
01
LEDDATA
P0_RxAct
P1_RxAct
P2_RxAct
P3_RxAct
P4_RxAct
P5_RxAct
P6_RxAct
P7_RxAct
P8_RxAct
P9_RxAct
P10_RxAct
P11_RxAct
P12_RxAct
P13_RxAct
P14_RxAct
P15_RxAct
LEDCLK
17
LEDDATA
Uti_1%
02
18
Uti_3%
03
19
Uti_5%
04
20
Uti_10%
Uti_15%
Uti_20%
Uti_30%
Uti_35%
Uti_40%
Uti_50%
Uti_60%
Uti_70%
Uti_80%
Uti_90%
BufferAlarm
MemTestFail
05
21
06
22
173
07
23
08
24
09
25
10
26
11
27
12
28
13
29
14
30
15
31
16
32
VCC
GND
11,28,42,68, PWR Power pins
83,95,107,
122,141,160,
179,190,
10,27,41,67, GND Ground pins
81,94,106,
120,140,159,
177,189,
8/27
MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
3.0 Power on Setting Configuration
Jumper Configuration After Power On Reset
defa
ult
Pin Name
MDC
Function
Descriptions
802.3x flow control function enable.
1
1
1
1
1
0
0
0
0
0
0
0
FlowCtrlEn
external pull_hgih =1, 802.3x flow control enable.
external pull_low = 0, 802.3x flow control disable.
In Half duplex mode, backpressure function enable.
EECLK
BakPsureEn
MiiPollEn
external pull_hgih =1, backpressure enable.
external pull_low = 0, backpressure disable.
EEDATA
LEDCLK
LEDDATA
TXEN13
TXEN12
TXEN11
TXEN10
TXEN9
Polling PHY device’s MII register function enable.
external pull_hgih =1, PHY auto polling enable.
external pull_low = 0, PHY auto polling disable.
Aging out function for address learning enable.
AgingEn
external pull_hgih =1, aging out function enable.
external pull_low = 0, aging out function disable.
Embbeded memory self-test function enable.
BISTEn
external pull_hgih =1, memory BIST enable.
external pull_low = 0, memory BIST disable.
For chip test only.
FastMode
ScanMode
8KAddrTblEn
EEPROMEn
external pull_hgih =1, chip fast test mode enable.
external pull_low = 0, chip fast test mode disable.
For chip test only.
external pull_hgih =1, chip scan test mode enable.
external pull_low = 0, chip scan test mode disable.
8K entry address table enable.
external pull_hgih =1, 8K address table enable.
external pull_low = 0, 8K address table disable; defaule is 1K entry.
Auto_load from EEPROM function enable.
external pull_hgih =1, auto load from EEPROM function enable.
external pull_low = 0, auto load from EEPROM function disable.
Broadcast storm protect function enable.
BroadStor-
mEn
external pull_hgih =1, broadcast storm protection enable.
external pull_low = 0, broadcast storm protection disable.
For 12 port switch, only Port11~Port0 enable.
TXEN8
En12PortSW
P15FXEn
external pull_hgih =1, 12 port switch enable.
external pull_low = 0, default is 16 port switch.
Port 15 FX function indicator.
TXEN7
external pull_hgih =1, port15 FX function enable.
external pull_low = 0, port15 FX function disable.
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MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
Jumper Configuration After Power On Reset
defa
ult
Pin Name
TXEN6
Function
Descriptions
0
0
0
0
0
0
0
Port15 duplex ability indicator (under port15 configured in FX mode).
external pull_hgih =1, port15 operate in full_duplex mode.
P15Full
external pull_low = 0, port15 operate in half_duplex mode.
VLAN tag 1522 bytes acceptance function enable.
TXEN5
TXEN4
TXEN3
TXEN2
TXEN1
TXEN0
En1522
FloodCtrlEn
FloodID[3]
FloodID[2]
FloodID[1]
FloodID[0]
external pull_hgih =1, VLAN tag 1522 bytes acceptance enable.
external pull_low = 0, VLAN tag 1522 bytes acceptance enable disable.
Flooding control function enable.
external pull_hgih =1, flooding control function enable.
external pull_low = 0, flooding control function disable.
Flooding Port ID bit 3
external pull_hgih =1.
external pull_low = 0.
Flooding Port ID bit 2
external pull_hgih =1.
external pull_low = 0.
Flooding Port ID bit 1
external pull_hgih =1.
external pull_low = 0.
Flooding Port ID bit 0
external pull_hgih =1.
external pull_low = 0.
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MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
4.0 FUNCTIONAL DESCRIPTIONS
The MTD516 is an 16 ports 10/100 Mbps fast Ethernet switch controller. It is a low cost solution for six-
teen ports fast Ethernet SOHO switch design. No CPU interface is required; After power on reset,
MTD516 provide an auto load configuration setting function through a 2 wire serial EEPROM interface
to acess external EEPROM device, and MTD516 can easily be configured to support port_trunking,
port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port assignment ...etc func-
tions. The following descriptions are MTD516’s major functional blocks overview.
4.1 Packet store and forwarding
The MTD516 use simple store and forward algorithm as packet switching method. Input packet from
ports will be stored to external memory first, while packet is good for forward (CRC chech ok, 64Bytes <
length < 1518Bytes, not local packets, in the same VLAN group ) , if this packet’s DA hits, than forward
this packet to the destination port, otherwise this packet will be broadcasted.
4.2 Learning and Routing
The MTD516 supports 1K or 8K MAC entries for switching. Dynamic address learning is performed by
each good unicast packet is completely received. The static address learning is achieved by EEPROM
configuration. On the other hand, the routing process is performed whenever the packet’s DA is cap-
tured. If the DA can not get a hit result, the packet is going to switch broadcast or forward to the dedi-
cated port according to the flooding control selction.
4.3 Aging
Only the dynamic address entries are scheduled in the aging machine. If one station does not transmit
any packet for a period of time, the belonging MAC address will be kicked out from the address table.
The aging out time can be program through the EEPROM auto load configuration. (Default value is 300
seconds)
4.4 Buffer Queue Management
The buffer queue manager is implemented to manage the external shared memory (use SDRAM/
SGRAM) for packet buffering. The main function of the buffer queue manager is to maintain the linked
list consists of buffer IDs, which is used to show the corresponding memory address for each incoming
packet. In addition, the buffer queue manager monitors the rested free spaces status of the external
memory, If the packet storage achieve the predefined threshold value, the buffer queue manager will
raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission ID
queue overflow happening. MTD516 provide 802.3x flow control in full duplex mode and back pressure
control in half duplex mode.
4.5 Full Duplex 802.3x Flow Control
In full duplex mode, MTD516 supports the standard flow control defined in IEEE802.3x standard. It
enables the stopping of remote node transmissions via a PAUSE frame information interactoin. When
the “802.3x flow control enable” bit is setted during power on reset (MDC pin is external pull_high),
it enables MTD516 supporting 802.3x flow control function in full_duplex mode; When output port buffer
queue’s on_using value reach the initialization setting threshold value(recommended XON_TH = 40’h
under total free ID less then 100’h), MTD516 will send out a PAUSE packet with pause time equal to
FFF to stop the remote node transmission; When the output port buffer queue’s on_using value reduce
to the initialization threshold value(recommended Xoff_TH = 1C’h when using 2Mbytes external mem-
ory), MTD516 will also send a PAUSE packet with pause time equal to zero to inform the remote node
to retransmit packet.
4.6 Half Duplex Back Pressure Control
In half duplex mode, MTD516 provide a back pressure control mechanism to avoid dropping packets
during network conjection situation. When the “back pressure control enable” bit is set during power on
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reset (EECLK pin is external pull_high), it enables MTD516 supporting back pressure function in
half_duplex mode; When output port buffer queue’s on_using value reach the initialization setting
threshold value (same with the Xon_TH value), MTD516 will send a JAM pattern in the input port when
it senses an incoming packet , thus force a collision to inform the remote node transmission back
off and will effectively avoid dropping packets. If the “back pressure control enable” bit is not set, and
there is no free buffer queue available for the incoming packets, the incoming packets will be dropped.
4.7 MII Polling
The MTD516 supports PHY management through the serial MDIO/MDC interface. After power on
reset, the MTD516 write related abilities to the advertisement register 4 of connected PHY devices and
restart the auto_negotiation prcedure via MDIO/MDC interface using the predefined PHY addresses
increasingly from “01000”b to “10111”b. The MTD516 will periodically and continuously poll and update
the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow control
capable status of the connected PHY devices through MDIO/MDC serial interface.
4.8 MAC and DMA engine
The MTD516’s MAC performs all the functions in IEEE802.3 protocol, such as frame formatting, frame
stripping, CRC checking, bad packet dropping, defering to line traffic, and collision handling. The MAC
Rx_engine checks incoming packets and drops the bad packet which include CRC error, alignment
error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the
“VLAN tag 1522 bytes receive enable” bit is set during power on reset). Before transmission, The MAC
Tx_engine will constantly monitor the line traffic using derfering precedure. Only if it has been idle for a
96 bits time (a minimum interpacket gap time, IPG time), actual transmmission can be started. For the
half duplex mode, MAC engine will detect collision; if a collision is detected, the MAC Tx_engine will
transmit a JAM pattern and then delay the re_transmission for a random time period determined by the
back_off algorithm (MTD516 implements the truncated exponential back_off algorithm defined in IEEE
802.3 standard). For the full duplex mode, collision signal is ignored.
The MTD516’s DMA engine performs the packets non_blocking transportation between MAC engine
and external memory according to a high speed switching procedure. The switching procedure is com-
pleted by address learning/routing process and buffer queue management operation.
4.9 EEPROM interface
MTD516 provide an auto load configuration setting function through a 2 wire serial EEPROM interface
to acess external EEPROM device(24C02) after power on reset . MTD516 can easily be configured to
support port_trunking, port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port
assignment ...etc functions.
4.10 Port Based VLAN
The MTD516 supports VLAN configuration by port based methodology. One port select the certain
ports to form its VLAN group by configuring the VLAN register. The packet (including broadcast packet)
is not forwarding to the destination port whose VLAN group is different from the source port.
4.11 Port Trunking
The port trunking function can also be implemented by VLAN registers. One trunk port isolates the
packet transmitting and receiving from the other trunk ports, which performs a logical trunk topology.
The non-trunk port should choose only one trunk port for transmitting, which can achieve the load bal-
ancing and maintain the packet sequences.
4.12 Memory Interface
Two kinds of external memory interface can be selected by user -- 2M byte memory (256K32 x 2) and 4
M bytes ( 512K32 x 2). Maximum 4M byte external memory can be used for packet buffering. “-10 “
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speed grade of SGRAM/SDRAM device is recommanded. The following table is the SGRAM applica-
tion pin connection :
Memory
Memory Type
A[8]
GND
Chip No
x 2
x 2
256K32
512K32
A8
A9
-
A8
4.13 Internal MII Registers Acess and Control
The MTD516 support 2 serial pins (SDIO/SDC) for internal registers acess and control; The detailed
registers informations are presented in Section5.0 (Internal MII Registers).
4.14 LED Display
The MTD516 use 2 pins to output 2 kinds of LED display -- LEDDATA, LEDCLK,
Using LEDCLK rising edge with 32 bits shift register to latch LEDDATA as DATA[31:0]. DATA[15:0]
report Port15~0 link/receive activity led status. DATA[29:16] report packet buffer utilization rating, and
DATA[31] report external memory test result(after power reset, MTD516 will test external SDRAM auto-
matically), DATA[30] report the buffer almost full alarm signal .
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5.0 Register Description
Global Register : Control Register (addr = 5’h0)
Bit
Name
R/W Descriptions
0
R/W “1” means Reg addr1-4 as Port Registers described as follows.
Port Reg Select
enable
“0” means Reg addr1-4 as Global Registers described as follows.
R/W If bit0 = 0, bit[4:1] don’t care, and under bit[0] = 1,
4-1
bit[4:1] = 0, Reg1-4 switch to Port0 Registers
bit[4:1] = 1, Reg1-4 switch to Port1 Registers
bit[4:1] = 2, Reg1-4 switch to Port2 Registers
bit[4:1] = 3, Reg1-4 switch to Port3 Registers
bit[4:1] = 4, Reg1-4 switch to Port4 Registers
bit[4:1] = 5, Reg1-4 switch to Port5 Registers
bit[4:1] = 6, Reg1-4 switch to Port6 Registers
bit[4:1] = 7, Reg1-4 switch to Port7 Registers
bit[4:1] = 8, Reg1-4 switch to Port8 Registers
bit[4:1] = 9, Reg1-4 switch to Port9 Registers
bit[4:1] = a, Reg1-4 switch to Port10 Registers
bit[4:1] = b, Reg1-4 switch to Port11 Registers
bit[4:1] = c, Reg1-4 switch to Port12 Registers
bit[4:1] = d, Reg1-4 switch to Port13 Registers
bit[4:1] = e, Reg1-4 switch to Port14 Registers
Port Reg Select
bit[4:1] = f, Reg1-4 switch to Port15 Registers
R/W “1” Enable
5
Scan Mode
Enable
“0” Disable
9-6
Scanout Group R/W bit[9:6]= 0 means group 0 , etc ...
Select
13-10 Scanout Port
R/W bit[13:10] = 0 means Port0, etc,...
Select
15-14
Reserved
16’h0000
15-0
Default Value
Global Register : XON/XOFF Register (addr = 5’h1)
Bit
7-0
Name
XONTH
XOFFTH
R/W
Descriptions
R/W XON threshold
R/W XOFF threshold
15-8
15-0
XON threshold default is 8’d64(2M)
XOFF threshold default is 8’h28(2M)
Default Value
P.S while EEPROM is enabled, this register’s content will be updated by
EEPROM.
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Global Register : Aging Register (addr = 5’h2)
Bit
15-0
15-0
Name
R/W
Descriptions
AgeTH
R/W Aging time.
Default is 16’d300.
Default Value
P.S while EEPROM is enabled, this register’s content will be updated by
EEPROM.
Global Register : Uplink0 Register (addr = 5’h3)
Bit
15
Name
R/W
Descriptions
Reserved
14-0
9-5
Port2 ID
Port1 ID
Port0 ID
R/W Specify port2’s uplink port ID
R/W Specify port1’s uplink port ID
R/W Specify port0’s uplink port ID
Default is 16’h001f.
4-0
15-0
Default Value
P.S this register’s writing sequence is Jumper setting ==> EEPROM
==>MII management command.
Global Register : Uplink1 Register (addr = 5’h4)
Bit
15
Name
R/W
Descriptions
Reserved
14-0
9-5
Port5 ID
Port4 ID
Port3 ID
R/W Specify port5’s uplink port ID
R/W Specify port4’s uplink port ID
R/W Specify port3’s uplink port ID
Default is 16’h0000.
4-0
15-0
Default Value
P.S this register’s writing sequence is Jumper setting ==> EEPROM
==>MII management command.
Global Register : Uplink2 Register (addr = 5’h5)
Bit
15
Name
R/W
Descriptions
Reserved
14-0
9-5
Port8 ID
Port7 ID
Port6 ID
R/W Specify port8’s uplink port ID
R/W Specify port7’s uplink port ID
R/W Specify port6’s uplink port ID
Default is 16’h0000.
4-0
15-0
Default Value
P.S this register’s writing sequence is Jumper setting ==> EEPROM
==>MII management command.
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Global Register : Uplink3 Register (addr = 5’h6)
Bit
15
Name
R/W
Descriptions
Reserved
14-0
9-5
Port11 ID
Port10 ID
Port9 ID
R/W Specify port11’s uplink port ID
R/W Specify port10’s uplink port ID
R/W Specify port9’s uplink port ID
Default is 16’h0000.
4-0
15-0
Default Value
P.S this register’s writing sequence is Jumper setting ==> EEPROM
==>MII management command.
Global Register : Uplink4 Register (addr = 5’h7)
Bit
15
Name
R/W
Descriptions
Reserved
14-0
9-5
Port14 ID
Port13 ID
Port12 ID
R/W Specify port14’s uplink port ID
R/W Specify port13’s uplink port ID
R/W Specify port12’s uplink port ID
Default is 16’h0000.
4-0
15-0
Default Value
P.S this register’s writing sequence is Jumper setting ==> EEPROM
==>MII management command.
Global Register : Uplink5 Register (addr = 5’h8)
Bit
15-5
4-0
Name
R/W
Descriptions
Reserved
Port15 ID
R/W Specify port15’s uplink port ID
Default is 16’h0000.
15-0
Default Value
P.S this register’s writing sequence is Jumper setting ==> EEPROM
==>MII management command.
Global Register : Brdcast Storm Threshold Register (addr = 5’h9)
Bit
15-9
8
Name
R/W
Descriptions
Reserved
R/W Backpressure Enhance Mode Enable.
R/W Specify broadcast storm threshold
Default is 16’h00ff.
7-0
Brdcast TH
15-0
Default Value
P.S this register’s writing sequence is Jumper setting ==> EEPROM
==>MII management command.
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Global Register : Status0 Register (addr = 5’ha)
Bit
Name
R/W
Descriptions
15-0
fifofull
R/O output Port15-0 RXDMA fifofull signal
Global Register : Status1 Register (addr = 5’hb)
Bit
Name
R/W
Descriptions
15-0
fifoempty
R/O output Port15-0 TXDMA TPUR(fifoempty)signal
Global Register : Status2 Register (addr = 5’hc)
Bit
15-14
13
12
11
10
9
Name
R/W
Descriptions
R/O Reserved
R/O Reserved
R/O Reserved
R/O Reserved
FreeCntIs0
EEDONE
R/O FreeCntIs0
R/O EEDONE
8
MemBistErr
MemBistDone
LthTblBistErr
R/O SGRAM Bist Error
R/O SGRAM Bist Done
R/O Length Table Bist Error
7
6
5
LthTblBistDone R/O Length Table Bist Done
AddrTblBistErr R/O Internal 1K address table Bist Error
4
3
AddTblBist-
Done
R/O Internal 1K address table Bist Done
2
1
0
BufInitDone
BufBistErr
R/O Buffer link initialization Done
R/O Buffer Table Bist Error
R/O Buffer Table Bist Done
BufBistDone
Global Register : Control/Status0 Register (addr = 5’hd)
R/W Descriptions
Bit
Name
15-0
R/W Output MII polling port15-0 flow control information.
FlowCtrl
P.S “1” means flow control is enabled
15-0
when Polling disabled, default value is 16’hffff
Default Value
when Polling enabled, default value is 16’h0000.
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Global Register : Control/Status1 Register (addr = 5’he)
R/W Descriptions
Bit
Name
15-0
R/W Output MII polling port15-0 link information.
Link
P.S “1” means link good
15-0
when Polling disabled, default value is 16’hffff
Default Value
when Polling enabled, default value is 16’h0000.
Global Register : Control/Status2 Register (addr = 5’hf)
R/W Descriptions
Bit
Name
15-0
R/W Output MII polling port15-0 speed information.
Speed
P.S “1” means 100M
15-0
when Polling disabled, default value is 16’hffff
Default Value
when Polling enabled, default value is 16’h0000.
Global Register : Control/Status3 Register (addr = 5’h10)
R/W Descriptions
Bit
Name
15-0
R/W Output MII polling port15-0 full duplex information.
FullDuplex
P.S “1” means full duplex
15-0
when Polling disabled, default value is 16’hffff
Default Value
when Polling enabled, default value is 16’h0000.
Global Register : DebugReg0 Register (addr = 5’h11)
R/W Descriptions
Bit
15-0
15-0
Name
LocalFilter
Default Value
R/W “1” disable port15-0 local packet filter function.
Default is 16’h0000
Global Register : DebugReg1 Register (addr = 5’h12)
R/W Descriptions
RXLengthChk R/W “1” disable port15-0 Rx Length Check function.
Default Value Default is 16’h0000
Bit
15-0
15-0
Name
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Global Register : DebugReg2 Register (addr = 5’h13)
Bit
15-0
15-0
Name
R/W
Descriptions
Reserved
R/W Reserved
Default Value
Default is 16’h0000
Global Register : DebugReg3 Register (addr = 5’h14)
R/W Descriptions
Bit
15-0
15-0
Name
CRCChk
R/W “1” disable port15-0 CRC check function.
Default is 16’h0000
Default Value
Global Register : DebugReg4 Register (addr = 5’h15)
R/W Descriptions
Bit
15-0
15-0
Name
Random#
R/W “1” fix port15-0 random backoff number.
Default is 16’h0000
Default Value
Global Register : DebugReg5 Register (addr = 5’h16)
Bit
15-0
15-0
Name
R/W
Descriptions
Reserved
R/W Reserved
Default Value
Default is 16’h0000
Global Register : FreeHead Register (addr = 5’h17)
R/W Descriptions
Bit
15-12
11-0
Name
Reserved.
R/O Output Free List Head ID
FreeHead
Global Register : FreeTail Register (addr = 5’h18)
R/W Descriptions
Bit
15-12
11-0
Name
Reserved.
R/O Output Free List Tail ID
FreeTail
Global Register : FreeCnt Register (addr = 5’h19)
R/W Descriptions
Bit
15-12
11-0
Name
Reserved.
FreeCnt
R/O Output Free List Count Value.
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Global Register : PortEnable Register (addr = 5’h1a)
Bit
15-0
15-0
Name
PortEnable
Default
R/W
Descriptions
R/W “1” disable Port 15-0
Default value is 16’h0000
Port Register : TxLinkHead Register (addr = 5’h1)
R/W Descriptions
Bit
15-13
12-0
Name
Reserved
TxLinkHead
R/O Output Port Tx Queue Head Value
Port Register : TxLinkHead Register (addr = 5’h2)
Bit
15-13
12-0
Name
R/W
Descriptions
Reserved
TxLinkCnt
R/O Output Port Tx Queue Count Value
Port Register : VLANReg Register (addr = 5’h3)
Bit
Name
R/W
Descriptions
15-0
VLANReg
R/W Select Port VLAN Group.
6.0 EEPROM Content
EEPROM Content
Descriptions
Addr
h0
Name
EOB
Last EEPROM content address value
Age Time bit 7-0.
h1
AgeLow
AgeHigh
VLAN0L
VLAN0H
VLAN1L
VLAN1H
VLAN2L
h2
Age Time bit 15-8.
h3
Port0 VLAN Low Byte Register.
Port0 VLAN Low Byte Register.
Port1 VLAN Low Byte Register.
Port1 VLAN Low Byte Register.
Port2 VLAN Low Byte Register.
h4
h5
h6
h7
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EEPROM Content
Addr
h8
Name
Descriptions
VLAN2H
VLAN3L
VLAN3H
VLAN4L
VLAN4H
VLAN5L
VLAN5H
VLAN6L
VLAN6H
VLAN7L
VLAN7H
VLAN8L
VLAN8H
VLAN9L
VLAN9H
VLAN10L
VLAN10H
VLAN11L
VLAN11H
VLAN12L
VLAN12H
VLAN13L
VLAN13H
VLAN14L
VLAN14H
VLAN15L
VLAN15H
Uplink0
Port2 VLAN Low Byte Register.
h9
Port3 VLAN Low Byte Register.
ha
Port3 VLAN Low Byte Register.
hb
Port4 VLAN Low Byte Register.
hc
Port4 VLAN Low Byte Register.
hd
Port5 VLAN Low Byte Register.
he
Port5 VLAN Low Byte Register.
hf
Port6 VLAN Low Byte Register.
h10
h11
h12
h13
h14
h15
h16
h17
h18
h19
h1a
h1b
h1c
h1d
h1e
h1f
h20
h21
h22
h23
h24
h25
h26
h27
h28
h29
h2a
h2b
h2c
h2d
h2e
h2f
h30
h31
h32
Port6 VLAN Low Byte Register.
Port7 VLAN Low Byte Register.
Port7 VLAN Low Byte Register.
Port8 VLAN Low Byte Register.
Port8 VLAN Low Byte Register.
Port9 VLAN Low Byte Register.
Port9 VLAN Low Byte Register.
Port10 VLAN Low Byte Register.
Port10 VLAN Low Byte Register.
Port11 VLAN Low Byte Register.
Port11 VLAN Low Byte Register.
Port12 VLAN Low Byte Register.
Port12 VLAN Low Byte Register.
Port13 VLAN Low Byte Register.
Port13 VLAN Low Byte Register.
Port14 VLAN Low Byte Register.
Port14 VLAN Low Byte Register.
Port15 VLAN Low Byte Register.
Port15 VLAN Low Byte Register.
[4:0] Port 0 flooding port. [7:5] Reserved.
[4:0] Port 1 flooding port. [7:5] Reserved.
[4:0] Port 2 flooding port. [7:5] Reserved.
[4:0] Port 3 flooding port. [7:5] Reserved.
[4:0] Port 4 flooding port. [7:5] Reserved.
[4:0] Port 5 flooding port. [7:5] Reserved.
[4:0] Port 6 flooding port. [7:5] Reserved.
[4:0] Port 7 flooding port. [7:5] Reserved.
[4:0] Port 8 flooding port. [7:5] Reserved.
[4:0] Port 9 flooding port. [7:5] Reserved.
[4:0] Port 10 flooding port. [7:5] Reserved.
[4:0] Port 11 flooding port. [7:5] Reserved.
[4:0] Port 12 flooding port. [7:5] Reserved.
[4:0] Port 13 flooding port. [7:5] Reserved.
[4:0] Port 14 flooding port. [7:5] Reserved.
[4:0] Port 15 flooding port. [7:5] Reserved.
Uplink1
Uplink2
Uplink3
Uplink4
Uplink5
Uplink6
Uplink7
Uplink8
Uplink9
Uplink10
Uplink11
Uplink12
Uplink13
Uplink14
Uplink15
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EEPROM Content
Addr
h33
h34
h35
h36
h37
h38
Name
Descriptions
BrdcastTH
XONTh
Broadcast Threshold
XON Threshold
XOFF Threshold
Disable Port 7-0
Disable Port 15-8
XOFFTH
DisPortL
DisPortH
System control byte bit0-- Enhance Backpressure Enable
CtrlEnable
[7:1] Reserved.
Reserved
h39-
h3f
h40-
h46
45[7:0]~40[7:0] means Static SA[47:0],
StaticSA1
StaticSA2
46[3:0] means Port ID, 46[7:4] Reserved.
4c[7:0]~47[7:0] means Static SA[47:0],
h47-
h4d
47[3:0] means Port ID, 47[7:4] Reserved.
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7.0 Electrical Characteristics
7.1 Absolute Maximum Ratings
Symbol
Parameter
Power Supply Voltage
Input Voltage
RATING
-0.3 to 3.6
Unit
V
VCC
VIN
-0.3 to Vcc+0.3
-0.3 to Vcc+0.3
-55 to 150
V
VOUT
TSTG
Output Voltage
V
oC
Storage Temperature
7.2 Recommended Operating Conditions
Symbol
Parameter
Min.
3.0
0
Typ.
3.3
-
Max.
3.6
Unit
V
VCC
Power Supply
Input Voltage
VIN
Vcc
115
V
oC
oC
Commercial Junction Operating Temperature
Industrial Junction Operating Temperature
0
25
Tj
-40
25
125
7.3 DC Electrical Characteristics
Symbol
Parameter
Input Leakage Current
Tri-state Leakage Current
Input Capacitance
Conditions
Min.
Typ.
Max.
Unit
uA
uA
pF
pF
pF
V
IIL
no pull-up or down
-1
-1
1
1
IOZ
CIN
2.8
COUT
CBID3
VIL
Output Capacitance
2.7
2.7
4.9
4.9
Bi-direction buffer Capacitance
Input Low Voltage
CMOS
0.3*Vcc
VIH
Input High Voltage
CMOS
0.7*Vcc
2.4
V
VOH
VOL
RI
IOL=2,4,8,12,16,24mA
IOH=2,4,8,12,16,24mA
VIL=0V or VIH=VCC
Output High Voltage
Output Low Voltage
0.4
V
V
Input Pull-up/down resistance
75
KOhm
(Under recommended operating conditions and Vcc = 3.0 ~ 3.6V, Tj = 0 to +115 oC)
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7.4 Electrical Characteristics
FIGURE 1. RMII timing
T1
REFCLK
T2
T4
CRSDV
RXD[1:0]
Valid
T3
TXEN
TXD[1:0]
Valid
Symbol
Parameter
RMII input setup time
RMII input hold time
RMII output setup time
RMII output hold time
Min.
Typ.
Max.
Unit
nS
Note
T1
T2
T3
T4
1
1
3
5
nS
nS
nS
FIGURE 2. Memory Write Timing
T5
MEMCLK
RASB
T6
T7
CASB
WEB
T8
T6 T7
T6
T7
AD[8:0]
Valid
Valid
T6 T7
DQ[63:0]
Valid
Symbol
Parameter
Memory clock cycle
Min.
Typ.
Max.
Unit
Note
T5
12
nS
Memory command/address/data
setup time
T6
6
2
nS
Memory command/address/data
hold time
T7
T8
nS
Row active to burst write
2
CLK
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FIGURE 3. Memory Read Timing
T5
MEMCLK
RASB
T6
T7
CASB
WEB
T8
T6 T7
Valid
T6
T7
AD[8:0]
Valid
T9
T10
DQ[63:0]
Valid
Symbol
Parameter
Min.
Typ.
Max.
Unit
nS
Note
T10
T11
Memory read data setup time
Memory ead data hold time
2
2
nS
FIGURE 4. EEPROM timing
T11
EECLK
T13
T12
EEDATA
Valid
Symbol
T11
Parameter
EEPROM clock cycle
Min.
Typ.
Max.
Unit
uS
Note
10
T12
EEDATA input setup time
EEDATA input hold time
1
1
nS
T13
nS
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FIGURE 5. LED Interface
T14
LEDCLK
T16
Valid
T15
LEDDATA
Valid
Valid
Symbol
T14
Parameter
Min.
Typ.
Max.
Unit
uS
Note
Led display strobe period
LEDCLK setup time
LEDCLK hold time
20
5
T15
uS
T16
5
uS
26/27
MTD516 Revision 1.2 19/06/2000
MYSON
MTD516
TECHNOLOGY
(Preliminary)
8.0 208 pin PQFP Package Data
A
D
Dimension in mm
Dimension in inch
Sym-
bol
A1
A2
D1
D2
Min
Norm
Max
Min
Norm
Max
-|0.05 s
A
-
-
4.10
-
-
-
-
0.161
-
A1
A2
D
0.25
3.20
-
0.010
157
208
3.32
3.60
0.126 0.131 0.142
1.205 BSC
1.102 BSC
1.004
156
30.60 BSC
28.00 BSC
25.50
1
D1
D2
E
30.60 BSC
28.00 BSC
25.50
12.05 BSC
1.102 BSC
1.004
E1
E2
R2
R1
0.08
0.08
-
0.25
-
0.003
0.003
-
-
0.010
-
-
o
o
o
o
o
o
0
3.5
7
0
3.5
-
7
o
o
-
-
-
1
2
0
0
o
o
o
8
8
REF
REF
8
8
REF
REF
o
3
c
0.09
0.45
0.15
0.60
0.20
0.75
0.004 0.006 0.008
0.018 0.024 0.030
0.052 REF
L
L1
S
1.30 REF
-
-
-
0.20
0.17
0.008
-
e
0.50 BSC
0.20
0.020 BSC
L1
105
52
b
0.27
0.007 0.008 0.011
C
2
aaa|C|A-B|O
bbb|H|A-B|O
O|ddd M |C|A-B s |D s
53
1
4x
104
R1
R2
e
b
GAGE PLANE
-C-
SEATING PLANE
0.25mm
|ccc|C
L
See Detail A
Seating Plane
3
S
y
Detail
27/27
MTD516 Revision 1.2 19/06/2000
相关型号：
MTD56
+3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHz
NSC
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