MX7841 [ETC]
Octal. 14-Bit Voltage-Output DAC with Parallel Interface ; 八。 14位电压输出DAC ，并行接口\n
| 型号： | MX7841 |
| 厂家： | 
ETC |
| 描述： | Octal. 14-Bit Voltage-Output DAC with Parallel Interface
|
| 文件： | 总14页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2953; Rev 0; 7/03
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
General Description
Features
The MX7841 contains eight 14-bit, voltage-output digi-
tal-to-analog converters (DACs). On-chip precision out-
put amplifiers provide the voltage outputs. The device
operates from 1ꢀ5 supplies. ꢁts bipolar output voltage
o Full 14-Bit Performance Without Adjustments
o Eight DACs in a Single Package
o Buffered Voltage Outputs
swing ranges from (5 + 2.ꢀ5) to (5
- 2.ꢀ5) and is
DD
SS
o Unipolar or Bipolar Voltage Swing of (V + 2.5V)
SS
achieved with no external components. The MX7841
has three pairs of differential reference inputs; two of
these pairs are connected to two DACs each, and a
third pair is connected to four DACs. The references
are independently controlled, providing different full-
scale output voltages to the respective DACs.
to (V
- 2.5V)
DD
o 31µs Output Settling Time
o Low Power Consumption: 8mA (typ)
o Small 44-Pin MQFP Package
o Double-Buffered Digital Inputs
The MX7841 features double-buffered interface logic
with a 14-bit parallel data bus. Each DAC has an input
latch and a DAC latch. Data in the DAC latch sets the
output voltage. The eight input latches are addressed
with three address lines. Data is loaded to the input
latch with a single write instruction. An asynchronous
load input (LDAC) transfers data from the input latch to
the DAC latch. The LDAC input controls all DACs;
therefore, all DACs can be updated simultaneously by
asserting LDAC.
o Asynchronous Load Updates All DACs
Simultaneously
o Asynchronous CLR Forces All DACs to
DUTGND_ _ Potential
Ordering Information
An asynchronous CLR input sets the output of all eight
DACs to the respective DUTGND input of the op amp.
Note that CLR is a CMOS input, which is powered by
PIN-
PACKAGE
INL
(LSB)
PART
TEMP RANGE
5 . All other logic inputs are TTL/CMOS compatible.
DD
MX7841BS
MX7841AS
-40°C to +8ꢀ°C
-40°C to +8ꢀ°C
44 MQFP
44 MQFP
2
4
The MX7841 is pin-for-pin compatible with AD7841.
Pin Configuration
Applications
Automatic Test Equipment (ATE)
ꢁndustrial Process Controls
TOP VIEW
Arbitrary Function Generators
Avionics Equipment
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
SONET Applications
DUTGNDAB
OUTA
1
33 DUTGNDGH
32 OUTH
2
3
4
5
6
7
8
9
REFAB-
REFAB+
31 REFGH-
30 REFGH+
29 CLR
V
DD
V
SS
28 DB13
MX7841
LDAC
A2
27 DB12
26 DB11
25 DB10
24 DB9
23 DB8
A1
A0 10
CS 11
Functional Diagram appears at end of data sheet.
MQFP
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
ABSOLUTE MAXIMUM RATINGS
5
5
5
to GND ...........................................................-0.35 to +175
to GND ........................................................... -175 to +0.35
to GND ............................................................ -0.35 to +65
Maximum Current into Any Signal Pin .............................. ꢀ0mA
OUT_ Short-Circuit Duration to 5 , 5 , and GND ................1s
DD
SS
CC
DD SS
Continuous Power Dissipation (T = +70°C)
A
A_, DB_, WR, CS, LDAC, CLR to GND .....+0.35 to (5
REF_ _ _ _+, REF_ _ _ _-,
+ 0.35)
44-Pin MQFP (derate 11.1mW/°C above +70°C).........870mW
Operating Temperature Range ...........................-40°C to +8ꢀ°C
Junction Temperature......................................................+1ꢀ0°C
Storage Temperature Range.............................-6ꢀ°C to +1ꢀ0°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
DUTGND_ _ .................................(5 - 0.35) to (5
+ 0.35)
SS
DD
OUT_ ..........................................................................5
Maximum Current into REF_ _ _ _ _, DUTGND_ _ ........... 10mA
to 5
SS
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(5
= +1ꢀ5 10ꢂ, 5 = -1ꢀ5 10ꢂ, 5
= +ꢀ5 ꢀꢂ, 5
= 5
= 0, 5
_ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, R = ꢀkΩ,
REF REF L
DD
SS
to T
CC
GND
DUTGND_ _
C = ꢀ0pF, T = T
, unless otherwise noted. Typical values are at T = +2ꢀ°C.)
L
A
MꢁN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (ANALOG SECTION)
Resolution
N
14
Bits
MX7841BS
MX7841AS
2
4
1
8
8
Relative Accuracy
ꢁNL
DNL
LSB
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Guaranteed monotonic
LSB
LSB
LSB
LSB
2
2
2
ppm
FSR/°C
Gain Temperature Coefficient
(Note 1)
(Note 1)
0.ꢀ
7ꢀ
10
DC Crosstalk
120
µ5
REFERENCE INPUTS
ꢁnput Resistance
100
MΩ
µA
5
ꢁnput Current
1
ꢀ
REF_ _ _ _+ ꢁnput Range
REF_ _ _ _- ꢁnput Range
0
-ꢀ
0
5
(REF_ _ _ _+) - (REF_ _ _ _-)
Range
2
10
5
A
NALOG OUTPUTS
(5 + 2.ꢀ) to
(5 - 2.ꢀ)
DD
SS
Output 5oltage Swing
5
Resistive Load to GND
Capacitive Load to GND
DC Output ꢁmpedance
ꢀ
kΩ
pF
Ω
ꢀ0
(Note 1)
0.ꢀ
2
_______________________________________________________________________________________
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(5
= +1ꢀ5 10ꢂ, 5 = -1ꢀ5 10ꢂ, 5
= +ꢀ5 ꢀꢂ, 5
= 5
= 0, 5
_ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, R = ꢀkΩ,
REF REF L
DD
SS
to T
CC
GND
DUTGND_ _
C = ꢀ0pF, T = T
, unless otherwise noted. Typical values are at T = +2ꢀ°C.)
L
A
MꢁN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DUTGND_ _ CHARACTERISTICS
ꢁnput ꢁmpedance per DAC
Maximum ꢁnput Current per DAC
ꢁnput Range
60
kΩ
µA
5
300
-2
+2
DIGITAL INPUTS
ꢁnput 5oltage High
5
2.4
5
5
ꢁH
ꢁnput 5oltage Low
5
0.8
10
10
ꢁL
ꢁnput Capacitance
C
(Note 1)
pF
µA
ꢁN
ꢁnput Current
ꢁ
ꢁN
Digital inputs = 05 or 5
1
CC
POWER SUPPLIES
5
Analog Power-Supply
DD
5
13.ꢀ
16.ꢀ
5
5
DD
Range
5
SS
Analog Power-Supply
5
-16.7ꢀ
4.7ꢀ
-13.ꢀ
SS
Range
5
CC
Digital Power Supply
5
CC
ꢀ.2ꢀ
10
5
Positive Supply Current
Negative Supply Current
Digital Supply Current
ꢁ
R = ∞
8
8
mA
mA
mA
dB
dB
DD
L
ꢁ
SS
R = ∞
L
10
ꢁ
(Note 2)
0.ꢀ
CC
PSRR, ∆5
PSRR, ∆5
/ ∆5
/ ∆5
5
DD
5
SS
= +1ꢀ5 ꢀꢂ
= -1ꢀ5 ꢀꢂ
90
90
OUT
OUT
DD
SS
INTERFACE TIMING CHARACTERISTICS
(5
= +1ꢀ5 10ꢂ, 5 = -1ꢀ5 10ꢂ, 5
= +ꢀ5 ꢀꢂ, 5
= 5
= 0, 5
_ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, Figure 2a,
REF REF
DD
SS
CC
GND
DUTGND_ _
T
A
= T
to T
, unless otherwise noted.)
MꢁN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
ꢀ0
ꢀ0
ꢀ0
0
TYP
MAX
UNITS
ns
t
1
CS Pulse Width Low
t
2
ns
WR Pulse Width Low
t
3
ns
LDAC Pulse Width Low
CS Low to WR Low
t
4
ns
t
ꢀ
0
ns
CS High to WR High
t
20
0
ns
Data 5alid to WR Setup
Data 5alid to WR Hold
Address 5alid to WR Setup
Address 5alid to WR Hold
CLR Pulse-Activation Time
6
t
7
ns
t
8
1ꢀ
0
ns
t
9
ns
t
10
(Figure 2b)
300
ns
_______________________________________________________________________________________
3
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
DYNAMIC CHARACTERISTICS
(5
= +1ꢀ5 10ꢂ, 5 = -1ꢀ5 10ꢂ, 5
= +ꢀ5 ꢀꢂ, 5
= 5
= 0, 5
_ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, R = ꢀkΩ,
REF REF L
DD
SS
to T
CC
GND
DUTGND_ _
C = ꢀ0pF, T = T
, unless otherwise noted. Typical values are at T = +2ꢀ°C.)
L
A
MꢁN
MAX A
PARAMETER
SYMBOL
CONDITIONS
To 0.ꢀ LSB of full scale
MIN
TYP
MAX
UNITS
µs
Output Settling Time
Output Slew Rate
Digital Feedthrough
Digital Crosstalk
31
0.7
0.1
0.2
230
40
5/µs
n5-s
n5-s
n5-s
n5-s
dB
(Note 3)
(Note 4)
Digital-to-Analog Glitch ꢁmpulse
DAC-to-DAC Crosstalk
Channel-to-Channel ꢁsolation
Output Noise Spectral Density
99
5
REF+
= 5
= 0
200
n5/√Hz
REF-
Note 1: Guaranteed by design. Not production tested.
Note 2: All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at GND or 5
potential.
CC
Note 3: All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at +0.85 or +2.45.
Note 4: All digital inputs (DB0 to DB13) transition from GND to 5
with WR = 5
CC
CC
Typical Operating Characteristics
(5
= +1ꢀ5 10ꢂ, 5 = -1ꢀ5 10ꢂ, 5
= +ꢀ5 ꢀꢂ, 5
= 5
= 0, 5
_ _ _ _+ = +ꢀ5, 5
_ _ _ _- = -ꢀ5, T =
DD
SS
CC
GND
DUTGND_ _
REF
REF A
+2ꢀ°C, unless otherwise noted.)
INL AND DNL ERROR
vs. TEMPERATURE
INL vs. CODE
DNL vs. CODE
0.4
0.3
0.2
0.1
0
0.500
0.500
0.400
0.300
0.200
0.100
0
0.400
0.300
0.200
0.100
0
INL
-0.100
-0.200
-0.300
-0.400
-0.500
-0.100
-0.200
-0.300
-0.400
-0.500
-0.1
-0.2
-0.3
-0.4
DNL
-40
-20
0
20
40
60
80
0
2048 4096 6144 8192 10240 12288 14336 16384
CODE
0
2048 4096 6144 8192 10240 12288 14336 16384
CODE
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
Typical Operating Characteristics (continued)
(5
= +1ꢀ5 10ꢂ, 5 = -1ꢀ5 10ꢂ, 5
= +ꢀ5 ꢀꢂ, 5
= 5
= 0, 5
_ _ _ _+ = +ꢀ5, 5
_ _ _ _- = -ꢀ5, T
=
DD
SS
CC
GND
DUTGND_ _
REF
REF
A
+2ꢀ°C, unless otherwise noted.)
ZERO-SCALE AND FULL-SCALE ERROR
I
AND I
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
DD
SS
vs. TEMPERATURE
vs. TEMPERATURE
1.2
8.0
7.5
7.0
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
1.0
0.8
I
DD
0.6
FULL SCALE
I
SS
0.4
0.2
6.5
6.0
5.5
5.0
0
ZERO SCALE
-0.2
-0.4
-0.6
-0.8
-40
-20
0
20
40
60
80
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SETTLING TIME
vs. CAPACITIVE LOAD
LARGE-SIGNAL STEP RESPONSE
REFERENCE INPUT FREQUENCY RESPONSE
5
100
90
80
70
60
50
40
30
20
10
0
REF_ _ _ _ _ = 200mVp-p
0
LDAC
-5
5V/div
-10
-15
-20
-25
-30
-35
-40
OUT_
5V/div
10µs/div
1k
10k
100k
1M
10M
10
100
1000
10,000
100,000
FREQUENCY (Hz)
CAPACITIVE LOAD (pF)
NOISE VOLTAGE DENSITY
vs. FREQUENCY
NEGATIVE SETTLING TIME
POSITIVE SETTLING TIME
1000
LDAC
5V/div
LDAC
5V/div
OUT_
1mV/div
OUT_
1mV/div
100
10
100
1k
10k
10µs/div
10µs/div
FREQUENCY (Hz)
_______________________________________________________________________________________
5
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
Typical Operating Characteristics (continued)
(5
= +1ꢀ5 10ꢂ, 5 = -1ꢀ5 10ꢂ, 5
= +ꢀ5 ꢀꢂ, 5
= 5
= 0, 5
_ _ _ _+ = +ꢀ5, 5
_ _ _ _- = -ꢀ5, T =
DD
SS
CC
GND
DUTGND_ _
REF
REF
A
10
10
+2ꢀ°C, unless otherwise noted.)
GAIN ERROR vs. V
MAJOR CARRY GLITCH IMPULSE
(0xFFFF–0x10000)
MAJOR CARRY GLITCH IMPULSE
REF
(V
- V
)
(0x1000–0xFFF)
REF+
REF-
MX7841 toc14
MX7841 toc13
1.1
0.9
LDAC
LDAC
5V/div
5V/div
0.7
0.5
0.3
OUT
OUT
5mV/div
0.1
5mV/div
-0.1
-0.3
-0.5
0
2
4
6
8
2µs/div
2µs/div
V
REF
(V)
DNL (MAX, MIN)
ZERO-SCALE ERROR
FULL-SCALE ERROR
vs. V
(V
- V
)
vs. V
(V
- V
)
vs. V
(V
- V
)
REF REF+
REF-
REF REF+
REF-
REF REF+
REF-
0.4
0.3
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
2
4
6
8
10
0
2
4
6
8
10
0
2
4
6
8
V
REF
(V)
V
REF
(V)
V
REF
(V)
INL (MAX, MIN)
SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
vs. V
(V
- V
)
REF REF+
REF-
0.5
0.4
30
20
10
0
0.3
ZERO-SCALE OUTPUT,
SINKING CURRENT
0.2
0.1
0
-10
-0.1
-0.2
-0.3
-0.4
-0.5
FULL-SCALE OUTPUT,
SOURCING CURRENT
-20
-30
-40
0
2
4
6
8
10
-40 -25 -10
5
20 35 50 65 80
°
TEMPERATURE ( C)
V
REF
(V)
6
_______________________________________________________________________________________
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
Pin Description
PIN
NAME
FUNCTION
Device Sense Ground ꢁnput for OUTA and OUTB. ꢁn normal operation, OUTA and OUTB are referenced
to DUTGNDAB. When CLR is low, OUTA and OUTB are forced to the potential on DUTGNDAB.
1
DUTGNDAB
2
3
4
OUTA
REFAB-
REFAB+
DAC A Buffered Output 5oltage
Negative Reference ꢁnput for DACs A and B
Positive Reference ꢁnput for DACs A and B
Positive Analog Power Supply. Normally set to +1ꢀ5. Connect both pins to the supply voltage. See the
Power Supplies, Grounding, and Bypassing section for bypass requirements.
ꢀ, 38
6
5
DD
Negative Analog Power Supply. Normally set to -1ꢀ5. See the Power Supplies, Grounding, and
Bypassing section for bypass requirements.
5
SS
Load ꢁnput. Drive this asynchronous input low to transfer the contents of the input latches to their
7
LDAC
respective DAC latches. DAC latches are transparent when LDAC is low and latched when LDAC is
high.
8
9
A2
A1
A0
CS
Address Bit 2 (MSB)
Address Bit 1
10
11
Address Bit 0 (LSB)
Chip Select. Active-low input.
Write ꢁnput. Active-low strobe for conventional memory write sequence. ꢁnput data latches are transpar-
ent when WR and CS are both low. WR latches data into the DAC input latch selected by A2, A1, A0 on
the rising edge of CS.
12
13
WR
Digital Power Supply. Normally set to +ꢀ5. See the Power Supplies, Grounding, and Bypassing section
for bypass requirements.
5
CC
14
GND
Ground
1ꢀ–28
DB0–DB13
Data Bits 0–13. Offset binary coding.
Clear ꢁnput. Drive CLR low to force all DAC outputs to the voltage on their respective DUTGND _ _.
29
CLR
Does not affect the status of internal registers. All DACs return to their previous levels when CLR goes
high.
30
31
REFGH+
REFGH-
Positive Reference ꢁnput for DACs G and H
Negative Reference ꢁnput for DACs G and H
_______________________________________________________________________________________
7
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
Pin Description (continued)
PIN
NAME
FUNCTION
32
OUTH
DAC H Buffered Output 5oltage
Device Sense Ground ꢁnput for OUTG and OUTH. ꢁn normal operation, OUTG and OUTH are referenced
to DUTGNDGH. When CLR is low, OUTG and OUTH are forced to the potential on DUTGNDGH.
33
DUTGNDGH
34
3ꢀ
OUTG
OUTF
DAC G Buffered Output 5oltage
DAC F Buffered Output 5oltage
Device Sense Ground ꢁnput for OUTE and OUTF. ꢁn normal operation, OUTE and OUTF are referenced
to DUTGNDEF. When CLR is low, OUTE and OUTF are forced to the potential on DUTGNDEF.
36
DUTGNDEF
37
39
40
41
OUTE
REFCDEF+
REFCDEF-
OUTD
DAC E Buffered Output 5oltage
Positive Reference ꢁnput for DACs C, D, E, and F
Negative Reference ꢁnput for DACs C, D, E, and F
DAC D Buffered Output 5oltage
Device Sense Ground ꢁnput for OUTC and OUTD. ꢁn normal operation, OUTC and OUTD are referenced
to DUTGNDCD. When CLR is low, OUTC and OUTD are forced to the potential on DUTGNDCD.
42
DUTGNDCD
43
44
OUTC
OUTB
DAC C Buffered Output 5oltage
DAC B Buffered Output 5oltage
8
_______________________________________________________________________________________
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
_______________Detailed Description
CLR
Analog Section
R
R
The MX7841 contains eight 14-bit voltage-output DACs.
OUT
These DACs are inverted R-2R ladder networks that
convert 14-bit digital inputs into equivalent analog out-
2R
2R
2R
2R
2R
2R
put voltages, in proportion to the applied reference volt-
ages (Figure 1). The MX7841 has three positive
reference inputs (REF_ _ _ _+) and three negative refer-
ence inputs (REF_ _ _ _-). The difference from
REF_ _ _ _+ to REF_ _ _ _-, multiplied by two, sets the
DAC output span.
D0
D12
D13
DUTGND
REF-
REF+
ꢁn addition to the differential reference inputs, the
MX7841 has four analog-ground input pins
(DUTGND_ _). When CLR is high (unasserted), the volt-
age on DUTGND_ _ offsets the DAC output voltage
range. ꢁf CLR is asserted, the output amplifier is forced
to the voltage present on DUTGND_ _.
Figure 1. DAC Simplified Circuit
Reference and DUTGND Inputs
All of the MX7841’s reference inputs are buffered with
precision amplifiers. This allows the flexibility of using
resistive dividers to set the reference voltages. Because
of the relatively high multiplying bandwidth of the refer-
ence input (188kHz), any signal present on the reference
pin within this bandwidth is replicated on the DAC output.
t
1
CS
WR
t
4
t
5
The DUTGND pins of the MX7841 are connected to the
negative source resistor (nominally 11ꢀkΩ) of the out-
put amplifier. The DUTGND pins are typically connect-
ed directly to analog ground. Each of these pins has an
input current that varies with the DAC digital code. ꢁf
the DUTGND pins are driven by external circuitry, bud-
get 200µA per DAC for load current.
t
2
t
8
t
9
A0–A2
Output-Buffer Amplifiers
The MX7841’s voltage outputs are internally buffered by
precision gain-of-two amplifiers with a typical slew rate
of 15/µs. With a full-scale transition at its output, the
typical settling time to 1/2 LSB is 31µs. This settling
time does not significantly vary with capacitive loads
less than 10,000pF.
t
6
t
7
DB0–DB13
t
t
3
(NOTE 3)
3
Output Deglitching Circuit
The MX7841’s internal connection from the DAC ladder
to the output amplifier contains special deglitch circuitry.
LDAC
NOTES:
1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF
+5V. t = t = 5ns.
CLR
r
f
2. MEASUREMENT REFERENCE LEVEL IS (V + V ) / 2.
INH
INL
3. IF LDAC IS ACTIVATED WHILE WR IS LOW, THEN LDAC MUST STAY LOW
V
OUT_
FOR t OR LONGER AFTER WR GOES HIGH.
3
t
10
t
10
Figure 2b. Digital Timing Diagram
Figure 2a. Digital Timing Diagram
_______________________________________________________________________________________
9
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
This glitch/deglitch circuitry is enabled on the falling
edge of LDAC to remove the glitch from the R-2R DAC.
This enables the MX7841 to exhibit a fraction of the glitch
impulse energy of parts without the deglitching circuit.
instantly. Transfer data from the input latches to the
DAC latches by asserting the asynchronous LDAC sig-
nal. Each DAC’s analog output reflects the data held in
its DAC latch. All control inputs are level triggered.
Table 2 is an interface truth table.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and
CMOS logic. The MX7841 interfaces with microproces-
sors using a data bus at least 14 bits wide. The inter-
face is double buffered, allowing simultaneous
updating of all DACs. There are two latches for each
DAC (see the Functional Diagram): an input latch that
receives data from the data bus, and a DAC latch that
receives data from the input latch. Address lines A0,
A1, and A2 select which DAC’s input latch receives
data from the data bus as shown in Table 1. Both the
input latches and the DAC latches are transparent
when CS, WR, and LDAC are all low. Any change of
DB0–DB13 during this condition appears at the output
Input Write Cycle
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch, and LDAC transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low,
and the DAC latch is transparent when LDAC is low.
The address lines (A0, A1, A2) must be valid for the
duration that CS and WR are low (Figure 2a) to prevent
data from being inadvertently written to the wrong DAC.
Data is latched within the input latch when either CS or
WR is high.
Loading the DACs
Taking LDAC high latches data into the DAC latches. ꢁf
LDAC is brought low when WR and CS are low, the
DAC addressed by A0, A1, and A2 is directly con-
trolled by the data on DB0–DB13. This allows the maxi-
mum digital update rate; however, it is sensitive to any
glitches or skew in the input data stream.
Table 1. MX7841 DAC Addressing
A2
A1
A0
FUNCTION
0
0
0
DAC A input latch
DAC B input latch
DAC C input latch
DAC D input latch
DAC E input latch
DAC F input latch
DAC G input latch
DAC H input latch
0
0
1
Asynchronous Clear
The MX7841 has an asynchronous clear pin (CLR) that,
when asserted, sets all DAC outputs to the voltage pre-
sent on their respective DUTGND pins. Deassert CLR to
return the DAC output to its previous voltage. Note that
CLR does not clear any of the internal digital registers.
See Figure 2b.
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Applications Information
Multiplying Operation
The MX7841 can be used for multiplying applications.
ꢁts reference accepts both DC and AC signals. Since
the reference inputs are unipolar, multiplying operation
is limited to two quadrants. See the graphs in the
Typical Operating Characteristics for dynamic perfor-
mance of the DACs and output buffers.
Table 2. Interface Truth Table
FUNCTION
CLR
X
LD
X
WR
0
CS
0
ꢁnput register transparent
ꢁnput register latched
ꢁnput register latched
DAC register transparent
DAC register latched
X
X
X
1
X
X
1
X
Digital Code and
Analog Output Voltage
X
0
X
X
X
1
X
X
The MX7841 uses offset binary coding. A 14-bit two’s
complement code is converted to a 14-bit offset binary
Outputs of DACs at
DUTGND_ _
0
1
X
1
X
X
X
X
13
code by adding 2 = 8192.
Outputs of DACs set to volt-
age defined by the DAC
register, the references,
and the corresponding
DUTGND_ _
Output Voltage Range
For typical operation, connect DUTGND to signal ground,
5
+ to +ꢀ5, and 5
- to -ꢀ5. Table 3 shows the rela-
REF
REF
tionship between digital code and output voltage.
X = Don’t care.
10 ______________________________________________________________________________________
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
mum performance, drive LDAC low after the inputs are
Table 3. Analog Voltage vs. Digital Code
either latched or steady state. This is best accom-
plished by having the falling edge of LDAC occur at
least ꢀ0ns after the rising edge of CS.
OUTPUT
INPUT CODE
VOLTAGE (V)
11 1111 1111 1111
10 0000 0000 0000
01 0011 1011 0010
00 0000 0000 0001
00 0000 0000 0000
+9.998779
0
Power Supplies, Grounding,
and Bypassing
For optimum performance, use a multilayer PC board
with an unbroken analog ground. For normal operation,
connect the four DUTGND pins directly to the ground
plane. Avoid sharing the connections of these sensitive
pins with other ground traces.
-3.845215
-9.998779
-10
Note: Output voltage is based on REF+ = +5V, REF- = -5V, and
DUTGND = 0.
As with any sensitive data-acquisition system, connect
the digital and analog ground planes together at a sin-
gle point, preferably directly underneath the MX7841.
Avoid routing digital signals underneath the MX7841 to
minimize their coupling into the ꢁC.
The DAC digital code controls each leg of the 14-bit
R-2R ladder. A code of 0x0 connects all legs of the lad-
der to REF-, corresponding to a DAC output voltage
(5
) equal to REF-. A code of 0x3FFF connects all
DAC
For normal operation, bypass 5
and 5 with 0.1µF
SS
DD
legs of the ladder to REF+, corresponding to a 5
DAC
ceramic chip capacitors to the analog ground plane. To
enhance transient response and capacitive drive capa-
bility, add 10µF tantalum capacitors in parallel with the
ceramic capacitors. Note, however, that the MX7841
does not require the additional capacitance for stability.
approximately equal to REF+.
The output amplifier multiplies 5
by 2, yielding an out-
DAC
✕
✕
put voltage range of 2 REF- to 2 REF+ (Figure 1).
Further manipulation of the output voltage span is accom-
plished by offsetting DUTGND. The output voltage of the
MX7841 is described by the following equation:
Bypass 5
with a 0.1µF ceramic chip capacitor to the
digital ground plane.
CC
Power-Supply Sequencing
To guarantee proper operation of the MX7841, ensure
that power is applied to 5 before 5 and 5 . Also
DATA
5
= 2 5
− 5
+ 5
REF−
(
)
OUT
REF+
REF−
14
2
DD
SS
CC
− 5
ensure that 5
is never more than 300m5 above
SS
DUTGND
ground. To prevent this situation, connect a Schottky
diode between 5 and the analog ground plane, as
where DATA is the numeric value of the DAC’s binary
input code, and DATA ranges from 0 to 16,383
(2 - 1). The resolution of the MX7841, defined as
1 LSB, is described by the following equation:
SS
shown in Figure 3. Do not power up the logic input pins
14
2 REF+ − REF−
(
)
LSB =
14
2
V
SS
V
SS
V
SS
Reference Selection
Because the MX7841 has precision buffers on its refer-
ence inputs, the requirements for interfacing to these
inputs are minimal. Select a low-drift, low-noise refer-
ence within the recommended REF+ and REF- voltage
ranges. The MX7841 does not require bypass capaci-
tors on its reference inputs. Add capacitors only if the
reference voltage source requires them to meet system
specifications.
MX7839
1N5817
GND
SYSTEM GND
Minimizing Output Glitch
The MX7841’s internal deglitch circuitry is enabled on
the falling edge of LDAC. Therefore, to achieve opti-
Figure 3. Schottky Diode Between V and GND
SS
______________________________________________________________________________________ 11
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
before establishing the supply voltages. If this is not
possible and the digital lines can drive more than
Chip Information
TRANSISTOR COUNT: 13,225
10mA, place current-limiting resistors (e.g., 470Ω) in
PROCESS: BiCMOS
series with the logic pins.
Driving Capacitive Loads
The MX7841 typically drives capacitive loads up to
0.01µF without a series output resistor. However, when-
ever driving high capacitive loads, it is prudent to use a
220Ω series resistor between the MX7841 output and
the capacitive load.
12 ______________________________________________________________________________________
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
Functional Diagram
REFAB-
REFAB+
REFCDEF-
REFCDEF+
REFGH-
REFGH+
______________________________________________________________________________________ 13
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
44L MQFP, 1.60 LEAD FORM
1
21-0826
D
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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