N79E352RADG [ETC]
IC MCU 8BIT 8KB FLASH 40DIP;
| 型号： | N79E352RADG |
| 厂家： | 
ETC |
| 描述： | IC MCU 8BIT 8KB FLASH 40DIP |
| 文件： | 总135页 (文件大小：2603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary N79E352/N79E352R Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
GENERAL DESCRIPTION.......................................................................................................... 4
FEATURES ................................................................................................................................. 5
PARTS INFORMATION LIST ..................................................................................................... 6
3.1
Lead Free (RoHS) Parts information list......................................................................... 6
4.
5.
6.
PIN CONFIGURATIONS............................................................................................................. 7
PIN DESCRIPTIONS .................................................................................................................. 9
FUNCTIONAL DESCRIPTION.................................................................................................. 11
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
On-Chip Flash EPROM................................................................................................. 11
I/O Ports........................................................................................................................ 11
Serial I/O ....................................................................................................................... 11
Timers........................................................................................................................... 11
Interrupts....................................................................................................................... 11
Data Pointers ................................................................................................................ 11
Architecture................................................................................................................... 11
Power Management...................................................................................................... 12
7.
MEMORY ORGANIZATION...................................................................................................... 13
7.1
7.2
7.3
Program Memory (on-chip Flash) ................................................................................. 13
Data Memory................................................................................................................. 14
Scratch-pad RAM and Register Map ............................................................................ 14
8.
9.
SPECIAL FUNCTION REGISTERS.......................................................................................... 17
8.1
8.2
SFR Location Table ...................................................................................................... 17
SFR Detail Bit Descriptions........................................................................................... 21
INSTRUCTION.......................................................................................................................... 51
9.1
9.2
9.3
9.4
Instruction Timing.......................................................................................................... 58
MOVX Instruction.......................................................................................................... 62
External Data Memory Access Timing.......................................................................... 63
Wait State Control Signal.............................................................................................. 66
10.
POWER MANAGEMENT.......................................................................................................... 67
10.1 Idle Mode ...................................................................................................................... 67
10.2 Economy Mode ............................................................................................................. 67
10.3 Power Down Mode........................................................................................................ 68
- 1 -
Preliminary N79E352/N79E352R Data Sheet
11.
12.
RESET CONDITIONS............................................................................................................... 69
11.1 Sources of reset............................................................................................................ 69
11.2 Reset State ................................................................................................................... 69
PROGRAMMABLE TIMERS/COUNTERS................................................................................ 71
12.1 Timer/Counters 0 & 1.................................................................................................... 71
12.2 Time-base Selection ..................................................................................................... 71
12.3 Timer/Counter 2............................................................................................................ 74
13.
NVM MEMORY ......................................................................................................................... 78
13.1 Operation ...................................................................................................................... 78
14.
15.
WATCHDOG TIMER................................................................................................................. 80
UART SERIAL PORT................................................................................................................ 82
15.1 Mode 0 .......................................................................................................................... 82
15.2 Mode 1 .......................................................................................................................... 83
15.3 Mode 2 .......................................................................................................................... 84
15.4 Mode 3 .......................................................................................................................... 87
15.5 Framing Error Detection................................................................................................ 88
15.6 Multiprocessor Communications................................................................................... 88
16.
I2C SERIAL PORT.................................................................................................................... 90
16.1 I2C Bus ......................................................................................................................... 90
16.2 The I2C Control Registers: ........................................................................................... 91
16.3 Modes of Operation ...................................................................................................... 93
16.4 Data Transfer Flow in Five Operating Modes ............................................................... 94
17.
18.
TIMED ACCESS PROTECTION............................................................................................. 100
INTERRUPTS ......................................................................................................................... 102
18.1 Interrupt Sources ........................................................................................................ 102
18.2 Priority Level Structure................................................................................................ 103
18.3 Interrupt Response Time ............................................................................................ 105
18.4 Interrupt Inputs............................................................................................................ 105
19.
20.
21.
22.
KEYBOARD FUNCTION......................................................................................................... 106
INPUT CAPTURE ................................................................................................................... 108
PULSE WIDTH MODULATED OUTPUTS (PWM) ................................................................. 110
I/O PORT................................................................................................................................. 111
22.1 Quasi-Bidirectional Output Configuration.................................................................... 111
22.2 Open Drain Output Configuration ............................................................................... 112
22.3 Push-Pull Output Configuration................................................................................... 113
22.4 Input Only Mode.......................................................................................................... 113
- 2 -
Preliminary N79E352/N79E352R Data Sheet
23.
24.
OSCILLATOR.......................................................................................................................... 115
23.1 On-Chip RC Oscillator Option..................................................................................... 115
23.2 External Clock Input Option ........................................................................................ 115
23.3 CPU Clock Rate select ............................................................................................... 116
POWER MONITORING .......................................................................................................... 117
24.1 Power On Detect......................................................................................................... 117
24.2 Brownout Detect and Reset ........................................................................................ 117
25.
26.
ICP(IN-CIRCUIT PROGRAM) FLASH PROGRAM................................................................. 119
CONFIG BITS ......................................................................................................................... 120
26.1 CONFIG0.................................................................................................................... 120
26.2 CONFIG1.................................................................................................................... 121
27.
ELECTRICAL CHARACTERISTICS....................................................................................... 123
27.1 Absolute Maximum Ratings ........................................................................................ 123
27.2 D.C. Characteristics.................................................................................................... 124
27.3 A.C. Characteristics .................................................................................................... 125
27.4 RC OSC AND AC CHARACTERISTICS .................................................................... 130
27.5 Typical Application Circuit........................................................................................... 130
28.
29.
PACKAGE DIMENSIONS ....................................................................................................... 131
28.1 40-pin DIP ................................................................................................................... 131
28.2 44-pin PLCC................................................................................................................ 132
28.3 44-pin PQFP ............................................................................................................... 133
28.4 48-pin LQFP................................................................................................................ 134
REVISION HISTORY .............................................................................................................. 135
Publication Release Date: Jul, 29, 2009
- 3 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
1. GENERAL DESCRIPTION
The N79E352(R) is an 8-bit Turbo 51 microcontroller which has Flash EPROM programmable
hardware writer. The instruction set of the N79E352(R) is fully compatible with the standard 8052. The
N79E352(R) contains a 8Kbytes of main Flash EPROM; a 256 bytes of RAM; 128 bytes NVM Data
Flash EPROM; three 16-bit timer/counters; 2-channel 8-bit PWM; 1-channel UART and 1 additional
input capture. These peripherals are supported by 11 interrupt sources four-level interrupt capability.
To facilitate programming and verification, the Flash EPROM inside the N79E352(R) allows the
program memory to be programmed and read electronically. Once the code is confirmed, the user can
protect the code for security. N79E352(R) is designed for cost effective applications which can serve
industrial devices, and other low power applications.
- 4 -
Preliminary N79E352/N79E352R Data Sheet
2. FEATURES
•
Fully static design 8-bit Turbo 51 CMOS microcontroller up to 24MHz when VDD=4.5V to 5.5V,
12MHz when VDD=2.7V to 5.5V, and 4MHz when VDD=2.4V to 5.5V.
•
•
•
•
•
8K bytes of AP Flash EPROM, with external writer programmable mode.
256 bytes of on-chip RAM.
128 bytes NVM Data Flash EPROM for customer data storage used and 10k writer cycles.
Instruction-set compatible with MCS-51.
On-chip configurable RC oscillator: 22.1184MHz/11.0592MHz (selectable by config bit) with ±2%
accuracy, at 5V voltage and 25°C condition. (±2% accuracy is only for N79E352R.)
•
•
•
•
Three 16-bit timer/counters.
One input capture.
11 interrupt source with four levels of priority.
One enhanced full duplex serial port with framing error detection and automatic address
recognition.
•
•
4 outputs mode and TTL/Schmitt trigger selectable Port.
Programmable Watchdog Timer with 20KHz internal RC clock can wake-up the power down
mode, and have very low power under 10uA at 5V.
•
•
•
•
•
•
•
•
•
Two-channel 8-bit PWM.
One I2C communication port.
Dual 16-bit Data Pointers.
Software programmable access cycle to external RAM/peripherals.
Eight keypads interrupt inputs with sharing the same interrupt source.
LED drive capability (20mA) on all port pins, total 100mA.
Low Voltage (3 levels) Detection interrupt and reset.
Industrial temperature grade -40oC~85oC.
Packages:
Lead Free (RoHS) DIP40: N79E352RADG
Lead Free (RoHS) PLCC44: N79E352RAPG
Lead Free (RoHS) PQFP44: N79E352RAFG
Lead Free (RoHS) LQFP48: N79E352RALG
Lead Free (RoHS) DIP40: N79E352ADG
Lead Free (RoHS) PLCC44: N79E352APG
Lead Free (RoHS) PQFP44: N79E352AFG
Lead Free (RoHS) LQFP48: N79E352ALG
-
Publication Release Date: Jul, 29, 2009
- 5 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
3. PARTS INFORMATION LIST
3.1 Lead Free (RoHS) Parts information list
INTERNAL RC
OSCILLATOR
ACCURACY1
EPROM
FLASH SIZE
NVM FLASH
EPROM
PART NO.
RAM
PACKAGE
DIP-40 Pin
N79E352RADG
N79E352RAPG
N79E352RAFG
N79E352RALG
8KB
8KB
8KB
8KB
256B
256B
256B
256B
128B
128B
128B
128B
22.1184MHz ± 2%
22.1184MHz ± 2%
22.1184MHz ± 2%
22.1184MHz ± 2%
PLCC-44 Pin
PQFP-44 Pin
LQFP-48 Pin
DIP-40 Pin
N79E352ADG
N79E352APG
N79E352AFG
N79E352ALG
8KB
8KB
8KB
8KB
256B
256B
256B
256B
128B
128B
128B
128B
22MHz ± 25%
22MHz ± 25%
22MHz ± 25%
22MHz ± 25%
PLCC-44 Pin
PQFP-44 Pin
LQFP-48 Pin
Table 3-1: Lead Free (RoHS) Parts information list
Note:
1. Factory calibration condition: VDD=5.0V±10%, TA = 25°C
- 6 -
Preliminary N79E352/N79E352R Data Sheet
4. PIN CONFIGURATIONS
T2, P1.0
T2EX, P1.1
SDA, P1.2
SCL, P1.3
PWM0, P1.4
PWM1, P1.5
P1.6
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
2
P0.0, AD0, KB0
P0.1, AD1, KB1
P0.2, AD2, KB2
P0.3, AD3, KB3
P0.4, AD4, KB4
P0.5, AD5, KB5
P0.6, AD6, KB6
P0.7, AD7, KB7
EA
3
4
5
6
7
P1.7
8
RST
9
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
10
11
12
13
14
15
16
17
18
19
20
ALE
PSEN
P2.7, A15
P2.6, A14
T1, P3.5
P2.5, A13
WR, P3.6
RD, P3.7
P2.4, A12
P2.3, A11
P2.2, A10
P5.0,XTAL2
P2.1, A9
P5.1,XTAL1
VSS
P2.0, A8
PWM1, P1.5
P1.6
7
8
9
39
P0.4, AD4, KB4
P0.5, AD5, KB5
P0.6, AD6, KB6
P0.7, AD7, KB7
EA
38
37
36
35
34
33
32
31
30
29
P1.7
RST
10
11
12
13
14
15
16
17
RXD, P3.0
P4.3
PLCC 44-pin
P4.1
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
Publication Release Date: Jul, 29, 2009
Revision A06
- 7 -
Preliminary N79E352/N79E352R Data Sheet
1
33
32
31
30
29
28
27
26
25
24
23
P0.4, AD4, KB4
P0.5, AD5, KB5
P0.6, AD6, KB6
P0.7, AD7, KB7
EA
PWM1, P1.5
P1.6
2
P1.7
RST
3
4
RXD, P3.0
P4.3
5
LQFP 44-pin
6
P4.1
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
7
ALE
8
PSEN
9
P2.7, A15
P2.6, A14
P2.5, A13
10
11
1
36
35
34
33
32
31
30
29
28
27
26
25
NC
PWM1, P1.5
P1.6
P1.7
2
P0.4, AD4, KB4
P0.5, AD5, KB5
P0.6, AD6, KB6
3
RST
4
P3.0
5
P0.7, AD7, KB7
EA
P4.3
6
LQFP 48-pin
P3.1
7
P4.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
NC
8
ALE
9
PSEN
10
11
12
P2.7, A15
P2.6, A14
P2.5, A13
- 8 -
Preliminary N79E352/N79E352R Data Sheet
5. PIN DESCRIPTIONS
SYMBOL
Alternate
Function 1
Alternate
function 2
Type
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the
processor to execute out of external ROM. It should
be kept high to access internal ROM. The ROM
address and data will not be present on the bus if
I
EA
EA
pin is high and the program counter is within
internal ROM area. Otherwise they will be present on
the bus.
PSEN
PROGRAM STORE ENABLE:
enables the
external ROM data onto the Port 0 address/data bus
during fetch and MOVC operations. When internal
O
PSEN
PSEN
ROM access is performed, no
outputs from this pin.
strobe signal
ADDRESS LATCH ENABLE: ALE is used to enable
the address latch that separates the address from
the data on Port 0.
ALE
O
XTAL1
P5.1
P5.0
I/O
CRYSTAL1: This is the crystal oscillator input. This
pin may be driven by an external clock or
configurable i/o pin, P5.1.
XTAL2
VDD
I/O
CRYSTAL2: This is the crystal oscillator output. It is
the inversion of XTAL1. Also a configurable i/o pin,
P5.0.
P
P
POWER SUPPLY: Supply voltage for operation.
GROUND: Ground potential.
VSS
RST
RESET: A high on this pin for two machine cycles
while the oscillator is running resets the device.
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
KB0
KB1
KB2
KB3
KB4
KB5
KB6
KB7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORT0:
Support 4 mode output and 2 mode input.
Multifunction pins for AD0-7and KB0-7.
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
T2
T2EX
SDA
SCL
PWM0
PWM1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORT1:
Support 4 mode output and 2 mode input.
Multifunction pins for SDA & SCL (I2C), T2, T2EX
and PWM0-1.
ICPDAT
ICPCLK
Publication Release Date: Jul, 29, 2009
- 9 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
A8
A9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PORT2:
A10
A11
A12
A13
A14
A15
RXD
TXD
/INT0
/INT1
T0
Support 4 mode output and 2 mode input.
Multifunction pins for A8-A15,.
PORT3:
Support 4 mode output and 2 mode input.
Multifunction pins for RXD & TXD (uart), /INT0,
/INT1, T0, T1, /WR and /RD.
T1
/WR
/RD
PORT4:
P4.1
P4.2
P4.3
I/O
I/O
I/O
Quasi output with internal pull up.
* Note: TYPE I: input, O: output, I/O: bi-directional.
In application if any pins need external pull-up, it is recommended to add a pull-up resistor
(10kΩ) between pin and power (VDD) instead of directly wiring pin to VDD for enhancing EMC.
- 10 -
Preliminary N79E352/N79E352R Data Sheet
6. FUNCTIONAL DESCRIPTION
N79E352(R) architecture consist of a 4T 8051 core controller surrounded by various registers, 8K
bytes Flash EPROM, 256 bytes of RAM, 128 bytes NVM Data Flash EPROM; three timer/counters,
one UART serial port, one I2C serial port, eight keyboard interrupt input, 2-channel PWM with 8-bit
counter and Flash EPROM program by Writer.
6.1 On-Chip Flash EPROM
N79E352(R) includes one 8K bytes of main Flash EPROM for application program which need Writer
to program the Flash EPROM.
6.2 I/O Ports
N79E352(R) has four 8-bit, one 4-bit port and one 2-bit port, with at least 36 I/O pins. All ports (except
port 4) can be used as four outputs mode when it may set by PxM1.y and PxM2.y registers, it has
strong pull-ups and pull-downs, and does not need any external pull-ups. Otherwise it can be used as
general I/O port as open drain circuit. All ports can be used bi-directional and these are as I/O ports.
These ports are not true I/O, but rather are pseudo-I/O ports. This is because these ports have strong
pull-downs and weak pull-ups.
6.3 Serial I/O
N79E352(R) has one UART serial port that is functionally similar to the serial port of the original 8052
family. However the serial port on N79E352(R) can operate in different modes in order to obtain timing
similarity as well. The Serial port has the enhanced features of Automatic Address recognition and
Frame Error detection.
6.4 Timers
The device has total three 16-bit timers; two 16-bit timers that have functions similar to the timers of
the 8052 family, and third timer is capable to function as timer and also provide capture support. When
used as timers, user has a choice to set 12 or 4 clocks per count that emulates the timing of the
original 8052. Each timer’s count value is stored in two SFR locations that can be written or read by
software. There are also some other SFRs associated with the timers that control their mode and
operation.
6.5 Interrupts
The Interrupt structure in N79E352(R) is slightly different from that of the standard 8052. Due to the
presence of additional features and peripherals, the number of interrupt sources and vectors has been
increased.
6.6 Data Pointers
The original 8052 had only one 16-bit Data Pointer (DPL, DPH). In the N79E352(R), there is an
additional 16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which
were unused in the original 8052. In addition there is an added instruction, DEC DPTR (op-code A5H),
which helps in improving programming flexibility for the user.
6.7 Architecture
N79E352(R) is based on the standard 8052 device. It is built around an 8-bit ALU that uses internal
registers for temporary storage and control of the peripheral devices. It can execute the standard 8052
instruction set.
Publication Release Date: Jul, 29, 2009
- 11 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
6.7.1 ALU
The ALU is the heart of the N79E352(R). It is responsible for the arithmetic and logical functions. It is
also used in decision making, in case of jump instructions, and is also used in calculating jump
addresses. The user cannot directly use the ALU, but the Instruction Decoder reads the op-code,
decodes it, and sequences the data through the ALU and its associated registers to generate the
required result. The ALU mainly uses the ACC which is a special function register (SFR) on the chip.
Another SFR, namely B register is also used in Multiply and Divide instructions. The ALU generates
several status signals which are stored in the Program Status Word register (PSW).
6.7.2 Accumulator
The Accumulator (ACC) is the primary register used in arithmetic, logical and data transfer operations
in N79E352(R). Since the Accumulator is directly accessible by the CPU, most of the high speed
instructions make use of the ACC as one argument.
6.7.3 B Register
This is an 8-bit register that is used as the second argument in the MUL and DIV instructions. For all
other instructions it can be used simply as a general purpose register.
6.7.4 Program Status Word:
This is an 8-bit SFR that is used to store the status bits of the ALU. It holds the Carry flag, the Auxiliary
Carry flag, General purpose flags, the Register Bank Select, the Overflow flag, and the Parity flag.
6.7.5 Scratch-pad RAM
N79E352(R) has a 256 bytes on-chip scratch-pad RAM. These can be used by the user for temporary
storage during program execution. A certain section of this RAM is bit addressable, and can be directly
addressed for this purpose.
6.7.6 Stack Pointer
N79E352(R) has an 8-bit Stack Pointer which points to the top of the Stack. This stack resides in the
Scratch Pad RAM. Hence the size of the stack is limited by the size of this RAM.
6.8 Power Management
Like the standard 80C52, the N79E352(R) also has IDLE and POWER DOWN modes of operation.
The N79E352(R) provides a new Economy mode which allow user to switch the internal clock rate
divided by either 4, 64 or 1024. In the IDLE mode, the clock to the CPU core is stopped while the
timers, serial ports and interrupts clock continue to operate. In the POWER DOWN mode, all the clock
are stopped and the chip operation is completely stopped. This is the lowest power consumption state.
- 12 -
Preliminary N79E352/N79E352R Data Sheet
7. MEMORY ORGANIZATION
N79E352(R) separates the memory into two separate sections, the Program Memory and the Data
Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is
used to store data or for memory mapped devices.
(128B NVM,
16bytes/page)
FFFFH
FC7Fh
Page 7
FC70h
FC6Fh
Page 6
FC60h
FC5Fh
Page 5
FC50h
FC4Fh
FC7FH
128B
NVM
Data Memory
(MOVX)
Page 4
FC40h
FC3Fh
External
Program
Memory
Page 3
Page 2
Page 1
Page 0
FC30h
FC2Fh
FC00H
FC20h
FC1Fh
FC10h
FC0Fh
FC00h
2000H
1FFFH
NVM Data Flash Area
8K Bytes
On-Chip
Code Memory
CONFIG 1
CONFIG 0
0000H
Program
Memory Space
Figure 7-1: N79E352(R) Memory Map
7.1 Program Memory (on-chip Flash)
The Program Memory on N79E352(R) can be up to 8K bytes long. All instructions are fetched for
execution from this memory area. The MOVC instruction can also access this memory region.
Publication Release Date: Jul, 29, 2009
- 13 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
7.2 Data Memory
The N79E352(R) has NVM data memory of 128 bytes for customer’s data store used. The NVM data
memory has 8 pages area and each page has 16 bytes. The N79E352(R) can access up to 64Kbytes
of external Data Memory. This memory region is accessed by the MOVX instructions. For NVM s/w
read access, user require to set EnNVM bit, otherwise, the access will goes to external data memory.
N79E352(R) has the standard 256 bytes of on-chip Scratchpad RAM. This can be accessed either by
direct addressing or by indirect addressing. There are also some Special Function Registers (SFRs),
which can only be accessed by direct addressing. Since the Scratchpad RAM is only 256 bytes, it can
be used only when data contents are small.
7.3 Scratch-pad RAM and Register Map
As mentioned before, N79E352(R) has separate Program and Data Memory areas. The on-chip 256
bytes scratch pad RAM is in addition to the external memory. There are also several Special Function
Registers (SFRs) which can be accessed by software. The SFRs can be accessed only by direct
addressing, while the on-chip RAM can be accessed by either direct or indirect addressing.
FFH
SFR
Indirect
Direct
RAM
Addressing
Addressing
Only
80H
7FH
Direct
&
Indirect
RAM
Addressing
00H
Figure 7-2: N79E352(R) RAM and SFR Memory Map
Since the scratch-pad RAM is only 256 bytes it can be used only when data contents are small. There
are several other special purpose areas within the scratch-pad RAM. These are illustrated in next
figure.
- 14 -
Preliminary N79E352/N79E352R Data Sheet
FFH
Indirect RAM
80H
7FH
Direct RAM
30H
2FH 7F 7E 7D 7C 7B 7A 79
2EH 77 76 75 74 73 72 71
2DH 6F 6E 6D 6C 6B 6A 69
2CH 67 66 65 64 63 62 61
2BH 5F 5E 5D 5C 5B 5A 59
2AH 57 56 55 54 53 52 51
29H 4F 4E 4D 4C 4B 4A 49
47 46 45
41
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
28H
44
43
42
27H 3F 3E 3D 3C 3B 3A 39
26H 34 33
25H 2F 2E 2D 2C 2B 2A 29
24H 27 26 25 24 23 22 21
23H 1F 1E 1D 1C 1B 1A 19
22H 17 16 15 14 13 12 11
21H 0F 0E 0D 0C 0B 0A 09
37
36
35
32
31
20H 07
1FH
06
05
04
03
02
01
Bank 3
18H
17H
Bank 2
Bank 1
Bank 0
10H
0FH
08H
07H
00H
Figure 7-3: Scratch-pad RAM
Publication Release Date: Jul, 29, 2009
Revision A06
- 15 -
Preliminary N79E352/N79E352R Data Sheet
7.3.1 Working Registers
There are four sets of working registers, each consisting of eight 8-bit registers. These are termed as
Banks 0, 1, 2, and 3. Individual registers within these banks can be directly accessed by separate
instructions. These individual registers are named as R0, R1, R2, R3, R4, R5, R6 and R7. However, at
any one time N79E352 can work with only one particular bank. The bank selection is done by setting
RS1-RS0 bits in the PSW. The R0 and R1 registers are used to store the address for indirect
accessing.
7.3.2 Bit addressable Locations
The Scratch-pad RAM area from location 20h to 2Fh is byte as well as bit addressable. This means
that a bit in this area can be individually addressed. In addition some of the SFRs are also bit
addressable. The instruction decoder is able to distinguish a bit access from a byte access by the type
of the instruction itself. In the SFR area, any existing SFR whose address ends in a 0 or 8 is bit
addressable.
7.3.3 Stack
The scratch-pad RAM can be used for the stack. This area is selected by the Stack Pointer (SP), which
stores the address of the top of the stack. Whenever a jump, call or interrupt is invoked the return
address is placed on the stack. There is no restriction as to where the stack can begin in the RAM. By
default however, the Stack Pointer contains 07h at reset. The user can then change this to any value
desired. The SP will point to the last used value. Therefore, the SP will be incremented and then
address saved onto the stack. Conversely, while popping from the stack the contents will be read first,
and then the SP is decreased.
- 16 -
Preliminary N79E352/N79E352R Data Sheet
8. SPECIAL FUNCTION REGISTERS
The N79E352(R) uses Special Function Registers (SFRs) to control and monitor peripherals and their
Modes.
The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of
the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit
without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or
8. The N79E352(R) contains all the SFRs present in the standard 8052. However, some additional
SFRs have been added. In some cases unused bits in the original 8052 have been given new
functions. The list of SFRs is as follows. The table is condensed with eight locations per row. Empty
locations indicate that there are no registers at these addresses. When a bit or register is not
implemented, it will read high.
8.1 SFR Location Table
IP1
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
B
IP1H
EIE
KBL
PORTS
CCL0
P5M1
CCH0
P5M2
ACC
WDCON
PSW
T2CON
I2CON
IP0
PWM0L
PWM1L
PWMCON1
PWMCON3
NVMDAT
TA
T2MOD
I2ADDR
SADEN
P0M1
RCAP2L
RCAP2H
TL2
TH2
NVMCON
NVMADDR
I2CLK
ROMMAP
PMR
STATUS
I2STATUS
P2M1
I2DATA
P1M2
I2TIMER
IP0H
P3
P0M2
P1M1
P2M2
IE
SADDR
KBI
P2
AUXR1
CAPCON0
CAPCON1
P4
SCON
P1
SBUF
P3M1
P3M2
P5
TCON
P0
TMOD
SP
TL0
TL1
TH0
DPL1
TH1
CKCON
DPS
8F
87
DPL
DPH
DPH1
PCON
Note: The SFRs in the column with dark borders are bit-addressable.
Table 8- 1: Special Function Register Location Table
Publication Release Date: Jul, 29, 2009
Revision A06
- 17 -
Preliminary N79E352/N79E352R Data Sheet
SYMBOL
IP1
DEFINITION
ADDRESS
F8H
MSB
PCAP
BIT ADDRESS, SYMBOL
LSB
PI2
RESET
INTERRUPT PRIORITY 1
INTERRUPT HIGH PRIORITY 1
B REGISTER
PBO
PBOH
B.6
-
PWDI
PWDIH
B.4
-
-
PKB
00x0 xx00B
00x0 xx00B
0000 0000B
IP1H
B
F7H
PCAPH
-
-
-
PKBH
B.1
PI2H
B.0
F0H
B.7
-
B.5
-
B.3
-
B.2
-
P5M2
PORT 5 OUTPUT MODE 2
EEH
-
-
P5M2.1
P5M2.0
CONFIG0.PMOD
E=1;
Xxxx xx00B
CONFIG0.PMOD
E=0;
Xxxx xx11B
P5M1
PORT 5 OUTPUT MODE 1
EDH
-
-
-
-
-
ENCLK
P5M1.1
P5M1.0
CONFIG0.PMOD
E=1;
Xxxx x000B
CONFIG0.PMOD
E=0;
Xxxx x011B
xx0x 0000B
0000 0000B
00x0 xx00B
0000 0000B
0000 0000B
0000 0000B
0xx0 xxxxB
0000 0000B
0000 0000B
POR:
PORTS
KBL
PORT SHMITT REGISTER
KEYBOARD LEVEL REGISTER
INTERRUPT ENABLE 1
ECH
E9H
E8H
E5H
E4H
E0H
DCH
DBH
DAH
D8H
-
-
P5S
-
P3S
P2S
P1S
P0S
KBL.7
KBL.6
EBO
KBL.5
-
KBL.4
EWDI
CCH0.4
CCL0.4
ACC.4
CLRPWM
PWM1.4
PWM0.4
-
KBL.3
-
KBL.2
-
KBL.1
EKB
KBL.0
EI2
EIE
ECPTF
CCH0.7
CCL0.7
ACC.7
CCH0
INPUT CAPTURE 0 HIGH
INPUT CAPTURE 0 LOW
ACCUMULATOR
CCH0.6
CCL0.6
ACC.6
-
CCH0.5
CCL0.5
ACC.5
-
CCH0.3
CCL0.3
ACC.3
-
CCH0.2
CCL0.2
ACC.2
-
CCH0.1
CCL0.1
ACC.1
-
CCH0.0
CCL0.0
ACC.0
-
CCL0
ACC
PWMCON1
PWM1L
PWM0L
WDCON
PWM CONTROL REGISTER 1
PWM 1 LOW BITS REGISTER
PWM 0 LOW BITS REGISTER
WATCH-DOG CONTROL
PWMRUN
PWM1.7
PWM0.7
WDRUN
PWM1.6
PWM0.6
POR
PWM1.5
PWM0.5
-
PWM1.3
PWM0.3
WDIF
PWM1.2
PWM0.2
WTRF
PWM1.1
PWM0.1
EWRST
PWM1.0
PWM0.0
WDCLR
X1xx 0000B
External reset:
Xxxx 0xx0B
Watchdog reset:
Xxxx 01x0B
Xx00 0000B
0000 0000B
PWMCON3
PSW
PWM CONTROL REGISTER 3
PROGRAM STATUS WORD
NVM DATA
D7H
D0H
CFH
-
-
PWM1OE
F0
PWM0OE
RS1
PCLK.1
RS0
PCLK.0
OV
FP1
F1
FP0
P
CY
AC
NVMDATA
NVMDATA.7 NVMDATA.6 NVMDATA.5 NVMDATA.4 NVMDATA. NVMDATA. NVMDATA. NVMDATA. 0000 0000B
3
2
1
0
NVMCON
TH2
NVM CONTROL
CEH
CDH
CCH
CBH
CAH
C9H
C8H
C7H
C6H
EER
EWR
TH2.6
TL2.6
EnNVM
TH2.5
TL2.5
-
-
-
-
-
000x xxxxB
0000 0000B
0000 0000B
TIMER 2 MSB
TH2.7
TL2.7
TH2.4
TL2.4
TH2.3
TL2.3
TH2.2
TL2.2
TH2.1
TL2.1
TH2.0
TL2.0
TL2
TIMER 2 LSB
RCAP2H
RCAP2L
T2MOD
T2CON
TA
TIMER 2 RELOAD MSB
TIMER 2 RELOAD LSB
TIMER 2 MODE
RCAP2H.7 RCAP2H.6
RCAP2H.5
RCAP2L.5
-
RCAP2H.4
RCAP2L.4
ICEN0
TCLK
RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0 0000 0000B
RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0 0000 0000B
RCAP2L.7
RCAP2L.6
-
-
T2CR
EXEN2
TA.3
1
T2OE
C/T2
TA.1
DCEN
CP/RL
TA.0
Xxx0 0100B
0000 0000B
0000 0000B
TIMER 2 CONTROL
TIMED ACCESS PROTECTION
NVM LOW BYTE ADDRESS
TF2
TA.7
EXF2
TA.6
RCLK
TA.5
TR2
TA.2
TA.4
NVMADDR
NVMADDR.7 NVMADDR.6 NVMADDR.5 NVMADDR.4 NVMADDR. NVMADDR. NVMADDR. NVMADDR. 0000 0000B
3
2
1
0
STATUS
PMR
STATUS REGISTER
C5H
C4H
-
-
-
-
-
-
-
SPTA0
SPRA0
-
Xxxx xx00B
010x xxxxB
POWER MANAGEMENT
REGISTER
CD1
CD0
SWB
-
ALE-OFF
-
ROMMAP
I2ADDR
ROMMAP REGISTER
I2C ADDRESS1
C2H
C1H
WS
1
-
-
-
1
1
0
01xxx110B
xxxxxxx0B
ADDR.7
ADDR.6
ADDR.5
ADDR.4
ADDR.3
ADDR.2
ADDR.1
GC
- 18 -
Preliminary N79E352/N79E352R Data Sheet
SYMBOL
DEFINITION
ADDRESS
MSB
BIT ADDRESS, SYMBOL
LSB
RESET
I2CON
I2C CONTROL REGISTER
C0H
-
-
ENSI
STA
STO
SI
AA
-
-
x00000xxB
Xxxx x000B
0000 0000B
I2TIMER
I2CLK
I2C TIMER COUNTER REGISTER BFH
-
-
-
-
ENTI
DIV4
TIF
I2C CLOCK RATE
I2C STATUS
BEH
BDH
I2CLK.7
I2CLK.6
I2CLK.5
I2CLK.4
I2CLK.3
I2CLK.2
I2CLK.1
I2CLK.0
I2STATUS
I2STATUS.7 I2STATUS.6 I2STATUS.5 I2STATUS.4 I2STATUS. I2STATUS. I2STATUS. I2STATUS. 1111 1000B
3
2
1
0
I2DAT
I2C DATA
BCH
B9H
I2DAT.7
I2DAT.6
I2DAT.5
I2DAT.4
I2DAT.3
I2DAT.2
I2DAT.1
I2DAT.0
xxxxxxxxB
SADEN
SLAVE ADDRESS MASK
SADEN.7
SADEN.6
SADEN.5
SADEN.4
SADEN.3
SADEN.2
SADEN.1
SADEN.0
00000000B
Xx00 0000B
Xx00 0000B
IP0
INTERRUPT PRIORITY
B8H
B7H
B6H
-
-
PT2
PS
PT1
PX1
PT0
PX0
IP0H
P2M2
INTERRUPT HIGH PRIORITY
PORT 2 OUTPUT MODE 2
-
-
PT2H
P2M2.5
PSH
PT1H
P2M2.3
PX1H
P2M2.2
PT0H
P2M2.1
PX0H
P2M2.0
P2M2.7
P2M2.6
P2M2.4
CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
P2M1
P1M2
P1M1
PORT 2 OUTPUT MODE 1
PORT 1 OUTPUT MODE 2
PORT 1 OUTPUT MODE 1
B5H
B4H
B3H
P2M1.7
P1M2.7
P1M1.7
P2M1.6
P1M2.6
P1M1.6
P2M1.5
P1M2.5
P1M1.5
P2M1.4
P1M2.4
P1M1.4
P2M1.3
P1M2.3
P1M1.3
P2M1.2
P1M2.2
P1M1.2
P2M1.1
P1M2.1
P1M1.1
P2M1.0
P1M2.0
P1M1.0
CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
1111 1111B
1111 1111B
1111 1111B
P0M2
P0M1
P3
PORT 0 OUTPUT MODE 2
PORT 0 OUTPUT MODE 1
PORT3
B2H
B1H
B0H
P0M2.7
P0M1.7
P3.7
P0M2.6
P0M1.6
P3.6
P0M2.5
P0M1.5
P3.5
P0M2.4
P0M1.4
P3.4
P0M2.3
P0M1.3
P3.3
P0M2.2
P0M1.2
P3.2
P0M2.1
P0M1.1
P3.1
P0M2.0
P0M1.0
P3.0
/RD
/WR
T1
T0
/INT1
/INT0
TXD
RXD
SADDR
IE
SLAVE ADDRESS
INTERRUPT ENABLE
PORT4
A9H
A8H
A5H
A4H
A3H
A2H
A1H
A0H
SADDR.7
SADDR.6
-
SADDR.5
SADDR.4
SADDR.3
ET1
SADDR.2
EX1
SADDR.1
ET0
SADDR.0
EX0
0000 0000B
0x00 0000B
Xxxx 1111B
00xx 0xx0B
Xxxx 00xxB
0000 0000B
0000 0000B
1111 1111B
EA
ET2
-
ES
P4
-
-
-
P4.3
P4.2
P4.1
-
P4.0
CAPCON1
CAPCON0
AUXR1
KBI
CAPTURE CONTROL 1
CAPTURE CONTROL 0
AUX FUNCTION REGISTER 1
KEYBOARD INTERRUPT
PORT 2
0
T0CC
-
-
-
ENF0
CCT0.1
SRST
KBI.3
P2.3
-
CPTF0
-
-
-
-
CCT0.0
BOV1
KBI.2
P2.2
-
KBF
KBI.7
P2.7
A15
P3M2.7
BOD
KBI.6
P2.6
A14
BOI
KBI.5
P2.5
A13
P3M2.5
LPBOV
KBI.4
P2.4
A12
BOV0
KBI.1
P2.1
A9
BOS
KBI.0
P2.0
P2
A11
A10
A8
P3M2
PORT 3 OUTPUT MODE 2
9FH
P3M2.6
P3M2.4
P3M2.3
P3M2.2
P3M2.1
P3M2.0
CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
Publication Release Date: Jul, 29, 2009
Revision A06
- 19 -
Preliminary N79E352/N79E352R Data Sheet
SYMBOL
DEFINITION
ADDRESS
MSB
BIT ADDRESS, SYMBOL
LSB
RESET
P3M1
PORT 3 OUTPUT MODE 1
9EH
P3M1.7
P3M1.6
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
CONFIG0.PMOD
E=1;
0000 0000B
CONFIG0.PMOD
E=0;
1111 1111B
Xxxx xxxxB
0000 0000B
Xxxx xx11B
SBUF
SCON
P5
SERIAL BUFFER
SERIAL CONTROL
PORT5
99H
98H
94H
SBUF.7
SM0/FE
-
SBUF.6
SM1
-
SBUF.5
SM2
-
SBUF.4
REN
-
SBUF.3
TB8
SBUF.2
RB8
-
SBUF.1
TI
SBUF.0
RI
-
P5.1
XTAL1
-
P5.0
-
-
-
-
-
-
XTAL2
CLKOUT
P1.0
-
-
-
-
-
-
P1
PORT 1
90H
P1.7
-
P1.6
-
P1.5
PWM1
T2M
TH1.5
TH0.5
TL1.5
TL0.5
M1
P1.4
PWM0
T1M
TH1.4
TH0.4
TL1.4
TL0.4
M0
P1.3
SCL
T0M
TH1.3
TH0.3
TL1.3
TL0.3
GATE
IE1
P1.2
SDA
MD2
TH1.2
TH0.2
TL1.2
TL0.2
C/T
P1.1
T2EX
MD1
TH1.1
TH0.1
TL1.1
TL0.1
M1
1111 1111B
T2
CKCON
TH1
CLOCK CONTROL
TIMER HIGH 1
8EH
8DH
8CH
8BH
8AH
89H
88H
87H
86H
85H
84H
83H
82H
81H
80H
WD1
TH1.7
TH0.7
TL1.7
TL0.7
GATE
TF1
WD0
TH1.6
TH0.6
TL1.6
TL0.6
C/T
MD0
0000 0001B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
001x 0000B
Xxxx xxx0B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0111B
1111 1111B
TH1.0
TH0.0
TL1.0
TL0.0
M0
TH0
TIMER HIGH 0
TL1
TIMER LOW 1
TL0
TIMER LOW 0
TMOD
TCON
PCON
DPS
DPH1
DPL1
DPH
DPL
TIMER MODE
TIMER CONTROL
POWER CONTROL
DATA POINTER SELECT
DATA POINTER HIGH 1
DATA POINTER LOW 1
DATA POINTER HIGH
DATA POINTER LOW
STACK POINTER
PORT 0
TR1
TF0
TR0
-
IT1
IE0
IT0
SM0D
-
SMOD0
-
BOF
-
GF1
-
GF0
-
PD
IDL
-
-
DPS.0
DPH1.0
DPL1.0
DPH.0
DPL.0
SP.0
DPH1.7
DPL1.7
DPH.7
DPL.7
SP.7
P0.7
DPH1.6
DPL1.6
DPH.6
DPL.6
SP.6
P0.6
DPH1.5
DPL1.5
DPH.5
DPL.5
SP.5
P0.5
DPH1.4
DPL1.4
DPH.4
DPL.4
SP.4
P0.4
DPH1.3
DPL1.3
DPH.3
DPL.3
SP.3
P0.3
DPH1.2
DPL1.2
DPH.2
DPL.2
SP.2
P0.2
DPH1.1
DPL1.1
DPH.1
DPL.1
SP.1
P0.1
SP
P0
P0.0
AD7
KB7
AD6
KB6
AD5
KB5
AD4
KB4
AD3
KB3
AD2
KB2
AD1
KB1
AD0
KB0
- 20 -
Preliminary N79E352/N79E352R Data Sheet
8.2 SFR Detail Bit Descriptions
PORT 0
Bit:
7
6
5
4
3
2
1
0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Mnemonic: P0
Address: 80h
Port 0 is an open-drain bi-directional I/O port. This port provides a multiplexed low order address/data
bus during accesses to external memory. The ports also support alternate input function for Keyboard
pins (KB0-7).
BIT NAME
FUNCTION
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
AD7 or KB7 or I/O pin by alternative.
AD6 or KB6 or I/O pin by alternative.
AD5 or KB5 or I/O pin by alternative.
AD4 or KB4 or I/O pin by alternative.
AD3 or KB3 or I/O pin by alternative.
AD2 or KB2 or I/O pin by alternative.
AD1 or KB1 or I/O pin by alternative.
AD0 or KB0 or I/O pin by alternative.
7
6
5
4
3
2
1
0
Note: The initial value of the port is set by CONFIG0.PRHI bit. The default setting for CONFIG0.PRHI =1 which the alternative
function output is turned on upon reset. If CONFIG0.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the
alternative function output.
STACK POINTER
Bit:
7
6
5
4
3
2
1
0
SP.7
SP.6
SP.5
SP.4
SP.3
SP.2
SP.1
SP.0
Mnemonic: SP
Address: 81h
BIT NAME
FUNCTION
7-0
SP.[7:0]
The Stack Pointer stores the Scratch-pad RAM address where the stack begins.
In other words it always points to the top of the stack.
DATA POINTER LOW
Bit:
7
6
5
4
3
2
1
0
DPL.7
DPL.6
DPL.5
DPL.4
DPL.3
DPL.2
DPL.1
DPL.0
Mnemonic: DPL
Address: 82h
BIT NAME
FUNCTION
7-0 DPL.[7:0]
This is the low byte of the standard 8052 16-bit data pointer.
DATA POINTER HIGH
Bit:
7
6
5
4
3
2
1
0
Publication Release Date: Jul, 29, 2009
Revision A06
- 21 -
Preliminary N79E352/N79E352R Data Sheet
DPH.7
Mnemonic: DPH
BIT NAME
DPH.6
DPH.5
DPH.4
DPH.3
DPH.2
DPH.1
DPH.0
Address: 83h
FUNCTION
7-0 DPH.[7:0] This is the high byte of the standard 8052 16-bit data pointer.
This is the high byte of the DPTR 16-bit data pointer.
DATA POINTER LOW 1
Bit:
7
6
5
4
3
2
1
0
DPL1.7
DPL1.6
DPL1.5
DPL1.4
DPL1.3
DPL1.2
DPL1.1
DPL1.0
Mnemonic: DPL1
Address: 84h
BIT NAME
FUNCTION
7-0 DPL1.[7:0] This is the low byte of the new additional 16-bit data pointer that has been added
to the N79E352(R). The user can switch between DPL, DPH and DPL1, DPH1
simply by setting register DPS = 1. The instructions that use DPTR will now
access DPL1 and DPH1 in place of DPL and DPH. If they are not required they
can be used as conventional register locations by the user.
DATA POINTER HIGH 1
Bit:
7
6
5
4
3
2
1
0
DPH1.7
DPH1.6
DPH1.5
DPH1.4
DPH1.3
DPH1.2
DPH1.1
DPH1.0
Mnemonic: DPH1
Address: 85h
BIT NAME
FUNCTION
7-0 DPH1.[7:0]
This is the high byte of the new additional 16-bit data pointer that has been
added to the N79E352(R). The user can switch between DPL, DPH and DPL1,
DPH1 simply by setting register DPS = 1. The instructions that use DPTR will
now access DPL1 and DPH1 in place of DPL and DPH. If they are not required
they can be used as conventional register locations by the user.
DATA POINTER SELECT
Bit:
7
6
5
-
4
-
3
-
2
-
1
-
0
-
-
DPS.0
Mnemonic: DPS
Address: 86h
BIT NAME
FUNCTION
Reserved.
7-1
0
-
DPS
This bit is used to select either the DPL,DPH pair or the DPL1,DPH1 pair as the
active Data Pointer. When set to 1, DPL1, DPH1 will be selected, otherwise DPL,
DPH will be selected.
POWER CONTROL
Bit:
7
6
5
4
3
2
1
0
- 22 -
Preliminary N79E352/N79E352R Data Sheet
SMOD
Mnemonic: PCON
BIT NAME
SMOD0
BOF
-
GF1
GF0
PD
IDL
Address: 87h
FUNCTION
7
SMOD
1: This bit doubles the serial port baud rate in mode 1, 2, and 3.
0: Framing Error Detection Disable. SCON.7 (SM0/FE) bit is used as SM0
(standard 8052 function).
6
SMOD0
1: Framing Error Detection Enable. SCON.7 (SM0/FE) bit is used to reflect as
Frame Error (FE) status flag.
0: Cleared by software.
5
BOF
1: Set automatically when a brownout reset or interrupt has occurred. Also set at
power on.
4
3
2
-
Reserved.
GF1
GF0
General purpose user flags.
General purpose user flags.
1: The CPU goes into the POWER DOWN mode. In this mode, all the clocks are
stopped and program execution is frozen.
1
0
PD
1: The CPU goes into the IDLE mode. In this mode, the clocks CPU clock
stopped, so program execution is frozen. But the clock to the serial, timer and
interrupt blocks is not stopped, and these blocks continue operating.
IDL
TIMER CONTROL
Bit:
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
BIT NAME
FUNCTION
Timer 1 Overflow Flag. This bit is set when Timer 1 overflows. It is cleared
automatically when the program does a timer 1 interrupt service routine.
Software can also set or clear this bit.
7
6
5
4
TF1
TR1
TF0
TR0
Timer 1 Run Control. This bit is set or cleared by software to turn timer/counter
on or off.
Timer 0 Overflow Flag. This bit is set when Timer 0 overflows. It is cleared
automatically when the program does a timer 0 interrupt service routine.
Software can also set or clear this bit.
Timer 0 Run Control. This bit is set or cleared by software to turn timer/counter
on or off.
Interrupt 1 Edge Detect Flag: Set by hardware when an edge/level is detected on
3
IE1
INT1
. This bit is cleared by hardware when the service routine is vectored to only
if the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
Interrupt 1 Type Control. Set/cleared by software to specify falling edge/ low level
triggered external inputs.
2
1
IT1
IE0
Interrupt 0 Edge Detect Flag. Set by hardware when an edge/level is detected on
Publication Release Date: Jul, 29, 2009
- 23 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
INT0
. This bit is cleared by hardware when the service routine is vectored to
only if the interrupt was edge triggered. Otherwise it follows the inverse of the pin.
Interrupt 0 Type Control: Set/cleared by software to specify falling edge/ low level
triggered external inputs.
0
IT0
TIMER MODE CONTROL
Bit:
7
6
5
4
3
2
1
0
GATE
M1
M0
GATE
M1
M0
C/T
C/T
TIMER1
TIMER0
Mnemonic: TMOD
Address: 89h
BIT NAME
FUNCTION
Gating control: When this bit is set, Timer/counter 1 is enabled only while the
7
GATE
INT1 pin is high and the TR1 control bit is set. When cleared, the INT1 pin has
no effect, and Timer 1 is enabled whenever TR1 control bit is set.
Timer or Counter Select: When clear, Timer 1 is incremented by the internal
clock. When set, the timer counts falling edges on the T1 pin.
6
C/T
5
4
M1
M0
Timer 1 mode select bit 1. See table below.
Timer 1 mode select bit 0. See table below.
Gating control: When this bit is set, Timer/counter 0 is enabled only while the
3
GATE
INT0 pin is high and the TR0 control bit is set. When cleared, the INT0 pin has
no effect, and Timer 0 is enabled whenever TR0 control bit is set.
Timer or Counter Select: When clear, Timer 0 is incremented by the internal
clock. When set, the timer counts falling edges on the T0 pin.
2
C/T
1
0
M1
M0
Timer 0 mode select bit 1. See table below.
Timer 0 mode select bit 0. See table below.
M1, M0: Mode Select bits:
M1
0
M0
0
MODE
Mode 0: 8-bit timer/counter TLx serves as 5-bit pre-scale.
Mode 1: 16-bit timer/counter, no pre-scale.
0
1
Mode 2: 8-bit timer/counter with auto-reload from THx.
1
0
Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer0
control bits. TH0 is an 8-bit timer only controlled by Timer1 control bits. (Timer 1)
Timer/Counter 1 is stopped.
1
1
TIMER 0 LSB
Bit:
7
6
5
4
3
2
1
0
TL0.7
TL0.6
TL0.5
TL0.4
TL0.3
TL0.2
TL0.1
TL0.0
Mnemonic: TL0
Address: 8Ah
- 24 -
Preliminary N79E352/N79E352R Data Sheet
BIT NAME
FUNCTION
Timer 0 LSB.
7-0 TL0.[7:0]
TIMER 1 LSB
Bit:
7
6
5
4
3
2
1
0
TL1.7
TL1.6
TL1.5
TL1.4
TL1.3
TL1.2
TL1.1
TL1.0
Mnemonic: TL1
Address: 8Bh
BIT NAME
FUNCTION
7-0
TL1.[7:0] Timer 1 LSB.
TIMER 0 MSB
Bit:
7
6
5
4
3
2
1
0
TH0.7
TH0.6
TH0.5
TH0.4
TH0.3
TH0.2
TH0.1
TH0.0
Mnemonic: TH0
Address: 8Ch
BIT NAME
FUNCTION
7-0
TH0.[7:0] Timer 0 MSB.
TIMER 1 MSB
Bit:
7
6
5
4
3
2
1
0
TH1.7
TH1.6
TH1.5
TH1.4
TH1.3
TH1.2
TH1.1
TH1.0
Mnemonic: TH1
Address: 8Dh
BIT NAME
FUNCTION
7-0
TH1.[7:0] Timer 1 MSB.
CLOCK CONTROL
Bit:
7
6
5
4
3
2
1
0
WD1
WD0
T2M
T1M
T0M
MD2
MD1
MD0
Mnemonic: CKCON
Address: 8Eh
BIT NAME
FUNCTION
Watchdog timer mode select bits: These bits determine the time-out period for
the watchdog timer. In all four time-out options the reset time-out is 512 clocks
more than the interrupt time-out period.
WD1 WD0 Interrupt time-out
Reset time-out
6
6
0
0
1
1
0
1
0
1
7-5 WD1~0
2
2 + 512
9
9
2
2 + 512
13
15
13
2
2
2
+ 512
+ 512
15
2
Publication Release Date: Jul, 29, 2009
Revision A06
- 25 -
Preliminary N79E352/N79E352R Data Sheet
BIT NAME
FUNCTION
Timer 2 clock select:
5
4
3
T2M
T1M
T0M
0: Timer 2 uses a divide by 12 clocks.
1: Timer 2 uses a divide by 4 clocks.
Timer 1 clock select:
0: Timer 1 uses a divide by 12 clocks.
1: Timer 1 uses a divide by 4 clocks.
Timer 0 clock select:
0: Timer 0 uses a divide by 12 clocks.
1: Timer 0 uses a divide by 4 clocks.
Stretch MOVX select bits: These three bits are used to select the stretch value
for the MOVX instruction. Using a variable MOVX length enables the user to
access slower external memory devices or peripherals without the need for
RD
WR
strobe will be stretched by the selected
external circuits. The
or
interval. When accessing the on-chip SRAM, the MOVX instruction is always in 2
machine cycles regardless of the stretch setting. By default, the stretch has value
of 1. If the user needs faster accessing, then a stretch value of 0 should be
selected.
MD2 MD1
MD0
Stretch value MOVX duration
2~0 MD2~0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2 machine cycles
3 machine cycles (Default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
PORT 1
Bit:
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Mnemonic: P1
Address: 90h
P1.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT NAME
FUNCTION
7
6
5
4
P1.7
P1.6
P1.5
P1.4
Dedicated I/O pin.
Dedicated I/O pin.
PWM1 or I/O pin by alternative.
PWM0 or I/O pin by alternative.
- 26 -
Preliminary N79E352/N79E352R Data Sheet
BIT NAME
FUNCTION
3
2
1
0
P1.3
P1.2
P1.1
P1.0
SCL or I/O pin by alternative.
SDA or I/O pin by alternative.
T2EX or I/O pin by alternative.
T2 or I/O pin by alternative.
PORT 5
Bit:
7
6
5
4
3
2
1
0
P5.0/
P5.1/
-
-
-
-
-
-
XTAL2/
XTAL1
CLKOUT
Mnemonic: P5
Address: 94h
BIT NAME
FUNCTION
7~2
1
-
Reserved.
P5.1
P5.0
XTAL1 clock input or I/O pin by alternative.
0
XTAL2 or CLKOUT pin or I/O pin by alternative.
SERIAL PORT CONTROL
Bit:
7
6
5
4
3
2
1
TI
0
SM0/FE
SM1
SM2
REN
TB8
RB8
RI
Mnemonic: SCON
Address: 98h
BIT NAME
FUNCTION
Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON
SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is
described below. When used as FE, this bit will be set to indicate an invalid stop
bit. This bit must be manually cleared in software to clear the FE condition.
SM0/FE
SM1
7
6
Serial Port mode select bit 1. See table below.
Multiple processors communication. Setting this bit to 1 enables the
multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is
set to 1, then RI will not be activated if the received 9th data bit (RB8) is 0. In
mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not
received. In mode 0, the SM2 bit controls the serial port clock. If set to 0, then the
serial port runs at a divide by 12 clock of the oscillator. This gives compatibility
with the standard 8052. When set to 1, the serial clock become divide by 4 of the
oscillator clock. This results in faster synchronous serial communication.
SM2
5
Receive enable:
REN
0: Disable serial reception.
1: Enable serial reception.
4
This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared
by software as desired.
TB8
RB8
3
2
In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is
Publication Release Date: Jul, 29, 2009
- 27 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
BIT NAME
FUNCTION
the stop bit that was received. In mode 0 it has no function.
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time
in mode 0, or at the beginning of the stop bit in all other modes during serial
transmission. This bit must be cleared by software.
TI
1
0
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in
mode 0, or halfway through the stop bits time in the other modes during serial
reception. However the restrictions of SM2 apply to this bit. This bit can be
cleared only by software.
RI
SM1, SM0: Mode Select bits:
MODE
SM1
SM0
DESCRIPTION
LENGTH
BAUD RATE
0
0
0
1
1
0
1
0
1
Synchronous
8
FCPU divided by 4 or 12
1
2
3
Asynchronous
Asynchronous
Asynchronous
10
11
11
Variable
FCPU divided by 32 or 64
Variable
SERIAL DATA BUFFER
Bit:
7
6
5
4
3
2
1
0
SBUF.7
SBUF.6
SBUF.5
SBUF.4
SBUF.3
SBUF.2
SBUF.1
SBUF.0
Mnemonic: SBUF
Address: 99h
BIT NAME
FUNCTION
Serial data on the serial port is read from or written to this location. It actually
consists of two separate internal 8-bit registers. One is the receive resister, and
the other is the transmit buffer. Any read access gets data from the receive data
buffer, while write access is to the transmit data buffer.
7-0
SBUF.[7:0]
PORT 3 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
1
0
P3M1.7
P3M1.6
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
Mnemonic: P3M1
Address: 9Eh
BIT NAME
FUNCTION
7-0 P3M1.7-0 To control the output configuration of P3 [7:0].
PORT 3 OUTPUT MODE 2
Bit:
7
6
5
4
3
2
1
0
P3M2.7
P3M2.6
P3M2.5
P3M2.4
P3M2.3
P3M2.2
P3M2.1
P3M2.0
Mnemonic: P3M2
Address: 9Fh
BIT NAME
FUNCTION
7-0 P3M2.7-0
See as below table.
- 28 -
Preliminary N79E352/N79E352R Data Sheet
Port Output Configuration Settings:
PXM1.Y
PXM2.Y
PORT INPUT/OUTPUT MODE
0
0
0
1
Quasi-bidirectional
Push-Pull
Input Only (High Impedance)
PORTS.PxS=0, TTL input
PORTS.PxS=1, Schmitt input
Open Drain
1
0
1
1
Note:
1.
X = 0-3, 5. Y = 0-7.
2.
CONFIG0.PMODE bit will determine the port1~3 and port 5 are Quasi or Open drain upon reset. See detail PMODE
descriptions.
PORT 2
Bit:
7
6
5
4
3
2
1
0
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
Mnemonic: P2
Address: A0h
P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper
address bits for accesses to external memory.
BIT NAME
FUNCTION
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
A15 or I/O pin by alternative.
A14 or I/O pin by alternative.
A13 or I/O pin by alternative.
A12 or I/O pin by alternative.
A11 or I/O pin by alternative.
A10 or I/O pin by alternative.
A9 or I/O pin by alternative.
A8 or I/O pin by alternative.
7
6
5
4
3
2
1
0
KEYBOARD INTERRUPT
Bit:
7
6
5
4
3
2
1
0
KBI.7
KBI.6
KBI.5
KBI.4
KBI.3
KBI.2
KBI.1
KBI.0
Mnemonic: KBI
Address: A1h
BIT NAME
FUNCTION
7
6
5
4
KBI.7
KBI.6
KBI.5
KBI.4
1: Enable P0.7 as a cause of a Keyboard interrupt.
1: Enable P0.6 as a cause of a Keyboard interrupt.
1: Enable P0.5 as a cause of a Keyboard interrupt.
1: Enable P0.4 as a cause of a Keyboard interrupt.
Publication Release Date: Jul, 29, 2009
Revision A06
- 29 -
Preliminary N79E352/N79E352R Data Sheet
3
2
1
0
KBI.3
KBI.2
KBI.1
KBI.0
1: Enable P0.3 as a cause of a Keyboard interrupt.
1: Enable P0.2 as a cause of a Keyboard interrupt.
1: Enable P0.1 as a cause of a Keyboard interrupt.
1: Enable P0.0 as a cause of a Keyboard interrupt.
AUX FUNCTION REGISTER 1
Bit:
7
6
5
4
3
2
1
0
KBF
BOD
BOI
LPBOV
SRST
BOV1
BOV0
BOS
Mnemonic: AUXR1
Address: A2h
BIT NAME
FUNCTION
Keyboard Interrupt Flag:
1: When any pin of port 0 that is enabled for the Keyboard Interrupt function
triggers (trigger level is depending on SFR KBL configuration). Must be cleared by
software.
KBF
7
6
Brown Out Disable:
0: Enable Brownout Detect function.
BOD
1: Disable Brownout Detect function and save power.
BOD is initialized at all resets with the inverse value of bit CBOD in config0.3 bit.
User is able to re-configure this bit after reset.
Brown Out Interrupt:
0: Disable Brownout Detect Interrupt function.
BOI
5
4
3
1: This prevents brownout detection from causing a chip reset and allows the
Brownout Detect function to be used as an interrupt.
Low Power Brown Out Detect control:
0: When BOD is enable, the Brown Out detect is always turned on by normal run
or Power Down mode.
LPBOV
SRST
1: When BOD is enable, the 1/16 time will be turned on Brown Out detect circuit
by Power Down mode. When uC is entry Power Down mode, the BOD will enable
internal RC OSC (20KHz).
Software reset:
1: Reset the chip as if a hardware reset occurred.
SRST require Timed Access procedure to write. The remaining bits have
unrestricted write accesses. Please refer TA register description.
- 30 -
Preliminary N79E352/N79E352R Data Sheet
Brownout voltage selection bits, see below table.
BOV.1
BOV.0
Brownout Voltage
0
1
1
x
0
1
Brownout voltage is 2.6V
Brownout voltage is 3.8V
Brownout voltage is 4.5V
BOV.1~0
2~1
These bits are initialized at all resets with the inverse values of bits CBOV.1-0 in
config1.3-2 bits. User is able to re-configure these bits after reset.
Brownout Status bit(Read only)
0: VDD is above VBOR+
BOS
0
1: VDD is below VBOR-
CAPTURE CONTROL 0 REGISTER
Bit:
7
-
6
-
5
-
4
-
3
2
1
-
0
-
CCT0.1
CCT0.0
Mnemonic: CAPCON0
Address: A3h
BIT NAME
7-4
FUNCTION
-
Reserved.
3-2 CCT0[1:0] Capture 0 edge select:
00 : Rising edge trigger.
01 : Falling edge trigger.
10 : Either rising or falling edge trigger.
11 : Reserved
1-0
-
Reserved.
CAPTURE CONTROL 1 REGISTER
Bit:
7
0
6
5
-
4
-
3
2
-
1
-
0
T0CC
ENF0
CPTF0
Mnemonic: CAPCON1
BIT NAME FUNCTION
Must be 0.
Timer 0 Clear Counter bit.
0: Timer 0 is not clear when input capture/cap sensor trigger.
Address: A4h
7
6
-
T0CC
1: Timer 0 will be cleared when input capture/cap sensor trigger.
Reserved.
5-4
3
-
ENF0
Enable filter for capture input 0.
Publication Release Date: Jul, 29, 2009
Revision A06
- 31 -
Preliminary N79E352/N79E352R Data Sheet
2-1
0
-
Reserved.
External input capture 0 interrupt flag. It can be cleared by software.
CPTF0
PORT 4
Bit:
7
6
-
5
-
4
-
3
2
1
0
-
P4.3
P4.2
P4.1
P4.0
Mnemonic: P4
Address: A5h
BIT NAME
FUNCTION
Reserved.
7~4
-
3~0 P4.3~0
Port 4 is a bi-directional I/O port with internal pull-ups. Port 4 can not use bit-
addressable instruction (SETB or CLR).
INTERRUPT ENABLE
Bit:
7
6
5
4
3
2
1
0
EA
-
ET2
ES
ET1
EX1
ET0
EX0
Mnemonic: IE
Address: A8h
BIT NAME
FUNCTION
Global enable. Enable/Disable all interrupts.
Reserved.
7
6
5
4
3
2
1
0
EA
-
Enable Timer 2 interrupt.
Enable Serial Port 0 interrupt.
Enable Timer 1 interrupt.
Enable external interrupt 1.
Enable Timer 0 interrupt.
Enable external interrupt 0.
ET2
ES
ET1
EX1
ET0
EX0
SLAVE ADDRESS
Bit:
7
6
5
4
3
2
1
0
SADDR.0
SADDR.7
SADDR.6
SADDR.5
SADDR.4
SADDR.3
SADDR.2
SADDR.1
Mnemonic: SADDR
Address: A9h
BIT NAME
FUNCTION
The SADDR should be programmed to the given or broadcast address for serial
port 0 to which the slave processor is designated.
7~0 SADDR
PORT 3
Bit:
7
6
5
4
3
2
1
0
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
Mnemonic: P3
Address: B0h
- 32 -
Preliminary N79E352/N79E352R Data Sheet
P3.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT NAME
FUNCTION
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
/RD or I/O pin by alternative.
/WR or I/O pin by alternative.
T1 or I/O pin by alternative.
T0 or I/O pin by alternative.
/INT1 or I/O pin by alternative.
/INT0 or I/O pin by alternative.
TxD or I/O pin by alternative.
RxD or I/O pin by alternative.
7
6
5
4
3
2
1
0
PORT 0 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
1
0
P0M1.7
P0M1.6
P0M1.5
P0M1.4
P0M1.3
P0M1.2
P0M1.1
P0M1.0
Mnemonic: P0M1
Address: B1h
BIT NAME
FUNCTION
7-0 P0M1
To control the output configuration of P0 bits [7:0]
PORT 0 OUTPUT MODE 2
Bit:
7
6
5
4
3
2
1
0
P0M2.7
P0M2.6
P0M2.5
P0M2.4
P0M2.3
P0M2.2
P0M2.1
P0M2.0
Mnemonic: P0M2
Address: B2h
BIT NAME
FUNCTION
7-0 P0M2
To control the output configuration of P0 bits [7:0]
PORT 1 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
1
0
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
Mnemonic: P1M1
Address: B3h
BIT NAME
FUNCTION
7-0 P1M1
To control the output configuration of P1 bits [7:0].
PORT 1 OUTPUT MODE 2
Bit:
7
6
5
4
3
2
1
0
P1M2.7
P1M2.6
P1M2.5
P1M2.4
P1M2.3
P1M2.2
P1M2.1
P1M2.0
Mnemonic: P1M2
Address: B4h
Publication Release Date: Jul, 29, 2009
Revision A06
- 33 -
Preliminary N79E352/N79E352R Data Sheet
BIT NAME
FUNCTION
To control the output configuration of P1 bits [7:0].
7-0 P1M2
PORT 2 OUTPUT MODE 1
Bit:
7
6
5
4
3
2
1
0
P2M1.7
P2M1.6
P2M1.5
P2M1.4
P2M1.3
P2M1.2
P2M1.1
P2M1.0
Mnemonic: P2M1
Address: B5h
BIT NAME
FUNCTION
7-0 P2M1
To control the output configuration of P2 bits [7:0]
PORT 2 OUTPUT MODE 2
Bit:
7
6
5
4
3
2
1
0
P2M2.7
P2M2.6
P2M2.5
P2M2.4
P2M2.3
P2M2.2
P2M2.1
P2M2.0
Mnemonic: P2M2
Address: B6h
BIT NAME
FUNCTION
7-0 P2M2
To control the output configuration of P2 bits [7:0]
INTERRUPT HIGH PRIORITY
Bit:
7
6
5
4
3
2
1
0
-
-
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Mnemonic: IP0H
Address: B7h
BIT NAME
FUNCTION
Reserved.
7~6 -
5
4
3
2
1
0
PT2H
PSH
1: To set interrupt high priority of Timer 2 is highest priority level.
1: To set interrupt high priority of Serial port is highest priority level.
1: Ro set interrupt high priority of Timer 1 is highest priority level.
PT1H
PX1H
PT0H
PX0H
1: To set interrupt high priority of External interrupt 1 is highest priority level.
1: To set interrupt high priority of Timer 0 is highest priority level.
1: To set interrupt high priority of External interrupt 0 is highest priority level.
INTERRUPT PRIORITY 0
Bit:
7
6
5
4
3
2
1
0
-
-
PT2
PS
PT1
PX1
PT0
PX0
Mnemonic: IP0
Address: B8h
BIT NAME
FUNCTION
Reserved.
1: To set interrupt priority of Timer 2 is higher priority level.
7~6 -
5
4
PT2
PS
1: To set interrupt priority of Serial port is higher priority level.
- 34 -
Preliminary N79E352/N79E352R Data Sheet
3
2
1
0
PT1
PX1
PT0
PX0
1: To set interrupt priority of Timer 1 is higher priority level.
1: To set interrupt priority of External interrupt 1 is higher priority level.
1: To set interrupt priority of Timer 0 is higher priority level.
1: To set interrupt priority of External interrupt 0 is higher priority level.
SLAVE ADDRESS MASK ENABLE
Bit:
7
6
5
4
3
2
1
0
SADEN.7
SADEN.6
SADEN.5
SADEN.4
SADEN.3
SADEN.2
SADEN.1
SADEN.0
Mnemonic: SADEN
Address: B9h
BIT NAME
FUNCTION
This register enables the Automatic Address Recognition feature of the Serial port
0. When a bit in the SADEN is set to 1, the same bit location in SADDR will be
compared with the incoming serial data. When SADEN is 0, then the bit becomes
a "don't care" in the comparison. This register enables the Automatic Address
Recognition feature of the Serial port 0. When all the bits of SADEN are 0,
interrupt will occur for any incoming address.
7~0 SADEN
I2C DATA REGISTER
Bit:
7
6
5
4
3
2
1
0
I2DAT.7
I2DAT.6
I2DAT.5
I2DAT.4
I2DAT.3
I2DAT.2
I2DAT.1
I2DAT.0
Mnemonic: I2DAT
Address: BCh
BIT NAME
FUNCTION
7-0 I2DAT.[7:0] The data register of I2C.
I2C STATUS REGISTER
Bit:
7
6
5
4
3
2
1
0
I2STATUS.7 I2STATUS.6 I2STATUS.5 I2STATUS.4 I2STATUS.3
-
-
-
Mnemonic: I2STATUS
Address: BDh
BIT NAME
FUNCTION
The status register of I2C:
The three least significant bits are always 0. The five most significant bits
contain the status code. There are 23 possible status codes. When
I2STATUS contains F8H, no serial interrupt is requested. All other
I2STATUS values correspond to defined I2C states. When each of these
states is entered, a status interrupt is requested (SI = 1). A valid status
code is present in I2STATUS one machine cycle after SI is set by hardware
and is still present one machine cycle after SI has been reset by software.
In addition, states 00H stands for a Bus Error. A Bus Error occurs when a
START or STOP condition is present at an illegal position in the formation
frame. Example of illegal position are during the serial transfer of an
address byte, a data byte or an acknowledge bit.
7-0 I2STATUS.[7:0]
I2C BAUD RATE CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
Publication Release Date: Jul, 29, 2009
Revision A06
- 35 -
Preliminary N79E352/N79E352R Data Sheet
I2CLK.7
I2CLK.6
I2CLK.5
I2CLK.4
I2CLK.3
I2CLK.2
I2CLK.1
I2CLK.0
Mnemonic: I2CLK
Address: BEh
BIT
NAME
FUNCTION
7-0
I2CLK.[7:0] The I2C clock rate bits.
I2C TIMER COUNTER REGISTER
Bit:
7
6
5
4
-
3
-
2
1
0
-
-
-
ENTI
DIV4
TIF
Mnemonic: I2TIMER
Address: BFh
BIT
NAME
FUNCTION
7~3
-
Reserved.
Enable I2C 14-bits Timer Counter:
0: Disable 14-bits Timer Counter count.
2
1
0
ENTI
DIV4
TIF
1: Enable 14-bits Timer Counter count. After enable ENTI and ENSI, the 14-bit
counter will be counted. When SI flag of I2C is set, the counter will stop to
count and 14-bits Timer Counter will be cleared.
I2C Timer Counter clock source divide function:
0: The 14-bits Timer Counter source clock is FCPU clock.
1: The 14-bits Timer Counter source clock is divided by 4.
The I2C Timer Counter count flag:
0: The 14-bits Timer Counter is not overflow.
1: The 14-bits Timer Counter is overflow. Before enable I2C Timer (both ENTI,
ENSI = [1,1]) the SI must be cleared. If I2C interrupt is enabled. The I2C
interrupt service routine will be executed. This bit is cleared by software.
I2C CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
-
0
-
-
ENSI
STA
STO
SI
AA
Mnemonic: I2CON
Address: C0h
BIT
NAME
FUNCTION
Reserved.
7
-
0: Disable I2C Serial Function. The SDA and SCL output are in a high
impedance state. SDA and SCL input signals are ignored, I2C is not in the
addressed slave mode or it is not addressable, and STO bit in I2CON is
forced to “0”. No other bits are affected. P1.3 (SCL) and P1.2 (SDA) may be
used as open drain I/O ports.
6
5
ENSI
STA
1: Enable I2C Serial Function. The P1.2 and P1.3 port latches must be to logic
1.
START flag:
0: The STA bit is reset, no START condition or repeated START condition will
- 36 -
Preliminary N79E352/N79E352R Data Sheet
be generated.
1: The STA bit is set to enter a master mode. The I2C hardware checks the
status of I2C bus and generates a START condition if the bus is free. If bus is
not free, then I2C waits for a STOP condition and generates a START
condition after a delay. If STA is set while I2C is already in a master mode
and one or more bytes are transmitted or received, I2C transmits a repeated
START condition. STA may be set any time. STA may also be set when I2C
interface is an addressed slave mode.
The bit STO bit is set while I2C is in a master mode. A STOP condition is
transmitted to the I2C bus. When the STOP condition is detected on the bus,
the I2C hardware clears the STO flag. In a slave mode, the STO flag may be
set to recover from a bus error condition. In this case, no STOP condition is
transmitted to the I2C bus. However, the I2C hardware behaves as if a STOP
condition has been received and it switches to the not addressable slave
receiver mode. The STO flag is automatically cleared by hardware. If the STA
and STO bits are both set, then a STOP condition is transmitted to the I2C bus
if I2C is in a master mode (in a slave mode, I2C generates an internal STOP
condition which is not transmitted). I2C then transmits a START condition.
4
STO
0: When the SI flag is reset, no serial interrupt is requested, and there is no
stretching on the serial clock on the SCL line.
1: When a new I2C bus state is present in the I2STATUS register, the SI flag is
set by hardware, and, if the EA and ES bits (in IE register) are both set, a
serial interrupt is requested when SI is set. The only state that does not
cause SI to be set is state F8H, which indicates that no relevant state
information is available. When SI is set, the low period of the serial clock on
the SCL line is stretched, and the serial transfer is suspended. A high level on
the SCL line is unaffected by the serial interrupt flag. SI must be cleared by
software.
3
SI
Assert Acknowledge Flag:
0: A not acknowledge (high level to SDA) will be returned during the
acknowledge clock pulse on SCL when: 1) A data has been received while
I2C is in the master receiver mode. 2) A data byte has been received while
I2C is in the addressed slave receiver mode.
2
AA
1: An acknowledge (low level to SDA) will be returned during the acknowledge
clock pulse on the SCL line when: 1) The own slave address has been
received. 2) A data byte has been received while I2C is in the master receiver
mode. 3) A data byte has been received while I2C is in the addressed slave
receiver mode. 4) The General Call address has been received while the
general call bit (GC) in I2ADDR is set.
1~0
-
Reserved.
I2C ADDRESS REGISTER
Bit:
7
6
5
4
3
2
1
0
I2ADDR.7 I2ADDR.6 I2ADDR.5 I2ADDR.4 I2ADDR.3 I2ADDR.2 I2ADDR.1 GC
Mnemonic: I2ADDR
NAME FUNCTION
Address: C1h
BIT
Publication Release Date: Jul, 29, 2009
Revision A06
- 37 -
Preliminary N79E352/N79E352R Data Sheet
I2C Address register:
The 8051 uC can read from and write to this 8-bit, directly addressable
SFR. The content of this register is irrelevant when I2C is in master mode.
In the slave mode, the seven most significant bits must be loaded with the
MCU’s own address. The I2C hardware will react if either of the address is
matched.
7~1
I2ADDR.[7:1]
General Call Function.
0
GC
0: Disable General Call Function.
1: Enable General Call Function.
ROMMAP
Bit:
7
6
1
5
-
4
-
3
-
2
1
1
1
0
0
WS
Mnemonic: ROMMAP
Address: C2h
BIT NAME
FUNCTION
Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The
7
WS
device will sample the wait state control signal WAIT via P4.0 during MOVX
instruction. This bit is time access protected.
6~0
-
Reserved.
TA
REG C7H
ROMMAP
REG C2H
CKCON
MOV
REG 8EH
TA,#AAH
MOV
TA,#55H
ORL
ROMMAP,#10000000B ; Set WS bit to enable wait signal.
POWER MANAGEMENT REGISTER
Bit:
7
6
5
4
-
3
-
2
1
-
0
-
CD1
CD0
SWB
ALE-OFF
Mnemonic: PMR
Address: C4h
BIT NAME
FUNCTION
- 38 -
Preliminary N79E352/N79E352R Data Sheet
Clock Divide Control. These bit selects the number of clocks required to
generate one machine cycle. There are three modes including divide by 4, 64 or
1024. Switching between modes must first go back devide by 4 mode. For
instance, to go from 64 to 1024 clocks/machine cycle the device must first go
from 64 to 4 clocks/machine cycle, and then from 4 to 1024 clocks/machine
cycle.
7~6 CD1~0
CD1, CD0
Clocks/machine Cycle
0
1
1
X
0
1
4
64
1024
Switchback Enable. Setting this bit allows an enabled external interrupt or serial
port/I2C activity to force the CD1, CD0 to divide by 4 state (0,X). The device will
switch modes at the start of the jump to interrupt service routine while an
external interrupt is enabled and actually recognized by microcontroller. While a
serial port/I2C reception, the switchback occurs at the start of the instruction
following the falling edge of the start bit. Note: Changing SWB bit is ignored
during serial port/I2C activities.
5
SWB
4~3
2
-
Reserved.
This bit disables the expression of the ALE signal on the device pin during all on-
board program and data memory accesses. External memory accesses will
automatically enable ALE independent of ALE-OFF.
ALE-0FF
-
0 = ALE expression is enable.
1 = ALE expression is disable.
Reserved.
1~0
STATUS
Bit:
7
6
-
5
-
4
-
3
-
2
-
1
0
-
SPTA0
SPRA0
Mnemonic: STATUS
Address: C5h
BIT NAME
FUNCTION
7-2
1
-
Reserved.
SPTA0
Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently
transmitting data. It is cleared when TI bit is set by hardware. Changing the Clock
Divide Control bits CD0, CD1 will be ignored when this bit is set to 1 and SWB =
1.
0
SPRA0
Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently
receiving a data. It is cleared when RI bit is set by hardware. Changing the Clock
Divide Control bits CD0, CD1 will be ignored when this bit is set to 1 and SWB =
1.
NVM LOW BYTE ADDRESS
Bit:
7
6
5
4
3
2
1
0
Publication Release Date: Jul, 29, 2009
Revision A06
- 39 -
Preliminary N79E352/N79E352R Data Sheet
-
NVMADD
R.6
NVMADD
R.5
NVMADD
R.4
NVMADD
R.3
NVMADD
R.2
NVMADD
R.1
NVMADD
R.0
Mnemonic: NVMADDR
Address: C6h
BIT NAME
FUNCTION
Reserved
6~0 NVMADDR.[6:0] The NVM address:
7
-
The register indicates NVM data memory address on On-Chip code
memory space.
TIMED ACCESS
Bit:
7
6
5
4
3
2
1
0
TA.7
TA.6
TA.5
TA.4
TA.3
TA.2
TA.1
TA.0
Mnemonic: TA
Address: C7h
BIT NAME
FUNCTION
The Timed Access register:
The Timed Access register controls the access to protected bits. To access
protected bits, the user must first write AAH to the TA. This must be immediately
followed by a write of 55H to TA. Now a window is opened in the protected bits
for three machine cycles, during which the user can write to these bits.
7-0 TA.[7:0]
TIMER 2 CONTROL
Bit:
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C / T2
CP / RL2
Address: C8h
Mnemonic: T2CON
BIT NAME
FUNCTION
Timer 2 overflow flag:
Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when
the count is equal to the capture register in down count mode. It can be set only
if RCLK and TCLK are both 0. It is cleared only by software. Software can also
set or clear this bit.
7
TF2
Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2
overflow will cause this flag to set based on the CP / RL2, EXEN2 and DCEN
bits. If set by a negative transition, this flag must be cleared by software. Setting
this bit in software or detection of a negative transition on T2EX pin will force a
timer interrupt if enabled.
6
5
EXF2
RCLK
Receive Clock Flag: This bit determines the serial port time-base when receiving
data in serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate
generation, otherwise timer 2 overflow is used. Setting this bit forces timer 2 in
baud rate generator mode.
- 40 -
Preliminary N79E352/N79E352R Data Sheet
Transmit Clock Flag: This bit determines the serial port time-base when
transmitting data in modes 1 and 3. If it is set to 0, the timer 1 overflow is used
to generate the baud rate clock otherwise timer 2 overflow is used. Setting this
bit forces timer 2 in baud rate generator mode.
4
TCLK
Timer 2 External Enable. This bit enables the capture/reload function on the
T2EX pin if Timer 2 is not generating baud clocks for the serial port. If this bit is
0, then the T2EX pin will be ignored, otherwise a negative transition detected on
the T2EX pin will result in capture or reload.
3
2
EXEN2
TR2
Timer 2 Run Control:
This bit enables/disables the operation of timer 2. Halting this will preserve the
current count in TH2, TL2.
Counter/Timer Select. This bit determines whether timer 2 will function as a timer
or a counter. Independent of this bit, the timer will run at 2 clocks per tick when
used in baud rate generator mode. If it is set to 0, then timer 2 operates as a
timer at a speed depending on T2M bit (CKCON.5), otherwise it will count
negative edges on T2 pin.
1
0
C/ T2
Compare/Reload Select:
This bit determines whether the capture or reload function will be used for timer
2. If either RCLK or TCLK is set, this bit will be ignored and the timer will function
in an auto-reload mode following each overflow. If the bit is 0 then auto-reload
will occur when timer 2 overflows or a falling edge is detected on T2EX pin if
EXEN2 = 1. If this bit is 1, then timer 2 captures will occur when a falling edge is
detected on T2EX pin if EXEN2 = 1.
CP/RL2
TIMER 2 MODE CONTROL
Bit:
7
6
5
-
4
3
2
1
1
0
-
-
ICEN0
T2CR
T2OE
DCEN
Mnemonic: T2MOD
Address: C9h
BIT NAME
FUNCTION
Reserved.
External input capture 0 enable:
7~5 -
4
3
ICEN0
T2CR
This bit enables input capture 0 on T0 pin.
Timer 2 Capture Reset:
In the Timer 2 Capture Mode this bit enables/disables hardware automatically
reset timer 2 while the value in TL2 and TH2 have been transferred into the
capture register.
2
1
-
Must be 1.
T2OE
Timer 2 Output Enable. This bit enables/disables the Timer 2 clock out function.
Down Count Enable: This bit, in conjunction with the T2EX pin, controls the
direction that timer 2 counts in 16-bit auto-reload mode.
0
DCEN
TIMER 2 CAPTURE LSB
Bit:
7
6
5
4
3
2
1
0
RCAP2L.
RCAP2L.
RCAP2L.
RCAP2L.
RCAP2L.
RCAP2L.
RCAP2L.
RCAP2L.
Publication Release Date: Jul, 29, 2009
Revision A06
- 41 -
Preliminary N79E352/N79E352R Data Sheet
7
6
5
4
3
2
1
0
Mnemonic: RCAP2L
Address: CAh
BIT NAME
FUNCTION
Timer 2 Capture LSB:
This register is used to capture the TL2 value when a timer 2 is configured in
capture mode.RCAP2L is also used as the LSB of a 16-bit reload value when
timer 2 is configured in auto-reload mode.
7-0 RCAP2L
- 42 -
Preliminary N79E352/N79E352R Data Sheet
TIMER 2 CAPTURE MSB
Bit:
7
6
5
4
3
2
1
0
RCAP2H.
7
RCAP2H.
6
RCAP2H.
5
RCAP2H.
4
RCAP2H.
3
RCAP2H.
2
RCAP2H.
1
RCAP2H.
0
Mnemonic: RCAP2H
Address: CBh
BIT NAME
FUNCTION
Timer 2 Capture MSB:
This register is used to capture the TH2 value when a timer 2 is configured in
capture mode. RCAP2H is also used as the MSB of a 16-bit reload value when
timer 2 is configured in auto-reload mode.
7-0 RCAP2H
TIMER 2 LSB
Bit:
7
6
5
4
3
2
1
0
TL2.7
TL2.6
TL2.5
TL2.4
TL2.3
TL2.2
TL2.1
TL2.0
Mnemonic: TL2
Address: CCh
BIT NAME
FUNCTION
7-0 TL2
Timer 2 LSB.
TIMER 2 MSB
Bit:
7
6
5
4
3
2
1
0
TH2.7
TH2.6
TH2.5
TH2.4
TH2.3
TH2.2
TH2.1
TH2.0
Mnemonic: TH2
Address: CDh
BIT NAME
FUNCTION
7-0 TL2
Timer 2 LSB.
NVM CONTROL
Bit:
7
6
5
4
-
3
-
2
-
1
-
0
-
EER
EWR
EnNVM
Mnemonic: NVMCON
BIT NAME FUNCTION
Address: CEh
7
EER
NVM page(n) erase bit:
0: Without erase NVM page(n).
1: Set this bit to erase page(n) of NVM. The NVM has 8 pages and each page
have 16 bytes data memory. Initiate page select by programming NVMADDL
registers, which will automatically enable page area. When user set this bit,
the page erase process will begin and program counter will halt at this
instruction. After the erase process is completed, program counter will
continue executing next instruction.
6
EWR
NVM data write bit:
0: Without write NVM data.
Publication Release Date: Jul, 29, 2009
- 43 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
1: Set this bit to write NVM bytes and program counter will halt at this instruction.
After write is finished, program counter will kept next instruction then
executed.
5
EnNVM
To enable read NVM data memory area.
0: To disable the MOVX instruction to read NVM data memory.
1: To enable the MOVX instruction to read NVM data memory, the External RAM
or AUX-RAM will be disabled.
4-0
-
Reserved
NVM DATA
Bit:
7
6
5
4
3
2
1
0
NVMDAT. NVMDAT. NVMDAT. NVMDAT. NVMDAT
NVMDAT. NVMDAT. NVMDAT.
7
6
5
4
3
2
1
0
Mnemonic: NVMDATA
Address: CFh
BIT NAME
FUNCTION
7~0 NVMDAT.[7:0] The NVM data write register. The read NVM data is by MOVC instruction.
PROGRAM STATUS WORD
Bit:
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Mnemonic: PSW
Address: D0h
BIT
NAME
FUNCTION
Carry flag:
7
CY
Set for an arithmetic operation which results in a carry being generated from the
ALU. It is also used as the accumulator for the bit operations.
6
Auxiliary carry:
AC
F0
Set when the previous operation resulted in a carry from the high order nibble.
User flag 0:
5
The General purpose flag that can be set or cleared by the user.
4~3 RS1~RS0 Register bank select bits.
Overflow flag:
2
OV
Set when a carry was generated from the seventh bit but not from the 8th bit as
a result of the previous operation, or vice-versa.
User Flag 1:
1
0
F1
P
The General purpose flag that can be set or cleared by the user software.
Parity flag:
Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.
RS.1-0: Register Bank Selection Bits:
- 44 -
Preliminary N79E352/N79E352R Data Sheet
RS1
RS0
REGISTER BANK
ADDRESS
0
0
1
1
0
1
0
1
0
1
2
3
00-07h
08-0Fh
10-17h
18-1Fh
PWM CONTROL REGISTER 3
Bit:
7
6
5
4
3
2
1
0
-
-
PWM1OE PWM0OE PCLK.1
PCLK.0
FP1
FP0
Mnemonic: PWMCON3
BIT NAME FUNCTION
Reserved.
Address: D7h
7~6
5
-
PWM1 output enable bit.
0: PWM1 output disabled.
1: PWM1 output enabled.
PWM0 output enable bit.
0: PWM0 output disabled.
1: PWM0 output enabled.
PWM1OE
4
PWM0OE
PWM clock source selection bits, see below table.
PCLK[1:0]
PWM clock source
00
01
10
11
Fosc
3~2 PCLK.1~0
Timer 0 overflow
Timer 1 overflow
Reserved
Select PWM frequency pre-scale select bits, see belowtable.
FP[1:0]
00
Fpwm
FPCLK/1 (default)
FPCLK/2
1~0
FP1~0
01
10
FPCLK/4
11
FPCLK/8
WATCHDOG CONTROL
Bit:
7
6
5
-
4
-
3
2
1
0
WDRUN
POR
WDIF
WTRF
EWRST
WDCLR
Mnemonic: WDCON
BIT NAME FUNCTION
Address: D8h
Publication Release Date: Jul, 29, 2009
Revision A06
- 45 -
Preliminary N79E352/N79E352R Data Sheet
0: The Watchdog is stopped.
1: The Watchdog is running.
7
WDRUN
Power-on reset flag. Hardware will set this flag on a power up condition. This flag
can be read or written by software. A write by software is the only way to clear
this bit once it is set.
6
POR
-
5~4
Reserved.
Watchdog Timer Interrupt flag:
0: If the interrupt is not enabled, then this bit indicates that the time-out period
has elapsed. This bit must be cleared by software.
3
WDIF
1: If the watchdog interrupt is enabled, hardware will set this bit to indicate that
the watchdog interrupt has occurred.
Watchdog Timer Reset flag:
1: Hardware will set this bit when the watchdog timer causes a reset. Software
can read it but must clear it manually. A power-fail reset will also clear the bit.
This bit helps software in determining the cause of a reset. If EWRST = 0,
the watchdog timer will have no affect on this bit.
2
1
WTRF
0: Disable Watchdog Timer Reset.
1: Enable Watchdog Timer Reset.
Reset Watchdog Timer:
EWRST
This bit helps in putting the watchdog timer into a know state. It also helps in
resetting the watchdog timer before a time-out occurs. Failing to set the EWRST
before time-out will cause an interrupt (if EWDI (EIE.4) is set), and 512 clocks
after that a watchdog timer reset will be generated (if EWRST is set). This bit is
self-clearing by hardware.
0
WDCLR
The WDCON SFR is set to a 01xx0000B on a power-on-reset. WTRF (WDCON.2) is set to a 1 on a
Watchdog timer reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by an
external reset. EWRST (WDCON.1) is set to 0 on all resets.
All the bits in this SFR have unrestricted read access. WDRUN, POR, EWRST, WDIF and WDCLR
require Timed Access procedure to write. The remaining bits have unrestricted write accesses. Please
refer TA register description.
TA
REG
C7H
D8H
WDCON
MOV
MOV
SETB
ORL
REG
TA, #AAH
TA, #55H
WDCON.0
; To access protected bits
; Reset watchdog timer
WDCON, #00110000B
TA, #AAH
; Select 26 bits watchdog timer
MOV
MOV
ORL
TA, #55H
WDCON, #10000010B
; Enable watchdog
PWM 0 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
- 46 -
Preliminary N79E352/N79E352R Data Sheet
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.0
Mnemonic: PWM0L
Address: DAh
BIT NAME
FUNCTION
PWM 0 Low Bits Register.
7~0 PWM0
PWM 0 LOW BITS REGISTER
Bit:
7
6
5
4
3
2
1
0
PWM1.7
PWM1.6
PWM1.5
PWM1.4
PWM1.3
PWM1.2
PWM1.1
PWM1.0
Mnemonic: PWM1L
Address: DBh
BIT NAME
FUNCTION
7~0 PWM1
PWM 1 Low Bits Register.
PWM CONTROL REGISTER 1
Bit:
7
6
5
-
4
3
-
2
-
1
-
0
-
PWMRUN
-
CLRPWM
Mnemonic: PWMCON1
BIT NAME FUNCTION
Address: DCh
0: The PWM is not running.
1: The PWM counter is running.
Reserved.
7
PWMRUN
6~5
4
-
1: Clear 8-bit PWM counter to 000H.
It is automatically cleared by hardware.
Reserved.
CLRPWM
-
3~0
ACCUMULATOR
Bit:
7
6
5
4
3
2
1
0
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
Mnemonic: ACC
Address: E0h
BIT NAME
FUNCTION
7-0 ACC
The A or ACC register is the standard 8052 accumulator.
INPUT CAPTURE 0 LOW REGISTER
Bit:
7
6
5
4
3
2
1
0
CCL0.7
CCL0.6
CCL0.5
CCL0.4
CCL0.3
CCL0.2
CCL0.1
CCL0.0
Mnemonic: CCL0
Address: E4h
BIT NAME
FUNCTION
Capture 0 low byte.
7-0 CCL0
Publication Release Date: Jul, 29, 2009
Revision A06
- 47 -
Preliminary N79E352/N79E352R Data Sheet
INPUT CAPTURE 0 HIGH REGISTER
Bit:
7
6
5
4
3
2
1
0
CCH0.7
CCH0.6
CCH0.5
CCH0.4
CCH0.3
CCH0.2
CCH0.1
CCH0.0
Mnemonic: CCH0
Address: E4h
BIT NAME
FUNCTION
Capture 0 high byte.
7-0 CCH0
IINTERRUPT ENABLE REGISTER 1
Bit:
7
6
5
4
3
-
2
-
1
0
ECPTF
EBO
-
EWDI
EKB
EI2
Mnemonic: EIE
Address: E8h
BIT NAME
FUNCTION
0: Disable capture interrupt.
1: Enable capture interrupt.
Enable brownout interrupt.
0: Disable brownout interrupt.
1: Enable brownout interrupt.
Reserved.
7
ECPTF
6
EBO
5
4
-
0: Disable Watchdog Timer Interrupt.
1: Enable Watchdog Timer Interrupt.
Reserved.
EWDI
3~2 -
0: Disable Keypad Interrupt.
1: Enable Keypad Interrupt.
0: Disable I2C Interrupt.
1
0
EKB
EI2
1: Enable I2C Interrupt.
KEYBOARD LEVEL
Bit:
7
6
5
4
3
2
1
0
KBL.7
KBL.6
KBL.5
KBL.4
KBL.3
KBL.2
KBL.1
KBL.0
Mnemonic: KBL
Address: E9h
BIT NAME
FUNCTION
Keyboard trigger level.
0: Low level trigger.x pin.
7~0 KBL.7~0
1: High level trigger on KBI.x pin.
[x = 0-7]
PORTS SHMITT REGISTER
Bit:
7
6
5
4
3
2
1
0
- 48 -
Preliminary N79E352/N79E352R Data Sheet
-
-
P5S
-
P3S
P2S
P1S
P0S
Mnemonic: PORTS
BIT NAME
Address: ECh
FUNCTION
-
Reserved.
7~6
5
P5S
-
1: Enables Schmitt trigger inputs on Port 5.
Reserved.
4
P3S
P2S
P1S
P0S
1: Enables Schmitt trigger inputs on Port 3.
1: Enables Schmitt trigger inputs on Port 2.
1: Enables Schmitt trigger inputs on Port 1.
1: Enables Schmitt trigger inputs on Port 0.
3
2
1
0
PORT 5 OUTPUT MODE 1
Bit:
7
6
5
-
4
-
3
-
2
1
0
-
-
ENCLK
P5M1.1
P5M1.0
Mnemonic: P5M1
Address: EDh
BIT NAME
FUNCTION
Reserved.
1: Enabled clock output to XTAL2 pin (P5.0).
7~3
2
-
ENCLK
1~0 P5M1.1~0 To control the output configuration of P5 bits [1:0].
PORT 5 OUTPUT MODE 2
Bit:
7
6
5
-
4
-
3
-
2
-
1
0
-
-
P5M2.1
P5M2.0
Mnemonic: P5M2
Address: EEh
BIT NAME
FUNCTION
Reserved.
7~2
-
1~0 P5M2.1~0 To control the output configuration of P5 bits [1:0].
B REGISTER
Bit:
7
6
5
4
3
2
1
0
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
Mnemonic: B
Address: F0h
BIT NAME
FUNCTION
7-0
B
The B register is the standard 8052 register that serves as a second
accumulator.
INTERRUPT HIGH PRIORITY 1
Bit:
7
6
5
4
3
2
1
0
Publication Release Date: Jul, 29, 2009
Revision A06
- 49 -
Preliminary N79E352/N79E352R Data Sheet
PCAPH
Mnemonic: IP1H
BIT NAME
PBOH
-
PWDIH
-
-
PKBH
PI2H
Address: F7h
FUNCTION
1: To set interrupt high priority of Input Capture 0 as highest priority level.
PCAPH
PBOH
-
7
1: To set interrupt high priority of Brownout is highest priority level.
Reserved.
6
5
PWDIH
-
1: To set interrupt high priority of Watchdog is highest priority level.
Reserved.
4
3~2
1
PKBH
PI2H
1: To set interrupt high priority of Keypad is highest priority level.
1: To set interrupt high priority of I2C is highest priority level.
0
INTERRUPT PRIORITY 1
Bit:
7
6
5
-
4
3
-
2
-
1
0
PCAP
PBO
PWDI
PKB
PI2
Mnemonic: IP1
Address: F8h
BIT NAME
FUNCTION
PCAP
PBO
-
1: To set interrupt priority of Input Capture 0 as higher priority level.
1: To set interrupt priority of Brownout is higher priority level.
Reserved.
7
6
5
PWDI
-
1: To set interrupt priority of Watchdog is higher priority level.
Reserved.
4
3~2
1
PKB
PI2
1: To set interrupt priority of Keypad is higher priority level.
1: To set interrupt priority of I2C is higher priority level.
0
- 50 -
Preliminary N79E352/N79E352R Data Sheet
9. INSTRUCTION
The N79E352(R) executes all the instructions of the standard 8052 family. The operation of these
instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of
these instructions is different. The reason for this is two fold. Firstly, in the N79E352(R), each machine
cycle consists of 4 clock periods, while in the standard 8052 it consists of 12 clock periods. Also, in the
N79E352(R) there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard
8052 there can be two fetches per machine cycle, which works out to 6 clocks per fetch.
The advantage the N79E352(R) has is that since there is only one fetch per machine cycle, the number
of machine cycles in most cases is equal to the number of operands that the instruction has. In case of
jumps and calls there will be an additional cycle that will be needed to calculate the new address. But
overall the N79E352(R) reduces the number of dummy fetches and wasted cycles, thereby improving
efficiency as compared to the standard 8052.
Table 9-1: Instructions that affect Flag settings
Auxiliary
Carry
Auxiliary
Carry
Instruction
Carry
Overflow
Instruction
Carry
Overflow
ADD
X
X
X
0
X
X
X
X
X
X
X
X
CLR C
CPL C
0
X
X
X
X
X
X
X
ADDC
SUBB
MUL
ANL C, bit
ANL C, bit
ORL C, bit
ORL C, bit
MOV C, bit
CJNE
DIV
0
DA A
X
X
X
1
RRC A
RLC A
SETB C
A "X" indicates that the modification is as per the result of instruction.
Publication Release Date: Jul, 29, 2009
Revision A06
- 51 -
Preliminary N79E352/N79E352R Data Sheet
Table 9-2: Instruction Timing for N79E352(R)
N79E352(R)
Machine
Cycles
N79E352(R)
Clock
Cycles
8052
Clock
Cycles
N79E352(R) vs.
8052 Speed
Ratio
HEX
Op-Code
Instruction
Bytes
NOP
00
28
29
2A
2B
2C
2D
2E
2F
26
27
25
24
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
4
4
4
4
4
4
4
4
4
4
4
8
8
12
12
12
12
12
12
12
12
12
12
12
12
12
3
3
ADD A, R0
ADD A, R1
ADD A, R2
ADD A, R3
ADD A, R4
ADD A, R5
ADD A, R6
ADD A, R7
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
3
3
3
3
3
3
3
3
3
1.5
1.5
- 52 -
Preliminary N79E352/N79E352R Data Sheet
Instruction Timing for N79E352(R), continued
N79E352(R)
Machine
Cycles
N79E352(R)
Clock
Cycles
8052
Clock
Cycles
N79E352(R) vs.
8052 Speed
Ratio
HEX
Instruction
Bytes
Op-Code
ADDC A, R0
ADDC A, R1
ADDC A, R2
ADDC A, R3
ADDC A, R4
ADDC A, R5
ADDC A, R6
ADDC A, R7
ADDC A, @R0
ADDC A, @R1
ADDC A, direct
ADDC A, #data
38
39
3A
3B
3C
3D
3E
3F
36
37
35
34
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
4
4
4
4
4
4
4
4
4
4
8
8
12
12
12
12
12
12
12
12
12
12
12
12
3
3
3
3
3
3
3
3
3
3
1.5
1.5
71, 91, B1, 11,
31, 51, D1, F1
ACALL addr11
AJMP ADDR11
2
2
3
3
12
12
24
24
2
2
01, 21, 41, 61,
81, A1, C1, E1
ANL A, R0
58
59
5A
5B
5C
5D
5E
5F
56
57
55
54
52
53
82
B0
B5
B4
B6
B7
B8
B9
BA
BB
BC
BD
BE
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
12
12
12
12
12
12
12
12
12
12
12
12
12
24
24
24
24
24
24
24
24
24
24
24
24
24
24
3
3
ANL A, R1
ANL A, R2
4
3
ANL A, R3
4
3
ANL A, R4
4
3
ANL A, R5
4
3
ANL A, R6
4
3
ANL A, R7
4
3
ANL A, @R0
4
3
ANL A, @R1
4
3
ANL A, direct
8
1.5
1.5
1.5
2
ANL A, #data
8
ANL direct, A
8
ANL direct, #data
ANL C, bit
12
8
3
ANL C, /bit
8
3
CJNE A, direct, rel
CJNE A, #data, rel
CJNE @R0, #data, rel
CJNE @R1, #data, rel
CJNE R0, #data, rel
CJNE R1, #data, rel
CJNE R2, #data, rel
CJNE R3, #data, rel
CJNE R4, #data, rel
CJNE R5, #data, rel
CJNE R6, #data, rel
16
16
16
16
16
16
16
16
16
16
16
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Publication Release Date: Jul, 29, 2009
Revision A06
- 53 -
Preliminary N79E352/N79E352R Data Sheet
Instruction Timing for N79E352(R), continued
N79E352(R)
Machine
Cycles
N79E352(R)
Clock
Cycles
8052
Clock
Cycles
N79E352(R) vs.
8052 Speed
Ratio
HEX
Op-Code
Instruction
Bytes
CLR A
CPL A
CLR C
E4
F4
C3
C2
B3
B2
14
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
2
2
2
2
2
2
2
3
1
1
1
1
1
1
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
2
2
5
1
3
3
3
3
3
3
3
3
4
1
1
1
1
1
1
4
4
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
-
3
3
4
3
CLR bit
8
1.5
3
CPL C
4
CPL bit
8
1.5
3
DEC A
4
DEC R0
18
4
3
DEC R1
19
4
3
DEC R2
1A
1B
1C
1D
1E
1F
16
4
3
DEC R3
4
3
DEC R4
4
3
DEC R5
4
3
DEC R6
4
3
DEC R7
4
3
DEC @R0
DEC @R1
DEC direct
DEC DPTR
DIV AB
4
3
17
4
3
15
8
1.5
-
A5
84
8
20
4
48
12
24
24
24
24
24
24
24
24
24
12
12
12
12
12
12
2.4
3
DA A
D4
D8
D9
DD
DA
DB
DC
DE
DF
D5
04
DJNZ R0, rel
DJNZ R1, rel
DJNZ R5, rel
DJNZ R2, rel
DJNZ R3, rel
DJNZ R4, rel
DJNZ R6, rel
DJNZ R7, rel
DJNZ direct, rel
INC A
12
12
12
12
12
12
12
12
16
4
2
2
2
2
2
2
2
2
1.5
3
INC R0
08
4
3
INC R1
09
4
3
INC R2
0A
0B
0C
4
3
INC R3
4
3
INC R4
4
3
- 54 -
Preliminary N79E352/N79E352R Data Sheet
Instruction Timing for N79E352(R), continued
N79E352(R)
Machine
Cycles
N79E352(R)
Clock
Cycles
8052
Clock
Cycles
N79E352(R) vs.
8052 Speed
Ratio
HEX
Op-Code
Instruction
Bytes
INC R6
INC R7
0E
0F
06
07
05
A3
73
60
70
40
50
20
30
10
12
02
A4
E8
E9
EA
EB
EC
ED
EE
EF
E6
E7
E5
74
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
2
1
1
2
2
2
2
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
3
3
3
3
4
4
4
4
4
5
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
4
4
12
12
12
12
12
24
24
24
24
24
24
24
24
24
24
24
48
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
3
3
INC @R0
4
3
INC @R1
4
3
INC direct
8
1.5
3
INC DPTR
JMP @A+DPTR
JZ rel
8
8
3
12
12
12
12
16
16
16
16
16
20
4
2
JNZ rel
2
JC rel
2
JNC rel
2
JB bit, rel
1.5
1.5
1.5
1.5
1.5
2.4
3
JNB bit, rel
JBC bit, rel
LCALL addr16
LJMP addr16
MUL AB
MOV A, R0
MOV A, R1
MOV A, R2
MOV A, R3
MOV A, R4
MOV A, R5
MOV A, R6
MOV A, R7
MOV A, @R0
MOV A, @R1
MOV A, direct
MOV A, #data
MOV R0, A
MOV R1, A
MOV R2, A
MOV R3, A
MOV R4, A
MOV R5, A
MOV R6, A
MOV R7, A
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
8
1.5
1.5
3
8
4
4
3
4
3
4
3
4
3
4
3
4
3
4
3
Publication Release Date: Jul, 29, 2009
Revision A06
- 55 -
Preliminary N79E352/N79E352R Data Sheet
Instruction Timing for N79E352(R), continued
N79E352(R)
Machine
Cycles
N79E352(R)
Clock
Cycles
8052
Clock
Cycles
N79E352(R) vs.
8052 Speed
Ratio
HEX
Op-Code
Instruction
Bytes
MOV R1, direct
A9
AA
AB
AC
AD
AE
AF
78
79
7A
7B
7C
7D
7E
7F
F6
F7
A6
A7
76
77
F5
88
89
8A
8B
8C
8D
8E
8F
86
87
85
75
90
93
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
12
12
12
8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
24
24
24
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
3
MOV R2, direct
MOV R3, direct
MOV R4, direct
MOV R5, direct
MOV R6, direct
MOV R7, direct
MOV R0, #data
MOV R1, #data
MOV R2, #data
MOV R3, #data
MOV R4, #data
MOV R5, #data
MOV R6, #data
MOV R7, #data
MOV @R0, A
MOV @R1, A
3
MOV @R0, direct
MOV @R1, direct
MOV @R0, #data
MOV @R1, #data
MOV direct, A
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
MOV direct, R0
MOV direct, R1
MOV direct, R2
MOV direct, R3
MOV direct, R4
MOV direct, R5
MOV direct, R6
MOV direct, R7
MOV direct, @R0
MOV direct, @R1
MOV direct, direct
MOV direct, #data
MOV DPTR, #data 16
MOVC A, @A+DPTR
2
2
3
- 56 -
Preliminary N79E352/N79E352R Data Sheet
Instruction Timing for N79E352(R), continued
N79E352(R)
Machine
Cycles
N79E352(R)
Clock
Cycles
8052
Clock
Cycles
N79E352(R) vs.
8052 Speed
Ratio
HEX
Op-Code
Instruction
Bytes
MOVX A, @R0
E2
E3
E0
F2
F3
F0
A2
92
48
49
4A
4B
4C
4D
4E
4F
46
47
45
44
42
43
72
A0
C0
D0
22
32
23
33
03
13
D3
D2
C4
80
98
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
2
2
1
1
1
1
1
1
1
2
1
2
1
2 - 9
8 - 36
24
24
24
24
24
24
12
24
12
12
12
12
12
12
12
12
12
12
12
12
12
24
24
24
24
24
24
24
12
12
12
12
12
12
12
24
12
3 - 0.66
MOVX A, @R1
MOVX A, @DPTR
MOVX @R0, A
MOVX @R1, A
MOVX @DPTR, A
MOV C, bit
MOV bit, C
ORL A, R0
ORL A, R1
ORL A, R2
ORL A, R3
ORL A, R4
ORL A, R5
ORL A, R6
ORL A, R7
ORL A, @R0
ORL A, @R1
ORL A, direct
ORL A, #data
ORL direct, A
ORL direct, #data
ORL C, bit
ORL C, /bit
PUSH direct
POP direct
RET
2 - 9
8 - 36
3 - 0.66
2 - 9
2 - 9
2 - 9
2 - 9
2
8 - 36
3 - 0.66
8 - 36
3 - 0.66
8 - 36
3 - 0.66
8 - 36
8
3 - 0.66
1.5
3
2
8
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
1
4
3
2
8
1.5
1.5
1.5
2
2
8
2
8
3
12
8
2
3
2
6
3
2
8
3
2
8
3
2
8
3
RETI
2
8
3
RL A
1
4
3
RLC A
1
4
3
RR A
1
4
3
RRC A
1
4
3
SETB C
1
4
3
SETB bit
2
8
1.5
3
SWAP A
1
4
SJMP rel
3
12
4
2
SUBB A, R0
1
3
Publication Release Date: Jul, 29, 2009
Revision A06
- 57 -
Preliminary N79E352/N79E352R Data Sheet
Instruction Timing for N79E352(R), continued
N79E352(R)
Machine
Cycles
N79E352(R)
Clock
Cycles
8052
Clock
Cycles
N79E352(R) vs.
8052 Speed
Ratio
HEX
Op-Code
Instruction
Bytes
SUBB A, R2
9A
9B
9C
9D
9E
9F
96
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
4
4
4
4
8
4
4
4
4
4
4
4
4
4
4
8
8
8
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
24
3
3
SUBB A, R3
SUBB A, R4
SUBB A, R5
SUBB A, R6
SUBB A, R7
SUBB A, @R0
SUBB A, @R1
SUBB A, direct
SUBB A, #data
XCH A, R0
3
3
3
3
3
97
3
95
1.5
1.5
3
94
C8
C9
CA
CB
CC
CD
CE
CF
C6
C7
D6
D7
C5
68
XCH A, R1
3
XCH A, R2
3
XCH A, R3
3
XCH A, R4
3
XCH A, R5
3
XCH A, R6
3
XCH A, R7
3
XCH A, @R0
XCH A, @R1
XCHD A, @R0
XCHD A, @R1
XCH A, direct
XRL A, R0
3
3
3
3
1.5
3
XRL A, R1
69
3
XRL A, R2
6A
6B
6C
6D
6E
6F
66
3
XRL A, R3
3
XRL A, R4
3
XRL A, R5
3
XRL A, R6
3
XRL A, R7
3
XRL A, @R0
XRL A, @R1
XRL A, direct
XRL A, #data
XRL direct, A
XRL direct, #data
3
67
3
65
1.5
1.5
1.5
2
64
62
63
9.1 Instruction Timing
- 58 -
Preliminary N79E352/N79E352R Data Sheet
The instruction timing for the N79E352(R) is an important aspect, especially for those users who wish
to use software instructions to generate timing delays. Also, it provides the user with an insight into the
timing differences between the N79E352(R) and the standard 8052. In the N79E352(R) each machine
cycle is four clock periods long. Each clock period is designated a state. Thus each machine cycle is
made up of four states, C1, C2 C3 and C4, in that order. Due to the reduced time for each instruction
execution, both the clock edges are used for internal timing. Hence it is important that the duty cycle of
the clock be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the
N79E352(R) does one op-code fetch per machine cycle. Therefore, in most of the instructions, the
number of machine cycles needed to execute the instruction is equal to the number of bytes in the
instruction. Of the 256 available op-codes, 128 of them are single cycle instructions. Thus more than
half of all op-codes in the N79E352(R) are executed in just four clock periods. Most of the two-cycle
instructions are those that have two byte instruction codes. However there are some instructions that
have only one byte instructions, yet they are two cycle instructions. One instruction which is of
importance is the MOVX instruction. In the standard 8052, the MOVX instruction is always two machine
cycles long. However in the N79E352(R), the user has a facility to stretch the duration of this instruction
from 2 machine cycles to 9 machine cycles. The RD and WR strobe lines are also proportionately
elongated. This gives the user flexibility in accessing both fast and slow peripherals without the use of
external circuitry and with minimum software overhead. The rest of the instructions are either three,
four or five machine cycle instructions. Note that in the N79E352(R), based on the number of machine
cycles, there are five different types, while in the standard 8052 there are only three. However, in the
N79E352(R) each machine cycle is made of only 4 clock periods compared to the 12 clock periods for
the standard 8052. Therefore, even though the number of categories has increased, each instruction is
at least 1.5 to 3 times faster than the standard 8052 in terms of clock periods.
Single Cycle
C4
C1
C2
C3
CLK
ALE
PSEN
AD7-0
A7-0
Data_ in D7-0
Address A15-8
PORT 2
Figure 9-1: Single Cycle Instruction Timing
Publication Release Date: Jul, 29, 2009
Revision A06
- 59 -
Preliminary N79E352/N79E352R Data Sheet
Operand Fetch
Instruction Fetch
C1
C2
C3
C4
C1
C2
C3
C4
CLK
ALE
PSEN
OP-CODE
PC
PC+1
OPERAND
AD7-0
Address A15-8
Address A15-8
PORT 2
Figure 9-2: Two Cycle Instruction Timing
Instruction Fetch
C2 C3
Operand Fetch
Operand Fetch
C1
C4
C1
C2
C3
C4
C1
C2
C3
C4
CLK
ALE
PSEN
AD7-0
A7-0
OPERAND
A7-0
OP-CODE
A7-0
OPERAND
Address A15-8
Address A15-8
Address A15-8
PORT 2
Figure 9-3: Three Cycle Instruction Timing
- 60 -
Preliminary N79E352/N79E352R Data Sheet
Operand Fetch
C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
Instruction Fetch
Operand Fetch
Operand Fetch
C1
CLK
ALE
PSEN
AD7-0
OP-CODE
A7-0 OPERAND
Address A15-8
OPERAND
A7-0
OPERAND
A7-0
A7-0
Port 2
Address A15-8
Address A15-8
Address A15-8
Figure 9-4: Four Cycle Instruction Timing
Operand Fetch
Instruction Fetch
Operand Fetch
Operand Fetch
Operand Fetch
C1
C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
A7-0
A7-0
A7-0
A7-0
A7-0
OPERAND
OP-CODE
OPERAND
OPERAND
OPERAND
AD7-0
Address A15-8
Address A15-8
Address A15-8
Address A15-8
Address A15-8
PORT 2
Figure 9-5: Five Cycle Instruction Timing
Publication Release Date: Jul, 29, 2009
Revision A06
- 61 -
Preliminary N79E352/N79E352R Data Sheet
9.2 MOVX Instruction
The N79E352(R), like the standard 8052, uses the MOVX instruction to access external Data Memory.
This Data Memory includes both off-chip memory as well as memory mapped peripherals. While the
results of the MOVX instruction are the same as in the standard 8052, the operation and the timing of
the strobe signals have been modified in order to give the user much greater flexibility.
The MOVX instruction is of two types, the MOVX @Ri and MOVX @DPTR. In the MOVX @Ri, the
address of the external data comes from two sources. The lower 8-bits of the address are stored in the
Ri register of the selected working register bank. The upper 8-bits of the address come from the port 2
SFR. In the MOVX @DPTR type, the full 16-bit address is supplied by the Data Pointer.
Since the N79E352(R) has two Data Pointers, DPTR and DPTR1, the user has to select between the
two by setting or clearing the DPS bit. The Data Pointer Select bit (DPS) is the LSB of the DPS SFR,
which exists at location 86h. No other bits in this SFR have any effect, and they are set to 0. When
DPS is 0, then DPTR is selected, and when set to 1, DPTR1 is selected. The user can switch between
DPTR and DPTR1 by toggling the DPS bit. The quickest way to do this is by the INC instruction. The
advantage of having two Data Pointers is most obvious while performing block move operations. The
accompanying code shows how the use of two separate Data Pointers speeds up the execution time
for code performing the same task.
Block Move with single Data Pointer:
; SH and SL are the high and low bytes of Source Address
; DH and DL are the high and low bytes of Destination Address
; CNT is the number of bytes to be moved
Machine Cycles of
N79E352(R)
#
MOV R2, #CNT
MOV R3, #SL
MOV R4, #SH
MOV R5, #DL
MOV R6, #DH
; Load R2 with the count value
2
2
2
2
2
; Save low byte of Source Address in R3
; Save high byte of Source address in R4
; Save low byte of Destination Address in R5
; Save high byte of Destination address in R6
LOOP:
MOV DPL, R3
MOV DPH, R4
MOVX A, @DPTR
; Load DPL with low byte of Source address
; Load DPH with high byte of Source address
; Get byte from Source to Accumulator
; Increment Source Address to next byte
; Save low byte of Source address in R3
; Save high byte of Source Address in R4
; Load low byte of Destination Address in DPL
; Load high byte of Destination Address in DPH
; Write data to destination
2
2
2
2
2
2
2
2
2
2
INC
DPTR
MOV R3, DPL
MOV R4, DPH
MOV DPL, R5
MOV DPH, R6
MOVX @DPTR, A
INC
DPTR
; Increment Destination Address
MOV DPL, R5
MOV DPH, R6
DJNZ R2, LOOP
; Save low byte of new destination address in R5 2
; Save high byte of new destination address in R6
; Decrement count and do LOOP again if count <> 0
2
2
- 62 -
Preliminary N79E352/N79E352R Data Sheet
Machine cycles in standard 8052 = 10 + (26 * CNT)
Machine cycles in N79E352(R) = 10 + (26 * CNT)
If CNT = 50
Clock cycles in standard 8052= ((10 + (26 *50)) * 12 = (10 + 1300) * 12 = 15720
Clock cycles in N79E352(R) = ((10 + (26 * 50)) * 4 = (10 + 1300) * 4 = 5240
Block Move with Two Data Pointers in N79E352(R):
; SH and SL are the high and low bytes of Source Address
; DH and DL are the high and low bytes of Destination Address
; CNT is the number of bytes to be moved
Machine Cycles of N79E352(R)
#
2
2
3
2
3
MOV R2, #CNT
MOV DPS, #00h
MOV DPTR, #DHDL ; Load DPTR with Destination address
INC DPS ; Set DPS to point to DPTR1
; Load R2 with the count value
; Clear DPS to point to DPTR
MOV DPTR, #SHSL ; Load DPTR1 with Source address
LOOP:
MOVX A, @DPTR
; Get data from Source block
; Increment source address
; Clear DPS to point to DPTR
; Write data to Destination
; Increment destination address
; Set DPS to point to DPTR1
; Check if all done
2
2
2
2
2
2
3
INC
DEC
DPTR
DPS
MOVX @DPTR, A
INC
INC
DPTR
DPS
DJNZ R2, LOOP
Machine cycles in N79E352(R) = 12 + (15 * CNT)
If CNT = 50
Clock cycles in N79E352(R) = (12 + (15 * 50)) * 4 = (12 + 750) * 4 = 3048
We can see that in the first program the standard 8052 takes 15720 cycles, while the N79E352(R)
takes only 5240 cycles for the same code. In the second program, written for the N79E352(R),
program execution requires only 3048 clock cycles. If the size of the block is increased then the saving
is even greater.
9.3 External Data Memory Access Timing
The timing for the MOVX instruction is another feature of the N79E352(R). In the standard 8052, the
MOVX instruction has a fixed execution time of 2 machine cycles. However in the N79E352(R), the
duration of the access can be varied by the user.
The instruction starts off as a normal op-code fetch of 4 clocks. In the next machine cycle, the
N79E352(R) puts out the address of the external Data Memory and the actual access occurs here. The
user can change the duration of this access time by setting the STRETCH value. The Clock Control
SFR (CKCON) has three bits that control the stretch value. These three bits are M2-0 (bits 2-0 of
CKCON). These three bits give the user 8 different access time options. The stretch can be varied
from 0 to 7, resulting in MOVX instructions that last from 2 to 9 machine cycles in length. Note that the
stretching of the instruction only results in the elongation of the MOVX instruction, as if the state of the
CPU was held for the desired period. There is no effect on any other instruction or its timing. By
Publication Release Date: Jul, 29, 2009
- 63 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
default, the Stretch value is set at 1, giving a MOVX instruction of 3 machine cycles. If desired by the
user the stretch value can be set to 0 to give the fastest MOVX instruction of only 2 machine cycles.
Table 9-3: Data Memory Cycle Stretch Values
RD or WR
strobe width
in Clocks
RD or WR
strobe width
@ 20 MHz
Machine
Cycles
M2
M1
M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
100 nS
200 nS
400 nS
600 nS
800 nS
1000 nS
1200 nS
1400 nS
3 (default)
4
4
5
6
7
8
9
8
12
16
20
24
28
Second
Next Instruction
Machine Cycle
Last Cycle
First
Machine cycle
of Previous
Instruction
Machine cycle
MOVX instruction cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
WR
A0-A7
A0-A7
D0-D7
D0-D7
D0-D7
A0-A7
A0-A7
D0-D7
PORT 0
MOVX Data
Address
Next Inst.
Address
MOVX Inst.
Address
MOVX Inst
.
Next Inst. Read
MOVX Data out
A15-A8
A15-A8
A15-A8
A15-A8
PORT 2
Figure 9-6: Data Memory Write with Stretch Value = 0
- 64 -
Preliminary N79E352/N79E352R Data Sheet
Last Cycle
First
Second
Third
Next Instruction
Machine Cycle
of Previous
Instruction
Machine Cycle Machine Cycle Machine Cycle
MOVX instruction cycle
C1 C2 C3 C4 C1
C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
C2
CLK
ALE
PSEN
WR
A0-A7
A0-A7
A0-A7
D0-D7
A0-A7
D0-D7
D0-D7
D0-D7
PORT 0
MOVX Inst.
Address
Next Inst.
Address
MOVX Data
Address
MOVX Data out
A15-A8
Next Inst.
Read
MOVX Inst.
A15-A8
A15-A8
A15-A8
PORT 2
Figure 9-7: Data Memory Write with Stretch Value = 1
Publication Release Date: Jul, 29, 2009
Revision A06
- 65 -
Preliminary N79E352/N79E352R Data Sheet
First
Second
Third
Fourth
Last Cycle
Next
Instruction
Machine Cycle
Machine Cycle
Machine Cycle
Machine Cycle
Machine Cycle
of Previous
Instruction
MOVX instruction cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
WR
A0-A7
A0-A7
A0-A7
A0-A7
D0-D7
D0-D7
D0-D7
D0-D7
PORT 0
MOVX Inst.
Address
Next Inst.
Address
MOVX Data
Address
MOVX Data out
Next Inst.
Read
MOVX Inst.
A15-A8
A15-A8
A15-A8
A15-A8
PORT 2
Figure 9-8: Data Memory Write with Stretch Value = 2
9.4 Wait State Control Signal
Either with the software using stretch value to change the required machine cycle of MOVX instruction,
the N79E352(R) provides another hardware signal WAIT to implement the wider duration of external
data access timing. This wait state control signal is the alternate function of P4.0. The wait state control
signal can be enabled by setting WS (SFR ROMMAP.7) bit. When enabled, the setting of stretch value
decides the minimum length of MOVX instruction cycle and the device will sample the WAIT pin at
each C2 state before the rising edge of read/write strobe signal during MOVX instruction. Once this
signal being recongnized, one more machine cycle (wait state cycle) will be inserted into next cycle.
The inserted wait state cycles are unlimited, so the MOVX instruction cycle will end in which the wait
state control signal is deactivated. Using wait state control signal allows a dynamically access timimg to
a selected external peripheral. The WS bit is accessed by the Timed Access Protection procedure.
- 66 -
Preliminary N79E352/N79E352R Data Sheet
10. POWER MANAGEMENT
The N79E352(R) has several features that help the user to control the power consumption of the
device. The power saving features are basically the POWER DOWN mode, ECONOMY mode and
the IDLE mode of operation.
10.1 Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer and Serial port
blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program
Status Word, the Accumulator and the other registers hold their contents. The port pins hold the logical
states they had at the time Idle was activated. The Idle mode can be terminated in two ways. Since the
interrupt controller is still active, the activation of any enabled interrupt can wake up the processor. This
will automatically clear the Idle bit, terminate the Idle mode, and the Interrupt Service Routine(ISR) will
be executed. After the ISR, execution of the program will continue from the instruction which put the
device into Idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either by
applying a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The
external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be
recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is already running there is no delay and execution
starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out
will cause a watchdog timer interrupt which will wake up the device. The software must reset the
Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.
When the N79E352(R) is exiting from an Idle mode with a reset, the instruction following the one which
put the device into Idle mode is not executed. So there is no danger of unexpected writes.
10.2 Economy Mode
The power consumption of microcontroller relates to operating frequency. The N79E352(R) offers a
Economy mode to reduce the internal clock rate dynamically without external components. By default,
one machine cycle needs 4 clocks. In Economy mode, software can select 4, 64 or 1024 clocks per
machine cycle. It keeps the CPU operating at a acceptable speed but eliminates the power
consumption. In the Idle mode, the clock of the core logic is stopped, but all clocked peripherals such
as watchdog timer are still running at a rate of clock/4. In the Economy mode, all clocked peripherals
run at the same reduced clocks rate as in core logic. So the Economy mode may provide a lower
power consumption than idle mode.
Software invokes the Economy mode by setting the appropriate bits in the SFRs. Setting the bits
CD0(PMR.6), CD1(PMR.7) decides the instruction cycle rate as below:
CD1 CD0
Clocks/Machine Cycle
0
1
1
X
0
1
4 (default)
64
1024
The selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching
to divide by 64 or 1024 mode must first go from divide by 4 mode. This means software can not switch
directly between clock/64 and clock/1024 mode. The CPU has to return clock/4 mode first, then go to
clock/64 or clock/1024 mode.
In Economy mode, the serial port can not receive/transmit data correctly because the baud rate is
changed. In some systems, the external interrupts may require the fastest process such that the
Publication Release Date: Jul, 29, 2009
- 67 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
reducing of operating speed is restricted. In order to solve these dilemmas, the N79E352(R) offers a
switchback feature which allows the CPU back to clock/4 mode immediately when triggered by serial
operation (uart and I2C) or external interrupts. The switchback feature is enabled by setting the SWB
bit (PMR.5). A serial port/I2C reception/transmission or qualified external interrupt which is enabled
and acknowledged without block conditions will cause CPU to return to divide by 4 mode. For the serial
port reception, a switchback is generated by a falling edge associated with start bit if the serial port
reception is enabled. When a serial port transmission, an instruction which writes a byte of data to
serial port buffer will cause a switchback to ensure the correct transmission. The switchback feature is
unaffected by serial port interrupt flags. Similarly for I2C reception/transmission, a switchback is
generated when a start condition is determined. After a switchback is generated, the software can
manually return the CPU to Economy mode. Note that the modification of clock control bits CD0 and
CD1 will be ignored during I2C or serial port transmit/receive when switchback is enabled. The
Watchdog timer reset, power-on/fail reset, software reset, brownout reset or external reset will force
the CPU to return to divide by 4 mode.
10.3 Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this
will be the last instruction to be executed before the device goes into Power Down mode. In the Power
Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN pins are pulled low. The port pins output the values held by their respective SFRs.
The N79E352(R) will exit the Power Down mode with a reset or by an external interrupt pin. An
external reset can be used to exit the Power down state. The high on RST pin terminates the Power
Down mode, and restarts the clock. The program execution will restart from 0000h. In the Power down
mode, the clock is stopped, so the Watchdog timer cannot be used to provide the reset to exit Power
down mode when its clock source is external OSC or crystal.
The sources that can wake up from the power down mode are external interrupts, keyboard interrupt
(KBI), brownout reset (BOR), and watchdog timer interrupt (if WDTCK = 0).
The N79E352(R) can be woken from the Power Down mode by forcing an external interrupt pin
activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and
the external input has been set to a level detect mode. If these conditions are met, then the low level
on the external pin re-starts the oscillator. Then device executes the interrupt service routine for the
corresponding external interrupt. After the interrupt service routine is completed, the program execution
returns to the instruction after the one which put the device into Power Down mode and continues from
there.
- 68 -
Preliminary N79E352/N79E352R Data Sheet
11. RESET CONDITIONS
The user has several hardware related options for placing the N79E352(R) into reset condition. In
general, most register bits go to their reset value irrespective of the reset condition, but there are a few
flags whose state depends on the source of reset. The user can use these flags to determine the
cause of reset using software.
11.1 Sources of reset
11.1.1 External Reset
The device samples the RST pin every machine cycle during state C4. The RST pin must be held high
for at least two machine cycles before the reset circuitry applies an internal reset signal. Thus, this
reset is a synchronous operation and requires the clock to be running.
The device remains in the reset state as long as RST pin is high and remains high up to two machine
cycles after RST is deactivated. Then, the device begins program execution at 0000h. There are no
flags associated with the external reset, but, since the other two reset sources do have flags, the
external reset is the cause if those flags are clear.
11.1.2 Power-On Reset (POR)
When the power supply rises to the configured level, VRST, the device will perform a power on reset and
set the POR flag. The software should clear the POR flag, or it will be difficult to determine the source
of future resets.
11.1.3 Brown-Out Reset (BOR)
If the power supply falls below brownout voltage of VBOV, the device goes into the reset state. When the
power supply returns to proper levels, the device performs a brownout reset.
11.1.4 Watchdog Timer Reset
The Watchdog Timer is a free-running timer with programmable time-out intervals. The program must
clear the Watchdog Timer before the time-out interval is reached to restart the count. If the time-out
interval is reached, an interrupt flag is set. 512 clocks later, if the Watchdog Reset is enabled and the
Watchdog Timer has not been cleared, the Watchdog Timer generates a reset. The reset condition is
maintained by the hardware for two machine cycles, and the WTRF bit in WDCON is set. Afterwards,
the device begins program execution at 0000h.
11.1.5 Software Reset
N79E352(R) is enhanced by a software reset. This allows the program code to reset the whole system
in software approach. Just writer 1 to SRET bit in AUXR1.3, a software reset will perform. Note that
SRST require Timed Access procedure to write. Please refer TA register description
11.2 Reset State
When the device is reset, most registers return to their initial state. The Watchdog Timer is disabled if
the reset source was a power-on reset. The Program Counter is set to 0000h, and the stack pointer is
reset to 07h. After this, the device remains in the reset state as long as the reset conditions are
satisfied.
Publication Release Date: Jul, 29, 2009
- 69 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
Reset does not affect the on-chip RAM, however, so RAM is preserved as long as VDD remains above
approximately 2V, the minimum operating voltage for the RAM. If VDD falls below 2V, the RAM
contents are also lost. In either case, the stack pointer is always reset, so the stack contents are lost.
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset
0xxx0x00b
Watchdog reset
0xxx0100b
Power on reset
01xx0000b
WDCON
The POR bit WDCON.6 is set only by the power on reset. WTRF bit WDCON.2 is set when the
Watchdog timer causes a reset. A power on reset will also clear this bit. The EWRST bit WDCON.1 is
cleared by all reset. This disables the Watchdog timer resets.
All the bits in this SFR have unrestricted read access. WDRUN, POR, EWRST, WDIF and WDCLR
require Timed Access procedure to write. The remaining bits have unrestricted write accesses.
- 70 -
Preliminary N79E352/N79E352R Data Sheet
12. PROGRAMMABLE TIMERS/COUNTERS
The N79E352(R) has three 16-bit programmable timer/counters and one programmable Watchdog
timer. The Watchdog timer is operationally quite different from the other two timers.
12.1 Timer/Counters 0 & 1
Each of these Timer/Counters has two 8 bit registers which form the 16 bit counting register. For
Timer/Counter 0 they are TH0, the upper 8 bits register, and TL0, the lower 8 bit register. Similarly
Timer/Counter 1 has two 8 bit registers, TH1 and TL1. The two can be configured to operate either as
timers, counting machine cycles or as counters counting external inputs.
When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to
be thought of as 1/12 of the system clock or 1/4 of the system clock. In the "Counter" mode, the
register is incremented on the falling edge of the external input pin, T0 in case of Timer 0, and T1 for
Timer 1. The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high
in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized
and the count register is incremented. Since it takes two machine cycles to recognize a negative
transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock
frequency. In either the "Timer" or "Counter" mode, the count register will be updated at C3. Therefore,
in the "Timer" mode, the recognized negative transition on pin T0 and T1 can cause the count register
value to be updated only in the machine cycle following the one in which the negative edge was
detected.
The "Timer" or "Counter" function is selected by the "C / T " bit in the TMOD Special Function Register.
Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for
Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each
Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done by
bits M0 and M1 in the TMOD SFR.
12.2 Time-base Selection
The N79E352(R) gives the user two modes of operation for the timer. The timers can be programmed
to operate like the standard 8051 family, counting at the rate of 1/12 of the clock speed. This will
ensure that timing loops on the N79E352(R) and the standard 8051 can be matched. This is the default
mode of operation of the N79E352(R) timers. The user also has the option to count in the turbo mode,
where the timers will increment at the rate of 1/4 clock speed. This will straight-away increase the
counting speed three times. This selection is done by the T0M and T1M bits in CKCON SFR. A reset
sets these bits to 0, and the timers then operate in the standard 8051 mode. The user should set these
bits to 1 if the timers are to operate in turbo mode.
12.2.1 Mode 0
In Mode 0, the timer/counters act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode we
have a 13 bit timer/counter. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx. The
upper 3 bits of TLx are ignored.
The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx
moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves
from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if
TRx is set and either GATE = 0 or INTx = 1. When C / T is set to 0, then it will count clock cycles, and
if C / T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for timer 1.
When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The timer
overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that when
used as a timer, the time-base may be either clock cycles/12 or clock cycles/4 as selected by the bits
TxM of the CKCON SFR.
Publication Release Date: Jul, 29, 2009
- 71 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
T0M = CKCON.3
(T1M = CKCON.4)
Timer 1 functions are shown in brackets
M1,M0 = TMOD.1,TMOD.0
(M1,M0 = TMOD.5,TMOD.4)
C/T = TMOD.2
(C/T = TMOD.6)
1/4
1
Fcpu
00
0
1
0
1/12
0
4
7
0
7
T0 = P3.4
(T1 = P3.5)
01
TL0
TH0
(TL1)
(TH1)
TR0 = TCON.4
(TR1 = TCON.6)
GATE = TMOD.3
(GATE = TMOD.7)
TFx
Interrupt
INT0 = P3.2
TF0
(INT1 = P3.3)
(TF1)
Figure 12-1: Timer/Counter Mode 0 & Mode 1
- 72 -
Preliminary N79E352/N79E352R Data Sheet
12.2.2 Mode 1
Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13
bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer
moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if
enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in
Mode 0. The gate function operates similarly to that in Mode 0.
12.2.3 Mode 2
In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count
register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx
bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues
from here. The reload operation leaves the contents of the THx register unchanged. Counting is
enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1
mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn.
T0M = CKCON.3
(T1M = CKCON.4)
Timer 1 functions are shown in brackets
C/T = TMOD.2
(C/T = TMOD.6)
1/4
TL0
(TL1)
1
0
Fcpu
0
1/12
TFx
Interrupt
0
4
7
1
T0 = P3.4
(T1 = P3.5)
TF0
(TF1)
TR0 = TCON.4
(TR1 = TCON.6)
GATE = TMOD.3
(GATE = TMOD.7)
INT0 = P3.2
0
7
(INT1 = P3.3)
TH0
(TH1)
Figure 12-2: Timer/Counter Mode 2
12.2.4 Mode 3
Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply
freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count
registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0
control bits C / T , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12 or
clock/4) or 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock cycle
counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from Timer/Counter 1. Mode 3 is
used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can still be used
in Modes 0, 1 and 2., but its flexibility is somewhat limited. While its basic functionality is maintained, it
no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still be used as a
timer/counter and retains the use of GATE and INT1 pin. In this condition it can be turned on and off by
switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the serial
port.
Publication Release Date: Jul, 29, 2009
- 73 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
T0M = CKCON.3
C/T = TMOD.2
1/4
1
TL0
Fcpu
0
0
1/12
TF0
Interrupt
0
4
7
1
T0 = P3.4
TR0 = TCON.4
GATE = TMOD.3
INT0 = P3.2
TF1
Interrupt
TR1 = TCON.6
0
7
TH0
Figure 12-3: Timer/Counter 0 Mode 3
12.3 Timer/Counter 2
Timer/Counter 2 is a 16 bit up/down counter which is configured by the T2MOD register and controlled
by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the Timer
0 and Timer 1 counters, there exists considerable flexibility in selecting and controlling the clock, and in
defining the operating mode. The clock source for Timer/Counter 2 may be selected for either the
external T2 pin (C/T2 = 1) or the crystal oscillator, which is divided by 12 or 4 (C/T2 = 0). The clock is
then enabled when TR2 is a 1, and disabled when TR2 is a 0.
12.3.1 Capture Mode
The capture mode is enabled by setting the CP / RL2 bit in the T2CON register to a 1. In the capture
mode, Timer/Counter 2 serves as a 16 bit up counter. When the counter rolls over from FFFFh to
0000h, the TF2 bit is set, which will generate an interrupt request. If the EXEN2 bit is set, then a
negative transition of T2EX pin will cause the value in the TL2 and TH2 register to be captured by the
RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which will
also generate an interrupt. Setting the T2CR bit (T2MOD.3), the N79E352(R) allows hardware to reset
timer 2 automatically after the value of TL2 and TH2 have been captured.
- 74 -
Preliminary N79E352/N79E352R Data Sheet
T2M=CKCON.5
1
1/4
C/T2=T2CON.1
0
Fcpu
T2CON.7
0
1/12
TL2 TH2
TF2
1
T2=P1.0
Timer2
Interrupt
TR2=T2CON.2
RCAP2L RCAP2H
T2EX=P1.1
EXF2
T2CON.6
EXEN2=T2CON.3
Figure 12-4: Timer 2 16-Bit Capture Mode
12.3.2 Auto-Reload Mode, Counting up
The auto-reload mode as an up counter is enabled by clearing the CP / RL2 bit in the T2CON register
and clearing the DCEN bit in T2MOD register. In this mode, Timer/Counter 2 is a 16 bit up counter.
When the counter rolls over from FFFFh, a reload is generated that causes the contents of the
RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers. The reload action also
sets the TF2 bit. If the EXEN2 bit is set, then a negative transition of T2EX pin will also cause a reload.
This action also sets the EXF2 bit in T2CON.
T2M=CKCON.5
1/4
1
C/T2=T2CON.1
0
Fcpu
T2CON.7
0
1/12
TL2 TH2
TF2
1
T2=P1.0
Timer2
Interrupt
TR2=T2CON.2
RCAP2L RCAP2H
T2EX=P1.1
EXF2
T2CON.6
EXEN2=T2CON.3
Figure 12-5: Timer 2 16-Bit Auto-reload Mode, Counting Up
12.3.3 Auto-Reload Mode, Counting Up/Down
Timer/Counter 2 will be in auto-reload mode as an up/down counter if CP / RL2 bit in T2CON is
cleared and the DCEN bit in T2MOD is set. In this mode, Timer/Counter 2 is an up/down counter
whose direction is controlled by the T2EX pin. A 1 on this pin cause the counter to count up. An
overflow while counting up will cause the counter to be reloaded with the contents of the capture
Publication Release Date: Jul, 29, 2009
- 75 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
registers. The next down count following the case where the contents of Timer/Counter equal the
capture registers will load an FFFFh into Timer/Counter 2. In either event a reload will set the TF2 bit.
A reload will also toggle the EXF2 bit. However, the EXF2 bit can not generate an interrupt while in this
mode.
Down Counting Reload Value
0FFh
0FFh
T2M=CKCON.5
1
1/4
C/T2=T2CON.1
Fcpu
0
T2CON.7
0
1/12
Timer2
Interrupt
TF2
TL2 TH2
1
T2=P1.0
TR2=T2CON.2
RCAP2L RCAP2H
Up Counting Reload Value
EXF2
T2EX=P1.1
T2CON.6
Figure 12-6: Timer 2 16-Bit Auto-reload Up/Down Counter
12.3.4 Baud Rate0 Generator Mode
The baud rate generator mode is enabled by setting either the RCLK or TCLK bits in T2CON register.
While in the baud rate generator mode, Timer/Counter 2 is a 16 bit counter with auto reload when the
count rolls over from FFFFh. However, rolling over does not set the TF2 bit. If EXEN2 bit is set, then a
negative transition of the T2EX pin will set EXF2 bit in the T2CON register and cause an interrupt
request.
Fcpu
1/2
C/T2=T2CON.1
0
Timer2
Overflow
TL2 TH2
1
T2=P1.0
TR2=T2CON.2
RCAP2L RCAP2H
T2EX=P1.1
Timer2
Interrupt
EXF2
T2CON.6
EXEN2=T2CON.3
Figure 12-7: Baud Rate Generator Mode
- 76 -
Preliminary N79E352/N79E352R Data Sheet
12.3.5 Programmable Clock-out
Timer 2 is equipped with a new clock-out feature which outputs a 50% duty cycle clock on P1.0. It can
be invoked as a programmable clock generator. To configure Timer 2 with clock-out mode, software
must initiate it by setting bit T2OE = 1, C/T2 = 0 and CP/RL = 0. Setting bit TR2 will start the timer. This
mode is similar to the baud rate generator mode, it will not generate an interrupt while Timer 2
overflow. So it is possible to use Timer 2 as a baud rate generator and a clock generator at the same
time. The clock-out frequency is determined by the following equation:
The Clock-Out Frequency = Oscillator Frequency / [4 X 65536-(RCAP2H, RCAP2L) ]
Timer2
Overflow
Fcpu
1/2
T2=P1.0
TL2 TH2
1/2
TR2=T2CON.2
RCAP2L RCAP2H
T2EX=P1.1
Timer2
Interrupt
EXF2
T2CON.6
EXEN2=T2CON.3
Figure 12-8: Programmable Clock-Out Mode
Publication Release Date: Jul, 29, 2009
Revision A06
- 77 -
Preliminary N79E352/N79E352R Data Sheet
13. NVM MEMORY
The N79E352(R) has NVM data memory of 128 bytes for customer’s data store used. The NVM data
memory has 8 pages area and each page has 16 bytes.
13.1 Operation
User is required to enable EnNVM (NVMCON.5) bit for NVM read. This is due to overlapping of NVM
data memory and external data memory physical address, the following table is defined. EnNVM bit
(NVMCON.5) will enable read access to NVM data memory area.
EnNVM
0
Data Memory Area
Enable External RAM read/write access by
MOVX
1
Enable NVM data Memory read access by
MOVX only. If EER or EWR is set and NVM
flash erase or write control is busy, to set this
bit read NVM data is invalid.
Table 13-1: MOVX instruction to Enable Read Data Memory Area Definition Table
The NVM memory can be read/write by customer program to access. Read NVM data is by MOVX
A,@DPTR/R0/R1 instructions, and write data is by SFR of NVMADDR, NVMDAT and NVMCON.
Before write data to NVM memory, the page must be erased by providing page address on
NVMADDR, which address of On-Chip Code Memory space will decode, then set EER of NVMCON.7.
This will automatically hold fetch program code and PC Counter, and execute page erase. After
finished, this bit will be cleared by hardware. The erase time is ~ 5ms.
For writing data to NVM memory, user must set address and data to NVMADDR and NVMDAT, then
set EWR of NVMCON.6 to initiate nvm data write. The uC will hold program code and PC Counter, and
then write data to mapping address. Upon write completion, the EWR bit will be cleared by hardware,
the uC will continue execute next instruction. The program time is ~50us.
NVM data Flash Memory is permanently operating from 11.0592MHz internal clock source. In order to
reduce power consumption, the on chip oscillator will only be enabled when during program or erase,
through EWR or EER in NVMCON SFR. EWR or EER bits are cleared by hardware after program or
erase completed. The program/erase time is automatically controlled by hardware.
- 78 -
Preliminary N79E352/N79E352R Data Sheet
Internal Signal
Clock
Source
NVM Data
Memory
Block
EER
ERC
11.0592MHz
RC OSC
EWR
EnNVM
Figure 13-1: NVM control
EnNVM = 0
Instructions
EnNVM = 1
Addr within
NVM
address
range
Addr out of
NVM address
range
MOVX A, @DPTR
(Read)
Ext memory
Ext memory
Ext memory
Ext memory
Ext memory
Ext memory
NVM
Ext memory
Ext memory[1]
Ext memory[1]
Ext memory
MOVX A, @R0
(Read)
NVM
MOVX A, @R1
(Read)
NVM
MOVX @DPTR, A
(Write)
Ext memory
MOVX @R0, A
(Write)
Ext
Ext memory[1]
Ext memory[1]
memory[1]
MOVX @R1, A
(Write)
Ext
memory[1]
Table 13-2: MOVX read/write access destination
Note: 1. Higher address bytes will come from SFR port 2 values.
For security purposes this NVM data flash provide an independent “Lock bit” located in Security bits, it
is used to protect the customer’s data code in NVM. It may be enabled in CONFIG1.6 after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, NVM Flash
EPROM data can not be accessed again by hardware writer mode.
Publication Release Date: Jul, 29, 2009
- 79 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
14. WATCHDOG TIMER
The Watchdog Timer is a free-running Timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if
it is enabled. The interrupt will occur if the individual interrupt enable and the global enable are set. The
interrupt and reset functions are independent of each other and may be used separately or together
depending on the user’s software.
Time-Out
Selector
20KHz+/-
100% RC
Oscillator
15-bits Counter
(WDCON.3)
00
WDIF
/Enable
0
5
Interrupt
(Security Bit)
WDTCK
01
10
11
6
8
EWDI
(EIE.4)
MUX
(WDCON.2)
9
12
14
Fcpu
WTRF
WDRUN
(WDCON.7)
13
512 clock
delay
Reset
WDCLR
(Reset Watchdog)
(WDCON.0)
WD1,WD0
(CKCON.7~6)
EWRST
(WDCON.1)
Figure 14-1: Watchdog Timer
The Watchdog Timer should first be restarted by using WDCLR. This ensures that the timer starts
from a known state. The WDCLR bit is used to restart the Watchdog Timer. This bit is self clearing, i.e.
after writing a 1 to this bit the software will automatically clear it. The Watchdog Timer will now count
clock cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and
CKCON.6). When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set.
After the time-out has occurred, the Watchdog Timer waits for an additional 512 clock cycles. If the
Watchdog Reset EWRST (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no
WDCLR, a system reset due to Watchdog Timer will occur. This will last for two machine cycles, and
the Watchdog Timer reset flag WTRF (WDCON.2) will be set. This indicates to the software that the
Watchdog was the cause of the reset.
When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the
WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a
time-out and the WDCLR allows software to restart the timer. The Watchdog Timer can also be used
as a very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an
interrupt will occur if the global interrupt enable EA is set.
The main use of the Watchdog Timer is as a system monitor. This is important in real-time control
applications. In case of some power glitches or electro-magnetic interference, the processor may begin
to execute errant code. If this is left unchecked the entire system may crash. Using the watchdog timer
interrupt during software development will allow the user to select ideal watchdog reset locations. The
code is first written without the watchdog interrupt or reset. Then the Watchdog interrupt is enabled to
identify code locations where interrupt occurs. The user can now insert instructions to reset the
Watchdog Timer, which will allow the code to run without any Watchdog Timer interrupts. Now the
Watchdog Timer reset is enabled and the Watchdog interrupt may be disabled. If any errant code is
- 80 -
Preliminary N79E352/N79E352R Data Sheet
executed now, then the reset Watchdog Timer instructions will not be executed at the required instants
and Watchdog reset will occur.
The Watchdog Timer time-out selection will result in different time-out values depending on the clock
speed. The reset will occur, when enabled, 512 clocks after the time-out has occurred.
WATCHDOG
INTERVAL
NUMBER OF
CLOCKS
TIME
@ 20 KHZ
WD1
WD0
0
0
1
1
0
1
0
1
26
64
512
8192
32768
3.2 mS
25.6 mS
409.6 mS
1638.4 mS
29
213
215
Table 14-1: Time-out values for the Watchdog timer.
The default Watchdog time-out is 26 clocks, which is the shortest time-out period. The EWRST, WDIF
and WDCLR bits are protected by the Timed Access procedure. This prevents software from
accidentally enabling or disabling the watchdog timer. More importantly, it makes it highly improbable
that errant code can enable or disable the Watchdog Timer.
The security bit WDTCK is located at bit 7 of CONFIG0 register. This bit is for user to configure the
clock source of watchdog timer either from the internal RC or from the uC clock.
Publication Release Date: Jul, 29, 2009
- 81 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
15. UART SERIAL PORT
Serial port in the N79E352(R) is a full duplex port. The N79E352(R) provides the user with additional
features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports
are capable of synchronous as well as asynchronous communication. In Synchronous mode the
N79E352(R) generates the clock and operates in a half duplex mode. In the asynchronous mode, full
duplex operation is available. This means that it can simultaneously transmit and receive data. The
transmit register and the receive buffer are both addressed as SBUF Special Function Register.
However any write to SBUF will be to the transmit register, while a read from SBUF will be from the
receive buffer register. The serial port can operate in four different modes as described below.
15.1 Mode 0
This mode provides synchronous communication with external devices. In this mode serial data is
transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is
provided by the N79E352(R) whether the device is transmitting or receiving. This mode is therefore a
half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame.
The LSB is transmitted/received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency.
This baud rate is determined by the SM2 bit (SCON.5). When this bit is set to 0, then the serial port
runs at 1/12 of the clock. When set to 1, the serial port runs at 1/4 of the clock. This additional facility of
programmable baud rate in mode 0 is the only difference between the standard 8051 and the
N79E352(R).
The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.
The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the
N79E352(R) and the device at the other end of the line. Any instruction that causes a write to SBUF will
start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin till all
8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the falling
edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then goes high
again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of shift clock on
TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This ensures
that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift clock
on TxD or latched when the TxD clock is low.
- 82 -
Preliminary N79E352/N79E352R Data Sheet
Transmit Shift Register
Internal
Data Bus
Write to
SBUF
PARIN
LOAD SOUT
Fcpu
1/12
RXD
P3.0 Alternate
CLOCK
Output Function
1/4
TX START
TX CLOCK
TX SHIFT
TI
SM2
0
1
Serial Interrupt
RI
RX CLOCK
TXD
SHIFT CLOCK
P3.1 Alternate
Output Function
RI
REN
LOAD SBUF
RX SHIFT
RX START
Read SBUF
Serial Controllor
CLOCK
Internal
Data Bus
SBUF
PAROUT
RXD
SIN
P3.0 Alternate
Input Function
Figure 15-1: Uart Serial Port Mode 0
The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive
data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch
data on the rising edge of shift clock. The external device should therefore present data on the falling
edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag is set
in C1 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI is
cleared by software.
15.2 Mode 1
In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of
10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit goes into RB8 in the SFR SCON. The baud rate in this
mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow or
1/16 of Timer 2 overflow. Since the Timer 1 and 2 can be set to different reload values, a wide variation
in baud rates is possible.
Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following
the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the next
rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16 counter
and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is
transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will be
at the 10th rollover of the divide by 16 counter after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with
the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line,
sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by
16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of the divide by
16 counter.
Publication Release Date: Jul, 29, 2009
- 83 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then
this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks
for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also
detected and shifted into the SBUF.
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and
RI is set. However certain conditions must be met before the loading and setting of RI can be done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
Transmit Shift Register
Timer 1
Timer 2
Overflow
Overflow
1
0
STOP
Internal
Data Bus
PARIN
Write to
SBUF
SOUT
TXD
START
LOAD
1/2
SMOD
0
1
CLOCK
TX START
TX CLOCK
0
1
1
TX SHIFT
TCLK
1/16
1/16
0
RCLK
Serial
Controllor
TI
Serial Interrupt
RX CLOCK
RI
SAMPLE
LOAD SBUF
RX SHIFT
1-To-0
DETECTOR
RX START
Read SBUF
Internal
Data Bus
SBUF
RB8
CLOCK PAROUT
BIT
DETECTOR
RXD
SIN
D8
Receive Shift Register
Figure 15-2: Uart Serial Port Mode 1
15.3 Mode 2
This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional
description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a
programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is
programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in
- 84 -
Preliminary N79E352/N79E352R Data Sheet
PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at
C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1
following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the
divide by 16 counter, and not directly to the write to SBUF signal. After all 9 bits of data are transmitted,
the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD
pin. This will be at the 11th rollover of the divide by 16 counter after a write to SBUF. Reception is
enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection
of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD line, sampling it at
the rate of 16 times the selected baud rate. When a falling edge is detected, the divide by 16 counter is
immediately reset. This helps to align the bit boundaries with the rollovers of the divide by 16 counter.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a
best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By
using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise
rejection feature of the serial port.
Transmit Shift Register
STOP
D8
Fcpu/2
TB 8
Internal
PARIN
Write to
SBUF
Data Bus
TXD
SOUT
START
LOAD
1/ 2
0
SMOD
1
CLOCK
TX START
TX CLOCK
TX SHIFT
1 / 16
Serial
Controllor
1 / 16
TI
Serial Interrupt
RX CLOCK
RI
SAMPLE
LOAD SBUF
RX SHIFT
1 - To -0
DETECTOR
RX START
Read SBUF
Internal
Data Bus
SBUF
RB 8
CLOCK PAROUT
BIT
RXD
SIN
D8
DETECTOR
Receive Shift Register
Figure 15-3: Uart Serial Port Mode 2
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,
and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.
If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF. After
shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is
set. However certain conditions must be met before the loading and setting of RI can be done.
1. RI must be 0 and
2. Either SM2 = 0, or the received stop bit = 1.
Publication Release Date: Jul, 29, 2009
- 85 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.
Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to
looking for a 1-to-0 transition on the RxD pin.
- 86 -
Preliminary N79E352/N79E352R Data Sheet
15.4 Mode 3
This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user
must first initialize the Serial related SFR SCON before any communication can take place. This
involves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3
are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination
register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a
clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the
incoming start bit if REN = 1. The external device will start the communication by transmitting the start
bit.
Transmit Shift Register
Timer 1
Timer 2
Overflow
1
TB8
STOP
D8
Overflow
Internal
PARIN
Write to
SBUF
Data Bus
TXD
SOUT
0
START
LOAD
1/2
SMOD
0
1
CLOCK
0
1
1
TX START
TX CLOCK
TX SHIFT
TCLK
1/16
1/16
0
RCLK
Serial
Controllor
TI
Serial Interrupt
RX CLOCK
RI
SAMPLE
LOAD SBUF
RX SHIFT
1-To-0
DETECTOR
RX START
Read SBUF
Internal
Data Bus
SBUF
RB8
CLOCK PAROUT
BIT
DETECTOR
RXD
SIN
D8
Receive Shift Register
Figure 15-4: Uart Serial Port Mode 3
Frame
Start
Bit
Stop
Bit
9th bit
SM1
SM0
Mode
Type
Baud Clock
Size
Function
None
None
0, 1
0
0
1
1
0
1
0
1
0
1
2
3
Synch.
Asynch.
Asynch.
Asynch.
4 or 12 TCLKS
Timer 1 or 2
32 or 64 TCLKS
Timer 1 or 2
8 bits
No
1
No
1
10 bits
11 bits
11 bits
1
1
1
1
0, 1
Table 15-1: Uart Serial Port Modes
Publication Release Date: Jul, 29, 2009
Revision A06
- 87 -
Preliminary N79E352/N79E352R Data Sheet
15.5 Framing Error Detection
A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data
communication. Typically the frame error is due to noise and contention on the serial communication
line. The N79E352(R) has the facility to detect such framing errors and set a flag which can be
checked by software.
The Frame Error FE bit is located in SCON.7. This bit is normally used as SM0 in the standard 8051
family. However, in the N79E352(R) it serves a dual function and is called SM0/FE. There are actually
two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as SCON.7 is
determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is indicated in
SM0/FE. When SMOD0 is set to 0, then the SM0 flag is indicated in SM0/FE.
The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while
reading or writing to FE. If FE is set, then any following frames received without any error will not clear
the FE flag. The clearing has to be done by software.
15.6 Multiprocessor Communications
Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the N79E352(R),
the RI flag is set only if the received byte corresponds to the Given or Broadcast address. This
hardware feature eliminates the software overhead required in checking every received address, and
greatly simplifies the software programmer task.
In the multiprocessor communication mode, the address bytes are distinguished from the data bytes by
transmitting the address with the 9th bit set high. When the master processor wants to transmit a block
of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All the slave
processors should have their SM2 bit set high when waiting for an address byte. This ensures that they
will be interrupted only by the reception of a address byte. The Automatic address recognition feature
ensures that only the addressed slave will be interrupted. The address comparison is done in hardware
not software.
The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 = 0,
the slave will be interrupted on the reception of every single complete frame of data. The unaddressed
slaves will be unaffected, as they will be still waiting for their address. In Mode 1, the 9th bit is the stop
bit, which is 1 in case of a valid frame. If SM2 is 1, then RI is set only if a valid frame is received and
the received byte matches the Given or Broadcast address.
The Master processor can selectively communicate with groups of slaves by using the Given Address.
All the slaves can be addressed together using the Broadcast Address. The addresses for each slave
are defined by the SADDR and SADEN SFRs. The slave address is an 8-bit value specified in the
SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in
SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in
SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives
the user flexibility to address multiple slaves without changing the slave address in SADDR.
- 88 -
Preliminary N79E352/N79E352R Data Sheet
The following example shows how the user can define the Given Address to address different slaves.
Slave 1:
SADDR1010 0100
SADEN 1111 1010
Given 1010 0x0x
Slave 2:
SADDR1010 0111
SADEN 1111 1001
Given 1010 0xx1
The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it
is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate only
with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to
communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The
bit 3 position is don't care for both the slaves. This allows two different addresses to select both slaves
(1010 0001 and 1010 0101).
The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result are
defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the
Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two
SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX
XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature,
since any selectivity is disabled.
Publication Release Date: Jul, 29, 2009
- 89 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
16. I2C SERIAL PORT
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the
bus. The main features of the bus are:
– Bidirectional data transfer between masters and slaves
– Multimaster bus (no central master)
– Arbitration between simultaneously transmitting masters without corruption of serial data on the bus
– Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
– Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial
transfer
– The I2C bus may be used for test and diagnostic purposes
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU
tHD;DAT
tSU;DAT
Figure 16-1: I2C Bus Timing
The device’s on-chip I2C logic provides the serial interface that meets the I2C bus standard mode
specification. The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers,
and a status register (I2STATUS) reflects the status of the I2C bus.
The I2C port, SCL and SDA are at P1.2 and P1.3. When the I/O pins are used as I2C port, user must
set the pins to logic high in advance. When I2C port is enabled by setting ENS to high, the internal
states will be controlled by I2CON and I2C logic hardware. Once a new status code is generated and
stored in I2STATUS, the I2C interrupt flag (SI) will be set automatically. If both EA and EI2C are also in
logic high, the I2C interrupt is requested. The 5 most significant bits of I2STATUS stores the internal
state code, the lowest 3 bits are always zero and the content keeps stable until SI is cleared by
software.
16.1 I2C Bus
The I2C bus is a serial I/O port, which supports all transfer modes from and to the I2C bus. The I2C
port handles byte transfers autonomously. To enable this port, the bit ENSI in I2CON should be set to
'1'. The CPU interfaces to the I2C port through the following six special function registers: I2CON
(control register, C0H), I2STATUS (status register, BDH), I2DAT (data register, BCH), I2ADDR
(address registers, C1H), I2CLK (clock rate register BEH) and I2TIMER (Timer counter register, BFH).
The H/W interfaces to the I2C bus via two pins: SDA (P1.2, serial data line) and SCL (P1.3, serial clock
line). Pull up resistor is needed for Pin P1.2 and P1.3 for I2C operation as these are 2 open drain pins
(on I2C mode).
- 90 -
Preliminary N79E352/N79E352R Data Sheet
16.2 The I2C Control Registers:
The I2C has 1 control register (I2CON) to control the transmit/receive flow, 1 data register (I2DAT) to
buffer the Tx/Rx data, 1 status register (I2STATUS) to catch the state of Tx/Rx, recognizable slave
address register for slave mode use and 1 clock rate control block for master mode to generate the
variable baud rate.
16.2.1 The Address Registers, I2ADDR
I2C port is equipped with one slave address register. The contents of the register are irrelevant when
I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the
MCU’s own slave address. The I2C hardware will react if the contents of I2ADDR are matched with the
received slave address.
The I2C ports support the “General Call” function. If the GC bit is set the I2C port1 hardware will
respond to General Call address (00H). Clear GC bit to disable general call function.
When GC bit is set, the I2C is in Slave mode, it can be received the general call address by 00H after
Master send general call address to I2C bus, then it will follow status of GC mode. If it is in Master
mode, the AA bit must be cleared when it will send general call address of 00H to I2C bus.
16.2.2 The Data Register, I2DAT
This register contains a byte of serial data to be transmitted or a byte which has just been received.
The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of
shifting a byte. This occurs when the bus is in a defined state and the serial interrupt flag (SI) is set.
Data in I2DAT remains stable as long as SI bit is set. While data is being shifted out, data on the bus is
simultaneously being shifted in; I2DAT always contains the last data byte present on the bus. Thus, in
the event of arbitration lost, the transition from master transmitter to slave receiver is made with the
correct data in I2DAT.
I2DAT and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the
hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge bit into
I2DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into
I2DAT, the serial data is available in I2DAT, and the acknowledge bit (ACK or NACK) is returned by the
control logic during the ninth clock pulse. Serial data is shifted out from I2DAT on the falling edges of
SCL clock pulses, and is shifted into I2DAT on the rising edges of SCL clock pulses.
I2C Data Register:
I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0
shifting direction
Publication Release Date: Jul, 29, 2009
- 91 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
16.2.3 The Control Register, I2CON
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by
hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is cleared
when a STOP condition is present on the bus. The STO bit is also cleared when ENS = "0".
ENSI
STA
STO
Set to enable I2C serial function block. When ENS=1 the I2C serial function enables. The
port latches of SDA1 and SCL1 must be set to logic high.
I2C START Flag. Setting STA to logic 1 to enter master mode, the I2C hardware sends a
START or repeat START condition to bus when the bus is free.
I2C STOP Flag. In master mode, setting STO to transmit a STOP condition to bus then
I2C hardware will check the bus condition if a STOP condition is detected this flag will be
cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to
the defined “not addressed” slave mode. This means it is NO LONGER in the slave
receiver mode to receive data from the master transmit device.
SI
I2C Port 1 Interrupt Flag. When a new I2C bus state is present in the S1STA register, the
SI flag is set by hardware, and if the EA and EI2C1 bits are both set, the I2C1 interrupt is
requested. SI must be cleared by software.
AA
Assert Acknowledge control bit. When AA=1 prior to address or data received, an
acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on
the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The
receiver devices are acknowledging the data sent by transmitter. When AA=0 prior to
address or data received, a Not acknowledged (high level to SDA) will be returned during
the acknowledge clock pulse on the SCL line.
16.2.4 The Status Register, I2STATUS
I2STATUS is an 8-bit read-only register. The three least significant bits are always 0. The five most
significant bits contain the status code. There are 26 possible status codes. When I2STATUS contains
F8H, no serial interrupt is requested. All other I2STATUS values correspond to defined I2C bus states.
When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is
present in I2STATUS one machine cycle after SI is set by hardware and is still present one machine
cycle after SI has been reset by software.
16.2.5 The I2C Clock Baud Rate Bits, I2CLK
The data baud rate of I2C is determines by I2CLK register when I2C is in a master mode. It is not
important when I2C is in a slave mode. In the slave modes, I2C will automatically synchronize with any
clock frequency up to 400 KHz from master I2C device.
The data baud rate of I2C setting is Data Baud Rate of I2C = Fcpu / (I2CLK+1). The Fcpu=Fosc/4. If
Fosc = 16MHz, the I2CLK = 40(28H), so data baud rate of I2C = 16MHz/(4X (40 +1)) = 97.56Kbits/sec.
The block diagram is as below figure.
- 92 -
Preliminary N79E352/N79E352R Data Sheet
16.2.6 I2C Time-out Counter, I2Timerx
The I2C logic block provides a 14-bit timer-out counter that helps user to deal with bus pending
problem. When SI is cleared user can set ENTI=1 to start the time-out counter. If I2C bus is pended
too long to get any valid signal from devices on bus, the time-out counter overflows cause TIF=1 to
request an I2C interrupt. The I2C interrupt is requested in the condition of either SI=1 or TIF=1. Flags
SI and TIF must be cleared by software.
0
1
Fcpu
14-bits Counter
TIF
Enable
To I2C Interrupt
1/4
Clear Counter
DIV4
SI
ENS1
ENTI
SI
Figure 16-2: I2C Timer Count Block Diagram
16.3 Modes of Operation
The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave
transmitter, Slave receiver, and GC call.
In a given application, I2C port may operate as a master or as a slave. In the slave mode, the I2C port
hardware looks for its own slave address and the general call address. If one of these addresses is
detected, and if the slave is willing to receive or transmit data from/to master(by setting the AA bit),
acknowledge pulse will be transmitted out on the 9th clock, hence an interrupt is requested on both
master and slave devices if interrupt is enabled. When the microcontroller wishes to become the bus
master, the hardware waits until the bus is free before the master mode is entered so that a possible
slave action is not interrupted. If bus arbitration is lost in the master mode, I2C port switches to the
slave mode immediately and can detect its own slave address in the same serial transfer.
16.3.1 Master Transmitter Mode
Serial data output through SDA while SCL outputs the serial clock. The first byte transmitted contains
the slave address of the receiving device (7 bits) and the data direction bit. In this case the data
direction bit (R/W) will be logic 0, and it is represented by “W” in the flow diagrams. Thus the first byte
transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an
acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the
end of a serial transfer.
16.3.2 Master Receiver Mode
In this case the data direction bit (R/W) will be logic 1, and it is represented by “R” in the flow diagrams.
Thus the first byte transmitted is SLA+R. Serial data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are output to indicate the beginning and end of a serial
transfer.
Publication Release Date: Jul, 29, 2009
- 93 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
16.3.3 Slave Receiver Mode
Serial data and the serial clock are received through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by hardware after reception of the slave address
and direction bit.
16.3.4 Slave Transmitter Mode
The first byte is received and handled as in the slave receiver mode. However, in this mode, the
direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA while
the serial clock is input through SCL. START and STOP conditions are recognized as the beginning
and end of a serial transfer.
16.4 Data Transfer Flow in Five Operating Modes
The five operating modes are: Master/Transmitter, Master/Receiver, Slave/Transmitter, Slave/Receiver
and GC Call. Bits STA, STO and AA in I2CON register will determine the next state of the I2C
hardware after SI flag is cleared. Upon complexion of the new action, a new status code will be
updated and the SI flag will be set. If the I2C interrupt control bits (EA and EI2) are enable, appropriate
action or software branch of the new status code can be performed in the Interrupt service routine.
Data transfers in each mode are shown in the following figures.
*** Legend for the following five figures:
Software's access to S1DAT with respect to "Expected next action":
(1) Data byte will be transmitted:
08H
Last state
A START has been
transmitted.
Last action is done
Software should load the data byte (to be transmitted)
into S1DAT before new S1CON setting is done.
(2) SLA+W (R) will be transmitted:
Software should load the SLA+W/R (to be transmitted)
into S1DAT before new S1CON setting is done.
(3) Data byte will be received:
(STA,STO,SI,AA)=(0,0,0,X)
SLA+W will be transmitted;
ACK bit will be received.
Next setting in S1CON
Expected next action
Software can read the received data byte from S1DAT
while a new state is entered.
New state
18H
SLA+W has been transmitted;
ACK has been received.
next action is done
Figure 16-3: Legen for the following four figures
- 94 -
Preliminary N79E352/N79E352R Data Sheet
Set STA to generate
a START.
From Slave Mode (C)
08H
A START has been
transmitted.
(STA,STO,SI,AA)=(0,0,0,X)
SLA+W will be transmitted;
ACK bit will be received.
From Master/Receiver (B)
18H
SLA+W will be transmitted;
ACK bit will be received.
or
20H
SLA+W will be transmitted;
NOT ACK bit will be received.
(STA,STO,SI,AA)=(0,0,0,X)
Data byte will be transmitted;
ACK will be received.
(STA,STO,SI,AA)=(0,1,0,X)
A STOP will be transmitted;
STO flag will be reset.
(STA,STO,SI,AA)=(1,0,0,X)
A repeated START will be transmitted;
(STA,STO,SI,AA)=(1,1,0,X)
A STOP followed by a START will
be transmitted;
STO flag will be reset.
10H
28H
Send a STOP
A repeated START has
been transmitted.
Data byte in S1DAT has been transmitted;
ACK has been received.
Send a STOP
followed by a START
or
30H
Data byte in S1DAT has been transmitted;
NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,0,X)
SLA+R will be transmitted;
ACK bit will be transmitted;
SIO1 will be switched to MST/REC mode.
38H
Arbitration lost in SLA+R/W or
Data byte.
To Master/Receiver (A)
(STA,STO,SI,AA)=(0,0,0,X)
I2C bus will be release;
Not address SLV mode will be entered.
(STA,STO,SI,AA)=(1,0,0,X)
A START will be transmitted when the
bus becomes free.
Enter NAslave
Send a START
when bus becomes free
Figure 16-4: Master Transmitter Mode
Publication Release Date: Jul, 29, 2009
Revision A06
- 95 -
Preliminary N79E352/N79E352R Data Sheet
Set STA to generate
a START.
From Slave Mode (C)
08H
A START has been
transmitted.
(STA,STO,SI,AA)=(0,0,0,X)
SLA+R will be transmitted;
ACK bit will be received.
From Master/Transmitter (A)
48H
40H
SLA+R has been transmitted;
NOT ACK has been received.
SLA+R has been transmitted;
ACK has been received.
(STA,STO,SI,AA)=(0,0,0,0)
Data byte will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,0,1)
Data byte will be received;
ACK will be returned.
58H
50H
Data byte has been received;
NOT ACK has been returned.
Data byte has been received;
ACK has been returned.
(STA,STO,SI,AA)=(0,1,0,X)
A STOP will be transmitted;
STO flag will be reset.
(STA,STO,SI,AA)=(1,1,0,X)
A STOP followed by a START will
be transmitted;
(STA,STO,SI,AA)=(1,0,0,X)
A repeated START will be transmitted;
STO flag will be reset.
10H
Send a STOP
A repeated START has
been transmitted.
Send a STOP
followed by a START
38H
(STA,STO,SI,AA)=(0,0,0,X)
SLA+R will be transmitted;
ACK bit will be transmitted;
Arbitration lost in NOT ACK
bit.
SIO1 will be switched to MST/REC mode.
To Master/Transmitter (B)
(STA,STO,SI,AA)=(1,0,0,X)
A START will be transmitted;
when the bus becomes free
(STA,STO,SI,AA)=(0,0,0,X)
I2C bus will be release;
Not address SLV mode will be entered.
Send a START
Enter NAslave
when bus becomes free
Figure 16-5: Master Receiver Mode
- 96 -
Preliminary N79E352/N79E352R Data Sheet
Set AA
A8H
Own SLA+R has been received;
ACK has been return.
or
B0H
Arbitration lost SLA+R/W as master;
Own SLA+R has been received;
ACK has been return.
(STA,STO,SI,AA)=(0,0,0,0)
Last data byte will be transmitted;
ACK will be received.
(STA,STO,SI,AA)=(0,0,0,1)
Data byte will be transmitted;
ACK will be received.
C8H
Last data byte in S1DAT has been transmitted;
ACK has been received.
C0H
B8H
Data byte in S1DAT has been transmitted;
ACK has been received.
Data byte or Last data byte in S1DAT has been
transmitted;
NOT ACK has been received.
(STA,STO,SI,AA)=(0,0,0,0)
Last data will be transmitted;
ACK will be received.
(STA,STO,SI,AA)=(0,0,0,1)
Data byte will be transmitted;
ACK will be received.
A0H
A STOP or repeated START has been
received while still addressed as SLV/TRX.
(STA,STO,SI,AA)=(1,0,0,1)
Switch to not address SLV mode;
Own SLA will be recognized;
A START will be transmitted when the
bus becomes free.
(STA,STO,SI,AA)=(1,0,0,0)
(STA,STO,SI,AA)=(0,0,0,1)
Switch to not addressed SLV mode;
Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,0,0)
Switch to not addressed SLV mode;
No recognition of own SLA.
Switch to not addressed SLV mode;
No recognition of own SLA;
A START will be transmitted when the
becomes free.
Enter NAslave
Send a START
when bus becomes free
To Master Mode (C)
Figure 16-6: Slave Transmitter Mode
Publication Release Date: Jul, 29, 2009
Revision A06
- 97 -
Preliminary N79E352/N79E352R Data Sheet
Set AA
60H
Own SLA+W has been received;
ACK has been return.
or
68H
Arbitration lost SLA+R/W as master;
Own SLA+W has been received;
ACK has been return.
(STA,STO,SI,AA)=(0,0,0,0)
Data byte will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,0,1)
Data byte will be received;
ACK will be returned.
80H
88H
Previously addressed with own SLA address;
Data has been received;
ACK has been returned.
Previously addressed with own SLA address;
NOT ACK has been returned.
(STA,STO,SI,AA)=(0,0,0,0)
Data will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(0,0,0,1)
Data will be received;
ACK will be returned.
A0H
A STOP or repeated START has been
received while still addressed as SLV/REC.
(STA,STO,SI,AA)=(1,0,0,1)
Switch to not address SLV mode;
Own SLA will be recognized;
A START will be transmitted when
the bus becomes free.
(STA,STO,SI,AA)=(1,0,0,0)
(STA,STO,SI,AA)=(0,0,0,1)
Switch to not addressed SLV mode;
Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,0,0)
Switch to not addressed SLV mode;
No recognition of own SLA.
Switch to not addressed SLV mode;
No recognition of own SLA;
A START will be transmitted when the
becomes free.
Enter NAslave
Send a START
when bus becomes free
To Master Mode (C)
Figure 16-7: Slave Receiver Mode
- 98 -
Preliminary N79E352/N79E352R Data Sheet
Set AA
70H
Reception of the general call address
and one or more data bytes;
ACK has been return.
or
78H
Arbitration lost SLA+R/W as master;
and address as SLA by general call;
ACK has been return.
(STA,STO,SI,AA)=(X,0,0,0)
Data byte will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(X,0,0,1)
Data byte will be received;
ACK will be returned.
90H
98H
Previously addressed with General Call;
Data has been received;
Previously addressed with General Call;
Data byte has been received;
ACK has been returned.
NOT ACK has been returned.
(STA,STO,SI,AA)=(X,0,0,0)
Data will be received;
NOT ACK will be returned.
(STA,STO,SI,AA)=(X,0,0,1)
Data will be received;
ACK will be returned.
A0H
A STOP or repeated START has been
received while still addressed as
SLV/REC.
(STA,STO,SI,AA)=(1,0,0,1)
(STA,STO,SI,AA)=(1,0,0,0)
(STA,STO,SI,AA)=(0,0,0,1)
Switch to not addressed SLV mode;
Own SLA will be recognized.
(STA,STO,SI,AA)=(0,0,0,0)
Switch to not addressed SLV mode;
No recognition of own SLA.
Switch to not address SLV mode;
Own SLA will be recognized;
A START will be transmitted when
the bus becomes free.
Switch to not addressed SLV mode;
No recognition of own SLA;
A START will be transmitted when the
becomes free.
Enter NAslave
Send a START
when bus becomes free
To Master Mode (C)
Figure 16-8: GC Mode
Publication Release Date: Jul, 29, 2009
Revision A06
- 99 -
Preliminary N79E352/N79E352R Data Sheet
17. TIMED ACCESS PROTECTION
The N79E352(R) has several new features, like the Watchdog timer, on-chip ROM size adjustment,
wait state control signal and Power on/fail reset flag, which are crucial to proper operation of the
system. If left unprotected, errant code may write to the Watchdog control bits resulting in incorrect
operation and loss of control. In order to prevent this, the N79E352(R) has a protection scheme which
controls the write access to critical bits. This protection scheme is done using a timed access.
In this method, the bits which are to be protected have a timed write enable window. A write is
successful only if this window is active, otherwise the write will be discarded. This write enable window
is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window
automatically closes. The window is opened by writing AAh and immediately 55h to the Timed
Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed
access window is
TA
REG 0C7h
; define new register TA, located at 0C7h
MOV TA, #0AAh
MOV TA, #055h
When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine
cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the
first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles, during
which the user may write to the protected bits. Once the window closes the procedure must be
repeated to access the other protected bits.
Examples of Timed Assessing are shown below
Example 1: Valid access
MOV TA, #0AAh
MOV TA, #055h
MOV WDCON, #00h
3 M/C
3 M/C
3 M/C
Note: M/C = Machine Cycles
Example 2: Valid access
MOV TA, #0AAh
MOV TA, #055h
NOP
3 M/C
3 M/C
1 M/C
2 M/C
SETB EWRST
Example 3: Valid access
MOV TA, #0Aah
MOV TA, #055h
3 M/C
3 M/C
ORL
WDCON, #00000010B 3M/C
Example 4: Invalid access
MOV TA, #0AAh
MOV TA, #055h
NOP
3 M/C
3 M/C
1 M/C
1 M/C
2 M/C
NOP
CLR
POR
Example 5: Invalid Access
MOV TA, #0AAh
NOP
3 M/C
1 M/C
- 100 -
Preliminary N79E352/N79E352R Data Sheet
MOV TA, #055h
SETB EWRST
3 M/C
2 M/C
In the first two examples, the writing to the protected bits is done before the 3 machine cycle window
closes. In Example 3, however, the writing to the protected bit occurs after the window has closed, and
so there is effectively no change in the status of the protected bit. In Example 4, the second write to TA
occurs 4 machine cycles after the first write, therefore the timed access window in not opened at all,
and the write to the protected bit fails.
Publication Release Date: Jul, 29, 2009
- 101 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
18. INTERRUPTS
N79E352(R) has four priority level interrupts structure with 11 interrupt sources. Each of the interrupt
sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can
be globally enabled or disabled.
18.1 Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, programmable
through bits IT0 and IT1 (SFR TCON). The bits IE0 and IE1 in TCON register are the flags which are
checked to generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every
machine cycle. If the sample is high in one cycle and low in the next, then a high to low transition is
detected and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since
the external interrupts are sampled every machine cycle, they have to be held high or low for at least
one complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If
the level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt
is serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced. The Watchdog timer can be used as a system monitor or a simple
timer. In either case, when the time-out count is reached, the Watchdog Timer interrupt flag WDIF
(WDCON.3) is set. If the interrupt is enabled by the enable bit EIE.4, then an interrupt will occur.
The timer 2 interrupt is generated through TF2 (timer 2 overflow/compare match). The hardware does
not clear these flags when a timer 2 interrupt is executed.
The uart serial block can generate interrupt on reception or transmission. There are two interrupt
sources from the uart block, which are obtained by the RI and TI bits in the SCON SFR. These bits are
not automatically cleared by the hardware, and the user will have to clear these bits using software.
This device also provide an independent I2C serial port. When new I2C state is present in I2STATUS,
the SI flag is set by hardware, and if EA and EI2 bits are both set, the I2C interrupt is requested. SI
must be cleared by software.
Keyboard interrupt is generated when any of the keypad connected to P0 pins is pressed. Each keypad
interrupt can be individually enabled or disabled. User will have to software clear the flag bit.
The input capture 0 interrupt is generated through CPTF0 flag. CPTF0 flag is set by input capture
events. The hardware does not clear this flag when the capture interrupt is executed. Software has to
clear the flag.
Brownout detect can cause brownout flag, BOF, to be asserted if power voltage drop below brownout
voltage level. Interrupt will occur if BOI (AUXR1.5), EBO (EIE.6) and global interrupt enable are set.
Source
Vector Address
0003H
Source
Timer 0 Overflow
Timer 1 Overflow
Brownout Interrupt
KBI Interrupt
-
Vector Address
000BH
External Interrupt 0
External Interrupt 1
Serial Port
0013H
001BH
0023H
002BH
I2C Interrupt
0033H
003BH
Timer 2 Overflow
Watchdog Timer
0043H
004BH
0053H
-
005BH
- 102 -
Preliminary N79E352/N79E352R Data Sheet
0063H
Input Capture 0 Interrupt
006BH
Table 18- 1: N79E352(R) interrupt vector table
18.2 Priority Level Structure
There are four priority levels for the interrupts, highest, high, low and lowest. The interrupt sources can
be individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted
by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts
themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous
requests having the same priority level. This hierarchy is defined as shown on Table 18- 2: Four-level
interrupts priority.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being execute.
3. The current instruction does not involve a write to IE, EIE, IP0, IP0H, IP1 or IPH1 registers and is not
a RETI.
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
repeated every machine cycle, with the interrupts sampled in the same machine cycle. If an interrupt
flag is active in one cycle but not responded to, and is not active when the above conditions are met,
the denied interrupt will not be serviced. This means that active interrupts are not remembered; every
polling cycle is new.
The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate
service routine. This may or may not clear the flag which caused the interrupt. In case of Timer
interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the
appropriate timer service routine. In case of external interrupt, /INT0 and /INT1, the flags are cleared
only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. In the
case of Timer 2 interrupt, the flags are not cleared by hardware. The Watchdog timer interrupt flag
WDIF has to be cleared by software. The hardware LCALL behaves exactly like the software LCALL
instruction. This instruction saves the Program Counter contents onto the Stack, but does not save the
Program Status Word PSW. The PC is reloaded with the vector address of that interrupt which caused
the LCALL. These address of vector for the different sources are as shown on Table 18- 3: Summary
of interrupt sources. The vector table is not evenly spaced; this is to accommodate future expansions
to the device family.
Execution continues from the vectored address till an RETI instruction is executed. On execution of the
RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the
stack. The user must take care that the status of the stack is restored to what it was after the hardware
LCALL, if the execution is to return to the interrupted program. The processor does not notice anything
if the stack contents are modified and will proceed with execution from the address put back into PC.
Note that a RET instruction would perform exactly the same process as a RETI instruction, but it would
not inform the Interrupt Controller that the interrupt service routine is completed, and would leave the
controller still thinking that the service routine is underway.
N79E352(R) uses a four priority level interrupt structure. This allows great flexibility in controlling the
handling of the interrupt sources.
Publication Release Date: Jul, 29, 2009
- 103 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPXH
IPX
0
0
0
1
1
Level 0 (lowest priority)
Level 1
1
0
Level 2
1
Level 3 (highest priority)
Table 18- 2: Four-level interrupts priority
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in registers IE
or EIE. The IE register also contains a global disable bit, EA, which disables all interrupts at once.
Each interrupt source can be individually programmed to one of four priority levels by setting or
clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service routine in progress can be
interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The
highest priority interrupt service cannot be interrupted by any other interrupt source. So, if two requests
of different priority levels are received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. This is called the arbitration ranking. Note that the arbitration
ranking is only used to resolve simultaneous requests of the same priority level.
Table below summarizes the interrupt sources, flag bits, vector address, enable bits, priority bits,
arbitration ranking, and whether each interrupt may wake up the CPU from Power Down mode.
Source
Flag
Vector
address
Enable
bit
Flag
cleared by
Priority
bit
Arbitration
ranking
Power-
down
wakeup
EX0
(IE.0)
IP0H.0,
IP0.0
External
Interrupt 0
IE0
BOF
0003H
002BH
0053H
000BH
0033h
0013H
Hardware,
Software
1(highest)
Yes
Yes
Yes
No
EBO
(EIE.6)
IP1H.6,
IP1.6
Brownout
Detect
Hardware
2
3
4
5
6
EWDI
(EIE.4)
IP1H.4,
IP1.4
Watchdog
Timer
WDIF
TF0
Software
ET0
(IE.1)
IP0H.1,
IP0.1
Timer 0
Overflow
Hardware,
Software
EI2
(EIE.0)
IP1H.0,
IP1.0
I2C
Interrupt
SI + TIF
IE1
Software
No
EX1
(IE.2)
IP0H.2,
IP0.2
External
Interrupt 1
Hardware,
Software
Yes
EKB
(EIE.1)
ET1
IP1H.1,
IP1.1
IP0H.3,
IP0.3
KBI
KBF
TF1
003BH
001BH
Software
7
8
Yes
No
Timer 1
Overflow
Hardware,
Software
(IE.3)
ES
(IE.4)
IP0H.4,
IP0.4
UART
RI + TI
0023H
Software
9
No
- 104 -
Preliminary N79E352/N79E352R Data Sheet
ET2
(IE.5)
IP0H.5,
IP0.5
Timer 2
Overflow/
TF2 + EXF2
CPTF0
0043H
006BH
Software
Software
10
11
No
No
Match
ECPTF
(EIE.7)
IP1H.7,
IP1.7
Input
Capture
Table 18- 3: Summary of interrupt sources
Note: 1. The Watchdog Timer can wake up Power Down Mode when its clock source is used internal RC.
18.3 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the
interrupt and the instruction underway. In the case of external interrupts INT0 to INT1 , they are
sampled at C3 of every machine cycle and then their corresponding interrupt flags IEx will be set or
reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has
occurred. These flag values are polled only in the next machine cycle. If a request is active and all
three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes
four machine cycles to be completed. Thus there is a minimum time of five machine cycles between
the interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the
instruction being executed, then an additional delay is introduced. The maximum response time (if no
other interrupt is in service) occurs if the device is performing a write to IE, EIE, IP0, IP0H, IP1 or IP1H
and then executes a MUL or DIV instruction. From the time an interrupt source is activated, the longest
reaction time is 12 machine cycles. This includes 1 machine cycle to detect the interrupt, 2 machine
cycles to complete the IE, EIE, IP0, IP0H, IP1 or IP1H access, 5 machine cycles to complete the MUL
or DIV instruction and 4 machine cycles to complete the hardware LCALL to the interrupt vector
location.
Thus in a single-interrupt system the interrupt response time will always be more than 5 machine
cycles and not more than 12 machine cycles. The maximum latency of 12 machine cycle is 48 clock
cycles. Note that in the standard 8051 the maximum latency is 8 machine cycles which equals 96
machine cycles. This is a 50% reduction in terms of clock periods.
18.4 Interrupt Inputs
N79E352(R) has two individual interrupt inputs as well as the Keyboard Interrupt function. The latter is
described separately elsewhere in this section. Two interrupt inputs are identical to those present on
the standard 80C51 microcontroller.
The external sources can be programmed to be level-activated or transition-activated by setting or
clearing bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a detected low at
the INTn pin. If ITn = 1, external interrupt n is edge triggered. In this mode if successive samples of the
/INTn pin show a high in one cycle and a low in the next cycle, interrupt request flag IEn in TCON is
set, causing an interrupt request.
Since the external interrupt pins are sampled once each machine cycle, an input high or low should
hold for at least 6 CPU Clocks to ensure proper sampling. If the external interrupt is high for at least
one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the
Publication Release Date: Jul, 29, 2009
- 105 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
transition is seen and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU
when the service routine is called.
If the external interrupt is level-activated, the external source must hold the request active until the
requested interrupt is actually generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is not necessary to clear the interrupt
flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the device is put into Power Down or Idle mode, the interrupt
will cause the processor to wake up and resume operation. Refer to the section on Power
Management for details.
IE0
EX0
IE1
EX1
BOF
EBO
KBF
EKB
Wakeup
(If in Power Down)
WDIF
EWDI
TF0
ET0
EA
Interrupt
to CPU
TF1
ET1
RI + TI
ES
SI
EI2
CPTF0
ECPTF
TF2
ET2
Figure 18- 1: Interrupt inputs
19. KEYBOARD FUNCTION
The N79E352(R) provideds 8 keyboard interrupt function to detect keypad status which key is acted,
and allow a single interrupt to be generated when any key is pressed on a keyboard or keypad
- 106 -
Preliminary N79E352/N79E352R Data Sheet
connected to specific pins of the N79E352(R), as shown below figure. This interrupt may be used to
wake up the CPU from Idle or Power Down modes, after chip is in Power Down or Idle Mode.
Keyboard function is supported through by Port 0. It can allow any or all pins of Port 0 to be enabled to
cause this interrupt. Port pins are enabled by the setting of bits of KBI0 ~ KBI7 in the KBI register, as
shown below figure. The Keyboard Interrupt Flag (KBF) in the AUXR1 register is set when any enabled
pin is triggered while the KBI interrupt function is active, and the low pulse must be more than 1
machine cycle, an interrupt will be generated if it has been enabled. The KBF bit set by hardware and
must be cleared by software. In order to determine which key was pressed, the KBI will allow the
interrupt service routine to poll port 0.
The N79E352(R) has addition SFR KBL level configuration register to control either a low or high level
trigger.
KBL.7
High/low
level
P0.7
KBI.7
KBI.6
KBL.6
P0.6
High/low
level
KBL.5
P0.5
High/low
level
KBI.5
KBI.4
KBI.3
KBI.2
KBI.1
KBI.0
KBL.4
P0.4
High/low
level
KBF (KBI
Interrupt)
KBL.3
P0.3
High/low
level
EKB
(From EIE Register)
KBL.2
P0.2
High/low
level
KBL.1
P0.1
High/low
level
KBL.0
P0.0
High/low
level
Figure 19-1: KBI inputs
Publication Release Date: Jul, 29, 2009
Revision A06
- 107 -
Preliminary N79E352/N79E352R Data Sheet
20. INPUT CAPTURE
The input capture modules are function to detect/measure pulse width and period of a square wave. It
supports one capture inputt with digital noise rejection filter. The modules are configured by
CAPCON0, CAPCON1 and T2MOD SFR registers. Input Capture has its own edge detector but share
with Timer 0. The Input Capture is a schmitt trigger pin. For this operation it basically consists of;
.
.
Capture module function block
Timer 0 (mode 0 and 1) block
The capture module block consists of 2 bytes capture registers, noise filter and programmable edge
triggers. Noise Filter is used to filter the unwanted glitch or pulse on the trigger input pin. The noise
filter can be enabled through bit ENF0 (CAPCON1). If enabled, the capture logic required to sample 4
consecutive same capture input value in order to recognize an edge as a capture event. A possible
implementation of digital noise filter is as follow;
SET
Tx filtered
J
Q
Q
SET
CLR
SET
CLR
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
D
Q
Q
D
Q
Q
Tx
K
CLR
Clk
Figure 20-1: Noise filter
The interval between pulses requirement for input capture is 1 machine cycle width, which is the same
as the pulse width required to guarantee a trigger for all trigger edge mode. For less than 3 system
clocks, anything less than 3 clocks will not have any trigger and pulse width of 3 or more but less than
4 clocks will trigger but will not guarantee 100% because input sampling is at stage C3 of the machine
cycle.
The trigger option is programmable through CCT0[1:0] (CAPCON0[3:2]). It supports positive edge,
negative edge and both edge triggers. The capture module consists of an enable, ICEN0 (T2MOD.4).
Timer/Counter 0 needs to be configured as mode 0 or 1 recommanded. It’s content will transfer to
CCL0 and CCH0 SFR when CPTF0 is set. If ICEN0 is enabled, each time the external pin trigger, the
content TL0 and TH0 (from Timer 0 block) will be captured/transferred into the capture registers, CCL0
and CCH0, depending which external pin trigger. This action also causes the CPTF0 flag bit in
CAPCON1 to be set, which will also generate an interrupt (if enabled by ECPTF bit in SFR EIE.7). The
flag is set by hardware and cleared by software.
Setting the T0CC bit (CAPCON1.6), will allow hardware to reset timer 0 automatically after the value of
TL0 and TH0 have been captured.
- 108 -
Preliminary N79E352/N79E352R Data Sheet
Capture 0 Block
CCH 0
CCL 0
CAPCON0.CCT0.1~0
Edge Select
CPTF0
With
Schmitt
Trigger
[00]
[01]
[10]
CAPCON1.ENF0
T0
(P3.4)
Noise
Filter
T2MOD.ICEN0
Timer 0
(recommanded mode 0 or 1)
CAPCON1.T0CC
(Timer 0 count clear enable)
Figure 20-2: Input capture block
Publication Release Date: Jul, 29, 2009
Revision A06
- 109 -
Preliminary N79E352/N79E352R Data Sheet
21. PULSE WIDTH MODULATED OUTPUTS (PWM)
The N79E352(R) contains two Pulse Width Modulated (PWM) channels which generate pulses of
programmable length and interval. The output for PWM0 is on P1.4 and PWM1 on P1.5. After chip
reset the internal output of the each PWM channel is a “1” (if PRHI=1). The PWM block diagram is
shown as below figure. The interval between successive outputs is controlled by a 8–bit up-counter
which uses the selectable clock sources. The clock sources supported are cpu clock, timer 0 overflow
and timer 1 overflow, selectable by PWMCON3.PCLK.1~0 bits. The clock sources can be further
divided with programmable PWMCON3.FP1~0 bits. When the counter reaches overflow, it is reloaded
with zero.
The width of each PWM output pulse is determined by the value in the appropriate Compare registers,
PWMnL (n=0,1). When the counter described above matches compare register value the PWM output
is forced low. It remains low until the counter value overflow. The number of clock pulses that the
PWMn output is low is given by:
tLO = (FFh – PWMn+1)
Vdd
P1.4
PWM0
(P1.4)
PWM0L
Register
PWM0L
Buffer
0
1
+
-
CLRPWM
>
overflow
Fcpu
Timer 0 overflow
Timer 1 overflow
Reserved
00
01
10
11
Divider
(/1, /2, /4, /8)
8-bit Up
Counter
PWM0OE
P1.5
PWMRUN
Vdd
overflow
PWM1
(P1.5)
PWM1L
Register
PWM1L
Buffer
0
1
+
-
FP.1~0
PCLK.1~0
>
PWM1OE
A compare value of all zeroes, 00H, causes the output to remain permanently high. A compare value of
all ones, FFH, results in the PWM output remaining permanently low.
The overall functioning of the PWM module is controlled by the contents of the PWMCON1 and
PWMCON3 registers. The operation of most of the control bits are straightforward. The transfer
Compare registers to the buffer registers is controlled by 8-bit counter overflow, while PWMCON1.7
(PWMRUN) allows the PWM to be either in the run or idle state. It has a CLRPWM bit to clear 8-bt up
counter.
When the PWMRUN is cleared, the PWM outputs take on the state they had just prior to the bit being
cleared. In general this state is not known. In order to place the outputs in a known state when
PWMRUN is cleared the Compare registers can be written to either the “all 1” or “all 0” so the output
will have the output desired when the counter is halted.
Note:
During PWM initial run, user is recommended to configure proper PWMn and/or PWM output pin (default high) follow by setting
PWMRUN and CLRPWM bits, prior to enable PWMnOE. This is to avoid unexpected PWM output.
- 110 -
Preliminary N79E352/N79E352R Data Sheet
22. I/O PORT
N79E352(R) has four 8 bits I/O ports; port 0, port 1, port 2, port 3, one partial port 4; P4.0 to P4.3 and
one partial port 5; P5.0 to P5.1. All pins of I/O ports (except port4) can be configured to one of four
types by software. User may configure the mode type for the above port pin by programming PxMy
SFRs.
Port 4 support only quasi mode.
PXM1.Y
PXM2.Y[Note]
PORT INPUT/OUTPUT MODE
0
0
0
1
Quasi-bidirectional.
Push-Pull
Input Only (High Impedance)
PORTS.PxS=0, TTL input
PORTS.PxS=1, Schmitt input
Open Drain
1
1
0
1
Table 22-1: I/O port configuration table
Note: X = 0-3 and 5. Y = 0-7.
In addition, port default mode is also configurable through CONFIG0.PMODE bit. When PMODE = 1,
ports 1~3 and 5 will default to quasi mode upon all reset. If PMODE = 0, ports 1~3 and 5 will default to
open drain mode upon all reset. See table below.
CONFIG0.PMODE
PORTS
UPON RESET
Open Drain
Quasi
PXM1,2 RESET VALUE
P0M1,2 = 1111 1111b
P(1~3)M1,2 = 0000 0000b
P(1~3)M1,2 = 1111 1111b
Not available.
X
1
0
X
1
P0
P1~3
P4
Open Drain
Quasi
P5M1 = xxxx x000b
P5M2 = xxxx xx00b
Quasi
P5[1]
0
P5M1 = xxxx x011b
P5M2 = xxxx xx11b
Open Drain
Table 22-2: Default port mode configuration by CONFIG0.PMODE bit.
Note: 1. Product configured to run internal rc.
All port pins can be determined to high or low after reset by configure PRHI bit in the CONFIG0
register.
Besides P4 is permenant Schmitt trigger intput, each I/O port of N79E352(R) may be selected to use
TTL level inputs or Schmitt inputs by P(n)S bit on PORTS SFR register; where n is 0, 1, 2, 3 or 5.
When P(n)S is set to 1, Ports are selected Schmitt trigger inputs on Port(n).
22.1 Quasi-Bidirectional Output Configuration
Publication Release Date: Jul, 29, 2009
- 111 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
The default port output configuration for standard N79E352(R) I/O ports is the quasi-bidirectional
output that is common on the 80C51 and most of its derivatives. This output type can be used as both
an input and output without the need to reconfigure the port. This is possible because when the port
outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is
pulled low, it is driven strongly and able to sink a fairly large current. These features are somewhat
similar to an open drain output except that there are three pull-up transistors in the quasi-bidirectional
output that serve different purposes. One of these pull-ups, called the “very weak” pull-up, is turned on
whenever the port latch for the pin contains a logic 1. The very weak pull-up sources a very small
current that will pull the pin high if it is left floating.
A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains a logic
1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a
quasi-bidirectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external
device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin
low under these conditions, the external device has to sink enough current to overpower the weak pull-
up and take the voltage on the port pin below its input threshold.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-high
transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1.
When this occurs, the strong pull-up turns on for a brief time, two CPU clocks, in order to pull the port
pin high quickly. Then it turns off again. The quasi-bidirectional port configuration is shown as below.
VDD
2 CPU
Clock Delay
Very
Weak
P
N
P
P
Strong
Weak
Port Pin
Port Latch
Data
Input Data
Figure 22-1: Quasi-Bidirectional Output
22.2 Open Drain Output Configuration
The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the
port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this
manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is
the same as for the quasi-bidirectional mode. The open drain port configuration is shown as below.
- 112 -
Preliminary N79E352/N79E352R Data Sheet
Port Pin
Port Latch
Data
N
Input Data
Figure 22-2: Open Drain Output
22.3 Push-Pull Output Configuration
The push-pull output configuration has the same pull-down structure as both the open drain and the
quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains
a logic 1. The push-pull mode may be used when more source current is needed from a port output.
The push-pull port configuration is shown below.
The value of port pins at reset is determined by the PRHI bit in the CONFIG0 register. Ports may be
configured to reset high or low as needed for the application. When port pins are driven high at reset,
they are in quasi-bidirectional mode and therefore do not source large amounts of current. Every
output on the device may potentially be used as a 20mA sink LED drive output. However, there is a
maximum total output current for all ports which must not be exceeded.
All ports pins of the device have slew rate controlled outputs. This is to limit noise generated by quickly
switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times.
VDD
P
Port Pin
Port Latch
Data
N
Input Data
Figure 22-3: Push-Pull Output
22.4 Input Only Mode
The input only port configuation is show in figure 21-4, it is a schmitt-triggered input or TTL input.
Publication Release Date: Jul, 29, 2009
- 113 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
Input Data
Port Pin
Schmitt-triggered or TTL
Figure 22-4: Push-Pull Output
- 114 -
Preliminary N79E352/N79E352R Data Sheet
23. OSCILLATOR
N79E352(R) provides three oscillator input option. These are configured at CONFIG register
(CONFIG0) that include On-Chip RC Oscillator Option, External Clock Input Option and Crystal
Oscillator Input Option. The Crystal Oscillator Input frequency may be supported from 4MHz to 24MHz,
and without capacitor or resister.
XTAL1
Oscillating
Circuit
External
XTAL
00
11
XTAL2
Fosc
Ext Clock
CPU Clock
Rate select
Fcpu
F
RC22M
RC11M
1
0
10
F
1/2
CD0 CD1
PMR[1:0]
F
F
OSC1
OSC0
FS1
(CONFIG1.5)
Internal
Oscillator
(22.1184MHz)
Timers, UART
PWM, I2C
WDT
Internal
Oscillator
(~20kHz)
BOD
For BOD in
power-saving
mode
ISP
Figure 23-1: Oscillator
23.1 On-Chip RC Oscillator Option
The On-Chip RC Oscillator is fixed at 11.0592MHz or 22.1184MHz (selectable by FS1 config bit) ±2%
for N79E352R, ±25% for N79E352 frequency to support clock source. When FOSC1, FOSC0 = 01b, the
On-Chip RC Oscillator is enabled.
23.2 External Clock Input Option
The clock source pin (XTAL1) is from External Clock Input by FOSC1, FOSC0 = 11b, and frequency
range is ffrom 0Hz up to 24MHz.
The device supports a clock output function when either the on-chip RC oscillator or external clock
input options are selected. This allows external devices to synchronize to the device. When enabled,
via the ENCLK bit in the P5M1 register, the clock output appears on the XTAL2/CLKOUT pin whenever
the on-chip oscillator is running, including in Idle Mode. The frequency of the clock output is 1/4 of the
CPU clock rate. If the clock output is not needed in Idle Mode, it may be turned off prior to entering
Publication Release Date: Jul, 29, 2009
- 115 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
Idle, saving additional power. The clock output may also be enabled when the external clock input
option is selected.
23.3 CPU Clock Rate select
The CPU clock of N79E352(R) may be selected by the PMR.CD0/1 bits. If (CD1,CD0) = 01b, the CPU
clock is running at 4 CPU clock per machine cycle, and without any division from source clock (Fosc).
This frequency division function affect all peripheral timings as they are all sourcing from the CPU
clock(Fcpu). The following table shows the PMR.CD1/0 bits definition.
CD1, CD0
Clocks/machine Cycle
0
1
1
x
0
1
4
64
1024
CD0/1 definitions
- 116 -
Preliminary N79E352/N79E352R Data Sheet
24. POWER MONITORING
In order to prevent incorrect operation during power up and power drop, the N79E352(R) provides two
power monitor function that are Power-On Detect and Brownout Detect.
24.1 Power On Detect
The Power–On Detect function is a design to detect power up after power voltage reaches to a level
where Brownout Detect can work. After power on detect, the POR (WDCON.6) will be set to “1” to
indicate an initial power up condition. The POR flag will be cleared by software.
24.2 Brownout Detect and Reset
The N79E352(R) has an on-chip Brown-out Detection circuit for monitoring the VDD level during
operation by comparing it to a programmable brownout trigger level. There are 4 brownout trigger
levels available for wider voltage applications. The 3 nominal levels are 2.6V, 3.8V and 4.5V
(programmable through BOV.1-0 bits). When VDD drops to the selected brownout trigger level (VBOR),
the brownout detection logics will either reset the CPU until the VDD voltage raises above VBOR or
requests a brownout interrupt at the moment that VDD falls and raises through VBOR. The brownout
detection circuits also provides a low power brownout detection mode for power saving. When
LPBOV=1, the brownout detection repeatly senses the voltage for 64/fBRC then turn off detector for
960/fBRC (fBRC = internal rc frequency), if VDD voltage still below brownout trigger level. fBRC, the
frequency of built-in RC oscillator is approximately 20KHz+/-100%.
The Brownout Detect block is shown in Figure 24-1.
BOV1
BOV0
Brownout Voltage
0
1
1
x
0
1
Brownout voltage is 2.6V
Brownout voltage is 3.8V
Brownout voltage is 4.5V
Brownout Voltage Selection
BOS
BOF
BOV[1:0]
To Reset
0
1
Brownout
Detect
Circuit
BOD
LPBOV
BOI
To Brownout interrupt
Figure 24-1: Brown-out Detect Block
Publication Release Date: Jul, 29, 2009
Revision A06
- 117 -
Preliminary N79E352/N79E352R Data Sheet
V
DD
VBOR+
VBOR -
Nominal Brown-
out Voltage
Brown-out Status
BOS
T
BOR
8ms
BOI=0 to select
Brown-out Reset
Reset
Clear by Software
Clear by Software
BOI=1 to select
Brown-out Interrupt
BOF
Set by Hardware
T
BOR :Brown-out Reset Delay Time with about 8mS
Figure 24-2: Brown-out Voltage Detection
- 118 -
Preliminary N79E352/N79E352R Data Sheet
25. ICP(IN-CIRCUIT PROGRAM) FLASH PROGRAM
The ICP(In-Circuit-Program) mode is another approach to access the Flash EPROM. There are only 3
pins needed to perform the ICP function. One is mode input, shared with RST pin, which must be kept
in Vdd voltage in the entire ICP working period. One is clock input, shared with P1.7, which accepts
serial clock from external device. Another is data I/O pin, shared with P1.6, that an external ICP
program tool shifts in/out data via P1.6 synchronized with clock(P1.7) to access the Flash EPROM of
N79E352(R).
(Note, While PRHI=0, P1.6, P1.7 are still quasi high during reset period. During reset period , P1.6,
P1.7 cann’t switch to open-drain by setting config).
Vcc
ICP Power
Jumper
ICP Connector
Vdd
Jumper
Vdd
Vpp
RST
P1.6
P1.7
To Reset or Input Pin
To I/O pin
Data
Clock
Vss
To I/O pin
Vss
ICP Program Tool
N79E352(R)
System Board
Figure 26-1: ICP Writer Tool connector pin assign
Note:
1.
When using ICP to upgrade code, the RST, P1.6 and P1.7 must be taken within design system
board.
2.
3.
4.
After program finished by ICP, to suggest system power must power off and remove ICP
connector then power on.
It is recommended that user performs erase function and programming configure bits
continuously without any interruption.
During ICP mode, all PWM pins will be tri-stated.
Publication Release Date: Jul, 29, 2009
- 119 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
26. CONFIG BITS
The N79E352(R) has two CONFIG bits (CONFIG0 located at FB00h, CONFIG1 located at FB01h) that
must be defined at power up and can not be set the program after start of execution. Those features
are configured through the use of two flash EPROM bytes, and the flash EPROM can be programmed
and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be
protected. The protection of flash EPROM (CONFIG1) and those operations on it are described below.
26.1 CONFIG0
7
6
5
4
-
3
2
1
0
WDTCK
PMODE
PRHI
CBOD
BPFR
Fosc 1
Fosc 0
WDTCK
PMODE
PRHI
CBOD
BPFR
Fosc1
Fosc0
: Watchdog Timer Clock Selection Bit.
: Port MODE Bit.
: Port Reset High Bit.
: Config Brownout Detect Enable Bit.
: Bypass Clock Filter Bit.
: CPU Oscillator Type Select Bit 1.
: CPU Oscillator Type Select Bit 0.
Figure 25-1: Config0 register bits
FUNCTION
Clock source of Watchdog Timer select bit:
BIT NAME
7
6
WDTCK 0: The internal 20KHz RC oscillator clock is for Watchdog Timer clock used.
1: The uC clock is for Watchdog Timer clock used.
Port Mode Type select bit:
PMODE 0: Port 1~3 and 5 reset to open drain mode.
1: Port 1~3 and 5 reset to quasi mode.
Port Reset High or Low select bit:
0: Port reset to low state.
PRHI
5
1: Port reset to high state.
Note: For product to run external program (/EA=0), user need to ensure PRHI is set to 1.
4
3
-
Reserved.
Config Brownout Detect Enable bit
0: Disable Brownout Detect.
1: Enable Brownout Detect.
Bypass Clock Filter.
CBOD
2
1
BPFR
Fosc1
0: Disable Clock Filter.
1: Enable Clock Filter.
CPU Oscillator Type select bit 1.
- 120 -
Preliminary N79E352/N79E352R Data Sheet
0
Fosc0
CPU Oscillator Type select bit 0.
Oscillator Configuration bits:
Fosc1
Fosc0
OSC source
0
0
0
1
4MHz ~ 24MHz crystal
Internal RC Oscillator (FS1 bit in CONFIG1.5 will determine
either 11.0592MHz or 22.1184MHZ)
Reserved
1
1
0
1
External Oscillator in XTAL1; XALT2 is in Tri-state
26.2 CONFIG1
7
6
5
4
-
3
2
1
0
-
C7
C6
FS1
CBOV.1-0
C1
C7
C6
: 8/4K Flash EPROM Code Lock Bit
: 512/256/128/64 byte Data Lock Bit
FS1
CBOV.1-0
C1
: Internal RC 11.0592MHz/22.1184MHz Selection Bit
: Brownout Level Selection Bits
: Movc Inhibit Enable Bit
Figure 25-2: Config1 register bits
C7: 8K Flash EPROM Lock bit
This bit is used to protect the customer’s program code. It may be set after the programmer finishes
the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data and
CONFIG Registers can not be accessed again.
C6: 128 byte Data Flash EPROM Lock bit
This bit is used to protect the customer’s 128 bytes of data code. It may be set after the programmer
finishes the programming and verifies sequence. Once this bit is set to logic 0, both the 128 bytes of
Flash EPROM data and CONFIG Registers can not be accessed again.
Bit 7 Bit 6 Function Description
1
1
Both security of 8KB program code and 128 Bytes data area are not locked. They can
be erased, programmed or read by Writer or JTAG mode.
0
1
The 8KB program code area is locked. It can not be read and written by Writer or
JTAG mode. The 128 Bytes data area can be program or read. The bank erase is
invalid.
1
0
0
0
Not supported.
Both security of 8KB program code and 128 Bytes data area are locked. They can not
be read and written by Writer or JTAG mode.
FS1: Internal Oscillator selection bit
This bit is used to select internal oscillator.
Publication Release Date: Jul, 29, 2009
Revision A06
- 121 -
Preliminary N79E352/N79E352R Data Sheet
FS1
0
Internal Oscillator Output
11.0592MHz
1
22.1184MHz (default)
Internal Oscillator Selection Table
CBOV.1-0: Brownout level selection bits
These bits are used to select brownout voltage level.
CBOV.1 CBOV.0 Brownout Voltage
1
0
0
x
1
0
Brownout voltage is 2.6V
Brownout voltage is 3.8V
Brownout voltage is 4.5V
C1: MOVC inhibit enable bit
MOVC inhibit MOVC access
enable bit
0
The MOVC instruction in external
memory cannot access the code in
internal memory.
1
No restriction.
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
- 122 -
Preliminary N79E352/N79E352R Data Sheet
27. ELECTRICAL CHARACTERISTICS
27.1 Absolute Maximum Ratings
SYMBOL
DC Power Supply
Input Voltage
PARAMETER
CONDITION
-0.3
RATING
+7.0
UNIT
V
VDD−VSS
VIN
VSS-0.3
-40
VDD+0.3
+85
V
Operating Temperature
Storage Temperature
Sink current
TA
°C
°C
mA
Tst
-55
+150
ISK
90
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
Publication Release Date: Jul, 29, 2009
- 123 -
Revision A06
Preliminary N79E352/N79E352R Data Sheet
27.2 D.C. Characteristics
(TA = -40~85°C, unless otherwise specified.)
SPECIFICATION
PARAMETER
Operating Voltage
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
2.4
5.5
V
VDD=4.5V ~ 5.5V @ 24MHz
VDD=2.7V ~ 5.5V @ 12MHz
VDD=2.4V ~ 5.5V @ 4MHz
Operating Current
IDD1
IDD2
IIDLE
5
15
4
mA
mA
mA
No load, RST = VDD, VDD= 3.0V
@ 11.0592MHz
No load, RST = VDD, VDD= 5.0V
@ 22.1184MHz
Idle Current
No load, VDD = 3.0V
@ 11.0592MHz
Power Down Current
IPWDN
1
1
5
5
µA
No load, VDD = 5.5V
@ Disable BOV function
No load, VDD = 3.0V
@ Disable BOV function
uA
Input / Output
Input Current P0, P1, P2, P3, P4,
P5
Input Current P1.5(RST pin)[1]
IIN1
IIN2
ILK
-50
-48
-10
-
-32
-
+10
-24
VDD = 5.5V, VIN = 0V or VIN=VDD
VDD = 5.5V, VIN = 0.45V
µA
µA
µA
µA
Input Leakage Current P0, P1,
P2, P3, P5 (Open Drain)
+10
VDD = 5.5V, 0<VIN<VDD
[*3]
ITL
-450
-93
0
-
-
-
-246
-56
1.0
0.6
1.0
VDD = 5.5V, VIN<2.0V
VDD=2.4 Vin = 1.3v
VDD = 4.5V
Logic 1 to 0 Transition Current
P0, P1, P2, P3, P4, P5
Input Low Voltage P0, P1, P2,
P3, P4, P5 (TTL input)
VIL1
V
0
-
VDD = 2.4V
2.0
1.5
0
-
-
-
-
-
-
V
DD +0.2
VDD +0.2
0.8
VDD = 5.5V
VDD = 2.4V
Input High Voltage P0, P1, P2,
P3, P4, P5 (TTL input)
VIH1
VIL3
VIH3
VILS
V
V
V
V
Input Low Voltage XTAL1[*2]
VDD = 4.5V
0
0.4
VDD = 3.0V
VDD = 5.5V
VDD = 3.0V
3.5
2.4
VDD +0.2
Input High Voltage XTAL1[*2]
VDD +0.2
Negative going threshold
(Schmitt input)
-0.5
-
-
0.3VDD
Positive going threshold
(Schmitt input)
VIHS
0.7VDD
VDD+0.5
1.6
V
Hysteresis voltage
Input Low Voltage RST [*1]
VHY
0.2VDD
1.0
V
V
V IL21
-
VDD=4.5V
- 124 -
Preliminary N79E352/N79E352R Data Sheet
V IL22
VIH21
VIH22
ISR1
-
0.7
2.3
1.5
-26
0.8
V
V
VDD=2.7V
Input High Voltage RST [*1]
3.5
2
VDD+0.2
VDD+0.2
-36
VDD=5.5V
V
VDD=2.7V
-16
mA
VDD = 4.5V, VS = 2.4V
Source Current P0, P1, P2, P3,
P5
-5
-7.9
-11
mA
VDD = 2.4V, VS = 2.0V
(PUSH-PULL Mode)
Source Current P0, P1, P2, P3,
P4, P5
-150
-39
13
-210
-53
-360
-69
24
VDD = 4.5V, VS = 2.4V
VDD = 2.4V, VS = 2.0V
VDD = 4.5V, VS = 0.45V
µA
µA
ISR2
(Quasi-bidirectional Mode)
Sink Current P0, P1, P2, P3, P4,
P5
18.5
mA
ISK2
(Quasi-bidirectional and PUSH-
PULL Mode)
9
15
21
VDD = 2.4V, VS = 0.45V
Brownout voltage with BOV[1:0]
=0xb
VBO2.4
VBO3.8
VBO4.5
2.55
3.65
4.35
2.6
3.8
4.5
2.85
3.95
4.65
V
V
V
Brownout voltage with BOV[1:0]
=10b
Brownout voltage with BOV[1:0]
=11b
VDD = 2.4V~5.5V,
35
10
-
-
150
60
mV
mV
(LPBOD,BOI) = (0,x) or (1,0)
VDD = 2.4V~5.5V,
Hysterisis range of BOD voltage
VBh
(LPBOD,BOI)=(1,1)
[*2]
-16
-5
-26
-7.9
18.5
15
-36
-11
24
Isk31
Isk32
Isr31
Isr32
mA
mA
mA
mA
VDD=4.5V, Vs = 0.45V
VDD=2.7V, Vs = 0.45V
Sink current
/PSEN
P0, P2, ALE,
[*2]
13
9
VDD=4.5V, Vs = 2.4V
Source current
/PSEN
P0, P2, ALE,
21
VDD=2.7V, Vs = 2.0V
Notes: *1. RST pin is a Schmitt trigger input. RST has internal pull-low resistor.
*2. XTAL1 is a CMOS input.
*3. Pins of P0, P1, P2, P3 and P5 can source a transition current when they are being externally driven from 1 to 0.
The transition current reaches its maximum value when Vin approximates to 2V.
27.3 A.C. Characteristics
tCLCL
tCLCH
tCLCX
tCHCL
tCHCX
Note: Duty cycle is 50%.
Publication Release Date: Jul, 29, 2009
Revision A06
- 125 -
Preliminary N79E352/N79E352R Data Sheet
27.3.1 External Clock Characteristics
PARAMETER
SYMBOL
tCHCX
tCLCX
MIN.
22.6
22.6
-
TYP.
MAX.
-
UNITS
nS
NOTES
Clock High Time
-
-
-
-
Clock Low Time
Clock Rise Time
Clock Fall Time
-
nS
tCLCH
10
10
nS
tCHCL
-
nS
27.3.2 AC Specification
VARIABLE CLOCK MIN.
VARIABLE CLOCK MAX.
PARAMETER
SYMBOL
UNITS
Oscillator Frequency
1/tCLCL
0
24
MHz
27.3.3 External clock Characteristics
PARAMETER SYMBOL MIN
TYP
MAX
UNITS
ns
NOTES
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
tCHCX
tCLCX
tCLCH
tCLCL
12.5
12.5
ns
10
10
ns
ns
tCLCL
tCLCH
tCLCX
tCHCX
tCHCL
Note: Duty cycle is 50%
Figure 26-1 External clock characteristics
27.3.4 Serial Port Mode 0 Timing Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Serial Port Clock Cycle Time
SM2=0 12 clocks per cycle
SM2=1 4 clocks per cycle
tXLXL
ns
12 tCLCL
4 tCLCL
Output Data Setup to Clock Rising Edge
SM2=0 12 clocks per cycle
SM2=1 4 clocks per cycle
tQVXH
ns
10 tCLCL
3 tCLCL
- 126 -
Preliminary N79E352/N79E352R Data Sheet
Output Data Hold to Clock Rising Edge
SM2=0 12 clocks per cycle
tXHQX
tXHDX
tXHDV
ns
ns
ns
2 tCLCL
tCLCL
SM2=1 4 clocks per cycle
Input Data Hold after Clock Rising
SM2=0 12 clocks per cycle
tCLCL
tCLCL
SM2=1 4 clocks per cycle
Clock Rising Edge to Input Data Valid
SM2=0 12 clocks per cycle
11 tCLCL
3 tCLCL
SM2=1 4 clocks per cycle
27.3.5 Program Memory Read Cycle
t
LHLL
t
LLIV
ALE
t
AVLL
t
PLPH
t
PLIV
PSEN
t
t
LLPL
PXIZ
t
PLAZ
t
t
PXIX
LLAX1
ADDRESS
PORT0
ADDRESS
A0-A7
INSTRUCTION
IN
A0-A7
t
AVIV1
AVIV2
t
PORT2
ADDRESS A8-15
ADDRESS A8-15
Figure 26-2 Program Memory Read Cycle
Publication Release Date: Jul, 29, 2009
Revision A06
- 127 -
Preliminary N79E352/N79E352R Data Sheet
27.3.6 Data Memory Read Cycle
t
LLDV
ALE
t
WHLH
t
LLWL
PSEN
RD
t
RLRH
t
LLAX1
t
RLDV
t
AVLL
t
RHDZ
t
RLAZ
t
AVWL1
t
RHDX
INSTRUCTION
IN
DATA
IN
ADDRESS
A0-A7
PORT0
PORT2
ADDRESS
A0-A7
t
t
AVDV1
AVDV2
ADDRESS A8-15
Figure 26-3 Data Memory Read Cycle
27.3.7 Data Memory Write Cycle
ALE
t
WHLH
t
LLWL
PSEN
t
WLWH
t
LLAX2
t
WR
AVLL
t
AVWL1
t
WHQX
t
QVWX
DATA OUT
ADDRESS
A0-A7
INSTRUCTION
IN
ADDRESS
A0-A7
PORT0
PORT2
t
AVDV2
ADDRESS A8-15
Figure 26-4 Data Memory Write Cycle
- 128 -
Preliminary N79E352/N79E352R Data Sheet
27.3.8 I2C Bus Timing Characteristics
PARAMETER
SYMBOL
Standard Mode I2C Bus UNIT
Min.
0
Max.
100
-
SCL clock frequency
fSCL
kHz
uS
bus free time between a STOP and START tBUF
condition
4.7
Hold time (repeated) START condition. After this tHd;STA
period, the first clock pulse is generated
4.0
-
uS
Low period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
4.7
4.0
4.7
5.0
250
-
-
uS
uS
uS
uS
nS
nS
nS
uS
pF
-
-
-
Data set-up time
-
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
1000
300
-
tf
-
tSU;STO
Cb
4.0
-
400
Repeated
START
STOP
START
STOP
SDA
SCL
tBUF
tLOW
tr
tf
tHIGH
tHD;STA
tSU;STA
tSU
tHD;DAT
tSU;DAT
Figure 26-5: I2C Bus Timing
EXPLANATION OF LOGIC SYMBOLS
In order to maintain compatibility with the original 8051 family, this device specifies the same
parameter as such device, using the same symbols. The explanation of the symbols is as follows.
t
Time
A
D
L
Address
C
H
Clock
Input Data
Logic level low
Logic level high
I
Instruction
P
R
PSEN
Q
Output Data
RD signal
V
X
Valid
W
Z
WR signal
Tri-state
No longer a valid state
Publication Release Date: Jul, 29, 2009
Revision A06
- 129 -
Preliminary N79E352/N79E352R Data Sheet
27.4 RC OSC AND AC CHARACTERISTICS
(VDD−VSS = 2.4~5V, TA = -40~85°C.)
Specification (reference)
Parameter
Test Conditions
Min.
Typ.
Max.
25
Unit
%
-25
VDD=2.4V~5.5V, TA = -40°C ~85°C
Frequency accuracy
of On-chip RC
oscillator
(for N79E352)
-2
-5
-7
-9
2
5
7
9
%
%
VDD=4.5V~5.5V, TA = 25°C
Frequency accuracy
of On-chip RC
oscillator with
VDD=2.7V~5.5V, TA = 0~85°C
VDD=2.7V~5.5V, TA = -20~85°C
VDD=2.7V~5.5V, TA = -40~85°C
calibration1
%
(for N79E352R)
%
256
clk
Wakeup time
Note:
1. These values are for design guidance only and are not tested.
27.5 Typical Application Circuit
CRYSTAL
C1
C2
R
4MHz ~ 24MHz
without
without
without
The above table shows the reference values for crystal applications.
C1
XTAL1
R
XTAL2
C2
N79E352(R)
- 130 -
Preliminary N79E352/N79E352R Data Sheet
28. PACKAGE DIMENSIONS
28.1 40-pin DIP
D
40
21
1
E
20
1
E
S
c
2
1
Base Plane
A
A
L
A
Seating Plane
B
e1
eA
α
B1
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
0.210
Max
5.33
A
1
A
2
A
0.010
0.150
0.25
0.155 0.160
3.81
0.41
1.22
0.20
3.94
0.46
4.06
0.56
0.016 0.018
0.022
0.054
B
0.050
1.27
1.37
0.048
0.008
1
B
c
0.36
0.010 0.014
2.055 2.070
0.25
52.58
15.49
13.97
2.79
52.20
15.24
13.84
2.54
D
E
0.610
0.590 0.600
14.99
13.72
0.540
0.545
1
0.550
0.110
E
1
e
0.090 0.100
2.29
3.05
0
0.140
15
3.30
0.120
0
0.130
0.650
3.56
15
L
α
A
e
17.02
2.29
0.630
0.670 16.00
0.090
16.51
S
Publication Release Date: Jul, 29, 2009
Revision A06
- 131 -
Preliminary N79E352/N79E352R Data Sheet
28.2 44-pin PLCC
H D
D
6
1
44
40
7
39
E
H
E
G
E
17
29
18
28
c
L
2
A
A
1
A
e
b
y
b1
Seating Plane
G D
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
0.185
Max
4.70
A
0.020
0.145
0.51
1
A
0.150
3.81
0.71
0.46
0.25
2
A
3.68
3.94
0.81
0.56
0.36
0.155
0.026 0.028
0.018
0.032 0.66
1
b
b
c
0.022
0.41
0.016
0.008 0.010 0.014 0.20
16.46 16.59 16.71
0.648 0.653 0.658
D
16.59
15.49
16.46
16.71
0.653
0.648
0.658
BSC
0.630
E
e
G
G
H
H
L
y
1.27
BSC
0.050
0.590
0.590
0.680
0.680
0.090
14.99
16.00
16.00
D
0.610
14.99 15.49
0.610 0.630
E
17.27
17.27
17.53 17.78
17.53 17.78
0.700
0.700
0.690
0.690
0.100
D
E
2.54
2.79
0.110 2.29
0.004
0.10
- 132 -
Preliminary N79E352/N79E352R Data Sheet
28.3 44-pin PQFP
HD
D
34
44
33
1
E
E
H
11
12
22
e
b
c
2
A
A
1
See Detail F
L
A
y
Seating Plane
L1
Detail F
Dimension in inch
Dimension in mm
Symbol
Nom
Nom
Min
Max Min
Max
-
-
A
1
A
2
A
b
c
D
E
e
0.002 0.01
0.02
0.25
2.05
0.35
0.15
10.00
10.00
0.80
0.05
1.90
0.25
0.10
9.9
0.5
2.20
0.45
0.25
10.1
10.1
0.081 0.087
0.075
0.01
0.014
0.006
0.018
0.010
0.004
0.390
0.390
0.394 0.398
0.394 0.398
.0315
9.9
D
H
0.530
0.520
0.510
12.95
13.20 13.45
0.530 12.95 13.20 13.45
0.510 0.520
HE
L
0.65
0.037
0.8
0.025
0.031
0.063
0.95
1.60
1
L
y
0.10
10
0.004
10
0
0
0
Publication Release Date: Jul, 29, 2009
Revision A06
- 133 -
Preliminary N79E352/N79E352R Data Sheet
28.4 48-pin LQFP
- 134 -
Preliminary N79E352/N79E352R Data Sheet
29. REVISION HISTORY
VERSION
A01
DATE
PAGE
DESCRIPTION
Aug, 14, 2008
Aug, 21, 2008
-
Initial Issued
A02
7,8
Update pin configurations.
-
-
A03
Feb, 2, 2009
Add access external memory diagram
Modify the part no. with each package
1. 40DIP: N79E352ADG, N79E352RADG
2. 44PLCC: N79E352APG, N79E352RAPG
3. 44PQFP: N79E352AFG, N79E352RAFG
4. 48LQFP: N79E352ALG, N79E352RALG
1. Correct typo errors.
A04
Feb, 9, 2009
-
108~109 2. Release input capture 0 function in Section 20.
3. Re-arrange section sequency after Section 20.
124~125 2. Update D.C specification.
A05
A06
Apr, 22, 2009
Jul, 29, 2009
3. Renew Figure 0-1: Oscillator
1. Add ICP description.
115
119
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Publication Release Date: Jul, 29, 2009
- 135 -
Revision A06
相关型号：
©2020 ICPDF网 联系我们和版权申明