NCN6000/D_技术文档

NCN6000

Product Preview

Compact Smart Card

Interface IC

The NCN6000 is an integrated circuit dedicated to the smart card

interface applications. The device handles any type of smart card

through a simple and flexible microcontroller interface. On top of that,

thanks to the built–in chip select pin, several couplers can be

connected in parallel. The device is particularly suited for low cost,

low power applications, with high extended battery life coming from

extremely low quiescent current.

http://onsemi.com

MARKING

DIAGRAM

20

Features

TSSOP–20

TBD

CASE 948E

TBD

20

• 100% Compatible with ISO 7816–3 and EMV Standard

• Wide Battery Supply Voltage Range: 2.7 < Vbat < 6.0 V

1

• Programmable Vcc Supply to Cope with either 3.0 V or 5.0 V Card

Operation

A

WL, L

YY, Y

= Assembly Location

= Wafer Lot

= Year

• Built–in DC/DC Converter Generates the Vcc Supply with a Single

External Low Cost Inductor only, providing a High Efficiency Power

Conversion

WW, W = Work Week

• Full Control of the Power Up/Down Sequence Yields High Signal

Integrity on both the Card I/O and the Signal Lines

• Programmable Card Clock Generator

• Built–in Chip Select Logic allows Parallel Coupling Operation

• ESD Protection on Card Pins (4.0 kV, Human Body Model)

PIN CONNECTIONS

A0

A1

1

V

L

20

19

bat

H

L

2

3

4

5

6

out_

PGM

PWR_ON

STATUS

CS

L

18

17

16

15

14

13

12

11

• Fault Monitoring includes Vbat and Vcc

providing Logic

low

low,

PWR_GND

GROUND

Feedback to External CPU

• Card Detection Programmable to Handle Positive or Negative Going

Input

CRD_V

CC

• Built–in Programmable CRD_CLK Stop Function Handle both High

RESET

I/O

CRD_IO

7

8

or Low State

CRD_CLK

CRD_RST

CRD_DET

INT

Typical Application

• E–Commerce Interface

• ATM Smart Card

• Pay TV System

9

CLOCK_IN

10

(Top View)

ORDERING INFORMATION

Device

NCN6000

Package

Shipping

TBD

TSSOP–20

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

November, 2000 – Rev. 0

NCN6000/D

NCN6000

+5 V

V

C1

10 µF

CC

U?

1

2

3

4

5

6

7

8

9

20

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

IRQ

A0

V

bat

GND

L1

19

18

17

16

15

14

13

12

A1

L

out_H

22 µF

L

PGM

PWR_ON

STATUS

CS

out_L

PWR_GND

GROUND

C2

C3

10 µF

GND

100 nF

CRD_V

CC

CRD_IO

CRD_CLK

CRD_RST

17

RESET

I/O

Swa

GND

18

8

Swb

C8

INT

10

11

4

CLOCK_IN CRD_DET

XTAL

C4

3

NCN6000

MCU GND

CLK

RST

2

1

GND

V

CC

5

GND

I/O

7

VPP

J1

SMARTCARD

Figure 1. Typical Application

http://onsemi.com

2

NCN6000

+V

bat

V

+

-

20

11

bat

V

bat_OK

2.0 V

50 k

V

bat

INT

9

500 k

GND

CRD_DET

50 µs

Delay

Q

S

R

GND

CARD DETECTION

+V

bat

POLARITY

PROGRAMMABLE

STATUS INT

50 k

CS

6

CLK STOP

V

CC

F

CLOCK

out

3

2

PGM

A1

DC/DC CONVERTER

DATA

SELECT

15

19

18

17

CRD_V

CC

DECODER

1:16

Power Down

Active Pwr_Down

L

out_H

A0

1

Set_V

CC

3 V / 5 V

GND

L

out_L

1/1

1/2

10

FAULT

ON/OFF

CLOCK_IN

PWR_GND

GROUND

CLOCK

DIVIDER

1/4

1/8

STATUS INT

16

DC/DC STATUS

ENABLE V

GND

CARD STATUS

LOGIC & CARD PINS SEQUENCER

CC

4

5

V

CC

PWR_ON

STATUS

V

bat

V

bat

V

bat_OK

50 k

CLOCK

CLK_STOP

SEQ 2

CRD_CLK

13

CLOCK

2

A

V

bat

1

GND

V

20 k

bat_OK

SEQ 1

I/O

CRD_IO

14

I/O

8

7

DATA

V

bat

1

2

3

RESET

CRD_RST

12

RESET

SEQ 3

PWR_ON

Figure 2. Block Diagram

http://onsemi.com

3

NCN6000

The programming can be achieved with the card powered

table in Figure 3. During the programming mode, the PGM

pin can be released to High since the mode is internally

latched by the Negative going transition presents on the Chip

Select pin.

ON or OFF. The identification of the interrupt is carried out

by polling the STATUS pin, the Vbat voltage and the DC/DC

results being provided on the same pin as depicted by the

INTERRUPT

ACKNOWLEDGE

CARD IDENTIFICATION

POLLING

CARD EXTRACTED

50 µs

CRD_DET

INT

CS

PGM

High

A0

A1

Low

STATUS

S1 CLEAR INTERRUPT

S2 CARD PRESENT: STATUS = 1

S3 CLEAR INTERRUPT

S4 CARD PRESENT: STATUS = 0

Figure 4. Interrupt Servicing and Card Polling

When a card is either inserted or extracted, the CRD_DET

pin signal is debounced internally prior to pull the INT pin

to Low. The built–in logic circuit automatically

accommodates positive or negative input signal slope, on

both insertion and extraction state, depending upon the

polarity defined during the initialization sequence. The

default condition is Normally Open switch, negative going

card detection. The external CPU shall acknowledge the

request by forcing CS = L which, in turn, releases the INT

pin to High upon positive going of Chip Select (see Table 5).

Polling the STATUS pin as depicted in Table 3 identifies the

active card. If a card is present, the STATUS returns High,

otherwise a Low is presented pin 5. The 50 µs digital filter

is activated during both Insertion and Extraction of the card.

The MPU shall clear the INT line when the card has been

extracted, making the interrupt function available for other

purposes. However, neither the NCN6000 operation nor the

smart card I/O line or commands are affected by the state of

the INT pin.

On the other hand, clearing the INT and reading the

STATUS register can be performed by a single read by the

MPU: states S1 and S2 can be combined in a single

instruction, the same for S3 and S4.

http://onsemi.com

5

NCN6000

ABBREVIATIONS

Lout_H

Lout_L

Cout

VCC

Icc

DC/DC External Inductor

Output Capacitor

Card Power Supply Input

Current at CRD_VCC Pin

5.0 V Smart Card

Class A

Class B

CS

3.0 V Smart Card

Chip Select (from MPU)

Z

High Impedance Logic State

(according to ISO7816)

CRD_VCC

CRD_CLK

CRD_RST

CRD_IO

CRD_DET

ATR

Interface IC Card Power Supply Output

Interface IC Card Clock Output

Interface IC Card Reset Output

Interface IC Card I/O Signal Line

Interface IC Card Detection

Answer to Reset

PGM

Select Programming or Normal Operation

Interrupt (to MPU)

INT

PIN FUNCTIONS AND DESCRIPTION

Name

Type

Description

1

A0

INPUT

This pin is combined with A1, PGM, RESET and I/O to program the chip mode of

operation and to read the data provided by STATUS.

(See Figures 3 and 4 and Tables 2 and 3)

2

3

4

A1

INPUT

This pin is combined with A0, PGM, RESET and I/O to program the chip mode of

operation and to read the data provided by STATUS.

(See Figures 3 and 4 and Tables 2 and 3)

PGM

This pin is combined with A0, A1, RESET and I/O to program the chip mode of

operation and to read the data provided by STATUS.

(See Figures 3 and 4 and Tables 2 and 3)

PWR_ON

INPUT

Pull Down

This pin validates the operation of the internal DC/DC converter:

CS = L + PWR_ON = Negative going: DC/DC is OFF

CS = L + PWR_ON = Positive going: DC/DC is ON

Note: The PWR_ON bit must be combined with a Low state CS signal to activate

the function.

5

6

STATUS

CS

OUTPUT

This pin provides logic state related to the card and NCN6000 status. According to

the A0, A1 and PGM logic state, this pin carries either the Card present status or the

Vbat or the DC/DC operation state. When PGM = L, STATUS is not affected.

INPUT

Pull Up

This pin provides the NCN6000 chip select function. The PWR_ON, RESET, I/O, A0,

A1 and PGM signals are disabled when CS = H. When PGM = L and CS = L, the

device jumps to the programming mode (See Figure 3 and Tables 1, 2 and 3). The

Chip Select pin must be a unique physical address when more than one card are

controlled by a single MPU. The data presented by the MPU are latched upon

positive going edge of the Chip Select pin.

7

RESET

INPUT

Pull Down

This pin provides two modes of operation depending upon the logic state of PGM

pin 3:

PGM = 1: The signal present on this pin is translated to pin 14 (card reset

signal) when CS = L and PWR_ON = H. It is latched when CS = H.

PGM = 0: The signal present on this pin is used as a logic input to program the

internal functions (See Figure 4 and Tables 1 and 2).

http://onsemi.com

6

NCN6000

PIN FUNCTIONS AND DESCRIPTION (continued)

Name

Type

Description

8

I/O

Input/Output

Pull Up

This pin is connected to an external microcontroller interface. A bidirectional level

translator adapts the serial I/O signal between the smart card and the

microcontroller. The level translator is enabled when CS = L. The signal present on

this pin is latched when CS = H. This pin is also used in programming mode

(See Tables 1, 2 and 3, Figures 3 and 4).

9

INT

OUTPUT

Pull Down

This pin is activated LOW when a card has been inserted and detected by the

interface or when the NCN6000 reports Vbat or CRD_VCC status (See Table 5). The

signal is reset to a logic 1 on the rising edge of either CS or PWR_ON. The Collector

open mode makes possible the wired AND/OR external logic. When two or more

interfaces share the INT function with a single microcontroller, the software must poll

the STATUS pin to identify the origin of the interrupt (See Figure 4).

10

11

CLOCK_IN

CRD_DET

CLOCK INPUT

High Impedance

This pin can be connected to either the microcontroller master clock, or to any clock

signal, to drive the external smart cards. The signal is fed to internal clock selector

circuit and translated to the CRD_CLK pin at either the same frequency, or divided

by 2 or 4 or 8, depending upon the programming mode (See Table 2).

INPUT

The signal coming from the external card connector is used to detect the presence of

the card. A built–in pull up low current source makes this pin active LOW or HIGH,

assuming one side of the external switch is connected to ground. At Vbat start up,

the default condition is Normally Open switch, negative going insertion detection.

The Normally Closed switch, positive going insertion detection, can be defined by

programming the NCN6000 accordingly. In this case, the polarity must be set up

during the first cycles of the system initialization, otherwise an already inserted card

will not be detected by the chip.

12

13

CRD_RST

CRD_CLK

OUTPUT

This pin is connected to the RESET pin of the card connector. A level translator

adapts the RESET signal from the microcontroller to the external card. The output

current is internally limited to 15 mA. The CRD_RST is validated when PWR_ON =

H and PGM = H and hard wired to Ground when the card is deactivated.

This pin is connected to the CLK pin of the card connector. The CRD_CLK signal

comes from the clock selector circuit output. Combining A0, A1, PGM and I/O, as

depicted in Table 3 and Figure 3, programs the clock selection. This signal can be

forced into a standby mode with CRD_CLK either High or Low, depending upon the

mode defined by the programming sequence (See Tables 1 and 2 and Figure 3).

14

15

CRD_IO

I/O

This pin handles the connection to the serial I/O pin of the card connector. A

bidirectional level translator adapts the serial I/O signal between the card and the

microcontroller. The CRD_IO pin current is internally limited to 15 mA. A built–in

register holds the previous state presents on the I/O input pin.

CRD_VCC

POWER

This pin provides the power to the external card. It is the logic level “1” for CRD_IO,

CRD_RST and CRD_CLK signals. The energy stored by the DC/DC external

inductor Lout must be smoothed by a 10 µF capacitor, associated with a 100 nF

ceramic in parallel, connected across CRD_VCC and GND. In the event of a

CRD_VCC U

voltage, the NCN6000 detects the situation and feedback the

VLOW

information in the STATUS bit. The device does not take any further action,

particularly the DC/DC converter is neither stopped nor reprogrammed by the

NCN6000. It is up to the external MPU to handle the situation. However, when the

CRD_VCC is overloaded, the NCN6000 shut off the DC/DC converter, pulls the INT

pin Low and reports the fault in the STATUS register.

16

GROUND

SIGNAL

The logic and low level analog signals shall be connected to this ground pin. This pin

must be externally connected to the PWR_GND pin 17. The designer must make

sure no high current transients are shared with the low signal currents flowing into

this pin.

17

18

PWR_GND

Lout_L

POWER

This pin is the Power Ground associated with the built–in DC/DC converter and must

be connected to the system ground together with GROUND pin 11. Using good

quality ground plane is recommended to avoid spikes on the logic signal lines.

The High Side of the external inductor is connected between this pin and Lout_H to

provide the DC/DC function. The built–in MOS devices provide the switching function

together with the CRD_VCC voltage rectification.

http://onsemi.com

7

NCN6000

PIN FUNCTIONS AND DESCRIPTION (continued)

Name

Type

Description

19

Lout_H

POWER

The High Side of the external inductor is connected between this pin and Lout_L to

provide the DC/DC function. The current flowing into this inductor is performed by a

sense resistor internally connected from Vbat/pin 20 and pin 19. Typically, Lout =

22 µH, with ESR < = 1.0 Ω, for a nominal 55 mA output load.

20

Vbat

POWER

This pin is connected to the supply voltage and monitored by the NCN6000. The

operation is inhibited when Vbat is below the minimum 2.70 V value, followed by a

PWR_DOWN sequence and a Low STATUS state.

MAXIMUM RATINGS

Rating

Symbol

Vbat

Ibat

Value

7.0

Unit

V

Battery Supply Voltage

Battery Supply Current

Power Supply Voltage

Power Supply Current

Digital Input Pins

"200

6.0

mA

V

Vcc

Icc

"100

mA

V

Vin

–0.5 V < V < V +0.5 V,

in bat

but < 7.0 V

Digital Input Pins

Iin

"5.0

mA

V

Digital Output Pins

Vout

–0.5 V < V < V +0.5 V,

in bat

but < 7.0 V

Digital Output Pins

Card Interface Pins

Inductor Current

Iout

Vcard

Icard

ILout

VESD

"10

mA

V

–0.5 V < V

< V +0.5 V

cc

card

"25

mA

kV

200

ESD Capability (See Note 2.)

Standard Pins

Card Interface Pins and CRD_DET

2.0

4.0

TSSOP–20 Package

Power Dissipation @ Tamb = +85°C

Thermal Resistance Junction to Air (Rthja)

P

Rθja

TBD

mW

°C/W

DS

Operating Ambient Temperature Range

Operating Junction Temperature Range

Maximum Junction Temperature (Note 3.)

Storage Temperature Range

TA

–25 to +85

–25 to +125

+150

°C

TJ

TJmax

Tsg

–65 to +150

1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T = +25°C.

A

2. Human Body Model, R = 1500 Ω, C = 100 pF.

3. Absolute Maximum Rating beyond which damage to the device may occur.

http://onsemi.com

8

NCN6000

POWER SUPPLY SECTION (–25°C to +85°C ambient temperature, unless otherwise noted.)

Rating

Symbol

20

Min

2.7

–

Typ

–

Max

Unit

V

Power Supply

Vbat

6.0

Standby Supply Current Conditions:

PWR_ON = L, STATUS = H, CLOCK_IN = H,

CS = H. All other logic inputs and outputs are open:

Vbat = 3.0 V

Ibat

20

–

µA

sb

op

5.0

15

Vbat = 5.0 V

DC Operating Current @ Vbat = 6.0 V, Vcc = 5.0 V

PWR_ON = H, CLOCK_IN = 0, CS = H, all CRD pins

unloaded

Ibat

20

–

TBD

mA

Vbat Undervoltage Detection

Vbat

20

15

2.2

2.1

–

2.35

2.25

100

2.7

2.6

–

V

mV

High

LH

Low

LL

Vbat

Hysteresis

HY

Output Card Supply Voltage @ Icc = 55 mA

@ 2.70 V < Vbat < 6.0 V

CRD_VCC = 3.0 V

Vcc

V

2.75

4.75

–

3.25

5.25

C3H

C5H

CRD_VCC = 5.0 V

@ Vbat < Vbat < 2.70 V

LL

CRD_VCC = 5.0 V

V

4.50

55

–

C5H

Output Card Supply Peak Current @ Vcc = 5.0 V

Output Current Limit Time Out

Output Over Current Limit

Iccp

tdoff

Iccov

Iccd

15

mA

ms

mA

4.0

–

85

–

Output Dynamic Peak Current @ Vcc = 3.0 V or 5.0 V,

Cout = 10 µF + 100 nF Ceramic, Pulse Width 400 ns

(See Notes 4. and 5.)

100

–

Battery Start–Up Current

@ Vcc = 3.0 V

0°C < TA < +85°C

–25°C < TA < 0°C

@ Vcc = 5.0 V

Icc

20

TBD

–

mA

st

0°C < TA < +85°C

–25°C < TA < 0°C

Output Card Supply Voltage Ripple @ Lout = 22 µH,

Cout 1 = 10 µF, Cout 2 = 100 nF

Vcc

15

–

mV

rip

Iout = 55 mA

(See Note 4.)

Vcc = 5.0 V

Vcc = 3.0V

50

Output Card Supply Turn On Time @ Lout = 22 µF,

Cout1 = 10 µF, Cout2 = 100 nF, Vbat = 2.7 V,

Vcc = 5.0 V

Vcc

15

–

2.0

ms

TON

Output Card Supply Shut Off Time @ Cout1 = 10 µF,

Vcc

250

µs

TOFF

Cout2 = 100 nF, Vbat = 2.7 V, Vcc = 5.0 V,

Vcc

< 0.4V

OFF

DC/DC Converter Operating Frequency

Power Switch Drain/Source Resistor

Output Rectifier ON Resistor

Fsw

18

15

–

600

–

kHz

Ω

R

ONS

R

OND

TBD

–

Ω

4. Ceramic, SMD type capacitors are mandatory to achieve the CRD_VCC specifications. When electrolytic capacitor is used, the external filter

must include a 100 nF, max 50 mΩ ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum. A good way

is to use 3 x 3.3 µF/ceramic capacitors in parallel.

5. According to ISO7816–3, paragraph 4.3.2.

http://onsemi.com

9

NCN6000

DIGITAL PARAMETERS SECTION @ 2.70 V < Vbat < 6.0 V, NORMAL OPERATING MODE (–25°C to +85°C ambient

temperature, unless otherwise noted.)

Rating

Symbol

Min

Typ

Max

Unit

Input Asynchronous Clock

Duty Cycle = 50%

Clock Rise Time

F

CLKIN

10

–

40

5.0

MHz

ns

Clock Fall Time

I/O Data Transfer Switching Time,

Both Directions (I/O and CRD_IO),

@ Cout = 30 pF

8, 14

–

µs

I/O Rise Time* (See Note 6.)

I/O Fall Time

T

1.0

RIO

FIO

Input/Output Data Transfer Time, Both

Directions @ 50% Vcc, L to H and H to L

T

8, 14

4

–

150

ns

TIO

Minimum PWR_ON Low Level Logic State

Time to Power Down the DC/DC

Converter

T

WON

2.0

–

µs

Vcc Power Up/Down Sequence Interval

STATUS Pull Up Resistance

T

–

0.5

50

–

2.0

70

µs

kΩ

V

DSEQ

R

5

6

9

30

STA

Chip Select CS Pull Up Resistance

Interrupt INT Pull Up Resistance

R

70

CSPU

INTPU

R

30

70

Positive Going Input High Voltage

Threshold (A0, A1, PGM, PWR_ON, CS,

RESET, CLOCK_IN, CRD_DET)

V

IH

1, 2,

3, 4,

6, 7,

0.70 * Vbat

Vbat + 0.3

10, 11

Negative Going Input High Voltage

Threshold (A0, A1, PGM, PWR_ON, CS,

RESET, CLOCK_IN, CRD_DET)

V

IL

1, 2,

3, 4,

6, 7,

–0.3

–

0.30 * Vbat

V

10, 11

Output High Voltage

V

5, 9

Vbat – 1.0 V

–

V

OH

STATUS, INT @ I = –10 µA

OH

Output High Voltage

V

0.40

OL

STATUS, INT @ I = 200 µA

OH

6. Since a 20 kΩ pull up resistor is provided by the NCN6000, the external MPU can use an Open Drain connection.

DIGITAL PARAMETERS SECTION @ 2.70 V < Vbat < 6.0 V, CHIP PROGRAMMING MODE (–25°C to +85°C ambient

temperature, unless otherwise noted.)

Rating

Symbol

Min

Typ

Max

Unit

A0, A1, PGM, PWR_ON, RESET and I/O

Data Set Up Time

T

1, 2,

3, 4,

7, 8

2.0

–

SMOD

HMOD

µs

A0, A1, PGM, PWR_ON, RESET and I/O

Data Set Up Time

T

1, 2,

3, 4,

7, 8

2.0

–

µs

Chip Select CS Low State Pulse Width

T

6

WCS

http://onsemi.com

10

NCN6000

SMART CARD SECTION (–25°C to +85°C ambient temperature, unless otherwise noted.)

Rating

Symbol

Min

Typ

Max

Unit

CRD_RST @ Vcc = +5.0 V

12

–

Output RESET V @ Irst = –20 µA

V

OL

Vcc –0.9

–0.3

Vcc

0.4

V

OH

Output RESET V @ Irst = 200 µA

OL

Output RESET Rise Time @ Cout = 30 pF

Output RESET Fall Time @ Cout = 30 pF

t

100

ns

R

F

CRD_RST @ Vcc = +3.0 V

Output RESET V @ Irst = –20 µA

V

OL

Vcc –0.9

–0.3

Vcc

0.4

V

OH

Output RESET V @ Irst = 200 µA

OL

Output RESET Rise Time @ Cout = 30 pF

Output RESET Fall Time @ Cout = 30 pF

t

100

ns

R

F

CRD_CLK @ Vcc = +3.0 V or Vcc = 5.0 V

13

–

CRD_VCC = +5.0 V

Output Frequency (See Note 7.)

Output Duty Cycle @ DC Fin = 50% "1%

Output CRD_CLK Rise Time @ Cout = 30 pF

Output CRD_CLK Fall Time @ Cout = 30 pF

Output CRD_CLK Delay

F

5.0

55

18

MHz

%

ns

V

CRDCLK

45

CRDDC

t

R

t

F

18

t

D

TBD

Vcc +0.3

+0.5

Output V @ Iclk = –20 µA

V

OH

3.15

–0.3

OH

Output V @ Iclk = 100 µA

V

OL

V

OL

CRD_VCC = +3.0 V

Output Frequency (See Note 7.)

Output Duty Cycle @ DC Fin = 50% "1%

Output CRD_CLK Rise Time @ Cout = 30 pF

Output CRD_CLK Fall Time @ Cout = 30 pF

Output CRD_CLK Delay

F

5.0

60

18

MHz

%

ns

V

CRDCLK

40

CRDDC

t

R

t

F

18

t

D

TBD

Vcc +0.3

0.7

Output V @ Iclk = –20 µA @ Cout = 30 pF

V

OH

1.85

–0.3

OH

Output V @ Iclk = 100 µA @ Cout = 30 pF

V

OL

V

OL

CRD_I/O @ CRD_VCC = +5.0 V

CRD_I/O Data Transfer Frequency

CRD_I/O Rise Time @ Cout = 30 pF

CRD_I/O Fall Time @ Cout = 30 pF

CRD_I/O Delay Time

14

F

315

kHz

µs

ns

V

IO

T

RIO

1.0

TBD

Vcc

0.4

T

FIO

DIO

Output V @ Icrd = –20 µA

V

OH

Vcc –0.9

–0.3

OH

Output V @ Iclk = 1.0 mA, V = 0 V

V

OL

V

OL

IL

CRD_I/O @ CRD_VCC = +3.0 V

CRD_I/O Data Transfer Frequency

CRD_I/O Rise Time @ Cout = 30 pF

CRD_I/O Fall Time @ Cout = 30 pF

CRD_I/O Delay Time

kHz

µs

F

IO

1.0

TBD

T

RIO

T

FIO

ns

T

DIO

Output V @ I = –20 µA

V

OL

Vcc –0.9

–0.3

Vcc

0.4

V

OH

Output V @ I = 1.0 mA, V = 0 V

OL

IL

CRD_IO Pull Up Resistor @ PWR_ON = H

R

14

11

14

20

–

26

kΩ

CRDPU

Card Detection Debouncing Delay:

Card Insertion

Card Extraction

T

50

150

µs

CRDIN

T

CRDOFF

Card Insertion or Extraction Positive Going Input

High Voltage

V

11

0.70 * Vbat

–

Vbat + 0.3

0.30 * Vbat

TBD

V

IHDET

Card Insertion or Extraction Negative Going

Input Low Voltage

V

–0.3

–

V

ILDET

Card Detection Bias Pull Up Current @

Vbat = 5.0 V

I

15

–

µA

mA

DET

Output Peak Max Current Under Card Static

Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V

Icrd

12,

13, 14

5.0

15

7. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over

the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz.

http://onsemi.com

11

NCN6000

Programming and Status Functions

The NCN6000 features a programming interface and a status interface. Figure 3 illustrates the programming mode.

Table 1. Programming and Status Functions Pinout Logic

CRD_VCC

Prg. 3.0 V/5.0 V

CLOCK_IN

Divide Ratio

CLOCK STOP Poll Card DC/DC

Vbat

Status

CRD_VCC

Status

AND START

Status

READ

0

Status

READ

0

Pins

Name

STATUS

CS

CRD_DET

5

6

Not Affected

READ

0

READ

0

Latch On

Rising Edge

3

1

2

7

8

PGM

A0

0

0/1

1

0

0/1

0

1

0

Z

1

0

Z

1

0

1

Z

1

Z

0/1

0

0/1

0

A1

RESET

I/O (in)

1

0/1

Card VCC, Card CLOCK and Card Detection

Polarity Programming

I/O logic states for the possible options. The default power

reset condition is state 1: asynchronous clock, ratio 1/1,

CRD_CLK active, CRD_DET = Normally Open. All

states are latched for each output variable in programming

mode at the positive going slope of Chip Select [CS] signal.

It is the system designer’s responsibility to set up the options

needed to match the chip with the peripherals. In particular,

when using Normally Close switch, the CRD_DET polarity

must be defined during the first cycles of the initialization.

The CRD_VCC and CLOCK_IN programming options

allows matching the system frequency with the card clock

frequency, and to select 3.0 V or 5.0 V CRD_VCC supply.

The CRD_DET programming option allows the usage of

either Normally Open or Normally Close detection switch.

The Table 2 given hereafter highlights the A0, A1, PGM and

http://onsemi.com

12

NCN6000

Table 2. Card VCC, Card Clock and Card Detection Polarity Truth Table

STATE#

PGM RESET A1

A0

L

I/O

L

H

L

CRD_VCC

CRD_CLK

CRD_DET

STATUS

–

12

1

2

L

H

L

3.0 V

CLOCK_IN 1/1

H

–

12

L

3.0 V

CLOCK_IN 1/2

H

12

3

L

H

L

3.0 V

CLOCK_IN 1/4

H

12

4

L

H

L

3.0 V

CLOCK_IN 1/8

H

12

5

L

H

L

5.0 V

CLOCK_IN 1/1

H

12

6

L

H

L

5.0 V

CLOCK_IN 1/2

H

12

7

L

H

L

5.0 V

CLOCK_IN 1/4

H

12

8

L

H

L

5.0 V

CLOCK_IN 1/8

H

12

9

H

Z

–

START

H

12

10

11

12

13

14

15

16

17

18

19

20

L

H

L

STOP Low

H

12

L

H

L

STOP High

H

12

L

H

L

Reserve

H

11

12

H

L

–

Normally Open

H

11

12

L

H

L

Normally Close

H

12

H

L

H

12

H

Z

Normally Close

H

–

Card Present

DC/DC Status

–

L

H

L

H

Vbat U

vLow

H

CRD_VCC U

vLow

8. The programmed conditions are latched upon Chip Select (CS pin 6) positive going transient.

9. Card clock integrity is guaranteed no spikes whatever be the frequency switching.

10.The STATUS register is not affected when the NCN6000 operates in any of the programming functions.

11. The CRD_VCC and CRD_CLK are not affected when the NCN6000 operates outside their respective decoded logic address.

12.At turn on, the NCN6000 is initialized with CRD_VCC = 3.0 V, CLOCK_IN Ratio = 1/1, CRD_CLK = START, CRD_DET = Normally Open.

13.The High Level present to status 1 to 16 included has been implemented to reduce current consumption but has no other meanings.

DC/DC Converter and Card Detector Status

Vbat undervoltage and CRD_VCC undervoltage situations.

When PGM = H, the STATUS pin returns a High if a card is

detected present, a Low being asserted if there is no card

inserted. In any case, the external card is not automatically

powered up. When the external MPU asserts PWR_ON = H,

together with CS = L, the Vcc supply is provided to the card

and the state of the DC/DC converter, the Vbat and the

CRD_VCC can be polled through the STATUS pin.

The NCN6000 status can be polled when CS = L. Please

consult Figures 3 and 4 for a description of input and output

signals. The status message is described in Table 3.

Table 3. Card and DC/DC Status Output

PGM

HIGH

A1

L

A0

L

STATUS

LOW

Message

No Card

Card Power Supply Timing

L

HIGH

LOW

Card Present

At power up, the CRD_VCC power supply rise time

depends upon the current capability of the DC/DC converter

associated with the external inductor L1 and the reservoir

capacitor connected across CRD_VCC and GROUND. On

the other hand, at turn off, the CRD_VCC fall time depends

upon the external reservoir capacitor and the peak current

absorbed by the internal CMOS transistor built across

CRD_VCC and GROUND. These behaviors are depicted in

Figure 5. Since none of these parameters can have infinite

L

H

DC/DC Converter

Overloaded

HIGH

L

H

L

HIGH

LOW

HIGH

LOW

DC/DC Converter OK

Vbat OK

H

L

Vbat Undervoltage

CRD_VCC OK

H

CRD_VCC Undervoltage

values, the designer must take care of these limits if the t

ON

The STATUS pin provides a feedback related to the

detection of the card, the state of the DC/DC converter, the

or the t

provided by the data sheets does not meet his

OFF

requirement.

http://onsemi.com

13

NCN6000

Figure 6. Turn ON & Turn OFF Typical Curve

as a Function of the Reservoir Capacitor

Figure 5. Card Power Supply Turn ON and OFF Timing

Basic NCN6000 Operating Modes Flow Chart

During the transaction operation, the external MPU takes

care of whatever is necessary to he data on the single

bidirectional I/O line. Leaving aside the DC–DC control and

associated failures, the NCN6000 does not take any further

responsibility in the data transaction.

When the chip operates in the programming mode, the

NCN6000 provide a flexible access to set up the CRD_VCC

voltage, the CRD_CLK and the CRD_DET smart card

signals.

The NCN6000 brings all the functions necessary to handle

data communication between a host computer and the smart

card. The built–in Chip Select pin provides a simple way to

share the same MPU bus with several card interface. On top

of that, the logic control are derived from specific pins,

avoiding the risk of mixing up the operation when the

interface is controlled by a low end microcontroller.

CRD_V = Over loaded

CC

V

= Under Voltage

bat

CS =

ACTIVE MODE

CS = L

PGM = H

PWR_ON = L

IDLE MODE

CS = L

PGM = H

STANDBY MODE

CS = H

PWR_ON = L

ISO STOP SEQUENCE

CS =

PWR_ON = L

CS =

ISO START SEQUENCE

CS =

TRANSACTION MODE

CS = L

PGM = L

PWR_ON = H

PROGRAMMING MODE

CS = L

PGM = L

Figure 7. Operating Modes Flow Chart

http://onsemi.com

14

NCN6000

Standby Mode

Programming Mode

The Standby Mode allows the NCN6000 to detect a card

insertion, keeping the power consumption at a minimum.

The power supply CRD_VCC is not applied to the card, until

the external MPU set PWR_ON = H with CS = L.

The programming mode allows the configuration of the

card power supply, card clock and Card Detection input

logic polarity. These signals (CRD_VCC, CRD_CLK and

CRD_DET) are described in the pin description paragraph

associated with Tables 1 and 2 and Figures 3 and 8.

Standby Mode

Logic Conditions:

Card Output:

Programming Mode

Logic Conditions:

Card Output:

CS = H

CRD_VCC = 0

PWR_ON = H

CRD_CLK = L

CRD_RST = L

CRD_IO = H/L depending upon

the previous I/O pin

logic state

CS = L

PWR_ON = L

CRD_VCC = 0

CRD_CLK = L

CRD_RST = L

CRD_IO = H/L depending upon

the previous I/O pin

logic state

A0

= Z

A1

A0

= 0/1

PGM

I/O

A1

PGM

I/O

= 0/1

= L

= 0/1

RESET

When a card is inserted, the internal logic filters the signal

present pin 11, then asserts the INT pin to Low. The external

MPU shall run whatever is necessary to handle the card.

The INT is cleared (return to High) when a positive going

transition is asserted to either the CS or to the PWR_ON

signal logically combined with Chip Select = Low.

The I/O and RESET pins are not connected to the smart

card and become logic inputs to control the NCN6000

programming sequence. The programmed values are

latched upon transition of CS from Low to High, PGM being

Low during the transition.

PROGRAMMING

NORMAL MODE

PGM

I/O

A0

A1

RESET

CS

2 µs 1 µs 2 µs

Figure 8. Minimum Programming Timings

When a programming mode is validated by a negative

going transient on Chip Select, the mode is latched and PGM

can be released to High. This latch is automatically reset

when CS returns to High.

Active Mode

Logic Conditions:

Card Output:

CS

= L

CRD_VCC = 0

CRD_CLK = L

PWR_ON = L

The logic input signals can be set simultaneously, or bit a

time (using either a STAA or a BSET function), the key point

being the minimum delay between the shorter bit and the

Chip Select pulse. The programmed value is latched into the

NCN6000 register on the CS positive going edge.

A0

A1

PGM

I/O

RESET

= 0

= 1

= Z

CRD_RST = L

CRD_IO = H/L depending upon

the previous I/O pin

logic state

STATUS = 0/1 is Card

Inserted?

Active Mode

The Chip Select pulse [CS] will automatically clear the

previously asserted INT signal.

If a card is present, the MPU shall activate the DC/DC

converter by asserting PWR_ON = H. The NCN6000 will

automatically run a power up sequence when the

In the active mode, the NCN6000 is selected by the

external MPU and the STATUS pin can be polled to get the

status of either the DC/DC converter or the presence of the

card (inserted or not valid). The power is not connected to

the card: CRD_VCC = 0 V.

http://onsemi.com

15

NCN6000

CRD_VCC reaches the undervoltage level (either V

or

In addition, the CRD_CLK signal can be stopped, as

C5H

depicted in Tables 1 and 2, to minimize the current

consumption of the external smart card, leaving CRD_VCC

active.

V

, depending upon the CRD_VCC voltage supply

C3H

programmed). The CRD_IO, CRD_RST and CRD_CLK

pins are validated, according to the ISO7816–3 sequence.

The interface is now in transaction mode and the system is

ready for data exchange through the I/O and RESET lines.

Power Down Operation

The power down mode can be initiated by either the

external MPU (pulling PWR_ON = L) or by one of the

internal error condition (CRD_VCC overload or Vbat Low).

The communication session is terminated immediately,

according to the ISO7816–3 sequence. On the other hand,

the MPU can run the Standby mode by forced CS = H.

When the card is extracted, the interface shall detect the

operation and run the Power Shut Off of the card as

described by the ISO/CEI 7816–3 sequence depicted here

after:

Transaction Mode

During the transaction mode, the NCN6000 maintains

power supply and clock signal to the card. All the signal

levels related with the card are translated as necessary to

cope with the MPU and the card.

The DC/DC converter status and the Vbat state can be

monitored on the STATUS by using the A0 and A1 logic

inputs as depicted Tables 2 and 3.

The time delay between each negative going signal is

500 ns typical.

Transaction Mode

Logic Conditions:

Card Output:

CS = L

PWR_ON = 1

CRD_VCC = Vcc 3.0 or

5.0 V

Card Detection

A0

A1

PGM

I/O

= 1

= 0

= 1

= DATA

TRANSFER

= H/L

CRD_CLK = CLOCK

CRD_RST = H/L

CRD_IO = DATA

TRANSFER

The card detector circuit gives a positive constant low

current to bias the CRD_DET pin, yielding a logic High

when the pin is left open. The internal logic associated with

pin 11 provides an automatic selection of the slope card

detection, depending upon the polarity set by the external

MPU. At start up, the CRD_DET is preset to cope with

Normally Open switch. When a Normally Close switch is

used in the card socket, it is mandatory to program the

NCN6000 chip during the initialization sequence, otherwise

the system will not start if a card was previously inserted.

Table 2 gives the programming code for such a function. The

next lines provide a typical assembler source to handle this

CRD_DET Normally Close polarity:

RESET

STATUS = 0/1 DC/DC status:

Fail/Pass?

To make sure the data is not polluted by power losses, it

is recommended to check the state of CRD_VCC before

launching a new data transaction.

Idle Mode

The idle mode is used when a card is powered up

(CRD_VCC = Vcc), without communication on going.

Smart EQU $20

LDX #$1000

LDAA #$09

; NCN6000 Physical CS Address

; Offset

; I/O = H, A0 = A1 = L, RESET = H

Idle Mode

STAA smart, X ; Set CRD_DET = Normally Closed

Switch

Logic Conditions:

Card Output:

CS = L

PWR_ON = 1

CRD_VCC = Vcc 3.0 or

5.0 V

The CRD_DET polarity can be updated at any time,

during the Program Mode sequence (PGM = L), but,

generally speaking, is useless since the switch does not

change during the usage of the considered module. On the

other hand, the card detection switch shall be connected

across pin 11 and ground, for any polarity selected.

A0

A1

PGM

I/O

RESET

= L

= 1

= Z

= H

CRD_CLK = CLOCK

CRD_RST = H

CRD_IO = Z

STATUS = 0/1 according to the

internal register

results

http://onsemi.com

16

NCN6000

CARD EXTRACTION

DETECTED

CRD_V Voltage

CC

CRD_CLK

CRD_RST

CRD_IO

Digital Filter Delay (50 µs min)

Figure 9. Typical Power Down Sequence in the NCN6000 Interface

The transition presents pin 11, whatever be the polarity, is

extraction, the power down sequence is activated, regardless

of the PWR_ON state, and the INT pin is asserted Low. It is

up to the external MPU to clear this interrupt by forcing a

chip select pulse as depicted in Figure 4.

The 75 µs delay represents the digital filter built into the

NCN6000 chip. Any pulse shorter than this delay does not

generate an interrupt.

filtered out by the internal digital filter circuit, avoiding false

interrupt. In addition to the typical internal 50 µs timing, the

MPU shall provide an additional delay to cope with the

mechanical stabilization of the card interface (typically

3 ms), prior to valid the CRD_VCC supply.

When a card is inserted, the detector circuit asserts INT =

Low as depicted before. When the NCN6000 detects a card

Digital Filter Delay

INTERRUPT

Chip Select Acknowledge or Clear Interrupt

Figure 10. Card Insertion Detection and Interrupt Signals

The Chip Select pulse is generated by the external

microcontroller, the minimum pulse width being 2.0 µs to

make sure the card is detected.

The oscillogram here above depicts the behavior for a

Normally Open switch.

When the card is extracted, the CRD_DET signal

generates an interrupt, assuming the positive pulse width is

longer than the digital filter. The oscillogram here above

depicts the behavior for a Normally Open switch.

http://onsemi.com

17

NCN6000

CRD_DET Input Voltage (card extracted)

Digital Filter Delay

INTERRUPT

Chip Select Acknowledge or Clear Interrupt

Figure 11. Card Extraction Detection and Interrupt Signals

CRD_DET Input Voltage (card inserted)

INTERRUPT

Chip Select

Figure 12. Interrupt Acknowledgement During a Card Insertion Detection Sequence

The interrupt signal, provided in pin 9, is cleared by a

In the event of a power up request coming from the

external MPU (PWR_ON = H, CS = L), the power manager

starts the DC/DC converter.

When the CRD_VCC voltage reaches the programmed

value (3.0 V or 5.0 V), the circuit activates the card signals

according to the following sequence:

positive going Chip Select signal as depicted by the

oscillogram here above. The CS pulse width is irrelevant, as

long as it is larger than 2.0 µs.

Power Management

CRD_VCC→CRD_IO→CRD_CLK→CRD_RST

The purpose of the power management is to activate the

circuit functions needed to run a given mode of operation,

yielding a minimum current consumption on the Vbat

supply. In the Standby mode (PWR_ON = L), the power

management provides energy to the card detection circuit

only. All the card interface pins are forced to ground

potential.

The logic level of the data lines are asserted High or Low,

depending upon the state forced by the external MPU, when

the start up sequence is completed. Under no situation the

NCN6000 shall launch a smart card ATR sequence.

http://onsemi.com

18

NCN6000

At the end of the transaction, asserted by the MPU

(PWR_ON = L, CS = L), or under a card extraction, the

ISO7816–3 power down sequence takes place:

When CS = L, the bidirectional I/O line (pin 8 and 15) is

forced into the High impedance mode to avoid signal

collision with any data coming from the external MPU.

CRD_RST→CRD_CLK→CRD_IO→CRD_VCC

CS

PWR_ON

CRD_V

CC

2 ms

250 µs

CRD _V Rise Time

CC

CRD_V No Change

CC

CRD_V Power Down Fall Time

CC

CRD_V No Change

CC

Figure 13. Card Power Supply Control

DC/DC Converter Operation

an automatic system to accommodate the mode of operation

whatever be the Vbat and CRD_VCC voltages. Comparator

U3/Figure 14 tracks the two voltages and set up the

operating mode accordingly.

The built–in DC/DC converter is based on a modified

boost structure to cover the full battery and card operating

voltage range. The built–in battery voltage monitor provides

V

bat

V

bat

20

19

+

-

Current Sense

U1

R1 1R

V

bat

L

out_H

–

V /V Comparator

bat CC

U3

GND

+

L2

22 µH

GND

L

out_L

PWR_ON

MOS Drive

18

15

Substrat Bias

3 V/ 5 V

CRD_V

CC

+

Q2

Overload

Gate Drive

Q1

C?

V

CC_OK

GND

Gate Drive

V

bat

V

ref

CAPACITOR: Electrolytic

Tantalum

Voltage Regulation

–

U2

Q3

+

Ceramic

GND

V

ref

_3/5 V

GND

PWR_GND

17

V

out

_3_5

GND

Figure 14. Basic DC/DC Structure

http://onsemi.com

19

NCN6000

When the input voltage Vbat is lower than the

typically 22 µH, stores the energy to drive the +5.0 V card

supply from a 2.7 V to 6.0 V voltage range battery. The

oscillogram Figure 15 depicts the DC/DC behavior under

these two modes of operation.

programmed CRD_VCC, the system operates under the

boost mode, providing the voltage regulation and current

limit to the smart card. In this mode, the external inductor,

POWER_ON

Ibat

I

L

CRD_VCC

Step Down Mode

CRD_VCC 5 V Step Up Mode

Figure 15. DC/DC Operating Modes

When the input voltage Vbat is higher than the

programmed CRD_VCC, the system operates under a step

down mode, yielding the voltage regulation and current

limit identical to the boost mode. In this case, the built–in

structure turns Off Q1 and inverts the Q2 substrate bias to

control the current flowing to the load.These operations are

fully automatic and transparent for the end user.

The High and Low limits of the current flowing into the

external inductor L1 are sensed by the operational amplifier

U1 associated with the internal shunt R1. Since this shunt

resistor is located on the hot side of the inductor, the device

reads both the charge and discharge of the inductor,

providing a clean operation of the converter.

The standard electrolytic capacitors have the low cost

advantage for a relative high micro farad value, but have

poor tolerance, high leakage current and high ESR.

The tantalum type brings much lower leakage current

together with high capacity value per volume, but cost can

be an issue and ESR is rarely better than 300 mΩ.

The new ceramic type have a very low leakage together

with ESR in the 50 mΩ range, but value above 10 µF are

relatively rare. Moreover, depending upon the low cost

ceramic material used to build these capacitors , the thermal

coefficient can be very bad, as depicted in Figure 15. The

X7R type are highly recommended when low voltage ripple

is mandatory.

In order to optimize the DC/DC power conversion

efficiency, it is recommended to use external inductor with

R < = 2.0 Ω.

Based on the experiments carried out during the NCN6000

characterization, the best comprise, at time of printing this

document, is to use two 6.8 µF/10 V/ceramic/X7R capacitor

in parallel to achieve the CRD_VCC filtering. The ESR will

not extend 50 mΩ over the temperature range and the

combination of standard parts provide an acceptable –20% to

+20% tolerance, together with a low cost. Obviously, the

capacitor must be SMD type to achieve the extremely low

ESR and ESL necessary for this application.

The output capacitor C1 stores the energy coming from the

converter and smooth the CRD_VCC voltage applied to the

external card. At this point, cares must be observed, beside the

micro farad value, to select the right type of capacitor.

According to the capacitor’s manufacturers, the internal ESR

can range from a low 10 mΩ to more than 1.0 Ω, thus yielding

high losses during the DC/DC operation, depending upon the

technology used to build the capacitor.

Table 4. Ceramic/Electrolytic Capacitors Comparison

Manufacturers

MURATA

Type/Series

Format

0805

Max Value

10 µF/6.3 V

Tolerance

Typ. Z @ 500 kHz

30 mW

CERAMIC/GRM225

Tantalum/594C/593C

Electrolytic/94SV

+80%/–20%

–20%/+20%

VISHAY

10 µF/16 V

10 µF/10 V

450 mW

VISHAY

400 mW

http://onsemi.com

20

NCN6000

Clock Divider

The logic input pins A0, A1, PGM, I/O and RESET fulfill

the programming functions when both PGM and CS are

Low. The clock input stage (CLOCK_IN) can handle a

40 MHz frequency maximum, the divider being capable to

provide a 1:8 ratio. Of course, the ratio must be defined by

the engineer to cope with the Smart Card considered in a

given application and, in any case, the output clock

[CRD_CLK] shall be limited to 20 MHz maximum. In order

to minimize the dI/dt and dV/dV developed in the

CRD_CLK line, the peak current as been internally limited

to 30 mA peak (typical @ CRD_VCC = 5.0 V), hence limited

the rise and fall time to 10 ns typical. Consequently, the

NCN6000 fulfills the ISO7816 specification up to 10 MHz

maximum, but can be used up to 20 MHz when the final

application operates in a limited ambient temperature range.

The main purpose of the built–in clock generator is

threefold:

1. Adapts the voltage level shifter to cope with the

different voltages that might exist between the MPU

and the Smart Card.

2. Provides a frequency division to adapt the Smart

Card operating frequency from the external clock

source.

3. Controls the clock state according to the smart card

specification.

In addition, the NCN6000 adjusts the signal coming from

the microprocessor to get the Duty Cycle window as defined

by the ISO7816–3 specification.

CLOCK_IN

1

3

CS

3

2

CRD_V

CC

1

2

RESET

PGM

I/O

Clock & V

Programming

Block

Level Shifter

& Control

CC

CRD_CLK

A0

A1

+3.0 V

+5.0 V

Figure 16. Simplified Frequency Divider and Programming Functions

In order to avoid any duty cycle out of the frequency smart

card ISO7816–3 specification, the divider is synchronized

by the last flip flop, thus yielding a constant 50% duty cycle,

whatever be the divider ratio. Consequently, the output

CRD_CLK frequency division can be delayed by eight

CLOCK_IN pulses and the microcontroller software must

take this delay into account prior to launch a new data

transaction.

http://onsemi.com

21

NCN6000

CLOCK

CRD CLK

PGM

CS

The example given by the oscillogram here above

highlights the delay coming from the internal clock duty

cycle resynchronization. In this case, the clock is internally

divided by 2 prior to be applied to the CRD_CLK pin. Since

the clock signal is asynchronous, it is up to the programmer

to make sure the next card transaction is not activated before

the CRD_CLK signal has been updated. Generally

speaking, such a delay can be derived from the maximum

clock frequency provided to the interface, keeping in mind

the maximum delay is eight incoming clock pulses.

CLOCK

CRD CLK

PGM

CS

Figure 17. Clock Programming Examples

The clock can be reprogrammed without halting the rest

of the circuit, whatever be the new clock divider ratio.

CRD CLK

CLOCK

PGM

RESET

A0_

A1_

IO

CS

Figure 18. Command Stop Clock HIGH

The CRD_CLK signal is halted in the High logic state,

following the Chip Select positive going transition. Logic

Input conditions:

PGM = Low

RESET = Low

A0 = Low

A1 = Low

CS = Low, pulsed

I/O

= Low

http://onsemi.com

22

NCN6000

CRD CLK

CLOCK

PGM

RESET

A0_

A1_

IO

CS

Figure 19. Command Stop Clock LOW

The CRD_CLK signal is halted in the Low logic state,

following the Chip Select positive going transition. Logic

Input conditions:

previous halted state is irrelevant and the clock signal is

synchronized with the internal clock divider to avoid non

CRD_CLK 50% duty cycle.

PGM = Low

RESET = Low

A0 = Low

A1 = Low

PGM = Low

RESET = High

A0 = Low

A1 = Low

I/O

= High

CS = Low, pulsed

I/O

= Low

CS = Low, pulsed

The CRD_CLK signal is resumed in the normal operation,

following the Chip Select positive going transition. The

CRD CLK

CLOCK

PGM

RESET

A0_

A1_

IO

CS

Figure 20. Command Resume Clock Normal Operation

http://onsemi.com

23

NCN6000

CRD_CLK

C3 Rise

CRD_CLK

C3 Fall

8.255 ns

Cp = 30 pF

7.900 ns

Cp = 30 pF

Figure 21. Card Clock Rise & Fall Time

Since the CRD_CLK signal can generate very fast

transient (i.e. tr = 2.5 ns @ Cp = 10 pF), adapting the design

to cope with the EMV noise specification might be

necessary at final check out. Using an external RC network

is a way to reduce the dv/dt, hence the EMI noise.

In order to avoid uncontrolled command applied to the

smart card, the NCN6000 internal logic circuit, together

with the Vbat monitoring, clamps the card outputs until the

CRD_VCC voltage reaches the minimum value. During the

CRD_VCC slope, all the card outputs are kept Low and no

spikes can be write to the smart card. The oscillograms give

the worst case operation when the stray capacitance is 15 pF.

Since both tr and tf increase when the stray capacitance

increases, the uncontrolled noise reduce as well. The

oscillogram on the right hand side is a magnification of the

curves given on the opposite side.

CRD_V

5.0 V

CC

5.0 V

CRD_V

CC

CRD_RST

CRD_CLK

Cp = 15 pF

CRD_CLK

Cp = 15 pF

CRD_IO

Figure 22. Smart Card Signal Sequence at Power On

http://onsemi.com

24

NCN6000

Bidirectional Level Shifter

When the CS signal goes High, or if the MPU is running

any of the programming functions, the built–in register

holds the previous state presents on the input I/O pin. This

mechanism is useful to force the CRD_IO card pin in either

a High or a Low pre–defined logic state. It is the

responsibility of the programmer to set up the I/O line

according to the system’s activity.

The NCN6000 carries out the voltage difference between

the MPU and the Smart Card I/O signals. When the start

sequence is completed, and if no failures have been detected,

the device becomes essentially transparent for the data

transferred on the I/O line. To fulfill the ISO7816–3

specification, both sides of the I/O line have built–in pulsed

circuitry to accelerate the signal rise transient. The I/O line

is connected on both side of the interface by a NMOS switch

which provide the level shifter and, thanks to its relative high

internal impedance, protects the Smart Card in the event of

data collision. Such a situation could occurs if either the

MPU of the smart card forces a signal in the opposite logic

level direction.

Input Schmitt Triggers

All the Logic Input pins have built–in Schmitt trigger

circuits to prevent the NCN6000 against uncontrolled

operation. The typical dynamic characteristics of the related

pins are depicted in Figure 10.

The output signal is guaranteed to go High when the input

voltage is above 0.70*Vbat, and will go Low when the input

voltage is below 0.30*Vbat.

V

bat

CRD_V

CC

Output

Q1

Q2

V

bat

20 k

I/O

20 k

200 ns

ON

CRD_IO

OFF

Q4

Q3

Input

V

bat

CARD ENABLE

Seq 1

LOGIC

GND

Figure 24. Typical Schmitt Trigger Characteristic

Figure 23. Basic Internal I/O Level Shifter

http://onsemi.com

25

NCN6000

Interrupt Function

The NCN6000 flags the external microprocessor by pulling down the INT signal provided in pin 9. This signal is activated

by one of the here below referenced operations.

Table 5. Interrupt Functions

Pin Related

Clear Function

STATUS Pin 5

High = Card Presents

Card Insertion and

Extraction

11

Positive Going Chip Select, or logical

combination of Chip Select Low and

PWR_ON Positive Going

Low = No Card Inserted

DC/DC Converter

Overloaded

15

Positive Going Chip Select, or logical

combination of Chip Select Low and

PWR_ON Positive Going

High = DC/DC Operates Normally

Low = Output CRD_VCC Overloaded

Security Features

limited to 15 mA. The CRD_VCC pin has the same ESD

protection, but can source up to 55 mA continuously, the

absolute maximum current being 85 mA.

In order to protect both the interface and the external smart

card, the NCN6000 provides security features to prevent

catastrophic failures as depicted here after.

Pin Current Limitation: In the case of a short circuit to

ground, the current forced by the device is limited to 15 mA

for any pins, except CRD_CLK pin. No feedback is

provided to the external MPU.

DC/DC Operation: The internal circuit continuously

senses the CRD_VCC voltage and, in the case of either over

or undervoltage situation, update the STATUS register

accordingly. This register can be read out by the MPU.

Battery Voltage: Both the Over and Undervoltage are

detected by the NCN6000, a POWER_DOWN sequence

and the STATUS register being updated accordingly. The

external MPU can read the STATUS pin to take whatever is

appropriate to cope with the situation.

Parallel Operation

When two or more NCN6000 operate in parallel on a

common digital bus, the Chip Select pin allows the selection

of one chip from the bank of the paralleled devices. Of

course, the external MPU shall provide one unique CS line

for each of the NCN6000 considered interfaces. When a

given interface is selected by CS = L, all the logic inputs

becomes active, the chip can be programmed or/and the

external card can be accessed. When CS = H, all the input

logic pins are in the high impedance state, thus leaving the

bus available for other purpose. On the other hand, when

CS = H, the CRD_IO and CRD_RST hold the previous I/O

and RESET logic state, the CRD_CLK being either active

or stopped, according to the programmed state forced by the

MPU.

ESD Protection

The NCN6000 includes silicon devices to protect the pins

against the ESD spikes voltages. To cope with the different

ESD voltages developed across these pins, the built–in

structures have been designed to handle either 2.0 kV, when

related to the microcontroller side, or 4.0 kV when

connected with the external contacts. Practically, the

CRD_RST, CRD_CLK, VRD_IO and CRD_DET pins can

sustain 4.0 kV, the maximum short circuit current being

Printed Circuit Board Layout

Since the NCN6000 carries high speed currents together

with high frequency clock, the printed circuit board must be

carefully designed to avoid the risk of uncontrolled

operation of the interface.

A typical single–sided PCB layout is provided in

Figure 25 highlighting the ground technique.

http://onsemi.com

26

NCN6000

2335 mis (60 mm)

SMARTCARD ISO CONTACTS

MPU

C4

CLK

C8

I/O

RST

V

PP

GND

GROUND

Figure 25. Typical Single Sided Printed Circuit Board Layout

The card socket uses a low cost ISO only version, all the

parts being located on the Component side. Connector J3

makes reference to the microcontroller used by the final

application. Of course, connector is not necessary and

standard copper tracks might be used to connect the MPU to

the NCN6000 interface chip.

http://onsemi.com

27

NCN6000

C11

C12

17

18

17

18

Swa

Swb

Swa

Swb

6.8 µF/10 V

8

6

7

8

6

7

8

1

2

3

4

1

2

3

4

C9

C10

GND

RST VPP

GND

RST VPP

V

CC

22 µF/10 V

CLK

C4

CLK

C4

I/O

C8

I/O

C8

1

2

3

4

11

10

9

14

7

3–>2

S2

6

7

8

9

1

3

1

8

2–>3

S1

12

13

3

5

Y1

POWER

SUPPLY

8 MHz

1

2

1

2

Figure 27.

http://onsemi.com

29

NCN6000

PACKAGE DIMENSIONS

TSSOP–20

TBD

CASE 948E–02

ISSUE A

20X K REF

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

M

S

V

0.10 (0.004)

T

U

S

U

0.15 (0.006) T

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

K

K1

20

11

^2XL/2

J J1

B

L

–U–

PIN 1

IDENT

SECTION N–N

1

10

0.25 (0.010)

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

N

S

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

0.15 (0.006) T

U

M

A

–V–

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.260

0.177

0.047

0.006

0.030

A

B

6.40

4.30

---

6.60 0.252

4.50 0.169

N

C

1.20

---

D

0.05

0.50

0.15 0.002

0.75 0.020

F

G

H

0.65 BSC

0.026 BSC

DETAIL E

0.27

0.09

0.19

0.37

0.011

0.015

0.008

0.006

0.012

0.010

J

0.20 0.004

0.16 0.004

0.30 0.007

0.25 0.007

–W–

J1

K

C

K1

L

6.40 BSC

0.252 BSC

0

G

D

M

0

8

_

H

DETAIL E

0.100 (0.004)

–T– ^SEATING

PLANE

http://onsemi.com

30

NCN6000

Notes

http://onsemi.com

31

NCN6000

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

Toll–Free from Mexico: Dial 01–800–288–2872 for Access –

then Dial 866–297–9322

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

001–800–4422–3781

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)

Email: ONlit–german@hibbertco.com

French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET)

Email: ONlit–french@hibbertco.com

Email: ONlit–asia@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2700

Email: r14525@onsemi.com

English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT)

Email: ONlit@hibbertco.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, UK, Ireland

NCN6000/D

http://onsemi.com

32


型号：	NCN6000/D
厂家：	ETC
描述：	Compact Smart Card Interface IC 小巧的智能卡接口IC\n
文件：	总32页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NCN6000/D [ETC]

相关型号：

NCN6000DTB

NCN6000DTBG

NCN6000DTBR2

NCN6000DTBR2G

NCN6001

NCN6001/D

NCN6001DTBR2

NCN6001DTBR2G

NCN6001MUR2G

NCN6001MUTWG

NCN6001_06

NCN6001_0610