NCP802/D [ETC]
Highly Integrated Lithium Battery Protection Circuit for One Cell Battery Packs ; 高度集成的锂电池保护电路一节电池组\n
| 型号： | NCP802/D |
| 厂家： | 
ETC |
| 描述： | Highly Integrated Lithium Battery Protection Circuit for One Cell Battery Packs
|
| 文件： | 总20页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP802
Highly Integrated Lithium
Battery Protection Circuit
for One Cell Battery Packs
The NCP802 resides in a lithium battery pack where the battery cell
continuously powers it. This circuit senses cell voltage, charge
current, and discharge current, and correspondingly controls the state
of two, N−channel MOSFET switches. These switches reside in series
with the negative terminal of the cell and the negative terminal of the
battery pack. During a fault condition, the NCP802 open circuits the
pack by turning off one of these MOSFET switches, which
disconnects the current path. Internal delay circuitry minimizes
external component count.
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MARKING
DIAGRAMS
SOT23−6
SUFFIX
6
KNxx
CASE 1262
1
Features
• Highly Accurate Overvoltage Detector
"25 mV at Room Temperature
"30 mV from −5 to 55°C
KN
xx
SON−6
SAN SUFFIX
CASE 494
6
• Fault Detection Thresholds
Overvoltage Threshold: SN1/SAN1=4.35 V, SAN5=4.275 V
Undervoltage Threshold: SN1/SAN1=2.4 V, SAN5=2.3 V
Discharge Current Threshold: SN1/SAN1=0.2 V, SAN5=0.1 V
Charge Current Threshold: 0.1 V
1
KN = Specific Device Code
xx = Date Code
• Internal Output Delays
PIN CONNECTIONS
Overvoltage Output Delay: SN1/SAN1=250 ms, SAN5=1 ms
Undervoltage Output Delay: 20 ms
DO
P−
1
2
6
5
Gnd
Discharge Current Output Delay: SN1/SAN1=12 ms, SAN5=6 ms
Charge Current Output Delay: SN1/SAN1=16 ms, SAN5=8 ms
• Absolute Maximum Rating of 28 V for the Charger Input
V
cell
• Low Quiescent Current
CO
3
4
DS
Normal Operating Current: 3.0 mA
Standby Current when Cells are Discharged: 0.1 mA
SOT23−6
(Top View)
• Zero Volt Charging
• Available in a Low Profile Surface Mount Package
• Pb−Free Package May be Available.* The G−Suffix Denotes a
Pb−Free Lead Finish
DO
1
6
5
4
P−
V
cell
2
3
CO
DS
Gnd
SON−6
(Top View)
V
cell
ORDERING INFORMATION
NCP802
†
Device
Package
Shipping
Gnd
DO
CO
P−
NCP802SN1T1
NCP802SAN1T1
SOT23−6 3000 Tape & Reel
SON−6
3000 Tape & Reel
3000 Tape & Reel
NCP802SAN1T1G SON−6
(Pb−Free)
NCP802SAN5T1
SON−6
3000 Tape & Reel
Figure 1. Typical One Cell Lithium Ion Battery Pack
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details,
please download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
January, 2004 − Rev. 8
NCP802/D
NCP802
V
cell
DS
5
4
Oscillator
Counter
Logic
Circuit
Level
Shift
VD1
VD2
Short
Detector
Delay
VD4
Logic
Circuit
VD3
6
1
3
2
Gnd
DO
CO
P−
Figure 2. Detailed Block Diagram
PIN FUNCTION DESCRIPTION
Pin #
Pin #
SOT23−6
SON−6
Symbol
Description
1
2
3
1
6
5
DO
This output connects to the gate of the discharge MOSFET allowing it to enable or disable
battery pack discharging.
P−
This is the charger negative input pin. It connects to the excess current detectors and serves as
the common node for the CO pin during turn−off.
CO
DS
This output connects to the gate of the charge MOSFET switch allowing it to enable or disable
battery pack charging.
4
5
4
2
This is the delay time reduction pin.
V
cell
This input connects to the positive terminal of the cell for voltage monitoring and provides
operating bias for the integrated circuit.
6
3
Gnd
This is the ground pin of the IC.
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2
NCP802
EXCESS
CHARGE
CURRENT CONNECT LOAD
DISCONNECT
CHARGER +
CONNECT
CHARGER
CONNECT
LOAD
CONNECT
CHARGER
CONNECT
LOAD
V
DET1
VCELL
t
V
DD
V
V
DET3
−P
Gnd
DET4
t
t
t
t
DET4
DET1
DET1
V
DD
CO
t
t
t
REL4
REL1
REL1
P−
t
CHARGE
CURRENT
CHARGE/
DISCHARGE
CURRENT
0
t
DISCHARGE
CURRENT
Figure 3. Overvoltage/Excess Charge Current Timing Chart
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3
NCP802
EXCESS
DISCHARGE
CURRENT
CONNECT
CHARGER
CONNECT
LOAD
CONNECT
LOAD
CONNECT
CHARGER
SHORT
OPEN
OPEN
VCELL
V
DET2
t
V
DD
V
short
V
−P
DET3
Gnd
DET4
V
t
t
short
t
t
t
DET3
DET2
DET2
V
DD
t
t
t
t
REL3
REL3
REL2
REL2
Gnd
DO
t
CHARGE
CURRENT
CHARGE/
DISCHARGE
CURRENT
0
t
DISCHARGE
CURRENT
Figure 4. Undervoltage/Excess Discharge Current Timing Chart
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4
NCP802
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Supply Voltage (Pin 5 to Pin 6)
V
DD
−0.3 to 12
V
Input Voltage
P− Pin Voltage (Pin 5 to Pin 2)
DS Pin Voltage (Pin 4 to Pin 6)
V
V
V
+ 0.3 to V − 28
−0.3 to 12
V
V
P−
DD
DD
V
DS
Output Voltage
CO Pin Voltage (Pin 3 to Pin 2)
DO Pin Voltage (Pin 1 to Pin 6)
V
V
+ 0.3 to V − 28
V
V
CO
DD
DD
−0.3 to 12
DO
Power Dissipation
P
150
mW
°C
D
Operating Junction Temperature
Storage Temperature
T
−40 to 85
−55 to 125
J
T
stg
°C
ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model (HBM)
Machine Model (MM)
(C = 100 pF, R = 1.5 kW)
(C = 200 pF, R = 0 W)
≤1 kV
≤150 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Latch−up Current Maximum Rating per JEDEC standard JESD78
Level 1
≤150 mA
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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5
NCP802
ELECTRICAL CHARACTERISTICS
(T = 25°C, for min/max values T is the operating junction temperature that applies, unless otherwise noted.)
A
A
NCP802SN1/SAN1T1
NCP802SAN5T1
Min
Typ
Max
Min
Typ
Max
Characteristic
VOLTAGE SENSING
Cell Charging Cutoff (Pin 5 to Pin 6)
Symbol
Unit Note 2
V
DET1
Overvoltage Threshold, V Increasing
DD
(R1 = 330W)
T = 25°C
T = −5°C to 55°C
A
4.325
4.32
4.35
4.35
4.375
4.38
4.25
4.275
4.30
V
V
A
4.245 4.275 4.305
A
A
Overvoltage Delay Time (V = 3.6 V to 4.4 V)
t
0.175
11
0.250
16
0.325
21
0.7
11
1
1.3
21
s
DD
DET1
Overvoltage Release Time (V = 4.0 V, V = 0 V
t
REL1
16
ms
V
B
DD
P−
to 1.0 V)
Cell Discharging Cutoff (Pin 5 to Pin 6)
V
2.34
2.4
2.46
2.24
2.3
2.36
C
DET2
Undervoltage Threshold, V Decreasing
DD
Undervoltage Time (V = 3.6 V to 2.2 V)
t
14
20
26
14
20
26
ms
ms
C
D
DD
DET2
Undervoltage Release Delay Time (V = 3.0 V,
t
0.7
1.2
1.7
0.7
1.2
1.7
DD
REL2
V
P−
= 3.0 V to 0 V)
CURRENT SENSING
Excess Discharge Current Threshold, V
Increasing
V
0.180
8
0.200
12
0.220
16
0.080 0.100 0.120
V
K
K
K
E
E
E
K
K
K
P−
DET3
Excess Discharge Current Delay Time (V = 3.0
t
4
6
8
ms
ms
V
DD
DET3
V, V = 0 V to 1.0 V)
P−
Excess Discharge Current Release Time (V = 3.0
t
0.7
1.2
1.7
0.7
1.2
1.7
DD
REL3
V, V = 3.0 V to 0 V)
P−
Excess Charge Current Threshold, V
Decreasing
V
DET4
−0.13
11
−0.1
16
−0.07
21
−0.13 −0.1 −0.07
P−
Excess Charge Current Delay Time (V = 3.0 V,
t
5
8
11
ms
ms
V
DD
DET4
V
P−
= 0 V to −1.0 V)
Excess Charge Current Release Time (V = 3.0
t
0.7
1.2
1.7
0.7
1.2
1.7
DD
REL4
V, V − = −1.0 V to 0 V)
P
Short Protection Voltage (V = 3.0 V)
V
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
DD
SHORT
−1.4
−1.1
−0.8
−1.4
−1.1
−0.8
Short Protection Delay Time (V = 3.0 V, V = 0
t
250
400
600
250
400
600
ms
kW
DD
P−
SHORT
V to 3.0 V)
Reset Resistance (V = 3.6 V, V = 1.0 V)
R
SHORT
15
30
45
15
30
45
DD
P−
2. Indicates test circuits shown on pages 15 and 16.
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6
NCP802
ELECTRICAL CHARACTERISTICS
(T = 25°C, for min/max values T is the operating junction temperature that applies, unless otherwise noted.)
A
A
Characteristic
Symbol
Min
Typ
Max
Unit Note 3
OUTPUTS
Charge Gate Drive Output Low (Pin 3 to Pin 2) (V = 4.5 V, I = 50 mA)
V
ol1
−
3.4
−
0.4
3.7
0.2
0.5
−
V
V
V
G
H
I
DD
o
Charge Gate Drive Output High (Pin 5 to Pin 3) (V = 3.9 V, I = −50 mA)
V
oh1
DD
o
Discharge Gate Drive Output Low (Pin 1 to Pin 6)
(V = 2.0 V, I = 50 mA)
V
ol2
0.5
DD
o
Discharge Gate Drive Output High (Pin 5 to Pin 1)
(V = 3.9 V, I = −50 mA)
V
oh2
3.4
3.7
−
V
J
DD
o
DELAY SHORTENING (DS PIN)
DS Pin High Input Voltage
V
V
−0.5
−
−
V
DD
+0.3
V
V
F
F
F
IH
DD
DS Pin Middle Input Voltage (V = 3.6 to 4.4 V)
V
IM
1.05
V
DD
−1.1
DD
DS Pin Pull−down Resistance (V = 3.6 V)
RDS
0.5
1.3
2.5
MW
DD
TOTAL DEVICE
Supply Current
I
L
cell
Operating (V = 3.9 V, V = 0 V)
−
−
3.0
−
6.0
0.1
µA
µA
DD
P−
Standby (V = 2.0 V)
DD
Operating Voltage
V
1.5
−
−
−
5.0
1.5
V
V
−
DD
Minimum Operating Cell Voltage for Zero Volt Charging
V
M
ST
(Pin 5 to Pin 2) (V − Gnd = 0 V)
DD
3. Indicates test circuits shown on pages 15 and 16.
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7
NCP802
4.37
4.36
4.35
4.34
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
4.33
4.32
4.31
4.30
−50
0
50
100
−50
0
50
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 5. Overvoltage Threshold vs.
Temperature
Figure 6. Overvoltage Delay Time vs.
Temperature
2.43
2.42
2.41
2.40
30
25
20
15
10
5
2.39
2.38
2.37
2.36
0
−50
0
50
100
−60 −40 −20
0
20
40
60
80
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Overvoltage Release Time vs.
Temperature
Figure 8. Undervoltage Threshold vs.
Temperature
1.8
1.6
1.4
1.2
1
35
30
25
20
0.8
15
10
5
0.6
0.4
0.2
0
−50
0
0
50
100
−60 −40
−20
0
20
40
60
80
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 9. Undervoltage Delay Time vs.
Temperature
Figure 10. Undervoltage Release Time vs.
Temperature
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8
NCP802
0.210
0.205
18
16
14
12
10
0.200
0.195
0.190
8
6
4
2
0
−60 −40
−20
0
20
40
60
80
100
−60 −40
−20
0
20
40
60
80
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 11. Excess Discharge Current
Threshold vs. Temperature
Figure 12. Excess Discharge Current Delay
Time vs. Temperature
50
1.8
1.6
1.4
40
30
20
V
DD
= 3.6 V
1.2
1
0.8
0.6
0.4
0.2
0
10
0
−60 −40
−20
0
20
40
60
80
100
−60 −40
−20
0
20
40
60
80
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 13. Excess Discharge Current Release
Time vs. Temperature
Figure 14. Reset Resistance vs. Temperature
30
−0.110
−0.105
25
20
15
10
5
−0.100
−0.095
−0.090
0
−50
0
50
100
−60 −40
−20
0
20
40
60
80
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 15. Excess Charge Current Threshold
vs. Temperature
Figure 16. Excess Charge Current Delay Time
vs. Temperature
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9
NCP802
1.8
1.6
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.4
1.2
1
V
DD
= 3.0 V
0.8
0.6
0.4
0.2
0
−60 −40 −20
0
20
40
60
80
100
−50
0
50
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 17. Excess Charge Current Release
Time vs. Temperature
Figure 18. Short Protection Threshold vs.
Temperature
3
700
600
500
400
300
200
100
0
2.5
2
1.5
1
V
DD
= 3.0 V
0.5
0
−50
−50
0
50
100
0
50
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 19. Short Protection Delay Time vs.
Temperature
Figure 20. DS Pin High Input Minimum Voltage
vs. Temperature
2.5
3
2.5
2
1.5
1
V
DD
= 3.6 V
2
1.5
1
V
DD
= 3.6 V to 4.4 V
0.5
0.5
0
−50
0
−50
0
50
100
0
50
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 21. DS Pin Middle Input Minimum
Voltage vs. Temperature
Figure 22. DS Pin Pull−Down Resistance vs.
Temperature
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NCP802
0.5
0.4
0.3
0.2
0.1
0
3.9
3.8
3.7
3.6
3.5
−60 −40 −20
0
20
40
60
80
100
−50
0
50
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 23. CO NCH Driver Output vs.
Temperature
Figure 24. CO PCH Driver Output vs.
Temperature
3.9
0.4
0.3
0.2
0.1
0
3.8
3.7
3.6
3.5
−50
0
50
100
−60 −40 −20
0
20
40
60
80
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 25. DO NCH Driver Output vs.
Temperature
Figure 26. DO PCH Driver Output vs.
Temperature
0.1
6
5
0.08
0.06
0.04
0.02
4
3
2
1
0
−50
0
−50
0
50
100
0
50
100
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 27. Operating Current vs. Temperature
Figure 28. Standby Current vs. Temperature
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NCP802
0.30
0.25
0.20
0.15
0.10
0.05
0.00
18
16
14
12
10
8
6
4
2
0
4.0
4.5
5.0
5.5
6.0
3.0
3.5
4.0
4.5
V
DD
, OPERATING VOLTAGE (V)
V
DD
, OPERATING VOLTAGE (V)
Figure 29. Overvoltage Delay Time vs.
Operating Voltage
Figure 30. Overvoltage Release Time vs.
Operating Voltage
1.4
1.2
1
22
20
18
16
14
12
10
8
0.8
0.6
0.4
0.2
0
6
4
2
0
1.0
1.5
2.0
2.5
2.0
2.5
3.0
, OPERATING VOLTAGE (V)
DD
3.5
4.0
4.5
V
DD
, OPERATING VOLTAGE (V)
V
Figure 31. Undervoltage Delay Time vs.
Operating Voltage
Figure 32. Undervoltage Release Time vs.
Operating Voltage
1.4
1.2
1
14
12
10
8
0.8
0.6
0.4
0.2
0
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
2.0
2.5
3.0
, OPERATING VOLTAGE (V)
DD
3.5
4.0
4.5
V
DD
, OPERATING VOLTAGE (V)
V
Figure 33. Excess Discharge Current Delay
Time vs. Operating Voltage
Figure 34. Excess Discharge Current Release
Time vs. Operating Voltage
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12
NCP802
18
16
1.4
1.2
1
14
12
10
0.8
0.6
0.4
0.2
0
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
2.0
2.5
3.0
3.5
4.0
4.5
V
DD
, OPERATING VOLTAGE (V)
V
DD
, OPERATING VOLTAGE (V)
Figure 35. Excess Charge Current Delay Time
vs. Operating Voltage
Figure 36. Excess Charge Current Release
Time vs. Operating Voltage
2.427
2.426
2.425
2.424
2.423
2.422
2.421
2.420
2.419
2.418
2.417
2.416
700
600
500
400
300
200
100
0
Undervoltage
Release
Threshold
Undervoltage
Threshold
0
100 200 300 400 500 600 700 800 900 1000
2
2.5
3
3.5
4
4.5
V
DD
, OPERATING VOLTAGE (V)
R1 (Ω)
Figure 37. Short Protection Delay Time vs.
Operating Voltage
Figure 38. Undervoltage Thresholds vs. R1
2.5
4.294
4.293
4.292
4.291
4.29
2
1.5
1
V
DD
= 4.25 V
Overvoltage
Threshold
Overvoltage
Release
Threshold
0.5
4.289
4.288
0
0
100 200 300 400 500 600 700 800 900 1000
0
50
100
150
R2 (kΩ)
200
250
300
R1 (Ω)
Figure 39. Overvoltage Thresholds vs. R1
Figure 40. Charger Voltage to Release from
Undervoltage vs. R2
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NCP802
2
1.8
1.6
1.4
1.2
1
V
DD
− GND = 0
0.8
0.6
0.4
0.2
0
−50
0
50
100
T , AMBIENT TEMPERATURE (°C)
A
Figure 41. Minimum Operating Voltage for 0 V
Charging vs. Temperature
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NCP802
A
E
VCELL
P−
VCELL
P−
CO
CO
DO
DO
CO
V
V
GND
GND
B
F
VCELL
P−
VCELL
P−
DS
DO
A
V
GND
GND
G
C
VCELL
VCELL
A
P−
P−
CO
V
V
GND
GND
D
H
A
VCELL
VCELL CO
P−
P−
V
GND
GND
Figure 42. Test Circuits
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NCP802
I
K
VCELL
VCELL
P−
DO
A
P−
DO
A
V
V
GND
GND
J
L
VCELL
A
VCELL DO
A
P−
V
P−
GND
GND
M
VCELL
V
DO
P−
V
CO
GND
Figure 43. Test Circuits
Overvoltage Detection
reset from an overvoltage fault as long as a charger is
connected to the battery. Rather, the excess−discharge
current detector (VD3) signals the IC to reset from an
overvoltage condition by detecting a load while in an
overvoltage condition. When the P− pin voltage becomes
equal to or greater than than the excess discharge−current
detector threshold (VDET3) during an overvoltage fault, the
NCP802 senses the voltage drop across the charge
MOSFET’s body diode induced by the load current. It then
resets from the overvoltage state.
There are internal, fixed delay times for both the detection
and release from an overvoltage condition. If the fault or
reset conditions are shorter than their respective delay times,
the NCP802 ignores that condition and stays in its previous
state.
The overvoltage detector (VD1) monitors the VCELL pin
voltage. When the VCELL voltage crosses the overvoltage
detector threshold (VDET1) from a low value to a value
higher than VDET1, VD1 detects an over−charging
condition. The NCP802 then turns off an external, charge
control, N−channel, MOSFET by driving the CO pin to its
low level. A level shifter, incorporated in a buffer driver for
the CO pin, drives the low level of the CO pin to the P− pin
voltage, which is connected to the source of the charge
control MOSFET by a resistor. The high level of the CO pin
is driven to the VCELL voltage with a CMOS buffer.
To reset the CO pin to its high level, the voltage at the
VCELL pin must decrease to a level lower than VDET1. The
overvoltage detector does not reset after the battery voltage
falls below some hysteresis voltage. The NCP802 will not
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NCP802
Undervoltage Detection
short circuit detector has activated; removing the cause of
that activation turns the discharge MOSFET back on. This
occurs because RSHORT pulls the P− pin, voltage level
down to the GND pin, voltage level. The NCP802 internally
disconnects RSHORT during a normal, fault−free, state. The
NCP802 only connects RSHORT if it has detected an excess
discharge−current or short circuit fault. In other words, VD3
is automatically released from excess discharge−current and
short circuit faults when the user removes the load.
The undervoltage detector (VD2) monitors the VCELL
pin voltage. When the VCELL voltage crosses the
undervoltage threshold (VDET2) from a high value to a
value lower than VDET2, VD2 senses an undervoltage
condition, and an external, discharge control, N−channel
MOSFET turns off by driving the DO pin to its low level.
The low level of DO is set to GND and the high level to
VCELL.
To reset the DO pin to its high level, one must connect a
charger to the battery pack. While the VCELL voltage
remains under VDET2, charge−current can flow through the
parasitic diode of the external discharge control MOSFET.
Once the VCELL voltage rises above VDET2, the NCP802
drives DO high. Connecting a charger to the battery pack
drives the DO level high instantaneously when the VCELL
voltage is higher than VDET2. VD2 has no hysteresis.
After VD2 detects an undervoltage condition, the
NCP802 enters a low supply current, standby mode.
Maximum standby current equals 0.1 mA at VCELL equal
to 2.0 V. An internal pull−up disables all the device functions
and thus drastically lowers quiescent current. When the
charger connects to the battery, it pulls small levels of
current from the P− pin. This overcomes the internal pull−up
and allows the NCP802 to reset.
The output delay time of excess discharge−current
detection is set shorter than the delay time for undervoltage
detection. Therefore, if VCELL voltage drops below
VDET2 during an excess discharge−current or short circuit
fault, the NCP802 detects the current fault first. This
prevents large discharge current faults from activating the
undervoltage detector and putting the NCP802 into standby
mode. Standby mode requires the charger to reset the
NCP802, while excess discharge−current and short circuit
faults only require that the fault be removed.
Excess Charge−Current Detection
When the battery pack is chargeable and discharge is also
possible, VD4 senses the P− pin voltage. For example, if the
user connects the battery to an inappropriate charger, excess
current can flow. Then, the P− voltage drops below the
excess charge−current threshold (VDET4). Next, the output
of CO becomes low. This prevents excess current flow into
the circuit by turning off the external MOSFET.
The output delay of the excess charge−current detector is
internally fixed. If the fault condition is within the delay time
window, the detector will not sense it and the MOSFET will
not change state. VD4 can be released by disconnecting a
charger and applying a load.
There are internal, fixed delay times for both the detection
and release from an undervoltage condition. If the fault or
reset conditions are shorter than their respective delay times,
the NCP802 ignores that condition and stays in its previous
state.
Excess Discharge−Current/Short Circuit Detection
The excess discharge−current detector (VD3) and the
short circuit detector can function when the control
MOSFET’s are on. When the P− pin voltage is below the
short circuit detection voltage (VSHORT) and above the
excess discharge−current threshold (VDET3), VD3
operates. When the P− pin voltage rises higher than
VSHORT, the NCP802 enables the short circuit detector.
When either detector activates, the NCP802 turns off an
external, discharge control, N−channel, MOSFET by
driving the DO pin to its low level.
The output delay time for the excess discharge−current
detector is internally fixed. If the P− pin, voltage level
recovers from a level between VSHORT and VDET3 within
the delay time, the discharge MOSFET stays in its high state.
Output delay time for release from excess discharge−current
detection is typically 1.2 ms. When the short circuit detector
activates, DO transitions to its low state after a delay time of
approximately 400 ms.
Delay Shortening Function
The output delay time of over−charge, over−discharge,
excess discharge−current, excess charge−current, and the
release from those detecting modes can be made shorter than
the pre−set value by forcing the VCELL voltage to the DS
pin. When one forces the specified middle range voltage to
the DS pin, the output delay circuit becomes disabled.
Therefore, under this condition, when over−charge or excess
charge current is detected, output level can be checked
without waiting for the delay.
A 1.3 MW pull−down resistor is connected between DS
pin and GND internally. For normal operation, the DS pin
should be at no connection state.
Zero Battery Voltage Charging
If the charger voltage is equal or higher than the zero−volt
charge, minimum voltage (VST), the NCP802 drives the CO
pin high. Therefore, it allows charging for batteries as low
as zero volts.
There is an integrated pull−down resistor (RSHORT)
connected between the P− and GND pins. After VD3 or the
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17
NCP802
+
R1
330 W
VCELL
DS
C1
0.1 µF
NCP802
P−
GND
DO
CO
R2
1 kW
−
Figure 44. Typical Application Circuit
Technical Notes
R1 and C1 will stabilize a supply voltage to the NCP802. A recommended R1 value is less than 1.0 kW A larger value of R1
leads to higher detection voltages. There may also be voltage detector errors from shoot through current into the NCP802.
R1 and R2 can also help current limit the circuit against reverse charge or a charger with excess charging voltage applied to
the NCP802 battery pack. Smaller R1 and R2 values may cause excessive power consumption over the specified power
dissipation rating. Therefore, the total value of R1 ) R2 should be equal to or more than 1.0 kW. However, if one uses a very
large value of R2, it might not be possible to release from undervoltage by connecting a charger. The recommended R2 value
is equal to or less than 30 kW.
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18
NCP802
PACKAGE DIMENSIONS
SOT23−6
SN SUFFIX
PLASTIC PACKAGE
CASE 1262−01
ISSUE A
E
M
M
C B
0.05
0.20
PIN 1
IDENTIFIER
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION D DOES NOT INCLUDE FLASH OR
PROTRUSIONS. FLASH OR PROTRUSIONS
SHALL NOT EXCEED 0.23 PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
C
1
2
6
5
A
A
5. DIMENSIONS D AND E1 ARE TO BE DETERMINED
AT DATUM PLANE H.
3
4
MILLIMETERS
A1
A
DIM MIN
MAX
1.45
0.15
0.50
0.45
0.20
0.15
3.00
3.00
1.75
E1
A
A1
b
0.90
0.00
0.35
0.35
0.09
0.09
2.80
2.60
1.50
B
A
b1
c
c1
D
b
E
E1
e
0.95
1.90
q
e1
L
0.25
0
0.55
10
q
_
_
H
L
b1
SECTION A−A
SON−6
SAN SUFFIX
PLASTIC PACKAGE
CASE 494−01
ISSUE 0
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
6
5
4
MILLIMETERS
INCHES
MIN
K
DIM MIN
MAX
1.80
2.80
0.90
0.30
1.44
MAX
0.071
0.110
0.035
0.012
0.057
E
B
L
A
B
C
D
E
G
J
1.40
2.40
−−−
0.055
0.094
−−−
0.10
1.24
0.004
0.049
1
2
3
0.50 BSC
0.020 BSC
0.08
0.18
0.003
0.007
K
L
0.30 BSC
0.012 BSC
0.112
0.124
C
2.85
3.15
0.10 (0.004)
J
−T−
SEATING PLANE
D 6 PL
M
0.15 (0.010)
T X Y
G
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19
NCP802
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NCP802/D
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