NLSF302/D [ETC]
Quad 2-Input NOR Gate ; 四2输入或非门\n
| 型号： | NLSF302/D |
| 厂家： | 
ETC |
| 描述： | Quad 2-Input NOR Gate
|
| 文件： | 总6页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLSF302
Quad 2−Input NOR Gate
The NLSF302 is an advanced high speed CMOS 2−input NOR gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
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MARKING
DIAGRAM
16
• High Speed: t = 3.6 ns (Typ) at V = 5 V
PD
CC
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
1
NLSF
302
ALYW
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
QFN−16
MN SUFFIX
CASE 485G
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
(Top View)
• Low Noise: V
• Function Compatible with Other Standard Logic Families
• QFN−16 Package
= 0.8 V (Max)
OLP
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 40 FETs or 10 Equivalent Gates
ORDERING INFORMATION
Device
NLSF302MN
Package
Shipping†
123 Units/Rail
QFN−16, 3x3
NLSF302MNR2 QFN−16, 3x3 3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
October, 2003 − Rev. 1
NLSF302/D
NLSF302
16
A1
B1
15
3
Y1
Y2
Y3
Y4
1
FUNCTION TABLE
4
5
A2
B2
Inputs
Output
A
B
C
Y = A + B
L
L
H
H
L
H
L
H
7
8
A3
B3
9
L
L
L
H
10
12
A4
B4
13
Figure 1. LOGIC DIAGRAM
16
15
14
13
12
11
10
9
B4
B1
NC
Y2
1
NLSF302
MN Package
NC
A4
Y3
2
3
4
(Top View)
A2
8
5
6
7
Figure 2. Pin Assignment (QFN−16)
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2
NLSF302
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
± 20
mA
mA
mA
mA
mW
°C
cuit. For proper operation, V and
in
I
Output Diode Current
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
± 25
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
DC Supply Current, V and GND Pins
± 50
CC
level (e.g., either GND or V ).
P
Power Dissipation in Still Air
Storage Temperature
450
CC
D
Unused outputs must be left open.
T
stg
– 65 to + 150
NOTES: Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under
absolute−maximum−rated conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
V
in
5.5
V
V
DC Output Voltage
Operating Temperature
Input Rise and Fall Time
0
V
V
out
CC
T
−40
+85
°C
ns/V
A
t , t
r
V
CC
= 3.3 V ± 0.3 V
=5.0 V ± 0.5 V
0
0
100
20
f
V
CC
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
V
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0 to 5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High−Level
Output Voltage
V
V
= V or V
IL
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
I
IH
= −50 mA
OH
= V or V
IL
in
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
OL
Maximum Low−Level
Output Voltage
V
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
I
IH
IL
= 50 mA
OL
V
= V or V
IH
in
I
I
IL
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
OL
I
Maximum Input Leak-
age Current
V
= 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
mA
mA
in
in
I
Maximum Quiescent
Supply Current
V
= V or GND
5.5
2.0
20.0
CC
in
CC
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3
NLSF302
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
1.0
Max
Symbol
Parameter
Test Conditions
= 3.3 ± 0.3 V C = 15 pF
Unit
t
,
Maximum Propagation Delay,
Input A or B to Output Y
V
V
5.6
8.1
7.9
11.4
9.5
13.0
ns
PLH
CC
L
t
C = 50 pF
L
1.0
PHL
= 5.0 ± 0.5 V C = 15 pF
3.6
5.1
5.5
7.5
1.0
1.0
6.5
8.5
CC
L
C = 50 pF
L
C
Maximum Input Capacitance
4
10
10
pF
pF
in
Typical @ 25°C, V = 5.0 V
CC
15
C
Power Dissipation Capacitance (Note 1)
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /4 (per gate). C is used to determine the
CC(OPR
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
in
.
D
PD
CC
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
0.3
0.8
− 0.8
3.5
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
− 0.3
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
TEST POINT
OUTPUT
V
CC
A or B
50%
DEVICE
UNDER
TEST
GND
t
t
PHL
PLH
C *
L
50% V
Y
CC
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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4
NLSF302
PACKAGE DIMENSIONS
QFN−16
MN SUFFIX
CASE 485G−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
−X−
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
M
MILLIMETERS
DIM MIN MAX
3.00 BSC
3.00 BSC
0.80
INCHES
MIN MAX
−Y−
A
B
C
D
E
F
0.118 BSC
0.118 BSC
1.00 0.031
0.039
0.011
0.073
0.073
0.23
1.75
1.75
0.28 0.009
1.85 0.069
1.85 0.069
B
G
H
J
0.50 BSC
0.875 0.925
0.20 REF
0.020 BSC
N
0.034
0.036
0.008 REF
K
L
0.00
0.35
0.05 0.000
0.45 0.014
0.002
0.018
0.25 (0.010) T
0.25 (0.010) T
M
N
P
R
1.50 BSC
1.50 BSC
0.875 0.925
0.60 0.80 0.024
0.059 BSC
0.059 BSC
0.034
0.036
0.031
J
R
C
SEATING
PLANE
−T−
0.08 (0.003) T
K
E
H
G
L
5
8
4
9
F
12
1
16
13
P
D NOTE 3
M
0.10 (0.004)
T
X Y
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5
NLSF302
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NLSF302/D
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