NM24W02EN [ETC]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | NM24W02EN |
| 厂家： | 
ETC |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总14页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
March 1999
NM24Wxx
2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface
Serial EEPROM with Full Array Write Protect
General Description
Features
The NM24Wxx devices are 2048/4096/8192/16,384 bits, respec-
tively, of CMOS non-volatile electrically erasable memory. These
devices conform to all specifications in the IIC 2-wire protocol and
are designed to minimize device pin count, and simplify PC board
layout requirements.
■ Hardware Write Protect for entire memory
■ Low Power CMOS
200µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
The entire ememory can be disabled (Write Protected) by con-
nectingtheWPpintoVCC.Thememorythenbecomesunalterable
■ IIC Compatible interface
unless WP is switched to VSS
.
— Provides bidirectional data transfer protocol
■ Sixteen byte page write mode
— Minimizes total write time per byte
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by Fairchild's family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs.
■ Self timed write cycle
— Typical write cycle time of 6ms
■ Endurance: 1,000,000 data changes
■ Data retention greater than 40 years
■ Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
■ Available in three temperature ranges
- Commercial: 0° to +70°C
Fairchild EEPROMs are designed and tested for applications
requiringhighendurance, highreliabilityandlowpowerconsump-
tion.
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
V
CC
V
SS
WP
H.V. GENERATION
TIMING &CONTROL
START CYCLE
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
16/
32/
64/
2
E
PROM
ARRAY
XDEC
SCL
128/
LOAD
INC
A2
A1
A0
WORD
ADDRESS
COUNTER
0/1/2/3
4
16
4
R/W
YDEC
Device Address Bits
8
CK
D
OUT
DATA REGISTER
D
IN
DS500074-1
1
© 1999 Fairchild Semiconductor Corporation
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NM24Wxx Rev. C.2
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Connection Diagrams
Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8)
A0
A1
A2
1
2
3
4
8
7
6
5
V
NC
A1
A2
1
2
3
4
8
7
6
5
V
NC
NC
A2
1
8
7
6
5
V
NC
NC
NC
1
8
7
6
5
V
CC
CC
CC
CC
WP
WP
2
WP
2
WP
NM24W02
NM24W04
NM24W08
NM24W16
SCL
SDA
SCL
SDA
3
SCL
SDA
3
SCL
SDA
V
V
V
4
V
SS
4
SS
SS
SS
DS500074-2
DS500074-3
DS500074-4
DS500074-18
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
A0,A1,A2
VSS
Device Address Inputs
Ground
SDA
SCL
WP
Data I/O
Clock Input
Write Protect
Power Supply
No Connect
VCC
NC
Ordering Information
NM 24
W
XX LZ
E
XX
Letter Description
Package
Temp. Range
N
M8
MT8
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
None
0 to 70°C
E
V
-40 to +85°C
-40°C to +125°C
Voltage Operating Range
Blank
L
4.5V to 5.5V
2.7V to 4.5V
LZ
2.7V to 4.5V and
<1µA Standby Current
Density
02
04
08
16
2K
4K
8K
16K
W
Total Array Write Protect
IIC
Interface
24
NM
Fairchild Non-Volatile
Memory
2
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Product Specifications
Operating Conditions
Ambient Operating Temperature
NM24Wxx
Absolute Maximum Ratings
Ambient Storage Temperature
–65°C to +150°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
All Input or Output Voltages
with Respect to Ground
NM24WxxE
NM24WxxV
6.5V to –0.3V
Lead Temperature
Positive Power Supply
NM24Wxx
(Soldering, 10 seconds)
+300°C
4.5V to 5.5V
2.7V to 4.5V
2.7V to 4.5V
ESD Rating
2000V min.
NM24WxxL
NM24WxxLZ
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Typ
Units
Min
Max
(Note 1)
ICCA
ISB
ILI
Active Power Supply Current
Standby Current
fSCL = 100 kHz
0.2
10
1.0
mA
µA
µA
µA
V
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
50
Input Leakage Current
Output Leakage Current
Input Low Voltage
0.1
0.1
1
1
ILO
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Voltage
VCC x 0.7
V
Output Low Voltage
IOL = 3 mA
V
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Limits
Typ
Units
Min
Max
(Note 1)
ICCA
ISB
Active Power Supply Current
fSCL = 100 kHz
0.2
1.0
mA
Standby Current for L
Standby Current for LZ
VIN = GND or VCC
VIN = GND or VCC
1
0.1
10
1
µA
µA
ILI
ILO
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VOUT = GND to VCC
0.1
0.1
1
1
µA
µA
V
VIL
VIH
VOL
–0.3
VCC x 0.3
VCC + 0.5
0.4
Input High Voltage
VCC x 0.7
V
Output Low Voltage
IOL = 3 mA
V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O
Test
Conditions
VI/O = 0V
Max Units
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
8
6
pF
pF
CIN
VIN = 0V
Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).
Note 2: This parameter is periodically sampled and not 100% tested.
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AC Conditions of Test
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels VCC x 0.5
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 4.5V)
Symbol
Parameter
100 KHz
400 KHz
Units
Min
Max
Min
Max
fSCL
TI
SCL Clock Frequency
100
100
3.5
400
KHz
ns
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
50
tAA
SCL Low to SDA Data Out Valid
0.3
4.7
0.1
1.3
0.9
µs
µs
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
tR
Data in Hold Time
0
0
ns
ns
µs
ns
µs
ns
ms
Data in Setup Time
250
100
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
tF
300
300
tSU:STO
tDH
4.7
0.6
50
300
tWR
(Note 3)
Write Cycle Time - NM24Wxx
- NM24WxxL, NM24WxxLZ
10
15
10
15
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24Wxx bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
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Bus Timing
t
t
R
F
t
HIGH
t
t
LOW
LOW
SCL
t
SU:STO
t
t
t
SU:DAT
SU:STA
HD:DAT
t
HD:STA
SDA
IN
t
BUF
t
t
AA
DH
SDA
OUT
DS500074-5
Background Information (IIC Bus)
DEFINITIONS
As mentioned, the IIC bus allows synchronous bidirectional com-
munication between Transmitter/Receiver using the SCL (clock)
and SDA (Data I/O) lines. All communication must be started with
a valid START condition, concluded with a STOP condition and
acknowledged by the Receiver with an ACKNOWLEDGE condi-
tion.
WORD
PAGE
8 bits of data
16 sequential addresses (one byte
each) that may be programmed
during a 'Page Write' programming
cycle
PAGE BLOCK
2,048 (2K) bits organized into 16
pages of addressable memory. (8
bits) x (16 bytes) x (16 pages) = 2,048
bits
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROMs, etc., a devce type identifier string must
follow the START condition. For EEPROMs, this 4-bit string is
1010 and is the first 4 bits in the slave address.
MASTER
SLAVE
Any IIC device CONTROLLING the
transfer of data (such as a micropro-
cessor)
As shown below, the EEPROMs on the IIC bus may be configured
inanymannerrequired, andfortheStandardIICprotocol, thetotal
memory addressed can not exceed 16K (16,384 bits). EEPROM
memory address programming is controlled by 2 methods:
Device being controlled (EEPROMs
are always considered Slaves)
• Hardware configuring the A0, A1, and A2 pins (Device
Address pins) with pull-up or pull-down to resistors. All
TRANSMITTER
RECEIVER
Device currently SENDING data on
the bus (may be either a Master or
Slave).
unused pins must be grounded (tied to V ).
SS
• Software addressing the required PAGE BLOCK within the
device memory array (as sent in the Slave Address string).
Device currently receiving data on the
bus (Master or Slave)
Addressing an EEPROM memory location involves sending a
command string with the following information:
[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK
ADDRESS]—[BYTE ADDRESS]
Example of 16K of Memory on 2-Wire Bus
V
V
CC
CC
SDA
SCL
V
V
V
V
CC
CC
CC
CC
NM24W02
NM24W02
NM24W04
NM24W08
A0 A1 A2
V
A0 A1 A2
V
A0 A1 A2
V
A0 A1 A2 V
SS
SS
SS
SS
To V
or V
To V
or V
To V
or V
To V
CC
or V
SS
DS500074-6
CC
SS
CC
SS
CC
SS
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.
It is recommended that the total line capacitance be less than 400pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
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Device
Address Pins
Memory Size
Number of
A0
A1
ADR
ADR
NC
A2
Page Blocks
NM24W02
NM24W04
NM24W08
NM24W16
ADR
NC
ADR
ADR
ADR
NC
2048 Bits
4096 Bits
8192 Bits
16,384 Bits
1
2
4
8
NC
NC
NC
ADR is the hardware address (VCC/1 or VSS/0) of the device(s) used.
Clock and Data Conventions
Pin Descriptions
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH are reserved for indicating
start and stop conditions. Refer to Figures 1 and 2.
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Serial Data (SDA)
Start Condition
SDA is a bidirectional pin used to transfer data into and out of the
device. It is an open drain output and may be wire–ORed with any
number of open drain or open collector outputs.
All commands are preceded by the start condition, which is a
HIGHtoLOWtransitionofSDAwhenSCLisHIGH.TheNM24Wxx
continuously monitors the SDA and SCL lines for the start condi-
tion and will not respond to any command until this condition has
been met.
Device Operation Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to V or V
to configure the EEPROM chip address. Table 1 shows the active
CC
SS
Stop Condition
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the NM24Wxx to place the device in the
standby power mode.
pins across the NM24Wxx device family.
TABLE 1.
Device
A0
A1
A2 Effects of Addresses
ACKNOWLEDGE
NM24W02 ADR ADR ADR 23 = 8; 8*x(1x2K)**=16K
Acknowledgeisasoftwareconventionusedtoindicatesuccessful
data transfers. The transmitting device, either master or slave, will
release the bus after transmitting eight bits.
NM24W04
NM24W08
NM24W16
x
x
x
ADR ADR 22 = 4; 4*x(2x2K)**=16K
x
x
ADR 21 = 2; 2*x(4x2K)**=16K
20 = 1; 1*x(8x2K)**=16K
During the ninth clock cycle the receiver will pull the SDA line to
LOW to acknowledge that it received the eight bits of data. Refer
to Figure 3.
x
*
Max # of devices on bus
** Number of page blocks per density
The NM24Wxx device will always respond with an acknowledge
after recognition of a start condition and its slave address. If both
thedeviceandawriteoperationhavebeenselected,theNM24Wxx
will respond with an acknowledge after the receipt of each
subsequent eight bit byte.
WP Write Protection
If tied to VCC, PROGRAM operations onto memory will not be
executed. (Only READ operations are possible.) If tied to VSS
,
normaloperationisenabled(READ/WRITEovertheentirememory
is possible).
In the read mode the NM24Wxx slave will transmit eight bits of
data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
Device Operation
TheNM24Wxxsupportsabidirectionalbusorientedprotocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device that is
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the NM24Wxx will be considered a slave in
all applications.
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Write Cycle Timing
SCL
SDA
8th BIT
WORD n
ACK
t
WR
STOP
START
CONDITION
CONDITION
DS500074-7
Data Validity (Figure 1)
SCL
SDA
DATA
CHANGE
DATA STABLE
DS500074-8
Start and Stop Definition (Figure 2)
SCL
START
STOP
CONDITION
SDA
CONDITION
DS500074-9
Acknowledge Responses from Receiver (Figure 3)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
DS500074-10
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Device Addressing
All Standard IIC protocol EEPROMs use an internal protocol that
defines a PAGE BLOCK size of 2K bits (for Byte addresses 00
through FF). Therefore, address bits A0, A1, or A2 (if designated
'P') are used to access a PAGE BLOCK in conjuction with the Byte
address used to access any individual data byte.
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier (see Figure 4). This
is fixed as 1010 for all EEPROM devices.
Slave Addresses (Figure 4)
Refer to the following table for Slave Address string details:
Device Type
Identifier
Device
Address
Device A0 A1 A2 Page
Blks
Page Block
Addresses
1
0
1
0
0
A2
A1
A0 R/W (LSB)
NM24W02
NM24W04
NM24W08
NM24W16
A
P
P
P
A
A
P
P
A
A
A
P
1 (2K)
2 (4K)
4 (8K)
(None)
0 1
NM24W02
Device Type
Identifier
Device
Address
00 01 10 11
8 (16K) 000 001 010 011 100
101 110 111
1
0
1
A2
A1
A0 R/W (LSB)
Page
Note:
A: Refers to a hardware configured Device Address pin.
P: Refers to an internal PAGE BLOCK memory segment
NM24W04
The last bit of the slave address defines whether a write or read
condition is requested by the master. A '1' indicates that a read
operation is to be executed, and a '0' initiates the write mode.
Block Address
Device Type
Identifier
Device
Address
A simple review: After the NM24Wxx recognizes the start condi-
tion, the devices interfaced to the IIC bus wait for a slave address
to be transmitted over the SDA line. If the transmitted slave
addressmatchesanaddressofoneofthedevices,thedesignated
slave pulls the line LOW with an acknowledge signal and awaits
further transmissions.
1
0
1
0
A2
A1
A0 R/W (LSB)
NM24W08
Page
Block Address
Device Type
Identifier
1
0
1
0
A2
A1
A0 R/W (LSB)
NM24W16
Page
Block Address
DS500074-11
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If the master should transmit more than sixteen words prior to
generating the stop condition, the address counter will 'roll over'
andthepreviouslywrittendatawillbeoverwritten. Aswiththebyte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address, acknowl-
edge, and data transfer sequence.
Write Operations
Byte Write
For a write operation a second address field is required which is
awordaddressthatiscomprisedofeightbitsandprovidesaccess
to any one of the 256 words in the selected page of memory. Upon
receipt of the word address the NM24Wxx responds with an
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
transferbygeneratingastopcondition,atwhichtimetheNM24Wxx
begins the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the NM24Wxx inputs are
disabled, and the device will not respond to any requests from the
master. Refer to Figure 5 for the address, acknowledge and data
transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host’s
write operation the NM24Wxx initiates the internal write cycle.
ACKpollingcanbeinitiatedimmediately. Thisinvolvesissuingthe
start condition followed by the slave address for a write operation.
If the NM24Wxx is still busy with the write operation no ACK will
bereturned.IftheNM24Wxxhascompletedthewriteoperationan
ACK will be returned and the host can then proceed with the next
read or write operation.
Page Write
Write Protection
The NM24Wxx is capable of a sixteen byte page write operation.
It is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data word is
transferred,themastercantransmituptofifteenmorewords.After
the receipt of each word, the NM24Wxx will respond with an
acknowledge.
Programming of the memory will not take place if the WP pin of the
NM24Wxx is connected to VCC. The NM24Wxx will accept slave
and word addresses; but if the memory accessed is write pro-
tected by the WP pin, the NM24Wxx will not generate an acknowl-
edge after the first byte of data has been received, and thus the
program cycle will not be started when the stop condition is
asserted.
After the receipt of each word, the internal address counter
incrementstothenextaddressandthenextSDAdataisaccepted.
Byte Write (Figure 5)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS
Bus Activity:
Master
DATA
SDA Line
A
C
K
A
C
K
A
C
K
Bus Activity:
NM24Wxx
DS500074-12
Page Write (Figure 6)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
BYTE ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:
NM24Wxx
DS500074-13
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Read Operations
Read operations are initiated in the same manner as write
operations,withtheexceptionthattheR/Wbitoftheslaveaddress
is set to a one. There are three basic read operations: current
address read, random read, and sequential read.
diately reissues the start condition and the slave address with the
R/W bit set to one. This will be followed by an acknowledge from
the NM24Wxx and then by the eight bit word. The master will not
acknowledge the transfer but does generate the stop condition,
and therefore the NM24Wxx discontinues transmission. Refer to
Figure 8 for the address, acknowledge and data transfer se-
quence.
Current Address Read
Internally the NM24Wxx contains an address counter that main-
tains the address of the last word accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to one, the
NM24Wxx issues an acknowledge and transmits the eight bit
word. The master will not acknowledge the transfer but does
generate a stop condition, and therefore the NM24Wxx discontin-
ues transmission. Refer to Figure 7 for the sequence of address,
acknowledge and data transfer.
Sequential Read
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24Wxx continues to output data for each acknowl-
edge received. The read operation is terminated by the master not
respondingwithanacknowledgeorbygeneratingastopcondition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter 'rolls over' and the
NM24Wxx continues to output data for each acknowledge re-
ceived. Refer to Figure 9 for the address, acknowledge, and data
transfer sequence.
Random Read
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address, R/W bit set to zero, and then the word address it is
to read. After the word address acknowledge, the master imme-
Current Address Read (Figure 7)
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
Bus Activity:
Master
SDA Line
A
C
K
DS500074-14
DATA
Random Read (Figure 8)
S
T
A
R
T
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
BYTE
ADDRESS
SLAVE
ADDRESS
Bus Activity:
Master
S
SDA Line
A
C
K
A
C
K
A
C
K
DATA n
DS500074-15
Sequential Read (Figure 9)
S
T
O
P
A
C
K
A
C
K
A
C
K
Bus Activity:
SLAVE
Master
ADDRESS
SDA Line
A
C
K
DATA n
DATA n +1
DATA n + 2
DATA n + x
DS500074-16
10
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Read Operations (Continued)
Typical System Configuration (Figure 11)
V
CC
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
DS500074-17
Master
Transmitter
Slave
Receiver
Note:
Due to open drain configuration of SDA, a bus-level resistor is called for (Typical value = 4.7Ω)
11
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Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8
7
6
5
0.228 - 0.244
(5.791 - 6.198)
1
2
3
4
Lead #1
IDENT
0.150 - 0.157
0.053 - 0.069
(1.346 - 1.753)
(3.810 - 3.988)
0.010 - 0.020
(0.254 - 0.508)
0.004 - 0.010
(0.102 - 0.254)
x 45°
8° Max, Typ.
All leads
Seating
Plane
0.04
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020
(0.356 - 0.508)
Typ.
8-Pin Molded Small Outline Package (M8)
Package Number M08A
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Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(7.72) Typ
(4.16) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
Land pattern recommendation
1
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0256 (0.65)
Typ.
Gage
plane
0.0075 - 0.0098
(0.19 - 0.30)
0°-8°
DETAIL A
Typ. Scale: 40X
0.0075 - 0.0098
(0.19 - 0.25)
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC
Package Number MTC08
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Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
7
0.032 ± 0.005
(0.813 ± 0.127)
8
7
6
5
4
0.092
(2.337)
RAD
DIA
0.250 - 0.005
Pin #1
IDENT
+
Pin #1 IDENT
(6.35 ± 0.127)
1
Option 1
1
2
3
Option 2
0.280
MIN
0.040
(1.016)
Typ.
(7.112)
0.030
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
MAX
(0.762)
0.300 - 0.320
(7.62 - 8.128)
20° ± 1°
0.130 ± 0.005
(3.302 ± 0.127)
0.125 - 0.140
95° ± 5°
(3.175 - 3.556)
0.065
(1.651)
0.125
(3.175)
DIA
0.020
90° ± 4°
Typ
0.009 - 0.015
(0.229 - 0.381)
(0.508)
Min
0.018 ± 0.003
(0.457 ± 0.076)
NOM
+0.040
-0.015
0.325
0.100 ± 0.010
+1.016
-0.381
8.255
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a)areintendedforsurgicalimplantintothebody,or(b)support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably ex-
pected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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Americas
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Fairchild Semiconductor
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Fairchild Semiconductor
Japan Ltd.
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Tel. 1-888-522-5372
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Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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