NM9835 [ETC]
PCI + Dual UART and 1284 Printer Port; PCI +双UART和1284打印机端口
| 型号： | NM9835 |
| 厂家： | 
ETC |
| 描述： | PCI + Dual UART and 1284 Printer Port |
| 文件： | 总23页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Features
Applications
• Single 5-V Operation
• Printer server
• Low Power
• Portable backup units
• Printer interface
• PCI compatible Dual UART
• Pin-to-Pin compatible to Nm9735
• 16 byte transmit-receive FIFO (UART)
• Selectable receive trigger levels
• Programmable baud rate generator
• Modem control signals
• Embedded applications
• High speed modems
• Monitoring equipment
• Add on I/O cards
• Serial networking
• 5, 6, 7, 8 Bit characters selection
• Even, Odd, No parity, or Force parity generations
• Status report capability
• Compatible with 16C550
• Multi-mode compatible controller (SPP, PS2, EPP,
ECP)
• Fast data rates up to 1.5 Mbytes/s (parallel port)
• Fast data rates up to 1 Mbytes/s (serial ports)
• On chip oscillator
• Re-map function for legacy ports
• 16 Byte FIFO (parallel)
• Microsoft Compatible
• Software programmable mode selects
• 128-pin VQFP package
General Description
Ordering Information
Commercial Grade
128-VQFP 0° C to +70° C
The Nm9835 is a PCI based dual-channel high perfor-
mance UART with Enhanced bi-directional parallel con-
troller. The Nm9835 offers 16 byte transmit and receive
FIFO for each UART channel and 16 byte FIFO for
printer channel. The Nm9835 perform serial-to-parallel
conversions on data received from a peripheral device,
and parallel-to-serial conversion on data received from
its CPU. In addition Nm9835 fully supports the existing
Centronics printer interface as well as PS/2, EPP, and
ECP modes.
Nm9835CV
Industrial Grade
Nm9835EV
128-VQFP -40° C to +85° C
The Nm9835 is ideally suited for PC applications, such
as high speed COM ports and parallel port. The Nm9835
is available in 128-Pin QFP package, It is fabricated in
an advanced in submicron CMOS process to achieve
low drain power and high speed requirements.
Page 1-51
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
128-Pin VQFP Package
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
AD28
AD27
AD26
AD25
AD24
GND
nC/BE3
IDSEL
VCC
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
N.C.
N.C.
N.C.
GND
PD7
PD6
PD5
PD4
GND
PD3
PD2
PD1
PD0
VCC
GND
PE
nACK
nBUSY
SLCT
nFAULT
VCC
nSTROBE
nAUTOFDX
nINIT
nSLCTIN
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
GND
GND
nC/BE2
nFRAME
nIRDY
nTRDY
nDEVSEL
nSTOP
nLOCK
nPERR
nSERR
PAR
nC/BE1
GND
AD15
AD14
AD13
TXB
nDTRB
nRTSB
RXB
nDSRB
nCTSB
nCDB
nRIB
N.C.
N.C.
VCC
N.C.
AD12
AD11
Page 1-52
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Pin Name
128
Type
Description
CLK
122
121
I
I
33 MHz PCI system clock input.
nRESET
PCI System reset (avtice low). Resets all internal register, sequencers, and
signals to a consistent state. During reset condition AD31-0, nSER are three-
stated.
AD31-29 126-128
I/O
Multiplexed PCI address / data bus. A bus transaction consists of an address
phase followed by one or more data phase. During the address phase AD31-
0 contain a physical address. Write data is stable and valid when nIRDY and
nTRDY are asserted (active).
AD28-24
2-6
I/O
I/O
I/O
I/O
I/O
I
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
AD23-16 11-18
AD15-11 34-38
AD10-8
AD7-0
40-42
46-53
23
nFRAME
Frame is driven by the current master to indicate the beginning and duration
of an access. nFRAME is asserted to indicate a bus transaction is beginning.
While nFRAME is active, data transfer continues.
nIRDY
24
I
Initiator Ready. During a write, nIRDY asserted indicates that the initiator is
driving valid data onto the data bus. During a read, nIRDY asserted indicates
that the initiator is ready to accept data from the Nm9835.
nTRDY
nSTOP
nLOCK
IDSEL
25
27
28
9
O
O
I
Target Ready (three-state). It is asserted when Nm9835 is ready to complete
the current data phase.
Nm9835 asserts nSTOP to indicate that it wishes the initiator to stop the
transaction in process on the current data phase.
Lock indicates an atomic operation that my require multiple transactions to
complete.
I
Initialization Device Select. It is used as a chip select during configuration
read and writes transactions.
nDEVSEL 26
O
O
Device Select (three-state). Nm9835 asserts nDEVSEL when the Nm9835
has decoded its address.
nPERR
29
Parity Error (three-state). Is used to report parity errors during all PCI trans-
Page 1-53
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Pin Name
128
Type
Description
actions except a Special Cycle. The minimum duration of nPERR is one clock
cycle.
nSERR
PAR
30
31
O
System Error (open drain). This pin goes low when address parity errors are
detected.
I/O
Even Parity. Parity is even parity across AD31-0 and nC/BE3-0. PAR is stable
and valid one clock after the address phase. For data phase PAR is stable
and valid one clock after either nIRDY is asserted on a write transaction or
nTRDY is asserted on a read transaction.
nC/BE3
nC/BE2
nC/BE1
nC/BE0
8
I
I
I
I
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables.nC/BE3 applies to byte “3”.
22
32
43
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables. nC/BE2 applies to byte “2”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables. nC/BE1 applies to byte “1”.
Bus Command and Byte Enable. During the address phase of a transaction,
nC/BE3-0 defines the bus command. During data phase nC/BE3-0 are used
as Byte Enables. nC/BE0 applies to byte “0”.
nINTA
EE-CS
120
115
O
O
PCI active low interrupt output (open-drain). This signal goes low (active)
when an interrupt condition occurs.
External EE-Prom chip select (active high). After power on reset, Nm9835
reads the EE-Prom and loads the read-only configuration registers sequen-
tially from the first 64 bytes in the EE-Prom.
EE-CLK
EE-DI
116
118
117
123
O
I
External EE-Prom clock.
External EE-Prom data input.
External EE-Prom data output.
EE-DO
EE-EN
O
I
Enable/Disable external EEprom (active high, internal pull-up). External
EEprom can be disabled when this pin is tied to GND or pulled low. When
external EEprom is disabled, the default values for Nm9835 will be loaded
into PCI configuration register.
XTAL1
62
I
Crystal oscillator input or External clock input pin (22.1184 MHz). This signal
Rev. 1.0
Page 1-54
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Pin Name
128
Type
Description
input is used in conjunction with XTAL2 to form a feedback circuit for the
internal timing. Two external capacitors (10pF) connected from each side of
the XTAL1 and XTAL2 to GND is required to form a crystal oscillator circuit.
XTAL2
61
58
O
O
Crystal oscillator output. See XTAL1 description.
12XCLK
External clock or crystal oscillator clock divide by 12 output (1.8432 MHz
standard PC UART clock for 115.2k data rate).
6XCLK
3XCLK
ACLK
56
55
59
57
O
O
I
External clock or crystal oscillator clock divide by 6 output (3.6864 MHz PC
UART clock for 230.4k data rate).
External clock or crystal oscillator clock divide by 3 output (7.3728 MHz UART
clock for 460.8k data rate).
UART-A clock input. ACLK should be connected to external clock source or
one of the 12XCLK, 6XCLK, 3XCLK output pins of the Nm9835.
BCLK
I
UART-B clock input. BCLK should be connected to external clock source or
one of the 12XCLK, 6XCLK, 3XCLK output pins of the Nm9835.
TXA
105
107
O
O
UART-A Serial data output.
nRTSA
Active low, UART-A request-to-send signal. It is set to high (in active) after a
hardware reset or during internal loop-back mode. When low, this indicates
that Modem or data set is ready to establish a communication link. nRTSA
has no effect on the transmitter or receiver.
nDTRA
106
O
Active low, UART-A data-terminal-ready signal. It is set to high (in active)
after a hardware reset or during internal loop-back mode. When low, this
output indicates to the Modem or data set that the UART-A is ready to estab-
lish a communication link. nDTRA has no effect on the transmitter or re-
ceiver.
RXA
109
111
I
I
UART-A, Serial data input.
nCTSA
Active low, UART-A clear-to-send signal. When low this indicates that Mo-
dem or data set is ready to exchange data. nCTSA has no effect on the
transmitter.
nDSRA
nCDA
110
112
I
I
Active low, UART-A data-set-ready signal.
Active low, UART-A Carrier-detect signal. When low this indicates that Mo-
dem or data set has detected the data carrier. nCDA has no effect on the
transmitter.
Page 1-55
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Pin Name
128
Type
Description
nRIA
113
76
I
Active low, UART-A ring-detect signal.
UART-B Serial data output.
TXB
O
O
nRTSB
74
Active low, UART-B request-to-send signal. It is set to high (in active) after a
hardware reset or during internal loop-back mode. When low, this indicates
that Modem or data set is ready to establish a communication link. nRTSB
has no effect on the transmitter or receiver.
nDTRB
75
O
Active low, UART-B data-terminal-ready signal. It is set to high (in-active)
after a hardware reset or during internal loop-back mode. When low, this
output indicates to the Modem or data set that the UART-B is ready to estab-
lish a communication link. nDTRB has no effect on the transmitter or re-
ceiver.
RXB
73
71
I
I
UART-B, Serial data input.
nCTSB
Active low, UART-B clear-to-send signal. When low this indicates that Mo-
dem or data set is ready to exchange data. nCTSB has no effect on the
transmitter.
nDSRB
nCDB
72
70
I
I
Active low, UART-B data-set-ready signal.
Active low, UART-B Carrier-detect signal. When low this indicates that Mo-
dem or data set has detected the data carrier. nCDB has no effect on the
transmitter.
nRIB
69
84
I
I
Active low, UART-B ring-detect signal.
SLCT
Peripheral/printer selected (internal pull-up). This pin is set to high by periph-
eral/printer when it is selected.
PE
87
85
86
I
I
I
Paper empty (internal pull-up). This pin is set to high by peripheral/printer
when printer paper is empty.
nBUSY
nACK
Peripheral/printer busy (internal pull-up). This pin is set to high by peripheral/
printer, when printer or peripheral is not ready to accept data.
Peripheral/printer data acknowledge (internal pull-up). This pin is set to low
by peripheral/printer to indicate a successful data transfer has taken place.
During SPP mode when interrupt is enabled, nINTA pin follows the nACK
input pin state.
nFAULT
83
I
Peripheral/printer data error (internal pull-up). This pin is set to low by periph-
eral/printer during error condition.
Page 1-56
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Pin Name
128
Type
Description
nSTROBE 81
nAUTOFDX 80
O
Peripheral/printer data strobe (open drain, active low). On the rising edge of
the nSTROBE, data is latched into printer port.
O
O
O
Peripheral/printer auto feed (open-drain, active low). Continuous autofed pa-
per is selected when this pin is set to low.
nINIT
79
78
Initialize the Peripheral/printer (open drain, active low). When set to low, Pe-
ripheral/printer starts it’s initialization routine.
nSLCTIN
Peripheral/printer select (open-drain, active low). Selects the peripheral/printer
when it is set to low.
PD7-PD4 98-95
PD3-PD0 93-90
I/O
I/O
Peripheral/printer data ports.
Peripheral/printer data ports.
Power and signal ground.
GND
7,20,21,
33,44,45,
60,77,88,
94,99,108
119,125
Pwr
VCC
1,10,19,
39,54,66,
82,89,104,
114
Pwr
5-V Supply.
Page 1-57
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
PCI bus operation:
Transaction duration:
The execution of PCI bus transaction takes place in The initiator, as stated earlier, gives only start address
broadly five stages, address phase, transaction Claim- during address phase but does not tell the number of
ing, data phase(s), final data transfer and transaction data transfers in a burst transfer transaction. However
completion.
the initiator indicates the completion of data transfer of
a transaction by asserting nIRDY and de-asserting
nFRAME during the last data transfer phase. The trans-
Address phase:
Every PCI transaction starts off with an address phase, action however, does not complete until the target has
one PCI clock period in duration. During address phase also asserted the nTRDY signal and the last data trans-
the initiator (Also known as current bus master) identi- fer takes place. At this point the nTRDY and nDEVSEL
fies the target device (via the address) and type of trans- are de-asserted by the target.
action. (via the Command).The initiator drives the 32
bit address on to 32 bit Address/Data bus and 4bit com- Transaction completion:
mand on to 4bit Command / Byte enable bus. The ini- When all of nIRDY, nTRDY, nDEVSEL, and nFRAME
tiator also asserts the nFRAME signal during the same are in inactive state (high state), the bus is in idle state.
clock cycle to indicate the presence of valid address The bus is ready to be claimed by another bus master.
and transaction type on those buses. The initiator sup-
plies start address (and the target, Nm9835, generates
the subsequent sequential addresses for burst trans- Internal address select configuration
fers) and command type for one PCI clock cycle. The
Address/Data bus becomes Data bus and Command/
Byte enable bus becomes Byte enable bus for the re-
mainder of the clock cycles of that transaction. The tar-
get (Nm9835) latches the address and command type
on the next rising edge of PCI clock (and so do all the
devices on that PCI bus). The target (Nm9835) decodes
the address and determines whether it is being ad-
dressed, and decodes the command to determine the
type of transaction.
I/O Address Function
XX00-XX07 UART-A
XX00-XX07 UART-B
XX00-XX07 Standard Printer
XX00
XX01
XX02
Printer Configuration Register A
Printer Configuration Register B
Printer ECR Register
Claiming the transaction:
When Nm9835 determines that it is the target of a trans-
action, it claims the transaction by asserting nDEVSEL.
Data phase(s):
The data phase of a transaction is the period during
which a data object is transferred between the initiator
and the target (Nm9835). The number of data bytes to
be transferred during a data phase is determined by
the number of Command/Byte enable signals that are
asserted by the initiator during the data phase. Each
data phase is at least one PCI clock period in duration.
Both initiator and target must indicate that they are ready
to complete a data phase. If not, the data phase is ex-
tended by a wait state of one clock period in duration.
The initiator and the target indicate this by asserting
nIRDY and nTRDY respectively and the data transfer
is completed at the rising edge of the next PCI clock.
Page 1-58
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Nm9835 Configuration space register map
AD 31-23
Device ID (9835)
Status
Class Code (070002)
Header Type
AD 22-16
AD 15-8
Vendor ID (9710)
Command
Revision ID (01)
Latency Timer Cache Size (08)
AD 7-0
Addr
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
BIST
I/O (E1)Base Address
I/O (E2)Base Address
I/O (E3)Base Address
I/O (E4)Base Address
Reserved
Reserved
Reserved
Subsystem ID
Subsystem Vendor ID
Reserved
Reserved
Reserved
Max Latency (00)
Min Grant (00)
Interrupt Pin (01)
Interrupt Line
Page 1-59
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
UART Registers Table
Ex A2 A1 A0
Register
RHR
BIT-7
bit-7
bit-7
0
BIT-6
bit-6
bit-6
0
BIT-5
bit-5
bit-5
BIT-4
bit-4
bit-4
BIT-3
bit-3
bit-3
BIT-2
bit-2
bit-2
BIT-1
bit-1
bit-1
BIT-0
bit-0
bit-0
Ex 0
Ex 0
Ex 0
0
0
0
0
0
1
THR
IER
Power
Down
Sleep
Mode
modem
status
receive transmit receive
line
holding
holding
interrupt
status
register register
interrupt
Ex 0
Ex 0
Ex 0
Ex 1
Ex 1
Ex 1
1
1
1
0
0
1
0
0
1
0
1
0
FCR
IIR
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
0
0
0
0
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
0/
0/
int
int
int
int
FIFO
FIFO
priority
bit-2
priority
bit-1
priority
bit-0
status
enabled enabled
LCR
MCR
LSR
MSR
divisor
latch
set
set
even
parity
stop
bits
word
length
bit-1
word
length
bit-0
break
parity
parity
enable
enable
0
0
Flow
loop
INT
(nOP1)
nRTS
nDTR
Control
back
enable
(nOP2)
0/
trans.
empty
trans.
break
framing
error
parity
error
overrun receive
FIFO
error
holding interrupt
empty
error
data
ready
nCD
nRI
nDSR
nCTS
delta
nCD
delta
nRI
delta
delta
nDSR
nCTS
Ex 1
Ex 0
Ex 0
1
0
0
1
0
1
SPR
DLL
DLM
bit-7
bit-7
bit-6
bit-6
bit-5
bit-5
bit-4
bit-4
bit-3
bit-3
bit-2
bit-2
bit-1
bit-1
bit-9
bit-0
bit-0
bit-8
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
DLL and DLM are accessible only when LCR Bit-7=1.
E1: Internal UART-A chip select
E2: Internal UART-B chip select
Page 1-60
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Printer Registers Table
Ex A2 A1 A0 REGISTER
D7
PD7
D6
D5
PD5
PE
D4
D3
PD3
D2
D1
PD1
“0”
D0
E3 0
E3 0
0
0
0
1
DPR
DSR
PD6
PD4
SLCT
PD2
PD0
nBUSY
nACK
FAULT
INT
EPP
state
TIMEOUT
E3 0
E3 0
1
1
0
1
DCR
“0”
“0”
DIR
INTA
nSLCTIN
ADD-3
INIT
nAUTOFDnSTROBE
EPP
ADD-7
ADD-6
ADD-5
ADD-4
ADD-2
ADD-1
DAT-1
DAT-9
ADD-0
DAT-0
DAT-8
Address
E3 1
E3 1
E3 1
E3 1
0
0
1
1
0
1
0
1
EPP
data
DAT-7
DAT-6
DAT-5
DAT-4
DAT-3
DAT-2
EPP
data
DAT-15 DAT-14 DAT-13 DAT-12 DAT-11 DAT-10
EPP
data
DAT-23 DAT-22 DAT-21 DAT-20 DAT-19 DAT-18 DAT-17 DAT-16
DAT-31 DAT-30 DAT-29 DAT-28 DAT-27 DAT-26 DAT-25 DAT-24
CDAT-7 CDAT-6 CDAT-5 CDAT-4 CDAT-3 CDAT-2 CDAT-1 CDAT-0
EPP
data
E4 0
E4 0
E4 0
0
0
0
0
0
1
C-FIFO
CONF-A
CONF-B
“1”
“0”
“0”
“0”
“0”
“1”
“0”
“0”
“0”
“1”
“0”
“0”
“0”
“0”
“0”
INT
Pin
E4 0
1
0
ECR
MODE
select
ErrIntrEn
enable
Service
Int
FIFO
full
FIFO
“0”
empty
E3: Internal standard printer chip select
E4: Internal printer configuration register chip select
Page 1-61
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
UART Registers Description
IER Bit-1:
0 = Disable the transmitter holding register empty inter-
rupt.
Transmitter Holding Register (THR)
The transmitter section of the Nm9835 consists of a 1 = Enable the transmitter holding register empty inter-
transmitter holding register (THR) and a transmitter shift rupt.
register (TSR). The THR is actually a 16-byte FIFO.
Transmitter section control is a function of the Nm9835 IER Bit-2:
line control register. The Nm9835 THR receives data 0 = Disables the receiver line status interrupt.
off the internal data bus and when the shift register is 1 = Enables the receiver line status interrupt.
idle, moves it into the TSR. The TSR serializes the data
and outputs it at TX. In the 16C450 mode, if the THR is IER Bit-3:
empty and the transmitter holding register empty (THRE) 0 = Disables the modem status interrupt.
interrupt is enabled (IER-1=1), an interrupt is generated. 1 = Enables the modem status interrupt.
This interrupt is cleared when a character is loaded into
the register. In the FIFO mode, the interrupts are gen- IER Bit 4:
erated based on the control setup in the FIFO control 0 = Standard 16C450/550 mode. Sleep mode is dis-
register.
abled.
1 = Enables Sleep mode. The Nm9835 is always awake
when there is a byte in the transmitter, activity on the
Receive Holding Register (RHR)
The receiver section of the Nm9835 consists of a re- RX, or either Delta CTS, Delta DSR, Delta CD, Delta RI
ceiver shift register (RSR) and a receiver Holding reg- is/are set to logic “1”, or when the device is in the loop-
ister (RHR). The RHR is actually a 16-byte FIFO. Tim- back mode.
ing to receive holding register is supplied by the 16x-
receiver clock. Receiver section control is a function of IER Bit 5:
the Nm9835 line control register.
0 = Standard 16C450/550 mode. Power down mode is
The Nm9835 RHR receives serial data from RX. The disabled.
RSR then concatenates the data and moves it into the 1 = Enables the power down mode. Power down mode
RHR FIFO. In the 16C450 mode, when a character is functions similar to Sleep mode, except oscillator sec-
placed in the receiver holding register and the received tion.
data available interrupt is enabled (IER-0=1), an inter-
rupt is generated. This interrupt is cleared when the data IER Bits 6-7:
is read out of the receiver holding register. In the FIFO These bits are not used (always set to 0).
mode, the interrupts are generated based on the con-
trol setup in the FIFO control register.
Interrupt Identification Register (IIR)
The Nm9835 has an on chip interrupt generation and
prioritization capability that permits a flexible interface
Interrupt Enable Register (IER)
The interrupt enables register enables each of the five with most popular microprocessors.
types of interrupts and INT pin response to an interrupt
generation. The interrupt enable register can also be IIR Bit-0:
used to disable the interrupt system by setting bits 0-3 0 = An interrupt is pending. Used either in a hardware
to logic 0. The contents of this register are described prioritized or polled interrupt system.
below.
1 = No interrupt is pending.
IER Bit-0:
0 = Disable the received data available interrupt.
1 = Enables the received data available interrupt.
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NetMos
Technology
PCI + Dual UART and 1284 Printer Port
IIR Bits 1-2:
Reading MSR register will clear this interrupt.
The Nm9835 provides four prioritized levels of interrupts:
IIR Bit-3:
Priority 1 - Receiver line status (highest priority)
Priority 2 - Receiver data ready
0 = In the 16C450 mode. In FIFO mode, this bit is set
along with bit-2 to indicate that a time-out interrupt is
pending.
Priority 2 - Receiver character time-out
Priority 3 - Transmitter holding register empty
Priority 4 - Modem status (lowest priority)
IIR Bit 4:
This bit is not used (always reset at 0).
When an interrupt is generated, the interrupt identifica-
tion register indicates that an interrupt is pending and IIR Bit 5:
encodes the type of interrupt in its three least signifi- 0 = 16C450/550 mode, 16 byte FIFO mode.
cant bits (bits 0, 1, and 2).
1 = Enhance FIFO mode. 64 byte FIFO mode enabled.
Interrupt Priority decode
IIR Bits 6-7:
0 = In the 16C450 mode.
1 = When FCR-0 is equal to 1.
Bit-3 Bit-2 Bit-1 Bit-0 Interrupt source
FIFO control register (FCR)
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
Receive data Error
Receive data ready
Receive time-out
The FIFO control register (FCR) is a write only register.
The (FCR) enables and clears the FIFO sets receive
FIFO trigger level, and selects the type of DMA signal-
ing.
Transmit holding empty
Modem status change
FCR Bit-0:
0 = 16C450 mode, disables the transmitter and receiver
The bits are used to identify the highest priority inter- FIFO.
rupt pending.
1 = Enables the transmitter and receiver FIFO. This bit
must be set to 1 when other (FCR) bits are written to or
IIR Bit-0 will clear to “1” when no interrupt is pending. they are not programmed. Changing this bit clears the
To clear the interrupts following reads from registers FIFO.
are required.
FCR Bit-1:
Receive Data Error:
0 = Normal operation
Reading LSR register will clear this interrupt. User 1 = Clears all bytes in the receiver FIFO and resets its
should save LSR value after reading the register to counter logic to 0. The shift register is not cleared. The
maintain the error condition.
one that is written to this bit position is self-clearing.
Receive Data Ready:
FCR Bit-2:
Reading RHR register till FIFO becomes empty.
0 = Normal operation
1 = Clears all bytes in the transmit FIFO and resets its
counter logic to 0. The shift register is not cleared. The
one that is written to this bit position is self-clearing.
Receive Timeout:
Reading entire characters from RHR.
Transmit Holding empty:
FCR Bit-3:
Writing a character into THR register or reading IIR reg- 0 = Mode [0]:
ister (if source of interrupt).
Supports single transfer DMA (16C450 mode) in which
a transfer is made between CPU bus cycle.
Modem Status Change:
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Technology
PCI + Dual UART and 1284 Printer Port
1 = Mode [1]:
This bit specifies, 1, 1-1/2, or 2 stop bits in each trans-
Supports multi transfer DMA in which multiple transfers mitted character. When bit-2 is reset to 0, one stop bit
are made continuously until the receiver FIFO has been is generated in the data. When bit-2 is set to 1, the num-
emptied.
ber of stop bits generated is dependent on the word
length selected with bits 0 and 1. The receiver clocks
only the first stop bit regardless of the number of stop
bits selected. The number of stop bits generated in re-
lation to word length and bit-2.
FCR Bit 5-4:
This bit is not used.
FCR Bits 6-7:
These bits are used to set the trigger level for receive Stop Bits
FIFO interrupt.
Receive trigger levels (BYTES)
Bit-2 Word length
Stop bit(s)
0
1
1
1
1
X
1
1-1/2
2
Bit-7 Bit-6
RX FIFO trigger level
5 bits
6 bits
7 bits
8 bits
0
0
1
1
0
1
0
1
1
4
2
2
8
14
LCR Bit-3:
0 = Parity is disabled. No parity is generated or checked.
1 = Parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received
Line Control Register (LCR)
The system programmer controls the format of the asyn- data, parity is checked.
chronous data communication exchange through the
line control register. In addition, the programmer is able LCR Bit-4:
to retrieve, inspect, and modify the contents of the line 0 = ODD parity select bit. When parity is enabled by bit-
control register; this eliminates the need for separate 3, a 1 in bit-4 produces odd parity (an odd number of
storage of the line characteristics in system memory.
1’s in the data and parity bits.
1 = Even parity select bit. When parity is enabled by bit-
3, a 1 in bit-4 produces even parity (an even number of
LCR Bits 0-1:
These two bits specify the number of bits in each trans- 1’s in the data and parity bits).
mitted or received serial character.
LCR Bit-5:
Word Length
0 = Stick parity is disabled.
1 = Stick parity bit. When bits 3-5 are set to 1 the parity
bit is transmitted and checked as a 0. When bits-3 and
5 are 1’s and bit-4 is a 0, the parity bit is transmitted and
checked as 1.
Bit-1 Bit-0 Word length
0
0
1
1
0
1
0
1
5 bits
6 bits
7 bits
8 bits
LCR Bit-2:
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NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Parity selection
MCR Bit-4:
0 = Normal operation.
1 = Internal loop back mode. Provides a local loop-back
Bit-5 Bit-4 Bit-3
Parity type
feature for diagnostic testing of the Nm9835. When
LOOP is set to 1, the following occurs:
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
The transmitter TX pin is set to high.
Odd parity
The receiver RX pin is disconnected.
Even parity
The output of the transmitter shift register is looped back
into the receiver shift register input.
Forced parity “1”
Forced parity “0”
The four modem inputs (nCTS, nDSR nCD and nRI)
pins are disconnected. The four modem outputs (nDTR,
nRTS, nOP1, and nOP2) pins are internally connected
to the four modem inputs. The four modem outputs are
LCR Bit-6:
0 = Normal operation. Break condition is disabled and forced to the high levels.
has no effect on the transmitter logic.
1 = Force a break condition. A condition where TX is In the diagnostic mode, data that is transmitted is im-
forced to the space (low) state.
mediately received. This allows the processor to verify
transmit and receive data paths to the Nm9835. The
receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but
LCR Bit-7:
0 = Normal operation.
1 = Divisor latch enable. Must be set to 1 to access the the modem control interrupt sources are now the lower
divisor latches of the baud generator during a read or four bits of the modem control register instead of the
write. Bit-7 must be reset to 0 during a read or write to four modem control inputs. All interrupts are still con-
the receiver holding, the transmitter holding register, or trolled by the interrupt enable register.
the interrupt enable register.
MCR Bit-5:
Modem Control Register (MCR)
0 = 16C450/550 mode. Hardware flow control is dis-
The modem control register is an 8-bit register that con- abled.
trols an interface with a modem, data set, or peripheral 1 = Enable hardware flow control (nRTS/nCTS).
device that is emulating a modem.
MCR Bit-0:
MCR Bit-5
MCR Bit-1
Flow Control
0 = Sets the nDTR output pin to high.
1 = Sets the nDTR output pin to low.
1
1
0
1
0
Auto RTS/CTS
Auto CTS only
Disabled
MCR Bit-1:
X
0 = Sets the nRTS output pin to high.
1 = Sets the nRTS output pin to low.
nRTS becomes active (low) when the receiver is empty
or the threshold has not been reached. When receiver
FIFO level reaches a trigger level of 1, 4, 8, and 14,
nRTS is de-asserted (high). nRTS is automatically re-
asserted once the receiver FIFO is empty by reading
receive holding register.
MCR Bit-2:
0 = Sets the nOP1 to high during loop-back mode.
1 = Sets the nOP1 to low during loop-back mode.
MCR Bit-3:
0 = Disables UART interrupt. Sets the nOP2 to high
during loop-back mode.
The transmitter circuitry checks nCTS before sending
1 = Enables UART interrupt. This bit is gated with IER the next data byte. When nCTS is active (low), the trans-
Bits 0-3. Sets the nOP2 to low during loop-back mode. mitter sends the next byte. To stop the transmitter from
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NetMos
Technology
PCI + Dual UART and 1284 Printer Port
sending the next byte, nCTS must be released before LSR Bit-3:
the middle of the last stop bit that is currently being sent. 0 = Normal operation (No framing error).
1 = It indicates that the received character did not have
MCR bits 6-7:
a valid stop bit. FE is reset every time the CPU reads
the contents of the line status register. In the FIFO mode,
this error is associated with the particular character in
the FIFO to which it applies. This error is revealed to
These bits are not used.
Line Status Register (LSR)
The line status register provides information to the CPU the CPU when its associated character is at the top of
concerning the status of data transfers. The line status the FIFO. The Nm9835 tries to re-synchronize after a
register is intended for read operations only; writing to framing error. To accomplish this, it is assumed that the
this register is not recommended. Bits 1-4 are the error framing error is due to the next start bit.
conditions that produce a receiver line status interrupt.
LSR Bit-4:
LSR Bit-0:
0 = Normal operation.
0 = No data in receive holding or FIFO.
1 = It indicates that the received data input was held in
1 = Data ready indicator for the receiver. This bit is set the logic low state for longer than a full word transmis-
to 1 whenever a complete incoming character has been sion time. A full word transmission time is defined as
received and transferred into the receiver holding reg- the total time to transmit the start, data, parity, and stop
ister or the FIFO. It is reset to 0 by reading all of the bits. BI is reset every time the CPU reads the contents
data in the receiver holding register or the FIFO.
of the line status register. In the FIFO mode, this error
is associated with the particular character in the FIFO
to which it applies. This error is revealed to the CPU
when its associated character is at the top of the FIFO.
LSR Bit-1:
0 = Normal operation. No overrun error.
1 = It indicates that before the character in the receiver When a break occurs, only one 0 character is loaded
holding register was read, it was over written by the into the FIFO.
next character transferred into the register. OE is reset
every time the CPU reads the contents of the line sta- LSR Bit-5:
tus register. If the FIFO mode data continues to fill the 0 = At least one byte is written to the transmit FIFO or
FIFO beyond the trigger level, an overrun error occurs transmit holding register.
only after the FIFO is full and the next character has 1 = Transmitter holding register is empty, indicating that
been completely received in the shift register. An over- the Nm9835 is ready to accept a new character. If the
run error is indicated to the CPU as soon as it happens. THRE interrupt is enabled when THRE is set to 1, an
The character in the shift register is overwritten, but it is interrupt is generated. THRE is set to 1 when the con-
not transferred to the FIFO.
tents of the transmitter holding register are transferred
to the transmitter shift register.
LSR Bit-2:
0 = Normal operation (No parity error).
LSR Bit-6:
1 = It indicates that the parity of the received data char- 0 = When either the transmitter holding register or the
acter does not match the parity selected in the line con- transmitter shift register contains a data character.
trol register. PE is reset every time the CPU reads the 1 = Transmitter holding register and the transmitter shift
contents of the line status register. In the FIFO mode, register are both empty.
this error is associated with the particular character in
the FIFO to which it applies. This error is revealed to LSR Bit-7:
the CPU when its associated character is at the top of 0 = In the 16C450, this bit is always reset to 0.
the FIFO.
1 = In the FIFO mode, at least one parity, framing, or
break error in the FIFO. It is cleared when the micro-
processor reads the LSR and there are no subsequent
errors in the FIFO.
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Technology
PCI + Dual UART and 1284 Printer Port
Modem Status Register (MSR)
MSR Bit-7:
The modem status register is an 8-bit register that pro- Complement of the data carrier detects (nCD) input.
vides information about the current state of the control When the Nm9835 is in the diagnostic test mode, this
lines from the modem, data set, or peripheral device to bit is equal to nOP2.
the CPU. Additionally, four bits of this register provide
change information, when input from the modem Scratch Pad Register (SPR)
Changes State, the appropriate bit is set to 1. All four The scratch pad register is an 8-bit register that is in-
bits are reset to 0 when the CPU reads the modem sta- tended for programmer use as a scratch pad in the sense
tus register.
that it temporarily holds the programmer data without
affecting any other Nm9835 operation.
MSR Bit-0:
0 = No change to nCTS input.
Programmable Baud-Rate Generator
1 = Indicates that the nCTS input has changed state The Nm9835 contains a programmable baud genera-
since the last time it was read by the CPU. When inter- tor that takes a clock input of 1.8432 MHz and divides it
16
rupt is enabled, a modem status interrupt is generated. by a divisor in the range between 1 and (2 -1) The out-
put frequency of the baud generator is 16 times the baud
MSR Bit-1:
rate. Two 8-bit registers, called divisor latches, store
the divisor in a 16-bit binary format. These divisor latches
0 = No change to nDSR input.
1 = Indicates that the nDSR input has changed state must be loaded during initialization of the Nm9835 in
since the last time it was read by the CPU. When inter- order to ensure desired operation of the baud genera-
rupt is enabled, a modem status interrupt is generated. tor. When either of the divisor latches is loaded, a 16-bit
baud counter is also loaded to prevent long counts on
MSR Bit-2:
initial load.
0 = No change to nRI input.
1 = Indicates that the nRI input has changed from a low Baud rate generator programming table for 1.8432
to a high level. When nRI is set to 1 and the modem MHz clock (12XCLK).
status interrupt is enabled, a modem status interrupt is
generated.
Baud out DLM
DLL
MSR Bit-3:
(hex) (hex)
0 = No change to nCD input.
1 = Indicates that the nCD input has changed state since
the last time it was read by the CPU. When interrupt is
enabled, a modem status interrupt is generated.
115.2k
57.6k
38.4k
19.2
9600
2400
1200
600
00
00
00
00
00
00
00
00
01
03
09
01
02
03
06
0C
30
60
C0
80
00
00
MSR Bit-4:
Complement of the clear to send (nCTS) input. When
the Nm9835 is in the diagnostic test mode, this bit is
equal to nRTS.
300
MSR Bit-5:
150
Complement of the data set ready (nDSR) input. When
the Nm9835 is in the diagnostic test mode, this bit is
equal to nDTR.
50
FIFO interrupt mode operation
MSR Bit-6:
When the receiver FIFO and receiver interrupts are
Complement of the ring indicator (nRI) input. When the enabled (FCR-0=1, IER-0=1, IER-2=1), a receiver in-
Nm9835 is in the diagnostic test mode, this bit is equal terrupt occurs as follows:
to nOP1.
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Technology
PCI + Dual UART and 1284 Printer Port
The received data available interrupt issued to the mi- time that TEMT=1. TEMT is set after the stop bit has
croprocessor when the FIFO has reached its pro- been completely shifted out.
grammed trigger level. It is cleared when the FIFO drops
below its programmed trigger level. The IIR receive data The transmitter FIFO empty indicator works the normal
available indication also occurs when the FIFO trigger way in this mode and is not delayed. Character time-
level is reached, and like the interrupt, it is cleared when out and receiver FIFO trigger-level interrupts have the
the FIFO drops below the trigger level.
same priority as the current
Received data available interrupt.
The receiver line status interrupt has higher priority than
the received data available interrupt. The data ready bit Parallel Port Register Description
(LSR-0) is set when a character is transferred from the
shift register to the receiver FIFO. It is reset when the Data Register
FIFO is empty.
Data register is cleared at initialization by RESET. Dur-
ing a write operation, the Data register latches the con-
When the receiver FIFO and receiver interrupts are tents of the data bus with the rising edge of the nIOW
enabled, FIFO time-out interrupt occurs when the fol- input. The contents of this register are buffered and
lowing conditions exist:
output onto the PD7-PD0 ports. During a read opera-
tion PD7-PD0 ports are buffered and output to the host
At least one character is in the FIFO. The most recent CPU on the falling edge of the nIOR input.
serial character was received more than four continu-
ous character times ago (if two stop bits are pro- Device Status Register
grammed, the second one is included in this time de- The contents of this register are latched for the duration
lay). The most recent microprocessor read of the FIFO of an nIOR cycle. The bits of the Status Port are de-
occurred more than five continuous character times ago. fined as follows.
When a time-out interrupt has occurred, it is cleared
and the timer is reset when the microprocessor reads DSR Bit-0:
one character from the receiver FIFO.
0 = Normal.
When a time-out interrupt has not occurred, the time- 1 = 10µs timeout (EPP mode only). Cleared by writing 1
out timer is reset after a new character is received or into DSR register or consecutive reads (after the first
after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are en-
read) always returns “0”.
abled (FCR-0=1, IER-1=1), transmit interrupts occur as DSR Bit-1:
follows:
Not used, set to “0”.
The occurrence of transmitter holding register empty DSR Bit-2:
interrupt is delayed one character time minus the last 0 = nACK input pin is at low state (INT follows the nACK
stop bit time when there have not been at least two pin), when SPP mode is selected. Normal (no interrupt)
bytes in the transmitter FIFO at the same time since the when PS/2 mode is selected.
last time the transmitter FIFO was empty. It is cleared 1 = Normal (no interrupt). In standard mode operation,
as soon as the transmitter holding register is written to INT is active (interrupt is generated on the rising edge
(1 to 64 characters may be written to transmit FIFO while of the nACK). It is cleared when DSR is read.
servicing this interrupt) or the IIR is read. The first trans-
mitter interrupt after changing FCR is immediate if it is DSR Bit-3:
enabled.
0 = Printer reports error condition.
1 = Normal operation.
The transmitter empty indicator is delayed one charac-
ter time when there has not been at least two bytes in DSR Bit-4:
the transmitter FIFO at the same time since the last 0 = Printer is off line.
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Technology
PCI + Dual UART and 1284 Printer Port
1 = Printer is on line.
DCR Bits 7-6:
Not used, set to “0”.
DSR Bit-5:
0 = Normal operation
1 = Paper End/Empty is detected
Config: -A Register
Configuration A register (read only). Reading this reg-
ister returns 10010100. Writing to this register has no
effect and the data is ignored.
DSR Bit-6:
0 = State of the nACK pin (ACK = low).
1 = State of the nACK pin (ACK = high).
Config: -B Register
DSR Bit-7:
0 = nBUSY pin is high, printer is not ready to take data. Configuration B register. This register allows software
1 = nBUSY pin is low, printer is read to take data.
to control the selecting of interrupts. A read-write imple-
mentation implies a “software-configurable” device.
Reading this register, returns the configured interrupt,
and interrupt pin state. If a value is not set to 000 (the
jumper-default) then it is assumed that the value in the
register is correct and software will use the default in-
Device Control Register
DCR Bit-0
0 = Sets the nSTROBE pin to high.
1 = Sets the nSTROBE pin to low. PD7-PD0 data are terrupt.
latched into printer
Config-B Bit-7:
DCR Bit-1:
Not used, set to “0”.
0 = Sets the nAUTOFD pin to high. Printer generates
auto line feed after each line is printed.
Config-B Bit-6:
1 = Sets the nAUTOFD pin to low. No auto feed func- 0 = Configured printer interrupt pin is low.
tion.
1 = Configured printer interrupt pin is high.
DCR Bit-2:
Config-B Bit 7-0:
0 = Sets the INIT pin to high.
1 = Sets the INIT pin to low. Peripheral/printer starts it’s
initialization routine.
Interrupt pin select register.
Extended Control Register (ECR)
DCR Bit-3:
0 = Sets the nSLCTIN pin to high. Selects the printer.
This register controls the mode selection and DMA op-
1 = Sets the nSLCTIN pin to low. Printer is not selected. eration.
DCR Bit-4:
0 = Disables Printer interrupt function. nACK pin has
no effect on the INT pin.
Bit-7
Bit-6
Bit-5
Operating Mode
1 = Enables Printer interrupt function. The INT follows
the nACK input pin during standard mode, latches high
on the rising edge of the nACK, when PS/2 mode is
selected.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SPP
PS/2
PPF (FIFO mode)
ECP
EPP
DCR Bit-5:
Not used
0 = PD7-PD0 pins are out put mode.
1 = PD7-PD0 pins are input mode.
FIFO test
Config A/B enable
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Technology
PCI + Dual UART and 1284 Printer Port
Mode changes.
The Byte mode protocol is used to transfer bi-directional
data via PD7-PD0 ports without FIFO utilization. The
After hardware reset, PS/2 mode is selected as default direction of the port is controlled with DIR bit in DCR
mode. It is required to select mode 000 or 001 between register. PS/2-Byte use SPP protocol for data transfer.
any other mode configuration.
DCR Bit-5:
Mode “000”
0 = PD7-PD0 pins are out put mode.
1 = PD7-PD0 pins are input mode.
SPP/Centronics/Compatible Mode
Forward direction only. The direction bit is forced to “0”
and PD7-PD0 are set to output direction. The Nm9835 Mode “010”
is under software controlled. This mode defines the pro- FIFO output Mode
tocol used by most PC’s to transfer data to a printer. It In this mode, bytes written to the FIFO are transmitted
is commonly called the “Centronics” mode and is the automatically using the SPP/Centronics standard pro-
method utilized with the standard parallel port. Data is tocol.
placed on the PD7-PD0 port’s, the printer status is
checked via DSR register. If no error condition is flagged Mode “011”
and printer is not Busy, software toggles the nSTROBE Extended Capability Port “ECP” Mode
pin to latch the PD7-PD0 data into printer. This operat- The ECP provides an advanced mode for communica-
ing cycle continues when printer/peripheral issues data tion with printer or peripherals. Like EPP protocol, ECP
acknowledge signal (pules the ACK and nBUSY pin).
provides 16 byte FIFO for a high performance bi-direc-
tional communication path between the host adapter
and the peripheral. The ECP protocol provides the fol-
lowing cycle types in both the forward and reverse di-
Nibble Mode
The Nibble mode is the most common way to get re- rection.
verse channel data from a printer or peripheral. This
mode is usually combined with the Centronics mode or • Data cycle
a proprietary forward channel mode to create a Bi-di- • Command cycles
rectional channel. In this mode printer status bits are
used as Nibble bits.
• Run-Length counts (RLE)
• Channel address
Bits order for Nibble mode.
The RLE feature enables real time data compression
that can achieve compression ratios up to 64:1. This is
particularly useful for printers and peripherals that are
transferring large raster images that have large strings
of identical data. In order for the RLE mode to be en-
abled, both the host and peripheral must support it.
Channel addressing is intended to address multiple logi-
cal devices within single physical device like Modem/
FAX/Printer in one physical package.
Pins
Data Bits
nBUSY
PE
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
SLCT
nFAULT
nBUSY
PE
Mode “100”
SLCT
nFAULT
Enhanced Parallel Port “EPP” Mode
In EPP mode, nSLCTIN (address strobe) and nAUTOFD
(data strobe) are automatically generated while
nSTROBE indicates a write or read cycle. Additional I/
O addresses are defined for data and address access
and when these locations are used, handshaking is
performed automatically by Nm9835.
Mode “001”
PS/2, Byte Mode
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Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Mode “110”
FIFO test Mode
bit to a “1” will not cause an interrupt.
In this mode, the FIFO can be written and read in any Port Direction (DCR Bit-5 = 0), this bit will be set to “1”
direction, but no data will be transmitted on the PD7- whenever there are Write Interrupt threshold (4 charac-
PD0 ports. Whoever, data in the FIFO may be displayed ters) or more bytes free in the FIFO. The Nm9835 gen-
on the PD7-PD0 ports.
erates interrupt when this condition is occurred and
Service Interrupt is cleared to “0”.
ECR Bit-4:
Error Interrupt Enable.
Port Direction (DCR Bit-5 = 1), this bit will be set to “1”
0 = Enable nFAULT interrupt. nFAULT pin is used as whenever there are Read Interrupt threshold (12 char-
source of interrupt.
acters) or more bytes to be read from the FIFO. The
1 = Disable nFAULT interrupt (nACK is used as source Nm9835 generates interrupt when this condition is oc-
of interrupt).
curred and Service Interrupt is cleared to “0”.
ECR Bit-3:
ECR Bit-1:
0 = normal operating mode.
0 = One or more empty location in FIFO is available.
1 = FIFO full.
ECR Bit-2:
1 = Disables service interrupt.
ECR Bit-0:
0 = Enables one of the following 3 cases of interrupts. 0 = One or more data in FIFO.
One of the 3 service interrupts has occurred, Service 1 = FIFO empty.
interrupt bit will be set to a “1” by hardware. Writing this
Master rest conditions
Register
BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
RHR
THR
IER
0
X
0
0
0
0
0
0
X
0
0
X
0
0
0
0
0
1
X
0
0
X
0
0
0
0
0
1
X
0
0
X
0
0
0
0
0
0
X
0
0
X
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
X
0
0
1
0
0
0
0
0
FCR
IIR
LCR
MCR
LSR
MSR
SPR
DPR
X
0
0
0
0
1
0
0
X
1
0
0
0
0
X
0
X
1
0
0
0
0
0
0
X
1
0
0
0
1
0
0
X
1
0
0
0
0
0
0
X
0
0
0
0
1
0
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
1
DSR
DCR
EPP
C-FIFO
CONF-A
CONF-B
ECR
Page 1-71
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Absolute Maximum Ratings
Supply Range
7 Volts
GND – 0.3 to VCC +0.3
-45° C to 90° C
-65° C to 150° C
500 mW
Voltage at any pin
Operating Temperature
Storage Temperature
Package Dissipation
ESD
±2000 Volts
Latch up
220 mA
DC Electrical Specification
T = 0° C to 70° C (-40° C to +85° C for industrial “E” grade parts), VCC = 5V ± 10% unless otherwise specified.
Symbol Parameter
5-V
Unit
Condition
Min
Max
Vil
Input Low voltage
-0.3
2.0
0.8
V
V
Vih
Input High voltage
Vt-
Schmitt trigger negative
going threshold voltage
1.10
V
Vt+
Schmitt trigger positive
going threshold voltage
1.87
V
Vol
Output low voltage
Output high voltage
0.4
V
C
Iol=4 mA
Ioh=4 mA
Voh
3.5
Iil
Input low current
Input high current
±1
±1
µA
µA
Iih
Ioz
Three state leakage current
±10
µA
Cin
Input capacitance
Output capacitance
3
3
5
5
pF
pF
Cout
Icc
Operating current
60
mA
No load
Revision Notes
Date
1.0
-
7/00
Page 1-72
Rev. 1.0
Nm9835
NetMos
Technology
PCI + Dual UART and 1284 Printer Port
Notes:
Page 1-73
Rev. 1.0
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