NRF2401_技术文档

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

Single chip 2.4 GHz Transceiver

Q5)ꢀꢁꢂꢃ

)($785(6

$33/,&$7,216

•

True single chip GFSK transceiver in a small

24-pin package (QFN24 5x5mm)

Data rate 0 to1Mbps

Only 2 external components

Multi channel operation

•

Wireless mouse, keyboard, joystick

Keyless entry

•

Wireless data communication

Alarm and security systems

Home automation

Surveillance

Automotive

Telemetry

Intelligent sports equipment

Industrial sensors

Toys

•

125 channels

Channel switching time <200µs.

Support frequency hopping

•

Data slicer / clock recovery of data

Address and CRC computation

DuoCeiver™ for simultaneous dual receiver

topology

•

ShockBurst™ mode for ultra-low power

operation and relaxed MCU performance

Power supply range: 1.9 to 3.6 V

Low supply current (TX), typical 10.5mA peak

@ -5dBm output power

•

Low supply current (RX), typical 18mA peak in

receive mode

•

100% RF tested

No need for external SAW filter

World wide use

*(1(5$/ꢄ'(6&5,37,21

nRF2401 is a single-chip radio transceiver for the world wide 2.4 - 2.5 GHz ISM

band. The transceiver consists of a fully integrated frequency synthesizer, a power

amplifier, a crystal oscillator and a modulator. Output power and frequency channels

are easily programmable by use of the 3-wire serial interface. Current consumption is

very low, only 10.5mA at an output power of -5dBm and 18mA in receive mode.

Built-in Power Down modes makes power saving easily realizable.

48,&.ꢄ5()(5(1&(ꢄ'$7$

3DUDPHWHU

9DOXH

1.9

8QLW

V

Minimum supply voltage

Maximum output power

Maximum data rate

Supply current in transmit @ -5dBm output power

Supply current in receive mode

Temperature range

0

1000

10.5

18

-40 to +85

-90

dBm

kbps

mA

° C

Sensitivity

Supply current in Power Down mode

dBm

µΑ

1

Table 1 nRF2401 quick reference data

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Page 1 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

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NRF2401 IC

'HVFULSWLRQ

24 pin QFN 5x5

9HUVLRQ

A

NRF2401-EVKIT

Evaluation kit (2 test PCB, 2 configuration PCB, SW)

1.0

Table 2 nRF2401 ordering information

%/2&.ꢄ',$*5$0

XC1

XC2

PWR_UP

DuoCeiver^TM

VSS=0V

ShockBurst^TM

VSS_PA=0V

DEMOD

VDD_PS=1.8V

CE

LNA

Clock

Recovery,

DataSlicer

ADDR

Decode

CRC

DR2

DOUT2

CLK2

Data

Channel 2

Frequency

Synthesiser

Code/Decode

FIFO

DR1

DATA

CLK1

In/Out

Data

Channel 1

ANT1

GFSK

Filter

PA

400

ANT2

Ω

3-wire

interface

CS

IREF

22kΩ

Figure 1 nRF2401 with external components.

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Page 2 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

ꢄ3,1ꢄ)81&7,216

3LQ 1DPH

3LQꢄIXQFWLRQ 'HVFULSWLRQ

1

2

3

4

5

6

7

CE

Digital Input

Digital Output

Digital I/O

Digital Output

Digital Input

Digital Output

Digital I/O

Chip Enable Activates RX or TX mode

DR2

CLK2

DOUT2

CS

DR1

CLK1

RX Data Ready at Data Channel 2 (ShockBurst™ only)

Clock Output/Input for RX Data Channel 2

RX Data Channel 2

Chip Select Activates Configuration Mode

RX Data Ready at Data Channel 1 (ShockBurst™ only)

Clock Input (TX) & Output/Input (RX) for Data Channel 1

3-wire interface

8

9

DATA

DVDD

VSS

XC2

XC1

VDD_PA

ANT1

ANT2

VSS_PA

VDD

VSS

IREF

VSS

VDD

VSS

PWR_UP

VDD

Digital I/O

Power

Analog Output

Analog Input

Power Output

RF

Power

Analog Input

Power

Digital Input

Power

RX Data Channel 1/TX Data Input/ 3-wire interface

Positive Digital Supply output for decoupling purposes

Ground (0V)

Crystal Pin 2

Crystal Pin 1

Power Supply (+1.8V) to Power Amplifier

Antenna interface 1

Antenna interface 2

Ground (0V)

Power Supply (+3V DC)

Ground (0V)

Reference current

Ground (0V)

Power Supply (+3V DC)

Ground (0V)

Power Up

Power Supply (+3V DC)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Table 3 nRF2401 pin function

3,1ꢄ$66,*10(17

IREF

VDD PWR_UP VSS

VDD

VSS

24 23 22

20 19

21

CE

VSS

VDD

18

17

16

15

14

13

1

Q5)ꢀꢁꢂꢃ

DR2

2

QFN24 5x5

CLK2

VSS_PA

ANT2

3

DOUT2

4

CS

ANT1

5

DR1

VDD_PA

6

7

8

9

DVDD

10 11 12

VSS

XC2

XC1

CLK1 DATA

Figure 2. nRF2401 pin assignment (top view) for a QFN24 5x5 package.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

(/(&75,&$/ꢄ63(&,),&$7,216

Conditions: VDD = +3V, VSS = 0V, T_A= - 40ºC to + 85ºC

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1RWHV

0LQꢅ

7\Sꢅ

0D[ꢅ

8QLWV

2SHUDWLQJꢄFRQGLWLRQV

VDD

TEMP

Supply voltage

1.9

-40

3.0

+27

3.6

+85

V

ºC

Operating Temperature

'LJLWDOꢄLQSXWꢄSLQ

HIGH level input voltage

LOW level input voltage

V_IH

V_IL

VDD- 0.3

Vss

VDD

0.3

V

'LJLWDOꢄRXWSXWꢄSLQ

HIGH level output voltage (I_OH=-0.5mA)

LOW level output voltage (I_OL=0.5mA)

V_OH

V_OL

VDD- 0.3

Vss

VDD

0.3

V

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Operating frequency

Crystal frequency

Frequency deviation

Data rate ShockBurst™

Data rate Direct Mode

f_OP

f_XTAL

∆f

R_GFSK

1)

2)

2400

4

2524

20

MHz

kHz

kbps

MHz

±156

1

>0

250

1000

3)

4)

F_CHANNELChannel spacing

7UDQVPLWWHUꢄRSHUDWLRQ

Maximum Output Power

RF Power Control Range

P_RF

P_RFC

P_RFCR

P_BW

P_RF2

P_RF3

I_VDD

0

20

+4

dBm

dB

kHz

dBm

mA

16

RF Power Control Range Resolution

20dB Bandwidth for Modulated Carrier

2^ndAdjacent Channel Transmit Power 2MHz

3^rdAdjacent Channel Transmit Power 3MHz

Supply current @ 0dBm output power

Supply current @ -20dBm output power

Average Supply current @ -5dBm output

power, ShockBurst™

±3

1000

-20

-40

5)

6)

13

8.8

0.8

I_VDD

Average Supply current in stand-by mode

Average Supply current in power down

7)

12

1

µA

5HFHLYHUꢄRSHUDWLRQ

I_VDD

Supply current one channel 250kbps

Supply current one channel 1000kbps

Supply current two channels 250kbps

Supply current two channels 1000kbps

18

19

23

mA

dBm

dB

25

RX_SENSSensitivity at 0.1%BER (@250kbps)

RX_SENSSensitivity at 0.1%BER (@1000kbps)

-90

-80

6

C/I_CO

C/I_1ST

C/I_2ND

C/I_3RD

RX_B

C/I Co-channel

1^stAdjacent Channel Selectivity C/I 1MHz

2^ndAdjacent Channel Selectivity C/I 2MHz

3^rdAdjacent Channel Selectivity C/I 3MHz

Blocking Data Channel 2

-1

-16

-26

-41

1) Usable band is determined by local regulations

2) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) which are specified in

the configuration word, see Table 8. 16MHz are required for 1Mbps operation.

3) Data rate must be either 250kbps or 1000kbps.

4) De-embedded Antenna load impedance = 400 Ω

5) De-embedded Antenna load impedance = 400 Ω. Effective data rate 250kbps or 1Mbps.

6) De-embedded Antenna load impedance = 400 Ω. Effective data rate 10kbps.

7) Current if 4 MHz crystal is used.

Table 4 nRF2401 RF specifications

Nordic VLSI ASA

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March 2003

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

3$&.$*(ꢄ287/,1(

nRF2401 uses the QFN 24LD 5x5 package. Dimensions are in mm.

3DFNDJHꢄ7\SH

QFN24

$

0.8

$

0.0

$ꢀ

0.75

E

0.25

0.3

'

(

H

-

.

/

3.47 3.47 0.35

3.57 3.57 0.4

0LQ

W\Sꢅ

(5x5 mm)

5 BSC

0.65 BSC

1

0.05

1

0.35

3.67 3.67 0.45

0D[

Figure 3 nRF2401 package outline.

Nordic VLSI ASA

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Vestre Rosten 81, N-7075 Tiller, Norway

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

$EVROXWHꢄ0D[LPXPꢄ5DWLQJV

6XSSO\ꢄYROWDJHV

VDD ............................- 0.3V to + 3.6V

VSS .................................................. 0V

,QSXWꢄYROWDJH

V_I.......................- 0.3V to VDD + 0.3V

2XWSXWꢄYROWDJH

V_O......................- 0.3V to VDD + 0.3V

7RWDOꢄ3RZHUꢄ'LVVLSDWLRQ

P_D(T_A=85°C).............................. 90mW

7HPSHUDWXUHV

Operating Temperature…. - 40°C to + 85°C

Storage Temperature….… - 40°C to + 125°C

1RWHꢀꢁ 6WUHVVꢁ H[FHHGLQJꢁ RQHꢁ RUꢁ PRUHꢁ RIꢁ WKHꢁ OLPLWLQJꢁ YDOXHVꢁ PD\ꢁ FDXVHꢁ SHUPDQHQW

GDPDJHꢁWRꢁWKHꢁGHYLFHꢂ

$77(17,21ꢈ

Electrostatic Sensitive Device

Observe Precaution for handling.

Nordic VLSI ASA

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Page 6 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

*ORVVDU\ꢄRIꢄ7HUPV

7HUP

CLK

'HVFULSWLRQ

Clock

CRC

CS

Cyclic Redundancy Check

Chip Select

CE

Chip Enable

DR

Data Ready

GFSK

ISM

MCU

OD

Gaussian Frequency Shift Keying

Industrial-Scientific-Medical

Micro controller

Overdrive

PWR_DWN

PWR_UP

RX

Power Down

Power Up

Receive

ST_BY

TX

Standby

Transmit

Table 5 Glossary

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

02'(6ꢄ2)ꢄ23(5$7,21

2YHUYLHZ

The nRF2401 can be set in the following main modes depending on three control

pins:

PWR_UP

CE

1

0

X

CS

0

1

0

X

0RGH

Active (RX/TX)

Configuration

Stand by

1

0

Power down

Table 6 nRF2401 main modes

For a complete overview of the nRF2401 I/O pins in the different modes please refer

to Table 7.

$FWLYHꢄPRGHV

The nRF2401 has two active (RX/TX) modes:

•

ShockBurst™

Direct Mode

The device functionality in these modes is decided by the content of a configuration

word. This configuration word is presented in configuration section.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

6KRFN%XUVW

The ShockBurst™ technology uses on-chip FIFO to clock in data at a low data rate

and transmit at a very high rate thus enabling extremely power reduction.

When operating the nRF2401 in ShockBurst™, you gain access to the high data rates

(1 Mbps) offered by the 2.4 GHz band without the need of a costly, high-speed micro

controller (MCU) for data processing.

By putting all high speed signal processing related to RF protocol on-chip, the

nRF2401 offers the following benefits:

•

Highly reduced current consumption

Lower system cost (facilitates use of less expensive micro controller)

Greatly reduced risk of ‘on-air’ collisions due to short transmission time

The nRF2401 can be programmed using a simple 3-wire interface where the data rate

is decided by the speed of the micro controller.

By allowing the digital part of the application to run at low speed while maximizing

the data rate on the RF link, the nRF ShockBurst™ mode reduces the average current

consumption in applications considerably.

6KRFN%XUVWꢄSULQFLSOH

When the nRF2401 is configured in ShockBurst™, TX or RX operation is conducted

in the following way (10 kbps for the example only).

Continuous 10kbps

Q5)ꢂꢃꢄꢅ

ꢀꢁELW

0&8

FIFO

ShockBurst^TM1Mbps

Figure 4 Clocking in data with MCU and sending with ShockBurst technology

Without ShockBurst^TM, running at speed dictated by 10Kbs MCU

10mA periode

10Kbs MCU with ShockBurst^TM

10mA period

0

20

40

60

80

100

120

140

160

180

200

220

240

Time mS

Figure 5 Current consumption with & without ShockBurst technology

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Page 9 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

NO

nRF2401 in

ShockBurst^TM

TX (CE=hi)?

YES

Data content of registers:

uController

Loading ADDR

and PAYLOAD

data

ADDR

PAYLOAD

Maximum 256 bits

nRF2401

Calculating CRC

ADDR

PAYLOAD

CRC

NO

CE=Low?

YES

nRF2401

Adding Preamble

Pre-

amble

ADDR

PAYLOAD

CRC

nRF2401

Sending

ShockBurst^TM

Package

Input FIFO not Empty

(250 or 1000kbps)

YES

NO

Sending

completed?

Figure 6 Flow Chart ShockBurst™ Transmit of nRF2401

Q5)ꢀꢁꢂꢃꢄ6KRFN%XUVWꢄ7UDQVPLWꢉ

MCU interface pins: CE, CLK1, DATA

1. When the application MCU has data to send, set CE high. This activates

RF2401 on-board data processing.

2. The address of the receiving node (RX address) and payload data is

clocked into the nRF2401. The application protocol or MCU sets the speed

<1Mbps (ex: 10kbps).

3. MCU sets CE low, this activates a nRF2401 ShockBurst™ transmission.

4. nRF2401 ShockBurst™:

•

RF front end is powered up

RF package is completed (preamble added, CRC calculated)

Data is transmitted at high speed (250 kbps or 1 Mbps configured

by user).

•

nRF2401 return to stand-by when finished

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Page 10 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

nRF2401 in

NO

ShockBurst^TM

RX?

YES

Data content of registers:

nRF2401

Detects

PREAMBLE and

Incoming Data

Pre-

ADDR

PAYLOAD

CRC

amble

NO

Correct

ADDR?

ADDR

PAYLOAD

CRC

YES

nRF2401

Receives Data

and

ADDR

PAYLOAD

Checking CRC

NO

nRF2401

Checks:

Correct CRC?

YES

nRF2401

Set Data Ready

(DR1/2) high

PAYLOAD

uController

Clocks out

Payload

NO

nRF2401

Register

Empty?

YES

nRF2401

Sets Data Ready

(DR1/2) low

Output Register Empty

Figure 7 Flow Chart ShockBurst™ Receive of nRF2401

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Page 11 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

Q5)ꢀꢁꢂꢃꢄ6KRFN%XUVWꢄ5HFHLYHꢉ

MCU interface pins: CE, DR1, CLK1 and DATA (one RX channel receive)

1. Correct address and size of payload of incoming RF packages are set when

nRF2401 is configured to ShockBurst™ RX.

2. To activate RX, set CE high.

3. After 200 µs settling, nRF2401 is monitoring the air for incoming

communication.

4. When a valid package has been received (correct address and CRC found),

nRF2401 removes the preamble, address and CRC bits.

5. nRF2401 then notifies (interrupts) the MCU by setting the DR1 pin high.

6. MCU may (or may not) set the CE low to disable the RF front end (low

current mode).

7. The MCU will clock out just the payload data at a suitable rate (ex. 10

kbps).

8. When all payload data is retrieved nRF2401 sets DR1 low again, and is

ready for new incoming data package if CE is kept high during data

download. If the CE was set low, a new start up sequence can begin, see

Figure 16.

'LUHFWꢄ0RGH

In direct mode the nRF2401 works like a traditional RF device. Data must be at

1Mbps, or 250kbps at low data rate setting, for the receiver to detect the signals.

'LUHFWꢄ0RGHꢄ7UDQVPLWꢉ

MCU interface pins: CE, DATA

1. When application MCU has data to send, set CE high

2. The nRF2401 RF front end is now immediately activated, and after 200 µs

settling time, data will modulate the carrier directly.

3. All RF protocol parts must hence be implemented in MCU firmware

(preamble, address and CRC).

'LUHFWꢄ0RGHꢄ5HFHLYHꢉ

MCU interface pins: CE, CLK1, and DATA

1. Once the nRF2401 is configured and powered up (CE high) in direct RX

mode, DATA will start to toggle due to noise present on the air.

2. CLK1 will also start to toggle as nRF2401 is trying to lock on to the

incoming data stream.

3. Once a valid preamble arrives, CLK1 and DATA will lock on to the

incoming signal and the RF package will appear at the DATA pin with the

same speed as it is transmitted.

4. To enable the demodulator to re-generate the clock, the preamble must be

8 bits toggling hi-low, starting with low if the first data bit low.

5. In this mode no data ready (DR) signals is available. Address and

checksum verification must also be done in the receiving MC.

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Page 12 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

'XR&HLYHUꢄ6LPXOWDQHRXVꢄ7ZRꢄ&KDQQHOꢄ5HFHLYHꢄ0RGH

In both ShockBurst™ & Direct modes the nRF2401 can facilitate simultaneous

reception of two parallel independent frequency channels at the maximum data rate.

This means:

•

nRF2401 can receive data from two 1 Mbps transmitters (ex: nRF2401 or

nRF2402) 8 MHz (8 frequency channels) apart through one antenna

interface.

•

The output from the two data channels is fed to two separate MCU

interfaces.

•

Data channel 1: CLK1, DATA, and DR1

Data channel 2: CLK2, DOUT2, and DR2

DR1 and DR2 are available only in ShockBurst™.

The nRF2401 DuoCeiver™ technology provides 2 separate dedicated data channels

for RX and replaces the need for two, stand alone receiver systems.

Q5)ꢀꢁꢂꢃ

7[ꢊ5[

Q5)ꢀꢁꢂꢃ

7[ꢊ5[

Q5)ꢀꢁꢂꢃ

7[ꢊ5[

Figure 8 Simultaneous 2 channel receive on nRF2401

There is one absolute requirement for using the second data channel. For the nRF2401

to be able to receive at the second data channel the frequency channel must be 8MHz

higher than the frequency of data channel 1. The nRF2401 must be programmed to

receive at the frequency of data channel 1. No time multiplexing is used in nRF2401

to fulfil this function. In direct mode the MCU must be able to handle two

simultaneously incoming data packets if it is not multiplexing between the two data

channels. In ShockBurst™ it is possible for the MCU to clock out one data channel at

a time while data on the other data channel waits for MCU availability, without any

lost data packets, and by doing so reduce the needed performance of the MCU.

DR1

Clock

Recovery,

DataSlicer

ADDR,

CRC

Check

F_RF1

CLK1

DATA

Data(F_RF1

)

DR2

Clock

Recovery,

DataSlicer

ADDR,

CRC

Check

F_RF2=F_RF1+8MHz

CLK2

DOUT2

Data(F_RF2

Figure 9 DuoCeiver^TMwith two simultaneously independent receive channels.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

&RQILJXUDWLRQꢄ0RGH

In configuration mode a configuration word of up to 15 bytes is downloaded to

nRF2401. This is done through a simple 3-wire interface (CS, CLK1 and DATA). For

more information on configuration please refer to the nRF2401 Device configuration

chapter on page16.

6WDQGꢋ%\ꢄ0RGH

Stand by mode is used to minimize average current consumption while maintaining

short start up times. In this mode, part of the crystal oscillator is active. Current

consumption is dependent on crystal frequency (Ex: 12 µA @ 4 MHz, 32 µA @ 16

MHz). The configuration word content is maintained during stand by.

3RZHUꢄ'RZQꢄ0RGH

In power down the nRF2401 is disabled with minimal current consumption, typically

less than 1µA. Entering this mode when the device is not active minimizes average

current consumption, maximizing battery lifetime. The configuration word content is

maintained during power down.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

'(9,&(ꢄ&21),*85$7,21

All configuration of the nRF2401 is done via a 3-wire interface to a single

configuration register. The configuration word can be up to 15 bytes long for

ShockBurst™ use and up to 2 bytes long for direct mode.

&RQILJXUDWLRQꢄIRUꢄ6KRFN%XUVWꢄRSHUDWLRQ

The configuration word in ShockBurst™ enables the nRF2401 to handle the RF

protocol. Once the protocol is completed and loaded into nRF2401 only one byte,

bit[7:0], needs to be updated during actual operation.

The configuration blocks dedicated to ShockBurst™ is as follows:

•

Payload section width: Specifies the number of payload bits in a RF package.

This enables the nRF2401 to distinguish between payload data and the CRC

bytes in a received package.

•

Address width: Sets the number of bits used for address in the RF package.

This enables the nRF2401 to distinguish between address and payload data.

Address (RX Channel 1 and 2): Destination address for received data.

CRC: Enables nRF2401 on-chip CRC generation and de-coding.

•

NOTE:

These configuration blocks, with the exception of the CRC, are dedicated for the

packages that a nRF2401 is to receive.

In TX mode, the MCU must generate an address and a payload section that fits the

configuration of the nRF2401 that is to receive the data.

When using the nRF2401 on-chip CRC feature ensure that CRC is enabled and uses

the same length for both the TX and RX devices.

PRE-AMBLE

ADDRESS

PAYLOAD

CRC

Figure 10 Data packet set-up

&RQILJXUDWLRQꢄIRUꢄ'LUHFWꢄ0RGHꢄRSHUDWLRQ

For direct mode operation only the two first bytes (bit[15:0]) of the configuring word

are relevant.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

&RQILJXUDWLRQꢄ:RUGꢄRYHUYLHZ

%LW

1XPEHU

1DPH

)XQFWLRQ

SRVLWLRQ RIꢄELWV

143:120

119:112

111:104

103:64

63:24

24

8

TEST

Reserved for testing

DATA2_W

DATA1_W

ADDR2

Length of data payload section RX channel 2

Length of data payload section RX channel 1

Up to 5 byte address for RX channel 2

Up to 5 byte address for RX channel 1

Number of address bits (both RX channels).

8 or 16 bit CRC

8

40

6

ADDR1

23:18

ADDR_W

CRC_L

17

1

16

15

1

CRC_EN

RX2_EN

Enable on-chip CRC generation/checking.

Enable two channel receive mode

14

13

1

3

2

7

1

CM

Communication mode (Direct or ShockBurst™)

RF data rate (1Mbps requires 16MHz crystal)

Crystal frequency

RFDR_SB

XO_F

12:10

9:8

7:1

0

RF_PWR

RF_CH#

RXEN

RF output power

Frequency channel

RX or TX operation

Table 8 Table of configuration words.

The configuration word is shifted in MSB first on positive CLK1 edges. New

configuration is enabled on the falling edge of CS.

NOTE.

On the falling edge of CS, the nRF2401 updates the number of bits actually shifted in

during the last configuration.

Ex:

If the nRF2401 is to be configured for 2 channel RX in ShockBurst™, a total of 120

bits must be shifted in during the first configuration after VDD is applied.

Once the wanted protocol, modus and RF channel are set, only one bit (RXEN) is

shifted in to switch between RX and TX.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

&RQILJXUDWLRQꢄ:RUGꢄ'HWDLOHGꢄ'HVFULSWLRQ

The following describes the function of the 144 bits (bit 143 = MSB) that is used to

configure the nRF2401.

General Device Configuration: bit[15:0]

ShockBurst™ Configuration: bit[119:0]

Test Configuration: bit[143:120]

MSB

D143

TEST

D139

Reserved for testing

D142

0

D141

0

D140

D138

1

D137

1

D136

0

Default

1

0

1

MSB

D135

TEST

D127

D134

D133

D132

D131

D130

D129

D128

D126

D125

D124

D123

D122

D121

D120

Close PLL in TX

Reserved for testing

Default

0

1

0

1

0

DATA2_W

D116 D115

Data width channel#2 in # of bits excluding addr/crc

D119

0

D118

D117

D114

D113

D112

0

Default

0

1

0

DATA1_W

D108 D107

Data width channel#1 in # of bits excluding addr/crc

D111

0

D110

D109

D106

D105

D104

0

1

0

ADDR2

D103

D102

D101

….

D71

D70

D69

D68

D67

0

D66

D65

1

D64

1

Channel#2 Address RX (up to 40bit)

1

Default

0

…

1

0

1

ADDR1

D63

0

D62

0

D61

0

….

D31

D30

D29

D28

D27

0

D26

1

D25

1

D24

1

Channel#1 Address RX (up to 40bit)

…

1

0

ADDR_W

D23

D22

D21

D20

D19

D18

Address width in # of bits (both channels)

Default

0

1

0

CRC

D17

D16

CRC Mode 1 = 16bit, 0 = 8bit

0

CRC 1 = enable; 0 = disable

1

Default

LSB

RF-Programming

D10 D9 D8

XO Frequency

D15

Two Ch.

0

D14

BUF

0

D13

OD

0

D12

D11

D7

D6

0

D5

D4

D3

D2

D1 D0

RXEN

RF Power

1

Channel selection

0

Default

0

1

0

1

0

Table 9 Configuration data word

The MSB bit should be loaded first into the configuration register.

Default configuration word: h8E08.1C20.2000.0000.00E7.0000.0000.E721.0F04.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

6KRFN%XUVWꢄFRQILJXUDWLRQꢆ

The section B[119:16] contains the segments of the configuration register dedicated to

ShockBurst™ operational protocol. After VDD is turned on ShockBurst™

configuration is done once and remains set whilst VDD is present. During operation

only the first byte for frequency channel and RX/TX switching need to be changed.

3//B&75/

'ꢃꢀꢃ 'ꢃꢀꢂ

3//

0

1

0

1

0

1

Open TX/Closed RX

Open TX/Open RX

Closed TX/Closed RX

Closed TX/Open RX

Table 10 PLL setting.

Bit 121-120:

PLL_CTRL: Controls the setting of the PLL for test purposes. With closed

PLL in TX no deviation will be present.

'$7$[B:

'$7$ꢀB:

119

111

118

110

117

109

116

115

114

106

113

105

112

104

'$7$ꢃB:

108

107

Table 11 Number of bits in payload.

Bit 119 – 112:

DATA2_W: Length of RF package payload section for receive-channel 2.

Bit 111 – 104:

DATA1_W: Length of RF package payload section for receive-channel 1.

NOTE:

The total number of bits in a ShockBurst™ RF package may not exceed 256!

Maximum length of payload section is hence given by:

'$7$[ _: (ELWV) = 256 − $''5 _: − &5&

Where:

ADDR_W: length of RX address set in configuration word B[23:18]

CRC: check sum, 8 or 16 bits set in configuration word B[17]

PRE: preamble, 4 or 8 bits are automatically included

Shorter address and CRC leaves more room for payload data in each package.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

$''5[

$''5ꢀ

103

102

101

….

71

31

70

69

68

28

67

27

66

65

64

24

ADDR1

30 29

63

62

61

26

25

Table 12 Address of receiver #2 and receiver #1.

Bit 103 – 64:

ADDR2: Receiver address channel 2, up to 40 bit.

Bit 63 – 24: ADDR1

ADDR1: Receiver address channel 1, up to 40 bit.

NOTE!

Bits in ADDRx exceeding the address width set in ADDR_W are redundant

and can be set to logic 0.

$''5B:ꢄꢇꢄ&5&

$''5B:

21

&5&B/ &5&B(1

23

22

20

19

18

17

16

Table 13 Number of bits reserved for RX address + CRC setting.

Bit 23 – 18:

ADDR_W: Number of bits reserved for RX address in ShockBurst™

packages.

NOTE:

Maximum number of address bits is 40 (5 bytes). Values over 40 in

ADDR_W are not valid.

Bit 17:

CRC_L:

CRC length to be calculated by nRF2401 in ShockBurst™.

Logic 0: 8 bit CRC

Logic 1: 16 bit CRC

Bit: 16:

CRC_EN:

Enables on-chip CRC generation (TX) and verification (RX).

Logic 0: On-chip CRC generation/checking disabled

Logic 1: On-chip CRC generation/checking enabled

NOTE:

An 8 bit CRC will increase the number of payload bits possible in each

ShockBurst™ data packet, but will also reduce the system integrity.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

*HQHUDOꢄGHYLFHꢄFRQILJXUDWLRQꢆ

This section of the configuration word handles RF and device related parameters.

Modes:

5;ꢀB(1

&0

14

5)'5B6%

;2B)

5)B3:5

15

13

12

11

10

9

8

Table 14 RF operational settings.

Bit 15:

RX2_EN:

Logic 0: One channel receive

Logic 1: Two channels receive

NOTE:

In two channels receive, the nRF2401 receives on two, separate

frequency channels simultaneously. The frequency of receive channel

1 is set in the configuration word B[7-1], receive channel 2 is always 8

channels (8 MHz) above receive channel 1.

Bit 14:

Communication Mode:

Logic 0: nRF2401 operates in direct mode.

Logic 1: nRF2401 operates in ShockBurst™ mode

Bit 13:

RF Data Rate:

NOTE:

Logic 0: 250 kbps

Logic 1: 1 Mbps

Utilizing 250 kbps instead of 1Mbps will improve the receiver

sensitivity by 10 dB. 1Mbps requires 16MHz crystal.

Bit 12-10:

XO_F:

Selects the nRF2401 crystal frequency to be used:

;2ꢄ)5(48(1&<ꢄ6(/(&7,21

'ꢃꢀ

'ꢃꢃ

'ꢃꢂ

&U\VWDOꢄ)UHTXHQF\ꢄ>0+]@

0

1

0

1

0

1

0

1

0

4

8

12

16

20

Table 15 Crystal frequency setting.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

Bit 9-8:

RF_PWR: Sets nRF2401 RF output power in transmit mode:

5)ꢄ287387ꢄ32:(5

'ꢈ

0

'ꢉ

0

1

3ꢄ>G%P@

-20

-10

-5

1

0

1

0

Table 16 RF output power setting.

5)ꢄFKDQQHOꢄꢇꢄGLUHFWLRQ

5)B&+ꢊ

5;(1

7

6

5

4

3

2

1

0

Table 17 Frequency channel + RX / TX setting.

Bit 7 – 1:

RF_CH#: Sets the frequency channel the nRF2401 operates on.

The channel frequency in WUDQVPLW is given by:

&KDQQHO = 2400 0+] + 5) _&+ # 1.0 0+]

RF_CH #: between 2400MHz and 2527MHz may be set.

The channel frequency in GDWDꢀFKDQQHOꢀꢁ is given by:

&KDQQHO = 2400 0+] + 5) _&+ # 1.0 0+] (Receive at PIN#8)

RF_CH #: between 2400MHz and 2524MHz may be set.

NOTE:

The channels above 83 can only be utilized in certain territories (ex: Japan)

The channel frequency in GDWDꢀFKDQQHOꢀꢂ is given by:

&KDQQHO = 2400 0+] + 5) _&+ # 1.0 0+] +8MHz (Receive at PIN#4)

RF_CH #: between 2408MHz and 2524MHz may be set.

Bit 0:

Set active mode:

Logic 0: transmit mode

Logic 1: receive mode

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

'$7$ꢄ3$&.$*(ꢄ'(6&5,37,21

PRE-AMBLE

ADDRESS

PAYLOAD

CRC

Figure 11 Data Package Diagram

The data packet for both ShockBurst™ mode and direct mode communication is

divided into 4 sections. These are:

•

The preamble field is required in ShockBurst™ and Direct modes

Preamble is 8 (or 4) bits in length and is dependent of the first data bit in

direct mode.

ꢃꢅꢀ 35($0%/(

PREAMBLE

01010101

1^stADDR-BIT

0

1

10101010

•

Preamble is automatically added to the data packet in ShockBurst™ and

thereby gives extra space for payload.

In ShockBurst™ mode the preamble is stripped from the received output

data, in direct mode the preamble is transparent to the output data.

•

The address field is required in ShockBurst™ mode.

8 to 40 bits length.

Address automatically removed from received packet in ShockBurst™

mode. In Direct mode MCU must handle address.

The data to be transmitted

ꢀꢀ $''5(66

ꢋꢀ 3$</2$'

•

In Shock-Burst mode payload size is 256 bits minus the following:

(Address: 8 to 40 bits. + CRC 8 or 16 bits).

•

In Direct mode the payload size is defined by 1Mbps for 4ms: 4000 bits

minus the following: (Preamble: 8 (or 4) bits. + Address: 8 to 40 bits. +

CRC: 0, 8 or 16 bits).

The CRC is optional in ShockBurst™ mode,

and is not used in Direct mode.

ꢁꢀ &5&

•

8 or 16 bits length

The CRC is stripped from the received output data.

Table 18 Data package description

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

,03257$17ꢄ7,0,1*ꢄ'$7$

The following timing applies for operation of nRF2401.

Q5)ꢀꢁꢂꢃꢄ7LPLQJꢄ,QIRUPDWLRQ

Q5)ꢀꢁꢂꢃꢄWLPLQJ

PWR_DWN Î ST_BY mode

0D[ꢅ

3ms

0LQꢅ

1DPH

Tpd2sby

PWR_DWNÎ Active mode (RX/TX)

ST_BY Î TX ShockBurst™

ST_BY Î TX Direct Mode

ST_BY Î RX mode

Minimum delay from CS to data.

Minimum delay from CE to data.

Minimum delay from DR1/2 to clk.

Maximum delay from clk to data.

Delay between edges

3ms

Tpd2a

Tsby2txSB

Tsby2txDM

Tsby2rx

Tcs2data

Tce2data

Tdr2clk

Tclk2data

Td

Ts

Th

Tfd

Thmin

Tsdm

195µs

202µs

5µs

50ns

500ns

1/data rate

500ns

Setup time

Hold time

Delay to finish internal GFSK data

Minimum input clock high

Set-up of data in Direct Mode

Minimum clock high in Direct Mode

Minimum clock low in Direct Mode

300ns

230ns

Thdm

Tldm

Table 19 Switching times for nRF2401

When the nRF2401 is in power down it must always settle in stand-by (Tpd2sby)

before it can enter configuration or one of the active modes.

PWR_UP

CS

CE

CLK1

DATA

Tpd2sby

Figure 12 Timing diagram for power down (or VDD off) to stand by mode

for nRF2401.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

PWR_UP

CS

CE

CLK1

DATA

Tpd2a

Figure 13 Power down (or VDD off) to active mode

Note that the configuration word will be lost when VDD is turned off and that the

device then must be configured before going to one of the active modes. If the device

is configured one can go directly from power down to the wanted active mode.

1RWHꢆ

CE and CS may not be high at the same time. Setting one or the other decides

whether configuration or active mode is entered.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

&RQILJXUDWLRQꢄPRGHꢄWLPLQJ

When one or more of the bits in the configuration word needs to be changed the

following timing apply.

PWR_UP

CS

CE

CLK1

DATA

Td

CS

CE

Thmin

CLK1

MSB

DATA

Ts Th

Figure 14 Timing diagram for configuration of nRF2401

If configuration mode is entered from power down, CS can be set high after Tpd2sby

as shown in Figure 12.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

6KRFN%XUVWꢄ0RGHꢄWLPLQJ

6KRFN%XUVWꢄ7;ꢆ

PWR_UP

CS

CE

CLK1

DATA

.

ANT1/ANT2

Toa

T

sby2txSB

Td

CS

T_Hmin

CE

CLK1

DATA

Ts

Th

Figure 15 Timing of ShockBurst™ in TX

The package length and the data rate give the delay Toa (time on air), as shown in the

equation.

7 =1/ GDWDUDWH (#GDWDELWV +1)

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

6KRFN%XUVWꢄ5;ꢆ

PWR_UP

CS

CE

DR1/2

CLK1/2

DATA/DOUT2

.

ANT1/ANT2

Td

Tsby2rx

CE

DR1/2

T_hmin

CLK1/2

DATA/

DOUT2

Td

Figure 16 Timing of ShockBurst™ in RX

The CE may be kept high during downloading of data, but the cost is higher current

consumption (18mA) and the benefit is no start-up time (200µs) after the DR1 goes

low.

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

'LUHFWꢄ0RGH

'LUHFWꢄ0RGHꢄ7;ꢆ

PWR_UP

CS

CE

CLK1

DATA

ANT1/ANT2

Td

ToaDM

Tfd

T

sby2txDM

Figure 17 Timing of direct mode TX

In TX direct mode the input data will be sampled by nRF2401 and therefore no clock

is needed. The clock must be stable at low level during transmission due to noise

considerations. The exact delay T_sby2txDMis given by the equation:

7

= 194XV +1/ )

14 + 2.25XV

2

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

'LUHFWꢄ0RGHꢄ5;ꢆ

PWR_UP

CS

CE

CLK1/2

DATA/DOUT2

ANT1/ANT2

Td

Tsby2rx

CE

T_hdmT_ldm

CLK1/2

DATA/DOUT2

Tsdm

Figure 18 Timing of direct mode RX

Tsby2rx describes the delay from the positive edge of CE to the start detection of

(demodulated) incoming data.

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Page 30 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

ꢄ3(5,3+(5$/ꢄ5)ꢄ,1)250$7,21

$QWHQQDꢄRXWSXW

The ANT1 & ANT2 output pins provide a balanced RF output to the antenna. The

pins must have a DC path to VDD, either via a RF choke or via the center point in a

dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be

in the range 200-700Ω. A de-embedded load impedance i.e. impedance seen at drain

terminals of the output transistors of 400Ω is recommended for maximum output

power (0dBm). Lower load impedance (for instance 50 Ω) can be obtained by fitting a

simple matching network.

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3RZHUꢄVHWWLQJꢄELWVꢄRI

5)ꢄRXWSXWꢄSRZHU

'&ꢄFXUUHQW

FRQILJXULQJꢄZRUG

FRQVXPSWLRQ

11

10

01

00

0 dBm ±3dB

-5 dBm ±3dB

-10 dBm ±3dB

-20 dBm ±3dB

13.0 mA

10.5 mA

9.4 mA

8.8 mA

Conditions: VDD = 3.0V, VSS = 0V, T_A= 27ºC, Load impedance = 400 Ω.

Table 20 RF output power setting for the nRF2401.

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Tolerance includes initially accuracy and tolerance over temperature and aging.

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&

(65

150 Ω

100 Ω

&

7ROHUDQFH

±30ppm

4

8

12

16

20

12pF

7.0pF

Table 21 Crystal specification of the nRF2401

To achieve a crystal oscillator solution with low power consumption and fast start-up

time, it is recommended to specify the crystal with a low value of crystal load

capacitance. Specifying C_L=12pF is OK, but it is possible to use up to 16pF.

Specifying a lower value of crystal parallel equivalent capacitance, Co is also good,

but this can increase the price of the crystal itself. Typically Co=1.5pF at a crystal

specified for Co_max=7.0pF.

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Page 31 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

3&%ꢄOD\RXWꢄDQGꢄGHFRXSOLQJꢄJXLGHOLQHV

A well-designed PCB is necessary to achieve good RF performance. Keep in mind

that a poor layout may lead to loss of performance, or even functionality, if due care is

not taken. A fully qualified RF-layout for the nRF2401 and its surrounding

components, including matching networks, can be downloaded from ZZZꢅQYOVLꢅQR.

A PCB with a minimum of two layers including a ground plane is recommended for

optimum performance. The nRF2401 DC supply voltage should be decoupled as close

as possible to the VDD pins with high performance RF capacitors, see Table 22. It is

preferable to mount a large surface mount capacitor (e.g. 4.7µF tantalum) in parallel

with the smaller value capacitors. The nRF2401 supply voltage should be filtered and

routed separately from the supply voltages of any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD

connections and VDD bypass capacitors must be connected as close as possible to the

nRF2401 IC. For a PCB with a topside RF ground plane, the VSS pins should be

connected directly to the ground plane. For a PCB with a bottom ground plane, the

best technique is to have via holes as close as possible to the VSS pads. One via hole

should be used for each VSS pin.

Full swing digital data or control signals should not be routed close to the crystal or

the power supply lines.

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March 2003

Page 32 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

$33/,&$7,21ꢄ(;$03/(

Q5)ꢀꢁꢂꢃꢄZLWKꢄVLQJOHꢄHQGHGꢄPDWFKLQJꢄQHWZRUN

xxx

VDD

C6

10nF

C5

1nF

R2

22K

PWR_UP

CE

DR2

CLK2

DOUT2

CS

C9

1

2

3

4

5

6

18

17

16

15

14

13

CE

AVSS

nRF2401

DR2

CLK2

DOUT2

CS

AVDD

VSS_PA

ANT2

ANT1

VDD_PA

1.0pF

C8

L1

3.6nH

DR1

CLK1

DATA

xxx

C4

2.2nF

C3

22pF

RF I/O

1.0pF

L2

22nH

U1

nRF2401

QFN24/5X5

X1

C7

33nF

16 MHz

R1

1M

xxx

C1

22pF

C2

22pF

Figure 19 nRF2401 schematic for RF layouts with single end 50Ω antenna

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Capacitor ceramic, 50V, NPO

Capacitor ceramic, 50V, X7R

Resistor

6L]H

0603

9DOXH

22

2.2

1.0

10

33

1.0

7ROHUDQFH

±5%

8QLWV

pF

nF

MΩ

KΩ

C1

C2

C3

C4

C5

C6

C7

R1

R2

U1

X1

±5%

±10%

±1%

Resistor

22

nRF2401

16¹⁾

±1%

Q5)ꢀꢁꢂꢃ transceiver

Crystal, CL = 12pF,

ESR < 100 ohm

QFN24 / 5x5

LxWxH =

4.0x2.5x0.8

+/- 30 ppm

MHz

L1

L2

C8

C9

Inductor, wire wound ²⁾

Ceramic capacitor, 50V, NP0

0603

3.6

22

1.0

± 5%

± 0.25 pF

nH

pF

Table 22 Recommended components (BOM) in nRF2401 withꢄantenna matching

network

¹⁾Q5)ꢀꢁꢂꢃ can operate at several crystal frequencies, please refer to page 31.

²⁾Wire wound inductors are recommended, other can be used if their self-resonant frequency (SFR) is

> 2.7 GHz

Nordic VLSI ASA

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March 2003

Page 33 of 37

PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

3&%ꢄOD\RXWꢄH[DPSOH

Figure 20 shows a PCB layout example for the application schematic in Figure 19.

A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane

on the bottom layer. Additionally, there are ground areas on the component side of the

board to ensure sufficient grounding of critical components. A large number of via

holes connect the top layer ground areas to the bottom layer ground plane.

No components in bottom layer

Top silk screen

Top view

Bottom view

Figure 20 nRF2401 RF layout with single ended connection to 50Ω antenna and 0603

size passive components

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Phone +4772898900

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Fax +4772898989

March 2003

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

ꢄ'(),1,7,216

'DWDꢄVKHHWꢄVWDWXV

Objective product specification This datasheet contains target specifications for product development.

Preliminary product

specification

This datasheet contains preliminary data; supplementary data may be

published from Nordic VLSI ASA later.

Product specification

This datasheet contains final product specifications. Nordic VLSI ASA

reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

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Stress above one or more of the limiting values may cause permanent damage to the device. These are stress

ratings only and operation of the device at these or at any other conditions above those given in the

Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may

affect device reliability.

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Where application information is given, it is advisory and does not form part of the specification.

Table 23. Definitions

Nordic VLSI ASA reserves the right to make changes without further notice to the

product to improve reliability, function or design. Nordic VLSI does not assume any

liability arising out of the application or use of any product or circuits described

herein.

/,)(ꢄ6833257ꢄ$33/,&$7,216

These products are not designed for use in life support appliances, devices, or systems

where malfunction of these products can reasonably be expected to result in personal

injury. Nordic VLSI ASA customers using or selling these products for use in such

applications do so at their own risk and agree to fully indemnify Nordic VLSI ASA

for any damages resulting from such improper use or sale.

Preliminary Product Specification: Revision Date: 27.03.2003.

Datasheet order code: 270303-nRF2401.

written permission of the copyright holder.

Nordic VLSI ASA

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

<285ꢄ127(6

Nordic VLSI ASA

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March 2003

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PRODUCT SPECIFICATION

Q5)ꢀꢁꢂꢃꢄꢄ6LQJOHꢄ&KLSꢄꢀꢅꢁꢄ*+]ꢄ5DGLRꢄ7UDQVFHLYHU

1RUGLFꢄ9/6,ꢄ$6$ꢄ±ꢄ:RUOGꢄ:LGHꢄ'LVWULEXWRUV

)RUꢄ<RXUꢄQHDUHVWꢄGHDOHUꢌꢄSOHDVHꢄVHHꢄKWWSꢆꢍꢍZZZꢅQYOVLꢅQR

0DLQꢄ2IILFHꢆ

Vestre Rosten 81, N-7075 Tiller, Norway

Phone: +47 72 89 89 00, Fax: +47 72 89 89 89

9LVLWꢄWKHꢄ1RUGLFꢄ9/6,ꢄ$6$ꢄZHEVLWHꢄDWꢄKWWSꢆꢍꢍZZZꢅQYOVLꢅQR

Nordic VLSI ASA

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Page 37 of 37


型号：	NRF2401
厂家：	ETC
描述：	Single chip 2.4 GHz Transceiver 单芯片的2.4 GHz收发器
文件：	总37页 (文件大小：849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NRF2401 [ETC]

相关型号：

NRF2401-EVKIT

NRF2401A

NRF2401A-EVKIT

NRF2401AG

NRF2401IC

NRF2402

NRF2402G

NRF24E2

NRF24L01

NRF24L01+

NRF24L01-EVKIT

NRF24L01IC