NRF9E5-EVKIT868 [ETC]
433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC; 868分之433 / 915MHz频段射频收发器与嵌入式8051兼容微控制器和4输入， 10位ADC
| 型号： | NRF9E5-EVKIT868 |
| 厂家： | 
ETC |
| 描述： | 433/868/915MHz RF Transceiver with Embedded 8051 Compatible Microcontroller and 4 Input, 10 Bit ADC |
| 文件： | 总104页 (文件大小：1540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRODUCT SPECIFICATION
433/868/915MHz RF Transceiver with
Embedded 8051 Compatible
Microcontroller and 4 Input, 10 Bit ADC
nRF9E5
FEATURES
APPLICATIONS
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
nRF905 433/868/915 MHz transceiver
8051 compatible microcontroller
4 input, 10bit 80ksps ADC
Single 1.9V to 3.6V supply
·
Sports and leisure
equipment
·
Alarm and security
system
Small 32 pin QFN (5x5 mm) package
Extremely low cost Bill of Material (BOM)
Internal VDD monitoring
2.5mA standby with wakeup on timer or external pin
Adjustable output power up to 10dBm
Channel switching time less than 650ms
Low TX supply current, typical 11mA @-10dBm
Low RX supply current typical 12.5mA peak
Low MCU supply current, typ. 1mA at 4MHz @3volt
Suitable for frequency hopping
·
·
·
·
·
·
·
Industrial sensors
Remote control
Surveillance
Automotive
Telemetry
Keyless entry
Toys
Carrier Detect for “listen before transmit protocol”
GENERAL DESCRIPTION
nRF9E5 is a true single chip system with fully integrated RF transceiver, 8051
compatible microcontroller and a 4 input 10bit 80ksps AD converter. The transceiver of
the system supports all the features available in the nRF905 chip including
ShockburstTM, which automatically handles preamble, address and CRC. The circuit has
embedded voltage regulators, which provides maximum noise immunity and allows
operation on a single 1.9V to 3.6V supply. nRF9E5 is compatible with FCC standard
CFR47 part 15 and ETSI EN 300 220-1.
QUICK REFERENCE DATA
Parameter
Value
1.9
-40 to +85
11
Unit
V
Minimum supply voltage
Temperature range
Supply current in transmit @ -10dBm output power
Supply current in receive mode
°C
mA
mA
mA
mA
12.5
1
0.9
Supply current for m-controller 4MHz @ 3volt
Supply current for ADC
Maximum transmit output power
Transmitted data rate (Manchester-encoder embedded)
Sensitivity
10
100
-100
2.5
dBm
kbps
dBm
mA
Supply current in power down mode
Table 1 nRF9E5 quick reference data.
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
ORDERING INFORMATION
Type number
nRF9E5 IC
Description
32L QFN 5x5 mm
Version
-
nRF9E5-EVKIT 433
nRF9E5-EVKIT 868/915
Evaluation kit 433MHz
Evaluation kit 868/915MHz
1.0
1.0
Table 2 nRF9E5 ordering information.
BLOCK DIAGRAM
AIN3 (26)
AIN2 (27)
AIN1 (28)
AIN0 (29)
4k byte
RAM
Boot
loader
256 byte
RAM
ANT1 (20)
7-channel interrupt
UART0
ANT2 (21)
VDD_PA (19)
nRF905
433/868/
915 MHz
Radio
AREF (30)
Timer 0
A/D
converter
Timer 1
IREF (23)
Timer 2
BIAS
Tranceiver
CPU
8051
XC2 (15)
compatible
XTAL
oscillator
Microcontroller
XC1 (14)
VSS (5)
VSS (16)
VSS (18)
Low power
RC
Oscillator
WATCH-
DOG
RTC
timer
PWM
SPI
Power mgmt
Reset
Regulators
VSS (22)
VSS (24)
VDD (4)
VDD (17)
VDD (25)
8. Ch programmable
Wakeup
Port logic
25320 EEPROM
Figure 1 nRF9E5 block diagram.
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
TABLE OF CONTENTS
1
Architectural Overview................................................................................................. 5
1.1 Microcontroller......................................................................................................... 5
1.2 PWM....................................................................................................................... 6
1.3 SPI.......................................................................................................................... 6
1.4 Port Logic ................................................................................................................ 6
1.5 Power Management.................................................................................................. 7
1.6 LF Clock, RTC Wakeup Timer, GPIO Wakeup and Watchdog.................................... 7
1.7 XTAL Oscillator....................................................................................................... 7
1.8 AD Converter .......................................................................................................... 8
1.9 Radio Transceiver..................................................................................................... 8
Eletrical Specification................................................................................................... 9
2.1 Detailed Current Information................................................................................... 10
Pin Assignment........................................................................................................... 11
Pin Function............................................................................................................... 12
System Clock............................................................................................................. 13
Digital I/O Ports......................................................................................................... 14
6.1 I/O Port Behavior During RESET............................................................................ 14
6.2 Port 0 (P0) ............................................................................................................. 14
6.3 Port 1 (P1 or SPI port) ............................................................................................ 15
Analog Interface......................................................................................................... 17
7.1 Crystal Specification............................................................................................... 17
7.2 Antenna Output...................................................................................................... 17
7.3 ADC Inputs............................................................................................................ 17
7.4 Current Reference .................................................................................................. 17
7.5 Digital Power De-Coupling ..................................................................................... 18
Internal Interface AD Converter and Transceiver.......................................................... 19
8.1 P2 - Radio General Purpose IO Port......................................................................... 19
Tranceiver Subsystem (nRF905).................................................................................. 21
9.1 RF Modes of Operation........................................................................................... 21
9.2 nRF ShockBurst™ Mode ........................................................................................ 21
9.3 Standby Mode ........................................................................................................ 26
9.4 Output Power Adjustment ....................................................................................... 26
9.5 Modulation............................................................................................................. 26
9.6 Output Frequency................................................................................................... 27
9.7 Carrier Detect......................................................................................................... 27
9.8 Address Match....................................................................................................... 28
9.9 Data Ready ............................................................................................................ 28
2
3
4
5
6
7
8
9
9.10
9.11
Auto Retransmit ................................................................................................. 28
RX Reduced Power Mode................................................................................... 28
10 AD Converter subsystem............................................................................................ 29
10.1 AD Converter .................................................................................................... 29
10.2 AD Converter Usage .......................................................................................... 30
10.3 AD Converter Sampling and Timing.................................................................... 31
11 Tranceiver and AD Converter Configuration................................................................ 33
11.1 Internal SPI Register Configuration...................................................................... 33
11.2 SPI – Instruction Set........................................................................................... 35
11.3 SPI Timing......................................................................................................... 36
11.4 RF Configuration – Register Description.............................................................. 37
11.5 ADC - Configuration Register Description ........................................................... 38
11.6 Status-Register Description................................................................................. 38
11.7 RF - Register Contents........................................................................................ 39
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nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
11.8 ADC Configuration Register Contents ................................................................. 40
11.9 ADC Data Register Contents............................................................................... 40
11.10 Status Register Contents ..................................................................................... 40
12 Tranceiver Subsytem Timing....................................................................................... 41
12.1 Device Switching Times ..................................................................................... 41
12.2 ShockBurstTM TX Timing.................................................................................... 41
12.3 ShockBurstTM RX Timing.................................................................................... 42
13 SPI............................................................................................................................ 43
14 PWM......................................................................................................................... 44
15 Interrupts ................................................................................................................... 45
15.1 Interrupt SFRs.................................................................................................... 45
15.2 Interrupt Processing............................................................................................ 48
15.3 Interrupt Masking ............................................................................................... 48
15.4 Interrupt Priorities .............................................................................................. 48
15.5 Interrupt Sampling.............................................................................................. 49
15.6 Interrupt Latency................................................................................................ 50
15.7 Interrupt Latency from Power Down State. .......................................................... 50
15.8 Single-Step Operation......................................................................................... 50
16 LF Clock Wakeup Functions and Watchdog................................................................. 51
16.1 The LF Clock..................................................................................................... 51
16.2 Tick Calibration.................................................................................................. 51
16.3 RTC Wakeup Timer............................................................................................ 52
16.4 Programmable GPIO Wakeup Function................................................................ 52
16.5 Watchdog........................................................................................................... 53
16.6 Programming Interface to Watchdog and Wakeup Functions ................................. 53
16.7 Reset................................................................................................................. 55
17 Power Saving Modes .................................................................................................. 57
17.1 Standard 8051 Power Saving Modes.................................................................... 57
17.2 Additional Power Down Modes........................................................................... 58
18 Microcontroller........................................................................................................... 60
18.1 Memory Organization......................................................................................... 60
18.2 Program Format in External EEPROM................................................................ 61
18.3 Instruction Set.................................................................................................... 62
18.4 Instruction Timing .............................................................................................. 68
18.5 Dual Data Pointers.............................................................................................. 68
18.6 Special Function Registers .................................................................................. 69
18.7 SFR Registers Unique to nRF9E5........................................................................ 73
18.8 Timers/Counters................................................................................................. 74
18.9 Serial Interface................................................................................................... 81
19 Package Outline.......................................................................................................... 92
20 PCB Layout and Decoupling Guidelines ...................................................................... 93
21 Application Examples................................................................................................. 94
21.1 Differential Connection to a Loop Antenna .......................................................... 94
21.2 PCB Layout Example, Differential Connection to a Loop Antenna ........................ 96
21.3 Single Ended Connection to 50W Antenna............................................................ 97
21.4 PCB Layout Example, Single Ended Connection to 50W Antenna ......................... 99
21.5 Configure the Chip as nRF905............................................................................. 99
22 Absolute Maximum Ratings .......................................................................................100
23 Glossery of Terms .....................................................................................................101
24 Definitions ................................................................................................................102
25 Your Notes ...............................................................................................................103
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
1 ARCHITECTURAL OVERVIEW
This section will give a brief overview of each of the blocks in the block diagram in
Figure 1.
1.1 Microcontroller
The nRF9E5 microcontroller is instruction set compatible with the industry standard
8051. Instruction timing is slightly different from the industry standard, typically each
instruction will use from 4 to 20 clock cycles, compared with 12 to 48 for the
“standard”. The interrupt controller is extended to support 5 additional interrupt sources;
ADC, SPI, 2 for the radio and a wakeup function. There are also 3 timers that are 8052
compatible, plus some extensions, in the microcontroller core. An 8051 compatible
UART that can use timer1 or timer2 for baud rate generation in the traditional
asynchronous modes is included. The CPU is equipped with 2 data pointers to facilitate
easier moving of data in the XRAM area, which is a common 8051 extension. The
microcontroller clock is derived from the crystal oscillator.
1.1.1 Memory Configuration
The microcontroller has a 256-byte data ram (8052 compatible, with the upper half only
addressable by register indirect addressing). A small ROM of 512 bytes contains a
bootstrap loader that is executed automatically after power on reset or if initiated by
software later. The user program is normally loaded into a 4k byte RAM1 from an
external serial EEPROM by the bootstrap loader. The 4k byte RAM may also (partially)
be used for data storage in some applications.
1.1.2 Boot EEPROM/FLASH
The program code for the device must be loaded from an external non-volatile memory.
The default boot loader expects this to be a “generic 25320” EEPROM with SPI
interface. These memories are available from several vendors with supply ranges down
to 1.8V. The SPI interface uses the pins MISO (from EEPROM SDO), SCK (to
EEPROM SCK), MOSI (to EEPROM SDI) and EECSN (to EEPROM CSN). When the
boot is completed, the MISO (P1.2), MOSI (P1.0) and SCK (P1.1) pins may be used for
other purposes such as other SPI devices or GPIO (General Purpose Input Output).
1.1.3 Register Map
The SFR (Special Function Registers) control several of the features of the nRF9E5.
Most of the nRF9E5 SFRs are identical to the standard 8051 SFRs. However, there are
additional SFRs that control features that are not available in the standard 8051.
The SFR map is shown in Table 3. The registers with grey background are registers with
industry standard 8051 behavior. Note that the function of P0, P1 and P2 are somewhat
different from the “standard” even if the conventional addresses (0x80, 0x90 and 0xA0)
are used.
1
Optionally this 4k block of memory can be configured as 2k mask ROM and 2k RAM or 4 k mask ROM
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
X000
EIP
X001
X010
X011
X100
X101
X110
HWREV
X111
F8
F0
E8
E0
D8
D0
C8
C0
B8
B
EIE
ACC
EICON
PSW
T2CON
RCAP2L RCAP2H
TL2
TH2
IP
CKLF
CON
RSTREA
S
PWM
CON
SPI
_DATA
PWM
DUTY
SPI
SPI
CLK
REGX
_LSB
TICK_
DV
REGX
_CTRL
CK_
CTRL
TEST_
MODE
B0
A8
_CTRL
REGX
_MSB
IE
P2
SCON
P1
A0
98
90
88
80
SBUF
EXIF
TMOD
SP
MPAGE P0_DRV
P0_DIR
TH0
P0_ALT
TH1
P1_DIR
P1_ALT
TCON
P0
TL0
TL1
CKCON SPC_FNC
DPS PCON
DPL0
DPH0
DPL1
DPH1
Table 3 SFR Register map.
1.2 PWM
The nRF9E5 has one programmable PWM (Pulse-Width Modulation) output, which is
the alternate function of P0.7. The resolution of the PWM is software programmable to
6, 7 or 8 bits. The frequency of the PWM signal is programmable via a 6 bit prescaler
from the XTAL oscillator. The duty cycle is programmable between 0% and 100% via
one 8-bit register.
1.3 SPI
nRF9E5 features a simple single buffered SPI (Serial Programmable Interface) master.
The 3 data lines of the SPI bus (MISO, SCK and MOSI) are multiplexed (by writing to
register SPI_CTRL) between the GPIO pins (lower 3 bits of P1) and the RF transceiver
and AD subsystems. The SPI hardware does not generate any chip select signal. The
programmer will typically use GPIO bits (from port P0) to act as chip selects for one or
more external SPI devices. The EECSN pin is a general purpose IO dedicated as chip
select for the boot EEPROM. When the SPI interfaces the RF transceiver, the chip
selects are available in an internal GPIO port, P2.
1.4 Port Logic
The device has 8 general-purpose bi-directional pins (the P0 port). Additionally the 4
SPI data pins may be used as general purpose IO (the P1). Most of the GPIO pins can
be used for multiple purposes under program control. The alternate functions include
two external interrupts, UART RXD and TXD, a SPI master port, three enable/count
signals for the timers and the PWM output and a slow programmable timer. Each pin in
the P0 port can be programmed for high sink or source current.
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1.5 Power Management
The nRF9E5 can be placed into several low power modes under program control, and
also the ADC and RF subsystems can be turned on or off under program control. The
CPU will stop, but all RAM’s and registers maintain their values. The watchdog, RTC
(Real Time Clock) wakeup timer and the GPIO wakeup function are always active
during power down. The current consumption is typically 2.5µA when running with the
crystal oscillator off.
The device can exit the power down modes by an external pin, an event on any of the P0
GPIO pins, by the wakeup timer if enabled or by a watchdog reset.
1.6 LF Clock, RTC Wakeup Timer, GPIO Wakeup and Watchdog
The nRF9E5 contains an internal low frequency clock CKLF that is always on. When
the crystal oscillator clocks the circuit, the CKLF is a 4kHz clock derived from the
crystal oscillator. When no crystal oscillator clock is available, the CKLF is a low power
RC oscillator that cannot be disabled, so it will run continuously as long as VDD =
1.8V. The RTC Wakeup timer, the GPIO wakeup and watchdog all run on the CKLF to
ensure these vital functions will work during all power down modes.
RTC Wakeup timer is a 24 bit programmable down counter and the Watchdog is a 16 bit
programmable down counter. The resolution of the watchdog and wakeup timer is
programmable (with prescaler TICK_DV) from approximately 300µs to approximately
80ms. By default the resolution is 1ms. The wakeup timer can be started and stopped by
user software. The watchdog is disabled after a reset, but if activated it cannot be
disabled again, except by another reset. An RTC Wakeup timer timeout also provides a
programmable pulse (GTIMER) that can be an output on a GPIO pin.
The GPIO wakeup function lets the software enable wakeup on one or more pins from
the P0 GPIO port. The edge sensitivity (rising, falling or both) and de-bouncing filter is
individually programmable for each pin.
1.7 XTAL Oscillator
The microcontroller, AD converter and transceiver run on the same crystal oscillator
generated clock. A range of crystals frequencies from 4 to 20 MHz may be utilized. For
details, please see chapter 7.1 on page 17. The oscillator may be started and stopped as
requested by software.
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1.8 AD Converter
The nRF9E5 AD converter has up to 10-bit dynamic range and linearity with a
conversion rate of 80 ksps used at the Nyquist rate. The reference for the AD converter
is software selectable between the AREF input and an internal 1.22V bandgap reference.
The converter has 5 inputs selectable by software. Selecting one of the inputs 0 to 3 will
convert the voltage on the respective AIN0 to AIN3 pin. Input 4 enables software to
monitor the nRF9E5 supply voltage by converting an internal input that is VDD/3 with
the 1.22V internal reference selected. The AD converter is typically used in a start/stop
mode. The sampling time is then under software control. The converter is by default
configured as 10 bits. For special requirements, the AD converter can be configured by
software to perform 6, 8 or 12 bit conversions. The converter may also be used in
differential mode with AIN0 used as negative input and one of the other 3 external
inputs used as noninverting input.
1.9 Radio Transceiver
The transceiver part of the circuit has identical functionality to the nRF905 single chip
RF transceiver. It is accessed through an internal parallel port and / or an internal SPI.
The data ready, carrier-detect and address match signals can be programmed as
interrupts to the microcontroller or polled via a GPIO port.
The nRF905 is a radio transceiver for the 433/868/915 MHz ISM bands. The transceiver
consists of a fully integrated frequency synthesizer, a power amplifier, a modulator and
a receiver unit. Output power and frequency channels and other RF parameters are easily
programmable by use of the on chip SPI interface to the nRF905 core. RF current
consumption is only 11 mA in TX mode (output power -10dBm) and 12.5 mA in RX
mode. For power saving the transceiver can be turned on / off under software control.
This document should be read in conjunction with the nRF905 datasheet.
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
2 ELETRICAL SPECIFICATION
Symbol
Parameter (condition)
Notes
Min.
Typ.
Max.
Units
Operating conditions
Supply voltage
Operating temperature
VDD
TEMP
1.9
-40
3.0
27
3.6
85
V
ºC
Digital input pin
HIGH level input voltage
LOW level input voltage
VIH
VIL
VDD-0.3
VSS
VDD
0.3
V
V
Digital output pin
HIGH level output voltage (IOH=-0.5mA)
LOW level output voltage (IOL=0.5mA)
VOH
VOL
VDD-0.3
VSS
VDD
0.3
V
V
General electrical specification
IPD
Supply current in power down mode
2.5
1
mA
General microcontroller conditions
Supply current @4MHz @3V
High drive sink current for P06, P04, P02 and
P00 @ VOL = 0.4V
High drive source current for P07, P05, P03
and P01 @ VOH = VDD-0.4V
Low power RC oscillator frequency
IVDD_MCU
IOL_HD
mA
mA
1)
1)
10
IOH_HD
fLP_OSC
10
5.5
mA
KHz
1
General RF conditions
fOP
fXTAL
Df
RGFSK
fCH_433
fCH_868
Operating frequency
Crystal frequency
2)
3)
430
4
±42
928
20
±58
MHz
MHz
kHz
kbps
kHz
kHz
Frequency deviation
GFSK data rate, Manchester-encoded
Channel spacing @ 433MHz
±50
100
100
200
Channel spacing @ 868 and 915 MHz
Transmitter operation
PRF10
PRF6
PRF-2
PRF-10
PBW
Output power 10dBm setting
4)
4)
4)
4)
7
3
-6
-14
10
6
-2
-10
190
-27
-54
30
11
9
2
dBm
dBm
dBm
dBm
kHz
dBc
dBc
mA
Output power 6dBm setting
Output power –2dBm setting
Output power -10dBm setting
20dB bandwidth for modulated carrier
1st adjacent channel transmit power
2nd adjacent channel transmit power
-6
PRF1
PRF2
5)
5)
ITX10dBm Supply current @ 10dBm output power
ITX-14dBm Supply current @ -10dBm output power
11
mA
Receiver operation
IRX
Supply current in receive mode
12.5
-100
mA
dBm
dBm
dB
dB
dB
RXSENS Sensitivity at 0.1%BER
RXMAX Maximum received signal
0
C/ICO
C/I1ST
C/I2ND
C/IIM
C/I Co-channel
6)
6)
6)
6)
13
-7
-16
-30
1st adjacent channel selectivity C/I 200kHz
2nd adjacent channel selectivity C/I 400kHz
Image rejection
dB
Table 4 nRF9E5 electrical specification.
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Symbol Parameter (condition)
ADC operation
Notes
Min.
Typ.
Max.
Units
DNL
Differential Nonlinearity fIN = 0.9991 kHz
Integral Nonlinearity fIN = 0.9991 kHz
Signal to Noise Ratio (DC input)
Midscale offset
LSB
LSB
dBFS
%FS
%FS
dBFS
±0.5
±0.75
59
± 1
±1
58
INL
SNR
VOS
Gain Error
eG
SNR
Signal to Noise Ratio (without harmonics)
fIN = 10 kHz
53
SFDR
VBG
Spurious Free Dynamic Range fIN = 10 kHz
Internal reference
Internal reference voltage drift
Reference voltage input (external ref)
Conversion rate
65
1.22
100
dB
V
ppm/°C
V
ksps
mA
ms
1.1
0.8
1.3
VFS
FS
IADC
tNPD
1.5
125
7)
Supply current ADC operation
Start-up time from ADC Power down
1
15
Table 5 nRF9E5 AD converter electrical specifications.
1) Higher sink/source current is possible if increased voltage changes on ports are accepted.
2) Operates in the 433, 868 and 915 MHz ISM band.
3) The crystal frequency may be chosen from 5 different values (4, 8, 12, 16, and 20MHz) which are specified in
the configuration word. Please see Table 22 on page 37.
4) Optimum Load Impedance.
5) Channel width and channel spacing is 200kHz.
6) Channel Level +3dB over sensitivity, interfering signal a standard carrier wave, Image 2 MHz above wanted.
7) Conversion rate is dependant on resolution, Please see chapter 10.3 page 31.
2.1 Detailed Current Information
MODE
Light power down
Moderate Power down
Standby mode
TYPICAL CURRENT
0.4 mA
125 uA
25 uA
Deep Power Down
MCU @0.5M 3 volt
MCU @1M 3 volt
MCU @2M 3 volt
MCU @4M 3 volt
MCU @8M 3 volt
MCU @12M 3 volt
MCU @16M 3 volt
MCU @20M 3 volt
Rx @ 433
Rx @ 868/915
Reduced Rx
Tx @ 10dBm
Tx @ 6dBm
Tx @ -2dBm
Tx @ -10dBm
2.5 uA
0.125 mA
0.25 mA
0.5 mA
1
2
3
4
5
mA
mA
mA
mA
mA
12.2 mA
12.8 mA
10.5 mA
30 mA
20 mA
14 mA
11 mA
Table 6 Detailed current information
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
3 PIN ASSIGNMENT
P00
AIN0
AIN1
AIN2
DVDD_1V2 AREF
AIN3
VDD
32 31 30 29 28
26 25
27
VSS
P01
P02
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
IREF
nRF9E5
P03
VSS
32L QFN 5x5
VDD
ANT2
ANT1
VSS
VDD_PA
P04
P05
VSS
P06
VDD
9
P07
12 13 14
SCK
10 11
15 16
EECSN
XC1
XC2
VSS
MOSI
MISO
Figure 2 Pin assignment nRF9E5.
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4 PIN FUNCTION
Pin
1
2
3
4
Name
P01
P02
P03
VDD
VSS
Pin function
Digital IN/OUT
Digital IN/OUT
Digital IN/OUT
Power
Description
uP Bi-directional digital pin
uP Bi-directional digital pin
uP Bi-directional digital pin
Power supply (+3V DC)
Ground (0V)
5
Power
6
7
8
9
P04
P05
P06
P07
MOSI
MISO
SCK
EECSN
XC1
Digital IN/OUT
Digital IN/OUT
Digital IN/OUT
Digital IN/OUT
SPI-Interface
SPI-Interface
SPI-clock
uP Bi-directional digital pin
uP Bi-directional digital pin
uP Bi-directional digital pin
uP Bi-directional digital pin
SPI output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SPI input
SPI clock
SPI-enable
SPI enable, active low
Crystal Pin 1/ External clock reference pin
Crystal Pin 2
Ground (0V)
Power supply (+3V DC)
Ground (0V)
Regulated positive supply (1.8V) to nRF905 power amplifier
Antenna interface 1
Antenna interface 2
Ground (0V)
Reference current
Ground (0V)
Power supply (+3V DC)
ADC Input 3
ADC Input 2
ADC Input 1
Analog Input
Analog Output
Power
Power
Power
Power Output
RF – port
RF – port
Power
Analog Input
Power
XC2
VSS
VDD
VSS
VDD_PA
ANT1
ANT2
VSS
IREF
VSS
VDD
AIN3
AIN2
AIN1
AIN0
AREF
DVDD_1V2
P00
Power
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Power Output
Digital IN/OUT
ADC Input 0
ADC Reference Voltage
Low voltage positive digital supply output for de-coupling
uP Bi-directional digital pin
Table 7 nRF9E5 pin function.
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5 SYSTEM CLOCK
The Microcontroller clock, CPU_CLK, is generated from the on chip crystal oscillator.
CPU_CLK frequency is configured in the RF-configuration register (see chapter 11) and
could be set to 0.5, 1, 2 or 4MHz. CPU_CLK could in addition be set equal to the crystal
oscillator frequency itself. The CPU_CLK generation is illustrated in Figure 3.
It is important to always set XOF equal to the actual crystal selected for the application.
fCPU_CLK
0.5 to 20MHz
UP_CLK_FREQ
0.5 - 4MHz
MUX
f
XO
4MHz
Divide 1 to 5
Divide 1 to 4
XO
UP_CLK_EN
UP_CLK
_FREQ
XOF
Figure 3 CPU_CLK generation in nRF9E5.
The chip has an internal low frequency clock that is always active. This clock ensure
proper operation of vital function when the chip is in power down mode and the crystal
oscillator is turned off, please see chapter 16 on page 51.
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6 DIGITAL I/O PORTS
The nRF9E5 has two IO ports located at the default locations for P0 and P1 in standard
8051, but the ports are fully bi-directional CMOS and the direction of each pin is
controlled by a _DIR and an _ALT bit for each bit as shown in the table below.
Pin
EECSN
MISO
SCK
MOSI
P00
P01
P02
P03
P04
Default function
P1.3
Alternate=1
SPI_CTRL != 01
P1.3
P1.2
P1.0
P1.1
SPI.datain
SPI.clock
SPI.dataout
P0.0
T2 (timer2 input)
GTIMER
RXD (UART)
TXD (UART)
INT0_N (interrupt)
INT1_N (interrupt)
T0 (timer0 input)
T1 (timer1 input)
PWM
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P05
P06
P07
Table 8 Port functions.
6.1 I/O Port Behavior During RESET
During this period the internal reset is active (regardless of whether or not the clock is
running), all the port pins related to P0 are configured as inputs, whereas the inputs
related to P1 are configured as required for an SPI master. When program execution
starts, all ports are still configured as during reset, and the program will need to set the
_ALT and/or the _DIR register for the pins that need another direction.
6.2 Port 0 (P0)
P0_ALT and P0_DIR control the P0 port function in that order of priority. If the
alternate function for port P0.n is set (by P0_ALT.n = 1) the pin will be input or output
as required by the alternate function (UART, external interrupt, timer inputs or PWM
output), except that the UART RXD direction will still depend on P0_DIR.1.
To use INT0_N or INT1_N as interrupts, the corresponding alternate function must be
activated, P0_ALT.3 / P0_ALT.4. When the P0_ALT.n is not set, bit ‘n’ of the port is a
GPIO function with the direction controlled by P0_DIR.n.
Pin
Data in P0_ALT.n,P0_DIR.n
11 00
GTIMER
10
GTIMER
RXD
TXD
INT0_N
INT1_N
T0
01
P00
P01
P02
P03
P04
P05
P06
P07
Out
Out
Out
In
In
In
Out
In
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Out
Out
Out
Out
Out
Out
Out
Out
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
In
In
In
In
In
In
In
In
RXD
TXD
INT0_N
INT1_N
T0
Out
In
In
In
T1
PWM
In
Out
T1
In
PWM
Out
Table 9 Port 0 (P0) functions.
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Port 0 is controlled by SFR-registers 0x80, 0x93, 0x94 and 0x95 listed in the table
below.
Addr
SFR
(hex)
R/W
#bit
Init
value
(hex)
Name
Function
80
93
R/W
R/W
8
8
FF
00
P0
P0_DRV
Port 0, pins P07 to P00
High drive strength for each bit of Port 0
0: Enable, 1: Disable
(See 6.2.1 belowfor a description)
94
95
R/W
R/W
8
8
FF
00
P0_DIR
P0_ALT
Direction for each bit of Port 0
0: Output, 1: Input
Direction is overridden if alternate function is
selected for a pin.
Select alternate functions for each pin of P0, if
corresponding bit in P0_ALT is set, as listed in
Table 9 Port 0 (P0) functions.
Table 10 Port 0 control and data SFR-registers.
6.2.1 High Current Drive Capability
Odd numbered bits will source high current when the corresponding bit in P0_DRV is
set, where as even number bits will sink high current when the corresponding bit in
P0_DRV is set.
6.3 Port 1 (P1 or SPI port)
The P1 port consists of 4 pins, one of which is a hardwired input. The primary function
of the P1 port (when SPI_CTRL is 01) is a SPI master port. The pin EECSN is used as a
chip select for the boot EEPROM, the GPIO bits in port P0 may be used as chip select(s)
for other SPI devices.
When not used as SPI port, P1_ALT.0 will force SCK (P1.0) to be the timer T2 input;
MOSI (P1.1) is now a GPIO. When P0_ALT.0 is 0, also SCK (P1.0) is a GPIO.
MISO (P1.2) is always an input. That is P1_DIR.2 and P1_ALT.2 are ignored.
EECSN (P1.3) is always a GPIO. It will be activated by the default boot loader after
reset and should be connected to the CSN of the boot flash.
Pin
SPI_CTRL = 01
SPI_CTRL != 01
P1_ALT.n = 0
P1_DIR.n = 0 P1_DIR.n = 1
P1_ALT.n = 1
SCK
SPI.clock
SPI.dataout
SPI.datain
P1.3
Out
Out
In
T2
In
P1.0
P1.1
P1.2
P1.3
In
In
In
In
P1.0
P1.1
P1.2
P1.3
Out
Out
In
MOSI
MISO
EECSN
P1.1
P1.2
P1.3
I/O2
In
Out
I/O2
Out
Table 11 Port 1 (P1) functions.
2
P1.1 and P1.3 are actually under control of P1_DIR.1 and P1_DIR.3 even when P1_ALT.1 or P1_ALT.3
are 1, since there are no alternate functions for these pins.
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Port 1 is controlled by SFR-registers 0x90, 0x96 and 0x97, and only the 4 lower bits of
the registers are used.
Addr R/W
SFR
(hex)
#bit
Init
value
(hex)
Name
Function
90
R/W
R/W
4
4
F
P1
Port 1, pins SPI_SCK, SPI_MOSI, SPI_MISO and
SPI_CSN
96
4
P1_DIR Direction for each bit of Port 1
0: Output, 1: Input
Direction is overridden if alternate function is selected
for a pin, or if SPI_CTRL=01.
SPI_MISO is always input.
97
R/W
4
0
P1_ALT Select alternate functions for each pin of P1
if corresponding bit in P1_ALT is set, as listed in Table
11 Port 1 (P1) functions
Table 12 Port 1 control and data SFR-registers.
P1 is by default configured as a SPI master port. In this case, it is then controlled by the
3 SFR registers 0xB2, 0xB3 and 0xB4 as shown in Table 33 on page 43.
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7 ANALOG INTERFACE
7.1 Crystal Specification
Tolerance includes initially accuracy and tolerance over temperature and aging.
Frequency
CL
ESR
C0max
Tolerance @
868/915 MHz
Tolerance @
433 MHz
4MHz
8MHz
12MHz
16MHz
20MHz
12pF
12pF
12pF
12pF
12pF
7.0pF
7.0pF
7.0pF
7.0pF
7.0pF
150W
100W
100W
100W
100W
±30ppm
±30ppm
±30ppm
±30ppm
±30ppm
±60ppm
±60ppm
±60ppm
±60ppm
±60ppm
Table 13 Crystal specification of nRF9E5.
To achieve a crystal oscillator solution with low power consumption and fast start-up
time, it is recommended to specify the crystal with a low value of crystal load
capacitance. Specifying CL =12pF is acceptable, but it is possible to use up to 16pF.
Specifying a lower value of crystal parallel equivalent capacitance, Co=1.5pF is also
good, but this can increase the price of the crystal itself. Typically Co=1.5pF at a crystal
specified for Co_max=7.0pF.
7.2 Antenna Output
The “ANT1 & ANT2” output pins provide a balanced RF output to the antenna. The
pins must have a DC path to VDD_PA, either via a RF choke or via the center point in a
dipole antenna. The load impedance seen between the ANT1/ANT2 outputs should be in
the range 200-700W. The optimum differential load impedance at the antenna ports is
given as:
900MHz
430MHz
225W+j210
300W+j100
A low load impedance (for instance 50W) can be obtained by fitting a simple matching
network or a RF transformer (balun). Further information regarding balun structures and
matching networks may be found in the Application Examples chapter.
7.3 ADC Inputs
The Analog to digital converter has four analog input channels and one reference
voltage input. Analog input is selected with CHSEL in the ADC_CONFIG_REG.
7.4 Current Reference
To get accurate internal biasing, an external low tolerance resistor is used. A resistor of
22kW and 1% accuracy should be connected between the pin IREF and ground for
proper operation of nRF9E5.
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7.5 Digital Power De-Coupling
nRF9E5 has internal regulator used for optimum performance and minimum power
dissipation in digital part of the system. De-coupling of the regulated power is needed
for proper operation of the chip. A capacitor of 10nF should be connected between
DVDD_1V2 and ground as close to the chip as possible. Please see PCB layout and de-
coupling guidelines for further information regarding layout.
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8 INTERNAL INTERFACE AD CONVERTER AND
TRANSCEIVER
8.1 P2 - Radio General Purpose IO Port
The P2 port controls the transceiver. The P2 port uses the address normally used by port
P2 in standard 8051. However since the radio transceiver is on chip, the port is not bi-
directional. The power on default values in the port “latch” also differs from traditional
8051 to match the requirements of the radio transceiver subsystem.
Operation of the transceiver is controlled by SFR registers P2 and SPI_CTRL:
Addr
SFR
(hex)
R/W
R/W
R/W
#bit
8
Init
value
(hex)
Name
Function
A0
04
P2
General purpose IO for interface to
nRF905 radio transceiver and AD
converter subsystems
B3
2
0
SPI_CTRL 00 -> SPI not used
01 -> SPI connected to port P1 (boot)
1x -> SPI connected to nRF905/AD
Table 14 nRF905 433/868/915 MHz transceiver subsystem control registers - SFR 0xA0
and 0xB3.
The bits of the P2 register correspond to similar pins of the nRF905 single chip, as
shown in Table 15 P2 (RADIO) register . In the documentation the pin names are used,
so please note that setting or reading any of these nRF905 pins, means to write or read
the P2 SFR register accordingly.
P2 register bit: Function
Corresponding nRF905
Transceiver pin name
Read :
7: nRF905 Transceiver address match
6: nRF905 Transceiver carrier detect
5: nRF905 Transceiver data ready
4: ADC end of conversion
3: 0 (not used)
AM
CD
DR
EOC
2: nrF905 Transceiver and ADC SPI data out (SBMISO)
1: 0 (not used)
MISO
0: 0 (not used)
Write :
7: Not used
6: Not used
5: nRF905 Transceiver enable receiver function
4: nRF905 Transceiver transmit/receive selection
TRX_CE
TX_EN
3: nrF905 Transceiver and ADC SPI Chip select (RACSN) CSN
2: Not used
1: nrF905 Transceiver and ADC SPI data in (SBMOSI)
0: nrF905 Transceiver and ADC SPI clock (SBSCK)
MOSI
SCK
Table 15 P2 (RADIO) register - SFR 0xA0, default initial data value is 0x08.
Note : Some of the pins are overridden when SPI_CTRL=1x, see Table 14.
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8.1.1 Controlling the Transceiver via SPI Interface.
Normally the SPI hardware interface rather than GPIO programming will do the data
transfers to the transceiver. Please see Table 33 SPI control and data SFR-registers for
use of SPI interface. When SPI_CTRL is ‘0x’, all radio pins are connected directly to
their respective port pins and the SPI functionality may be implemented in software.
P2 register
SPI_CTRL==1x
nRF905/AD
Read
AM
bit
7
Write
EOC
AM
CD
CD
6
DR
5
TRX_CE
TX_EN
SBCSN
TRX_CE
TX_EN
CSN
DR
EOC
4
3
SBMISO
2
1 MUX
1
SBMOSI
SBSCK
MOSI
SCK
0
0
1
MUX
0
SPI Hardware
dataout
clock
datain
MISO
0
1
from IO-pin
MUX
Figure 4 Transceiver interface.
8.1.2 P2 Port Behavior During RESET
During the period the internal reset is active (regardless of whether or not the clock is
running), the P2 outputs that control the nRF905 transceiver subsystem are forced to
their respective default values. When program execution starts, these ports will remain at
those default levels until the programmer actively changes them by writing to the P2
register.
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9 TRANCEIVER SUBSYSTEM (nRF905)
9.1 RF Modes of Operation
The Transceiver has two active (RX/TX) modes and one power-saving mode when the
microcontroller is running.
9.1.1 Active Modes
·
·
ShockBurst™ RX
ShockBurst™ TX
9.1.2 Power Saving Mode
·
Standby and SPI - programming
The transceiver mode is decided by the settings of TRX_CE, TX_EN
TRX_CE
TX_EN
Operating Mode
0
1
1
X
0
1
Standby and SPI – programming
Radio Enabled - ShockBurstTM RX
Radio Enabled - ShockBurstTM TX
Table 16 transceiver operational modes.
9.2 nRF ShockBurst™ Mode
The nRF9E5 uses the Nordic Semiconductor ShockBurst™ feature. ShockBurstTM
makes it possible to use the high data rate offered by the nRF905. By embedding all
high speed signal processing related to RF protocol in the transceiver, the nRF905 offers
the micro controller a simple SPI interface. Data rate is decided by the interface-speed
the micro controller itself sets up. By allowing the digital part of the application to run at
low speed, while maximizing the data rate on the RF link, the nRF905 ShockBurst™
mode reduces the average current consumption in applications. In ShockBurstTM RX,
Address Match (AM) and Data Ready (DR) notifies the MCU when a valid address and
payload is received respectively. In ShockBurstTM TX, the nRF905 automatically
generates preamble and CRC. Data Ready (DR) notifies the MCU that the transmission
is completed. All together, this means reduced memory demand and more available
resources in the MCU, as well as reduced software development time.
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Typical ShockBurstTM TX:
1. When the application MCU has data for a remote node, the address of the
receiving node (TX-address) and payload data (TX-payload) are clocked into
nRF905 via the SPI interface. The application protocol or MCU sets the
speed of the interface.
2. MCU sets TRX_CE and TX_EN high, this activates a nRF905 ShockBurst™
transmission.
3. nRF905 ShockBurst™:
·
·
·
·
Radio is automatically powered up.
Data package is completed (preamble added, CRC calculated).
Data package is transmitted (100kbps, GFSK, Manchester-encoded).
Data Ready is set high when transmission is completed.
4. If AUTO_RETRAN is set high, the nRF905 continuously retransmits the
package until TRX_CE is set low.
5. When TRX_CE is set low, the nRF905 finishes transmitting the outgoing
package and then sets itself into standby mode.
The ShockBurstTM mode ensures that a transmitted package that has started always
finishes regardless of what TRX_EN and TX_EN is set to during transmission. The new
mode is activated when the transmission is completed. Please see subsequent chapters
for detailed timing
For test purposes such as antenna tuning and measuring output power it is possible to set
the transmitter so that a constant carrier is produced. To do this TRX_CE must be
maintained high instead of being pulsed. In addition Auto Retransmit should be
switched off. After the burst of data has been sent then the device will continue to send
the unmodulated carrier.
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Radio in Standby
TX_EN = HI
PWR_UP = HI
TRX_CE = LO
Data Package
SPI - programming
uController loading ADDR
and PAYLOAD data
ADDR
PAYLOAD
(Configuration register if
changes since last TX/RX)
TRX_CE
= HI ?
NO
YES
Transmitter
is powered
up
nRF ShockBurst TX
DR is
set low
after pre-
amble
Generate CRC and preamble
Sending package
DR is set high when completed
Pre-
amble
ADDR
PAYLOAD
CRC
NO
AUTO_
RETRAN
= HI ?
YES
TRX_CE
= HI ?
NO
Bit in configuration
register
YES
NB: DR is set low under the following conditions after it has been set high:
·
If TX_EN is set low
Figure 5 Flowchart ShockBurstTM transmit of nRF905.
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Typical ShockBurstTM RX:
1. ShockBurstTM RX is selected by setting TRX_CE high and TX_EN low.
2. After 650ms nRF905 is monitoring the air for incoming communication.
3. When the nRF905 senses a carrier at the receiving frequency, Carrier Detect
(CD) pin is set high.
4. When a valid address is received, Address Match (AM) pin is set high.
5. When a valid package has been received (correct CRC found), nRF905
removes the preamble, address and CRC bits, and the Data Ready (DR) pin is
set high.
6. MCU sets the TRX_CE low to enter standby mode (low current mode).
7. MCU can clock out the payload data at a suitable rate via the SPI interface.
8. When all payload data is retrieved, nRF905 sets Data Ready (DR) and
Address Match (AM) low again.
9. The chip is now ready for entering ShockBurstTM RX, ShockBurstTM TX or
power down mode.
If TRX_CE or TX_EN is changed during an incoming package, the nRF905 changes
mode immediately and the package is lost. However, if the MCU is sensing the Address
Match (AM) pin, it knows when the chip is receiving an incoming package and can
therefore decide whether to wait for the Data Ready (DR) signal or enter a different
mode.
To avoid spurious address matches it is recommended that the address length be 24 bits
or higher in length. Small addresses such as 8 or 16 bits can often lead to statistical
failures due to the address being repeated as part of the data packet. This can be avoided
by using a longer address.
Each byte within the address should be unique. Repeating bytes within the address
reduces the effectiveness of the address and increases its susceptibility to noise hence
increasing the packet error rate. The address should also have several level shifts (i.e.
10101100) to reduce the statistical effect of noise and hence reduce the packet error rate.
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Radio in Standby
TX_EN = LO
PWR_UP = HI
NO
TRX_CE
= HI ?
YES
Receiver is
powered up
Receiver
Sensing for incomming data
CD is set high if carrier
Data Package
NO
Correct
ADDR?
Pre-
amble
ADDR
PAYLOAD
CRC
YES
AM is set
high
Receiving
data
Correct
CRC?
NO
AM is set low
DR and AM are
set low
DR and AM are
set low
YES
DR high is
set high
MCU clocks out payload via
the SPI interface
MCU clocks out payload via
the SPI interface
PAYLOAD
TRX_CE
= HI ?
Radio enters
STBY
RX Remains
On
NO
YES
Figure 6 Flowchart ShockBurstTM receive of nRF905.
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9.3 Standby Mode
Standby mode is used to minimize average current consumption while not transmitting
or receiving and still maintaining short start up times to ShockBurstTM RX and
ShockBurstTM TX. In this mode the crystal oscillator have to be active. The
configuration word content is maintained during standby.
9.4 Output Power Adjustment
The power amplifier in nRF905 can be programmed to four different output power
settings by the configuration register. By reducing output power, the total TX current is
reduced.
Power setting
RF output power
DC current consumption
00
01
10
11
-10 dBm
-2 dBm
6 dBm
11.0 mA
14.0 mA
20.0 mA
30.0 mA
10 dBm
Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 400 W.
Table 17 RF output power setting for the nRF905.
9.5 Modulation
The modulation of nRF905 is Gaussian Frequency Shift Keying (GFSK) with a data-rate
of 100kbps. Deviation is ±50kHz. GFSK modulation results in a more bandwidth
effective transmission-link compared with ordinary FSK modulation.
The data is internally Manchester encoded (TX) and Manchester decoded (RX). That is,
the effective symbol-rate of the link is 50kbps. By using internally Manchester
encoding, no scrambling in the u-controller is needed.
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9.6 Output Frequency
The operating RF-frequency of nRF905 is set in the configuration register by CH_NO
and HFREQ_PLL. The operating frequency is given by:
fOP = (422.4 + (CH _ NO/10)) × (1+ HFREQ _ PLL) MHz
When HFREQ_PLL is ‘0’ the frequency resolution is 100kHz and when it is ‘1’ the
resolution is 200kHz.
The application operating frequency has to be chosen to apply with the Short Range
Devise regulation in the area of operation.
Operating frequency
430.0 MHz
HFREQ_PLL
CH_NO
[0]
[0]
[0]
[0]
[001001100]
[001101011]
[001101100]
[001111011]
433.1 MHz
433.2 MHz
434.7 MHz
862.0 MHz
868.2 MHz
868.4 MHz
869.8 MHz
[1]
[1]
[1]
[1]
[001010110]
[001110101]
[001110110]
[001111101]
902.2 MHz
902.4 MHz
927.8 MHz
[1]
[1]
[1]
[100011111]
[100100000]
[110011111]
Table 18 Examples of real operating frequencies.
9.7 Carrier Detect.
When the nRF905 is in ShockBurst
TM
RX, the Carrier Detect (CD) pin is set high if a
RF carrier is present at the channel the device is programmed to. This feature is very
effective to avoid collision of packages from different transmitters operating at the same
frequency. Whenever a device is ready to transmit it could first be set into receive mode
and sense whether or not the wanted channel is available for outgoing data. This forms a
very simple listen before transmit protocol. Operating Carrier Detect (CD) with Reduced
RX Power mode is an extremely power efficient RF system. Typical Carrier Detect level
(CD) is typically 5dB lower than sensitivity, i.e. if sensitivity is –100dBm then the
Carrier Detect function will sense a carrier wave as low as –105dBm. Below –105dBm
the Carrier Detect signal will be low, i.e. 0V. Above –95dBm the Carrier Detect signal
will be high, i.e. Vdd. Between approximately -95 to -105 the Carrier Detect Signal will
toggle.
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9.8 Address Match
TM
When the nRF905 is in ShockBurst
RX mode, the Address Match (AM) pin is set
high as soon as an incoming package with an address that is identical with the device’s
own identity is received. With the Address Match pin the controller is alerted that the
nRF905 is receiving data actually before the Data Ready (DR) signal is set high. If the
Data Ready (DR) pin is not set high i.e. the CRC is incorrect then the Address Match
(AM) pin is reset to low at the end of the received data packet. This function can be very
useful for an MCU. If Address Match (AM) is high then the MCU can make a decision
to wait and see if Data Ready (DR) will be set high indicating a valid data package has
been received or ignore that a possible package is being received and switch modes.
9.9 Data Ready
The Data Ready (DR) signal makes it possible to largely reduce the complexity of the
MCU software program.
In ShockBurst TM TX, the Data Ready (DR) signal is set high when a complete package
is transmitted, telling the MCU that the nRF905 is ready for new actions. It is reset to
low at the start of a new package transmission or when switched to a different mode i.e.
receive mode or standby mode.
TM
In ShockBurst
TX Auto Retransmit the Data Ready (DR) signal is set high at the
beginning of the pre-amble and is set low at the end of the preamble. The Data Ready
(DR) signal therefore pulses at the beginning of each transmitted data packet.
In ShockBurst TM RX, the signal is set high when nRF905 has received a valid package,
i.e. a valid address, package length and correct CRC. The MCU can then retrieve the
payload via the SPI interface. The Data Ready (DR) pin is reset to low once the data has
been clocked out of the data buffer or the device is switched to transmit mode.
9.10 Auto Retransmit
One way to increase system reliability in a noisy environment or in a system without
collision control is to transmit a package several times. This is easily accomplished with
the Auto Retransmit feature in nRF905. By setting the AUTO_RETRAN bit to “1” in
the configuration register, the circuit keeps sending the same data package as long as
TRX_CE and TX_EN is high. As soon as TRX_CE is set low the device will finish
sending the packet it is currently transmitting and then return to standby mode.
9.11 RX Reduced Power Mode
To maximize battery lifetime in application where the nRF905 high sensitivity is not
necessary; nRF905 offers a built in reduced power mode. In this mode, the receive
current consumption reduces from 12.5mA to only 10.5mA. The sensitivity is reduced to
typical –85dBm, ±10dB. Some degradation of the nRF905 blocking performance should
be expected in this mode. The reduced power mode is an excellent option when using
Carrier Detect to sense if the wanted channel is available for outgoing data.
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10 AD CONVERTER SUBSYSTEM
10.1 AD Converter
The nRFE5 AD converter has 10 bit dynamic range and linearity when used at the
Nyquist rate. With lower signal frequencies and post filtering, up to 12 bits resolution is
possible. The reference for the AD converter is selectable between the AREF input and
an internal 1.22V bandgap reference.
The converter default SPI setting is 10 bits. For special requirements, the AD converter
can be configured to perform 6, 8, 10 or 12 bit conversions. The converter may also be
used in differential mode with AIN0 used as inverting input and one of the other 3
external inputs used as noninverting input.
Two registers interface the AD converter, ADC_CONFIG_REG and
ADC_DATA_REG. AD converter status bit are available in the STATUS_REGISTER.
Registers are described in detail in chapter 11.
Selection of input channel is directly embedded in the START_ADC_CONV command,
alternatively it is set by CHSEL in the ADC_CONFIG_REG. Values of CHSEL from 0
to 3 would select AIN0 to AIN3 respectively. Setting CHSEL to [1xxx] will monitor the
nRF9E5 supply voltage by converting an internal input that is VDD/3 with the 1.22V
internal reference.
The AD conversion result is available as ADCDATA in ADC_DATA_REG at the end
of conversion. The data in ADC_DATA_REG is stored according to Table 19 with left
or right justified data selected by ADC_RL_JUST.
ADC_
RL_JUST
ADC
_RESCTRL
# bit
ADC_DATA_REG[15:0]
High byte [15:8]
Low byte [7:0]
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
6
8
10
12
6
8
10
12
ADCDATA[5:0]
ADCDATA[7:0]
ADCDATA[9:0]
ADCDATA[11:0]
‘0’
ADCDATA[5:0]
ADCDATA[7:0]
ADCDATA[9:0]
ADCDATA[11:0]
‘0’
Table 19 ADC_DATA_REGISTER justified data.
Overflow status is stored as ADC_RFLAG in the STATUS_REGISTER after each
conversion.
The complete subsystem is switched off by clearing bit ADC_PWR_UP.
Instructions for the AD converter are given in Table 21 on page 35.
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10.2 AD Converter Usage
10.2.1 Measurements with External Reference
When VFSSEL is set to 1 and CHSEL selects an input AINi(i.e. AIN0 to AIN3), the
result in ADCDATA is directly proportional to the ratio between the voltage on the
selected input, and the voltage on pin AREF:
ADCDATA
VAINi =VAREF
×
2 N
and for differential measurements a similar equation apply:
ADCDATA - 2(N -1)
V AINi - V AIN0 = V AREF
×
2N
Where N is the number of bits set in RESCTRL
This mode of operation is normally selected for sources where the voltage is depending
on the supply voltage (or another variable voltage), as shown in Figure 7 below. The
resistor R1 is selected to keep AREF = 1.5V for the maximum VDD voltage.
SUPPLY
R1
VDD
AREF
nRF9E5
R2
AIN0
AIN1
R3
Figure 7 Typical use of AD with 2 ratiometric inputs.
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10.2.2 Measurements with Internal Reference
When VFSSEL is set to 0 and CHSEL selects an input AINI (i.e. AIN0 to AIN3), the
result in ADCDATA is directly proportional to the ratio between the voltage on the
selected input and the internal bandgap reference (nominally 1.22V):
ADCDATA
VAINi =1.22 ×
2N
and for differential measurements a similar equation apply:
ADCDATA - 2(N -1)
V AINi - V AIN0 = 1.22 ×
2N
Where N is the number of bits set in RESCTRL
This mode of operation is normally selected for sources where the voltage is not
depending on the supply voltage.
10.2.3 Supply Voltage Measurement
When CHSEL is set to [1xxx], the ADC will use the internal bandgap reference
(nominally 1.22V). The input to the converter is 1/3 of the voltage on the VDD pins.
The result in ADCDATA is thus directly proportional to the VDD voltage.
ADCDATA
VVDD = 3.66 ×
2N
Where N is the number of bits set in RESCTRL
10.3 AD Converter Sampling and Timing
An AD conversion is initialized after a low to high transition on CSTASRT in
ADC_CONFIG_REG or by using the instruction START_ADC_CONV. In both cases
the conversion itself would start at the first positive edge of ADCCLK after RACSN is
set high after instruction is issued.
When ADCRUN is low, a single conversion would be performed and a pulse on EOC is
generated when the converted value is available in ADC_DATA_REG. If CSTARTN is
set low or a new START_ADC_CONV command is issued, the previous conversion
will be aborted. Conversion time, tconv, depends on resolution.
N
tconv
=
+ 3 ADCCLK cycles
2
Where N is the number of resolution bit. In Figure 8 a 10-bit conversion is shown.
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ADCCLK
SBCSN
analog
sampled
tCONV
EOC
ADCDATA
Figure 8 Timing diagram single step conversion.
When ADCRUN is high the ADC is running continuously. Cycle time t
is the time
cycle
between each conversion. EOC indicates every time a new conversion value is stored in
ADC_DATA_REG.
N
tcycle
=
+ 1 ADCCLK cycles
2
where N is number of resolution bits. Figure 9 shows 10-bit conversion where
ADCRUN is set high.
n
n+1
n+2
analog sample
ADCCLK
tConv
EOC
tCycle
sample n-1
sample n
ADCDATA
Figure 9 Timing diagram continuous mode conversion.
A 500 kHz clock (ADCCLK) clocks the ADC converter. Table 20 shows t
as
cycles
function of resolution.
Resolution
[Number of bits]
tcycles
[ms]
8
10
12
Sampling rate
[kspls]
6
8
10
12
125
100
83.3
71.4
14
Table 20 ADC resolution and maximum sampling rate.
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11 TRANCEIVER AND AD CONVERTER CONFIGURATION
All configuration of the transceiver and AD converter subsystem is done via an internal
SPI -interface of the two systems. The interface consists of 7 registers, a SPI instructions
set is used to decide which operation shall be performed. The SPI-interface can only be
activated when the transceiver is in standby mode. All references to the SPI interface in
this chapter refer to the internal SPI interface of the transceiver and AD converter
subsystem.
11.1 Internal SPI Register Configuration
The SPI-interface consists of seven internal registers. A register read-back mode is
implemented to allow verification of the register contents
MISO
MOSI
EN
SCK
I/O-reg
STATUS-REGISTER
CSN
CLK
EN
ADC-CONFIGURATION-
DTA
REGISTER
CLK
EN
ADC-DATA-
REGISTER
DTA
CLK
EN
RF-CONFIGURATION-
DTA
REGISTER
CLK
EN
DTA
CLK
TX-ADDRESS
EN
DTA
CLK
TX-PAYLOAD
RX-PAYLOAD
EN
CLK
Figure 10 SPI – interface composed of seven internal registers.
Status – Register
Register contains status of Data Ready (DR), Address Match (AM),
ADC_End_Of_Conversion and ADC_Ready_Flag
ADC- Configuration – Register
Register contains information of ADC setup such as resolution control, channel select,
differential or single ended mode, continuous or single conversion mode etc.
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ADC- Data – Register
Register contains AD converter results.
RF - Configuration Register
Register contains transceiver setup information such as frequency and output power ext.
TX – Address
Register contains address of target device. How many bytes used is set in the
configuration register.
TX – Payload
Register containing the payload information to be sent in a ShockBurst TM package. How
many bytes used is set in the configuration register.
RX – Payload
Register containing the payload information derived from a received valid ShockBurst
TM
package. How many bytes used is set in the configuration register. Valid data in the
RX-Payload register is indicated with a high Date Ready (DR) signal.
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11.2 SPI – Instruction Set
The available commands to be used on the SPI-interface are given in Table 21.
Whenever CSN is set low the interface would expect an instruction. Every new
instruction has to be presided by a high to low transaction on CSN.
Instruction set for the Transceiver and AD converter subsystem
Instruction Name
Instruction
Format
Operation
W_RF_CONFIG
(WRC)
0000 AAAA
Write Configuration-register. AAAA indicates which byte
the write operation is to be started from. Number of bytes
depending on start address AAAA.
R__RF_CONFIG
(RRC)
0001 AAAA
Read Configuration-register. AAAA indicates which byte
the read operation is to be started from. Number of bytes
depending on start address AAAA.
W_TX_PAYLOAD
(WTP)
R_TX_PAYLOAD
(RTP)
W_TX_ADDRESS
(WTA)
R_TX_ADDRESS
(RTA)
R_RX_PAYLOAD
(RRP)
R_ADC_DATA
(RAD)
W_ADC_CONFIG
(WAC)
R_ADC_CONFIG
(RAC)
0010 0000
0010 0001
0010 0010
0010 0011
0010 0100
0100 000A
0100 0100
0100 0110
Write TX-payload: 1 – 32 bytes. A write operation will
always start at byte 0.
Read TX-payload: 1 – 32 bytes. A read operation will
always start at byte 0.
Write TX-address: 1 – 4 bytes. A write operation will
always start at byte 0.
Read TX-address: 1 – 4 bytes. A read operation will
always start at byte 0.
Read RX-payload: 1 – 32 bytes. A read operation will
always start at byte 0.
Read ADC data. A indicates which byte the read
operation is to be started from.
Write ADC configuration register: 1 – 3 bytes.
A write operation will always start at byte 0.
Read ADC configuration register: 1 – 3 bytes.
A read operation will always start at byte 0.
Special command for fast setting of CH_NO,
HFREQ_PLL and PA_PWR in the CONFIGURATION
REGISTER. CH_NO= ccccccccc, HFREQ_PLL = h
PA_PWR = pp
CHANNEL_CONFIG 1000 pphc
(CC) cccc cccc
START_ADC_CONV 1100 ssss
(SAV)
Special command for start of an ADC conversion for a
given source – ssss = CHSEL.
Table 21 Instruction set for the Transceiver AD converter subsystem.
A read or a write operation may operate on a single byte or on a set of succeeding bytes
from a given start address defined by the instruction. When accessing succeeding bytes
one will read or write MSB of the byte with the smallest byte number first. The content
of the status-register will always be read to MISO after a high to low transition on CSN.
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11.3 SPI Timing
Data is clocked into or out of the device on the rising edge of the clock pulse. The clock
speed is determined by the MCU and may be from 1Hz to 10MHz depending on the
MCU. The device must be in one of the power saving modes for the configuration
registers to be read or written to.
CSN
0
1
2
3
7
8
15
SCK
Command 8 bits, MSB = C7
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
MOSI
MISO
Status byte as output, MSB = S7
Addressed byte as output, MSB = O7
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
Succeeding bytes to addressed byte
as output
Figure 11 Internal SPI read operation.
CSN
0
1
2
3
7
8
15
SCK
Command 8 bits, MSB = C7
First data byte as input, MSB = D7
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Succeeding data bytes as input
MOSI
MISO
Status byte as output, MSB = S7
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
Figure 12 Internal SPI write operation.
The transceiver and AD converter SPI interface is controlled by P2 in the micro
controller. That is, SCK, MOSI, MISO and CSN are P2.0, P2.1, P2.2 and P2.3
respectively. Detailed information of mapping is found in chapter 8.
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11.4 RF Configuration – Register Description
Parameter
Bitwidth
Description
CH_NO
9
Sets center frequency together with HFREQ_PLL (default value = 001101100b = 108d).
fRF = ( 422.4 + CH_NOd /10)*(1+HFREQ_PLLd) MHz
Sets PLL in 433 or 868/915 MHz mode (default value = 0).
'0' – Chip operating in 433MHz band
HFREQ_
PLL
1
'1' – Chip operating in 868 or 915 MHz band
PA_PWR
2
Output power (default value = 00).
'00' -10dBm
'01' -2dBm
'10' +6dBm
'11' +10dBm
RX_RED_
PWR
1
1
3
Reduces current in RX mode by 1.6mA. Sensitivity is reduced (default value = 0).
'0' – Normal operation
'1' – Reduced power
AUTO_
RETRAN
Retransmit contents in TX – register as long TRX_CE and TXEN is high (default value = 0).
'0' – No retransmission
'1' – Retransmission of data package
RX_AFW
TX_AFW
RX_PW
RX-address width (default value = 100).
'001' – 1 byte RX address field width
.
'100' – 4 byte RX address field width
3
6
TX-address width (default value = 100).
'001' – 1 byte TX address field width
.
'100' – 4 byte TX address field width
RX-payload width (default value = 100000).
'000001' – 1 byte RX payload field width
'000010' – 2 byte RX payload field width
.
'100000' – 32 byte RX payload field width
TX_PW
6
TX-payload width (default value = 100000).
'000001' – 1 byte TX payload field width
'000010' – 2 byte TX payload field width
.
'100000' – 32 byte TX payload field width
RX_
ADDRESS
UP_CLK_
FREQ
32
2
RX address identity. Used bytes depend on RX_AFW (default value = E7E7E7E7h).
CPU clock frequency (default value = 11).
'00' – 4MHz
'01' – 2MHz
'10' – 1MHz
'11' – 500kHz
UP_CLK_
EN
1
3
CPU clock enable (default value = 1).
'0' – CPU using UP_CLK_FREQ frequency
'1' – CPU using XOF frequency
XOF
Crystal oscillator frequency. Must be set according to external crystal resonant-frequency.
'000' – 4MHz
'001' – 8MHz
'010' – 12MHz
'011' – 16MHz
'100' – 20MHz
(default value = 100)
CRC_EN
1
1
CRC – check enable (default value = 1).
'0' – Disable
'1' – Enable
CRC – mode (default value = 1).
'0' – 8 CRC check bit
CRC_
MODE
'1' – 16 CRC check bit
Table 22 RF configuration-register description.
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11.5 ADC - Configuration Register Description
Parameter
Bitwidth
Description
1
Positive edge of this signal will start one AD conversion when ADCRUN is
inactive. This bit is internally synchronized to the ADC clock
ADC running continuously when active.
CSTARTN is ignored in this case
CSTARTN
1
1
ADCRUN
Enable ADC
ADC_PWR_
UP
1
4
Select reference for AD converter
0: Use internal band gap reference (nominally 1.22V)
1: Use external pin AREF for reference (ignored if CHSEL=[1xxx]).
Cannel select input
0000: AIN0
VFSSEL
CHSEL
0001: AIN1
0010: AIN2
0011: AIN3
1xxx: internal VDD/3.
2
RESCTRL
Set A/D converter resolution:
00: 6 bit
01: 8 bit
10: 10 bit
11: 12 bit
1
1
Enable differential measurements, AIN0 must be used as inverting input and one of
the other inputs AIN1 to AIN3, as selected by ADCSEL, must be used as
noninverting input.
Select left or right justified data format:
0: Data will be left justified in ADC_DATA_REG
1: Data will be right justified in ADC_DATA_REG
DIFFMODE,
ADC_
RL_JUST
Table 23 ADC Configuration-register description.
11.6 Status-Register Description
Parameter
Bitwidth
Description
AM
1
Address Match, indicate that the receiver has received an address equal to its own
identity.
Detailed description in chapter 9.8.
CD
DR
1
1
1
3
Carrier Detect, indicates that a carrier is found on the receiving channel. Detailed
description in chapter 9.7
Data Ready, indicate that the receiver has received a data package with correct
address and CRC. Detailed description in chapter 9.9.
End Of Conversion, indicates that an AD conversion is completed and that data is
placed in ADC_DATA_REG.
Overflow indication in ADC
EOC
ADC_
RFLAG
RFLAG[2]: Underflow (ADCDATA = 0)
RFLAG[1]: Overflow (ADCDATA = 2N-1)
RFLAG[0]: Over range = RFLAG[1] or RFLAG[2]
Table 24 Status-register description.
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11.7 RF - Register Contents
RF-CONFIG_REGISTER (R/W)
Byte #
Content bit[7:0], MSB = bit[7]
Init value
0110_1100
0000_0000
0
1
CH_NO[7:0]
bit[7:6] not used, AUTO_RETRAN, RX_RED_PWR, PA_PWR[1:0],
HFREQ_PLL, CH_NO[8]
0100_0100
0010_0000
0010_0000
E7
2
3
4
5
6
7
8
9
bit[7] not used, TX_AFW[2:0] , bit[3] not used, RX_AFW[2:0]
bit[7:6] not used, RX_PW[5:0]
bit[7:6] not used, TX_PW[5:0]
RX_ADDRESS (device identity) byte 0
RX_ADDRESS (device identity) byte 1
RX_ADDRESS (device identity) byte 2
E7
E7
E7
RX_ADDRESS (device identity) byte 3
1110_0111
CRC_MODE,CRC_EN, XOF[2:0], UP_CLK_EN, UP_CLK_FREQ[1:0]
Table 25 RF config register contents.
TX_PAYLOAD (R/W)
Content bit[7:0], MSB = bit[7]
TX_PAYLOAD[7:0]
TX_PAYLOAD[15:8]
-
Byte #
Init value
X
X
X
X
X
X
0
1
-
-
30
31
-
TX_PAYLOAD[247:240]
TX_PAYLOAD[255:248]
Table 26 TX payload register contents.
TX_ADDRESS (R/W)
Content bit[7:0], MSB = bit[7]
TX_ADDRESS[7:0]
Byte #
Init value
E7
E7
0
1
2
3
TX_ADDRESS[15:8]
TX_ADDRESS[23:16]
TX_ADDRESS[31:24]
E7
E7
Table 27 TX address register contents.
RX_PAYLOAD (R)
Content bit[7:0], MSB = bit[7]
RX_PAYLOAD[7:0]
RX_PAYLOAD[15:8]
-
Byte #
Init value
X
X
X
0
1
X
X
X
-
30
31
RX_PAYLOAD[247:240]
RX_PAYLOAD[255:248]
Table 28 RX payload register contents.
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11.8 ADC Configuration Register Contents
ADC_CONFIG_REG (R/W)
Byte #
Content bit[7:0], MSB = bit[7]
Control: CHSEL[7:4], VFSSEL, PWR_UP, ADCRUN, CSTARTN
Static: bit[7:4] not used, ADC_RL_JUST, DIFFMODE, RESCTRL[1:0]
Init value
0000_0001
0000_0010
0
1
Table 29 ADC Configuration Register contents.
11.9 ADC Data Register Contents
ADC_DATA_REG (R)
Byte #
Content bit[7:0], MSB = bit[7]
Left or right justified data from ADC
Left or right justified data from ADC
Init value
0
1
X
X
Table 30 ADC DATA Register contents.
11.10Status Register Contents
STATUS_REGISTER (R)
Byte #
Content bit[7:0], MSB = bit[7]
Init value
0
AM, CD, DR, EOC, ADC_RFLAG[2:0], Even parity
X
Table 31 Status Register contents.
The length of all registers is fixed. However, the bytes in TX_PAYLOAD,
TM
RX_PAYLOAD, TX_ADDRESS and RX_ADDRESS used in ShockBurst
RX/TX
are set in the configuration register. Register content is not lost when the device enters
one of the power saving modes.
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12 TRANCEIVER SUBSYTEM TIMING
The following timing must be obeyed during nRF905 operation.
12.1 Device Switching Times
nRF905 timing
STBY è TX Shock Burst™
STBY è RX Shock Burst™
Max.
650 ms
650 ms
550 1ms
550 1ms
RX Shock Burst™ è TX Shock Burst™
TX Shock Burst™ è RX Shock Burst™
Notes to table:
1)
RX to TX or TX to RX switching is available without re-programming of the RF
configuration register. The same frequency channel is maintained.
Table 32 Switching times for nRF905.
12.2 ShockBurstTM TX Timing
MOSI
CSN
PWR_UP
TX_EN
TRX_CE
TX DATA
TIME
Programming of
Configuration Register
and TX Data Register
T0 T1
T2
T3
Transmitted Data 100kbps
Manchester Encoded
T0 = Radio Enabled
T1 = T0+10uS Minimum TRX_CE pulse
T2 = T0 + 650uS.Start of TX Data transmission
T3 = End of Data Packet, enter Standby mode
Figure 13 Timing diagram for standby to transmit.
After a data packet has finished transmitting the device will automatically enter Standby
mode and wait for the next pulse of TRX_CE. If the Auto Re-Transmit function is
enabled the data packet will continue re-sending the same data packet until TRX_CE is
set low.
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12.3 ShockBurstTM RX Timing
PWR_UP
TX_EN
TRX_CE
RX DATA
CD
AM
DR
650uS
TIME
650uS to enter RX
T0
T1
T2
T3
mode from
TRX_CE being set
high.
T0 = Receiver Enabled -Listening for Data
T1 = Carrier Detect finds a carrier
T2 = AM - Correct Address Found
T3 = DR - Data packet with correct Address/CRC
Figure 14 Timing diagram for standby to receiving.
After the Data Ready (DR) has been set high a valid data packet is available in the RX
data register. This may be clocked out in Standby mode. After the data has been clocked
out via the SPI interface the Data Ready (DR) and Address Match (AM) signals are reset
to low.
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13 SPI
nRF9E5 SPI is a simple single buffered master. The 3 data lines of the SPI bus (MISO,
SCK and MOSI) are multiplexed (by writing to register SPI_CTRL) between the GPIO
pins (lower 3 bits of P1) and the RF transceiver and AD converter subsystems. The SPI
hardware does not generate any chip select signal. The bootstrap loader uses EECSN
(GPIO P0.3) as chip select for the boot EEPROM. On-chip GPIO P2.3 is dedicated as
chip select for the RF transceiver and AD converter subsystems. GPIO pins from port 0
may be used as chip selects for other external SPI slaves.
The SPI hardware is controlled by SFR’s SPI_DATA (0xb2), SPI_CTRL (0xb3) and
SPICLK (0xb4) as explained in Table 33 below.
Addr
SFR
R/W #bit
Init
(hex)
Name
Function
(hex)
B2
B3
R/W
R/W
8
2
0
0
SPI_DATA
SPI_CTRL
SPI data input/output
00 -> SPI not used no clock generated
01 -> SPI connected to port P1 (as for booting)
(see also Table 11 Port 1 (P1) functions)
10 -> SPI connected to the nRF905 transceiver
(see Table 15 P2 (RADIO) register )
Divider factor from CPU clock to SPI clock
0000: 1/2 of CPU clock frequency
0001: 1/2 of CPU clock frequency
0010: 1/4 of CPU clock frequency
0011: 1/8 of CPU clock frequency
0100: 1/16 of CPU clock frequency
0101: 1/32 of CPU clock frequency
0110: 1/64 of CPU clock frequency
other: 1/64 of CPU clock frequency
B4
R/W
4
0
SPICLK
Table 33 SPI control and data SFR-registers.
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14 PWM
The nRF9E5 PWM output is a one-channel PWM with a 2 register interface. The first
register, PWMCON, enables PWM function and PWM period length, which is the
number of clock cycles for one PWM period, as shown in the table below. The other
register, PWMDUTY, controls the duty cycle of the PWM output signal. When this
register is written, the PWM signal will change immediately to the new value. This can
result in 4 transitions within one PWM period, but the transition period will always have
a “DC value” between the “old” sample and the “new” sample.
The table shows how PWM frequency (or period length) and PWM duty cycle are
controlled by the settings in the two PWM SFR-registers. For a crystal frequency of 16
MHz, PWM frequency range will be about 1-253 kHz.
PWMCON[7:6]
(Number of bits)
PWM frequency
PWMDUTY
(duty cycle)
00 (0)
01 (6)
10 (7)
11 (8)
0 (PWM module inactive)
1
0
PWMDUTY
63
5 : 0
f XO
×
(
[
]
)
63 × PWMCON 5 : 0 + 1
1
PWMDUTY
127
6 : 0
f XO
×
(
[
]
)
127 × PWMCON 5 : 0 + 1
PWMDUTY
1
f XO
×
(
[
]
)
255
255 × PWMCON 5 : 0 + 1
Table 34 PWM frequency and duty-cucle.
PWM is controlled by SFR 0xA9 and 0xAA.
Addr
SFR
R/W
#bit
Init
(hex)
Name
Function
(hex)
A9
R/W
8
0
PWMCON
PWM control register
7-6: Enable / period length select
00: Disable PWM
01: Period length is 6 bit
10: Period length is 7 bit
11: Period length is 8 bit
5-0: PWM frequency prescale factor
(see table above)
AA
R/W
8
0
PWMDUTY
PWM duty cycle (6 to 8 bits according to
period length)
Table 35 PWM control registers - SFR 0xA9 and 0xAA.
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15 INTERRUPTS
nRF9E5 supports the following interrupt sources:
Interrupt
signal
INT0_N
Natural
Priority
1
Interupt
Vector
0x03
Flag
Enable
Control
Description
TCON.1
IE.0
IP.0
External interrupt, active
low, configurable as edge-
sensitive or level-sensitive,
at Port P0.3
TF0
INT1_N
2
3
0x0B
0x13
TCON.5
TCON.3
IE.1
IE.2
IP.1
IP.2
Timer 0 interrupt
External interrupt, active
low, configurable as edge-
sensitive or level-sensitive,
at Port P0.4
TF1
TI or RI
4
5
0x1B
0x23
TCON.7
SCON.0
(RI),
IE.3
IE.4
IP.3
IP.4
Timer 1 interrupt
Receive/transmit interrupt
from Serial Port
SCON.1 (TI)
T2CON.7
(TF2),
TF2 or
EXF2
6
0x2B
IE.5
IP.5
Timer 2 interrupt
T2CON.6
(EXF2)
int2
int3
int4
int5
wdti
8
0x43
0x4B
0x53
0x5B
0x63
EXIF.4
EXIF.5
EXIF.6
EXIF.7
EICON.3
EIE.0
EIE.1
EIE.2
EIE.3
EIE.4
EIP.0
EIP.1
EIP.2
EIP.3
EIP.4
Internal ADC EOC (end of
AD conversion) interrupt
Internal SPI READY
interrupt
Internal Radio Data Ready
(DR) interrupt
Internal Radio Address
Match (AM) interrupt
Internal Wakeup (GPIO
wakeup and RTC timer)
interrupt
9
10
11
12
Table 36 nRF9E5 interrupt sources.
15.1 Interrupt SFRs
The following SFRs are associated with interrupt control:
- IE – SFR 0xA8 (Table 37)
- IP – SFR 0xB8 (Table 38)
- EXIF – SFR 0x91 (Table 39)
- EICON – SFR 0xD8 (Table 40)
- EIE – SFR 0xE8 (Table 41)
- EIP – SFR 0xF8 (Table 42)
The IE and IP SFRs provide interrupt enable and priority control for the standard
interrupt unit, as with industry standard 8051. The EXIF, EICON, EIE, and EIP registers
provide flags, enable control, and priority control for the extended interrupt unit.
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Table 37 explains the bit functions of the IE register.
Bit
Function
IE.7
EA • Global interrupt enable. Controls masking of all interrupts. EA = 0 disables all
interrupts (EA overrides individual interrupt enable bits). When EA = 1, each interrupt
is enabled or masked by its individual enable bit.
IE.6
IE.5
Reserved. Read as 0.
ET2 • Enable Timer 2 interrupt. ET2 = 0 disables Timer 2 interrupt (TF2). ET2 = 1
enables interrupts generated by the TF2 or EXF2 flag.
IE.4
IE.3
IE.2
IE.1
IE.0
ES • Enable Serial Port interrupt. ES = 0 disables Serial Port interrupts (TI and RI). ES
= 1 enables interrupts generated by the TI or RI flag.
ET1 • Enable Timer 1 interrupt. ET1 = 0 disables Timer 1 interrupt (TF1). ET1 = 1
enables interrupts generated by the TF1 flag.
EX1 • Enable external interrupt 1. EX1 = 0 disables external interrupt 1 (INT1_N). EX1
= 1 enables interrupts generated by the INT1_N pin.
ET0 • Enable Timer 0 interrupt. ET0 = 0 disables Timer 0 interrupt (TF0). ET0 = 1
enables interrupts generated by the TF0 flag.
EX0 • Enable external interrupt 0. EX0 = 0 disables external interrupt 0 (INT0_N). EX0
= 1 enables interrupts generated by the INT0_N pin.
Table 37 IE Register – SFR 0xA8.
Table 38 explains the bit functions of the IP register.
Bit
Function
IP.7
IP.6
IP.5
Reserved. Read as 1.
Reserved. Read as 0.
PT2 • Timer 2 interrupt priority control. PT2 = 0 sets Timer 2 interrupt (TF2) to low
priority. PT2 = 1 sets Timer 2 interrupt to high priority.
IP.4
IP.3
IP.2
IP.1
IP.0
PS • Serial Port interrupt priority control. PS = 0 sets Serial Port interrupt (TI or RI) to
low priority. PS = 1 sets Serial Port interrupt to high priority.
PT1 • Timer 1 interrupt priority control. PT1 = 0 sets Timer 1 interrupt (TF1) to low
priority. PT1 = 1 sets Timer 1 interrupt to high priority.
PX1 • External interrupt 1 priority control. PX1 = 0 sets external interrupt 1 (INT1_N)
to low priority. PT1 = 1 sets external interrupt 1 to high priority.
PT0 • Timer 0 interrupt priority control. PT0 = 0 sets Timer 0 interrupt (TF0) to low
priority. PT0 = 1 sets Timer 0 interrupt to high priority.
PX0 • External interrupt 0 priority control. PX0 = 0 sets external interrupt 0 (INT0_N)
to low priority. PT0 = 1 sets external interrupt 0 to high priority.
Table 38 IP Register – SFR 0xB8.
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Table 39 explains the bit functions of the EXIF register.
Bit
Function
EXIF.7
IE5 • Interrupt 5 flag. IE5 = 1 indicates that a rising edge was detected on the radio AM
signal (see P2). IE5 must be cleared by software. Setting IE5 in software generates an
interrupt, if enabled.
EXIF.6
EXIF.5
EXIF.4
IE4 • Interrupt 4 flag. IE4 = 1 indicates that a rising edge was detected on the radio DR
signal (see P2). IE4 must be cleared by software. Setting IE4 in software generates an
interrupt, if enabled.
IE3 • Interrupt 3 flag. IE3 = 1 indicates that the internal SPI module has sent or received
8 bits, and is ready for a new command. IE3 must be cleared by software. Setting IE3 in
software generates an interrupt, if enabled.
IE2 • Interrupt 2 flag. IE2 = 1 indicates that a rising edge was detected on the ADC’s
EOC signal (see chapter 10 ). IE2 must be cleared by software. Setting IE2 in software
generates an interrupt, if enabled.
EXIF.3
Reserved. Read as 1.
EXIF.2•0
Reserved. Read as 0.
Table 39 EXIF Register – SFR 0x91.
Table 40 explains the bit functions of the EICON register.
Bit
Function
EICON.7
EICON.6
EICON.5
EICON.4
EICON.3
Not used.
Reserved. Read as 1.
Reserved. Read as 0.
Reserved. Read as 0.
WDTI • Wakeup (GPIO wakeup and RTC timer) interrupt flag. WDTI = 1 indicates a
wakeup event interrupt was detected. WDTI must be cleared by software before
exiting the interrupt service routine. Otherwise, the interrupt occurs again. Setting
WDTI in software generates a wakeup event interrupt, if enabled.
EICON.2•0
Reserved. Read as 0.
Table 40 EICON Register – SFR 0xD8.
Table 41 explains the bit functions of the EIE register.
Bit
Function
EIE.7•5
EIE.4
Reserved. Read as 1.
EWDI • Enable RTC wakeup timer interrupt. EWDI = 0 disables wakeup timer
interrupt (wdti). EWDI = 1 enables interrupts generated by wakeup.
EX5 • Enable interrupt 5. EX5 = 0 disables interrupt 5 (radio AM (address match)).
EX5 = 1 enables interrupts generated by the radio AM signal.
EX4 • Enable interrupt 4. EX4 = 0 disables interrupt 4 (radio DR (data ready)). EX4 = 1
enables interrupts generated by the radio DR signal.
EX3 • Enable interrupt 3. EX3 = 0 disables interrupt 3 (SPI READY). EX3 = 1 enables
interrupts generated by the SPI READY signal.
EX2 • Enable interrupt 2. EX2 = 0 disables interrupt 2 (ADC EOC). EX2 = 1 enables
interrupts generated by the ADC EOC signal.
EIE.3
EIE.2
EIE.1
EIE.0
Table 41 EIE Register – SFR 0xE8.
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Table 42 explains the bit functions of the EIP register.
Bit
Function
EIP.7•5
EIP.4
Reserved. Read as 1.
PWDI • Wakeup interrupt priority control. WDPI = 0 sets the wakeup interrupt (wdti)
to low priority. PS = 1 sets wakeup timer interrupt to high priority.
PX5 • interrupt 5 priority control. PX5 = 0 sets interrupt 5 (radio AM) to low priority.
PX5 = 1 sets interrupt 5 to high priority.
PX4 • interrupt 4 priority control. PX4 = 0 sets interrupt 4 (radio DR) to low priority.
PX4 = 1 sets interrupt 4 to high priority.
PX3 • interrupt 3 priority control. PX3 = 0 sets interrupt 3 (SPI READY) to low
priority. PX3 = 1 sets interrupt 3 to high priority.
PX2 • interrupt 2 priority control. PX2 = 0 sets interrupt 2 (ADC EOC) to low priority.
PX2 = 1 sets interrupt 2 to high priority.
EIP.3
EIP.2
EIP.1
EIP.0
Table 42 EIP Register – SFR 0xF8.
15.2 Interrupt Processing
When an enabled interrupt occurs, the CPU vectors to the address of the interrupt
service routine (ISR) associated with that interrupt, as listed in Table 36. The CPU
executes the ISR to completion unless another interrupt of higher priority occurs. Each
ISR ends with an RETI (return from interrupt) instruction. After executing the RETI, the
CPU returns to the next instruction that would have been executed if the interrupt had
not occurred.
An ISR can only be interrupted by a higher priority interrupt. That is, an ISR for a low-
level interrupt can be interrupted only by a high-level interrupt. The CPU always
completes the instruction in progress before servicing an interrupt. If the instruction in
progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, the CPU
completes one additional instruction before servicing the interrupt.
15.3 Interrupt Masking
The EA bit in the IE SFR (IE.7) is a global enable for all interrupts. When EA = 1, each
interrupt is enabled/masked by its individual enable bit. When EA = 0, all interrupts are
masked. Table 36 provides a summary of interrupt sources, flags, enables, and priorities.
15.4 Interrupt Priorities
There are two stages of interrupt priority assignment: interrupt level and natural priority.
The interrupt level (high, or low) takes precedence over natural priority. All interrupts
can be assigned either high or low priority. In addition to an assigned priority level (high
or low), each interrupt has a natural priority, as listed in Table 36. Simultaneous
interrupts with the same priority level (for example, both high) are resolved according to
their natural priority. For example, if INT0_N and int2 are both programmed as high
priority, INT0_N takes precedence. Once an interrupt is being serviced, only an interrupt
of higher priority level can interrupt the service routine of the interrupt currently being
serviced.
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15.5 Interrupt Sampling
The internal timers and serial port generate interrupts by setting their respective SFR
interrupt flag bits. The CPU samples external interrupts once per instruction cycle, at the
rising edge of CPU_clk at the end of cycle C4.
The INT0_N and INT1_N signals are both active low and can be programmed through
the IT0 and IT1 bits in the TCON SFR to be either edge-sensitive or level-sensitive. For
example, when IT0 = 0, INT0_N is level-sensitive and the CPU sets the IE0 flag when
the INT0_N pin is sampled low. When IT0 = 1, INT0_N is edge-sensitive and the CPU
sets the IE0 flag when the INT0_N pin is sampled high then low on consecutive
samples. To ensure that edge-sensitive interrupts are detected, the corresponding ports
should be held high for four clock cycles and then low for four clock cycles. Level-
sensitive interrupts are not latched and must remain active until serviced.
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15.6 Interrupt Latency
Interrupt response time depends on the current state of the CPU. The fastest response
time is five instruction cycles: one to detect the interrupt, and four to perform the
LCALL to the ISR. The maximum latency (thirteen instruction cycles) occurs when the
CPU is currently executing an RETI instruction followed by a MUL or DIV instruction.
The thirteen instruction cycles in this case are: one to detect the interrupt, three to
complete the RETI, five to execute the DIV or MUL, and four to execute the LCALL to
the ISR.
For the maximum latency case, the response time is 13 x 4 = 52clock cycles.
15.7 Interrupt Latency from Power Down State.
The nRF9E5 may be set into Power Down state by writing a non zero value to SFR
0xB6, register CK_CTRL. The CPU will then perform a controlled shutdown of clock
and power regulator depending on what mode was selected. The system can only be
restarted from an RTC wakeup, a GPIO wakeup or a Watchdog reset. If a wakeup
interrupt is enabled, the startup time for regulators and clocks will be added to the
interrupt latency. See 17.2.1 Startup Time From Reset
15.8 Single-Step Operation
The nRF9E5 interrupt structure provides a way to perform single-step program
execution. When exiting an ISR with an RETI instruction, the CPU will always execute
at least one instruction of the task program. Therefore, once an ISR is entered, it cannot
be re-entered until at least one program instruction is executed. To perform single-step
execution, program one of the external interrupts (for example, INT0_N) to be level
sensitive and write an ISR for that interrupt that terminates as follows:
JNB TCON.1,$ ;
JB TCON.1,$ ;
RETI ;
wait for high on INT0_N
wait for low on INT0_N
return for ISR
The CPU enters the ISR when INT0_N goes low, then waits for a pulse on INT0_N.
Each time INT0_N is pulsed, the CPU exits the ISR, executes one program instruction,
then re-enters the ISR.
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16 LF CLOCK WAKEUP FUNCTIONS AND WATCHDOG
16.1 The LF Clock
The nRF9E5 contains has an internal low frequency clock CKLF that is always active.
When the crystal oscillator clocks the circuit, the CKLF is a 4kHz clock derived from
the crystal oscillator (provided the CKLFCON register is set according to crystal
frequency and prescaler. XOF and UP_CLK_FREQ respectively, see Table 22). When
no crystal oscillator clock is available, the CKLF is a low power RC oscillator
(LP_OSC) that cannot be disabled, so it will run continuously as long as VDD = 1.8V.
The microprocessor can determine the phase of the CKLF clock by reading CK_CTRL
SFR 0xB6, see Table 50.
16.2 Tick Calibration
The “TICK” is an interval (in CKLF periods) that determines the resolution of the
watchdog and the RTC wakeup timer. The tick is nominally 1ms (4 CKLF cycles).
When the CPU is active and in power down modes where the chip still has crystal clock,
the “TICK” will be as accurate as the crystal oscillator. When the CKLF switches to the
RC oscillator (LP_OSC) in deep power down modes, the tick will no longer be accurate.
The LP_OSC clock source is very inaccurate, and may vary from 0.5ms to 3ms
depending production lot, temperature and supply voltage. That means that Watchdog
and RTC wakeup may not be used for any accurate timing functions if these power
down modes are used.
The accuracy can be improved by calibrating the TICK value at regular intervals. The
register TICK_DV controls how many LP_OSC periods elapse between each TICK. The
frequency of the LP_OSC (between 1 kHz and 5 kHz) can be measured by timer2 in
capture mode with t2ex enabled (EXEN2=1). The signal connected to t2ex has exactly
half the frequency of LP_OSC. The 16-bit difference between two consecutive captures
in SFR-registers{RCAP2H,RCAP2L} is proportional to the LP_OSC period. For details
about timer2 see ch. 18.8.3 and Figure 21 Timer 2 – Timer/Counter with Capture
TICK is controlled by SFRs 0xB5 and 0xBF
Addr
SFR
R/W #bit
Init
Hex
Name
Function
B5
R/W
R/W
8
6
03
TICK_DV
Divider that’s used in generating TICK from CKLF
frequency.
TTICK = (1 + TICK_DV) / fCKLF
The default value gives a TICK of 1ms nominal as
default (with CKLF derived from crystal oscillator).
BF
27
CKLFCON Configure CKLF generation with crystal frequency
and prescaler value. Note this register only controls the
generation of CKLF, not the actual prescaler values.
5-3: Should be set equal to XOF, Table 22
2: Should be set equal to UP_CLK_EN, Table 22
1-0: Should be set equal to UP_CLK_FREQ, Table 22
Table 43 TICK control register - SFR 0xB5.
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16.3 RTC Wakeup Timer
The RTC is a simple 24 bit down counter that produces an optional interrupt and reloads
automatically when the count reaches zero. This process is initially disabled, and will be
enabled with the first write to the lower 16 bit of the timer latch. Writing the lower 16
bits of the timer latch will always be followed by a reload of the counter. Writing the
upper 8 bit of the timer latch should only be done when the timer is disabled. The
counter may be disabled again by writing a disable opcode to the control register. Both
the latch and the counter value may be read by giving the respective codes in the control
register, see description in Table 45.
This counter is used for a wakeup sometime in the future (a relative time wakeup call).
If ‘N’ is written to the counter, the first wakeup will happen from somewhere between
‘N+1’ and ‘N+2’ “TICK” from the completion of the write, thereafter a new wakeup is
issued every “N+1” "TICK" until the unit is disabled or another value is written to the
latch.
The wakeup timer is one of the sources that can generate a WDTI interrupt to the CPU.
The programmer may poll the EICON.3 flag or enable the interrupt. If the device is in a
power down state, the wakeup will force the device to exit power down regardless of the
state of EIE.4 interrupt enable.
The nRF9E5 do not provide any “absolute time functions”. Absolute time functions in
nRF9E5 can well be handled in software since the RAM is continuously powered even
when in sleep mode.
16.4 Programmable GPIO Wakeup Function
Any number of the pins in port 0 may be used as wakeup signals for the nRF9E5. The
device may be programmed to react on either rising or falling or both edges of each pin
individually. Additionally each pin is equipped with a programmable “filter” that can be
used for glitch suppression.
CKLF
P0x
Wakeup P0x
DEBOUNCE
[1:0]
EDGE
[3:2]
WWCON
Figure 15 Wakeup filter, each pin for GPIO wakeup function.
The debounce act as a low pass filter. The input has to be stable for a number of clock
pulses given for the corresponding change to appear on the output. Edge triggers on
either positive, negative or both edges. The edge delay is 2 clock cycles. Please see
Table 44 and Table 47 for filter configuration.
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Filter selection Debounce
WCON [1:0] Number of clock pulses
Edge detector selection
WCON [3:2]
pos / neg trigger
00
01
10
11
0
2
8
00
01
10
11
Off
Pos
Neg
Both
64
Table 44 GPIO wakeup filter configuration.
16.5 Watchdog
The watchdog is activated on the first write to its control register SFR 0xAD. It can not
be disabled by any other means than a reset. The watchdog register is loaded by writing
a 16-bit value to the two 8-bit data registers (SFR 0xAB and 0xAC) and then the writing
the correct opcode to the control register. The watchdog will then count down towards 0
and when 0 is reached the complete microcontroller will be reset To avoid the reset, the
software must load new values into the watchdog register sufficiently often.
16.6 Programming Interface to Watchdog and Wakeup Functions
Figure 16 shows how the blocks that are always active are connected to the CPU. RTC
timer GPIO wakeup and Watchdog are controlled via SFRs 0xAB, 0xAC and 0xAD.
These 3 registers REGX_MSB, REGX_LSB and REGX_CTRL are used to interface the
blocks running on the slow CKLF clock. The 16-bit register {REGX_MSB,
REGX_LSB} can be written or read as two bytes from the CPU.
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Typical sequences are:
Write: Wait until REGX_CRTL.4 == 0 (i.e. not busy)
Write REGX_MSB, Write REGX_LSB, Write REGX_CTRL
Read: Wait until REGX_CRTL.4 == 0 (i.e. not busy)
Write REGX_CTRL, Wait until REGX_CRTL.4 == 0 (i.e. not busy)
Read REGX_MSB, Read REGX_LSB
Note : Please wait until not busy before accessing SFR 0xB6 CK_CTRL (page 58)
8-bit CPU
register
REGX_CTRL
8-bit CPU
register
REGX_MSB
8-bit CPU
register
REGX_LSB
Clocked on CPU clock
16-BIT BUS
Clocked
on CKLF
8+16-BIT
REGISTER
Load
TIMER_LATCH
Load
CE
Load
CE
Load
16-BIT
DOWN
24-BIT
DOWN
GPIO
WAKEUP
P1 GPIO
IO
COUNTER
COUNTER
RTC
INT
Zero
Zero
WAKEUP INT
TICK
WATCHDOG_RESET
Figure 16 Block diagram of wakeup and watchdog function.
Table 45 below describe the functions of the SFR registers that control these blocks, and
Table 46 and Table 47 explains the contents of the individual control registers for
watchdog and wakeup functions.
Addr
SFR
(hex)
R/W
R/W
R/W
R/W
#bit
8
Init
Hex
Name
Function
AB
AC
AD
00
REGX_MSB
REGX_LSB
REGX_CTRL
Most significant part of 16 bit register for
interface to Watchdog, RTC timer and GPIO
wakeup
Least significant part of 16 bit register for
interface to Watchdog, RTC timer and GPIO
wakeup
8
00
00
5
Control for 16 bit register for transfers to and
from Watchdog, RTC timer and GPIO wakeup.
4: REGX interface busy (read only).
3: Read (0) / Write (1)
2-0: Indirect address, see leftmost column in
Table 46
Table 45 Wakeup, RTC timer and Watchdog SFR-registers.
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Addr
Ctrl
[2:0]
R/W
Ctrl
[3]
#bit
Init
Hex
Name
Function
0
1
16
16
0000
0000
RWD
Watchdog register (count)
Watchdog register (count)
0
1
WWD
0
16
0000
RGTIMER
15-8: MSB part of RTC counter
7-0: MSB part of RTC latch
1
0
12
16
000
WGTIMER
RRTCLAT
11-8: GTIMER latch
7-0: MSB part of RTC latch
Least significant part of RTC latch
0000
2
3
1
0
1
16
16
0
0000
0000
-
WRTCLAT
RRTC
Least significant part of RTC latch
RTC counter value
WRTCDIS
Disable RTC (data not used)
0
9
000
RWSTA0
Wakeup status
Bit 8: RTC timer status
7-0: Wakeup status for pins P07-P00
4
5
1
16
0000
WWCON0
GPIO wakeup configuration for
P03-P00. See Table 47.
Wakeup status (Identical to WSTA0)
GPIO wakeup configuration for
P07-P04. See Table 47.
0
1
9
16
000
0000
RWSTA1
WWCON1
Table 46 Indirect addresses and functions.
Bits
WWCON1 function
WWCON0 unction
Edge selection for P03
Edge filter for P03
Edge selection for P02
Edge filter for P02
Edge selection for P01
Edge filter for P01
Edge selection for P00
Edge filter for P00
15:14 Edge selection for P07
13:12 Edge filter for P07
11:10 Edge selection for P06
9:8
7:6
5:4
3:2
1:0
Edge filter for P06
Edge selection for P05
Edge filter for P05
Edge selection for P04
Edge filter for P04
Table 47 Bit fields in register WWCON1 and WWCON0.
16.7 Reset
The nRF9E5 can be reset either by the on-chip power-on reset circuitry or by the on-
chip watchdog counter.
16.7.1 Power-on Reset
The power-on reset circuitry keeps the chip in power-on-reset state until the supply
voltage reaches VDDmin (a voltage, less than 1.9V sufficiently high for digital
operation). At this point the internal voltage generators and oscillators start up, the SFRs
are initialized to their reset values, as listed in Table 62, and thereafter the CPU begins
program execution at the standard reset vector address 0x0000. The startup time from
power-on reset is normally determined by both the crystal oscillator startup time and the
frequency of the low power oscillator (LP_OSC). This total may vary from 1 to 3 ms
depending on processing, temperature and supply voltage.
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16.7.2 Watchdog Reset
If the Watchdog reset signal goes active, nRF9E5 enters the same reset sequence as for
power-on reset. That is, the internal voltage generators and oscillators start up, the SFRs
are initialized to their reset values, as listed in Table 62, and thereafter the CPU begins
program execution at the standard reset vector address 0x0000. The startup time from
watchdog reset is somewhat shorter; expect a variation from 0.4 to 2ms depending on
processing, temperature and supply voltage.
16.7.3 Program Reset Address
The program reset address is controlled by the RSTREAS register, SFR 0xB1, see Table
48This register shows which reset source that caused the last reset, and provides a
choice of two different program start addresses. The default value is power-on reset,
which starts the boot loader, while a watchdog reset does not reboot and restarts at
address 0 of the already loaded program.
Addr
SFR
R/W
#bit
Init
(hex)
Name
Function
(hex)
B1
R/W
2
02
RSTREAS
bit 0: Reason for last reset
0: POR
1: Any other reset source
Clear this bit in software to force a
reboot after jump to zero (boot loader
will load code RAM if this bit is 0)
bit 1: Use IROM for reset vector
0: Reset vectors to 0x0000.
1: Reset vectors to 0x8000.
Table 48 Reset control register - SFR 0xB1.
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17 POWER SAVING MODES
nRF9E5 provides the two industry standard 8051 power saving modes: idle mode and
stop mode. To Achieve more power saving several additional power-down modes are
provided, where both oscillator and internal power regulators may be turned off.
The bits that control entry into idle and stop modes are in the PCON register at SFR
address 0x87, listed in Table 49. The bits that control entry into power down mode are in
the CK_CTRL register at SFR address 0xB6, listed in Table 51.
Bit
Function
PCON.7
SMOD – Serial Port baud-rate doubler enable. When SMOD = 1, the baud rate for
Serial Port is doubled.
PCON.6–4
PCON.3
Reserved.
GF1 – General purpose flag 1. Bit-addressable, general purpose flag for software
control.
PCON.2
GF0 – General purpose flag 0. Bit-addressable, general purpose flag for software
control.
PCON.1
PCON.0
STOP – Stop mode select. Setting the STOP bit places the nRF9E5 in stop mode.
IDLE – Idle mode select. Setting the IDLE bit places the nRF9E5 in idle mode.
Table 49 PCON Register – SFR 0x87.
17.1 Standard 8051 Power Saving Modes
17.1.1 Idle Mode
An instruction that sets the IDLE bit (PCON.0) causes the nRF9E5 to enter idle mode
when that instruction completes. In idle mode, CPU processing is suspended and internal
registers and memory maintain their current data. However, unlike the standard 8051,
the CPU clock is not disabled internally, thus not much power is saved.
There are two ways to exit idle mode: activate any enabled interrupt or watchdog reset.
Activation of any enabled interrupt causes the hardware to clear the IDLE bit and
terminate idle mode. The CPU executes the ISR associated with the received interrupt.
The RETI instruction at the end of the ISR returns the CPU to the instruction following
the one that put the nRF9E5 into idle mode. A watchdog reset causes the nRF9E5 to exit
idle mode, reset internal registers, execute its reset sequence and begin program
execution at the standard reset vector address 0x0000.
17.1.2 Stop Mode
An instruction that sets the STOP bit (PCON.1) causes the nRF9E5 to enter stop mode
when that instruction completes. Stop mode is identical to idle mode, except that the
only way to exit stop mode is by watchdog reset Since there is little power saving, stop
mode is not recommended, as it is more efficient to use power down mode.
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17.2 Additional Power Down Modes
An instruction that sets the CK_CTRL (SFR 0xB6) to a non zero value causes the
nRF9E5 to enter power down mode when that instruction completes. In power down
mode, CPU processing is suspended, while internal registers and memories maintain
their current data. The CPU will perform a controlled shutdown of clock and power
regulators as requested by CK_CTRL.
The device can only be restarted from an event on a P0 GPIO pin, an RTC wakeup or a
Watchdog reset. Activation of any enabled wakeup source causes the hardware to clear
the CK_CTRL bit and terminate power down mode. If there is an enabled interrupt
associated with the wakeup even, the CPU executes the ISR associated with that
interrupt immediately after power and clocks are restored. The RETI instruction at the
end of the ISR returns the CPU to the instruction following the one that put the nRF9E5
into power down mode. A watchdog reset causes the nRF9E5 to exit power down mode,
reset internal registers, execute its reset sequence and begin program execution at the
standard reset vector address 0x0000.
Addr
SFR
R/W #bit
Init
Hex
Name
Function
B6
W
R
3
1
0
-
CK_CTRL
CK_CTRL
Set power down according to Table 51.
Read LFCK clock in LSB. Other bits are
unpredictable.
Table 50 CK_CTRL register – SFR 0xB6.
Note: Before writing the CK_CTRL register, make sure that the busy bit of
RTC/Watchdog SFR 0xAD, bit 4 (page 54) is not set
Note: When using power down modes where the CKLF source is LP_OSC, the startup
time may be so long that the CPU may loose the corresponding interrupt.
CK_CTRL
(write)
Function
CKLF
source
XTAL Typical
Osc Current Startup
On
Typical
000
001
010
011
1--
Normal operation, active
Light power down
Moderate power down
Standby mode
XTAL
XTAL
XTAL
LP_OSC
LP_OSC
1 mA
0.4 mA
125 µA
25 µA
-
On
On
On
Off
2.5 µs
7 µs
150 µs
1000 µs
Deep power down
2.5 µA
Table 51 Power down modes.
The table above shows typical startup time from interrupt. For GPIO the debounce time
must be added, but during debounce the device is still in power down.
17.2.1 Startup Time From Reset
Startup time consists of a number of LP_OSC cycles + a number of XTAL clock
cycles. fLP_OSC may vary from 1 to 5.5kHz over voltage and temperature.
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Startup times are summarized in the table below:
Reason of startup
Power on
Phase I
(power and Clock)
Phase II
(Initialization and
synchronization)
The longest of:
XO start-up time (3ms max)
2500 fXTAL cycles
0-1 LP_OSC cycles
The longest of:
2500 fCPU cycles
0-1 LP_OSC cycles
Watchdog
XO start-up time if
not already running
Table 52 Startup times from Power down mode.
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18 MICROCONTROLLER
The embedded microcontroller is the DW8051 MacroCell from Synopsys which is
similar to the Dallas DS80C320 in terms of hardware features and instruction-cycle
timing.
18.1 Memory Organization
FFFFh
81FFh
Boot loader
8000h
IRAM
SFR
FFh
Upper
128
FFh
80h
Accessible by
indirect
addressing only.
Accessible by
direct addressing
only.
bytes.
80h
7Fh
0FFFh
0000h
Program/data memory.
Accessible with movc and
movx.
Accessible by
direct and indirect
addressing.
Lower
128
bytes.
Special
Function
Registers
00h
Program memory/Data
Memory (ERAM)
Internal Data Memory
Figure 17 Memory Map and Organization.
18.1.1 Program Memory/Data Memory
The nRF9E5 has 4KB of program memory available for user programs located at the
bottom of the address space as shown in Figure 17. This memory also function as a
random access memory and can be accessed with the movx and movc instructions.
After power on reset the boot loader loads the user program from the external serial
EEPROM and stores it from address 0 in this memory.
18.1.2 Internal Data Memory
The Internal Data Memory, illustrated in Figure 17, consists of:
·
·
·
128 bytes of registers and scratchpad memory accessible through direct or indirect
addressing (addresses 0x00–0x7F).
128 bytes of scratchpad memory accessible through indirect addressing (0x80–
0xFF).
128 special function registers (SFRs) accessible through direct addressing.
The lower 32 bytes form four banks of eight registers (R0–R7). Two bits on the program
status word (PSW) select which bank is in use. The next sixteen bytes form a block of
bit-addressable memory space at bit addresses 0x00–0x7F. All of the bytes in the lower
128 bytes are accessible through direct or indirect addressing. The SFRs and the upper
128 bytes of RAM share the same address range (0x80-0xFF). However, the actual
address space is separate and is differentiated by the type of addressing. Direct
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addressing accesses the SFRs, while indirect addressing accesses the upper 128 bytes of
RAM. Most SFRs are reserved for specific functions, as described in 18.6 Special
Function Registers on page 69. SFR addresses ending in 0h or 8h are bit-addressable.
18.2 Program Format in External EEPROM
The table below shows the layout of the first few bytes of the EEPROM image.
7
6
5
4
3
2
1
0
0:
Version
(now 00)
Reserved
(now 00)
SPEED
XO_FREQ
1:
Offset to start of user program (N)
2:
Number of 256 byte blocks in user program (includes block 0 that is not full)
…
…
N:
Optional User data, not interpreted by boot loader
…
First byte of user program, goes into ERAM at 0x0000
N+1:
Second byte of user program, goes into ERAM at 0x0001
…
Table 53 EEPROM layout.
The contents of the 4 lowest bits in the first byte is used by the boot loader to set the
correct SPI frequency. These fields are encoded as shown below:
SPEED (bit 3): EEPROM max speed
0 = 1MHz
1 = 0.5MHz
XO_FREQ (bits 2,1 and 0): Crystal oscillator frequency
000 = 4MHz,
001 = 8MHz,
010 = 12MHz,
011 = 16MHz,
100 = 20MHz
The program eeprep1 can be used to add this header to a program file.
Command format: eeprep [options] <infile> <outfile>
<infile> is the output file of an assembler or compiler
<outfile> is a file suitable for programming the EEPROM (above format with no user
data).
Both files are “Intelhex” format.
The options available for eeprep are:
-c n
-i
Set crystal frequency in MHz.
Ignore checksums
-p n Set program memory size (default 4096 bytes)
-s Select slow EEPROM clock (500KHz)
1
Available on www.nordicsemi.no
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18.3 Instruction Set
All nRF9E5 instructions are binary-code–compatible and perform the same functions
that they do in the industry standard 8051. The effects of these instructions on bits, flags,
and other status functions is identical to the industry-standard 8051. However, the timing
of the instructions is different, both in terms of number of clock cycles per instruction
cycle and timing within the instruction cycle.
Table 55 to Table 60 lists the nRF9E5 instruction set and the number of instruction
cycles required to complete each instruction.
Symbol
Function
A
Accumulator
Rn
Register R0–R7
direct
@Ri
rel
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two’s complement offset byte
Direct bit address
bit
#data
#data 16
addr 16
addr 11
8-bit constant
16-bit constant
16-bit destination address
11-bit destination address
Table 54 Legend for Instruction Set Table.
Table 55 to Table 60 define the symbols and mnemonics used in Table 54.
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Arithmetic Instructions
Mnemonic
Description
Byte
Instr.
Hex
Cycles
Code
ADD A, Rn
Add register to A
Add direct byte to A
Add data memory to A
Add immediate to A
Add register to A with carry
Add direct byte to A with carry
Add data memory to A with carry
Add immediate to A with carry
Subtract register from
borrow
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
28–2F
25
26–27
24
38–3F
35
36–37
34
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
A
with
98–9F
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
Subtract direct byte from A with
borrow
Subtract data memory from A with
borrow
Subtract immediate from A with
borrow
2
1
2
2
1
2
95
96–97
94
INC A
INC Rn
Increment A
Increment register
1
1
2
1
1
1
2
1
1
1
1
1
1
1
2
1
1
1
2
1
3
5
5
1
04
08–0F
05
06–07
14
18–1F
15
16–17
A3
A4
84
D4
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Increment direct byte
Increment data memory
Decrement A
Decrement register
Decrement direct byte
Decrement data memory
Increment data pointer
Multiply A by B
Divide A by B
Decimal adjust A
All mnemonics are copyright © Intel Corporation 1980.
Table 55 nRF9E5 Instruction Set, Arithmetic Instructions.
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Logical Instructions
Mnemonic
Description
Byte
Instr.
Hex
Cycles
Code
ANL A, Rn
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
58–5F
55
56–57
54
52
53
48–4F
45
46–47
44
42
43
68–6F
65
66–67
64
62
63
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
AND direct byte to A
AND data memory to A
AND immediate to A
AND A to direct byte
AND immediate data to direct byte
OR register to A
OR direct byte to A
OR data memory to A
OR immediate to A
OR A to direct byte
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR data memory to A
Exclusive-OR immediate to A
Exclusive-OR A to direct byte
Exclusive-OR immediate to direct
byte
CLR A
CPL A
SWAP A
RL A
RLC A
RR A
Clear A
Complement A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
1
1
1
1
1
1
1
1
1
1
1
1
1
1
E4
F4
C4
23
33
03
13
RRC A
All mnemonics are copyright © Intel Corporation 1980.
Table 56 nRF9E5 Instruction Set, Logical Instructions.
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Boolean Instructions
Mnemonic
Description
Byte
Instr.
Hex
Cycles
Code
CLR C
CLR bit
SETB C
SETB bit
CPL C
Clear carry
Clear direct bit
Set carry
Set direct bit
Complement carry
Complement direct bit
AND direct bit to carry
AND direct bit inverse to carry
OR direct bit to carry
OR direct bit inverse to carry
Move direct bit to carry
Move carry to direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
2
1
2
1
2
2
2
2
2
2
2
C3
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
All mnemonics are copyright © Intel Corporation 1980.
Table 57 nRF9E5 Instruction Set, Boolean Instructions.
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Data Transfer Instructions
Mnemonic
Description
Byte
Instr.
Hex
Cycles
Code
MOV A, Rn
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
3
E8–EF
E5
E6–E7
74
F8–FF
A8–AF
78–7F
F5
88–8F
85
86–87
75
F6–F7
A6–A7
76–77
90
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
Move direct byte to A
Move data memory to A
Move immediate to A
Move A to register
Move direct byte to register
Move immediate to register
Move A to direct byte
Move register to direct byte
MOV direct, direct Move direct byte to direct byte
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
MOV @Ri, direct
MOV @Ri, #data
Move data memory to direct byte
Move immediate to direct byte
Move A to data memory
Move direct byte to data memory
Move immediate to data memory
MOV DPTR, #data Move immediate to data pointer
MOVC
A, Move code byte relative DPTR to A
93
@A+DPTR
MOVC A, @A+PC Move code byte relative PC to A
1
1
1
3
2–9*
2–9*
83
E2–E3
E0
MOVX A, @Ri
MOVX
Move external data (A8) to A
A, Move external data (A16) to A
@DPTR
MOVX @Ri, A
MOVX @DPTR, Move A to external data (A16)
A
Move A to external data (A8)
1
1
2–9*
2–9*
F2–F3
F0
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
XCHD A, @Ri
Push direct byte onto stack
Pop direct byte from stack
Exchange A and register
Exchange A and direct byte
Exchange A and data memory
2
2
1
2
1
1
2
2
1
2
1
1
C0
D0
C8–CF
C5
C6–C7
D6–D7
Exchange
nibble
A and data memory
All mnemonics are copyright © Intel Corporation 1980.
Table 58 nRF9E5 Instruction Set, Data Transfer Instructions.
* Number of cycles is 2 + CKCON.2-0. (CKCON.2-0 is the integer value of the 3LSB
of SFR 0x8E CKCON). Default is 3 cycles.
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Branching Instructions
Mnemonic
Description
Byte
Instr.
Hex
Cycles
Code
ACALL addr 11
LCALL addr 16
RET
Absolute call to subroutine
Long call to subroutine
Return from subroutine
Return from interrupt
Absolute jump unconditional
Long jump unconditional
Short jump (relative address)
Jump on carry = 1
Jump on carry = 0
Jump on direct bit = 1
Jump on direct bit = 0
Jump on direct bit = 1 and clear
Jump indirect relative DPTR
Jump on accumulator = 0
Jump on accumulator /= 0
2
3
1
1
2
3
2
2
2
3
3
3
1
2
2
3
3
3
4
4
4
3
4
3
3
3
4
4
4
3
3
3
4
4
11–F1
12
22
32
01–E1
02
80
40
50
20
30
10
73
60
70
B5
B4
RETI
AJMP addr 11
LJMP addr 16
SJMP rel
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel Compare A, direct JNE relative
CJNE A, #d, rel
Compare A, immediate JNE
relative
CJNE Rn, #d, rel
Compare reg, immediate JNE
relative
3
3
4
4
B8–BF
B6–B7
CJNE @Ri, #d, rel Compare ind, immediate JNE
relative
DJNZ Rn, rel
DJNZ direct, rel
Decrement register, JNZ relative
Decrement direct byte, JNZ relative
2
3
3
4
D8–DF
D5
All mnemonics are copyright © Intel Corporation 1980.
Table 59 nRF9E5 Instruction Set, Branching Instructions.
Miscellaneous Instructions
Mnemonic
Description
Byte
Instr.
Hex
Cycles
Code
NOP
No operation
1
1
00
There is an additional reserved opcode (A5) that will also act as a NOP.
All mnemonics are copyright © Intel Corporation 1980.
Table 60 nRF9E5 Instruction Set, Miscellaneous Instructions.
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18.4 Instruction Timing
Instruction cycles in the nRF9E5 are four clock cycles in length, as opposed to twelve
clock cycles per instruction cycle in the standard 8051. This translates to a 3X
improvement in execution time for most instructions. However, some instructions
require a different number of instruction cycles on the nRF9E5 than they do on the
standard 8051. In the standard 8051, all instructions except for MUL and DIV take one
or two instruction cycles to complete. In the nRF9E5 architecture, instructions can take
between one and five instruction cycles to complete. For example, in the standard 8051,
the instructions MOVX A, @DPTR and MOV direct, direct each take two instruction
cycles (twenty-four clock cycles) to execute. In the nRF9E5 architecture, MOVX A,
@DPTR takes two instruction cycles (eight clock cycles) and MOV direct, direct takes
three instruction cycles (twelve clock cycles). Both instructions execute faster on the
nRF9E5 than they do on the standard 8051, but require different numbers of clock
cycles.
For timing of real-time events, use the numbers of instruction cycles from Table 55 to
Table 60 to calculate the timing of software loops. The bytes column of these table
indicates the number of memory accesses (bytes) needed to execute the instruction. In
most cases, the number of bytes is equal to the number of instruction cycles required to
complete the instruction. However, as indicated in Table 55, there are some instructions
(for example, DIV and MUL) that require a greater number of instruction cycles than
memory accesses.By default, the nRF9E5 timer/counters run at twelve clock cycles per
increment so that timer-based events have the same timing as with the standard 8051.
The timers can be configured to run at four clock cycles per increment to take advantage
of the higher speed of the nRF9E5.
18.5 Dual Data Pointers
The nRF9E5 employs dual data pointers to accelerate data memory block moves. The
standard 8051 data pointer (DPTR) is a 16-bit value used to address external data RAM
or peripherals. The nRF9E5 maintains the standard data pointer as DPTR0 at SFR
locations 0x82 and 0x83. It is not necessary to modify code to use DPTR0. The nRF9E5
adds a second data pointer (DPTR1) at SFR locations 0x84 and 0x85. The SEL bit in the
DPTR Select register, DPS (SFR 0x86), selects the active pointer. When SEL = 0,
instructions that use the DPTR will use DPL0 and DPH0. When SEL = 1, instructions
that use the DPTR will use DPL1 and DPH1. SEL is the bit 0 of SFR location 0x86. No
other bits of SFR location 0x86 are used. All DPTR-related instructions use the
currently selected data pointer. To switch the active pointer, toggle the SEL bit. The
fastest way to do so is to use the increment instruction (INC DPS). This requires only
one instruction to switch from a source address to a destination address, saving
application code from having to save source and destination addresses when doing a
block move. Using dual data pointers provides significantly increased efficiency when
moving large blocks of data.
The SFR locations related to the dual data pointers are:
- 0x82 DPL0 DPTR0 low byte
- 0x83 DPH0 DPTR0 high byte
- 0x84 DPL1 DPTR1 low byte
- 0x85 DPH1 DPTR1 high byte
- 0x86 DPS
DPTR Select (LSB)
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18.6 Special Function Registers
The Special Function Registers (SFRs) control several of the features of the nRF9E5.
Most of the nRF9E5 SFRs are identical to the standard 8051 SFRs. However, there are
additional SFRs that control features that are not available in the standard 8051. Table
61 lists the nRF9E5 SFRs and indicates which SFRs are not included in the standard
8051 SFR space. When writing software for the nRF9E5, use equate statements to
define the SFRs that are specific to the nRF9E5 and custom peripherals. In Table 61,
SFR bit positions that contain a 0 or a 1 cannot be written to and, when read, always
return the value shown (0 or 1). SFR bit positions that contain “–” are available but not
used. Table 62 shows the value of each SFR, after power-on reset or a watchdog reset,
together with a pointer to a detailled description of each register. Please note that any
unused address in the SFR address space is reserved and should not be written to.
Notes to Table 61 on next page :
(1)
(2)
(3)
Not part of standard 8051 architecture.
Registers unique to nRF9E5
P0, P1 and P3 differ from standard 8051
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Addr
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0xA0
P0(3)
SP
DPL0
DPH0
DPL1(1)
DPH1(1)
DPS(1)
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON(1)
SPC_FNC(1)
P1(3)
EXIF(1)
MPAGE(1)
P0_DRV(2)
P0_DIR(2)
P0_ALT(2)
P1_DIR(2)
P1_ALT(2)
SCON
Port 0
Stack pointer
Data pointer 0, low byte
Data pointer 0, high byte
Data pointer 1, low byte
Data pointer 1, high byte
0
0
•
TR1
C/T
0
1
TF0
M1
0
1
TR0
M0
0
GF1
IE1
GATE
0
0
SEL
IDLE
IT0
SMOD
TF1
GATE
GF0
IT1
C/T
STOP
IE0
M1
M0
Timer/counter 0 value, low byte
Timer/counter 1 value, low byte
Timer/counter 0 value, high byte
Timer/counter 1 value, high byte
•
0
•
IE5
•
•
0
•
IE4
•
T2M
0
•
IE3
•
T1M
0
•
IE2
•
T0M
0
MD2
0
MD1
0
Port 1 bit 3:0
MD0
WRS
1
•
0
•
0
•
0
•
Drive Strength of port 0
Direction of Port 0
Alternate functions of Port 0
•
•
•
•
•
•
•
•
Direction of Port 1
Alt.funct.of Port 1
RB8
SM0
SM1
SM2
REN
TB8
TI
RI
SBUF
P2(3)
Serial port data buffer
EOC/
TX_EN
AM
CD
DR/
TRX_CE
ET2
SBMISO
SBMOSI
ET0
SBSCK
EX0
RACSN
ET1
0xA8
0xA9
IE
EA
0
ES
EX1
PWMCON(2)
PWM_LENGTH
PWM_PRESCALE
PWM_DUTY_CYCLE
High byte of Watchdog/RTC register
Low byte of Watchdog/RTC register
0xAA PWMDUTY(2)
0xAB REGX_MSB(2)
0xAC REGX_LSB(2)
0xAD REGX_CTRL(2)
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB8
0xBF
•
•
•
•
•
•
Control of REGX_MSB and REGX_LSB
RSTREAS(2)
SPI_DATA(2)
SPI_CTRL(2)
SPICLK(2)
TICK_DV(2)
CK_CTRL(2)
IP
•
•
•
RFLR
SPI_DATA input/output bits
•
•
•
•
•
•
•
•
•
SPI_CTRL
SPICLK
TICK_DV
•
•
1
-
•
0
-
•
•
PS
CK_CTRL
PT0
UP_CLK_FREQ
PT2
PT1
PX1
UP_CLK
_EN
PX0
CKLFCON (2)
XOF
0xC8
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
0xCA RCAP2L
0xCB RCAP2H
0xCC TL2
Timer/counter 2 capture or reload, low byte
Timer/counter 2 capture or reload, high byte
Timer/counter 2 value, low byte
0xCD TH2
Timer/counter 2 value, high byte
0xD0
0xD8
0xE0
0xE8
0xF0
0xF8
0xFE
0xFF
PSW
EICON(1)
ACC
EIE(1)
B
EIP(1)
HWREV (2)
-----
CY
-
AC
1
F0
0
RS1
0
RS0
WDTI
OV
0
F1
0
P
0
Accumulator register
EWDI
B-register
PWDI
1
1
1
1
1
1
EX5
EX4
EX3
PX3
EX2
PX2
PX5
PX4
Device hardware revision number
Reserved, do not use
Table 61 Special Function Registers summary.
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Register
Addr
Reset value
Description
ACC
B
CK_CTRL
CKCON
CKLFCON
DPH0
DPH1
DPL0
DPL1
DPS
EICON
EIE
EIP
EXIF
HWREV
IE
0xE0
0xF0
0xB6
0x8E
0xBF
0x83
0x85
0x82
0x84
0x86
0xD8
0xE8
0xF8
0x91
0xFE
0xA8
0xB8
0x92
0x80
0x95
0x94
0x93
0x90
0x97
0x96
0xA0
0x87
0xD0
0xA9
0xAA
0xCB
0xCA
0xAD
0xAC
0xAB
0xB1
0x99
0x98
0x81
0x8F
0xB3
0xB2
0xB4
0xC8
0x88
0x8C
0x8D
0xCD
0xB5
0x8A
0x8B
0xCC
0x89
0x00
0x00
0x00
0x01
0x27
0x00
0x00
0x00
0x00
0x00
0x40
0xE0
0xE0
0x08
0x00,read only
0x00
0x80
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xF4
0x08
0x30
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x00
0x07
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x1D
0x00
0x00
0x00
0x00
Accumulator register
B-register
Table 51, page 58
Table 67, page 78
Table 43 on page 51
ch.18.5, page 68
ch.18.5, page 68
ch.18.5, page 68
ch.18.5, page 68
ch.18.5, page 68
Table 40, page 47
Table 41, page 47
Table 42, page 48
Table 39, page 47
hardware revision no
Table 37, page 46
Table 38, page 46
do not use
Table 10, page 15
Table 10, page 15
Table 10, page 15
Table 10, page 15
Table 12, page 16
Table 12, page 16
Table 12, page 16
Table 15, page 19
Table 49, page 57
Table 63, page 72
Table 35, page 44
Table 35, page 44
ch.18.8.3.3, page 80
ch.18.8.3.3, page 80
Table 45, page 54
Table 45, page 54
Table 45, page 54
Table 48, page 56
ch.18.9, page 81
Table 71, page 82
Stack pointer
IP
MPAGE
P0
P0_ALT
P0_DIR
P0_DRV
P1
P1_ALT
P1_DIR
P2
PCON
PSW
PWMCON
PWMDUTY
RCAP2H
RCAP2L
REGX_CTRL
REGX_LSB
REGX_MSB
RSTREAS
SBUF
SCON
SP
SPC_FNC
SPI_CTRL
SPI_DATA
SPICLK
T2CON
TCON
TH0
TH1
TH2
TICK_DV
TL0
TL1
do not use
Table 33, page 43
Table 33, page 43
Table 33, page 43
Table 68, page 79
Table 66, page 75
ch.18.8, page 74
ch.18.8, page 74
ch.18.8, page 74
Table 43, page 51
ch.18.8, page 74
ch.18.8, page 74
ch.18.8, page 74
Table 65, page 74
TL2
TMOD
Table 62 Special Function Register reset values and description, alphabetically.
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Table 63 lists the functions of the bits in the PSW register.
Bit
Function
PSW.7
CY • Carry flag. Set to 1 when last arithmetic operation resulted in a carry (during
addition) or borrow (during subtraction); otherwise cleared to 0 by all arithmetic
operations.
PSW.6
AC • Auxiliary carry flag. Set to 1 when last arithmetic operation resulted in a carry into
(during addition) or borrow from (during subtraction) the high-order nibble; otherwise
cleared to 0 by all arithmetic operations.
PSW.5
PSW.4
F0 • User flag 0. Bit-addressable, general purpose flag for software control.
RS1 • Register bank select bit 1. Used with RS0 to select a register blank in internal
RAM.
PSW.3
RS0 • Register bank select bit 0, decoded as:
RS1 RS0 Bank selected
0
0
1
1
0
1
0
1
Register bank 0, addresses 0x00•0x07
Register bank 1, addresses 0x08•0x0F
Register bank 2, addresses 0x10•0x17
Register bank 3, addresses 0x18•0x1F
PSW.2
OV • Overflow flag. Set to 1 when last arithmetic operation resulted in a carry (addition),
borrow (subtraction), or overflow (multiply or divide); otherwise cleared to 0 by all
arithmetic operations.
PSW.1
PSW.0
F1 • User flag 1. Bit-addressable, general purpose flag for software control.
P • Parity flag. Set to 1 when modulo-2 sum of 8 bits in accumulator is 1 (odd parity);
cleared to 0 on even parity.
Table 63 PSW Register – SFR 0xD0.
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18.7 SFR Registers Unique to nRF9E5
The table below lists the SFR registers that are unique to nRF9E5 (not part of standard
8051 register map) The registers P0, P1 and P2 (radio) use the addresses for the ports
P0, P1 and P2 in a standard 8051. Whereas the functionality of these ports is similar to
that of the corresponding ports in standard 8051, it is not identical.
Addr
SFR
R/W
#bit
Init
hex
FF
FF
Name
Function
80*
R/W
R/W
8
8(4)
P0
P1**
Port 0, pins P07 to P00
Port 1, pins SPI_CSN, SPI_MISO, SPI_MOSI
and SPI_SCK
90*
94
95
96
97
A0*
R/W
R/W
R/W
R/W
R/W
8
8
8(4)
8(4)
8
FF
00
F4
00
08
P0_DIR
P0_ALT
P1_DIR
P1_ALT
P2
Direction of each GPIO bit of port 0
Select alternate functions for each pin of port 0
Direction for each GPIO bit of port 1
Select alternate functions for each pin of port 1
General purpose IO for interface to nRF905 radio,
for details see chapter 8.1
A9
AA
AB
R/W
R/W
R/W
8
8
8
0
0
0
PWMCON
PWMDUTY
REGX_MSB
PWM control register
PWM duty cycle
High part of 16 bit register for interface to
Watchdog and RTC
AC
R/W
8
0
REGX_LSB
Low part of 16 bit register for interface to
Watchdog and RTC
AD
B1
B2
B3
R/W
R/W
R/W
R/W
5
2
8
2
0
02
0
REGX_CTRL
RSTREAS
SPI_DATA
SPI_CTRL
Control of interface to Watchdog and RTC.
Reset status and control
SPI data input/output
00 -> SPI not used 01 -> connect to P1
10 or 11 -> connect to RADIO
Divider from CPU clock to SPI clock
TICK Divider.
0
B4
B5
B6
B7
R/W
R/W
W
2
8
3
4
0
1D
0
SPICLK
TICK_DV
CK_CTRL
TEST_MODE
Clock control
Test mode register.
R
0
This register must always be 0 in normal mode.
BF
FE
R/W
R
6
8
27
00
CKLFCON
HWREV
Control generation of 4 kHz CKLF
Silicon stepping
Table 64 SFR registers unique to nRF9E5.
*
This bit addressable register differs in usage from “standard 8051
**
Only 4 lower bits are meaningful in P1 and corresponding P1_DIR and P1_ALT
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18.8 Timers/Counters
The nRF9E5 includes three timer/counters (Timer 0, Timer 1 and Timer 2). Each
timer/counter can operate as either a timer with a clock rate based on the CPU clock , or
as an event counter clocked by the t0 pin (Timer 0), t1 pin (Timer 1), or the t2 pin
(Timer 2). These pins are alternate function bits of Port 0 and 1 as this : t0 is P0.5, t1 is
P0.6 and t2 is P1.0, for details please see ch. 6.3 on page 15.
Each timer/counter consists of a 16-bit register that is accessible to software as three
SFRs: (Table 61)
Timer 0 • TL0 and TH0
Timer 1 • TL1 and TH1
Timer 2 • TL2 and TH2
18.8.1 Timers 0 and 1
Timers 0 and 1 each operate in four modes, as controlled through the TMOD SFR
(Table 65) and the TCON SFR (Table 66). The four modes are:
-
-
-
-
13-bit timer/counter (mode 0)
16-bit timer/counter (mode 1)
8-bit counter with auto-reload (mode 2)
Two 8-bit counters (mode 3, Timer 0 only)
Bit
Function
TMOD.7
GATE • Timer 1 gate control. When GATE = 1, Timer 1 will clock only when external
interrupt INT1_N = 1 and TR1 (TCON.6) = 1. When GATE = 0, Timer 1 will clock only
when TR1 = 1, regardless of the state of INT1_N.
TMOD.6
C/T • Counter/Timer select. When C/T = 0, Timer 1 is clocked by CPU_clk/4 or
CPU_clk/12, depending on the state of T1M (CKCON.4). When C/T = 1, Timer 1 is clocked
by the t1 pin.
TMOD.5
TMOD.4
M1 • Timer 1 mode select bit 1.
M0 • Timer 1 mode select bit 0, decoded as:
M1 M0 Mode
00 Mode 0 : 13-bit counter
01 Mode 1 : 16-bit counter
10 Mode 2 : 8-bit counter with auto-reload
11 Mode 3 : Two 8-bit counters
TMOD.3
TMOD.2
GATE • Timer 0 gate control. When GATE = 1, Timer 0 will clock only when external
interrupt INT0_N = 1 and TR0 (TCON.4) = 1. When GATE = 0, Timer 0 will clock only
when TR0 = 1, regardless of the state of INT0_N.
C/T • Counter/Timer select. When C/T = 0, Timer 0 is clocked by CPU_clk/4 or
CPU_clk/12, depending on the state of T0M (CKCON.3). When C/T = 1, Timer 0 is clocked
by the t0 pin.
TMOD.1
TMOD.0
M1 • Timer 0 mode select bit 1.
M0 • Timer 0 mode select bit 0, decoded as:
M1 M0 Mode
00 Mode 0 : 13-bit counter
01 Mode 1 : 16-bit counter
10 Mode 2 : 8-bit counter with auto-reload
11 Mode 3 : Two 8-bit counters
Table 65 TMOD Register – SFR 0x89.
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Bit
Function
TCON.7
TF1 • Timer 1 overflow flag. Set to 1 when the Timer 1 count overflows and cleared when
the CPU vectors to the interrupt service routine.
TCON.6
TCON.5
TR1 • Timer 1 run control. Set to 1 to enable counting on Timer 1.
TF0 • Timer 0 overflow flag. Set to 1 when the Timer 0 count overflows and cleared when
the CPU vectors to the interrupt service routine.
TCON.4
TCON.3
TR0 • Timer 0 run control. Set to 1 to enable counting on Timer 0.
IE1 • Interrupt 1 edge detect. If external interrupt 1 is configured to be edge-sensitive (IT1
= 1), IE1 is set by hardware when a negative edge is detected on the INT1_N external
interrupt pin and is automatically cleared when the CPU vectors to the corresponding
interrupt service routine. In edge-sensitive mode, IE1 can also be cleared by software.
If external interrupt 1 is configured to be level-sensitive (IT1 = 0), IE1 is set when the
INT1_N pin is low and cleared when the INT1_N pin is high. In level-sensitive mode,
software cannot write to IE1.
TCON.2
TCON.1
IT1 • Interrupt 1 type select. When IT1 = 1, the nRF9E5 detects external interrupt pin
INT1_N on the falling edge (edge-sensitive). When IT1 = 0, the nRF9E5 detects INT1_N
as a low level (level-sensitive).
IE0 • Interrupt 0 edge detect. If external interrupt 0 is configured to be edge-sensitive (IT0
= 1), IE0 is set by hardware when a negative edge is detected on the INT0_N external
interrupt pin and is automatically cleared when the CPU vectors to the corresponding
interrupt service routine. In edge-sensitive mode, IE0 can also be cleared by software.
If external interrupt 0 is configured to be level-sensitive (IT0 = 0), IE0 is set when the
INT0_N pin is low and cleared when the INT0_N pin is high. In level-sensitive mode,
software cannot write to IE0.
TCON.0
IT0 • Interrupt 0 type select. When IT1 = 1, the nRF9E5 detects external interrupt INT0_N
on the falling edge (edge-sensitive). When IT1 = 0, the nRF9E5 detects INT0_N as a low
level (level-sensitive).
Table 66 TCON Register – SFR 0x88.
18.8.1.1 Mode 0
Mode 0 operation, illustrated in Figure 18, is the same for Timer 0 and Timer 1. In mode
0, the timer is configured as a 13-bit counter that uses bits 0–4 of TL0 (or TL1) and all
eight bits of TH0 (or TH1). The timer enable bit (TR0/TR1) in the TCON SFR starts the
timer. The C/T bit selects the timer/counter clock source, CPU_clk or T0/T1. The timer
counts transitions from the selected source as long as the GATE bit is 0, or the GATE bit
is 1 and the corresponding interrupt pin (INT0_N or INT1_N) is deasserted. INT0_N
and INT1_N are alternate function bits of Port0, please see Table 8 Port functions. When
the 13-bit count increments from 0x1FFF (all ones), the counter rolls over to all zeros,
the TF0 (or TF1) bit is set in the TCON SFR, and the t0_out (or t1_out) pin goes high
for one clock cycle. The upper three bits of TL0 (or TL1) are indeterminate in mode 0
and must be masked when the software evaluates the register.
18.8.1.2 Mode 1
Mode 1 operation is the same for Timer 0 and Timer 1. In mode 1, the timer is
configured as a 16-bit counter. As illustrated in, all eight bits of the LSB register (TL0 or
TL1) are used. The counter rolls over to all zeros when the count increments from
0xFFFF. Otherwise, mode 1 operation is the same as mode 0.
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T0M (T1M)
Divide by 12
0
CPU_CLK
C/T
0
TL0 (TL1)
1
clk
0
1
2
3
4
5
6
7
Divide by 4
1
P05/T0 (P06/T1)
Mode 0
Mode 1
TH0 (TH1)
TR0 (TR1)
GATE
0
1
2
3
4
5
6
7
P03/INT0_N (P04/INT1_N)
P0_ALT.3 (P0_ALT.4)
INT
TF0 (TF1)
To serial port
(timer 1 only)
Figure 18 Timer 0/1 – Modes 0 and 1.
18.8.1.3 Mode 2
Mode 2 operation is the same for Timer 0 and Timer 1. In mode 2, the timer is
configured as an 8-bit counter, with automatic reload of the start value. The LSB register
(TL0 or TL1) is the counter, and the MSB register (TH0 or TH1) stores the reload value.
As illustrated in Figure 19 Timer 0/1 – Mode 2, mode 2 counter control is the same as
for mode 0 and mode 1. However, in mode 2, when TLn increments from 0xFF, the
value stored in THn is reloaded into TLn.
T0M (T1M)
Divide by 12
0
CPU_CLK
C/T
0
TL0 (TL1)
1
clk
0
0
1
2
3
4
4
5
5
6
6
7
7
Divide by 4
1
P05/T0 (P06/T1)
1
2
3
TR0 (TR1)
GATE
TH0 (TH1)
P03/INT0_N (P04/INT1_N)
P0_ALT.3 (P0_ALT.4)
INT
TF0 (TF1)
To serial port
(timer 1 only)
Figure 19 Timer 0/1 – Mode 2.
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18.8.1.4 Mode 3
In mode 3, Timer 0 operates as two 8-bit counters, and Timer 1 stops counting and holds
its value. As shown in Figure 20 Timer 0 – Mode 3, TL0 is configured as an 8-bit
counter controlled by the normal Timer 0 control bits. TL0 can count either CPU clock
cycles (divided by 4 or by 12) or high-to-low transitions on t0, as determined by the C/T
bit. The GATE function can be used to give counter enable control to the INT0_N
signal.
T0M
0
Divide by 12
CPU_CLK
C/T
0
TL0
1
1
clk
0
2
3
4
5
6
7
Divide by 4
1
P05/T0
INT
INT
TF0
TF1
TR0
GATE
P03/INT0_N
clk
0
1
2
3
4
5
6
7
P0_ALT.3
TR1
TH0
Figure 20 Timer 0 – Mode 3.
TH0 functions as an independent 8-bit counter. However, TH0 can count only CPU
clock cycles (divided by 4 or by 12). The Timer 1 control and flag bits (TR1 and TF1)
are used as the control and flag bits for TH0.
When Timer 0 is in mode 3, Timer 1 has limited usage because Timer 0 uses the Timer
1 control bit (TR1) and interrupt flag (TF1). Timer 1 can still be used for baud rate
generation and the Timer 1 count values are still available in the TL1 and TH1
registers.Control of Timer 1 when Timer 0 is in mode 3 is through the Timer 1 mode
bits. To turn Timer 1 on, set Timer 1 to mode 0, 1, or 2. To turn Timer 1 off, set it to
mode 3. The Timer 1 C/T bit and T1M bit are still available to Timer 1. Therefore,
Timer 1 can count CPU_clk/4, CPU_clk/12, or high-to-low transitions on the t1 pin. The
Timer 1 GATE function is also available when Timer 0 is in mode 3.
18.8.2 Timer Rate Control
The default timer clock scheme for the nRF9E5 timers is twelve CPU clock cycles per
increment, the same as in the standard 8051. However, in the nRF9E5, the instruction
cycle is four clock cycles.
Using the default rate (twelve clocks per timer increment) allows existing application
code with real-time dependencies, such as baud rate, to operate properly. However,
applications that require fast timing can set the timers to increment every four clock
cycles by setting bits in the Clock Control register (CKCON) at SFR location 0x8E,
described in Table 67 CKCON Register – SFR 0x.
The CKCON bits that control the timer clock rates are:
CKCON bit Counter/Timer
5
4
3
Timer 2
Timer 1
Timer 0
When a CKCON register bit is set to 1, the associated counter increments at four-clock
intervals. When a CKCON bit is cleared, the associated counter increments at twelve-
clock intervals. The timer controls are independent of each other. The default setting for
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all three timers is 0; that is, twelve-clock intervals. These bits have no effect in counter
mode.
Bit
Function
CKCON.7,6
CKCON.5
Reserved
T2M – Timer 2 clock select. When T2M = 0, Timer 2 uses CPU_clk/12 (for
compatibility with 80C32); when T2M = 1, Timer 2 uses CPU_clk/4. This bit has
no effect when Timer 2 is configured for baud rate generation.
CKCON.4
CKCON.3
T1M – Timer 1 clock select. When T1M = 0, Timer 1 uses CPU_clk/12 (for
compatibility with 80C32); when T1M = 1, Timer 1 uses CPU_clk/4.
T0M – Timer 0 clock select. When T0M = 0, Timer 0 uses CPU_clk/12 (for
compatibility with 80C32); when T0M = 1, Timer 0 uses CPU_clk/4.
CKCON.2–
0
MD2, MD1, MD0 – Control the number of cycles to be used for external MOVX
instructions; number of cycles is 2 + { MD2, MD1, MD0}
Table 67 CKCON Register – SFR 0x8E.
default initial data value is 0x01, i.e. MOVX takes 3 cycles.
18.8.3 Timer 2
Timer 2 runs only in 16-bit mode and offers several capabilities not available with
Timers 0 and 1. The modes available with Timer 2 are:
- 16-bit timer/counter
- 16-bit timer with capture
- 16-bit auto-reload timer/counter
- Baud-rate generator
The SFRs associated with Timer 2 are:
- T2CON – SFR 0xC8; refer to Table 68 T2CON Register – SFR 0x
- RCAP2L – SFR 0xCA – Used to capture the TL2 value when Timer 2 is configured
for capture mode, or as the LSB of the 16-bit reload value when Timer 2 is configured
for auto-reload mode.
- RCAP2H – SFR 0xCB – Used to capture the TH2 value when Timer 2 is configured
for capture mode, or as the MSB of the 16-bit reload value when Timer 2 is configured
for auto-reload mode.
TL2 – SFR 0xCC – Lower eight bits of the 16-bit count.
TH2 – SFR 0xCD – Upper eight bits of the 16-bit count.
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Bit
T2CON.7
Function
TF2 • Timer 2 overflow flag. Hardware will set TF2 when Timer 2 overflows from
0xFFFF. TF2 must be cleared to 0 by the software. TF2 will only be set to a 1 if RCLK and
TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled.
EXF2 • Timer 2 external flag. Hardware will set EXF2 when a reload or capture is caused
by a high-to-low transition on the t2ex pin, and EXEN2 is set. EXF2 must be cleared to 0
by the software. Writing a 1 to EXF2 forces a Timer 2 interrupt if enabled.
T2CON.6
T2CON.5 RCLK • Receive clock flag. Determines whether Timer 1 or Timer 2 is used for Serial port
timing of received data in serial mode 1 or 3. RCLK = 1 selects Timer 2 overflow as the
receive clock. RCLK = 0 selects Timer 1 overflow as the receive clock.
T2CON.4 TCLK • Transmit clock flag. Determines whether Timer 1 or Timer 2 is used for Serial port
timing of transmit data in serial mode 1 or 3. TCLK =1 selects Timer 2 overflow as the
transmit clock. TCLK = 0 selects Timer 1 overflow as the transmit clock.
T2CON.3 EXEN2 • Timer 2 external enable. EXEN2 = 1 enables capture or reload to occur as a result
of a high-to-low transition on t2ex, if Timer 2 is not generating baud rates for the serial
port. EXEN2 = 0 causes Timer 2 to ignore all external events at t2ex.
T2CON.2 TR2 • Timer 2 run control flag. TR2 = 1 starts Timer 2. TR2 = 0 stops Timer 2.
T2CON.1 C/T2 • Counter/timer select. C/T2 = 0 selects a timer function for Timer 2. C/T2 = 1 selects
a counter of falling transitions on the t2 pin. When used as a timer, Timer 2 runs at four
clocks per increment or twelve clocks per increment as programmed by CKCON.5, in all
modes except baud-rate generator mode. When used in baud-rate generator mode, Timer 2
runs at two clocks per increment, independent of the state of CKCON.5.
T2CON.0 CP/RL2 • Capture/reload flag. When CP/RL2 = 1, Timer 2 captures occur on high-to-low
transitions of t2ex, if EXEN2 = 1. When CP/RL2 = 0, auto-reloads occur when Timer 2
overflows or when high-to-low transitions occur on t2ex, if EXEN2 = 1. If either RCLK or
TCLK is set to 1, CP/RL2 will not function, and Timer 2 will operate in auto-reload mode
following each overflow.
Table 68 T2CON Register – SFR 0xC8.
18.8.3.1 Timer 2 Mode Control
Table 69 summarizes how the SFR bits determine the Timer 2 mode.
RCLK
TCLK
CP/RL2
TR2
Mode
0
0
1
X
X
0
0
X
1
X
1
0
X
X
X
1
1
1
1
0
16-bit timer/counter with capture
16-bit timer/counter with auto-reload
Baud-rate generator
Baud-rate generator
Off
Table 69 Timer 2 Mode Control Summary.
18.8.3.2 16-Bit Timer/Counter Mode
Figure 21 Timer 2 – Timer/Counter with Capture illustrates how Timer 2 operates in
timer/counter mode with the optional capture feature. The C/T2 bit determines whether
the 16-bit counter counts clock cycles (divided by 4 or 12), or high-to-low transitions on
the t2 pin. The TR2 bit enables the counter. When the count increments from 0xFFFF,
the TF2 flag is set, and t2_out goes high for one clock cycle.
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T2M
Divide by 12
Divide by 4
0
CPU_CLK
C/T2
0
1
0
7
8
15
clk
TL2
TH2
1
SCK/T2
capture
TR2
0
7
8
15
RCAP2L RCAP2H
EXEN2
TF2
LP_OSC
Divide by 2
INT
EXF2
Figure 21 Timer 2 – Timer/Counter with Capture.
18.8.3.3 16-Bit Timer/Counter Mode with Capture
The Timer 2 capture mode, illustrated in Figure 21 Timer 2 – Timer/Counter with
Capture, is the same as the 16-bit timer/counter mode, with the addition of the capture
registers and control signals. The CP/RL2 bit in the T2CON SFR enables the capture
feature. When CP/RL2 = 1, a high-to-low transition on t2ex when EXEN2 = 1 causes
the Timer 2 value to be loaded into the capture registers (RCAP2L and RCAP2H).
18.8.3.4 16-Bit Timer/Counter Mode with Auto-Reload
When CP/RL2 = 0, Timer 2 is configured for the auto-reload mode illustrated in Figure
22 Timer 2 – Timer/Counter with Auto-Reload. Control of counter input is the same as
for the other 16-bit counter modes. When the count increments from 0xFFFF, Timer 2
sets the TF2 flag and the starting value is reloaded into TL2 and TH2. The software
must preload the starting value into the RCAP2L and RCAP2H registers.
When Timer 2 is in auto-reload mode, a reload can be forced by a high-to-low transition
on the t2ex pin, if enabled by EXEN2 = 1.
T2M
0
Divide by 12
CPU_CLK
C/T2
0
0
7 8
15
1
clk
Divide by 4
TL2
TH2
1
SCK/T2
reload
TR2
0
7 8
15
RCAP2L RCAP2H
EXEN2
TF2
LP_OSC
Divide by 2
INT
EXF2
Figure 22 Timer 2 – Timer/Counter with Auto-Reload.
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18.8.3.5 Baud Rate Generator Mode
Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial
port in serial mode 1 or 3. In baud-rate generator mode, Timer 2 functions in auto-reload
mode. However, instead of setting the TF2 flag, the counter overflow generates a shift
clock for the serial port function. As in normal auto-reload mode, the overflow also
causes the preloaded start value in the RCAP2L and RCAP2H registers to be reloaded
into the TL2 and TH2 registers.
When either TCLK = 1 or RCLK = 1, Timer 2 is forced into auto-reload operation,
regardless of the state of the CP/RL2 bit.
When operating as a baud rate generator, Timer 2 does not set the TF2 bit. In this mode,
a Timer 2 interrupt can be generated only by a high-to-low transition on the t2ex pin
setting the EXF2 bit, and only if enabled by EXEN2 = 1.The counter time base in baud-
rate generator mode is CPU_clk/2. To use an external clock source, set C/T2 to 1 and
apply the desired clock source to the t2 pin.
Timer 1 overflow
SMOD0
Divide by 2
0
1
CPU_CLK
C/T2
0
Divide by 2
RCLK
0
0
7
8
15
clk
RX
clock
TL2
TH2
1
Divide by 16
1
SCK/T2
TCLK
0
TR2
0
7
8
15
Divide by 16
RCAP2L RCAP2H
1
TX
clock
EXEN2
INT
LP_OSC
EXF2
Divide by 2
Figure 23 Timer 2 – Baud Rate Generator Mode.
18.9 Serial Interface
The nRF9E5 is configured with one serial port, which is identical in operation to the
standard 8051 serial port. The two serial port pins rxd and txd are available as alternate
functions of P0.1 and P0.2, for details please see ch. 6.3 on page 15.
The serial port can operate in synchronous or asynchronous mode. In synchronous
mode, the nRF9E5 generates the serial clock and the serial port operates in half-duplex
mode. In asynchronous mode, the serial port operates in full-duplex mode. In all modes,
the nRF9E5 buffers receive data in a holding register, enabling the UART to receive an
incoming word before the software has read the previous value.
The serial port can operate in one of four modes, as outlined in Table 70.
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Mode Sync/As
ync
Baud Clock
Data Bits
Start/ Stop
9th Bit Function
None
0
1
2
3
Sync
CPU_clk/4
CPU_clk/12
or
8
8
9
9
None
Async
Async
Async
Timer 1 or Timer
2
CPU_clk/32 or
CPU_clk/64
Timer 1 or Timer
2
1 start,
1 stop
1 start,
1 stop
1 start,
1 stop
None
0, 1, parity
0, 1, parity
Table 70 Serial Port Modes.
The SFRs associated with the serial port are:
- SCON – SFR 0x98 – Serial port control (Table 71)
- SBUF – SFR 0x99 – Serial port buffer
Bit
Function
SCON.7
SCON.6
SM0 • Serial port mode bit 0.
SM1 • Serial port mode bit 1, decoded as:
SM0 SM1 Mode
0
0
1
1
0
1
0
1
0
1
2
3
SCON.5
SM2 • Multiprocessor communication enable. In modes 2 and 3, SM2 enables the
multiprocessor communication feature. If SM2 = 1 in mode 2 or 3, RI will not be
activated if the received 9th bit is 0. If SM2 = 1 in mode 1, RI will be activated only
if a valid stop is received. In mode 0, SM2 establishes the baud rate: when SM2 =
0, the baud rate is CPU_clk/12; when
SM2 = 1, the baud rate is CPU_clk/4.
SCON.4
SCON.3
SCON.2
REN • Receive enable. When REN = 1, reception is enabled.
TB8 • Defines the state of the 9th data bit transmitted in modes 2 and 3.
th
RB8 • In modes 2 and 3, RB8 indicates the state of the 9 bit received. In mode 1,
RB8 indicates the state of the received stop bit. In mode 0, RB8 is
not used.
SCON.1
TI • Transmit interrupt flag. Indicates that the transmit data word has been shifted
out. In mode 0, TI is set at the end of the 8 data bit. In all other modes, TI is set
th
when the stop bit is placed on the txd pin. TI must be cleared by the software.
Table 71 SCON Register – SFR 0x98.
18.9.1 Mode 0
Serial mode 0 provides synchronous, half-duplex serial communication. For Serial Port
0, both serial data input and output occur on rxd pin, and txd provides the shift clock
for both transmit and receive. The rxd and txd pins are alternate function bits of Port 0,
please also see Table 9 Port 0 (P0) functions for port and pin configuration. The lack of
open drain ports on nRF9E5 makes it a programmer responsibility to control the
direction of the rxd pin.
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The serial mode 0 baud rate is either CPU_clk/12 or CPU_clk/4, depending on the state
of the SM2. When SM2 = 0, the baud rate is CPU_clk/12; when SM2 = 1, the baud rate
is CPU_clk/4.
Mode 0 operation is identical to the standard 8051. Data transmission begins when an
instruction writes to the SBUF SFR. The UART shifts the data out, LSB first, at the
selected baud rate, until the 8-bit value has been shifted out.
Mode 0 data reception begins when the REN bit is set and the RI bit is cleared in the
corresponding SCON SFR. The shift clock is activated and the UART shifts data in on
each rising edge of the shift clock until eight bits have been received. One machine cycle
after the 8th bit is shifted in, the RI bit is set and reception stops until the software clears
the RI bit.
Figure 24 Serial Port Mode 0 receive timing for low-speed (CPU_clk/12) operation.
Figure 25 Serial Port Mode 0 receive timing for high-speed (CPU_clk/4) operation.
:
Figure 26 Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4) operation.
:
Figure 27 Serial Port Mode 0 transmit timing for high-speed (CPU_clk/4) operation.
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18.9.2 Mode 1
Mode 1 provides standard asynchronous, full-duplex communication, using a total of ten
bits: one start bit, eight data bits, and one stop bit. For receive operations, the stop bit is
stored in RB8. Data bits are received and transmitted LSB first.
18.9.2.1 Mode 1 Baud Rate
The mode 1 baud rate is a function of timer overflow. Serial port can use either Timer 1
or Timer 2 to generate baud rates. Each time the timer increments from its maximum
count (0xFF for Timer 1 or 0xFFFF for Timer 2), a clock is sent to the baud-rate circuit.
The clock is then divided by 16 to generate the baud rate. When using Timer 1, the
SMOD bit selects whether or not to divide the Timer 1 rollover rate by 2. Therefore,
when using Timer 1, the baud rate is determinedby the equation:
2SMOD
Baud Rate =
SMOD is SFR bit PCON.7
x Timer 1 Overflow
32
When using Timer 2, the baud rate is determined by the equation:
Timer 2 Overflow
Baud Rate =
16
To use Timer 1 as the baud-rate generator, it is best to use Timer 1 mode 2 (8-bit counter
with auto-reload), although any counter mode can be used. The Timer 1 reload value is
stored in the TH1 register, which makes the complete formula for Timer 1:
2SMOD
32
clk
Baud Rate =
x
4 x (256 - TH1)
The 4 in the denominator in the above equation can be obtained by setting the T1M bit
in the CKCON SFR. To derive the required TH1 value from a known baud rate (when
TM1 = 0), use the equation:
2SMOD *clk
TH1 = 256 -
128*Baud Rate
You can also achieve very low serial port baud rates from Timer 1 by enabling the
Timer 1 interrupt, configuring Timer 1 to mode 1, and using the Timer 1 interrupt to
initiate a 16-bit software reload. Table Table 72 lists sample reload values for a variety
of common serial port baud rates.
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Desired
Baud Rate
SMOD
C/T
Timer 1
Mode
TH1
Value TH1
Value
8 MHz
for 16 MHz for
CPU clk
0xF3
CPU clk
19.2 Kb/s
9.6 Kb/s
4.8 Kb/s
0.4 Kb/s
1.2 Kb/s
1
1
1
1
1
0
0
0
0
0
2
2
2
2
2
-
0xE6
0XcC
0x98
0x30
0xF3
0xE6
0xCC
0x98
Table 72 Timer 1 Reload Values for Serial Port Mode 1 Baud Rates.
To use Timer 2 as the baud-rate generator, configure Timer 2 in auto-reload mode and
set the TCLK and/or RCLK bits in the T2CON SFR. TCLK selects Timer 2 as the baud-
rate generator for the transmitter; RCLK selects Timer 2 as the baud-rate generator for
the receiver. The 16-bit reload value for Timer 2 is stored in the RCAP2L and RCA2H
SFRs, which makes the equation for the Timer 2 baud rate:
clk
Baud Rate =
32 x (65536 -{RCAP2H, RCAP2L})
where RCAP2H,RCAP2L is the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned number. The 32 in the denominator is the result of the CPU_clk signal being
divided by 2 and the Timer 2 overflow being divided by 16. Setting TCLK or RCLK to
1 automatically causes the CPU_clk signal to be divided by 2, as shown in Figure 23
Timer 2 – Baud Rate Generator Mode, instead of the 4 or 12 determined by the T2M bit
in the CKCON SFR.
To derive the required RCAP2H and RCAP2L values from a known baud rate, use the
equation:
clk
RCAP2H,RCAP2L = 65536 –
32 x Baud Rate
Table Table 73 lists sample values of RCAP2L and RCAP2H for a variety of
desired baud rates.
Baud Rate
C/T 16 MHz CPU clk
2
RCAP2H
0xFF
RCAP2L
0xF7
57.6 Kb/s
19.2 Kb/s
9.6 Kb/s
4.8 Kb/s
0.4 Kb/s
1.2 Kb/s
0
0
0
0
0
0
0xFF
0xFF
0xFF
0xFF
0xE6
0xCC
0x98
0x30
0x5F
0xFE
Table 73 Timer 2 Reload Values for Serial Port Mode 1 Baud Rates.
When either RCLK or TCLK is set, the TF2 flag will not be set on a Timer 2
rollover, and the t2ex reload trigger is disabled.
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18.9.2.2 Mode 1 Transmit
Figure 28 illustrates the mode 1 transmit timing. In mode 1, the UART begins
transmitting after the first rollover of the divide-by-16 counter after the software writes
to the SBUF register. The UART transmits data on the txd pin in the following order:
start bit, eight data bits (LSB first), stop bit. The TI bit is set two clock cycles after the
stop bit is transmitted.
Figure 28 Serial port Mode 1 Transmit Timing.
18.9.2.3 Mode 1 Receive
Figure 29 illustrates the mode 1 receive timing. Reception begins at the falling edge of a
start bit received on rxd_in, when enabled by the REN bit. For this purpose, rxd_in is
sampled sixteen times per bit for any baud rate. When a falling edge of a start bit is
detected, the divide-by-16 counter used to generate the receive clock is reset to align the
counter rollover to the bit boundaries.
Figure 29 Serial port Mode 1 Receive Timing.
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For noise rejection, the serial port establishes the content of each received bit by a
majority decision of three consecutive samples in the middle of each bit time. This is
especially true for the start bit. If the falling edge on rxd_in is not verified by a majority
decision of three consecutive samples (low), then the serial port stops reception and
waits for another falling edge on rxd_in.
At the middle of the stop bit time, the serial port checks for the following conditions:
-?RI = 0
- If SM2 = 1, the state of the stop bit is 1
(if SM2 = 0, the state of the stop bit does not matter)
If the above conditions are met, the serial port then writes the received byte to the SBUF
register, loads the stop bit into RB8, and sets the RI bit. If the above conditions are not
met, the received data is lost, the SBUF register and RB8 bit are not loaded, and the RI
bit is not set. After the middle of the stop bit time, the serial port waits for another high-
to-low transition on the rxd_in pin.
Mode 1 operation is identical to that of the standard 8051 when Timers 1 and 2 use
CPU_clk/12 (the default).
18.9.3 Mode 2
Mode 2 provides asynchronous, full-duplex communication, using a total of eleven bits:
- One start bit
- Eight data bits
- One programmable 9th bit
- One stop bit
The data bits are transmitted and received LSB first. For transmission, the 9th bit is
determined by the value in TB8. To use the 9th bit as a parity bit, move the value of the
P bit (SFR PSW.0) to TB8.
The mode 2 baud rate is either CPU_clk/32 or CPU_clk/64, as determined by the SMOD
bit. The formula for the mode 2 baud rate is:
2SMOD * clk
Baud Rate =
64
Mode 2 operation is identical to the standard 8051.
18.9.3.1 Mode 2 Transmit
Figure 30 illustrates the mode 2 transmit timing. Transmission begins after the first
rollover of the divide-by-16 counter following a software write to SBUF . The UART
shifts data out on the txd pin in the following order: start bit, data bits (LSB first), 9th
bit, stop bit. The TI bit is set when the stop bit is placed on the txd pin.
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Figure 30 Serial port Mode 2 Transmit Timing.
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
18.9.3.2 Mode 2 Receive
Figure 31 illustrates the mode 2 receive timing. Reception begins at the falling edge of a
start bit received on rxd_in, when enabled by the REN bit. For this purpose, rxd_in is
sampled sixteen times per bit for any baud rate. When a falling edge of a start bit is
detected, the divide-by-16 counter used to generate the receive clock is reset to align the
counter rollover to the bit boundaries.
Figure 31 Serial port Mode 2 Receive Timing.
For noise rejection, the serial port establishes the content of each received bit by a
majority decision of three consecutive samples in the middle of each bit time. This is
especially true for the start bit. If the falling edge on rxd_in is not verified by a majority
decision of three consecutive samples (low), then the serial port stops reception and
waits for another falling edge on rxd_in.
At the middle of the stop bit time, the serial port checks for the following conditions:
- RI = 0
- If SM2 = 1, the state of the stop bit is 1
(if SM2 = 0, the state of the stop bit does not matter)
If the above conditions are met, the serial port then writes the received byte to the SBUF
register, loads the 9th received bit into RB8, and sets the RI bit. If the above conditions
are not met, the received data is lost, the SBUF register and RB8 bit are not loaded, and
the RI bit is not set. After the middle of the stop bit time, the serial port waits for another
high-to-low transition on the rxd_in.
18.9.4 Mode 3
Mode 3 provides asynchronous, full-duplex communication, using a total of eleven bits:
- One start bit
- Eight data bits
- One programmable 9th bit
- One stop bit; the data bits are transmitted and received LSB first
The mode 3 transmit and receive operations are identical to mode 2. The mode 3 baud
rate generation is identical to mode 1. That is, mode 3 is a combination of mode 2
protocol and mode 1 baud rate. Figure 32 illustrates the mode 3 transmit timing. Mode 3
operation is identical to that of the standard 8051 when Timers 1 and 2 use CPU_clk/12
(the default).
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Figure 32 Serial port Mode 3 Transmit Timing.
Figure 33 illustrates the mode 3 receive timing.
Figure 33 Serial port Mode 3 Receive Timing.
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
18.9.5 Multiprocessor Communications
The multiprocessor communication feature is enabled in modes 2 and 3 when the SM2
bit is set in the SCON SFR for a serial port. In multiprocessor communication mode, the
9th bit received is stored in RB8 and, after the stop bit is received, the serial port
interrupt is activated only if RB8 = 1. A typical use for the multiprocessor
communication feature is when a master wants to send a block of data to one of several
slaves. The master first transmits an address byte that identifies the target slave. When
th
transmitting an address byte, the master sets the 9 bit to 1; for data bytes, the 9th bit is
0.
When SM2 = 1, no slave will be interrupted by a data byte. However, an address byte
interrupts all slaves so that each slave can examine the received address byte to
determine whether that slave is being addressed. Address decoding must be done by
software during the interrupt service routine. The addressed slave clears its SM2 bit and
prepares to receive the data bytes. The slaves that are not being addressed leave the SM2
bit set and ignore the incoming data bytes.
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19 PACKAGE OUTLINE
nRF9E5 uses the QFN 32L 5x5 green package with a mat tin finish. Dimensions are in
mm. Recommended soldering reflow profile can be found in application note nAN400-
08, QFN soldering reflow guidelines, www.nordicsemi.no.
+
A
A1
A2
b
D
E
e
J
K
L
Package
Type
QFN32
(5x5 mm)
Min
typ.
Max
0.8
0.9
0.0
0.65
0.69
0.18
0.23
0.3
3.2
3.3
3.4
3.2
3.3
3.4
0.3
0.4
0.5
5 BSC
5 BSC
0.5 BSC
0.05
Figure 34 nRF9E5 package outline.
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20 PCB LAYOUT AND DECOUPLING GUIDELINES
nRF9E5 is an extremely robust RF device due to internal voltage regulators and requires
the minimum of RF layout protocols. However the following design rules should still be
incorporated into the layout design.
A PCB with a minimum of two layers including a ground plane is recommended for
optimum performance. The nRF9E5 DC supply voltage should be decoupled as close as
possible to the VDD pins with high performance RF capacitors. It is preferable to mount
a large surface mount capacitor (e.g. 4.7mF tantalum) in parallel with the smaller value
capacitors. The nRF9E5 supply voltage should be filtered and routed separately from the
supply voltages of any digital circuitry.
Long power supply lines on the PCB should be avoided. All device grounds, VDD
connections and VDD bypass capacitors must be connected as close as possible to the
nRF9E5 IC. For a PCB with a topside RF ground plane, the VSS pins should be
connected directly to the ground plane. For a PCB with a bottom ground plane, the best
technique is to place via holes as close as possible to the VSS pins. A minimum of one
via hole should be used for each VSS pin.
Full swing digital data or control signals should not be routed close to the crystal or the
power supply lines.
A fully qualified RF-layout for the nRF9E5 and its surrounding components, including
antennas and matching networks, can be downloaded from www.nordicsemi.no.
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PRODUCT SPECIFICATION
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21 APPLICATION EXAMPLES
21.1 Differential Connection to a Loop Antenna
aaaaaaaa
R3
AREF
1K
C9
1nF
C10
100nF
AIN3
AIN2
AIN1
AIN0
VDD
C7
10nF
C5
33pF
C6
4.7nF
J1
Loop Antenna
9.5x9.5mm
R2
22K
C12
3.9pF
P00
1
24
23
22
21
20
19
18
17
P01
P02
P03
P04
P05
P06
P07
MOSI (P1.1)
MISO (P1.2)
P01
P02
P03
VDD
VSS
P04
P05
P06
VSS
IREF
VSS
2
3
4
5
6
7
8
nRF9E5
R6
18K
VDD
ANT2
C13
4.7pF
ANT1
VDD_PA
VSS
C3
33pF
VDD
VDD
C14
5.6pF
SCK (P1.0)
EECSN (P1.3)
VDD
U1
nRF9E5
R4
10K
C8
33pF
U2
CS
SO
WP
VSS
VDD
1
8
C4
3.3nF
0603
VCC
2
3
4
7
6
5
HOLD
SCK
SI
X1
R5
100K
C11
10nF
25XX320
16 MHz
R1
1M
C1
22pF
C2
22pF
aaaaaaaa
Figure 35 nRF9E5 application schematic, differential connection to a loop antenna
(868MHz).
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Component
Description
Size
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
0603
Value
22
22
33
3.3
33
4.7
10
33
1
100
10
3.9
4.7
5.6
1
22
1
10
100
18
Tol.
±5%
±5%
±5%
Units
pF
pF
pF
nF
pF
nF
nF
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
R1
R2
R3
R4
R5
R6
U1
NP0 ceramic chip capacitor, (Crystal oscillator)
NP0 ceramic chip capacitor, (Crystal oscillator)
NP0 ceramic chip capacitor, (PA supply decoupling)
X7R ceramic chip capacitor, (PA supply decoupling)
NP0 ceramic chip capacitor, (Supply decoupling)
X7R ceramic chip capacitor, (Supply decoupling)
X7R ceramic chip capacitor, (Supply decoupling)
NP0 ceramic chip capacitor, (Supply decoupling)
X7R ceramic chip capacitor, (AREF filtering)
X7R ceramic chip capacitor, (AREF filtering)
X7R ceramic chip capacitor
NP0 ceramic chip capacitor, (Antenna tuning)
NP0 ceramic chip capacitor, (Antenna tuning)
NP0 ceramic chip capacitor, (Antenna tuning)
0.1W chip resistor, (Crystal oscillator bias)
0.1W chip resistor, (Reference bias)
0.1W chip resistor
±10%
±5%
±10%
±10%
±5%
±10%
±10%
±10%
±0.1
±0.1
±0.1
±1%
±1%
±1%
±1%
±1%
±1%
pF
nF
nF
nF
pF
pF
pF
MW
kW
kW
kW
kW
kW
0.1W chip resistor
0.1W chip resistor
0603
0603
0603
0.1W chip resistor, (Antenna Q reduction)
nRF9E5 Transceiver
QFN32L/5x5
U2
X1
4 kbyte serial EEPROM with SPI interface
Crystal (see chapter 7.1)
SO8
LxWxH =
2XX320
16
MHz
±30ppm
4.0x2.5x0.8
Table 74 Recommended External Components, differential connection to a loop antenna
(868MHz).
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21.2 PCB Layout Example, Differential Connection to a Loop Antenna
Figure 36 shows a PCB layout example for the application schematic in Figure 35.
A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on
the bottom layer. Additionally, there are ground areas on the component side of the
board to ensure sufficient grounding of critical components. A large number of via holes
connect the top layer ground areas to the bottom layer ground plane. There is no ground
plane beneath the antenna.
No components in bottom layer
b) Bottom silk screen
a) Top silk screen
c) Top view
d) Bottom view
Figure 36 PCB layout example for nRF9E5, differential connection to a loop antenna.
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nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
21.3 Single Ended Connection to 50W Antenna
aaaaaaaa
868/915MHz
433MHz
C3 33pF, ±5%
180pF, ±5%
R3
1K
C12 3.9pF, ±0.25pF18pF, ±5%
C13 3.9pF, ±0.25pF18pF, ±5%
AREF
C9
1nF
C10
100nF
AIN3
AIN2
AIN1
AIN0
C14
Not fitted
Not fitted
6.8pF, ±5%
Not fitted
C15 33pF, ±5%
C16 Not fitted
VDD
L1 12nH, 5%
L2 12nH, 5%
12nH, 5%
39nH, 5%
C7
10nF
C5
33pF
C6
4.7nF
L3 12nH, 5%
39nH, 5%
C12
R2
C16
22K
C15
L2
L3
P00
P01
P02
P03
P04
P05
P06
P07
1
2
3
4
5
6
24
23
22
21
20
19
50 ohm RF I/O
P01
P02
P03
VDD
VSS
P04
P05
P06
VSS
IREF
VSS
ANT2
ANT1
VDD_PA
VSS
VDD
nRF9E5
L1
VDD
C14
Not fitted
7
8
18
17
C3
MOSI (P1.1)
VDD
MISO (P1.2)
SCK (P1.0)
EECSN (P1.3)
C13
VDD
U1
nRF9E5
R4
C8
10K
33pF
U2
CS
SO
WP
VSS
VDD
1
2
3
4
8
7
6
5
C4
3.3nF
VCC
HOLD
SCK
SI
X1
R5
100K
C11
10nF
25XX320
16 MHz
R1
1M
C1
22pF
C2
22pF
a a a a a a a a
Figure 37 nRF9E5 application schematic, single ended connection to 50W antenna by
using a differential to single ended matching network.
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PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
Component
Description
NP0 ceramic chip capacitor, (Crystal oscillator)
NP0 ceramic chip capacitor, (Crystal oscillator)
NP0 ceramic chip capacitor, (PA supply decoupling)
@ 433MHz
Size
0603
0603
0603
Value
22
22
Tol.
Units
pF
pF
C1
C2
C3
±5%
±5%
±5%
pF
180
33
@ 868
@ 915MHz
33
C4
C5
C6
C7
C8
X7R ceramic chip capacitor, (PA supply decoupling)
NP0 ceramic chip capacitor, (Supply decoupling)
0603
0603
0603
0603
0603
0603
0603
0603
0603
3.3
33
4.7
10
33
1
±10%
±5%
±10%
±10%
±5%
±10%
±10%
±10%
nF
pF
nF
nF
pF
nF
nF
nF
pF
X7R ceramic chip capacitor, (Supply decoupling)
X7R ceramic chip capacitor, (Supply decoupling)
NP0 ceramic chip capacitor, (Supply decoupling)
X7R ceramic chip capacitor, (AREF filtering)
X7R ceramic chip capacitor, (AREF filtering)
X7R ceramic chip capacitor
C9
C10
C11
C12
100
10
NP0 ceramic chip capacitor, (Impedance matching)
@ 433MHz
@ 868
@ 915MHz
18
3.9
3.9
±5%
<±0.25pF
<±0.25pF
C13
NP0 ceramic chip capacitor, (Impedance matching)
0603
pF
@ 433MHz
@ 868
@ 915MHz
18
3.9
3.9
±5%
<±0.25pF
<±0.25pF
C14
C15
NP0 ceramic chip capacitor, (Impedance matching)
NP0 ceramic chip capacitor, (Impedance matching)
0603
0603
Not fitted
pF
pF
@ 433MHz
@ 868
@ 915MHz
6.8
33
33
±5%
±5%
±5%
C16
L1
NP0 ceramic chip capacitor, (Impedance matching)
0603
0603
0603
pF
nH
nH
@ 433MHz
@ 868
@ 915MHz
Not fitted
Not fitted
Not fitted
Chip inductor, (Impedance matching)
@ 433MHz: SRF> 433MHz
@ 868MHz: SRF> 868MHz
@ 915MHz: SRF> 915MHz
Chip inductor, (Impedance matching)
@ 433MHz: SRF> 433MHz
@ 868MHz: SRF> 868MHz
@ 915MHz: SRF> 915MHz
±5%
12
12
12
L2
39
12
12
±5%
±5%
±5%
L3
Chip inductor, (Impedance matching)
@ 433MHz: SRF> 433MHz
@ 868MHz: SRF> 868MHz
@ 915MHz: SRF> 915MHz
0603
nH
39
12
12
±5%
±5%
±5%
R1
R2
R3
R4
R5
U1
0.1W chip resistor, (Crystal oscillator bias)
0.1W chip resistor, (Reference bias)
0.1W chip resistor
0.1W chip resistor
0.1W chip resistor
0603
0603
0603
0603
0603
1
22
1
10
100
±1%
±1%
±1%
±1%
±1%
MW
kW
kW
kW
kW
nRF9E5 Transceiver
QFN32L/5x5
U2
X1
4 kbyte serial EEPROM with SPI interface
Crystal (see chapter 7.1)
SO8
LxWxH =
2XX320
16
MHz
±30ppm
4.0x2.5x0.8
Table 75 Recommended External Components, single ended connection to 50W antenna.
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21.4 PCB Layout Example, Single Ended Connection to 50W Antenna
Figure 38 shows a PCB layout example for the application schematic in Figure 37.
A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on
the bottom layer. Additionally, there are ground areas on the component side of the
board to ensure sufficient grounding of critical components. A large number of via holes
connect the top layer ground areas to the bottom layer ground plane.
No components in bottom layer
b) Bottom silk screen
a) Top silk screen
c) Top view
d) Bottom view
Figure 38 PCB layout example for nRF9E5, single ended connection to 50W antenna by
using a differential to single ended matching network.
21.5 Configure the Chip as nRF905.
nRF9E5 is easily configurable as nRF905. Upon power up the boot loader is run. If
MISO is set to low value during the first 10ms, the microcontroller configures itself to
nRF905 mode. All pins are then defined as for the nRF905 chip.
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22 ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD...............................- 0.3V to + 3.6V
VSS .....................................................0V
Input Voltage
VI..........................- 0.3V to VDD + 0.3V
Output Voltage
VO.........................- 0.3V to VDD + 0.3V
Total Power Dissipation
PD (TA=85°C)................................ 230mW
Temperatures
Operating temperature............................................ - 40°C to + 85°C
Storage temperature...............................................- 40°C to + 125°C
Note: Stress exceeding one or more of the limiting values may cause permanent damage
to the device.
ATTENTION!
Electrostatic sensitive device.
Observe precaution for handling.
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23 GLOSSERY OF TERMS
Term
ADC
AM
Description
Analog to Digital Converter
Address Match
BOM
CD
Bill Of Material
Carrier Detect
CLK
Clock
CRC
CSN
DR
Cyclic Redundancy Check
SPI Chip Select Not
Data Ready
GFSK
GPIO
ISM
Gaussian Frequency Shift Keying
General Purpose Input Output
Industrial-Scientific-Medical
kilo Samples per Second
Micro Controller Unit
SPI Master In Slave Out
SPI Master Out Slave In
Pulse-Width Modulation
Power Down
ksps
MCU
MISO
MOSI
PWM
PWR_DWN
PWR_UP
RAM
ROM
RTC
Power Up
Random Access Memory
Read Only Memory
Real Time Clock
RX
Receive
SCK
SPI Serial Clock
SPI
Serial Programmable Interface
Standby
Transmit/Receive Enable
Transmit
STBY
TRX_EN
TX
TX_EN
UART
XTAL
Transmit Enable
Universal Asynchronous Receiver Transmitter
Crystal
Table 76 Glossary of terms.
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PRODUCT SPECIFICATION
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24 DEFINITIONS
Data sheet status
Objective product specification This datasheet contains target specifications for product development.
Preliminary
specification
product This datasheet contains preliminary data; supplementary data may be
published from Nordic Semiconductor ASA later.
Product specification
This datasheet contains final product specifications. Nordic Semiconductor
ASA reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Limiting values
Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Table 77 Definitions.
Nordic Semiconductor ASA reserves the right to make changes without further notice to
the product to improve reliability, function or design. Nordic Semiconductor does not
assume any liability arising out of the application or use of any product or circuits
described herein.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Nordic Semiconductor ASA customers using or selling these products for use in
such applications do so at their own risk and agree to fully indemnify Nordic
SemiconductorSemiconductor ASA for any damages resulting from such improper use
or sale.
Product specification revision date: 8.06.2004
Datasheet order code: 080604nRF9E5
All rights reserved ®. Reproduction in whole or in part is prohibited without the prior
written permission of the copyright holder.
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25 YOUR NOTES
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PRODUCT SPECIFICATION
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Nordic Semiconductor ASA – World Wide Distributors
For Your nearest dealer, please see http://www.nordicsemi.no
Main Office:
Vestre Rosten 81, N-7075 Tiller, Norway
Phone: +47 72 89 89 00, Fax: +47 72 89 89 89
Visit the Nordic Semiconductor ASA website at http://www.nordicsemi.no
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