NS32202-10中文资料_数据手册_规格书

July 1991

NS32202-10 Interrupt Control Unit

General Description

The NS32202 Interrupt Control Unit (ICU) is the interrupt

Features

Y

16 maskable interrupt sources, cascadable to 256

controller for the Series 32000 microprocessor family. It is

Programmable 8- or 16-bit data bus mode

Edge or level triggering for each hardware interrupt with

individually selectable polarities

É

a support circuit that minimizes the software and real-time

overhead required to handle multi-level, prioritized inter-

rupts. A single NS32202 manages up to 16 interrupt sources,

resolvesinterruptpriorities,andsuppliesasingle-byteinterrupt

vector to the CPU.

Y

8 software interrupts

Fixed or rotating priority modes

Two 16-bit, DC to 10 MHz counters, that may be con-

catenated into a single 32-bit counter

Optional 8-bit I/O port available in 8-bit data bus mode

High-speed XMOS^TMtechnology

The NS32202 can operate in either of two data bus modes:

16-bit or 8-bit. In the 16-bit mode, eight hardware and eight

software interrupt positions are available. In the 8-bit mode,

16 hardware interrupt positions are available, 8 of which can

be used as software interrupts. In this mode, up to 16 addi-

tional ICUs may be cascaded to handle a maximum of 256

interrupts.

Y

a

Single, 5V supply

40-pin, dual in-line package

Two 16-bit counters, which may be concatenated under pro-

gram control into a single 32-bit counter, are also available

for real-time applications.

Basic System Configuration

TL/EE/5117–1

Series 32000É is a registered trademark of National Semiconductor Corp.

XMOS^TMis a trademark of National Semiconductor Corp.

C

1995 National Semiconductor Corporation

TL/EE/5117

RRD-B30M105/Printed in U. S. A.

Table of Contents

1.0 PRODUCT INTRODUCTION

3.0 ARCHITECTURAL DESCRIPTION (Continued)

3.9 FPRT - First Priority Registers (R14, R15)

3.10 MCTL - Mode Control Register (R16)

3.11 OSCASN - Output Clock Assignment (R17)

3.12 CIPTR - Counter Interrupt Pointer Register (R18)

3.13 PDAT - Port Dada Register (R19)

1.1 I/O Buffers

1.2 Read/Write Logic and Decoders

1.3 Timing and Control

1.4 Priority Control

1.5 Counters

3.14 IPS - Interrupt/Port Select Register (R20)

3.15 PDIR - Port Direction Register (R21)

2.0 FUNCTIONAL DESCRIPTION

2.1 Reset

3.16 CCTL - Counter Control Register (R22)

3.17 CICTL - Counter Interrupt Control Register (R23)

2.2 Initialization

2.3 Vectored Interrupt Handling

3.18 LCSV/HCSV - L-Counter Starting Value/H-Counter

Starting Value Registers (R24, R25, R26, and R27)

2.3.1 Non-Cascaded Operation

2.3.2 Cascade Operation

3.19 LCCV/HCCV - L-Counter Current Value/H-Counter

Current Value Registers (R28, R29, R30, and R31)

2.4 Internal ICU Operating Sequence

2.5 Interrupt Priority Modes

3.20 Register Initialization

4.0 DEVICE SPECIFICATIONS

2.5.1 Fixed Priority Mode

4.1 NS32202 Pin Descriptions

2.5.2 Auto-Rotate Mode

2.5.3 Special Mask Mode

2.5.4 Polling Mode

4.1.1 Power Supply

4.1.2 Input Signals

4.1.3 Output Signals

4.1.4 Input/Output Signals

3.0 ARCHITECTURAL DESCRIPTION

3.1 HVCT - Hardware Vector Register (R0)

4.2 Absolute Maximum Ratings

4.3 Electrical Characteristics

4.4 Switching Characteristics

3.2 SVCT - Software Vector Register (R1)

3.3 ELTG - Edge/Level Triggering Registers (R2, R3)

3.4 TPL - Triggering Polarity Registers (R4, R5)

3.5 IPND - Interrupt Pending Registers (R6, R7)

3.6 ISRV - Interrupt In-Service Registers (R8, R9)

3.7 IMSK - Interrupt Mask Registers (R10, R11)

3.8 CSRC - Cascaded Source Registers (R12, R13)

4.4.1 Definitions

4.4.1.1 Timing Tables

4.4.1.2 Timing Diagrams

List of Illustrations

NS32202 ICU Block Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-1

Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial ValuesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-2

Counter Configuration and Basic OperationsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-3

Interrupt Control Unit Connections in 16-Bit Bus Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-1

Interrupt Control Unit Connections in 8-Bit Bus Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-2

Cascaded Interrupt Control Unit Connections in 8-Bit Bus Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-3

CPU Interrupt Acknowledge SequenceÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-4

Interrupt Dispatch and Cascade Tables ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-5

CPU Return from Interrupt Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-6

ICU Interrupt Acknowledge Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-7

ICU Return from Interrupt Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-8

ICU Internal Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-1

HVCT Register Data Coding ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-2

Recommended ICU’s Initialization Sequence ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-3

NS32202 ICU Connection Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-1

Timing Specification Standard ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-2

READ/INTA Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-3

Write CycleÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-4

Interrupt Timing in Edge Triggering ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-5

Interrupt Timing in Level Triggering Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-6

External Interrupt-Sampling-Clock to be Provided at Pin COUT/SCIN When in Test ModeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-7

Internal Interrupt-Sampling-Clock to be Provided at Pin COUT/SCIN ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-8

Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT/SCIN or G0/R0–G3/R6,

in Both Pulsed Form and Square Waveform ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-9

2

1.0 Product Introduction

The NS32202 ICU functions as an overall manager in an

interrupt-oriented system environment. Its many features

and options permit the design of sophisticated interrupt sys-

tems.

1.4 PRIORITY CONTROL

The Priority Control Block contains 16 units, one for each

interrupt position. These units provide the following func-

tions.

Figure 1–1 shows the internal organization of the NS32202.

As shown, the NS32202 is divided into five functional

blocks. These are described in the following paragraphs:

Sensing the various forms of hardware interrupt sig-

nals e.g. level (high/low) or edge (rising/falling)

Resolving priorities and generating an interrupt re-

quest to the CPU

Handling cascaded arrangements

Enabling software interrupts

Providing for an automatic return from interrupt

Enabling the assignment of any interrupt position to

the internal counters

Providing for rearrangement of priorities by assigning

the first priority to any interrupt position

Enabling automatic rotation of priorities

#

1.1 I/O BUFFERS AND LATCHES

#

The I/O Buffers and Latches block is the interface with the

system data bus. It contains bidirectional buffers for the

data I/O pins. It also contains registers and logic circuits

that control the operation of pins G0/IR0, . . . ,G7/IR14

when the ICU is in the 8-bit bus mode.

#

1.2 READ/WRITE LOGIC AND DECODERS

#

The Read/Write Logic and Decoders manage all internal

and external data transfers for the ICU. These include Data,

Control, and Status Transfers. This circuit accepts inputs

from the CPU address and control buses. In turn, it issues

commands to access the internal registers of the ICU.

1.5 COUNTERS

This block contains two 16-bit counters, called the H-coun-

ter and the L-counter. These are down counters that count

from an initial value to zero. Both counters have a 16-bit

register (designated HCSV and LCSV) for loading their re-

starting values. They also have registers containing the cur-

rent count values (HCCV and LCCV). Both sets of registers

are fully described in Section 3.

1.3 TIMING AND CONTROL

The Timing and Control Block contains status elements that

select the ICU operating mode. It also contains state ma-

chines that generate all the necessary sequencing and con-

trol signals.

TL/EE/5117–2

FIGURE 1–1. NS32202 ICU Block Diagram

3

1.0 Product Introduction (Continued)

2.0 Functional Description

2.1 RESET

The counters are under program control and can be used to

generate interrupts. When the count reaches zero, either

counter can generate an interrupt request to any of the 16

interrupt positions. The counter then reloads the start value

from the appropriate registers and resumes counting. Figure

1–2 shows typical counter output signals available from the

NS32202.

The ICU is reset when a logic low signal is present on the

RST pin. At reset, most internal ICU registers are affected,

and the ICU becomes inactive.

2.2 INITIALIZATION

After reset, the CPU must initialize the NS32202 to establish

its configuration. Proper initialization requires knowledge of

the ICU register’s formats. Therefore, a flowchart of a rec-

ommended initialization sequence is shown in (Figure 3–3 )

after the discussion of the ICU registers.

The maximum input clock frequency is 2.5 MHz.

A divide-by-four prescaler is also provided. When the pre-

scaler is used, the input clock frequency can be up to 10

MHz.

The operation sequence shown in Figure 3–3 ensures that

all counter output pins remain inactive until the counters are

completely initialized.

When intervals longer than provided by a 16-bit counter are

needed, the L- and H-counters can be concatenated to form

a 32-bit counter. In this case, both counters are controlled

by the H-counter control bits. Refer to the discussion of the

Counter Control Register in Section 3 for additional informa-

tion. Figure 1-3 summarizes counter read/write operations.

2.3 VECTORED INTERRUPT HANDLING

For details on the operation of the vectored interrupt mode

for a particular Series 32000 CPU, refer to the data sheet for

TL/EE/5117–4

FIGURE 1–2. Counter Output Signals in Pulsed Form and Square Waveform for Three Different Initial Values

4

2.0 Functional Description (Continued)

that CPU. In this discussion, it is assumed that the NS32202

is working with a CPU in the vectored interrupt mode. Sever-

al ICU applications are discussed, including non-cascaded

and cascaded operation. Figures 2–1, 2–2, and 2–3 show

typical configurations of the ICU used with the NS32016

CPU.

rupt Output (INT) pin and generates an interrupt vector byte.

The interrupt vector byte identifies the interrupt source in its

four least significant bits. When the CPU detects a low level

on its Interrupt Input pin, it performs one or two interrupt

acknowledge cycles depending on whether the interrupt re-

quest is from the master ICU or a cascaded ICU. Figure 2–4

shows a flowchart of a typical CPU Interrupt Acknowledge

sequence.

A peripheral device issues an interrupt request by sending

the proper signal to one of the NS32202 interrupt inputs. If

the interrupt input is not masked, the ICU activates its Inter-

TL/EE/5117–5

BASIC OPERATIONS:

WRITING TO LCSV/HCSV

READING LCSV/HCSV

WRITING TO LCCV/HCCV

A

w

x

w

x

(IDB)

A

B

C

(only possible when counters are halted)

READING LCCV/HCCV

(only possible when counter

readings are frozen)

COUNTER COUNTS AND READINGS ARE

NOT FROZEN

C

B

A

w

B

COUNTER RELOADS STARTING VALUE

(occurs on the clock cycle following

the one in which it reaches zero)

FIGURE 1–3. Counter Configuration and Basic Operations

5

2.0 Functional Description (Continued)

TL/EE/5117–6

FIGURE 2–1. Interrupt Control Unit Connections in 16-Bit Bus Mode

TL/EE/5117–7

NOTE: In the 8-Bit Bus Mode the Master ICU Registers appear at even

e

addresses (A0 0) since the ICU communicates with the least sig-

nificant byte of the CPU data bus.

FIGURE 2–2. Interrupt Control Unit Connections in 8-Bit Bus Mode

6

2.0 Functional Description (Continued)

TL/EE/5117–8

FIGURE 2–3. Cascaded Interrupt Control Unit Connections in 8-Bit Bus Mode

7

2.0 Functional Description (Continued)

* Cond. A is true if current instruction is terminated

or an interruptible point in a string instruction is

reached.

TL/EE/5117–9

FIGURE 2–4. CPU Interrupt Acknowledge Sequence

8

2.0 Functional Description (Continued)

In general, vectored interrupts are serviced by interrupt rou-

tines stored in system memory. The Dispatch Table stores

up to 256 external procedure descriptors for the various

service procedures. The CPU INTBASE register points to

the top of the Dispatch Table. Figure 2–5 shows the layout

of the Dispatch Table. This figure also shows the layout of

the Cascade Table, which is discussed with ICU cascaded

operation.

2.3.2 Cascaded Operation. In cascaded operation, one or

more of the interrupt inputs of the master ICU are connect-

ed to the Interrupt Output pin of one or more cascaded

ICUs. Up to 16 cascaded ICUs may be used, giving a sys-

tem total of 256 interrupts.

Note: The number of cascaded ICUs is practically limited to 15 because the

Dispatch Table for the NS32016 CPU is constructed with entries 1

through 15 either used for NMI and Trap descriptors, or reserved for

future use. Interrupt position 0 of the master ICU should not be cas-

caded, so it can be vectored through Dispatch Table entry 0, reserved

for non-vectored interrupts. In this case, the non-vectored interrupt

entry (entry 0) is also available for vectored interrupt operation, since

the CPU is operating in the vectored interrupt mode.

2.3.1 Non-Cascaded Operation. Whenever an interrupt re-

quest from a peripheral device is issued directly to the mas-

ter ICU, a non-cascaded interrupt request to the CPU re-

sults. In a system using a single NS32202, up to 16 interrupt

requests can be prioritized. Upon receipt of an interrupt re-

quest on the INT pin, the CPU performs a Master Interrupt-

Acknowledge bus cycle, reading a vector byte from address

The address of the master ICU should be FFFE00 . (*)

16

Cascaded ICUs can be located at any system address. A list

of cascaded ICU addresses is maintained in the Cascade

Table as a series of sixteen 32-bit entries.

FFFE00 . This vector is then used as an index into the

16

(*)Note: The CPU status corresponding to both, master interrupt acknowl-

edge and return from interrupt bus cycles, as well as address bit A8,

could be used to generate the chip select (CS) signal for accessing

the master ICU during one of the above cycles. In this case the

master ICU can reside at any system address. The only limitation is

that the least significant 5 or 6 address bits (6 in the 8-bit bus mode)

must be zero. The address bit A8 must be decoded to prevent an

NMI bus cycle from reading the hardware vector register of the ICU.

This could happen, since the NS32016 CPU performs a dummy

dispatch table in order to find the External Procedure De-

scriptor for the proper interrupt service procedure. The serv-

ice procedure eventually returns via the Return-from-Inter-

rupt (RET) instruction, which performs a Return-from-Inter-

rupt bus cycle, informing the ICU that it may re-prioritize any

interrupt requests still pending. Figure 2–6 shows a typical

CPU RETI sequence. In a system with only one ICU, the

vectors provided must be in the range of 0 through 127; this

can be ensured by writing 0XXXXXXX into the SVCT regis-

ter. By providing a negative vector value, the master ICU

flags the interrupt source as a cascaded ICU (see below).

read cycle from address FFFF00 , with the same status as a mas-

16

ter INTA cycle, when a non-maskable-interrupt is acknowledged.

TL/EE/5117–10

* Table entries 1 to 15 should not be used by the ICU since they contain NMI and Trap Descriptors

or are reserved for future use. (For more details refer to NS32016 data sheet.)

FIGURE 2–5. Interrupt Dispatch and Cascade Tables

9

2.0 Functional Description (Continued)

cascaded ICU, of course, has its own set of 16 unique inter-

rupt vectors, one vector for each of its 16 interrupt positions.

The CPU interprets the vector value read during a Cascad-

ed Interrupt Acknowledge cycle as an unsigned number.

Thus, this vector can be in the range 0 through 255.

When a cascaded interrupt service routine completes its

task, it must return control to the interrupted program with

the same RETI instruction used in non-cascaded interrupt

service routines. However, when the CPU performs a Mas-

ter Return From Interrupt cycle, the CPU accesses the mas-

ter ICU and reads the negative Cascade Table index identi-

fying the cascaded ICU that originally received the interrupt

request. Using the cascaded ICU address, the CPU now

performs a Cascaded Return From Interrupt cycle, informing

the cascaded ICU that the service routine is over. The byte

provided by the cascaded ICU during this cycle is ignored.

2.4 INTERNAL ICU OPERATING SEQUENCE

The NS32202 ICU accepts two interrupt types, software and

hardware.

Software interrupts are initiated when the CPU sets the

proper bit in the Interrupt Pending (IPND) registers (R6, R7),

located in the ICU. Bits are set and reset by writing the

proper byte to either R6 or R7. Software interrupts can be

masked, by setting the proper bit in the mask registers (R10,

R11).

Hardware interrupts can be either internal or external to the

ICU. Internal ICU hardware interrupts are initiated by the on-

chip counter outputs. External hardware interrupts are initia-

ted by devices external to the ICU, that are connected to

any of the ICU interrupt input pins.

Hardware interrupts can be masked by setting the proper bit

in the mask registers (R10, R11). If the Freeze bit (FRZ),

located in the Mode Control Register (MCTL), is set, all in-

coming hardware interrupts are inhibited from setting their

corresponding bits in the IPND registers. This prevents the

ICU from recognizing any hardware interrupts.

Once the ICU is initialized, it is enabled to accept interrupts.

If an active interrupt is not masked, and has a higher priority

than any interrupt currently being serviced, the ICU acti-

vates its Interrupt Output (INT). Figure 2–7 is a flowchart

showing the ICU interrupt acknowledge sequence.

TL/EE/5117–11

FIGURE 2–6. CPU Return from Interrupt Sequence

The master ICU maintains a list (in the CSRC register pair)

of its interrupt positions that are cascaded. It also provides a

4-bit (hidden) counter (in-service counter) for each interrupt

position to keep track of the number of interrupts being

serviced in the cascade ICUs. When a cascaded interrupt

input is active, the master ICU activates its interrupt output

and the CPU responds with a Master Interrupt Acknowledge

Cycle. However, instead of generating a positive interrupt

vector, the master ICU generates a negative Cascade Table

index.

The CPU responds to the active INT line by performing an

Interrupt Acknowledge bus cycle. During this cycle, the ICU

clears the IPND bit corresponding to the active interrupt po-

sition and sets the corresponding bit in the Interrupt In-Serv-

ice Registers (ISRV). The 4-bit in-service counter in the

master ICU is also incremented by one if the fixed priority

mode is selected and the interrupt is from a cascaded ICU.

The ISRV bit remains set until the CPU performs a RETI bus

cycle and the 4-bit in-service counter is decremented to

zero. Figure 2–8 is a flowchart showing ICU operation dur-

ing a RETI bus cycle.

The CPU interprets the negative number returned from the

master ICU as an index into the Cascade Table. The Cas-

cade Table is located in a negative direction from the Dis-

patch Table, and it contains the virtual addresses of the

hardware vector registers for any cascaded NS32202s in

the system. Thus, the Cascade Table index supplied by the

master ICU identifies the cascaded ICU that requested the

interrupt.

When the ISRV bit is set, the INT output is disabled. This

output remains inactive until a higher priority interrupt posi-

tion becomes active, or the ISRV bit is cleared.

An exception to the above occurs in the master ICU when

the fixed priority mode is selected, and the interrupt input is

connected to the INT output of a cascaded ICU. In this case

the ISRV bit does not inhibit an interrupt of the same priority.

Once the cascaded ICU is identified, the CPU performs a

Cascaded Interrupt Acknowledge cycle. During this cycle,

the CPU reads the final vector value directly from the cas-

caded ICU, and uses it to access the Dispatch Table. Each

This is to allow nesting of interrupts in a cascaded ICU.

10

2.0 Functional Description (Continued)

* Cond. B is true if any one of the following condi-

tions is satisfied.

1) No interrupt is being serviced

2) There is

a pending unmasked interrupt with

priority higher than that of the interrupt being

serviced.

3) There is a pending unmasked interrupt from a

cascaded ICU with priority higher or same as that

of the highest priority interrupt position in the

master ICU with the ISRV bit set.

TL/EE/5117–12

FIGURE 2–7. ICU Interrupt Acknowledge Sequence

11

2.0 Functional Description (Continued)

TL/EE/5117–13

FIGURE 2–8. ICU Return from Interrupt Sequence

12

2.0 Functional Description (Continued)

2.5 INTERRUPT PRIORITY MODES

The bits of the ISRV registers are changed with either the

Set Bit Interlocked or Clear Bit Interlocked instructions (SBI-

TIW or CBITIW). The in-service bit is cleared to enable low-

er priority interrupts and set to disable them.

The NS32202 ICU can operate in one of four interrupt priori-

ty modes: Fixed Priority; Auto-Rotate; Special Mask; and

Polling. Each mode is described below.

Note: For proper operation of the ICU, an interrupt service routine must set

its ISRV bit before executing the RETI instruction. This prevents the

RETI cycle from clearing the wrong ISRV bit.

2.5.1 Fixed Priority Mode

In the Fixed Priority Mode (also called Fully Nested Mode),

each interrupt position is ranked in priority from 0 to 15, with

0 being the highest priority. In this mode, the processing of

lower priority interrupts is nested with higher priority inter-

rupts. Thus, while an interrupt is being serviced, any other

interrupts of the same or lower priority are inhibited. The ICU

does, however, recognize higher priority interrupt requests.

2.5.4 Polling Mode

The Polling Mode gives complete control of interrupt priority

to the system software. Either some or all of the interrupt

positions can be assigned to the polling mode. To assign all

interrupt positions to the polling mode, the CPU interrupt

enable flag is reset. To assign only some of the interrupt

positions to the polling mode, the desired interrupt positions

are masked in the Interrupt Mask registers (IMSK). In either

case, the polling operation consists of reading the Interrupt

Pending (IPND) registers.

When the interrupt service routine executes its RETI instruc-

tion, the corresponding ISRV bit is cleared. This allows any

lower priority interrupt request to be serviced by the CPU.

At reset, the default priority assignment gives interrupt IR0

priority 0 (highest priority), interrupt IR1 priority 1, and so

forth. Interrupt IR15 is, of course, assigned priority 15, the

lowest priority. The default priority assignment can be al-

tered by writing an appropriate value into register FPRT (L)

as explained in Section 3.9.

If necessary, the IPND read can be synchronized by setting

the Freeze (FRZ) bit in the Mode Control register (MCTL).

This prevents any change in the IPND registers during the

read. The FRZ bit must be reset after the polling operation

so the IPND contents can be updated. If an edge-triggered

interrupt occurs while the IPND registers are frozen, the in-

terrupt request is latched, and transferred to the IPND regis-

ters as soon as FRZ is reset.

Note: When the ICU generates an interrupt request to the CPU for a higher

priority interrupt while a lower priority interrupt is still being serviced by

the CPU, the CPU responds to the interrupt request only if its internal

interrupt enable flag is set. Normally, this flag is reset at the beginning

of an interrupt acknowledge cycle and set during the RETI cycle. If the

CPU is to respond to higher priority interrupts during any interrupt

service routine, the service routine must set the internal CPU interrupt

enable flag, as soon during the service routine as desired.

The polling mode is useful when a single routine is used to

service several interrupt levels.

3.0 Architectural Description

2.5.2 Auto-Rotate Mode

The NS32202 has thirty-two 8-bit registers that can be ac-

cessed either individually or in pairs. In 16-bit data bus

mode, register pairs can be accessed with the CPU word or

double-word reference instructions. Figure 3–1 shows the

ICU internal registers. This figure summarizes the name,

function, and offset address for each register.

The Auto Rotate Mode is selected when the NTAR bit is set

to 0, and is automatically entered after Reset. In this mode

an interrupt source position is automatically assigned lowest

priority after a request at that position has been serviced.

Highest priority then passes to the next lower priority posi-

tion. For example, when servicing of the interrupt request at

position 3 is completed (ISRV bit 3 is cleared), interrupt po-

sition 3 is assigned lowest priority and position 4 assumes

highest priority. The nesting of interrupts is inhibited, since

the interrupt being serviced always has the highest priority.

Because some registers hold similar data, they are grouped

into functional pairs and assigned a single name. However,

if a single register in a pair is referenced, either an L or an H

is appended to the register name. The letters are placed in

parentheses and stand for the low order 8 bits (L) and the

high order 8 bits (H). For example, register R6, part of the

Interrupt Pending (IPND) register pair, is referred to individu-

ally as IPND(L).

This mode is used when the interrupting devices have to be

assigned equal priority. A device requesting an interrupt, will

have to wait, in the worst case, until each of the 15 other

devices has been serviced at most once.

The following paragraphs give detailed descriptions of the

registers shown in Figure 3–1.

2.5.3 Special Mask Mode

The Special Mask Mode is used when it is necessary to

dynamically alter the ICU priority structure while an interrupt

is being serviced. For example, it may be desired in a partic-

ular interrupt service routine to enable lower priority inter-

rupts during a part of the routine. To do so, the ICU must be

programmed in fixed priority mode and the interrupt service

routine must control its own in-service bit in the ISRV regis-

ters.

3.1 HVCT Ð HARDWARE VECTOR REGISTER (R0)

The HVCT register is a single register that contains the in-

terrupt vector byte supplied to the CPU during an Interrupt

Acknowledge (INTA) or Return From Interrupt (RETI) cycle.

The HVCT bit map is shown below:

7

6

5

4

3

2

1

0

B

V

13

3.0 Architectural Description (Continued)

REG. NUMBER AND

ADDRESS IN HEX.

REG.

REG. FUNCTION

NAME

R0 (00

R1 (01

R2 (02

R4 (04

R6 (06

R8 (08

)

HVCT Ð

SVCT Ð

ELTG Ð

TPL Ð

HARDWARE VECTOR

16

SOFTWARE VECTOR

R3 (03

R5 (05

R7 (07

R9 (09

)

EDGE/LEVEL TRIGGERING

TRIGGERING POLARITY

INTERRUPTS PENDING

INTERRUPTS IN-SERVICE

INTERRUPT MASK

16

IPND Ð

ISRV Ð

IMSK Ð

CSRC Ð

FPRT Ð

MCTL Ð

OCASN Ð

CIPTR Ð

PDAT Ð

IPS Ð

R11 (0B

)

R10 (0A

R12 (0C

R14 (0E

)

16

R13 (0D

)

CASCADED SOURCE

R15 (0F

)

FIRST PRIORITY

16

R16 (10

R17 (11

R18 (12

R19 (13

R20 (14

R21 (15

R22 (16

R23 (17

R24 (18

)

MODE CONTROL

16

OUTPUT CLOCK ASSIGNMENT

COUNTER INTERRUPT POINTER

PORT DATA

INTERRUPT/PORT SELECT

PORT DIRECTION

PDIR Ð

CCTL Ð

CICTL Ð

LCSV Ð

HCSV Ð

LCCV Ð

HCCV Ð

COUNTER CONTROL

COUNTER INTERRUPT CONTROL

L-COUNTER STARTING VALUE

H-COUNTER STARTING VALUE

L-COUNTER CURRENT VALUE

H-COUNTER CURRENT VALUE

R25 (19

)

16

R27 (1B

R29 (1D

)

R26 (1A

R28 (1C

R30 (1E

)

16

)

16

R31 (1F

)

16

FIGURE 3–1. ICU Internal Registers

14

3.0 Architectural Description (Continued)

The BBBB field is the bias which is programmed by writing

BBBB0000 to the SVCT register (R1). The VVVV field iden-

2

tifies one of the 16 interrupt positions. The contents of the

HVCT register provide various information to the CPU, as

shown in Figure 3–2:

TL/EE/5117–14

3.3 ELTG Ð EDGE/LEVEL TRIGGERING

REGISTERS (R2, R3)

Note 1: The ICU always interprets a read of the HVCT register as either an

INTA or RETI cycle. Since these cycles cause internal changes to

the ICU, normal programs must never read the ICU HVCT register.

The ELTG registers determine the input trigger mode for

each of the 16 interrupt inputs. Each input is assigned a bit

in this register pair. An interrupt input is level-triggered if its

bit in ELTG is set to 1. The input is edge-triggered if its bit is

cleared. At reset, all bits in ELTG are set to 1.

e

Note 2: If the HVCT register is read with ST1

0 (INTA cycle) and no

unmasked interrupt is pending, the binary value BBBB1111 is re-

turned and any pending edge-triggered interrupt in position 15 is

cleared.

If the auto-rotate priority mode is selected, the FPRT register is also

cleared, thus preventing any interrupt from being acknowledged. In

this case a re-intialization of the FPRT register is required for the

ICU to acknowledge interrupts again.

If odd-numbered interrupt positions must be used for soft-

ware interrupts, the edge triggering mode must be selected

and the corresponding interrupt inputs should be prevented

from changing state.

e

If a read of the HVCT register is performed with ST1

cycle), the binary value BBBB1111 is returned.

1 (RETI

3.4 TPL Ð TRIGGERING POLARITY

REGISTERS (R4, R5)

If the auto-rotate mode is selected, a priority rotation is also per-

formed.

The TPL registers determine the polarity of either the active

level or the active edge for each of the 16 interrupt inputs.

As with the ELTG registers, each input is assigned a bit.

Possible triggering modes for the various combinations of

ELTG and TPL bits are shown below.

3.2 SVCT Ð SOFTWARE VECTOR REGISTER (R1)

The SVCT register is a copy of the HVCT register. It allows

the programmer to read the contents of the HVCT register

without initiating a INTA or RETI cycle in the ICU. It also

allows a programmer to change the BBBB field of the HVCT

register. The bit map of the SVCT register is the same as for

the HVCT register.

ELTG BIT

TPL BIT

TRIGGERING MODE

Falling Edge

Rising Edge

0

1

0

1

0

1

During a write to SVCT, the four least significant bits are

unaffected while the four most significant bits are written

into both SVCT and HVCT (R1 and R0).

Low Level

High Level

Software interrupt positions are not affected by their TPL

bits. At reset, all TPL bits are set to 0.

The SVCT register is updated dynamically by the ICU. The

four least significant bits always contain the vector value

that would be returned to the CPU if a INTA or RETI cycle

were executed. Therefore, when reading the SVCT register,

the state of the CPU ST1 pin is used to select either pend-

ing interrupt data or in-service interrupt data. For example, if

Note 1: If edged-triggered interrupts are to be handled, the TPL register

should be programmed before the ELTG register.

This prevents spurious interrupt requests from being generated dur-

ing the ICU initialization from edge-triggered interrupt positions.

Note 2: Hardware interrupt inputs connected to cascaded ICUs must have

e

the SVCT register is read with ST1

0 (as for an INTA

their TPL bits set to 0.

cycle), the VVVV field contains the encoded value of the

highest priority pending interrupt. On the other hand, if the

3.5 IPND Ð INTERRUPT PENDING REGISTERS (R6, R7)

e

the encoded value of the highest priority in-service interrupt.

SVCT register is read with ST1

1, the VVVV field contains

The IPND registers track interrupt requests that are pending

but not yet serviced. Each interrupt position is assigned a bit

in IPND. When an interrupt is pending, the corresponding bit

in IPND is set. The IPND data are used by the ICU to gener-

ate interrupts to the CPU. These data are also used in poll-

ing operations.

Note: If the CPU ST1 output is connected directly to the ICU ST1 input, the

vector read from SVCT is always the RETI vector. If both the INTA

and RETI vectors are desired, additional logic must be added to drive

the ICU ST1 input. A typical circuit is shown below. In this circuit, the

state of the ICU ST1 input is controlled by both the CPU ST1 output

and the selected address bit.

e

INTA CYCLE (ST1 0)

e

RETI CYCLE (ST1 1)

Highest priority pending interrupt is from:

Highest priority in-service interrupt was from:

cascaded ICU

1111

any other source

cascaded ICU

1111

any other source

BBBB

VVVV

programmed bias*

encoded value of the highest

priority pending interrupt

encoded value of the highest

priority in-service interrupt

*The Programmed bias for the master ICU must range from 0000 to 0111 because the CPU interprets a one in the most significant bit position as a Cascade Table

2

Index indicator for a cascaded ICU.

FIGURE 3–2. HVCT Register Data Coding

15

3.0 Architectural Description (Continued)

The IPND registers are also used for requesting software

interrupts. This is done by writing specially formatted data

bytes to either IPND(L) or IPND(H). The formats differ for

registers R6 and R7. These formats are shown below:

3.7 IMSK Ð INTERRUPT MASK REGISTERS (R10, R11)

Each NS32202 interrupt position can be individually

masked. A masked interrupt source is not acknowledged by

the ICU. The IMSK registers store a mask bit for each of the

ICU interrupt positions. If an interrupt position’s IMSK bit is

set to 1, the position is masked.

IPND(L) (R6) Ð S0000PPP

IPND(H) (R7) Ð S0001PPP

e

1) or Clear (S 0)

Where:

S

Set (S

The IMSK registers are controlled by the system software.

At reset, all IMSK bits are set to 1, disabling all interrupts.

PPP

is a binary number identifying one of

eight bits

Note: If an interrupt must be masked off, the CPU can do so by setting the

corresponding bit in the IMSK register. However, if an interrupt is set

pending during the CPU instruction that masks off that interrupt, the

CPU may still perform an interrupt acknowledge cycle following that

instruction since it might have sampled the INT line before the ICU

deasserted it. This could cause the ICU to provide an invalid vector.

To avoid this problem, the above operation should be performed with

the CPU interrupt disabled.

Note: The data read from either R6 or R7 are different from that written to

the register because the ICU returns the register contents, rather than

the formatted byte used to set the register bits.

The ICU automatically clears a set IPND bit when the pend-

ing interrupt request is serviced. All pending interrupts in a

register can be cleared by writing the pattern ‘X1XXXXXX’

e

to it (X

don’t care). To avoid conflicts with asynchronous

3.8 CSRC Ð CASCADED SOURCE

REGISTERS (R12, R13)

hardware interrupt requests, the IPND registers should be

frozen before pending interrupts are cleared. Refer to the

Mode Control Register description for details on freezing

the IPND registers.

The CSRC registers track any cascaded interrupt positions.

Each interrupt position is assigned a bit in the CSRC regis-

ters. If an interrupt position’s CSRC bit is set, that position is

connected to the INT output of another NS32202 ICU, i.e., it

is a cascaded interrupt.

At reset, all IPND bits are set to 0.

Note: The edge sensing mechanism used for hardware interrupts in the

NS32202 ICU is a latching device that can be cleared only by ac-

knowledging the interrupt or by changing the trigger mode to level

sensing. Therefore, before clearing pending interrupts in the IPND

registers, any edge-triggered interrupt inputs must first be switched to

the level-triggered mode. This clears the edge-triggered interrupts;

the remaining interrupts can then be cleared in the manner described

above. This applies to clearing the interrupts only. Edge-triggered in-

terrupts can be set without changing the trigger mode.

At reset, the CSRC registers are set to 0.

Note 1: If any cascaded ICU is used, the CSRC register should be cleared

during initialization (if the initialization does not follow a hardware

reset) by writing zeroes into it. This should be done before setting

the bits corresponding to the cascaded interrupt positions. This op-

eration ensures that the 4-bit in-service counters (associated with

each interrupt position to keep track of cascaded interrupts) always

get cleared when the ICU is re-initialized.

3.6 ISRV Ð INTERRUPT IN-SERVICE

REGISTERS (R8, R9)

Note 2: Only the Master ICU should have any CSRC bits set. If CSRC bits

are set in a cascaded ICU, incorrect operation results.

The ISRV registers track interrupt requests that are current-

ly being serviced. Each interrupt position is assigned a bit in

ISRV. When an interrupt request is serviced by the ICU, its

corresponding bit is set in the ISRV registers. Before gener-

ating an interrupt to the CPU, the ICU checks the ISRV reg-

isters to ensure that no higher priority interrupt is currently

being serviced.

3.9 FPRT Ð FIRST PRIORITY REGISTERS (R14, R15)

The FPRT registers track the ICU interrupt position that cur-

rently holds first priority. Only one bit of the FPRT registers

is set at one time. The set bit indicates the interrupt position

with first (highest) priority.

The FPRT registers are automatically updated when the ICU

is in the auto-rotate mode. The first priority interrupt can be

determined by reading the FPRT registers. This operation

returns a 16-bit word with only one bit set. An interrupt posi-

tion can be assigned first priority by writing a formatted data

byte to the FPRT(L) register. The format is shown below:

Each time the CPU executes an RETI instruction, the ICU

clears the ISRV bit corresponding to the highest priority in-

terrupt in service. The ISRV registers can also be written

into by the CPU. This is done to implement the special mask

priority mode.

7

6

5

4

3

2

1

0

At reset, the ISRV registers are set to 0.

Note: If the ICU initialization does not follow a hardware reset, the ISRV

X

F

register should be cleared during initialization by writing zeroes into it.

e

Where: XXXX

FFFF

Don’t Care

A binary number from 0 to 15 indi-

cating the interrupt position as-

signed first priority.

Note: The byte above is written only to the FPRT(L) register. Any data writ-

ten to FPRT(H) is ignored.

At reset the FFFF field is set to 0, thus giving interrupt posi-

tion 0 first priority.

3.10 MCTL Ð MODE CONTROL REGISTER (R16)

The contents of the MCTL set the operating mode of the

NS32202 ICU. The MCTL bit map is shown below.

7

6

5

4

3

2

1

0

CFRZ COUTD COUTM CLKM FRZ unused NTAR T16N8

16

3.0 Architectural Description (Continued)

Note: The interrupt sensing mechanism on pins G0/IR0, . . . ,G3/IR6 is not

disabled when any of these pins is programmed as clock output.

Thus, to avoid spurious interrupts, the corresponding bits in register

IPS should also be set to zero.

CFRZ

Determines whether or not the NS32202 coun-

ter readings are frozen. When frozen, the

counters continue counting but the LCCV and

HCCV registers are not updated. Reading of

the true value of LCCV and HCCV is possible

only while they are frozen.

3.12 CIPTR Ð COUNTER INTERRUPT

POINTER REGISTER (R18)

The CIPTR register tracks the assignment of counter out-

puts to interrupt positions. A bit map of this register is shown

below.

l

e

CFRZ

0

1

LCCV and HCCV Not Frozen

LCCV and HCCV Frozen

COUTD

Determines whether the COUT/SCIN pin is an

input or an output. COUT/SCIN should be

used as an input only for testing purposes. In

this case an external sampling clock must be

provided otherwise hardware interrupts will not

be recognized.

7

6

5

4

3

2

1

0

H

L

e

Where: HHHH

A 4-bit binary number identifying the

interrupt position assigned to the H-

a

Counter (or the H L-counter if the

counters are concatenated).

l

e

COUTD

0

1

COUT/SCIN is Output

COUT/SCIN is Input

e

LLLL

A 4-bit binary number identifying the

interrupt position assigned to the L-

counter.

COUTM

CLKM

FRZ

When the COUT/SCIN pin is programmed as

e

an output (COUTD 0), this bit determines

whether the output signal is in pulsed form or in

square wave form.

Note: Assignment of a counter output to an interrupt position also requires

control bits to be set in the CICTL register. If counter output is

a

assigned to an interrupt position, external hardware interrupts at that

position are ignored.

l

e

COUTM

0

1

Square Wave Form

Pulsed Form

At reset, all bits in the CIPTR are set to 1. (This means both

counters are assigned to interrupt position 15.)

Used only in the 8-bit Bus Mode. This bit con-

trols the clock wave form on any of the pins

GO/IRO, . . . ,G3/IR6 programmed as counter

output.

3.13 PDAT Ð PORT DATA REGISTER (R19)

Used only in the 8-bit Bus Mode. This register is used to

input or output data through any of the pins G0/

IR0, . . . ,G7/IR14 programmed as I/O ports by the IPS reg-

ister. Any pin programmed as an output delivers the data

written into PDAT. The input pins ignore it. Reading PDAT

provides the logical value of all I/O pins, INPUT and OUT-

PUT.

l

e

CLKM

0

1

Square Wave Form

Pulsed Form

Freeze Bit. In order to allow a synchronous

reading of the interrupt pending registers

(IPND), their status may be frozen, causing the

ICU to ignore incoming requests. This is of spe-

cial importance if a polling method is used.

3.14 IPS Ð INTERRUPT/PORT SELECT REGISTER (R20)

Used only in the 8-bit Bus Mode. This register controls the

function of the pins G0/IR0, . . . ,G7/IR14. Each of these

pins is individually programmed as an I/O port, if the corre-

sponding bit of IPS is 0; as an interrupt source, if the corre-

sponding bit is 1. The assignment of the H-Counter output

to G0/IR0, . . . ,G3/IR6 by means of reg. OCASN overrides

the assignment to these pins as I/O ports or interrupt in-

puts.

l

e

FRZ

0

1

IPND Not Frozen

IPND Frozen

NTAR

Determines whether the ICU is in the AUTO-

ROTATE or FIXED Priority Mode. In AUTO-

ROTATE mode, the interrupt source at the

highest priority position, after being serviced, is

assigned automatically lowest priority. In this

mode, the interrupt in service always has high-

est priority and nesting of interrupts is therefore

inhibited.

At Reset, all the IPS bits are set to 1.

Note: Whenever

a bit in the IPS register is set to zero, to program the

corresponding pin as an I/O port, any pending interrupt on the corre-

sponding interrupt position will be cleared.

l

e

NTAR

0

1

Auto-Rotate Mode

Fixed Mode

3.15 PDIR Ð PORT DIRECTION REGISTER (R21)

T16N8

Controls the data bus mode of operation.

Used only in the 8-bit Bus Mode. This register determines

the direction of any of the pins G0/IR0, . . . ,G7/IR14 pro-

grammed as I/O ports by the IPS register. A logic 1 indi-

cates an input, while a logic 0 indicates an output.

l

e

T16N8

0

1

8-Bit Bus Mode

16-Bit Bus Mode

At reset, all MCTL bits except COUTD, are reset to 0.

COUTD is set to 1.

At Reset, all the PDIR bits are set to 1.

3.16 CCTL Ð COUNTER CONTROL REGISTER (R22)

3.11 OCASN Ð OUTPUT CLOCK

ASSIGNMENT REGISTER (R17)

The CCTL register controls the operating modes of the

counters. A bit map of CCTL is shown below.

Used only in the 8-bit Bus Mode. The four least significant

bits of this register control the output clock assignments on

pins G0/IR0, . . . ,G3/IR6. If any of these bits is set to 1, the

7

6

5

4

3

2

1

0

CCON CFNPS COUT1 COUT0 CRUNH CRUNL CDCRH CDCRL

a

clock generated by either the H-Counter or the H L-Coun-

ter will be output to the corresponding pin. The four most

significant bits of OCASN are not used. At Reset the four

least significant bits are set to 0.

CCON

Determines whether the counters are indepen-

dent or concatenated to form a single 32-bit

a

counter (H L-Counter). If a 32-bit counter is

selected, the bits corresponding to the H-

17

3.0 Architectural Description (Continued)

a

Counter will control the H L-Counter, while

control bits. In this case the CIEL bit should be set to zero to

avoid spurious interrupts from the L-Counter. A bit map of

the CICTL register is shown following.

the bits corresponding to the L-Counter are not

used.

l

e

7

6

5

4

3

2

1

0

CCON

0

1

Two 16-bit Counters

One 32-bit Counter

CERH CIRH CIEH WENH CERL CIRL CIEL WENL

CFNPS

Determines whether the external clock is

prescaled or not.

CERH

H-Counter Error Flag. This bit is set (1) when a

second interrupt request from the H-Counter

a

(or H L-Counter) occurs before the first re-

quest is acknowledged.

l

e

CFNPS

0

Clock Prescaled (divided by 4)

l

e

1

Clock Not Prescaled.

COUT1 &

COUT0

CIRH

H-Counter Interrupt Request. It is set (1) when

an interrupt is pending from the H-Counter (or

These bits are effective only when the COUT/

SCIN pin is programmed as an OUTPUT

(COUTD bit in reg. MCTL is 0). Their logic lev-

els are decoded to provide different outputs for

COUT/SCIN, as detailed in the table below:

a

the interrupt is acknowledged.

H

L-Counter). It is automatically reset when

CIEH

H-Counter Interrupt Enable. When it is set, the

a

H-Counter (or H L-Counter) interrupt is en-

abled.

COUT1 COUT0 COUT/SCIN Output Signal

WENH

CERL

H-Counter Control Write Enable. When WEHN

is set (1), bits CERH, CIRH, and CIEH can be

written.

0

1

0

1

0

1

Internal Sampling Oscillator

Zero Detect Of L-Counter

Zero Detect Of H-Counter

L-Counter Error Flag. This bit is set (1) when a

second interrupt request from the L-Counter

occurs before the first request is acknowl-

edged.

a

Zero Detect Of H L-Counter*

*If the H- and L-Counters are not concatenated and

COUT1/COUT0 are both 1, the COUT/SCIN pin is active

when either counter reaches zero.

CIRL

L-Counter Interrupt Request. It is set (1) when

an interrupt is pending from the L-Counter. It is

automatically reset when the interrupt is ac-

knowledged.

CRUNH

Determines the state of either the H-Counter or

a

the H L-Counter, depending upon the status

of CCON.

l

e

a

H-Counter or H L-Counter

CRUNH

Halted

0

1

CIEL

L-Counter Interrupt Enable. When it is set (1),

the L-Counter interrupt is enabled.

e

a

H-Counter or H L-Counter

CRUNH

Running

WENL

L-Counter Control Write Enable. When WENL

is set (1), bits CERL, CIRL, and CIEL can be

written.

e

0. This bit deter-

CRUNL

CDCRH

Effective only when CCON

Note: Setting the write enable bits (WENH or WENL) and writing any of the

other CICTL bits are concurrent operations. That is, the ICU will ig-

nore any attempt to alter CICTL bits if the proper write enable bit is

not set in the data byte.

mines whether the L-Counter is running or halt-

ed.

l

e

CRUNL

0

1

L-Counter Halted

L-counter Running

At reset, all CICTL bits are set to 0. However, if the counters

are running, the bits CIRL, CERL, CIRH and CERH may be

set again after the reset signal is removed.

e

Effective only when CRUNH 0 (Counter Halt-

ed). This bit is the single cycle decrement sig-

a

nal for either the H-Counter or the H L-Coun-

ter.

3.18 LCSV/HCSV Ð L-COUNTER STARTING VALUE/

H-COUNTER STARTING VALUE REGISTERS

(R24, R25, R26, AND R27)

l

e

CDCRH

0

No Effect

l

e

CDCRH

a

1

Decrement H-Counter or

The LCSV and HCSV registers store the start values for the

L-Counter and H-Counter, respectively. Each time a counter

reaches zero, the start value is automatically reloaded from

either LCSV or HCSV, one clock cycle after zero count is

reached. Loading LCSV or HCSV from the CPU must be

synchronized to avoid writing the registers while the reload-

ing of the counters is occurring. One method is to halt the

counters while the registers are loaded.

H

L-Counter

e

0 and CCON

CDCRL

Effective only when CRUNL

0. This bit is the single cycle decrement signal

for the L-Counter.

l

e

CDCRL

0

1

No Effect

Decrement L-Counter

Note: The bits CDCRL and CDCRH are set when a logic 1 is written into

them, but, they are automatically cleared after the end of the write

operation. This is needed to accomplish the decrement operation.

Therefore, these bits always contain 0 when read.

When the 16-bit counters are concatenated, the LCSV and

HCSV registers hold the 32-bit start count, with the least

significant byte in R24 and the most significant byte in R27.

Reset does not affect the CCTL bits.

3.19 LCCV/HCCV Ð L-COUNTER CURRENT VALUE/

H-COUNTER CURRENT VALUE REGISTERS

(R28, R29, R30, AND R31)

3.17 CICTL Ð COUNTER INTERRUPT

CONTROL REGISTER (R23)

The LCCV and HCCV registers hold the current value of the

counters. If the CFRZ bit in the MCTL register is reset (0),

these registers are updated on each clock cycle with the

current value of the counters. LCCV and HCCV can be read

only when the counter readings are frozen (CFRZ bit in the

The CICTL register controls the counter interrupts and rec-

ords counter interrupt status. Interrupts can be generated

from either of the 16-bit counters. When the counters are

concatenated, the interrupt control is through the H-Counter

18

3.0 Architectural Description (Continued)

TL/EE/5117–15

FIGURE 3–3. Recommended ICU’s Initialization Sequence

19

Status (ST1): Status signal from the CPU. When the Hard-

ware Vector Register is read, this signal differentiates an

3.0 Architectural

Description ^(Continued)

MCTL register is 1). They can be written only when the

counters are halted (CRUNL and/or CRUNH bits in the

CCTL register are 0). This last feature allows new initial

count values to be loaded immediately into the counters,

and can be used during initialization to avoid long initial

counts.

e

INTA cycle from an RETI cycle. If ST1 0 the ICU initiates

an INTA cycle. If ST1 1 an RETI cycle will result.

e

Interrupt Requests (IR1, IR3 . . . , IR15): These eight in-

puts are used for hardware interrupts. Each may be individu-

ally triggered in one of four modes: Rising Edge, Falling

Edge, Low Level, or High Level.

Counter Clock (CLK): External clock signal to drive the ICU

internal counters.

When the 16-bit counters are concatenated, the LCCV and

HCCV registers hold the 32-bit current value, with the least

significant byte in R28 and the most significant byte in R31.

4.1.3 Output Signals

Interrupt Output (INT): Active low. This signal indicates

that an interrupt is pending.

3.20 REGISTER INITIALIZATION

Figure 3–3 shows a recommended initialization procedure

for the ICU that sets up all the ICU registers for proper oper-

ation.

4.1.4 Input/Output Signals

Data Bus 0–7 (D0 through D7): Eight low-order data bus

lines used in both 8-bit and 16-bit bus modes.

General Purpose I/O Lines (G0/IR0, G1/IR2, . . . ,G7/

IR14): These pins are the high-order data bits when the ICU

is in the 16-bit bus mode. When the ICU is in the 8-bit bus

mode, each of these can be individually assigned one of the

following functions:

4.0 Device Specifications

4.1 NS32202 PIN DESCRIPTIONS

4.1.1 Power Supply

a

Power (V ): 5V DC Supply

Ground (GND): Power Supply Return

Additional Hardware Interrupt Input (IR0 through

IR14)

#

CC

General Purpose Data Input

General Purpose Data Output

Clock Output from H-Counter (Pins G0/IR0 through

G3/IR6 only)

#

4.1.2 Input Signals

#

Reset (RST): Active low. This signal initializes the ICU. (The

ICU initializes to the 8-bit bus mode.)

#

Chip Select (CS): Active low. This signal enables the ICU to

respond to address, data, and control signals from the CPU.

Addresses (A0 through A4): Address lines used to select

the ICU internal registers for read/write operations.

High Byte Enable (HBE): Active low. Enables data trans-

fers on the most-significant byte of the Data Bus. If the ICU

is in the 8-bit Bus Mode, this signal is not used and should

It should be noted that, for maximum flexibility in assigning

interrupt priorities, the interrupt positions corresponding to

pins G0/IR0, . . . ,G7/IR14 and IR1, . . . ,IR15 are inter-

leaved.

Counter or Oscillator Output/Sampling Clock Input

(COUT/SCIN): As an output, this pin provides either a clock

signal generated by the ICU internal oscillator, or a zero

detect signal from one or both of the ICU counters. As an

input, it is used for an external clock, to override the internal

oscillator used for interrupt sampling. This is done only for

testing purposes.

be connected to either GND or V

.

CC

Read (RD): Active low. Enables data to be read from the

ICU’s internal registers.

Write (WR): Active low. Enables data to be written into the

ICU’s internal registers.

20

4.0 Device Specifications (Continued)

4.2 ABSOLUTE MAXIMUM RATINGS

a

0 C to 70 C

Temperature Under Bias

Storage Temperature

All Input or Output Voltages with

Respect to GND

Note: Absolute maximum ratings indicate limits beyond

which permanent damage may occur. Continuous operation

at these limits is not intended; operation should be limited to

those conditions specified under Electrical Characteristics.

§

65 C to 150 C

§

b

a

§

b

a

0.5V to 7.0V

Power Dissipation

1.5 Watt

4.3 ELECTRICAL CHARACTERISTICS

e

e a

CC

e

g

T

A

0

§

to 70 C, V

§

5V

5%, GND

0V

Symbol

Parameter

Conditions

Min

2.0

2.4

Typ

Max

Units

V

Input Low Voltage

Input High Voltage

0.8

V

IL

IH

e

Output Low Voltage

Output High Voltage

Leakage Current

I

2 mA

0.45

OL

OH

OL

e b

400 mA

OH

s

V

I

0.4

V

IN

L

CC

b

20

mA

(Output and I/O Pins in TRI-STATE/Input mode)

e

I

Input Load Current

V

I

0 to V

CC

20

mA

I

in

e

Power Supply Current

0, T

0 C

§

300

mA

CC

out

Connection Diagram

TL/EE/5117–3

Top View

Order Number NS32202D-10

See NS Package Number D40C

FIGURE 4–1

21

4.0 Device Specifications (Continued)

4.4 SWITCHING CHARACTERISTICS

4.4.1 Definitions

Abbreviations:

L.E.Ðleading edge

T.E.Ðtrailing edge

R.E.Ðrising edge

F.E.Ðfalling edge

All the timing specifications given in this section refer to

0.8V or 2.0V on the input and output signals as illustrated in

Figure 1, unless specifically stated otherwise.

TL/EE/5117–16

FIGURE 4–2. Timing Specification Standard

4.4.1.1 Timing Tables

NS32202-10

Symbol

Figure

Description

Reference/Conditions

Units

Min

Max

READ CYCLE

t

4-3

Address Hold Time

Address Setup Time

CS Hold Time

After RD T.E.

10

35

15

30

5

ns

AhRDia

AsRDa

CShRDia

CSsRDa

DhRDia

RDaDv

RDw

Before RD L.E.

After RD T.E.

CS Setup Time

Data Hold Time

Data Valid

Before RD L.E.

After RD T.E.

50

After RD L.E.

150

RD Pulse Width

ST1 Setup Time

ST1 Hold Time

At 0.8V (Both Edges)

Before RD L.E.

After RD T.E.

160

35

SsRDa

ShRDia

b

30

WRITE CYCLE

t

4-4

Address Hold Time

Address Setup Time

CS Hold Time

After WR T.E.

10

ns

AhWRia

AsWRa

CShWRia

CSsWRa

DhWRia

DsWRia

WRiaPf

WRiaPv

WRw

Before WR L.E.

After WR T.E.

35

15

30

70

CS Setup Time

Before WR L.E.

After WR T.E.

Data Hold Time

Data Setup Time

Port Output Floating

Port Output Valid

WR Pulse Width

Before WR T.E.

After WR T.E. (To PDIR)

After WR T.E.

200

At 0.8V (Both Edges)

160

22

4.0 Device Specifications (Continued)

4.4.1.1 Timing Tables (Continued)

NS32202-10

Symbol

Figure

Description

Reference/Conditions

Units

Min

Max

OTHER TIMINGS

t

4-8

Internal Sampling Clock

Low Time

At 0.8V (Both Edges)

COUTI

50

ns

t

4-8

4-7

4-9

Internal Sampling Clock Period

External Sampling Clock High Time

External Sampling Clock Low Time

External Sampling Clock Period

400

100

800

ns

COUTp

SCINh

SCINI

SCINp

Ch

At 2.0V (Both Edges)

At 0.8V (Both Edges)

External Clock High Time

(Without Prescaler)

At 2.0V (Both Edges)

At 0.8V (Both Edges)

100

40

ns

t

4-9

External Clock High Time

(With Prescaler)

Chp

CI

External Clock Low Time

(Without Prescaler)

100

40

External Clock Low Time

(With Prescaler)

CIp

Cy

External Clock Period

(Without Prescaler)

400

100

External Clock Period

(With Prescaler)

Cyp

ns

t

4-9

Counter Output Transition Delay

After CLK F.E.

300

800

GCOUTI

COUTw

Counter Output Pulse

Width in Pulsed Form

At 0.8V (Both Edges)

50

t

4-5

Interrupt Request Delay

After Previous Interrupt

Acknowledge

ACKIR

IRId

500

ns

INT Output Delay

After Interrupt

Request Active

Interrupt Request Pulse

Width in Edge Trigger

At 0.8V (Both Edges)

IRw

50

ns

RST Pulse Width

At 0.8V (Both Edges)

400

RSTw

4.4.1.2 Timing Diagrams

TL/EE/5117–17

FIGURE 4–3. READ/INTA Cycle

23

4.0 Device Specifications (Continued)

TL/EE/5117–18

FIGURE 4–4. Write Cycle

TL/EE/5117–19

FIGURE 4–5. Interrupt Timing in Edge Triggering Mode

TL/EE/5117–20

FIGURE 4–6. Interrupt Timing in Level Triggering Mode

24

4.0 Device Specifications (Continued)

TL/EE/5117–21

Note: Interrupts are sampled on the rising edge of CLK.

FIGURE 4–7. External Interrupt-Sampling-Clock to be Provided at Pin COUT/SCIN When in Test Mode

TL/EE/5117–22

FIGURE 4–8. Internal Interrupt-Sampling-Clock Provided at Pin COUT/SCIN

TL/EE/5117–23

FIGURE 4–9. Relationship Between Clock Input at Pin CLK and Counter Output Signals at Pins COUT/SCIN or

G0/R0,...,G3/R6, in Both Pulsed Form and Square Waveform

25

Ý

Lit. 114298

Physical Dimensions inches (millimeters)

Hermetic Dual-In-Line Package (D)

Order Number NS32202D-10

NS Package Number D40C

Ordering Information

NS32202D-10

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

National Semiconductor

Corporation

National Semiconductor

Europe

National Semiconductor

Hong Kong Ltd.

National Semiconductor

Japan Ltd.

a

1111 West Bardin Road

Arlington, TX 76017

Tel: 1(800) 272-9959

Fax: 1(800) 737-7018

Fax:

(

49) 0-180-530 85 86

@

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Hong Kong

Tel: (852) 2737-1600

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a

Deutsch Tel:

English Tel:

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(

49) 0-180-530 85 85

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