NT256D64S8HA0G-75B [ETC]
184pin Two Bank Unbuffered DDR SDRAM MODULE; 184PIN两行无缓冲DDR SDRAM模块型号: | NT256D64S8HA0G-75B |
厂家: | ETC |
描述: | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
文件: | 总13页 (文件大小:185K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
184pin Two Bank Unbuffered DDR SDRAM MODULE Based on DDR266/200 16Mx8 SDRAM
Features
• 184-Pin Unbuffered 8-Byte Dual In-Line Memory Module
• 32Mx64 Double Data Rate (DDR) SDRAM DIMM
• Performance :
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
Also aligns QFC transitions with clock during Read cycles
• Address and control signals are fully synchronous to positive
clock edge
PC1600
- 8B
2
PC2100
• Programmable Operation:
Unit
Speed Sort
- 75B
- 7K
2
- DIMM
Latency: 2, 2.5
CAS
DIMM
Latency
2.5
133
7.5
CAS
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
f CK Clock Frequency
t CK Clock Cycle
100
10
133
7.5
266
MHz
ns
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 12/10/2 Addressing (row/column/bank)
• 15.6 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
f DQ DQ Burst Frequency
200
266
MHz
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
• Single Pulsed
interface
RAS
• SDRAMs have 4 internal banks for concurrent operation
• Module has two physical banks
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
• Differential clock inputs
• Data is read or written on both clock edges
Description
NT256D64S8HA0G is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a dual-bank high-speed memory array. The 32Mx64 module is a two-bank DIMM that uses sixteen 16Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 and / or CKE1
controls all devices on the DIMM.
Prior to any access operation, the device
latency and burst type/ length/operation type must be programmed into the DIMM by
CAS
address inputs A0-A11 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
Ordering Information
Part Number
Speed
143MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
133MHz (7.5ns @ CL= 2.5 )
100MHz (10ns @ CL = 2 )
125MHz (8ns @ CL = 2.5 )
100MHz (10ns @ CL = 2 )
Organization
32Mx64
Leads
Gold
Power
2.5V
NT256D64S8HA0G-7K
PC2100
PC2100
PC1600
NT256D64S8HA0G -75B
NT256D64S8HA0G -8B
Preliminary
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Pin Description
CK0, CK1, CK2
Differential Clock Inputs
DQ0-DQ63
Data input/output
,
,
CK0 CK1 CK2
CKE0, CKE1
RAS
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
DQS0-DQS7,
DQS9-DQS16
VDD
Bidirectional data strobes
Power (2.5V)
Supply voltage for DQs(2.5V)
Ground
CAS
WE
VDDQ
,
Chip Selects
VSS
S0 S1
A0-A9, A11
A10/AP
BA0, BA1
VREF
Address Inputs
NC
No Connect
Address Input/Autoprecharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
VDD Identification flag.
SCL
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply(2.5V)
SDA
SA0-2
VDDID
VDDSPD
Pinout
Pin
1
Front
VREF
DQ0
VSS
Pin
93
Back
VSS
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Front
A5
Pin
Back
VSS
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
2
94
DQ4
DQ5
VDDQ
DQS9
DQ6
DQ7
VSS
DQ24
VSS
DQ25
DQS3
A4
A6
DQ45
VDDQ
S0
3
95
DQ28
DQ29
VDDQ
DQS12
A3
DQ41
CAS
VSS
4
DQ1
DQS0
DQ2
VDD
96
5
97
S1
6
98
DQS5
DQ42
DQ43
VDD
DQS14
VSS
7
99
VDD
DQ26
DQ27
A2
8
DQ3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQ30
VSS
DQ46
DQ47
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
NC
DQ31
NC
NC
VSS
NC
VSS
A1
DQ48
DQ49
VSS
VDDQ
DQ52
DQ53
NC
DQ8
DQ9
DQS1
VDDQ
CK1
VDDQ
DQ12
DQ13
DQS10
VDD
NC
NC
VDDQ
CK0
CK0
VSS
NC
CK2
VDD
NC
CK2
VDD
VDDQ
DQS6
DQ50
DQ51
VSS
DQS15
DQ54
DQ55
VDDQ
NC
DQ14
DQ15
CKE1
VDDQ
NC
A0
NC
CK1
VSS
NC
A10
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
VSS
NC
NC
VDDQ
NC
BA1
VDDID
DQ56
DQ57
VDD
DQ60
DQ61
VSS
DQ20
NC
KEY
KEY
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
VSS
DQS16
DQ62
DQ63
VDDQ
SA0
DQ21
A11
DQS7
DQ58
DQ59
VSS
A9
DQS11
VDD
DQS13
DQ38
DQ39
VSS
DQ18
A7
DQ22
A8
BA0
NC
SA1
VDDQ
DQ19
DQ35
DQ40
SDA
SA2
DQ23
DQ44
SCL
VDDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
Preliminary
2
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Input/Output Functional Description
Function
Symbol
Type
Polarity
The positive line of the differential pair of system clock inputs which drives the input to the
on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the rising
edge of their associated clocks.
Positive
Edge
CK0 , CK1, CK2
(SSTL)
Negative The negative line of the differential pair of system clock inputs which drives the input to the
Edge on-DIMM PLL.
,
,
(SSTL)
(SSTL)
CK0 CK1 CK2
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
Active
CKE0, CKE1
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
High
mode.
Enables the associated SDRAM command decoder when low and disables the command
Active
(SSTL)
decoder when high. When the command decoder is disabled, new commands are ignored
,
S0 S1
Low
but previous operations continue.
When sampled at the positive rising edge of the clock,
operation to be executed by the SDRAM.
,
, WE define the
RAS CAS
Active
Low
(SSTL)
Supply
Supply
(SSTL)
,
, WE
RAS CAS
VREF
VDDQ
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
BA0, BA1
-
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
A0 - A9
A10/AP
A11
(SSTL)
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
DQ0 - DQ63,
(SSTL)
-
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
DQS0 - DQS7
DQS9 - DQS16
Active
High
(SSTL)
Supply
VDD , VSS
SA0 – SA2
Power and ground for the DDR SDRAM input buffers and core logic
Address inputs. Connected to either V
DD
or V
on the system board to configure the
SS
-
-
-
Serial Presence Detect EEPROM address.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pullup.
SDA
SCL
VDDSPD
Supply
Serial EEPROM positive power supply.
Preliminary
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Functional Block Diagram ( 2 Bank, 16Mx8 DDR SDRAMs )
S1
S0
DQS0
DQS4
DQS9
DQS13
DM
DM
DM
DM
CS DQS
CS
DQS
DQS
DQS
DQS
CS DQS
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
D0
D8
D4
I/O 7 D12
I/O 2
I/O 3
I/O 4
I/O 5
DQS1
DQS5
DQS10
DQS14
DM
DQS
DQS
DQS
DM
DM
DQS
DM
CS
CS
CS
CS
DQS
DQS
DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D9
D5
I/O 7 D13
I/O 2
I/O 3
I/O 4
I/O 5
DQS2
DQS6
DQS11
DQS15
DM CS
I/O 7
DM CS
I/O 7
DQS
DM
DM
CS
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 6
I/O 0
I/O 1
I/O 6
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7 D10
I/O 2
I/O 7 D14
I/O 2
D2
D6
I/O 3
I/O 3
I/O 4
I/O 4
I/O 5
I/O 5
DQS3
DQS7
DQS12
DQS16
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DM
CS
CS
CS
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 6
I/O 0
I/O 1
I/O 6
D3
I/O 7 D11
I/O 2
D7
I/O 7 D15
I/O 2
I/O 3
I/O 3
I/O 4
I/O 4
I/O 5
I/O 5
BA0-BA1
A0-A11
RAS
BA0 - BA1 : SDRAMs D0 -D15
A0 - A11 : SDRAMs D0 -D15
RAS : SDRAMs D0 -D15
CAS : SDRAMs D0 -D15
CKE0 : SDRAMs D0 -D7
WE : SDRAMs D8 -D15
WE : SDRAMs D0 -D15
VDDQ
VDD
D0 - D15
CK0
D0 - D15
D0 - D15
D0 - D15
120 ohm
120 ohm
120 ohm
SDRAM x 4
SDRAM x 6
SDRAM x 6
VREF
VSS
CK0
CK1
CAS
VDDID
Strap: see Note 4
CKE0
CKE1
WE
CK1
CK2
Serial PD
A1
SCL
WP
SDA
CK2
A0
SA0
A2
Notes :
1. DQ-to-I/O wring may be changed within a byte.
SA1 SA2
2. DQ/DQS/DM/CKE/S relationships are maintained as shown.
3. DQ/DQS/DM/DQS resistors are 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD is not equal to VDDQ.
Preliminary
4
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Absolute Maximum Ratings
Symbol
, V
Parameter
Voltage on I/O pins relative to Vss
Rating
-0.5 to VDDQ+0.5
-0.5 to +3.6
-0.5 to +3.6
-0.5 to +3.6
0 to+70
Units
V
V
IN OUT
V
IN
Voltage on Input relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Power Dissipation
V
V
DD
V
V
DDQ
V
T
°C
°C
W
A
T
-55 to +150
16
STG
P
D
I
Short Circuit Output Current
50
mA
OUT
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Symbol
CI1
Max.
24
Units
pF
Notes
Parameter
, CK1, , CK2,
CK1
1
1
Input Capacitance: CK0,
CK0
CK2
CI2
60
pF
Input Capacitance: A0-A11, BA0, BA1, WE ,
,
RAS CAS
CI3
30
pF
1
Input Capacitance: CKE0, CKE1,
,
S0 S1
CIO1
14
pF
1,2
Input/Output Capacitance DQ0-63; DQS0-7, 9-16
1. VDDQ = VDD = 2.5V ± 0.2V, f = 100 MHz, T A = 25 °C, V OUT (DC) = VDDQ/2 , VOUT (Peak to Peak) = 0.2V.
2. DQS inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at
the board level.
Preliminary
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
DC Electrical Characteristics and Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
VDD
Parameter
Min
2.3
2.3
0
Max
2.7
2.7
0
Units
V
Notes
Supply Voltage
1
1
VDDQ
I/O Supply Voltage
V
VSS , VSSQ
VREF
Supply Voltage, I/O Supply Voltage
/O Reference Voltage
V
0.49 x VDDQ 0.51 x VDDQ
V
1,2
1,3
1
VTT
I/O Termination Voltage (System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
VREF – 0.04
VREF + 0.15
-0.3
VREF + 0.04
VDDQ + 0.3
VREF- 0.15
VDDQ + 0.3
V DDQ + 0.6
V
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
V
V
1
Input Voltage Level, CK and
Inputs
-0.3
V
1
CK
Input Differential Voltage, CK and
Input Leakage Current
Inputs
0.30
V
1,4
CK
II
-5
5
µA
1
Any input 0V £ VIN £ VDD; (All other pins not under test = 0V)
Output Leakage Current
IOZ
IOH
IOL
-5
5
-
µA
mA
mA
1
1
1
(DQs are disabled; 0V £ Vout £ VDDQ
Output High Current
-16.8
16.8
(VOUT = VDDQ -0.373V, min VREF , min VTT )
Output Low Current
-
(VOUT = 0.373, max VREF , max VTT )
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF ,
and must track variations in the DC level of VREF .
4. VID is the magnitude of the difference between the input level on CK and the input level on
.
CK
Preliminary
6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS .
2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or
to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC) unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the
signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.
AC Output Load Circuits
V
TT
50 ohms
Output
Timing Reference Point
VOUT
30 pF
AC Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Parameter/Condition
Input High (Logic 1) Voltage.
Min
VREF + 0.31
-
Max
-
Unit
V
Notes
1, 2
Input Low (Logic 0) Voltage.
VREF -?0.31
VDDQ + 0.6
(0.5*VDDQ ) +?0.2
V
1, 2
Input Differential Voltage, CK and
Inputs
0.62
V
1, 2, 3
1, 2, 4
CK
Input Differential Pair Cross Point Voltage, CK and
Inputs
(0.5*VDDQ ) - 0.2
V
CK
1. Input skew rate = 1V/ ns
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same.
.
Preliminary
7
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Operating, Standby, and Refresh Currents
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
I DD0
Parameter/Condition
PC1600
1000
PC2100
1160
Unit
mA
Notes
1,2
Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;
tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current : one bank; active / read / precharge; Burst = 2;
tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;
address and control inputs changing once per clock cycle
Precharge Power-Down Standby Current :
1120
1360
mA
1,2
I DD1
240
480
240
240
560
240
mA
mA
mA
1,2
1,2
1,2
I DD2P
I DD2N
I DD3P
all banks idle; power-down mode; CKE £ VIL (MAX) ; tCK = tCK (MIN)
Idle Standby Current : CS ³ VIH (MIN) ; all banks idle; CKE >= VIH(MIN) ;
tCK = tCK (MIN) ; address and control inputs changing once per clock cycle
Active Power-Down Standby Current : one bank active;
power-down mode; CKE £ VIL (MAX) ; tCK = tCK (MIN)
Active Standby Current : one bank; active / precharge; CS ³ VIH (MIN) ;
CKE ³ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS
inputs changing twice per clock cycle;
800
1640
1320
960
1800
1680
mA
mA
mA
1,2
1,2
1,2
I DD3N
I DD4R
I DD4W
address and control inputs changing once per clock cycle
Operating Current : one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
tCK = tCK (MIN) ; IOUT = 0mA
Operating Current : one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
tCK = tCK (MIN)
t RC = t RFC (MIN)
Auto-Refresh Current :
1840
252
32
2400
252
32
mA
mA
mA
1,2
I DD5
I DD6
t RC = 15.625 µs
1,2,4
1,2,3
Self-Refresh Current : CKE £ ?0.2V
1. I DD specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ ns .
3. Enables on-chip refresh and address counters.
4. Current at 15.625 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 15.625 µs.
Preliminary
8
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
-7K
-75B
-8B
Symbol
Parameter
Unit
Notes
Min.
-0.75
-0.75
0.45
0.45
7
Max.
+0.75
+0.75
0.55
0.55
12
Min.
-0.75
-0.75
0.45
0.45
7.5
Max.
+0.75
+0.75
0.55
0.55
12
Min.
-0.8
-0.8
0.45
0.45
8
Max.
+0.8
+0.8
0.55
0.55
12
tAC
tDQSCK
tCH
DQ output access time from CK/
ns
ns
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
CK
DQS output access time from CK/
CK high-level width
CK
tCK
tCK
ns
tCL
CK low-level width
tCK
CL=2.5
CL=2
Clock cycle time
tCK
7.5
12
10
12
10
12
ns
1,2,3,4
,15,16
tDH
DQ and DM input hold time
0.5
0.5
0.6
ns
1,2,3,4
,15,16
tDS
tDIPW
tHZ
DQ and DM input setup time
0.5
1.75
-0.75
0.5
0.6
2
ns
ns
ns
DQ and DM input pulse width (each input)
Data-out high-impedance time from
1.75
-0.75
1,2,3,4
1, 2, 3,
4, 5
+0.75
+0.75
+0.75
+0.75
-0.8
+0.8
+0.8
CK/
CK
Data-out low-impedance time from
CK/
1, 2, 3,
4, 5
tLZ
-0.75
-0.75
-0.8
ns
CK
DQS-DQ skew (DQS & associated DQ
signals)
tDQSQ
0.5
0.5
0.5
0.5
0.6
0.6
ns
ns
1,2,3,4
1,2,3,4
tDQSQA
DQS-DQ skew (DQS & all DQ signals)
Minimum half clk period for any given
cycle; defined by clk high(tCH )
or clk low (tCL ) time
tCH
or
tCH
or
tCH
or
tHP
tCK
1,2,3,4
tCL
tCL
tHP -
tCL
tHP -
0.75ns
tHP -
1.0ns
tQH
tDQSS
tDQSL,H
tDSS
Data output hold time from DQS
tCK
tCK
tCK
tCK
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
0.75ns
Write command to 1st DQS latching
transition
0.75
0.35
0.2
1.25
0.75
1.25
0.75
0.35
0.2
1.25
DQS input low (high) pulse width
(write cycle)
0.35
0.2
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
tDSH
tMRD
0.2
14
0.2
15
0.2
16
tCK
ns
1,2,3,4
1,2,3,4
Mode register set command cycle time
1, 2, 3,
4, 7
tWPRES
Write preamble setup time
0
0
0
ns
1, 2, 3,
4, 6
tWPST
tWPRE
Write postamble
Write preamble
0.40
0.25
0.60
0.40
0.25
0.60
0.40
0.25
0.60
tCK
tCK
1,2,3,4
2, 3, 4,
9, 11,
12
Address and control input hold time
(fast slew rate)
tIH
tIS
tIH
0.9
0.9
1.0
1.1
1.1
1.1
1.1
1.1
1.1
ns
ns
ns
2, 3, 4,
9, 11,
12
Address and control input setup time
(fast slew rate)
2, 3, 4,
10, 11,
12, 14
Address and control input hold time
(slow slew rate)
Preliminary
9
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)
-7K
-75B
-8B
Symbol
Parameter
Unit
Notes
Min.
1.0
Max.
Min.
1.0
Max.
Min.
1.1
Max.
2, 3, 4,
10, 11,
Address and control input setup time
(slow slewrate)
tIS
ns
ns
12, 14
2, 3, 4,
12
tIPW
Input pulse width
2.2
2.2
-
1,2,3,4
1,2,3,4
1,2,3,4
tRPRE
tRPST
tRAS
Read preamble
0.9
0.40
45
1.1
0.60
0.9
0.40
45
1.1
0.9
0.40
50
1.1
0.60
tCK
tCK
ns
Read postamble
0.60
Active to Precharge command
Active to Active/Auto-refresh
command period
120,000
120,000
120,000
1,2,3,4
tRC
65
65
70
ns
ns
Auto-refresh to Active/Auto-refresh
command period
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
tRFC
tRCD
tRAP
tRP
75
20
20
20
15
15
75
20
20
20
15
15
80
20
20
20
15
15
Active to Read or Write delay
Active to Read Command with
Autoprecharge
ns
ns
ns
ns
ns
Precharge command period
Active bank A to Active bank B
command
tRRD
tWR
Write recovery time
(tWR/
tCK )
+
(tWR/
tCK )
+
(tWR/
tCK )
+
1, 2, 3,
4, 13
Auto precharge write recovery +
precharge time
tDAL
tCK
(tRP/
tCK )
1
(tRP /
tCK )
1
(tRP /
tCK )
1
tWTR
Internal write to read command delay
Exit self-refresh to non-read
command
tCK
ns
1,2,3,4
1,2,3,4
tXSNR
75
75
80
tXSRD
tREFI
Exit self-refresh to read command
200
200
200
tCK
µs
1,2,3,4
1, 2, 3,
Average Periodic Refresh Interval
15.6
15.6
15.6
4, 8
Preliminary
10
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/
input reference level (for timing reference to CK/
) is the point at which CK and
cross: the input reference level for
CK
CK
CK
signals other than CK/
, is VREF.
CK
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS .
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC).
11. CK/
slew rates are >= 1.0 V/ns.
CK
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system
clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate
0.5 V/ns
D?elta ( tIS )
Delta ( tIH )
Unit
ps
Note
1,2
0
0
0
0
0.4 V/ns
+50
+100
ps
1,2
0.3 V/ns
ps
1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly
for rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate
0.5 V/ns
Delta ( tDS )
Delta ( tDH )
Unit
ps
Note
1,2
0
0
0.4 V/ns
+75
+75
ps
1,2
0.3 V/ns
+150
+150
ps
1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for
rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.
Delta Rise and Fall Rate
0.0 ns/V
Delta ( tDS )
Delta ( tDH )
Unit
ps
Note
0
0
1,2,3,4
1,2,3,4
1,2,3,4
0.25 ns/V
+50
+100
+50
+100
ps
0.5 ns/V
ps
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly
for rising transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each
device.
Preliminary
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect
32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD
Serial PD Data Entry
SPD Entry Value
Byte
Description
(Hexadecimal)
Note
-7K
-75B
-8B
-7K
-75
80
08
07
0C
0A
02
40
00
04
75
75
00
80
08
00
-8B
0
1
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
128
256
2
SDRAM DDR
3
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
12
10
4
5
2
6.
7
Data Width of Assembly
X64
Data Width of Assembly (cont’)
X64
8
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=2.5
SDRAM Device Access Time from Clock at CL=2.5
DIMM Configuration Type
SSTL 2.5V
7.5ns
9
7ns
0.75ns
8ns
70
75
80
80
10
11
12
13
14
0.75ns
Non-Parity
15.6µs / SR
X8
0.8ns
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Device Width
SDRAM Device Attributes :
N/A
15
1 Clock
01
Minimum Clock Delay, Random Column Access
SDRAM Device Attributes: Burst Length Supported
SDRAM Device Attributes: Number of Device Banks
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2,4,8
0E
04
0C
01
02
20
00
A0
75
00
00
50
3C
50
2D
20
90
90
50
50
00
00
9D
4
2, 2.5
0
SDRAM Device Attributes:
SDRAM Device Attributes:
Latency
2, 2.5
2, 2.5
0C
0C
CAS
Latency
CS
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
1
Differential Clock
SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
+/-0.2V Voltage Tolerance
7.5ns
10ns
10ns
75
75
A0
80
Maximum Data Access Time from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at CL=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active delay (tRRD)
Minimum RAS to CAS delay (tRCD)
Minimum RAS Pulse Width (tRAS)
± 0.75ns ± 0.75ns ± 0.8ns
N/A
N/A
20ns
15ns
20ns
45ns
20ns
15ns
20ns
15ns
20ns
50ns
50
3C
50
2D
50
3C
50
32
20ns
45ns
Module Bank Density
128MB
0.9ns
0.9ns
0.5ns
0.5ns
Undefined
0
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
0.9ns
0.9ns
0.5ns
0.5ns
1.1ns
1.1ns
0.6ns
0.6ns
90
90
50
50
B0
B0
60
60
36-61 Reserved
62
63
SPD Revision
Checksum Data
0
0
00
00
23
6D
64-71 Manufacturer’s JEDED ID Code
72 Module Manufacturing Location
0B
7F7F7F0B00000000
00
N/A
N/A
N/A
73-90 Module Part number
N/A
N/A
00
00
00
00
91-92 Module Revision Code
93-94 Module Manufacturing Data
Year / Week Code
Serial Number
Undefined
yy/ww
00
1,2
95-98 Module Serial Number
99-255 Reserved
00
1. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
2. ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
Preliminary
12
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Package Dimensions
FRONT
133.35
5.25
128.95
5.077
q 2.50
0.098
Detail A
Detail B
Side
BACK
3.99
0.157 max.
1.27+/- 0.10
Detail A
Detail B
0.050 +/- 0.004
1.00 Width
0.039
6.35
1.27 Pitch
0.05
0.250
1.80
0.071
Note : All dimensions are typical unless otherwise stated.
Millimeters
Unit :
Inches
Preliminary
13
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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