NT56V6620C0T-75B [ETC]
x16 SDRAM ; X16 SDRAM\n
| 型号： | NT56V6620C0T-75B |
| 厂家： | 
ETC |
| 描述： | x16 SDRAM
|
| 文件： | 总66页 (文件大小：1687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
NT56V6610C0T (8Mx8)
NT56V6620C0T (4Mx16)
64Mb Synchronous DRAM
Data Sheet
REV 1.1 June, 2000
1
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Revision Log
Rev Date
Sep / 1999
June / 2000
Version
1.0
Content of Modification
1 st Revision
1.1
Added speed grade –75B (PC133@CL3 & PC100@CL2) to
following items as :
1. Product Family
2. DC currents
3. AC Timing Parameters
REV 1.1 June, 2000
2
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Contents
Revision Log ................................................................................................................................................................02
Table of Contents.........................................................................................................................................................03
Description...................................................................................................................................................................05
Features........................................................................................................................................................................06
Product Family ............................................................................................................................................................07
Pin Assignment............................................................................................................................................................07
Pin Description.............................................................................................................................................................08
Functional Block Diagram ...........................................................................................................................................09
Ordering Information...................................................................................................................................................10
DC Characteristics.......................................................................................................................................................11
.......................................................................................................................................11
Absolute Maximum Ratings
.....................................................................................................................11
Recommended DC Operating Conditions
..........................................................................................................................................................11
Capacitance
.....................................................................................................................................11
DC Electrical Characteristics
............................................................................................................................................12
DC Output Load Circuit
...................................................................................................................13
Operating, Standby, and Refresh Currents
AC Characteristics.......................................................................................................................................................14
...........................................................................................................................................14
AC Output Load Circuits
AC Timing Parameters.................................................................................................................................................15
............................................................................................................................15
Clock and Clock Enable Parameters
...............................................................................................................................................15
Common Parameters
..........................................................................................................................................15
Mode Register Set Cycle
...........................................................................................................................................................16
Read Cycle
........................................................................................................................................................16
Refresh Cycle
...........................................................................................................................................................16
Write Cycle
....................................................................................................................................16
Clock Frequency and Latency
Command Truth Table.................................................................................................................................................18
DEVICE OPERATIONS .................................................................................................................................................24
........................................................................................................................................24
Power On and Initialization
................................................................................................................................24
Programming the Mode Register
..........................................................................................................................................24
Mode Register Definition
..............................................................................................................................................25
Burst Mode Operation
......................................................................................................................................25
Burst Length and Sequence
..........................................................................................................................................26
Bank Activate Command
...........................................................................................................................................................26
Bank Select
..................................................................................................................................27
Read and Write Access Modes
.............................................................................................................................................28
Burst Read Command
.......................................................................................................................................29
......................................................................................................................................30
Read Interrupted by a Read
Read Interrupted by a Write
.............................................................................................................................................30
Burst Write Command
......................................................................................................................................31
......................................................................................................................................31
Write Interrupted by a Write
Write Interrupted by a Read
..............................................................................................................................................32
Burst Stop Command
........................................................................................................................................33
Auto-Precharge Operation
...............................................................................................................................................37
Precharge Command
...............................................................................................................37
Bank Selection for Precharge by Address Bits
.............................................................................................................................................39
Precharge Termination
....................................................................................................................................40
Automatic Refresh Command
............................................................................................................................................40
Self Refresh Command
..................................................................................................................................................41
Power Down Mode
............................................................................................................................................................41
Data Mask
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
...........................................................................................................................................41
No Operation Command
.................................................................................................................................................41
...............................................................................................................................................42
Deselect Command
Clock Suspend Mode
Timing Diagrams .........................................................................................................................................................43
................................................................................................................................43
AC Parameters for Write Timing
.......................................................................................................................44
.......................................................................................................................45
.......................................................................................................................46
.......................................................................................................................47
AC Parameters for Read Timing (3/3/3)
AC Parameters for Read Timing (2/2/2)
AC Parameters for Read Timing (3/2/2)
AC Parameters for Read Timing (3/3/3)
..................................................................................................................................................48
Mode Register Set
...............................................................................................................49
..................................................................................................................50
.................................................................................................................51
Power On Sequence and Auto Refresh (CBR)
Clock Suspension, DQM during Burst Read
Clock Suspension, DQM during Burst Write
........................................................................................................................52
Power Down Mode and Clock Suspend
................................................................................................................................................54
Auto Refresh (CBR)
.....................................................................................................................................54
Self Refresh (Entry and Exit)
..................................................................................................55
Random Row Read (Interleaving Banks) with Precharge
Random Row Read (Interleaving Banks) with Auto Precharge
Random Row Write (Interleaving Banks) with Auto Precharge
...........................................................................................56
...........................................................................................57
..................................................................................................58
Random Row Write (Interleaving Banks) with Precharge
...................................................................................................................................................59
Read-Write Cycle
..................................................................................................................................60
...............................................................................................................................61
................................................................................................................................62
Interleaved Column Read Cycle
Auto Precharge after Read Burst
Auto Precharge after Write Burst
........................................................................................................................63
Burst Read and Single Write Operation
Full Page Burst Read and Single Write Operation
/CS Function (Only /CS signal needs to be asserted at minimum rate)
...........................................................................................................64
.................................................................................65
Package Dimension .....................................................................................................................................................66
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Description
The NT56V6610C0T and NT56V6620C0T are four-bank Synchronous DRAMs organized as 2Mbit x 8 I/O x 4 Bank and 1Mbitx16I/Ox4Bank,
respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture
that synchronizes the output data to a system clock. The chip is fabricated with NANYA advanced 64Mbit single transistor CMOS DRAM
process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of
the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock.
/RAS, /CAS, /WE, and /CS are pulsed signals which are examined at the positive edge of each externally applied clock (CLK). Internal chip
operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A
fourteen bit address bus accepts address data in the conventional /RAS /CAS multiplexing style. Twelve row addresses (A0-A11) and two
bank select addresses (A12, A13) are strobed with /RAS. Ten column addresses (A0-A9) plus bank select addresses and A10 are strobed
with /CAS. Column address A9 is dropped on the x8 device and column addresses A8 and A9 are dropped on the x16 device. Access to the
lower or upper DRAM in a stacked device is controlled by /CS0 and /CS1, respectively.
Prior to any access operation, the /CAS latency, burst length, and burst sequence must be programmed into the device by address inputs
A0-A9 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write
through cache operation.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, /CAS latency, and speed
grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto
Refresh (CBR), Self Refresh, and Low Power operation are supported.
Feature
·
·
·
·
·
·
JEDEC standard 3.3V± 0.3V Power Supply
LVTTL compatible inputs and outputs
Four Banks controlled by Bank Selects(A12/A13)
Single Pulsed /RAS Interface
Fully Synchronous to Positive Clock Edge
MRS cycle with address key programmability for :
- CAS Latency ( 2, 3 )
- Burst Length ( 1, 2, 4, 8 & Full-page )
- Burst Type ( Sequential or Interleave )
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard Power operation
·
·
·
·
·
·
·
·
·
·
4096 refresh cycles/64ms
Random Column Address every CLK (1-N Rule)
Package:54-pin 400 mil TSOP-Type II
REV 1.1 June, 2000
5
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Product Family
Speed
( MHz@CL-tRP-tRCD)
Part NO.
Organization
Interface
Package
NT56V6610C0T-75B
NT56V6610C0T-75
NT56V6610C0T-8B
NT56V6610C0T-8A
NT56V6620C0T-7
NT56V6620C0T-75B
NT56V6620C0T-75
NT56V6620C0T-8B
NT56V6620C0T-8A
133 MHz @ 3-3-3
100 MHz @ 2-2-2
133 MHz @ 3-3-3
125 MHz @ 3-3-3
125 MHz @ 3-3-3
143 MHz @ 3-3-3
133 MHz @ 3-3-3
133 MHz @ 3-3-3
125 MHz @ 3-3-3
125 MHz @ 3-3-3
-
8M x 8
100MHZ @ 2-2-2
100MHz @ 3-2-2
-
54pin
LVTTL
TSOP II
100 MHz @ 2-2-2
-
4M x 16
100MHZ @ 2-2-2
100MHz @ 3-2-2
REV 1.1 June, 2000
6
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Pin Assignment ( Top View )
4M x 16
8M x 8
¡´
1
VDD
VDD
DQ0
VDDQ
NC
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ7
VssQ
NC
Vss
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
2
DQ15
VssQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
3
4
DQ1
VSSQ
NC
5
DQ6
VDDQ
NC
6
7
DQ2
VDDQ
NC
8
DQ5
VSSQ
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ3
VSSQ
NC
DQ4
VDDQ
NC
VDD
NC
VSS
NC
LDQM
WE
NC
WE
DQM
CLK
CKE
NC
UDQM
CLK
CKE
NC
CAS
RAS
CS
CAS
RAS
CS
A13/BS0 A13/BS0
A12/BS1 A12/BS1
A11
A9
A11
A9
A10/AP
A0
A10/AP
A0
A8
A8
A7
A7
A1
A1
A6
A6
A2
A2
A5
A5
A3
A3
A4
A4
VDD
VDD
VSS
VSS
54-pin Plastic TSOP-II 400 mil
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Pin Description
CLK
Clock Input
Clock Enable
DQ0-DQ15
Data Input/Output
Data Mask
CKE
DQM, LDQM, UDQM
/CS (/CS0, /CS1 )
/RAS
Chip Select
VDD
VSS
VDDQ
VSSQ
NC
Power (+3.3V)
Ground
Row Address Strobe
Column Address Strobe
Write Enable
/CAS
Power for DQs (+3.3V)
Ground for DQs
No Connection
--
/WE
BS1, BS0 (A12, A13)
A0-A11
Bank Select
Address Inputs
--
Input / Output Functional Description
Symbol
Type
Polarity
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of
the clock.
CLK
Input
Positive Edge
Activates the CLK signal when high and deactivates the CLK signal when low. By
deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or
the Self Refresh mode.
CKE
Input
Input
Active High
Active Low
/CS enables the command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
/CS
When sampled at the positive rising edge of the clock, /CAS, /RAS, and /WE define
the operation to be executed by the SDRAM.
/RAS, /CAS /WE
Input
Input
Active Low
--
BS1, BS0
(A12, A13)
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-
RA11) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-
CA9) when sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write
cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to
be precharged. If A10 is low, autoprecharge is disabled.
A0 - A11
Input
--
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to
control which bank(s) to precharge. If A10 is high, all banks will be precharged
regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define
which bank to precharge.
Input-
DQ0-DQ15
--
Data Input/Output pins operate in the same manner as on conventional DRAMs
Output
The Data Input/Output mask places the DQ buffers in a high impedance state when
sampled high. In x16 products, LDQM and UDQM control the lower and upper byte
I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and
controls the output buffers like an output enable. DQM low turns the output buffers
on and DQM high turns them off. In Write mode, DQM has a latency of zero and
operates as a word mask by allowing input data to be written if it is low but blocks
the write operation if DQM is high.
DQM
LDQM
UDQM
Input
Active High
VDD, VSS
Supply
Supply
--
--
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
VDDQ, VSSQ
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Functional Block Diagram
CKE
Buffer
CKE
CLK
Column Decoder
Column Decoder
CLK
Buffer
Cell Array
Cell Array
Memory Bank 0
Memory Bank 1
Sense Amplifiers
Sense Amplifiers
A0
A1
A2
A3
DQ0
A4
A5
A6
A7
A8
A9
A11
A12
A13
A10
DQX
DQM
Column Decoder
Column Decoder
Cell Array
Cell Array
Memory Bank 2
Memory Bank 3
CS
RAS
CAS
WE
Sense Amplifiers
Sense Amplifiers
Cell Array , per bank , for 2Mb x 8 DQ : 4096 Row x 512 Col x 8 DQ (DQ0-DQ7 ).
Cell Array , per bank , for 1Mb x 16 DQ : 4096 Row x 256 Col x 16 DQ (DQ0-DQ15).
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Part Number Guide
NT 56
V
6
6
10
C
0
T - XX
Speed*(10)
Package*(9)
NANYA Memory*(1)
Device*(2)
Interface*(8)
Voltage*(3)
Revision*(7)
Density*(4)
Configration*(6)
Refresh Time*(5)
(1) NANYA Memory
(6) Configuration
10 - - - - - - - - 4 bank, x 8
20 - - - - - - - - 4 bank, x 16
(2) Device
56 - - - - - - - - SDRAM
(7) Revision
A - - - - - - - - 1st version
B - - - - - - - - 2nd version
C - - - - - - - - 3rd version
D - - - - - - - - 4th version
(3) Voltage
V - - - - - - - - 3.3V
(8) Interface
0 - - - - - - - - LVTTL
1 - - - - - - - - SSTL
(4) Density
1 - - - - - - - - 16M
(9) Package
T - - - - - - - -TSOP II
F - - - - - - - -TQFP
Q - - - - - - - -QFP
6 - - - - - - - - 64M
2 - - - - - - - - 128M
(5) Refresh Time
(10) Speed
7 - - - - - - - - 2K/32ms
6 - - - - - - - - 4K/64ms
7 - - - - - - - -143MHz
75 - - - - - - -133MHz
8 - - - - - - - -125MHz
10 - - - - - - -100MHz
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
DC Characteristics
Absolute Maximum Ratings
Symbol
Parameter
Rating
-0.3 to +4.6
-0.3 to +4.6
-0.3 to VDD+0.3
-0.3 to VDD+0.3
0 to +70
Units
V
Notes
VDD
Power Supply Voltage
1
1
1
1
1
1
1
1
VDDQ
VIN
Power Supply Voltage for Output
Input Voltage
V
V
VOUT
TA
Output Voltage
V
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
°C
°C
W
TSTG
PD
-55 to +125
1.0
IOUT
Short Circuit Output Current
50
mA
1.Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C )
Rating
Symbol
Parameter
Units
Notes
Min.
3.0
Typ.
3.3
3.3
-
Max.
3.6
VDD
Power Voltage
V
V
V
V
1
1
VDDQ
VIH
Power Voltage for Output
Input High Voltage
3.0
3.6
2.0
VDD + 0.3
0.8
1,2
1,3
VIL
Input Low Voltage
-0.3
-
1. All voltages referenced to VSS and VSSQ
.
2. V IH (max) = V DD / V DDQ + 1.2V for pulse width £ 5ns
3. VIL (min) = VSS /VSSQ - 1.2V for pulse width £ 5ns .
Capacitance (T = 25 °C, f = 1MHz, VDD = 3.3V ± 0.3V)
A
Symbol
Parameter
Min.
Typ.
3.0
Max.
3.8
Units
pF
Notes
1
Input Capacitance
2.5
(A0-A11, BS0, BS1, /CS, /RAS, /CAS, /WE, CKE, DQM)
Input Capacitance (CLK)
CI
2.5
4.0
2.8
4.5
3.5
6.5
CO
Output Capacitance (DQ0 – DQ15)
1. Multiply given planar values by 2 for 2-High stacked device except /CS.
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
DC Electrical Characteristics (TA = 0 to +70 °C , VDD = 3.3V ± 0.3V)
Symbol
Parameter
Min.
-1
Max.
+1
Units
uA
Notes
1
Input Leakage Current, any input
II(L)
(0.0V £ VIN £ VDD), All Other Pins Not Under Test = 0V
Output Leakage Current
IO(L)
VOH
VOL
-1
2.4
-
+1
-
uA
V
1
-
(DOUT is disabled, 0.0V £ VOUT £ VDDQ
)
Output Level (LVTTL )
Output "H" Level Voltage (IOUT = -2.0mA)
Output Level (LVTTL )
0.4
V
-
Output "L" Level Voltage (IOUT = +2.0mA)
1. Multiply given planar values by 2 for 2-High stacked device.
DC Output Load Circuit
3.3 V
1200 ohms
VOH(DC) = 2.4V,IOH= -2mA
VOL(DC) = 0.4V,IOL= -2mA
Output
50 pF
870 ohms
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Operating, Standby, and Refresh Currents (VDD =3.3V ± 10% , TA =0°C to 70°C)
Version
Parameter
Symbol
Test condition
1 bank operation ,
Unit
Note
- 7
- 75(B)
- 8B
- 8A
tRC = tRC(mim), tCK = min
Active-Precharge
Command cycling
1,2,3
mA
Operating current
ICC1
75
75
70
70
without burst operation
CKE <= VIL(max),
Precharge
standby current
in power-down mode
ICC2P
ICC2PS
ICC2N
2
2
mA
mA
mA
1
1
1
tCK = min, /CS = VIH(min),
CKE <= VIL(max), tCK =oo,
/CS = VIH(min)
CKE >= VIH(min),
/CS = VIH(min), tCK = min
35
35
25
25
Precharge
standby current in non
power-down mode
ICC2NS CKE >= VIH(min), tCK =oo
5
3
mA
1,5
ICC3P
ICC3N
CKE<=VIL(max), tCK =min
mA
mA
1,7
1,5
No Operating current
( Active state : 4 bank)
CKE >=VIH(min),
40
40
30
90
30
90
/CS = VIH(min), tCK =min
t CK =min , Read/ Write
command cycling,
Multiple banks active,
gapless data, BL=4
t RC = tRC(min) ; tCK =min
CBR command cycling
Operating current
( Burst mode )
ICC4
120
145
120
145
mA
1,6
Auto(CBR)
refresh current
Self refresh current
ICC5
ICC6
140
140
mA
mA
1,3,4
1
CKE <= 0.2V
1
Note :
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the
other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of
t and t .Input signals are changed up to three times during t (min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during t (min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
AC Characteristics (TA = 0 to +70 °C , VDD = 3.3V ± 0.3V)
1. An initial pause of 200us,with DQM and CKE held high , is required after power-up. A precharge All Banks command
must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set
operation .
2. The Transition time is measured between VIH and VIL (or between VIL and VIH).
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between
VIL and VIH) in a monotonic manner.
4. Load Circuit A : AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point
5. Load Circuit A : AC measurements assume tT = 1.0ns.
6. Load Circuit B : AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point
7. Load Circuit B : AC measurements assume tT = 1.2ns.
AC Output Load Circuits
tT
Vtt = 1.4V
50 ohm
VIH
tCKL
tCKH
1.4V
VIL
Output
Clock
Input
Zo = 50 ohm
50 pF
50 pF
tSETUP
tHOLD
AC Output Load Circuit ( A )
1.4V
Output
tAC
tOH
1.4V
Zo = 50 ohm
tLZ
Output
AC Output Load Circuit ( B )
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
AC Timing Parameters
Clock and Clock Enable Parameters
- 7
- 75B
- 75
Max.
- 8B
Max.
- 8A
Max.
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
Note
Min.
7
Max.
-
Min.
Max.
Min.
7.5
Min.
8
Min.
8
Clock Cycle Time,
/CAS Latency = 3
Clock Cycle Time,
/CAS Latency = 2
Clock Access Time,
/CAS Latency = 3
Clock Access Time,
/CAS Latency = 2
Clock Access Time,
/CAS Latency = 3
Clock Access Time,
/CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Clock Enable Set-up Time
Clock Enable Hold Time
Power down mode
Entry Time
tCK3
7.5
10
-
-
-
-
-
-
-
tCK2
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
10
-
12
-
tAC3(A)
tAC2(A)
tAC3(B)
tAC2(B)
-
-
1
1
2
2
-
-
-
-
-
-
-
-
-
5.4
-
5.4
-
-
6
6
-
6
6
-
6
-
-
tCKH
tCKL
tCES
tCEH
3
3
2
1
-
-
-
-
2.5
2.5
1.5
0.8
-
-
-
-
2.5
2.5
1.5
0.8
-
-
-
-
3
3
2
1
-
-
-
-
3
3
2
1
-
-
-
-
ns
ns
ns
ns
tSB
tT
0
7
0
7.5
10
0
7.5
10
0
10
10
0
12
10
ns
ns
Transition Time
0.5
10
0.5
0.5
0.5
0.5
(Rise and Fall)
1.Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A
2.Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
- 7
- 75B
- 75
Max.
- 8B
- 8A
Symbol
Parameter
Unit
Note
Min.
2
Max.
Min.
Max.
Min.
1.5
Min.
2
Max.
Min.
2
Max.
tCS
Command Setup Time
Command Hold Time
Address and Bank Select
Set-up Time
-
-
1.5
0.8
-
-
-
-
-
-
-
-
ns
ns
tCH
tAS
1
0.8
1
1
2
1
-
-
1.5
0.8
-
-
1.5
0.8
-
-
2
1
-
-
2
1
-
-
ns
ns
Address and Bank Select
Hold Time
tAH
tRCD
tRC
/RAS to /CAS Delay
Bank Cycle Time
21
70
49
21
14
1
-
-
20
65
45
20
15
1
-
-
20
65
45
20
15
1
-
-
20
70
50
20
20
1
-
-
20
70
50
20
20
1
-
-
-
-
-
-
ns
ns
1
1
1
1
1
tRAS
tRP
Active Command Period
Precharge Time
ns
-
-
-
-
-
-
-
-
-
-
-
-
ns
tRRD
tCCD
Bank to Bank Delay Time
/CAS to /CAS Delay Time
ns
CLK
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of
clock cycles = specified value of timing / clock period (count fractions as a whole number).
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Mode Register Set Cycle
- 7
- 75B
- 75
Max.
- 8B
Max.
- 8A
Max.
Symbol
Parameter
Unit
Note
1
Min.
2
Max.
-
Min.
Max.
Min.
2
Min.
2
Min.
2
Mode Register Set
Cycle Time
tRSC
2
-
-
-
-
CLK
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of
clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
- 7
- 75B
- 75
Max.
- 8B
Max.
- 8A
Max.
Symbol
Parameter
Unit
Note
Min.
2.5
Max.
-
Min.
Max.
Min.
-
Min.
2.5
3
Min.
2.5
3
-
-
-
-
-
-
-
-
-
ns
ns
1
2
tOH
Data Out Hold Time
2.7
2.7
Data Out to Low Impedance
Time
tLZ
0
-
0
-
0
-
0
-
0
-
ns
tHZ3
tHZ2
Data Out to High
Impedance Time
3
-
6
-
3
-
5.4
-
3
-
5.4
-
3
3
6
6
3
3
6
8
ns
ns
3
3
DQM Data Out Disable
Latency
tDQZ
2
-
2
-
2
-
2
-
2
-
CLK
1.AC Output Load Circuit A.
2.AC Output Load Circuit B.
3.Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
- 7
- 75B
- 75
Max.
- 8B
Max.
- 8A
Symbol
Parameter
Unit
Note
Note
Min.
-
Max.
64
-
Min.
Max.
64
-
Min.
-
Min.
-
Min.
-
Max.
64
-
tREF
Refresh Period
Self Refresh Exit Time
-
64
-
64
-
ms
ns
tSREX
10
10
10
10
10
Write Cycle
- 7
- 75B
- 75
- 8B
- 8A
Symbol
Parameter
Unit
Min.
2
Max.
Min.
1.5
0.8
15
Max.
Min.
1.5
0.8
15
Max.
Min.
2
Max.
Min.
2
Max.
tDS
Data In Set-up Time
Data In Hold Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
tDH
tDPL
1
1
1
Data input to Precharge
Data In to Active Delay
/CAS Latency = 3
14
15
15
tDAL3
5
-
5
-
5
-
5
-
5
-
CLK
Data In to Active Delay
/CAS Latency = 2
tDAL2
tDQW
-
-
-
-
-
-
-
-
-
4
0
-
-
3
0
-
-
CLK
ns
DQM Write Mask Latency
0
0
0
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Clock Frequency and Latency
Symbol
Parameter
- 7
- 75B
- 75
- 8B
- 8A
Units
tCK
Clock Frequency
143
7
133
7.5
3
100
10
2
133
7.5
3
125
8
100
10
2
125
8
83
12
2
MHz
ns
tCK
Clock Cycle Time
tAA
/CAS Latency
3
3
3
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
tRP
Precharge Time
3
3
2
3
3
2
3
2
tRCD
tRC
/RAS to /CAS Delay
Bank Cycle Time
3
3
2
3
3
2
3
2
10
7
9
7
9
9
7
9
6
tRAS
tDPL
tDAL
tRRD
tCCD
tWL
Minimum Bank Active Time
Data In to Precharge
Data In to Active/Refresh
Bank to Bank Delay Time
/CAS to /CAS Delay Time
Write Latency
6
5
6
6
5
6
4
2
2
2
2
2
2
2
2
5
5
4
5
5
4
5
4
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
tDQW
tDQZ
tCSL
DQM Write Mask Latency
DQM Data Disable Latency
Clock Suspend Latency
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Command Truth Table
CKE
Device
A12,
A13
A11,
A0-A9
Function
/CS
/RAS /CAS
/WE
DQM
A10
Notes
Previous
Cycle
Current
Cycle
State
Mode Register
Set
Auto (CBR)
Refresh
Entry Self
Refresh
Exit Self
Refresh
Single Bank
Precharge
Precharge all
Banks
Bank Activate
Write
Write with
Auto-
Precharge
Read
Idle
Idle
Idle
H
H
H
L
X
H
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
X
X
OP Code
X
X
X
X
X
L
X
X
X
X
X
Idle(Self-
Refresh)
See Current
State Table
See Current
State Table
Idle
H
L
X
H
X
H
X
H
H
X
X
X
H
H
L
L
L
L
H
H
L
L
BS
X
2
H
H
H
X
X
L
L
L
H
H
L
H
L
X
X
BS
BS
Row address
L
2
2
Active
Column
Column
Column
Column
Active
Active
Active
H
H
H
X
X
X
L
L
L
H
H
H
L
L
L
L
H
H
X
X
X
BS
BS
BS
H
L
2
2
2
Read with
Auto-
H
Precharge
Burst
Active
Any
H
H
H
X
X
X
L
L
H
H
X
H
H
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
3,8
Termination
No Operation
Device
Deselect
Clock
Any
H
Active
Active
Active
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
Suspend
Mode Entry
Clock
Suspend
Mode Exit
Data
Write/Output
Enable
Data
Mask/Output
Disable
Power Down
Mode Entry
4
5
H
Active
H
H
L
X
L
H
X
X
X
X
X
X
X
X
X
X
X
H
L
X
H
X
H
X
H
Idle/Active
6,7
6,7
Any
(Power
Down)
H
L
X
H
X
H
X
H
Power Down
Mode Exit
H
1
All of the SDRAM operations are defined by states of /CS, /WE, /RAS, /CAS, and DQM at the positive rising edge of the clock.
Operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other
deck. Refer to the Current State Truth Table.
2. Bank Select(BS0,BS1):BS0,BS1=0,0 selects bank0; BS0,BS1=0,1 selects bank1; BS0,BS1=1,0 selects bank2; BS0,BS1= 1,1
selects bank 3.
3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the /CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high data clock
timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function
for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the
device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device
can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.
REV 1.1 June, 2000
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©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Clock Enable (CKE) Truth Table
CKE
Command
Current
State
Action
Notes
Previous
Cycle
H
Current
Cycle
X
A12,
A13
X
A11–
A10
X
/CS
X
/RAS
X
/CAS
X
/WE
X
INVALID
1
2
Exit Self Refresh with
Device Deselect
Exit Self Refresh with No
Operation
L
L
H
H
H
X
X
X
X
X
X
X
Self
L
H
H
H
2
Fresh
L
L
L
L
H
H
H
H
L
L
L
L
X
X
H
H
L
X
X
H
L
X
X
X
L
X
X
X
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
ILLEGAL
Maintain Self Refresh
INVALID
Power Down mode exit,
all banks idle
ILLEGAL
Maintain Power Down
Mode
2
2
2
X
X
X
X
X
1
2
2
L
L
L
H
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Power
Down
X
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
X
H
L
L
L
X
H
L
L
L
X
X
H
L
X
X
X
H
L
X
X
X
H
L
Refer to the Idle State
section of the Current
State Truth Table
CBR Refresh
Mode Register Set
Refer to the Idle State
section of the Current
State Truth Table
Entry Self Refresh
Mode Register Set
Power Down
3
3
3
X
X
All
Banks
Idle
L
OP Code
4
3
3
3
4
X
X
H
L
L
X
X
X
OP Code
X
X
X
X
X
4
Refer to operations in the
Current State Truth Table
Begin Clock Suspend
next cycle
Exit Clock Suspend next
cycle
H
H
H
L
X
X
X
X
X
X
X
X
X
X
Any
State
other
than
listed
above
X
X
5
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Maintain Clock Suspend
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on
the first rising clock after CKE goes high .
3. The address inputs (A13 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table
for more information.
4. The Precharge Power Down Mode,the Self Refresh Mode,and the Mode Register Set can only be entered from the all banks idle
state.
5. Must be a legal command as defined in the Current State Truth Table.
REV 1.1 June, 2000
19
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Current State Truth Table (Part 1 of 3)(See note 1)
Command
Current
State
Action
Notes
A12,
A13
/CS
/RAS
/CAS
/WE
A11-A0
OP Code
Description
L
L
L
L
L
L
L
L
H
L
H
L
Mode Register Set
Auto or Self Refresh
Precharge
Set the Mode Register
Start Auto or Self Refresh
No Operation
2
2,3
X
BS
X
X
Row
Address
Column
Column
X
Activate the specified bank
and row
ILLEGAL
ILLEGAL
No Operation
No Operation
No Operation or Power Down
ILLEGAL
ILLEGAL
Precharge
L
L
H
H
BS
Bank Active
Idle
L
L
L
L
H
L
L
L
H
H
H
H
X
L
L
L
H
H
X
L
L
H
L
H
X
L
BS
BS
X
X
X
Write
Read
4
4
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
X
X
5
OP Code
L
L
L
H
H
L
X
BS
X
X
6
4
Row
Address
L
L
L
L
H
H
H
L
L
H
L
BS
BS
BS
Bank Active
Write
ILLEGAL
Row
Active
Start Write; Determine if Auto
Precharge
Start Read; Determine if Auto
Precharge
Column
Column
7,8
7,8
H
Read
L
L
H
L
L
H
H
X
L
H
H
X
L
L
H
X
L
X
X
X
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
No Operation
No Operation
No Operation
ILLEGAL
OP Code
L
L
H
X
X
ILLEGAL
Terminate Burst; Start the
Precharge
L
L
L
L
L
L
H
H
L
L
H
L
BS
X
Precharge
Bank Active
Write
Row
Address
BS
BS
BS
ILLEGAL
4
Read
Terminate Burst; Start the
Write cycle
Terminate Burst; Start a new
Read cycle
H
H
Column
Column
8,9
8,9
L
H
Read
L
L
H
L
L
H
H
X
L
H
H
X
L
L
H
X
L
X
X
X
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
OP Code
L
L
H
X
X
ILLEGAL
Terminate Burst; Start the
Precharge
L
L
L
L
L
L
H
H
L
L
H
L
BS
X
Precharge
Bank Active
Write
Row
Address
BS
BS
BS
ILLEGAL
4
Write
Terminate Burst; Start a new
Write cycle
Terminate Burst; Start the
Read cycle
H
H
Column
Column
8,9
8,9
L
H
Read
L
L
H
H
H
X
H
H
X
L
H
X
X
X
X
X
X
X
Burst Termination
No Operation
Device Deselect
Terminate the Burst
Continue the Burst
Continue the Burst
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the
Command is being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
REV 1.1 June, 2000
20
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Current State Truth Table (Part 2 of 3)(See note 1)
Command
A12,
A13
Current
State
Action
Notes
/CS
/RAS
/CAS
/WE
A11-A0
Description
L
L
L
L
L
L
L
L
H
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
X
BS
X
X
4
4
Row
Address
Column
Column
X
L
L
H
H
BS
Bank Active
ILLEGAL
Read with
Auto
Precharge
L
L
L
L
H
L
L
L
H
H
H
H
X
L
L
L
H
H
X
L
L
H
L
H
X
L
BS
BS
X
X
X
Write
Read
ILLEGAL
ILLEGAL
ILLEGAL
Continue the Burst
Continue the Burst
ILLEGAL
4
4
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
X
X
OP Code
L
L
L
H
H
L
X
BS
X
X
ILLEGAL
ILLEGAL
4
4
Row
Address
Column
Column
X
L
L
H
H
BS
Bank Active
ILLEGAL
Write with
Auto
Precharge
L
L
L
L
H
L
L
H
H
H
H
X
L
L
L
H
H
X
L
L
H
L
H
X
L
BS
BS
X
X
X
Write
Read
ILLEGAL
ILLEGAL
ILLEGAL
Continue the Burst
Continue the Burst
ILLEGAL
4
4
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
X
X
OP Code
L
L
H
X
X
ILLEGAL
No Operation;
Bank(s) idle after tRP
L
L
L
L
H
H
L
BS
X
Precharge
Row
H
BS
Bank Active
ILLEGAL
4
Address
Column
Column
L
L
H
H
L
L
L
H
BS
BS
Write
Read
ILLEGAL
ILLEGAL
4
4
Precharging
No Operation;
Bank(s) idle after tRP
No Operation;
Bank(s) idle after tRP
No Operation;
Bank(s) idle after tRP
ILLEGAL
L
L
H
H
X
H
H
X
L
H
X
X
X
X
X
X
X
Burst Termination
No Operation
H
Device Deselect
L
L
L
L
L
L
L
L
H
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
X
BS
X
X
ILLEGAL
ILLEGAL
4
Row
L
L
H
H
BS
Bank Active
ILLEGAL
4,10
Address
Column
Column
L
L
H
H
L
L
L
H
BS
BS
Write
Read
ILLEGAL
ILLEGAL
4
4
Row
Activating
No Operation;
Row Active after tRCD
No Operation;
Row Active after tRCD
No Operation;
Row Active after tRCD
L
L
H
H
X
H
H
X
L
H
X
X
X
X
X
X
X
Burst Termination
No Operation
H
Device Deselect
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the
Command is being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Current State Truth Table (Part 3of 3)(See note 1)
Command
Current
State
Action
Notes
A12,
A13
/CS
L
/RAS
L
/CAS
L
/WE
L
A11-A0
Description
Mode Register
Set
OP Code
ILLEGAL
Auto or Self
Refresh
Precharge
L
L
L
L
L
L
L
H
H
H
L
X
X
ILLEGAL
ILLEGAL
ILLEGAL
BS
BS
X
Row
Address
4
4
H
Bank Active
Write
Start Write; Determine if Auto
Precharge
Start Write; Determine if Auto
Precharge
Write
Recovering
L
L
L
L
H
L
H
H
H
H
X
L
L
L
L
H
L
BS
BS
X
Column
9
9
Column
Read
Burst
Termination
No Operation;
H
H
X
L
X
X
X
Row Active after tDPL
No Operation;Row Active after
tDPL
No Operation;
Row Active after tDPL
H
X
L
X
No Operation
X
Device Deselect
Mode Register
Set
OP Code
ILLEGAL
Auto or Self
Refresh
Precharge
L
L
L
L
L
L
L
H
H
H
L
X
X
ILLEGAL
ILLEGAL
ILLEGAL
BS
BS
X
Row
Address
Column
Column
4
4
Write
H
Bank Active
Recovering
With Auto
Precharge
L
L
H
H
L
L
L
H
BS
BS
Write
Read
ILLEGAL
ILLEGAL
4,9
4,9
Burst
Termination
No Operation;
Precharge Active after tDPL
No Operation;
Precharge Active after tDPL
No Operation;
L
L
H
H
X
L
H
H
X
L
L
H
X
L
X
X
X
X
X
X
No Operation
H
L
Device Deselect
Precharge Active after tDPL
Mode Register
Set
OP Code
ILLEGAL
Auto or Self
Refresh
Precharge
L
L
L
L
L
L
L
H
H
H
L
X
X
ILLEGAL
ILLEGAL
ILLEGAL
BS
BS
X
Row
Address
Column
Column
H
Bank Active
Refreshing
L
L
H
H
L
L
L
H
BS
BS
Write
Read
ILLEGAL
ILLEGAL
Burst
Termination
No Operation;
Idle after tRC
No Operation;
Idle after tRC
No Operation;
Idle after tRC
L
L
H
H
X
L
H
H
X
L
L
H
X
L
X
X
X
X
X
X
No Operation
H
L
Device Deselect
Mode Register
Set
OP Code
ILLEGAL
Auto or Self
Refresh
Precharge
L
L
L
L
L
L
L
H
H
H
L
X
X
ILLEGAL
ILLEGAL
ILLEGAL
BS
BS
X
Row
Address
Column
Column
Mode
Register
Accessing
H
Bank Active
L
L
H
H
L
L
L
H
BS
BS
Write
Read
ILLEGAL
ILLEGAL
Burst
L
H
H
L
X
X
ILLEGAL
Termination
No Operation
Device Deselect
L
H
H
X
H
X
H
X
X
X
X
X
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the
Command is being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is
entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
DEVICE OPERATIONS
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization
sequence guarantees the device is preconditioned to each users specific needs.
Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD
and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on
voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power
on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have
been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles
(CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to
unpredictable start-up modes.
Programming the Mode Register
For application flexibility, /CAS latency, burst length, burst sequence, and operation type are user defined variables and must be
programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered
by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four
variables must be redefined when the Mode Register Set Command is issued.
After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a
precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set
Command is activated by the low signals of /RAS, /CAS, /CS, and /WE at the positive edge of the clock. The address input data during this
cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode
register set command once a delay equal to tRSC has elapsed.
/CAS Latency
The /CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when
the data from that Read Command becomes available at the outputs. The /CAS latency is expressed in terms of clock cycles and can have
a value of 2 or 3 cycles. The value of the /CAS latency is determined by the speed grade of the device and the clock frequency that is used
in the application. A table showing the relationship between the /CAS latency, speed grade, and clock frequency appears in the Electrical
Characteristics section of this document. Once the appropriate /CAS latency has been selected it must be programmed into the mode
register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section.
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Mode Register Definition
Mode Register set: (Programming mode)
Address bus
(Ax)
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Mode Register
(Mx)
Operation Mode
CAS Latency
Burst Length
CAS Latency
Burst Type
Burst Length
M6
M5
M4
0
Latency
Reserved
Reserved
2
M3
Type
M2
M1
0
M0
BT=0
BT=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
1
0
0
1
4
1
3
1
8
0
Reserved
Reserved
Reserved
Reserved
0
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
1
0
0
1
1
1
Operation Mode
M13
M12
0
M11
0
M10
0
M9
0
M8
M7
0
Mode
Normal
Multiple Burst with Single Write
0
0
0
0
0
0
0
1
0
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle).
Three parameters define how the burst mode will operate: burst sequence, burst length, and operation mode. The burst sequence and burst
length are programmable and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also
programmable and is set by address bits A7 - A13.
Burst sequence defines the order in which the burst data will be delivered or stored to the SDRAM. The two types of burst sequence
supported are sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write
Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page (actual page length is dependent on organization:
x4, x8, or x16). Full page burst operation is only possible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will
perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation
was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are
single write operations when this mode is selected.
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Length and Sequence
Burst Length
Starting Bit
Interleave
Sequential
A0
0
0-1
1-0
0-1
1-0
2
1
A1
0
A0
0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0
1
4
1
0
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0
0
1
0
1
0
0
1
1
8
1
0
0
1
0
1
1
1
0
1
1
1
Full Page
(Note)
n
n
n
Not supported
Cn, Cn+1,Cn+2…..
Note : Page length is a function of I/O organization and column addressing.
X 8 organization (CA0-CA8); Page Length = 512 bits
X16 organization (CA0-CA7); Page Length = 256 bits
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling /RAS signal. The Bank Activate
command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The bank select address A12 -
A13 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in the selected bank. Activation
of banks within both decks of a 2-high stacked device is allowed.
The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must meet or exceed the /RAS to /CAS delay time (tRCD). Once a
bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum
time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The
minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time
(tRRD). The maximum time that each bank can be held active is specified as tRAS(max).
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Bank Activate Command Cycle
CAS Latency = 3, tRCD = 3
Tn+2 Tn+3
T0
T1
T2
T3
Tn
Tn+1
CLK
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank A
Row Addr.
ADDRESS
RAS-CAS delay(tRCD)
NOP
RAS-RAS delay(tRCD)
Write A
with Aotu
Precharge
Bank A
Activate
Bank B
Activate
Bank A
Activate
NOP
NOP
COMMAND
RAS Cycle time (tRC)
: "H" or "L"
Bank Select
The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation.
Bank Selection Bits
BS0
BS1
0
Bank
0
Bank 0
Bank 1
Bank 2
Bank 3
0
1
1
0
1
1
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high and /CAS low at the
clock's rising edge after the necessary /RAS to /CAS delay (tRCD). /WE must also be defined at this time to determine whether the access
cycle is a read operation (/WE high), or a write operation (/WE low). The address inputs determine the starting column address.
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on
successive clock cycles at data rates of up to 147 MHz. The number of serial data bits for each access is equal to the burst length, which is
programmed into the Mode Register. If the burst length is full page, data is repeatedly read out or written until a Burst Stop or Precharge
Command is issued.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address
information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can
be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as
the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the
new address.
Precharging an active bank after each read or write operation is not necessary, providing the same row is to be accessed again. To perform
a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be
issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access
operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be
done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock
cycle.
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Read Command
The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The
address inputs determine the starting column address for the burst. The Mode Register sets the type of burst (sequential or interleave) and
the burst length (1, 2, 4, 8, full page). The delay from the start of the command to when the data from the first cell appears on the outputs is
equal to the value of the /CAS latency that is set in the Mode Register.
Burst Read Operation
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
tCK2, DQs
DOU A0
DOU A1
DOU A0
DOU A2
DOU A3
CAS latency = 3
tCK3, DQs
DOU A1
DOU A2
DOU A3
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval
that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are
overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the
/CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears.
Read Interrupted by a Read
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
tCK2, DQs
DOU A0
DOU B0
DOU A0
DOU B1
DOU B2
DOU B3
CAS latency = 3
tCK3, DQs
DOU B0
DOU B1
DOU B2
DOU B3
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid
data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is
needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus.
Minimum Read to Write Interval
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
tCK2, DQs
DIN A1
DIN A1
DIN A2
DIN A2
DIN A3
DIN A3
CAS latency = 3
tCK3, DQs
DIN A0
: "H" or "L"
Non-Minimum Read to Write Interval
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
COMMAND
CL = 2 : DQM needed to mask first, second bit of READ data.
DIN A1 DIN A2 DIN A3
CL = 3 : DQM needed to mask first, second bit of READ data.
DIN A1 DIN A2 DIN A3
CAS latency = 2
tCK2, DQs
DIN A0
DIN A0
CAS latency = 3
tCK3, DQs
: DQM high for CAS latency = 2
: DQM high for CAS latency = 3
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Write Command
The Burst Write command is initiated by having /CS, /CAS, and /WE low while holding /RAS high at the rising edge of the clock. The
address inputs determine the starting column address. There is no /CAS latency required for burst write cycles. Data for the first burst write
cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be
supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied
to the DQ pins will be ignored.
Burst Write Operation
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DOU A0
DOU A1
DOU A2
DOU A3
Don't care
DQs
The First data elemant and the Write are
registered on the same clock edge.
Extra data is masked
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the
remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is
satisfied.
Write Interrupted by a Write
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
1 Clk Interval
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
DQs
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in
the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the
Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the
Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
DIN A0
READ B
don't care
don't care
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
tCK2, DQs
DOU B0
DOU B1
DOU B2
DOU B3
DOU B2
CAS latency = 3
tCK3, DQs
DIN A0
don't care
DOU B0
DOU B1
DOU B3
Input data must be removed from the DQs at least one clock cycle
before the data appears on the outputs to avoid data contention.
Input data for the write is masked
Non-Minimum Write to Read Interval
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
DIN A0
NOP
READ B
don't care
don't care
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
tCK2, DQs
DIN A1
DIN A1
DOUT B0
DOUT B1
DOUT B2
DOUT B3
CAS latency = 3
tCK3, DQs
DIN A0
don't care
DOUT B0
DOUT B1
DOUT B2
DOUT B3
Input data must be removed from the DQs at least one clock cycle
before the data appears on the outputs to avoid data contention.
Input data for the write is masked
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Stop Command
Once a burst read or write operation has been initiated, there exist several methods in which to terminate the burst operation prematurely.
These methods include using another Read or Write Command to interrupt an existing burst operation or using a Precharge Command to
interrupt a burst cycle and close the active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention.
If the burst length is full page, the Burst Stop Command may also be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank. Use of the Burst Stop Command during other burst length
operations is illegal. The Burst Stop Command is defined by having /RAS and /CAS high with /CS and /WE low at the rising edge of the
clock.
When using the Burst Stop Command during a burst read cycle, the data DQs go to a high impedance state after a delay which is equal to
the /CAS Latency set in the Mode Register.
Termination of a Burst Read Operation
Burst Length = Full Page, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
The burst ends after a delay equal to the
CAS latency.
CAS latency = 2
tCK2, DQs
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A3
CAS latency = 3
tCK3, DQs
DOUT A1
DOUT A2
DOUT A3
If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.
Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory.
Termination of a Burst Write Operation
Burst Length = Full Page, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
NOP
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency=2,3
DQs
DIN A1
DIN A2
don't care
Input data for the Write is masked
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-
precharge function. When a Read or a Write Command is given to the SDRAM, the /CAS timing accepts one extra address, column address
A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is
low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the
completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged.
During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all
burst read cycles have been completed. Regardless of burst length, the precharge will begin (/CAS latency - 1) clocks prior to the last data
output. Auto-precharge can also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command
with auto-precharge can not be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the
same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge
operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. It should be noted that the device
will not respond to the Auto-Precharge command if the device is programmed for full page burst read or write cycles, or full page burst read
cycles with single write operation.
When using the Auto-Precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge
operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended.
Burst Read with Auto-Precharge
Burst Length = 1, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
Auto-
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tRP#
*
CAS latency = 2
tCK2, DQs
DOUT A0
*
tRP#
CAS latency = 3
tCK3, DQs
DOUT A0
Begin Auto-Precharge
Bank can be reactivated at completion of tRP.
*
tRP is a function of clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Read with Auto-Precharge
Burst Length = 2, CAS Latency = 2, 3
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
READ A
Auto-
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tRP#
*
CAS latency = 2
tCK2, DQs
DOUT A0
DOUT A1
*
tRP#
CAS latency = 3
tCK3, DQs
DOUT A0
DOUT A1
Begin Auto-Precharge
Bank can be reactivated at completion of tRP.
*
tRP is a function of clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
Burst Read with Auto-Precharge
Burst Length = 4, CAS Latency = 2, 3
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
READ A
Auto-
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tRP#
*
CAS latency = 2
tCK2, DQs
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A3
*
tRP#
CAS latency = 3
tCK3, DQs
DOUT A1
DOUT A2
DOUT A3
Begin Auto-Precharge
Bank can be reactivated at completion of tRP.
*
tRP is a function of clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Although a Read Command with auto-precharge cannot be interrupted by a command to the same bank, it can be interrupted by a Read or
Write Command to a different bank. If the interrupting command is issued before auto-precharge begins then the precharge function will
begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP.
Burst Read with Auto-Precharge Interrupted by Read
Burst Length = 4, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
Auto-
Precharge
NOP
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tRP#
*
CAS latency = 2
tCK2, DQs
DOUT A0
DOUT A1
DOUT B0
DOUT B1
DOUT B2
DOUT B3
tRP#
*
CAS latency = 3
tCK3, DQs
DOUT
B3
DOUT A0
DOUT A1
DOUT B0
DOUT B1
DOUT B2
Bank can be reactivated at completion of tRP.
*
tRP is a function of clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.
Burst Read with Auto-Precharge Interrupted by Write
Burst Length = 8, CAS Latency = 2
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
READ A
Auto-
Precharge
NOP
NOP
NOP
WRITE B
NOP
NOP
NOP
NOP
COMMAND
tRP#
*
CAS latency = 2
tCK2, DQs
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B4
DQM
Bank can be reactivated at completion of tRP.
*
tRP is a function of clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-precharge
can not be reactivated until tDAL, Data-in to Active delay , is satisfied.
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Write with Auto-Precharge
Burst Length = 2, CAS Latency = 2, 3
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
READ A
Auto-
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
*
tDAL#
CAS latency = 2
tCK2, DQs
DIN A0
DIN A0
DIN A1
DIN A1
*
tDAL#
CAS latency = 3
tCK3, DQs
Bank can be reactivated at completion of tDAL.
*
Number of clocks required depends on clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be
interrupted by a Read or Write Command to a different bank, however. The precharge function will begin with the new command. The bank
may be reactivated after tRP is satisfied.
Burst Write with Auto-Precharge Interrupted by Write
Burst Length = 4, CAS Latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
Auto-
Precharge
NOP
WRITE B
DIN B0
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tDAL#
*
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
DIN B1
DIN B2
DIN B3
Bank can be reactivated at completion of tDAL.
*
Number of clocks required depends on clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Write with Auto-Precharge Interrupted by Read
Burst Length = 4, CAS Latency = 3
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
WRITE A
Auto-
Precharge
NOP
NOP
READ B
NOP
NOP
NOP
NOP
NOP
COMMAND
tDAL#
*
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
DIN A2
DOUT B0
DOUT B1
DOUT B2
Bank A can be reactivated at completion of tDAL.
*
Number of clocks required depends on clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is
triggered when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock. The Precharge Command can
be used to precharge each bank separately or all banks simultaneously. Three address bits--A10, A12, and A13--are used to
define which bank(s) is to be precharged when the command is issued.
Bank Selection for Precharge by Address Bits
A10
LOW
HIGH
Bank Select
Precharged Bank(s)
Bank defined by BS0, BS1 only
All Banks
BS0, BS1
DON'T CARE
For read cycles, the Precharge Command may be applied (/CAS latency - 1) clocks prior to the last data output. For write cycles, a delay
must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL, Data-
in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The
delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP).
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Read followed by the Precharge Command
Burst Length = 4, CAS Latency = 2
T6 T7 T8
T0
T1
T2
T3
T4
T5
CLK
READ Ax0
NOP
NOP
NOP
NOP
Precharge A
DOUT Ax2
NOP
NOP
NOP
COMMAND
tRP
*
CAS latency = 2
tCK2, DQs
DOUT Ax0
DOUT Ax1
DOUT Ax3
Bank A can be reactivated at completion of tRP.
*
Burst Write followed by the Precharge Command
Burst Length = 2, CAS Latency = 2
T7 T8
T0
T1
T2
T3
T4
T5
T6
CLK
Activate
Bank Ax
NOP
NOP
WRITE Ax0
DIN Ax0
NOP
NOP
Precharge A
NOP
NOP
COMMAND
tDPL#
tRP#
*
CAS latency = 2
tCK2, DQs
DIN Ax1
Bank can be reactivated at completion of tRP.
*
tDPL and tRP are functions of clock cycle time and
speed sort.See the clock Frequency and Latency table.
#
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued,
the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus
as a function of /CAS Latency.
Burst Read Interrupted by Precharge
Burst Length = 8, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ Ax0
NOP
NOP
NOP
Precharge A
DOUT Ax2
DOUT Ax1
NOP
NOP
NOP
NOP
COMMAND
tRP#
*
CAS latency = 2
tCK2, DQs
DOUT Ax0
DOUT Ax1
DOUT Ax0
DOUT Ax3
*
tRP#
CAS latency = 3
tCK3, DQs
DOUT Ax2
DOUT Ax3
Bank A can be reactivated at completion of tRP.
*
tRP is a function of clock cycle time and speed sort.
See the clock Frequency and Latency table.
#
Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that
write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay,
tDPL.
Precharge Termination of a Burst Write
Burst Length = 8, CAS Latency = 2, 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
WRITE Ax0
NOP
NOP
NOP
Precharge A
NOP
NOP
COMMAND
DQM
tDPL#
tDPL
CAS latency = 2
tCK2, DQs
DIN Ax0
DIN Ax0
DIN Ax1
DIN Ax1
DIN Ax2
DIN Ax2
CAS latency = 3
tCK3, DQs
tDPL is an asynchronous timing and may be completed in one or two
clock cycles depending on clock cycle time .
#
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Automatic Refresh Command ( /CAS before /RAS Refresh)
When /CS, /RAS, and /CAS are held low with CKE and /WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode
(CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command
(CBR) can be applied. For a stacked device, both decks may be refreshed at the same time using Automatic Refresh Mode. An address
counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this
cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh
Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the /RAS cycle
time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having /CS,
/RAS, /CAS, and CKE held low with /WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh
Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has
entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh
Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be
restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is
returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued.
This delay is equal to the /RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). When using Self Refresh, both decks of a stacked
device may be refreshed at the same time.
Power Down Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter
Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can
enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered.
(Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock
Suspend mode. See the following section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except
CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode
longer than the Refresh period (tREF) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or a Device Deselect Command)
is required on the next rising clock edge.
Power Down Mode Exit Timing
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+8
CLK
CKE
tCK
tCES(min)
NOP
COMMAND
NOP
NOP
NOP
NOP
NOP
COMMAND
: "H" or "L"
REV 1.1 June, 2000
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NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated
(DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a
read cycle, the data outputs are disabled and become high impedance after a two clock delay, independent of /CAS latency.
Data Mask Activated During a Read Cycle
( Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQs
DOUT A0
DOUT A1
A two-clock delay before the
DQs become Hi-Z
: "H" or "L"
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation
Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered
when /CS is low with /RAS, /CAS, and /WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous
operation that is still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when /CS is brought high,
the /RAS, /CAS, and /WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is registered low while at least one of the banks is active,
Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation
that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM's
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is
exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins
will be actively held valid until Clock Suspend mode is exited.
REV 1.1 June, 2000
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Clock Suspend During a Read Cycle
( Burst Length = 4, CAS Latency = 2)
T7 T8
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
A one clock delay to exit the
Suspend command
A one clock delay before
suspend operaton starts
NOP
READ A
NOP
NOP
NOP
NOP
COMMAND
DQs
DOUT A0
DOUT A1
DOUT A2
: "H" or "L"
DOUT element at the DQs when the suspend operation
starts is held valid
If Clock Suspend mode is initiated during a burst write operation, then the input data is masked and ignored until the Clock Suspend mode
is exited.
Clock Suspend During a Write Cycle
( Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CKE
A one clock delay to exit the
Suspend command
A one clock delay before
suspend operaton starts
NOP
WRITE A
DIN A0
NOP
NOP
NOP
NOP
COMMAND
DQs
DIN A1
DIN A2
DIN A3
: "H" or "L"
DIN is masked during the Clock Suspend Period
REV 1.1 June, 2000
42
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Timing Waveform Diagram
AC Parameters for Write Timing
REV 1.1 June, 2000
43
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
AC Parameters for Read Timing (3/3/3)
REV 1.1 June, 2000
44
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
AC Parameters for Read Timing (2/2/2)
REV 1.1 June, 2000
45
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
AC Parameters for Read Timing (3/2/2)
REV 1.1 June, 2000
46
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
AC Parameters for Read Timing (3/3/3)
REV 1.1 June, 2000
47
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Mode Register Set
REV 1.1 June, 2000
48
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Power On Sequence and Auto Refresh (CBR)
REV 1.1 June, 2000
49
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Clock Suspension, DQM during Burst Read
REV 1.1 June, 2000
50
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Clock Suspension, DQM during Burst Write
REV 1.1 June, 2000
51
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Power Down Mode and Clock Suspend
REV 1.1 June, 2000
52
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Auto Refresh (CBR)
REV 1.1 June, 2000
53
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Self Refresh (Entry and Exit)
REV 1.1 June, 2000
54
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Random Row Read (Interleaving Banks) with Precharge
REV 1.1 June, 2000
55
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Random Row Read (Interleaving Banks) with Auto Precharge
REV 1.1 June, 2000
56
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Random Row Write (Interleaving Banks) with Auto Precharge
REV 1.1 June, 2000
57
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Random Row Write (Interleaving Banks) with Precharge
REV 1.1 June, 2000
58
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Read-Write Cycle
REV 1.1 June, 2000
59
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Interleaved Column Read Cycle
REV 1.1 June, 2000
60
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Auto Precharge after Read Burst
REV 1.1 June, 2000
61
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Auto Precharge after Write Burst
REV 1.1 June, 2000
62
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Burst Read and Single Write Operation
REV 1.1 June, 2000
63
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Full Page Burst Read and Single Write Operation
REV 1.1 June, 2000
64
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
/CS Function (Only /CS signal needs to be asserted at minimum rate)
REV 1.1 June, 2000
65
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT56V6610C0T NT56V6620C0T
64Mb : x8 x16
PC133 / PC100 Synchronous DRAM
Package Dimension
( 400 mil; 54 pin; Thin Small Outline Package )
MILLIMETER
SYMBOL
INCH
NOM.
MIN.
NOM.
MAX.
1.20
0.15
1.05
0.45
0.21
MIN.
MAX.
0.047
0.006
0.041
0.018
0.008
A
A1
A2
B
0.05
0.95
0.30
0.12
0.10
1.00
0.35
0.002
0.037
0.012
0.005
0.004
0.039
0.014
c
D
HE
E
e
L
22.22 BSC
11.76
0.875 BSC
0.463
11.56
10.03
0.80 BSC
0.40
11.96
10.29
0.460
0.390
0.031
0.016
0.470
0.410
10.16
0.400
0.50
0.60
0.020
0.024
L1
S
0.80 REF
0.71 REF
0.031 REF
0.028 REF
0 °
-
8 °
0 °
-
8 °
q
Note:
1. Dimension D odes not include mold protrusions or gate burrs.
2. Mold protrusion and gate burrs shall exceed 0.15 mm per side.
3. Dimension E1 does not include interlead mold protrusions.
4. Interlead mold protrusions shall not exceed 0.25 mm per side.
REV 1.1 June, 2000
66
©NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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