NT5SV32M8AT-75B_技术文档

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Features

• High Performance:

• Multiple Burst Read with Single Write Option

• Automatic and Controlled Precharge Command

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR) and Self Refresh

• Suspend Mode and Power Down Mode

• Standard Power operation

3

-7K

-75B,

-8B,

CL=2

Units

CL=2

CL=3

133

7.5

f

t

Clock Frequency

Clock Cycle

133

7.5

—

100

10

—

MHz

ns

CK

AC

1

2

Clock Access Time

—

ns

5.4

6

ns

• 8192 refresh cycles/64ms

• Random Column Address every CK (1-N Rule)

• Single 3.3V ± 0.3V Power Supply

• LVTTL compatible

1. Terminated load. See AC Characteristics on page 37.

2. Unterminated load. See AC Characteristics on page 37.

3. t

= t

= 2 CKs

RCD

RP

• Package: 54-pin 400 mil TSOP-Type II

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• Four Banks controlled by BA0/BA1 (Bank Select)

• Programmable CAS Latency: 2, 3

• -7K parts for PC133 2-2-2 operation

-75B parts for PC133 3-3-3 operation

-8B parts for PC100 2-2-2 operation

• Programmable Burst Length: 1, 2, 4, 8

• Programmable Wrap: Sequential or Interleave

Description

The NT5SV64M4AT, NT5SV32M8AT, and NT5SV16M16AT

are four-bank Synchronous DRAMs organized as 16Mbit x 4

I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4

Bank, respectively. These synchronous devices achieve

high-speed data transfer rates of up to 133MHz by employing

a pipeline chip architecture that synchronizes the output data

to a system clock. The chip is fabricated with NTC’ s

advanced 256Mbit single transistor CMOS DRAM process

technology.

cycle. In addition, it is possible to program a multiple burst

sequence with single write cycle for write through cache

operation.

Operating the four memory banks in an interleave fashion

allows random access operation to occur at a higher rate

than is possible with standard DRAMs. A sequential and gap-

less data rate of up to 133MHz is possible depending on

burst length, CAS latency, and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are sup-

ported.

The device is designed to comply with all JEDEC standards

set for synchronous DRAM products, both electrically and

mechanically. All of the control, address, and data input/out-

put (I/O or DQ) circuits are synchronized with the positive

edge of an externally supplied clock.

RAS, CAS, WE, and CS are pulsed signals which are exam-

ined at the positive edge of each externally applied clock

(CK). Internal chip operating modes are defined by combina-

tions of these signals and a command decoder initiates the

necessary timings for each operation. A fifteen bit address

bus accepts address data in the conventional RAS/CAS mul-

tiplexing style. Thirteen row addresses (A0-A12) and two

bank select addresses (BA0, BA1) are strobed with RAS.

Eleven column addresses (A0-A9, A11) plus bank select

addresses and A10 are strobed with CAS. Column address

A11 is dropped on the x8 device, and column addresses A11

and A9 are dropped on the x16 device.

Prior to any access operation, the CAS latency, burst length,

and burst sequence must be programmed into the device by

address inputs A0-A12, BA0, BA1 during a mode register set

1

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Pin Assignments for Planar Components (Top View)

V

1

2

3

4

5

54

53

52

51

50

V

SS

V

DD

SS

DQ0

NC

V

DQ7

DQ15

DQ0

V

DDQ

SSQ

DDQ

DQ1

NC

DQ14

DQ13

DQ2

DQ1

DQ0

DQ3

DQ6

V

6

7

49

48

V

SSQ

NC

DDQ

DQ3

NC

DQ12

DQ11

NC

DQ4

NC

8

47

46

45

44

DQ5

DQ2

V

9

V

SSQ

DDQ

SSQ

DDQ

DQ5

NC

10

11

NC

DQ10

DQ9

NC

DQ6

DQ3

DQ1

DQ2

DQ4

V

12

43

V

SSQ

DDQ

DQ7

NC

13

14

15

16

42

41

40

39

NC

DQ8

V

DD

SS

NC

LDQM

WE

NC

WE

DQM

UDQM

CAS

RAS

CS

CAS

RAS

CS

CAS

RAS

CS

17

18

19

38

37

36

CK

CKE

A12

CKE

A12

CKE

A12

BA0

20

35

A11

BA1

A10/AP

A0

21

22

23

34

33

32

A9

A8

A7

A9

A8

A7

A9

A8

A7

A10/AP A10/AP

A0

A1

A2

A1

A2

A1

A2

24

25

31

30

A6

A5

A6

A5

A6

A5

A3

26

27

29

28

A4

V

DD

SS

54-pin Plastic TSOP(II) 400 mil

16Mbit x 4 I/O x 4 Bank

NT5SV64M4AT

8Mbit x 8 I/O x 4 Bank

NT5SV32M8AT

4Mbit x 16 I/O x 4 Bank

NT5SV16M16AT

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Pin Description

CK

CKE (CKE0, CKE1)

CS

Clock Input

Clock Enable

Chip Select

DQ0-DQ15

Data Input/Output

Data Mask

DQM, LDQM, UDQM

V

Power (+3.3V)

Ground

DD

RAS

CAS

Row Address Strobe

Column Address Strobe

Write Enable

V

SS

V

Power for DQs (+3.3V)

Ground for DQs

No Connection

—

DDQ

SSQ

WE

BA1, BA0

A0 - A12

Bank Select

NC

—

Address Inputs

Input/Output Functional Description

Symbol

Type

Polarity

Function

Positive

Edge

CK

Input

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

CKE, CKE0,

CKE1

Activates the CK signal when high and deactivates the CK signal when low. By deactivating the

clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.

Input

Active High

Active Low

CS enables the command decoder when low and disables the command decoder when high. When

the command decoder is disabled, new commands are ignored but previous operations continue.

CS

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be

executed by the SDRAM.

RAS, CAS, WE

BA1, BA0

Input

Active Low

—

Selects which bank is to be active.

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sam-

pled at the rising clock edge.

During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9,

CA11), when sampled at the rising clock edge. Assume the x4 organization.

A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is

high, auto-precharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low,

autoprecharge is disabled.

A0 - A12

Input

—

During a Precharge command cycle, A10 is used in conjunction with BA0, BA1 to control which

bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10

is low, then BA0 and BA1 are used to define which bank to precharge.

Input-

Output

DQ0 - DQ15

—

Data Input/Output pins operate in the same manner as on conventional DRAMs.

The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In

x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In

Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output

enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has

a latency of zero and operates as a word mask by allowing input data to be written if it is low but

blocks the write operation if DQM is high.

DQM

LDQM

UDQM

Input

Active High

V

, V

V

Supply

—

Power and ground for the input buffers and the core logic.

DD

SS

V

Isolated power supply and ground for the output buffers to provide improved noise immunity.

DDQ SSQ

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Ordering Information

Speed Grade

Self

Refresh

Organization

Part Number

Package

Clock Frequency@CAS Latency

Note

NT5SV64M4AT-7K

NT5SV64M4AT-75B

NT5SV64M4AT-8B

NT5SV32M8AT-7K

NT5SV32M8AT-75B

NT5SV32M8AT-8B

NT5SV16M16AT-7K

NT5SV16M16AT-75B

NT5SV16M16AT-8B

NT5SV16M16AT-7KL

NT5SV16M16AT-75BL

NT5SV16M16AT-8BL

143MHz@CL3

133MHz@CL3

125MHz@CL3

143MHz@CL3

133MHz@CL3

125MHz@CL3

143MHz@CL3

133MHz@CL3

125MHz@CL3

143MHz@CL3

133MHz@CL3

125MHz@CL3

133MHz@CL2

100MHz@CL2

133MHz@CL2

100MHz@CL2

133MHz@CL2

100MHz@CL2

133MHz@CL2

100MHz@CL2

PC133 , PC100

PC100

64M x 4

PC133 , PC100

PC100

400mil 54-

TSOP II

32M x 8

16M x 16

SP

PC133 , PC100

PC100

PC133 , PC100

PC100

LP

SP : Standard Power ; LP : Low power

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Block Diagram

Column Decoder

KE

CKE Buffer

Cell Array

Memory Bank 0

Memory Bank 1

CK

CK Buffer

Sense Amplifiers

A0

A1

A2

A3

A4

A5

A6

DQ₀

DQ_X

A7

A8

A9

A11

A12

BA1

BA0

A10

DQM

Column Decoder

CS

RAS

CAS

Cell Array

Memory Bank 2

Cell Array

Memory Bank 3

WE

Sense Amplifiers

Cell Array, per bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3).

Cell Array, per bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7).

Cell Array, per bank, for 4Mb x 16 DQ:8192 Row x 512 Col x 16 DQ (DQ0-DQ15).

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Power On and Initialization

The default power on state of the mode register is supplier specific and may be undefined. The following power on and initializa-

tion sequence guarantees the device is preconditioned to each users specific needs.

Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power

on, all V_DDand V_DDQpins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP”

state. The power on voltage must not exceed V_DD+0.3V on any of the input pins or V_DDsupplies. The CK signal must be started

at the same time. After power on, an initial pause of 200ms is required followed by a precharge of all banks using the precharge

command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high

during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to ini-

tialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after

programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.

Programming the Mode Register

For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be

programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can

be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register

variables, all four variables must be redefined when the Mode Register Set Command is issued.

After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must

be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The

Mode Register Set Command is activated by the low signals of RAS, CAS, CS, and WE at the positive edge of the clock. The

address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new

command may be issued following the mode register set command once a delay equal to t_RSChas elapsed.

CAS Latency

The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock

edge to when the data from that Read Command becomes available at the outputs. The CAS latency is expressed in terms of

clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the

device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed

grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS

latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure

see Programming the Mode Register in the previous section.

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Mode Register Operation (Address Input For Mode Set)

Address

Bus (Ax)

BA1 BA0 A12

A11 A10

A9

A8

A7

A6

A5

A4

A3

BT

A2

A1

A0

Mode

Register(Mx)

Operation Mode

CAS Latency

Burst Length

Burst Type

M3

0

Type

Sequential

Interleave

1

Operation Mode

Burst Length

M1 4 M13 M12 M11 M10 M9 M8 M7

Mode

Length

0

Normal

M2

M1 M0

Sequential Interleave

Multiple Burst

with

Single Write

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

1

2

4

8

CAS Latency

M6

M5

M4

Latency

Reserved

2

Reserved Reserved

0

1

0

1

0

1

3

1

0

Reserved

1

0

1

0

1

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations

(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst

sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by

address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits

A7 - A12, BA0, and BA1.

The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst

sequences are supported, sequential and interleaved. See the table below.

The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a

Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 (actual page length is dependent on organi-

zation: x4, x8, or x16).

Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the

device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with

single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to

read cycles. All write cycles are single write operations when this mode is selected.

Burst Length and Sequence

Burst Length

Starting Address (A2 A1 A0)

Sequential Addressing (decimal)

0, 1

Interleave Addressing (decimal)

0, 1

x x 0

x x 1

x 0 0

x 0 1

x 1 0

x 1 1

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

2

1, 0

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

4

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

Note: Page length is a function of I/O organization and column addressing.

x4 organization (CA0-CA9, CA11); Page Length = 2048 bits

x8 organization (CA0-CA9); Page Length = 1024 bits

x16 organization (CA0-CA8); Page Length = 512 bits

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Bank Activate Command

In relation to the operation of a fast page mode DRAM, the Bank Activate command correlates to a falling RAS signal. The Bank

Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The Bank Select

address BA0 - BA1 is used to select the desired bank. The row address A0 - A12 is used to determine which row to activate in

the selected bank.

The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the

Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS

delay time (t_RCD). Once a bank has been activated it must be precharged before another Bank Activate command can be

applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is deter-

mined by the RAS cycle time of the device (t_RC). The minimum time interval between interleaved Bank Activate commands

(Bank A to Bank B and vice versa) is the Bank to Bank delay time (t_RRD). The maximum time that each bank can be held active

is specified as t_RAS(max)

.

Bank Activate Command Cycle

(CAS Latency = 3, t_RCD= 3)

T0

T1

T2

T3

Tn

Tn+1

Tn+2

Tn+3

CK

. . . . . . . . . .

Bank A

Row Addr.

Bank A

Bank B

Row Addr.

Bank A

Row Addr.

. . . . . . . . . .

ADDRESS

Col. Addr.

RAS-CAS delay (t_RCD

)

RAS - RAS delay time (t_RRD)

Write A

with Auto

Precharge

Bank B

NOP

Bank A

Activate

Bank A

Activate

. . . . . . . . . .

NOP

COMMAND

Activate

: “H” or “L”

RAS Cycle time (t_RC

)

Bank Select

The Bank Select inputs, BA0 and BA1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write oper-

ation.

Bank Selection Bits

BA0

BA1

Bank

0

1

0

1

0

1

Bank 0

Bank 1

Bank 2

Bank 3

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Read and Write Access Modes

After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low

at the clock’ s rising edge after the necessary RAS toCAS delay (t_RCD). WE must also be defined at this time to determine

whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the start-

ing column address.

The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write

operation on successive clock cycles up to 133MHz. The number of serial data bits for each access is equal to the burst length,

which is programmed into the Mode Register.

Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected

row address information. The refresh period (t_REF) is what limits the number of random column accesses to an activated bank.

A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock

cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Com-

mand, the remaining addresses are overridden by the new address.

Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again.

To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Acti-

vate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations

are possible. By using the programmed burst length and alternating the access and precharge operations between multiple

banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are acti-

vated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be

issued to the same bank or between active banks on every clock cycle.

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Burst Read Command

The Burst Read command is initiated by having CS and CAS low while holdingRAS and WE high at the rising edge of the clock.

The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or

interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears

on the outputs is equal to the value of the CAS latency that is set in the Mode Register.

Burst Read Operation

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

READ A

NOP

COMMAND

CAS latency = 2

DOUT A

0

1

2

3

t

_,DQs

CK2

CAS latency = 3

DOUT A

3

0

1

2

t

_,DQs

CK3

Read Interrupted by a Read

A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that

the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remain-

ing addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to

appear on the outputs until the CAS latency from the interrupting Read Command is satisfied, at this point the data from the

interrupting Read Command appears.

Read Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

READ A

READ B

NOP

COMMAND

CAS latency = 2

DOUT A

DOUT B

DOUT A

DOUT B

3

0

1

2

t

_,DQs

CK2

CAS latency = 3

DOUT B

3

0

1

2

t

_,DQs

CK3

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance

state to avoid data contention on the DQ bus. If a Read Command will issue data on the first or second clocks cycles of the

write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ

bus.

Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

DQM high for CAS latency = 2 only.

Required to mask first bit of READ data.

DQM

NOP

READ A

WRITE A

NOP

COMMAND

CAS latency = 2

DIN A

0

DIN A

1

2

3

t

_,DQs

CK2

CAS latency = 3

DIN A

0

DIN A

2

1

t

_,DQs

CK3

: “H” or “L”

12

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256Mb Synchronous DRAM

Non-Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2, 3)

T5 T6 T7 T8

T0

T1

T2

T3

T4

CK

DQM

READ A

NOP

WRITE A

NOP

COMMAND

CL = 2: DQM needed to mask

first, second bit of READ data.

CAS latency = 2

DIN A

0

1

2

3

t

_,DQs

CK2

CL = 3: DQM needed to

mask first bit of READ data.

CAS latency = 3

DIN A

1

2

t

_,DQs

CK3

: DQM high for CAS latency = 2

: DQM high for CAS latency = 3

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256Mb Synchronous DRAM

Burst Write Command

The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock.

The address inputs determine the starting column address. There is no CAS latency required for burst write cycles. Data for the

first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining

data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has fin-

ished, any additional data supplied to the DQ pins will be ignored.

Burst Write Operation

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

NOP

WRITE A

NOP

COMMAND

DIN A

3

DQs

0

1

2

: “ H” or “ L”

The first data element and the Write

are registered on the same clock edge.

Extra data is masked.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is inter-

rupted, the remaining addresses are overridden by the new address and data will be written into the device until the pro-

grammed burst length is satisfied.

Write Interrupted by a Write

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

NOP

WRITE A

WRITE B

NOP

COMMAND

1 CK Interval

DIN A

DIN B

3

DQs

0

1

2

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NT5SV16M16AT(L)

256Mb Synchronous DRAM

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs

must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data

contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is pre-

sented on the DQ pins before the Read Command is initiated will actually be written to the memory.

Minimum Write to Read Interval

(Burst Length = 4, CAS latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

WRITE A

READ B

NOP

COMMAND

CAS latency = 2

DIN A

0

DOUT B

0

DOUT B

1

2

1

3

t

_,DQs

CK2

CAS latency = 3

DIN A

0

DOUT B

0

2

3

t

_,DQs

CK3

: “H” or “L”

Input data for the Write is masked.

Input data must be removed from the DQs at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

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256Mb Synchronous DRAM

Non-Minimum Write to Read Interval

(Burst Length = 4, CAS latency = 2, 3)

T5 T6 T7 T8

T0

T1

T2

T3

T4

CK

WRITE A

NOP

READ B

NOP

COMMAND

CAS latency = 2

DIN A

DOUT B

0

DOUT B

0

1

2

3

t

_,DQs

CK2

CAS latency = 3

DOUT B

3

0

1

2

t

_,DQs

CK3

: “ H” or “ L”

Input data for the Write is masked.

Input data must be removed from the DQs at least one clock

cycle before the Read data appears on the outputs to avoid

data contention.

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NT5SV16M16AT(L)

256Mb Synchronous DRAM

Auto-Precharge Operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command

or the auto-precharge function. When a Read or a Write Command is given to the SDRAM, the CAS timing accepts one extra

address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during

the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst opera-

tion is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write

Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as

normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed.

Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last data output. Auto-precharge can

also be implemented during Write commands.

A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or

Write Command with auto-precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or

Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst oper-

ation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (t_RP) has

been satisfied.

When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal

precharge operation must satisfy t_RAS(min). If this interval does not satisfy t_RAS(min)then t_RCDmust be extended.

Burst Read with Auto-Precharge

(Burst Length = 1, CAS Latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

READ A

NOP

COMMAND

Auto-Precharge

t

‡

RP

CAS latency = 2

*

t

_,DQs

DOUT A

CK2

0

t

‡

RP

CAS latency = 3

*

t

_,DQs

DOUT A

CK3

0

Bank can be reactivated at completion of t

.

RP

*

Begin Auto-precharge

‡ t is a function of clock cycle time and speed sort.

RP

See the Clock Frequency and Latency table.

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256Mb Synchronous DRAM

Burst Read with Auto-Precharge

(Burst Length = 2, CAS Latency = 2, 3)

T5 T6 T7 T8

T0

T1

T2

T3

T4

CK

READ A

Auto-Precharge

NOP

COMMAND

t

‡

RP

CAS latency = 2

*

t

_,DQs

DOUT A

CK2

0

1

t

‡

RP

CAS latency = 3

*

t

_,DQs

DOUT A

CK3

0

1

Begin Auto-precharge

Bank can be reactivated at completion of t

.

R P

*

‡ t is a function of clock cycle time and speed sort.

See the Clock Frequency and Latency table.

R P

Burst Read with Auto-Precharge

(Burst Length = 4, CAS Latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

READ A

NOP

COMMAND

Auto-Precharge

t_RP

‡

CAS latency = 2

*

t

_,DQs

DOUT A

3

CK2

0

1

2

1

t_RP

‡

CAS latency = 3

*

t

_,DQs

DOUT A

3

CK3

0

2

Bank can be reactivated at completion of t

.

RP

*

‡ t is a function of clock cycle time and speed sort.

Begin Auto-precharge

R P

See the Clock Frequency and Latency table.

*

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256Mb Synchronous DRAM

Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it can be interrupted

by a Read or Write Command to a different bank. If the command is issued before auto-precharge begins then the precharge

function will begin with the new command. The bank being auto-precharged may be reactivated after the delay t_RP

.

Burst Read with Auto-Precharge Interrupted by Read

(Burst Length = 4, CAS Latency = 2, 3)

T5 T6 T7 T8

T0

T1

T2

T3

T4

CK

READ A

NOP

READ B

DOUT A

COMMAND

Auto-Precharge

t

‡

RP

CAS latency = 2

*

t

_CK2,DQs

DOUT A

DOUT B

3

0

1

0

1

0

2

t

‡

RP

CAS latency = 3

*

t

_,DQs

CK3

DOUT A

DOUT B

3

0

1

2

Bank can be reactivated at completion of t

.

RP

*

‡ t is a function of clock cycle time and speed sort.

RP

See the Clock Frequency and Latency table.

If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention.

Burst Read with Auto-Precharge Interrupted by Write

(Burst Length = 8, CAS Latency = 2)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

READ A

Auto-Precharge

NOP

WRITE B

COMMAND

t

‡

RP

CAS latency = 2

*

t

_CK2,DQs

DOUT A

DIN B

4

0

1

2

3

DQM

Bank can be reactivated at completion of t

.

RP

*

‡ t is a function of clock cycle time and speed sort. .

RP

See the Clock Frequency and Latency table.

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256Mb Synchronous DRAM

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-

precharge cannot be reactivated until t_DAL, Data-in to Active delay, is satisfied.

Burst Write with Auto-Precharge

(Burst Length = 2, CAS Latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

WRITE A

NOP

COMMAND

Auto-Precharge

t

‡

DAL

CAS latency = 2

*

t

_,DQs

DIN A

0

DIN A

CK2

1

t

‡

DAL

*

CAS latency = 3

t

_,DQs

DIN A

0

CK3

Bank can be reactivated at completion of t

.

DAL

*

‡ t

is a function of clock cycle time and speed sort.

DAL

See the Clock Frequency and Latency table.

Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank.

It can be interrupted by a Read or Write Command to a different bank, however. The interrupting command will terminate the

write. The bank undergoing auto-precharge can not be reactivated until t_DALis satisfied.

Burst Write with Auto-Precharge Interrupted by Write

(Burst Length = 4, CAS Latency = 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

WRITE A

NOP

WRITE B

NOP

COMMAND

Auto-Precharge

t

‡

DAL

CAS latency = 3

*

t

_CK3,DQs

DIN A

DIN B

3

0

1

0

1

2

Bank can be reactivated at completion of t

.

DAL

*

‡ t

is a function of clock cycle time and speed sort.

DAL

See the Clock Frequency and Latency table.

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256Mb Synchronous DRAM

Burst Write with Auto-Precharge Interrupted by Read

(Burst Length = 4, CAS Latency = 3)

T6 T7 T8

T0

T1

T2

T3

T4

T5

CK

WRITE A

NOP

READ B

NOP

COMMAND

Auto-Precharge

t

‡

DAL

*

CAS latency = 3

t

_,DQs

DIN A

0

DIN A

2

DOUT B

CK3

1

0

1

2

Bank A can be reactivated at completion of t

.

*

DAL

‡ t

is a function of clock cycle time and speed sort.

DAL

See the Clock Frequency and Latency table.

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered

when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to pre-

charge each bank separately or all banks simultaneously. Three address bits, A10, BA0, and BA1, are used to define which

bank(s) is to be precharged when the command is issued.

Bank Selection for Precharge by Address Bits

A10

LOW

HIGH

Bank Select

BA0, BA1

Precharged Bank(s)

Single bank defined by BA0, BA1

All Banks

DON’ T CARE

For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a

delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is

known as t_DPL, Data-in to Precharge delay.

After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be

executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Pre-

charge time (t_RP).

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Burst Read Followed by the Precharge Command

(Burst Length = 4, CAS Latency = 3)

T6 T7 T8

T0

T1

T2

T3

T4

T5

CK

READ Ax

NOP

Precharge A

NOP

COMMAND

0

‡

t

RP

*

CAS latency = 3

DOUT Ax

3

0

1

2

t

_,DQs

CK2

Bank A can be reactivated at completion of t

.

RP

*

‡ t is a function of clock cycle and speed sort.

R P

Burst Write Followed by the Precharge Command

(Burst Length = 2,CAS Latency = 2)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

Activate

Bank Ax

NOP

Precharge A

NOP

WRITE Ax

NOP

COMMAND

0

t

‡

t

‡

RP

DPL

*

CAS latency = 2

t

_CK2,DQs

DIN Ax

1

0

Bank can be reactivated at completion of t

.

RP

*

‡ t

and t

are functions of clock cycle and speed sort.

DPL

See the Clock Frequency and Latency table.

RP

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Precharge Termination

The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command

is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to

appear on the data bus as a function of CAS Latency.

Burst Read Interrupted by Precharge

(Burst Length = 8, CAS Latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

READ Ax

NOP

Precharge A

COMMAND

CAS latency = 2

0

t

‡

RP

*

DOUT Ax

3

0

1

2

t

_,DQs

CK2

t

‡

RP

*

DOUT Ax

3

CAS latency = 3

DOUT Ax

0

1

2

t

_,DQs

CK3

Bank A can be reactivated at completion of t

.

RP

‡

t

is a function of clock cycle time and speed sort.

*

R P

See the Clock Frequency and Latency table.

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256Mb Synchronous DRAM

Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the

device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the

Data-in to Precharge delay, t_DPL

.

Precharge Termination of a Burst Write

(Burst Length = 8,CAS Latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

NOP

Precharge A

NOP

WRITE Ax

NOP

COMMAND

0

DQM

t

‡

DPL

CAS latency = 2

t

_,DQs

DIN Ax

CK2

0

1

2

t

DPL

CAS latency = 3

t

_,DQs

DIN Ax

CK3

‡ t

is an asynchronous timing and may be completed in one or two clock cycles

DPL

depending on clock cycle time.

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Automatic Refresh Command (CAS before RAS Refresh)

When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic

Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (t_RP) before

the Auto Refresh Command (CBR) can be applied. An address counter, internal to the device provides the address during the

refresh cycle. No control of the external address pins is required once this cycle has started.

When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto

Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or

equal to the RAS cycle time (t_RC).

Self Refresh Command

The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by hav-

ing CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the

Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.

When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is

internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self

Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is

cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the devic e

exits Self Refresh Operation and before the next command can be issued. This delay is equal to the RAS cycle time (t_RC) plus

the Self Refresh exit time (t_SREX).

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Power Down Mode

In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down

mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (t_RP) must

occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation,

Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or

Write operation causes the device to enter Clock Suspend mode. See the following Clock Suspend section.) Once the Power

Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does

not perform any refresh operations, therefore the device can’ t remain in Power Down mode longer than the Refresh period

(t_REF) of the device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or Device Deselect

Command) is required on the next rising clock edge.

Power Down Mode Exit Timing

Tm

Tm+1

Tm+2

Tm+3

Tm+4

Tm+5

Tm+6

Tm+7

Tm+ 8

CK

t

CK

CKE

t

CES(min)

NOP

COMMAND

NOP

COMMAND

: “ H” or “ L”

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Data Mask

The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is

activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is

activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent

of CAS latency.

Data Mask Activated during a Read Cycle

(Burst Length = 4,CAS Latency = 2)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

DQM

NOP

READ A

NOP

COMMAND

DOUT A

DQs

DOUT A

1

0

A two-clock delay before

the DQs become Hi-Z

: “H” or “L”

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No

Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation

Command is registered when CS is low withRAS, CAS, and WE held high at the rising edge of the clock. A No Operation Com-

mand will not terminate a previous operation that is still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is

brought high, the RAS, CAS, and WE signals become don’ t cares.

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Clock Suspend Mode

During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks

is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes”

any clocked operation that was currently being executed. There is a one-clock delay between the registration of CKE low and

the time at which the SDRAM’ s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands

that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE

returns high to when Clock Suspend mode is exited.

When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto

the DQ pins will be actively held valid until Clock Suspend mode is exited.

Clock Suspend during a Read Cycle

(Burst Length = 4, CAS Latency = 2)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

A one clock delay to exit

the Suspend command

CKE

A one clock delay before

suspend operation starts

NOP

READ A

NOP

COMMAND

DQs

DOUT A

2

DOUT A

0

1

: “ H” or “ L”

DOUT element at the DQs when the

suspend operation starts is held valid

If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until the Clock Sus-

pend mode is exited.

Clock Suspend during a Write Cycle

(Burst Length = 4, CAS Latency = 2)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

A one clock delay to exit

the Suspend command

CKE

A one clock delay before

suspend operation starts

NOP

WRITE A

DIN A

NOP

COMMAND

DIN A

3

DQs

1

2

0

: “H” or “L”

DIN is masked during the Clock Suspend Period

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Command Truth Table (See note 1)

CKE

A12,

A11,

A9-A0

BA0,

BA1

Function

Device State

CS

RAS CAS

WE

DQM

A10

Notes

Previous Current

Cycle

Mode Register Set

Auto (CBR) Refresh

Entry Self Refresh

Idle

H

X

H

L

H

L

H

X

H

X

OP Code

Idle

X

L

X

H

X

H

Idle (Self-

Refresh)

Exit Self Refresh

L

H

X

See Current

State Table

Single Bank Precharge

Precharge all Banks

H

X

L

H

L

X

BS

X

L

X

2

See Current

State Table

H

Bank Activate

Write

Idle

H

L

X

L

H

X

H

X

H

L

H

L

X

L

BS

X

Row Address

2

Active

L

H

L

Column

Write with Auto-Precharge

Read

L

Column

L

H

L

Column

Read with Auto-Precharge

Reserved

L

H

X

Column

L

H

X

H

X

H

X

No Operation

Device Deselect

Any

L

H

X

H

X

H

X

H

X

H

L

X

Clock Suspend Mode Entry Active

X

4

Clock Suspend Mode Exit

Data Write/Output Enable

Data Mask/Output Disable

Active

H

X

H

X

5

H

X

Power Down Mode Entry

Power Down Mode Exit

Idle/Active

H

L

X

6, 7

H

L

Any (Power

Down)

H

1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Refer to the

Current State Truth Table.

2. Bank Select (BA0, BA1): BA0, BA1 = 0,0 selects bank 0; BA0, BA1 = 1,0 selects bank 1; BA0, BA1 = 0,1 selects bank 2; BA0, BA1 = 1,1

selects bank 3.

3. Not applicable.

4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and

Write operations. One clock delay is required for mode entry and exit.

5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the

data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles.

When it activates, the Write operation at the clock is prohibited (zero clock latency).

6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device

state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’ t remain in

this mode longer than the Refresh period (t

) of the device. One clock delay is required for mode entry and exit.

REF

7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.

29

REV 1.0

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Clock Enable (CKE) Truth Table

CKE

Command

Current State

Action

Notes

Current

Cycle

BA0,

BA1

CS

RAS

CAS

WE

A12 - A0

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

INVALID

1

2

Exit Self Refresh with Device Deselect

Exit Self Refresh with No Operation

ILLEGAL

L

Self Refresh

L

X

H

L

ILLEGAL

L

X

H

L

ILLEGAL

L

X

H

L

X

H

L

Maintain Self Refresh

INVALID

H

L

X

H

L

1

2

Power Down mode exit, all banks idle

ILLEGAL

Power Down

L

X

H

L

Maintain Power Down Mode

H

L

H

L

3

Refer to the Idle State section of the

Current State Truth Table

L

X

CBR Refresh

L

OP Code

Mode Register Set

4

3

4

All Banks Idle

H

L

X

H

L

X

H

L

X

H

L

Refer to the Idle State section of the

Current State Truth Table

L

X

Entry Self Refresh

Mode Register Set

Power Down

L

OP Code

X

4

5

Refer to operations in the Current State

Truth Table

H

X

Any State

other than

listed above

H

L

H

L

X

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

Maintain Clock Suspend

1. For the given Current State CKE must be low in the previous cycle.

2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE

(t ) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising

CES

clock after CKE goes high (see page 26).

3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more informa-

tion.

4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle stat e.

5. Must be a legal command as defined in the Current State Truth Table.

30

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Current State Truth Table (Part 1 of 3)(See note 1)

Command

Current State

Action

Set the Mode Register

Notes

CS RAS CAS WE BA0,BA1

A12 - A0

Description

L

H

L

H

L

H

L

H

L

OP Code

Mode Register Set

2

H

L

X

Auto or Self Refresh Start Auto or Self Refresh

2, 3

L

H

L

BS

X

Precharge

No Operation

L

H

L

Row Address Bank Activate

Activate the specified bank and row

Idle

Row Active

Read

H

X

L

Column

Write w/o Precharge ILLEGAL

Read w/o Precharge ILLEGAL

4

L

H

X

L

Column

H

X

L

X

No Operation

X

Device Deselect

Mode Register Set

No Operation or Power Down

ILLEGAL

5

OP Code

L

H

L

X

Auto or Self Refresh ILLEGAL

L

H

L

BS

X

Precharge

6

L

H

L

Row Address Bank Activate

ILLEGAL

4

H

X

L

Column

Write

Start Write; Determine if Auto Precharge

Start Read; Determine if Auto Precharge

No Operation

7, 8

L

H

X

L

Column

Read

H

X

L

X

No Operation

Device Deselect

Mode Register Set

X

No Operation

OP Code

ILLEGAL

L

H

L

X

Auto or Self Refresh ILLEGAL

Precharge Terminate Burst; Start the Precharge

L

H

L

BS

X

L

H

L

Row Address Bank Activate

ILLEGAL

4

H

X

L

Column

Write

Terminate Burst; Start the Write cycle

Terminate Burst; Start a new Read cycle

Continue the Burst

8, 9

L

H

X

L

Column

Read

H

X

L

X

No Operation

Device Deselect

Mode Register Set

X

Continue the Burst

OP Code

ILLEGAL

L

H

L

X

Auto or Self Refresh ILLEGAL

Precharge Terminate Burst; Start the Precharge

L

H

L

BS

X

L

H

L

Row Address Bank Activate

ILLEGAL

4

Write

H

X

Column

Write

Terminate Burst; Start a new Write cycle

Terminate Burst; Start the Read cycle

Continue the Burst

8, 9

L

H

X

Column

Read

H

X

No Operation

Device Deselect

X

Continue the Burst

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (t

) must be satisfied.

RAS

7. The RAS to CAS Delay (t

) must occur before the command is given.

RCD

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

) is not satisfied.

RRD

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Current State Truth Table (Part 2 of 3)(See note 1)

Command

Current State

Action

Notes

CS RAS CAS WE BA0,BA1

A12 - A0

Description

L

H

L

H

L

H

L

H

L

OP Code

Mode Register Set

ILLEGAL

H

L

X

Auto or Self Refresh ILLEGAL

L

H

L

BS

X

Precharge

ILLEGAL

4

Read with

Auto Pre-

charge

L

H

L

Row Address Bank Activate

H

X

L

Column

Write

L

H

X

L

Column

Read

H

X

L

X

No Operation

Device Deselect

Mode Register Set

Continue the Burst

ILLEGAL

X

OP Code

L

H

L

X

Auto or Self Refresh ILLEGAL

L

H

L

BS

X

Precharge

ILLEGAL

4

L

H

L

Row Address Bank Activate

ILLEGAL

Write with Auto

Precharge

H

X

L

Column

Write

ILLEGAL

L

H

X

L

Column

Read

ILLEGAL

H

X

L

X

No Operation

Device Deselect

Mode Register Set

Continue the Burst

ILLEGAL

X

OP Code

L

H

L

X

Auto or Self Refresh ILLEGAL

Precharge No Operation; Bank(s) idle after t

L

H

L

BS

X

RP

L

H

L

Row Address Bank Activate

ILLEGAL

4

Precharging

H

X

L

Column

Write

ILLEGAL

L

H

X

L

Column

Read

ILLEGAL

H

X

L

X

No Operation

Device Deselect

Mode Register Set

No Operation; Bank(s) idle after t

ILLEGAL

RP

X

OP Code

L

H

L

X

Auto or Self Refresh ILLEGAL

L

H

L

BS

X

Precharge

ILLEGAL

4

4, 10

4

L

H

L

Row Address Bank Activate

ILLEGAL

Row

Activating

H

X

Column

Write

ILLEGAL

L

H

X

Column

Read

ILLEGAL

4

H

X

No Operation

Device Deselect

No Operation; Row Active after t

RCD

X

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (t

) must be satisfied.

RAS

7. The RAS to CAS Delay (t

) must occur before the command is given.

RCD

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

) is not satisfied.

RRD

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Current State Truth Table (Part 3 of 3)(See note 1)

Command

Current State

Action

Notes

CS RAS CAS WE BA0,BA1

A12 - A0

Description

L

H

L

H

L

H

L

H

L

OP Code

Mode Register Set

ILLEGAL

H

L

X

Auto or Self Refresh ILLEGAL

L

H

L

BS

X

Precharge

ILLEGAL

4

9

L

H

L

Row Address Bank Activate

Write

Recovering

H

X

L

Column

Write

Start Write; Determine if Auto Precharge

Start Read; Determine if Auto Precharge

L

H

X

L

Column

Read

H

X

L

X

No Operation

Device Deselect

Mode Register Set

No Operation; Row Active after t

DPL

X

No Operation; Row Active after t

DPL

OP Code

ILLEGAL

L

H

L

X

Auto or Self Refresh ILLEGAL

Write

Recovering

with

Auto Pre-

charge

L

H

L

BS

X

Precharge

ILLEGAL

4

L

H

L

Row Address Bank Activate

ILLEGAL

4

H

X

L

Column

Write

ILLEGAL

4, 9

L

H

X

L

Column

Read

ILLEGAL

H

X

L

X

No Operation

Device Deselect

Mode Register Set

No Operation; Precharge after t

ILLEGAL

DPL

X

OP Code

L

H

L

X

Auto or Self Refresh ILLEGAL

L

H

L

BS

X

Precharge

ILLEGAL

L

H

L

Row Address Bank Activate

ILLEGAL

Refreshing

H

X

L

Column

Write

ILLEGAL

L

H

X

L

Column

Read

ILLEGAL

H

X

L

X

No Operation

Device Deselect

Mode Register Set

No Operation; Idle after t

ILLEGAL

RC

X

OP Code

L

H

L

X

Auto or Self Refresh ILLEGAL

L

H

L

BS

X

Precharge

ILLEGAL

Mode

Register

Accessing

L

H

L

Row Address Bank Activate

H

X

Column

Write

L

H

X

Column

Read

H

X

No Operation

Device Deselect

No Operation; Idle after two clock cycles

X

1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is

being applied to.

2. All Banks must be idle; otherwise, it is an illegal action.

3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is

entered.

4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being refer-

enced by the Current State then the action may be legal depending on the state of that bank.

5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.

6. The minimum and maximum Active time (t

) must be satisfied.

RAS

7. The RAS to CAS Delay (t

) must occur before the command is given.

RCD

8. Column address A10 is used to determine if the Auto Precharge function is activated.

9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.

10. The command is illegal if the minimum bank to bank delay time (t

) is not satisfied.

RRD

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Absolute Maximum Ratings

Symbol

Parameter

Rating

Units

V

Notes

V

Power Supply Voltage

Power Supply Voltage for Output

Input Voltage

-0.3 to +4.6

1

DD

V

DDQ

V

-0.3 to V +0.3

V

IN

DD

V

Output Voltage

-0.3 to V +0.3

V

OUT

DD

T

Operating Temperature (ambient)

Storage Temperature

Power Dissipation

0 to +70

-55 to +125

1.0

°C

W

A

T

STG

P

D

I

Short Circuit Output Current

50

mA

OUT

1. Stresses greater than those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Recommended DC Operating Conditions (T_A= 0°C to 70°C)

Rating

Symbol

Parameter

Units

Notes

Min.

3.0

Typ.

3.3

—

Max.

3.6

V

Supply Voltage

V

1

DD

V

Supply Voltage for Output

Input High Voltage

3.0

3.6

1

DDQ

V

2.0

V

+ 0.3

DD

1, 2

1, 3

IH

V

Input Low Voltage

-0.3

—

0.8

IL

1. All voltages referenced to V

and V

.

SSQ

SS

2. V (max) = V

+ 1.2V for pulse width £ 5ns.

DD

IH

3. V (min) = V - 1.2V for pulse width £ 5ns.

IL

SS

Capacitance (T_A= 25°C, f = 1MHz, V_DD= 3.3V ± 0.3V)

Symbol

Parameter

Min.

Typ

3.0

2.8

4.5

Max.

Units

pF

Notes

Input Capacitance (A0-A12, BA0, BA1, CS, RAS, CAS, WE, CKE, DQM)

Input Capacitance (CK)

2.5

4.0

3.8

3.5

6.5

C

I

pF

C

Output Capacitance (DQ0 - DQ15)

pF

O

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

DC Electrical Characteristics (T_A= 0 to +70°C, V_DD= 3.3V ±0.3V)

Symbol

Parameter

Min.

-1

Max.

+1

Units

Notes

1

Input Leakage Current, any input

(0.0V £ V £ V ), All Other Pins Not Under Test = 0V

I

mA

I(L)

IN

DD

Output Leakage Current

(D is disabled, 0.0V £ V

I

-1

2.4

—

+1

—

mA

V

O(L)

£ V )

DDQ

OUT

IOUT

OUT

Output Level (LVTTL)

Output “ H” Level Voltage (

V

OH

= -2.0mA)

= +2.0mA)

Output Level (LVTTL)

Output “ L” Level Voltage (I

V

0.4

V

OL

DC Output Load Circuit

3.3 V

1200W

V

(DC) = 2.4V, I

= -2mA

OH

Output

V

(DC) = 0.4V, I = 2mA

OL

50pF

870W

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Operating, Standby, and Refresh Currents (T_A= 0 to +70°C, V_DD= 3.3V ±0.3V)

Speed

Parameter

Symbol

Test Condition

Units

mA

Notes

-7K

130

-75B

120

-8B

115

1 bank operation

= t (min), t = min

CK

Active-Precharge command cycling with-

out burst operation

t

RC

Operating Current

I

1, 2, 3

CC1

CKE £ V (max), t = min,

IL

C K

I

2

mA

1

CC2P

CS = V (min)

IH

Precharge Standby Current

in Power Down Mode

CKE £ V (max), t = Infinity,

IL

C K

I

CC2PS

CS = V (min)

IH

CKE ³ V (min), t

= min,

IH

CK

I

30

8

30

8

20

8

mA

1, 5

1, 7

1, 5

1, 6

CC2N

Precharge Standby Current

in Non-Power Down Mode

CS = V (min)

IH

CKE ³ V (min), t

= Infinity,

= min,

CC2NS

IH

CK

CKE ³ V (min), t

IH

I

60

6

60

6

45

6

CC3N

CC3P

No Operating Current

(Active state: 4 bank)

CS = V (min)

IH

CKE £ V (max), t = min,

IL

C K

t

= min,

CK

Operating Current (Burst

Mode)

Read/ Write command cycling,

Multiple banks active, gapless data, BL =

4

I

120

90

mA

1, 3, 4

CC4

t

= min, t

= t (min)

RC RC

CK

Auto (CBR) Refresh Current

Self Refresh Current

I

175

155

mA

1

CC5

CC6

CBR command cycling

SP

LP

3

mA

1,8

8

CKE £ 0.2V

1.2

1. Currents given are valid for a single device. .

2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t_CKand t_RC. Input sig-

nals are changed up to three times during t_RC(min).

3. The specified values are obtained with the output open.

4. Input signals are changed once during t_CK(min).

5. Input signals are changed once during three clock cycles.

6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).

7. Input signals are stable.

8. SP : Standard power ; LP : Lower power

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Characteristics (T_A= 0 to +70°C, V_DD= 3.3V ± 0.3V)

1. An initial pause of 200ms, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must

be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation.

2. The Transition time is measured between V_IHand V_IL(or between V_ILand V )

IH

3. In addition to meeting the transition rate specification, the clock and CKE must transit between V_IHand V (or between V_IL

IL

and V_IH) in a monotonic manner.

4. Load Circuit A: AC timing tests have V_IL= 0.4 V and V_IH= 2.4 V with the timing referenced to the 1.40V crossover point

5. Load Circuit A: AC measurements assume t_T= 1.0ns.

6. Load Circuit B: AC timing tests have V_IL= 0.8 V and V_IH= 2.0 V with the timing referenced to the 1.40V crossover point

7. Load Circuit B: AC measurements assume t_T= 1.2ns.

.

AC Characteristics Diagrams

t_T

Vtt = 1.4V

V_IH

50W

Output

t_CKL

t_CKH

1.4V

V_IL

Clock

Input

Z_o= 50W

50pF

t_SETUP

AC Output Load Circuit (A)

t_HOLD

1.4V

Output

Z_o= 50W

t_OH

50pF

t_AC

t_LZ

AC Output Load Circuit (B)

Output

1.4V

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Clock and Clock Enable Parameters

-7 K

-75B

-8B

Symbol

Parameter

Units Notes

Min.

7

Max.

1000

—

Min.

7.5

10

—

Max.

1000

—

Min.

8

Max.

1000

—

t

Clock Cycle Time, CAS Latency = 3

Clock Cycle Time, CAS Latency = 2

Clock Access Time, CAS Latency = 3

Clock Access Time, CAS Latency = 2

Clock Access Time, CAS Latency = 3

Clock Access Time, CAS Latency = 2

Clock High Pulse Width

ns

CK3

CK2

7.5

—

10

—

3

t

—

ns

1

2

AC3 (A)

AC2 (A)

AC3 (B)

AC2 (B)

—

5.4

—

5.4

6

—

6

t

2.5

1.5

0.8

0

2.5

1.5

0.8

0

—

CKH

t

Clock Low Pulse Width

—

3

—

CKL

CES

CEH

t

Clock Enable Set-up Time

—

2

—

Clock Enable Hold Time

—

1

—

t

Power down mode Entry Time

Transition Time (Rise and Fall)

7.5

10

7.5

10

0

10

SB

t

0.5

T

1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.

2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.

Common Parameters

-7K

-75B

-8B

Symbol

Parameter

Units Notes

Min.

1.5

0.8

1.5

0.8

15

Max.

—

Min.

1.5

0.8

1.5

0.8

20

Max.

—

Min.

2

Max.

—

t

Command Setup Time

ns

CS

t

Command Hold Time

—

1

—

CH

t

Address and Bank Select Set-up Time

Address and Bank Select Hold Time

RAS to CAS Delay

—

2

—

AS

AH

—

1

—

t

—

20

70

50

20

1

—

ns

CK

1

RCD

t

Bank Cycle Time

60

—

67.5

45

—

RC

Active Command Period

Precharge Time

45

100K

—

100K

—

100K

—

RAS

t

15

20

RP

t

Bank to Bank Delay Time

CAS to CAS Delay Time

15

—

15

—

RRD

CCD

1

—

1

—

1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:

the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).

Mode Register Set Cycle

-7K

-75B

-8B

Symbol

Parameter

Units

Min.

15

Max.

—

Min.

15

Max.

—

Min.

20

Max.

—

t

Mode Register Set Cycle Time

ns

RSC

38

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Read Cycle

-7K

-75B

-8B

Symbol

Parameter

Units Notes

Min.

—

2.7

0

Max.

—

Min.

—

2.7

0

Max.

—

Min.

2.5

3

Max.

—

6

ns

CK

1

t

Data Out Hold Time

OH

—

2, 4

t

Data Out to Low Impedance Time

Data Out to High Impedance Time

DQM Data Out Disable Latency

—

0

LZ

t

3

5.4

—

3

5.4

6

3

HZ3

t

3

6

HZ2

t

2

—

2

—

DQZ

1. AC Output Load Circuit A.

2. AC Output Load Circuit B.

3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.

4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).

Refresh Cycle

-7K

-75B

-8B

Symbol

Parameter

Units Notes

Min.

—

Max.

64

Min.

—

Max.

64

Min.

—

Max.

64

t

Refresh Period

Self Refresh Exit Time

ms

ns

1

REF

t

10

—

10

—

10

—

SREX

1. 8192 auto refresh cycles.

Write Cycle

-7K

-75B

-8B

Symbol

Parameter

Units

Min.

1.5

0.8

15

Max.

—

Min.

1.5

0.8

15

Max.

—

Min.

2

Max.

—

t

Data In Set-up Time

Data In Hold Time

ns

DS

t

—

1

—

DH

t

Data input to Precharge

—

20

—

DPL

Data In to Active Delay

CAS Latency = 3

t

5

—

5

—

5

—

CK

DAL3

Data In to Active Delay

CAS Latency = 2

t

5

0

—

5

0

—

5

0

—

CK

DAL2

DQW

DQM Write Mask Latency

39

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Clock Frequency and Latency

Symbol

Parameter

-7K

-75B

-8B

Units

MHz

ns

f

Clock Frequency

Clock Cycle Time

CAS Latency

143

7

133

7.5

2

133

7.5

3

100

10

2

125

8

100

10

2

CK

t

C K

t

3

CK

AA

t

Precharge Time

RAS to CAS Delay

Bank Cycle Time

3

2

3

2

3

2

R P

t

3

2

3

2

3

2

RCD

t

9

8

9

7

9

7

RC

t

Minimum Bank Active Time

Data In to Precharge

6

5

6

5

RAS

DPL

DAL

t

2

Data In to Active/Refresh

Bank to Bank Delay Time

CAS to CAS Delay Time

Write Latency

5

t

2

RRD

CCD

1

t

0

WL

t

DQM Write Mask Latency

DQM Data Disable Latency

Clock Suspend Latency

0

DQW

t

2

DQZ

t

1

CSL

40

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Timing Diagrams

Page

AC Parameters for Write Timing..................................................................................................................................42

AC Parameters for Read Timing (3/3/3), BL=4 ...........................................................................................................43

AC Parameters for Read Timing (2/2/2), BL=2 ...........................................................................................................44

AC Parameters for Read Timing (3/2/2), BL=2 ...........................................................................................................45

AC Parameters for Read Timing (3/3/3), BL=2 ...........................................................................................................46

Mode Register Set.......................................................................................................................................................47

Power on Sequence and Auto Refresh (CBR) ............................................................................................................48

Clock Suspension / DQM During Burst Read .............................................................................................................49

Clock Suspension / DQM During Burst Write ............................................................................................................50

Power Down Mode and Clock Suspend......................................................................................................................51

Auto Refresh (CBR).....................................................................................................................................................52

Self Refresh (Entry and Exit) .......................................................................................................................................53

Random Row Read (Interleaving Banks) with Precharge, BL=8.................................................................................54

Random Row Read (Interleaving Banks) with Auto-precharge, BL=8 ........................................................................55

Random Row Write (Interleaving Banks) with Auto-Precharge, BL=8 ........................................................................56

Random Row Write (Interleaving Banks) with Precharge, BL=8.................................................................................57

Read/Write Cycle

...............................................................................................................................................58

Interleaved Column Read Cycle..................................................................................................................................59

Auto Precharge after a Read Burst, BL=4...................................................................................................................60

Auto Precharge after a Write Burst, BL=4...................................................................................................................61

Burst Read and Single Write Operation ......................................................................................................................62

CS Function (Only CS signal needs to be asserted at minimum rate) ........................................................................63

41

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Write Timing

\

42

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (3/3/3)

\

43

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (2/2/2)

\

44

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (3/2/2)

\

45

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

AC Parameters for Read Timing (3/3/3)

\

46

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Mode Register Set

\

47

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Power-On Sequence and Auto Refresh (CBR)

\

48

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Clock Suspension / DQM During Burst Read

\

49

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Clock Suspension / DQM During Burst Write

\

50

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Power Down Mode and Clock Suspend

\

51

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Auto Refresh (CBR)

\

52

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Self Refresh (Entry and Exit)

\

53

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Read (Interleaving Banks) with Precharge

\

54

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Read (Interleaving Banks) with Auto-Precharge

\

55

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Write (Interleaving Banks) with Auto-Precharge

\

56

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Random Row Write (Interleaving Banks) with Precharge

\

57

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Read / Write Cycle

\

58

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Interleaved Column Read Cycle

\

59

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Auto Precharge after Read Burst

\

60

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Auto Precharge after Write Burst

\

61

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Burst Read and Single Write Operation

\

62

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

CS Function (Only CS signal needs to be asserted at minimum rate)

\

63

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Package Dimensions (400mil; 54 lead; Thin Small Outline Package)

22.22 ± 0.13

Detail A

Lead #1

Seating Plane

0.10

+ 0.10

0.35

0.80 Basic

0.71REF

- 0.05

Detail A

Gage Plane

0.25 Basic

0.5 ±0.1

0.05 Min

64

REV 1.0

May, 2001

©

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

®

Nanya Technology Corporation.

©

Printed in Taiwan, R.O.C. May 2001

The following are trademarks of NANYA TECHNOLOGY CORPORATION in R.O.C , or other countries, or both.

NANYA NANYA logo

Other company, product and service names may be trademarks or services maeks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance

of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’ s

standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this

warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government

requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or

environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE

FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such

applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should

be directed to NTC through a local sales office.

In order to minimize risks associated with the customer’ s applications, adequate design and operating safeguards should be

provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents

or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under

any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination,

machine, or process in which such semiconductor products or services might be or are used.

NANYA TECHNOLOGY CORPORATION

HWA YA Technology Park

669, FU HSING 3rd Rd., Kueishan,

Taoyuan, Taiwan, R.O.C.

The NANYA TECHNOLOGY CORPORATION home page can be found at

http:\\www.nanya.com


型号：	NT5SV32M8AT-75B
厂家：	ETC
描述：	256Mb Synchronous DRAM 256Mb的同步DRAM 动态存储器
文件：	总65页 (文件大小：818K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NT5SV32M8AT-75B [ETC]

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