NT68P61A_技术文档

NT68P61A

8-Bit Microcontroller for Monitor (24K OTP ROM Type)

Features

40 pin DIP & 42 pin SDIP package

Operating Voltage Range: 4.5V to 5.5V

CMOS technology for low power consumption

Crystal oscillator or ceramic resonator* available

6502 8-bit CMOS CPU core

Hsync/Vsync signal processor

Hardware sync signals polarity & freq. evaluator

Built-In I²C bus interface

Supporting VESA DDC1/2B function

Six-interrupt sources

8MHz operation of frequency

- INTV (Vsync INT)

24K bytes of OTP (one time programming) ROM

256 bytes of RAM (which stores EDID for DDC1/2B)

One 8-bit pre-loadable base timer

- INTE (External INT with rising edge trigger)

- INTMR(Timer INT )

- INTA (Slave Address Matched INT)

- INTD (Shift Register INT)

14 channels of 8 bit PWM outputs:

6 channel with 5V open drain and 8 channel with 12V

open drain

2 channel A/D converters with 6-bit resolution

24 bi-directional I/O port pins and 1 I/P pin

- INTS (SCL GO-LOW INT)

Hardware watch-dog timer function

Built-In Low Voltage reset circuit (LVRC)

General Description

NT68P61A is a monitor component µC for auto-sync and

Users can store EDID data in the 128 bytes of RAM for

DDC1/2B, so that users can save the cost of dedicated

EEPROM for EDID. Half frequency output function can

save external one-shot circuit. All of these designs create

savings in component costs.

digital controlled applications. It contains

a 6502

8-bit CPU core, 256 bytes of RAM used as working RAM

and stack area, 24K bytes of OTP ROM**, 14-channel 8-

bit PWM D/A converters, 2-channel A/D converters for

key detection saving I/O pins, one 8 bit pre-loadable

base timer, internal Hsync and Vsync signals processor

providing mode detection, watch-dog timer preventing

system from abnormal operation, and an I²C bus

interface. The LVRC enables NT68P61A operate

properly.

* The frequency deviation of ceramic resonator has

+/- 6% maximum.

** The NT6861 (MASK ROM type) will provide

4/8/12/16/24K bytes program ROM.

1

V1.0

NT68P61A

Pin Configuration

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

[OE] DAC2

D A C 1

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

VSYNCI/INTV

HSYNCI

VSYNCI/INTV/ [A14]

[OE] DAC2

D A C 1

2

HSYNCI

D A C 0

3

D A C 0

3

DAC3 [PGM]

DAC4 [MODE0]

DAC5 [MODE1]

N C

DAC3 [PGM]

DAC4 [MODE0]

DAC5 [MODE1]

DAC6 [MODE2]

D A C 7

4

[VPP] RESET

V _DD

[VPP] RESET

V_DD

5

6

N C

G N D

7

G N D

7

DAC6 [MODE2]

DAC7 [A14]

O S C O

OSCI

8

O S C O

P07/HSYNCO [A7]

OSCI

9

P07/HSYNCO [A7]

P06/VSYNCO [A6]

P05/DAC13 [A5]

P04/DAC12 [A4]

P03/DAC11 [A3]

P02/DAC10 [A2]

P01/DAC9 [A1]

P00/DAC8 [A0]

P31/SCL [A13]

P30/SDA [A12]

P20 [DB0]

P06/VSYNCO [A6]

P05/DAC13 [A5]

P15

[CE] P14

10

11

12

13

14

15

16

17

18

19

20

P15

10

11

12

13

14

15

16

17

18

19

20

21

[CE] P14

[A11] P13/HALFHI

[A10] P12/HALFHO

[A9] P11/AD1

[A8] P10/AD0

P16/INTE

[DB7] P27

[DB6]P26

[DB5] P25

[DB4] P24

[DB3] P23

[A11] P13/HALFHI

[A10] P12/HALFHO

[A9] P11/AD1

P04/DAC12 [A4]

P03/DAC11 [A3]

P02/DAC10 [A2]

P01/DAC9 [A1]

P00/DAC8 [A0]

[A8] P10/AD0

P16/INTE

[DB7] P27

[DB6] P26

[DB5] P25

[DB4] P24

[DB3] P23

P31/SCL [A13]

P30/SDA [A12]

P20 [DB0]

P21 [DB1]

P22 [DB2]

* [ ]: OTP Mode

Block Diagram

V

DD

S C L

IIC BUS

OTP Program ROM

24K Bytes

G N D

Timing Generator

SDA

OSCI

DAC0 - DAC7

DAC8 - DAC13

P W M D A C s

O S C O

SRAM

+ STACK

CPU core

6502

256 Bytes

INTE

A/D Converter

AD0 - AD1

VSYNCI/INTV

HSYNCI

Interrupt

Controller

8 Bit Base Timer

P00 - P07

P10 - P15

P16

I/O Ports

LVRC

VSYNCO

H S Y N C O

H/V Sync Signals

Processor

Watch Dog Timer

P20 - P27

P30 - P31

HALFHI

HALFHO

2

NT68P61A

Pin Descriptions

Pin No.

Designation

Reset Init.

I/O

Description

40 Pin

42 Pin

1

DAC2

O

[ I ]

Open drain 12V, D/A converter output 2

[OTP ROM program output enable]

OE

[

]

2

3

4

2

3

4

DAC1

DAC0

O

Open drain 12V, D/A converter output 1

Open drain 12V, D/A converter output 0

I

Schmitt trigger input pin, low active reset**

[OPT ROM program supply voltage]

RESET

[ VPP ]

[ P ]

5

P

Power

DD

V

6

7

8

GND

OSCO

OSCI

P15

P

O

I

Ground

Crystal OSC output

Crystal OSC input

Bi-directional I/O pin

8

9

10

11

I/O

10

P14

[ CE ]

I/O

[ I ]

Bi- directional I/O pin

[OTP ROM program chip enable]

11

12

13

12

13

14

P13/HALFHI

[ A11 ]

P13

P12

P11

I/O

[ I ]

Bi- directional I/O pin, shared with half hsync input

[OTP ROM program address buffer]

P12/HALFHO

[ A10 ]

I/O

[ I ]

Bi- directional I/O pin, shared with half hsync output

[OTP ROM program address buffer]

P11/AD1

I/O

Bi- directional I/O pin, shared with A/D converter channel

1 input

[ A9 ]

[ I ]

I/O

[OTP ROM program address buffer]

14

15

P10/AD0

P10

P16

Bi- directional I/O pin, shared with A/D converter

channel 0 input

[OTP ROM program address buffer]

[ A8 ]

[ I ]

I

15

16

P16/INTE

Schmitt trigger input pin with internal pull high, shared

with external Rising-edge trigger interrupt

16 - 23

17 - 24

P27 - P20

I/O

Bi- directional I/O pin, push-pull structure with high current

drive/sink capability

[ DB7 ] -

[ DB0 ]

[ I/O ] [OTP ROM program data buffer]

24

25

26

25

26

27

P30/SDA

P30

P31

P00

I/O

Open drain 5V Bi-direction I/O pin P30, shared with SDA

pin of I²C bus schmitt trigger buffer

[OTP ROM program address buffer]

[ A12 ]

[ I ]

I/O

P31/SCL

Open drain 5V Bi-direction I/O pin P31, shared with SCL

pin of I²C bus schmitt trigger buffer

[OTP ROM program address buffer]

[ A13 ]

[ I ]

I/O

P00/DAC8

Bi- directional I/O pin, shared with open drain 5V D/A

converter output 8

[ A0 ]

[ I ]

[OTP ROM program address buffer]

* [ ]: OTP Mode

RESET

** This

voltage to reset system all the time.

pin must be pulled high by external pulled-up resistor (5K suggestion), or it will stay low

Ω

3

NT68P61A

Pin Descriptions (continued)

Pin No.

Designation

Reset Init.

I/O

Description

40 Pin

42 Pin

27

28

29

30

31

28

P01/DAC9

P01

I/O

Bi- directional I/O pin, shared with open drain 5V D/A

converter output 9

[OTP ROM program address buffer]

[ A1 ]

[ I ]

I/O

29

30

31

32

P02/DAC10

P02

P03

P04

P05

Bi- directional I/O pin, shared with open drain 5V D/A

converter output 10

[OTP ROM program address buffer]

[ A2 ]

[ I ]

I/O

P03/DAC11

Bi- directional I/O pin, shared with open drain 5V D/A

converter output 11

[OTP ROM program address buffer]

[ A3 ]

[ I ]

I/O

P04/DAC12

Bi- directional I/O pin, shared with open drain 5V D/A

converter output 12

[OTP ROM program address buffer]

[ A4 ]

[ I ]

I/O

P05/DAC13

Bi- directional I/O pin, shared with open drain 5V D/A

converter output 13

[ A5 ]

[ I ]

[OTP ROM program address buffer]

32

33

34

35

36

37

38

33

34

35

36

38

39

40

P06/VSYNCO

[ A6 ]

P06

P07

I/O

[ I ]

Bi- directional I/O pin, shared with vsync out

[OTP ROM program address buffer]

P07/HSYNCO

[ A7 ]

I/O

[ I ]

Bi-directional I/O pin, shared with hsync out

[OTP ROM program address buffer]

DAC7

[ A14 ]

O

Open drain 12V, D/A converter output

[OTP ROM program address buffer]

DAC6

[ MODE2 ]

O

[ I ]

Open drain 12V, D/A converter output

[OTP ROM mode select]

DAC5

[ MODE1 ]

O

[ I ]

Open drain 12V, D/A converter output

[OTP ROM mode select]

DAC4

[ MODE0 ]

O

[ I ]

Open drain 12V, D/A converter output

[OTP ROM mode select]

DAC3

O

[ I ]

Open drain 12V, D/A converter output

[OTP ROM program control]

PGM

[

]

39

40

41

42

HSYNCI

I

Debouncing & schmitt trigger input pin for video horizontal

sync signal, internal pull high, shared with composite sync

input

VSYNCI/INTV

VSYNCI

I

Debouncing & schmitt trigger input pin for video vertical

sync signal, internal pull high, shared with external

interrupt source

[A14]

NC

[ I ]

I/O

-

6

Bi-directional I/O pin, with internal pulled up 22KΩ

resister, only 42 pin SDIP available

37

NC

I/O

Bi-directional I/O pin, with internal pulled up 22KΩ

resister, only 42 pin SDIP available

* [ ]: OTP Mode

4

NT68P61A

Functional Descriptions

1. 6502 CPU

The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true

indexing capability, programmable stack pointer with variable length stack, a wide selection of addressable memory, and

interrupt input options.

The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Refer to 6502 data sheet for more details.

7

0

8

Accumulator A

Index Register Y

Index Register X

15

Program Counter PCH

PCL

7

0

Stack Pointer SP

7

0

C

N

V

B

D

I

Z

Status Register P

Carry

1 = TRUE

1 = Result ZERO

1 = DISABLE

1 = TRUE

Zero

IRQ Disable

Decimal Mode

BRK Command

Overflow

1 = BRK

1 = TRUE

Negative

1 = NEG

Figure 1. 6502 CPU Registers and Status Flags

5

NT68P61A

2. Instruction Set List

Instruction Code

ADC

AND

ASL

Meaning

Add with carry

Operation

A + M + C → A, C

Logical AND

A ^•M → A

Shift left one bit

C ← M7 ^{• • •}M0 ← 0

Branch on C = 0

Branch on C = 1

Branch on Z = 1

BCC

BCS

BEQ

BIT

Branch if carry clears

Branch if carry sets

Branch if equal to zero

Bit test

A ^•M, M7 → N, M6 → V

Branch on N = 1

Branch on Z = 0

Branch on N = 0

Forced Interrupt PC+2 ↓ PC ↓

Branch on V = 0

Branch on V = 1

0 → C

BMI

Branch if minus

BNE

BPL

Branch if not equal to zero

Branch if plus

BRK

BVC

BVS

CLC

CLD

CLI

Break

Branch if overflow clears

Branch if overflow sets

Clear carry

Clear decimal mode

Clear interrupt disable bit

Clear overflow

0 → D

0 →

CLV

0 → V

CMP

CPX

CPY

DEC

DEX

DEY

EOR

INC

Compare accumulator to memory

Compare with index register X

Compare with index register Y

Decrement memory by one

Decrement index X by one

Decrement index Y by one

Logical exclusive-OR

Increment memory by one

Increment index X by one

Increment index Y by one

A − M

X − M

Y − M

M − 1 → M

X − 1 → X

Y − 1→ Y

A

M → A

M + 1 → M

X + 1 → X

Y + 1 → Y

INX

INY

6

NT68P61A

Instruction Set List (continued)

Instruction Code

Meaning

Jump to new location

Jump to subroutine

Operation

JMP

JSR

LDA

LDX

LDY

LSR

NOP

ORA

PHA

PHP

PLA

PLP

ROL

ROR

RTI

(PC+1) → PCL, (PC+2) → PCH

PC + 2 ↓, (P+1) → PCL, (PC+2) → PCH

Load accumulator with memory

Load Index register X with memory

Load Index register Y with memory

Shift right one bit

M → A

M → X

M → Y

0 → M7 ^{• • •}M0 → C

No operation

No operation (2 cycles)

Logical OR

A + M → A

Push accumulator on stack

Push status register on stack

Pull accumulator from stack

Pull status register from stack

Rotate left through carry

Rotate right through carry

Return from interrupt

A ↓

P ↓

A ↑

P ↑

C ← M7 ^{• • •}M0 ← C

C → M7 ^{• • •}M0 → C

P ↑, PC ↑

RTS

SBC

SEC

SED

SEI

Return from subroutine

PC ↑, PC+1 → PC

A − M − C → A, C

1 → C

Subtract with borrow

Set carry

Set decimal mode

1 → D

1 →

Set interrupt disable status

Store accumulator in memory

Store index register X in memory

Store index register Y in memory

Transfer accumulator to index X

Transfer accumulator to index Y

Transfer stack pointer to index X

Transfer index X to accumulator

Transfer index X to stack Pointer

Transfer index Y to accumulator

STA

STX

STY

TAX

TAY

TSX

TXA

TXS

TYA

A → M

X → M

Y → M

A → X

A → Y

S → X

X → A

X → S

Y → A

* Refer to 6502 programming data book for more details.

7

NT68P61A

3. OTP ROM: 24K X 8 bits

The OTP ROM storing application program code, executed by 6502 CPU, has a capacity of 24K X 8 bits, addressed from

$A000 to $FFFF. It is programmed by the universal EPROM writer through a conversion adapter.

In PROGRAMMING mode, OTP ROM is integrated with system and cannot be directly accessed. When using the OTP

RESET

ROM alone, first enter the PROGRAMMING mode by setting:

= VPP.

At this time, through multiplex pins, normal procedures are used to program and verify the OTP ROM block with the

universal programmer.

OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode)

DD

A

(V = 5V , T = 25°C, unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Unit

V

Test Conditions

Note

1

IH

V

DD

V +0.3

V

-0.3

Input Voltage

Input Current

-0.3

0.3

V

IL

V

+/-10

µA

IL

I

-400

1

OH

DD

OH

I

V

=5V, V = 4.5V

Output Voltage

µA

OL

I

V

=5V, V = 0.5V

Operating Current

Standby Current

1

f = 4MHz

2

3

µA

DD

I

ISTB1

100

Notes: 1. All inputs and outputs are CMOS compatible

IH

DD

2. f = 4MHz, Iout = 0mA, CE = V , V = 5V

^IHOE

3. CE = V ,

IL

DD

= V , V = 5V

OTP ROM Mega Cell l A.C. Electrical Characteristics (READ Mode)

DD

A

(V = 5V, T = 25°C, unless otherwise specified)

Symbol

Tcyc

T12

Parameter

Cycle Time

Min.

250

5

Max.

Unit

ns

Conditions

Nonoverlap Time to PH1 & PH2

65

ns

Tacc

Tce

145

ns

Address Access Time

OTPCE to Output Valid

Output Data Setup Time

Output Data Hold Time

DD

4.5V < V < 5.5V

ns

Tst

20

0

ns

Toh

ns

OTP ROM MEGA CELL A.C. Test Conditions

Output Load

1 CMOS Gate and CL = 10pF

10ns Max.

Input Pulse Rise and Fall Times

Input Pulse Levels

0V to 5V

Timing Measurement Reference Level

Inputs 0V and 5V outputs 0.3V and 4.7V

8

NT68P61A

OTP ROM Mega Cell Timing Waveforms (READ Mode)

T12

Tcyc

PH1

PH2

A0 - A14

OTPCE

DB0 - DB7

Tacc & Tce

Tst

Toh

OTP ROM Mega Cell A.C. Electrical Characteristics (PROGRAMMING Mode)

A

°

(T = 25 C, unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

Note

DD

V

Supply Voltage

6

6.5

12.75

DD

V

4

VPP

10.5

2

Input Voltage

IH

V

+0.3

-0.3

0.8

V

IL

V

IIL

Input Current

+/-10

µA

Output Current

-400

1

µA

OH

DD

OH

I

V

= 5V, V = 4.5V

mA

OL

I

V

= 5V, V = 0.5V

Programming

Current

30

20

DD

I

IPP

VPP = 12.75V

DD

Note: 4. For reliability concern, we suggested V = 6V & VPP = 12.75V for test OTP ROM AC characteristics in

PROGRAMMING mode, using the same condition for the universal programmer supply voltage.

9

NT68P61A

OTP ROM Mega Cell D.C. Electrical Characteristics (PROGRAMMING Mode)

A

°

(T = 25 C, unless otherwise specified)

Symbol

Tms

Tmh

Tas

Parameter

Mode Decode Setup Time

Mode Decode Hold Time

Address Setup Time

Address Hold Time

CE Setup Time

Min.

2

Typ.

Max.

Unit

Test Conditions

Note

m

s

2

Tah

2

Tces

Tceh

Tds

2

CE Hold Time

2

Data Setup Time

2

Tdh

Data Hold Time

2

Tvs

VPP Setup Time

2

Tpw

Tdv

Program Pulse Width

100

150

n

s

OE

to Output Valid

Tdf

90

n

s

IL

CE = V

to Output in High-Z

OTP ROM Mega Cell A.C. Test Conditions

Output Load

1 TTL Gate and CL = 100pF

10ns Max.

Input Pulse Rise and Fall Times

Input Pulse Levels

0.45V to 2.4V

Timing Measurement Reference Level

Inputs 0.8V and 2.2V

Outputs 0.8V and 2.4V

DD

PP

Note: 5. V must be applied simultaneously or before VPP and cut off simultaneously or after V

.

PP

6. Removing the device from power or setting the device with V = 12.75V may cause permanent damage

to the device.

10

NT68P61A

OTP ROM Mega Cell Timing Waveforms (PROGRAM Mode)

Tms

Tmh

MODE DEC.

TEST = VPP, MODE [0..2] = 000;

Tvs

VPP

Tas

Tah

A0 - A14

CE

OE

Tceh

Tces

Tdf

DOUT

DB0 - DB7

PGM

D IN

Tdv

Tds

Tpw

Tdh

11

NT68P61A

OTP ROM Mega cell Mode Selection

Mode [0..2]

Mode

CE

VPP

DB0 -

DB7

RESET = 12.75V, OSCI = V^IL,

P16 = V^IH, DAC0 = V^IL

OE

not VPP

VPP

- - -

000

Normal Operating

Output Disable

-

high-Z

IH

V

VPP

000

001

Program

VPP

data in

data out

high-Z

IH

V

Program Verify

IH

V

IL

V

Program Inhibit (Standby)

Security (Program)

-

V_IL

data in

IH

V

VPP

010

011

100

Word-line Stress

Bit-line Stress

-

VPP

-

"0"

OTP Row (after pkg)

data in

IH

V

IH

V

VPP

101

OTP Column (after pkg)

VPP

data in

IH

V

IH

V

* The security byte is at address $0000.

READ

PROGRAM

NT68P61A's OTP ROM mega cell has 2 control pins. CE

(Chip Enable) controls the operation power and is used

Initially, all bits are in "1" state which is the erased state.

The program operation is to introduce "0" data into the

desired bit locations by electrical programming. When

OE

for device selection. The

the output buffers.

(Output Enable) controls

IH

the VPP input is at 12.75V and CE is at V , the chip

enters the PROGRAMMING mode.

OUTPUT DISABLE

PROGRAM VERIFY

OE

IH

If

= V , the outputs will be in a high impedance

state. Two or more ROMs can be connected together on

a common bus.

The VERIFY mode is to check if the desired data is

correctly programmed on the programmed bit. The

IH

VERIFY is accomplished with CE at V , VPP input is at

STANDBY

OE

IL

12.75V, and

= V .

By applying a low power level to the CE input, the chip

enters STANDBY reducing the operating current to

100µA.

PROGRAM INHIBIT

Using this mode, programming of two or more OTP

ROMs in parallel with different data is accomplished. All

OE

inputs except for CE and

may be commonly

connected, and a TTL high level program pulse is

applied to the CE of the desired device only and TTL

high level signal is applied to the other devices.

12

NT68P61A

4. RAM: 256 X 8 bits

256 X 8-bit SRAM is used for data memory and stack. The RAM addressing range is from $0080 to $017F. From $0100 to

$017F is used as the EDID data buffer when activating DDC1/2B mode transmission. The contents of RAM are

undetermined at power-up and are not affected by system reset. Software programmers can allocate stack area in the

RAM by setting stack pointer register S. Because the 6502 default stack pointer is $01FF, programmers must set register

S to FFH when starting the program, so the stack area will map $01FF - $0180 to $00FF - $0080.

as;

LDX

TXS

#$FF

$0000

$0025

$0080

System Registers

Unused

R A M

EDID

stack pointer

$00FF

$0100

$017F

$0180

Unused

$BFFF

$A000

(24K Bytes)

OTP

ROM

$FFFC

$FFFD

$FFFE

$FFFF

RST-L

RESET vector

IRQ vector

RST-H

IRQ-L

IRQ-H

13

NT68P61A

5. System Registers

Addr.

$0000

$0001

Register

PT0

INIT

FFH

7FH

Bit7

P07

-

Bit6

P06

P16

Bit5

P05

P15

Bit4

P04

P14

Bit3

P03

P13

Bit2

P02

P12

Bit1

P01

P11

Bit0

P00

P10

RW

PT1

$0002

PT2DIR

FFH

W

P27OE

P26OE

P25OE

P24OE

P23OE

P22OE

P21OE

P21

P20OE

P20

$0003

$0004

$0005

PT2

PT3

FFH

03H

07H

P27

-

P26

-

P25

-

P24

-

P23

-

P22

-

RW

P31

P30

MD CON

R

S/ C

MD1/ 2

-

INSEN

HSEL

W

$0006

HV CON

2FH HCNTOV

VCNTOV

HSYNCI

VSYNCI

HPOLI

VPOLI

R

HPOLO

HCL1

HCH1

VCL1

VPOLO

HCL0

HCH0

VCL0

W

$0007

$0008

$0009

$000A

HCNT L

HCNT H

VCNT L

VCNT H

00H

HCL7

HCL6

HCL5

HCL4

HCL3

HCH3

VCL3

VCH3

HCL2

HCH2

VCL2

VCH2

R

-

VCL7

-

VCL6

-

VCL4

-

VCL5

-

VCH1

VCH0

$000B

$000C

SYNCON FFH

ENDAC FFH

HALFPOL

W

ENHALF

ENAD0

NOHALF

ENAD1

CEND

FRUN

FRFREQ

ENH

ENV

ENDK13

AD05

ENDK12

AD04

ENDK11

AD03

ENDK10

AD02

ENDK9

AD01

ENDK8

AD00

$000D AD0 REG C0H

R

W

CSTA

$000E AD1 REG 00H

-

AD15

AD14

AD13

AD12

AD11

AD10

R

$000F

IEX

00H

IEINTS

IEINTD

IEINTA

IEINTR

IEINTE

IEINTV

W

14

NT68P61A

System Registers (continued)

Addr.

$0010

$0011

$0012

$0013

$0014

Register

IRQX

INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

00H

-

CLRVOV

1

IRQINTS

IRQINTD

IRQINTA

IRQINTR

IRQINTE

IRQINTV

R

W

CLR FLG

CLR WDT

II ADR

00H CLRHOV

CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV

-

0

1

0

1

0

1

-

W

FFH

00H

AR7

SR7

AR6

AR5

SR5

AR4

SR4

AR3

SR3

AR2

SR2

AR1

SR1

W

II DAT

SR6

SR0

RW

$0015

II STS

08H

-

START

STOP

RXAK

-

R

W

TRX

BT2

-

ENDDC

BT3

$0016

$0017

BT

00H

03H

BT7

-

BT6

-

BT5

-

BT4

-

BT1

TBS

BT0

W

BT CON

-

ENBT

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

$0020

$0021

$0022

$0023

$0024

$0025

DACH0

DACH1

DACH2

DACH3

DACH4

DACH5

DACH6

DACH7

DACH8

DACH9

DACH10

DACH11

DACH12

DACH13

80H

DKVL7

DKVL6

DKVL5

DKVL4

DKVL3

DKVL2

DKVL1

DKVL0

RW

Note: The line above a writable signal name indicate an active low signal

The dash line in these control register indicate an undefined bit

The address of control register from $0026 to $007F are not used.

15

NT68P61A

6. Timing Generator

This block generates the system timing and control signal to be supplied to the CPU and on-chip peripherals. A crystal

quartz, ceramic resonator, or an external clock signal provided to the OSCI pin generates 8MHz system clock,

(4 MHz for CPU), Although internal circuits have a feedback resistor and capacitor included, components may be

externally added to ensure proper operation. The typical clock frequency is 8MHz. This frequency will affect the operation

of on-chip peripherals whose operating frequency is based on the system clock .

OSCI

External Clock

Unconnected

OSCI

8MHz

OSCO

(2)

(1)

NT68P61A

Figure 2. Oscillator Connections

7. A/D Converter

The analog to digital converter is a single 6-bit successive approximation converter. Analog voltage is supplied from

external sources to the A/D input pins and the results of the conversion are stored in the 6-bit data latch registers

($000D & $000E). The A/D converter is controlled by the control bits in the A/D control register ENDAC. Refer to the A/D

channel format table A/D input pins activation. A conversion is started by setting a '0' to the CONVERSION START bit

CSTA

CEND

(

) in the A/D control register ($000D). This automatically sets the CONVERSION END bit (

) to '1'. When a

CEND

conversion has been finished,

($000D & $000E) is valid digital data.

bit automatically clears to '0'. The A/D conversion data in the AD LATCH registers

The analog voltage to be measured should be stable during the conversion operation. The variation should exceed

1/2 LSB for accuracy in measurement. Please refer Figure 3 for checking the linearity of A/D.

A/D Channel Format Table

P11 line

AD1

P10 line

AD0

ENAD1

ENAD0

0

1

0

1

0

1

AD1

P10

P11

AD0

P11

P10

16

NT68P61A

A/D Channel Control Register

Addr.

Register

INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$000C

ENDAC

FFH

W

ENAD1

CEND

ENAD0

ENDK13

AD05

ENDK12

AD04

ENDK11

AD03

ENDK10

AD02

ENDK9

AD01

ENDK8

$000D AD0 REG C0H

$000E AD1 REG 00H

AD00

R

W

CSTA

-

AD15

AD14

AD13

AD12

AD11

AD10

R

Input Voltage Digital Value

0.12

0.37

0.53

0.78

1

0 ($00)

1 ($01)

1.79

2.03

2.27

2.51

2.76

3

23 ($17)

27 ($1B)

30 ($1E)

33 ($21)

36 ($24)

40 ($28)

43 ($2B)

3.5

3.75

3.99

4.22

4.46

4.7

46 ($2E)

49 ($31)

52 ($34)

56 ($38)

63 ($3F)

7 ($07)

10 ($0A)

14 ($0E)

17 ($11)

20 ($14)

1.28

1.54

3.25

4.95

70

60

50

40

30

20

10

0

These digitals have

Linear Range

±1 LSB deviation

V

DD

0

1

0.3

0.7

0.4

0.6

0.8

0.2

Input Voltage

Figure 3. A/D Converter Linearity Diagram

17

NT68P61A

8. PWM DACs (Pulse Width Modulation D/A Converters)

There are 14 PWM D/A converters with 8-bit resolution in NT68P61A. Eight of these D/A (DAC0 - DAC7) converters are

open-drain output structures with 12V applied (maximum), and the other six D/A converters (DAC8 - DAC13) are

open-drain output structures with 5V applied (maximum). The PWM frequency is 31.25 KHz on 8 MHz system clock. Use

of a different oscillator frequency will result in different PWM frequency. As DAC8 - DAC13 are shared with I/O port pins,

user can write '0' to corresponding enable bit in the ENDAC control register to activate each of DACH8 - 13. There are 14-

channel readable DACH registers corresponding to 14 D/A converters. Each PWM output pulse width is programmable by

setting the 8 bit digital to the corresponding DACH registers. When these DACH registers are set to 00H, the DAC will

output LOW (GND level) and each bit addition will add 125ns pulse width. After reset, all DAC outputs are set to 80H (1/2

duty output). Refer to Figure 4 for the detailed timing diagram of PWM D/A output.

8MHz Fosc

255

0

1

2

m

m+1

m+2

255

0

1

PWM value:

00

01

02

m

255 (FF)

Figure 4. The DAC Output Timing Diagram and Wave Table

DKVL7

DKVL6

DKVL5

DKVL4

DKVL3

DKVL2

DKVL1

DKVL0

DAC Output Duty Cycle

GND

0

1

0

1

0

1

0

1

0

1/256 Vref.

2/256 Vref.

3/256 Vref.

4/256 Vref.

-

X /256 Vref.

1

0

1

254/256 Vref.

255/256 Vref.

The DAC value correspondent to PWM output

* Vref. is 12V or 5V

18

NT68P61A

Addr. Register INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$000C

$0018

$0019

$001A

$001B

$001C

$001D

$001E

$001F

$0020

$0021

ENDAC

DACH0

DACH1

DACH2

DACH3

DACH4

DACH5

DACH6

DACH7

DACH8

DACH9

FFH

80H

W

ENAD1

DKVL7

ENAD0

DKVL6

ENDK13

DKVL5

ENDK12

DKVL4

ENDK11

DKVL3

ENDK10

DKVL2

ENDK9

DKVL1

ENDK8

DKVL0

RW

$0022 DACH10 80H

$0023 DACH11 80H

$0024 DACH12 80H

$0025 DACH13 80H

DAC control register ($000C) and DAC value register ($0018 - $0025)

Control Bit Description:

Addr. Register INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$000C

$0018

ENDAC

DACH0

FFH

80H

W

ENAD1

DKVL7

ENAD0

DKVL6

ENDK13

DKVL5

ENDK12

DKVL4

ENDK11

DKVL3

ENDK10

DKVL2

ENDK9

DKVL1

ENDK8

DKVL0

RW

ENDK8

:Enable DAC channel 8; When clearing this bit

to '0', the I/O port, P00, will change to DAC channel 8.

When setting this bit to '1', the I/O port will

restore to P00.

ENDK9

ENDK13

-

: The manipulation is the same as

ENDK8

bit, and control DAC channel 9 - 13.

DACH0 (DKVL0 - DKVL7): Setting DAC output waveform

of DAC channel 8. Please check Figure 3 for the timing

diagram

and wave table.

DACH1 - DACH13: The manipulation is the same as

DACH0 register, and control DAC channel 1 - 13.

19

NT68P61A

9. RESET

RESET

This

pin must be pulled high by external pulled-

up resistor (5KΩ suggestion), or it will stay low voltage to

reset system all the time.

NT68P61A can be reset by the external reset pin or by

the internal watch-dog timer. This resets or starts the

microcontroller from a power-down condition. During the

time that this reset pin is held low (*reset line must be

held low for at least two CPU clock cycles), writing to or

from the µC is inhibited. When positive edge is detected

on the reset input, the µC will immediately begin reset

sequence.

After a system initialization time of six CPU clock cycles,

the mask interrupt flag will be set and the µC will load the

program counter from the memory vector locations

$FFFC and $FFFD. This is the start location for program

control. To improve noise immunity a Schmitt Trigger

10. Watch-dog timer (WDT) and Low Voltage

Reset Circuit (LVRC)

NT68P61A implements a watch-dog timer reset to avoid

system shut-down or malfunction. The clock of the WDT

is from on-chip RC oscillator not requiring any external

components. The WDT runs regardless if the clock of the

OSCI/OSCO pins of the device has been stopped. The

WDT time interval is about 0.5 second. The WDT must

be cleared within every 0.5 second when software is in

normal sequence, otherwise the WDT will overflow and

cause reset. The WDT is cleared and enabled after

system is reset. It cannot be disabled by software. Users

can clear the WDT by writing 55H to CLRWDT register.

RESET .

buffer is provided at the

Reset status is as follows:

1. PORT0 PORT1. PORT2. PORT3 pins will act as

I/O ports with HIGH output.

2. Sync processor counters reset and VCNT | HCNT

latches cleared

NT68P61A will check voltage level of power supply.

When the voltage level of power supply is below a

threshold of 4.0V, the LVRC will issue a reset output to

the chip. After the power supply is restored to 4.0V and

above, the LVRC will keep reset signal low for 10mS and

then restore to high voltage. A power glitch of pulse

width less than 1µs will be ignored and no reset will

occur. This allows the µC enter the reset state in a good

condition. Refer to Figure 5 for the timing diagram.

3. All sync outputs are disabled

4. Base timer is disabled and cleared

5. A/D converter is disabled and stopped

6. DDC1/2B function is disabled

7. PWM DAC0 - DAC7 output 50% duty

waveform and DAC8 - DAC13 is disabled

8. Watch-dog timer is cleared and enabled

as;

LDA

STA

#$55

$0012

Addr.

$0012

Register

INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

CLR WDT

-

0

1

0

1

0

1

0

1

W

Vcc = 5.0 V

4.0 V

G N D

Hold 10 mS

System Reset

Figure 5. LVR Reset Timing Diagram

20

NT68P61A

11. Interrupt Controller

external pins (INTV & INTE), base timer overflow (INTR),

SCL line go-low (INTS), and serial bus interrupt (INTA &

INTD). The serial bus interrupt is generated by the I²C

circuit as described in under I²C bus interface sections.

The interrupt enable (IEX) bit will effects the interrupt

process if the IRQX has already been set. Once IEX bit

is set, its corresponding interrupt will generate an

interrupt source for 6502 CPU. The IRQX will be set no

matter the IEX bit enable or not. The interrupt request is

generated when IRQX and IEX are both '1'. The IRQX

remains in HIGH state unless the CLRIRQ register is

cleared (write '1' to correspondent bit in CLRIRQ

register). The interrupt enable register (IEX) and interrupt

request register (IRQX) are memory mapped registers

which can only be accessed or tested by program. These

registers are cleared to '0' at initialization after the chip is

reset .

The µC will complete the current instruction being

executed before recognizing the interrupt request. At this

time, the interrupt mask bit in the status register will be

examined. If the interrupt mask bit is not set, µC will

begin interrupt sequence. The program counter and

processor status register are stored in the stack. µC will

then set the interrupt mask flag HIGH so that no further

interrupts occur. At the end of this cycle, the program

counter will be loaded from addresses $FFFE & $FFFF,

transferring program control to the memory vector

located at these addresses.

Six interrupt sources are available in this system:

- INTV INT (Vsync INT): Rising edge of every Vsync

pulse

- INTE INT (External INT): Rising edge of external

interrupt pulse

When interrupt occurs, CPU jumps to $FFFE & $FFFF to

execute interrupt service routine and finds which one of

the interrupt sources is active by checking the IRQX.

Upon entering the interrupt service routine, the IRQX that

caused the interrupt service must be cleared in the

interrupt service routine program. CPU clears IRQX by

writing '1' to the corresponding bit in CLRIRQ register. If

more than one interrupt is pending and waiting to be

served, each is executed by priority. Priority is defined by

the programmer.

- INTMR INT (Timer INT): As the Base Timer counter

overflow and counting from $FF to $00

- INTA INT (Address Matched INT): External device

calling NT68P61A in DDC2 mode communication

- INTD INT (Shift Register INT): Shift register is

empty or receiving a new byte data in DDC1 & DDC2

mode communication

- INTS INT (SCL Go-Low INT): External device

proceed a DDC2 communication

Three memory mapped registers are used to control the

interrupt operation. The IRQX is set by the rising edge of

Control bit description:

ADDR. REGISTER INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$000F

$0010

$0011

IEX

IRQX

00H

-

IEINTS

IRQINTS

IEINTD

IRQINTD

IEINTA

IRQINTA

IEINTR

IRQINTR

IEINTE

IRQINTE

IEINTV

IRQINTV

W

R

CLR FLG

00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV

W

IRQINTS is the interrupt flag for SCL- At DDC2B TRANSMISSION mode, it is set when SCL line changes from '1' to '0'.

IEINTS enable 6502 interrupt for INTS. - When this bit is set to '1' and IRQINTS flag is set, 6502 will accept interrupt

source and jump to interrupt service routine assigned by interrupt vector.

CLRINTS clears INTS interrupt flag. - Before returning from interrupt service routine, this flag must be cleared.

The manipulation of other interrupt source is the same as INTS.

CLRHOV & CLRVOV: Clear the overflow flag of H/V counter and reset H/V counter to zero.

21

NT68P61A

P00 - P05 are shared with DAC8 - DAC13 respectively. If

12. I/O PORTs

ENDK8

ENDK13

LOW in ENDAC register,

user sets

P00 - P05 will act as DAC8 - DAC13 respectively

ENDK ENDK13

-

NT68P61A has 25 pins dedicated to input and output.

These pins are grouped into 4 ports .

(Figure 7). After the chip is reset,

enter HIGH state and P00 - P05s will act as I/O ports.

-

will

12.1. Port0: P00 - P07

Port0 is an 8-bit bi-directional CMOS I/O port with PMOS

as internal pull-up (Figure 6). Each pin of Port0 may be

bit programmed as an input or output port without the

software controlling the data direction register. When

Port0 works as output, the data to be output is latched to

the port data register and output to the pin. Port0 pins

that have '1's written to them are pulled high by the

internal PMOS pull-ups. In this state they can be used as

input, then the input signal can be read. This port outputs

high after reset .

P06, P07 are shared with VSYNCO & HSYNCO

ENH ENV

to low in SYNCON

respectively. If user sets

register, P06, P07 will act as VSYNCO & HSYNCO

ENH

,

respectively (Figure 8). After the chip is reset,

,

ENV

pins.

, will enter high state and P06, BP07 will act as I/O

Addr.

Register

INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$0000

PT0

FFH

P07

P06

P05

P04

P03

P02

P01

P00

R

W

$000B SYNCON FFH

$000C ENDAC FFH

-

HALFPOL

ENDK10

W

FRFREQ

ENDK11

NOHALF

ENAD1

ENHALF

ENAD0

FRUN

ENH

ENV

ENDK13

ENDK12

ENDK9 ENDK8

P W M

Output

Vcc

P W M

Data In

I/O

Figure 7. PWM Output Structure

V c c

Data Out

O / P

Data In

Data Out

Figure 6. I/O Structure

22

NT68P61A

Figure 8. Output Structure

23

NT68P61A

12.2. Port1: P10 - P16

Port10-Port15 are 6-bit bi-directional CMOS I/O ports

with PMOS as the internal pull-up (Figure 6). Port16 is

an input pin only. Each bi-directional I/O pin may be bit

programmed as an input or output port without software

controlling the data direction register. When Port1 works

as output, the data to be output is latched to the port

data register and output to the pin. Port1 pins that have

'1's written to them are pulled high after reset.

P12, P13 are shared with half signals input and output

pins by accessing SYNCON control register. If user

ENHALF

clears the

bit to low, P13 will switch to HALFHI

pin (input pin) and P12 will switch to HALFHO pin

(output pin, Figure 8). Refer to half frequency function in

the H/V sync processor paragraph concerning HALFHI &

ENHALF

HALFHO pin. After the chip is reset, the

bits

will enter HIGH state and P12, P13 will act as I/O pins.

P10, P11 are shared with AD0 & AD1 input pins

P16 has a Schmitt Trigger input buffer (Figure 9) and is

shared with the external interrupt pin if set the IEINTE bit

in IEX control register. Refer to 'Interrupt Controller'

section above for function details.

ENADX

respectively. If user clears the

bit in the ENDAC

control register to low, A/D converters will activate

ENADX

simultaneously. After the chip is reset,

HIGH state and P10, P11 act as I/O pins.

bits enter

Addr.

$0001

$000C

Register

PT1

INIT

7FH

FFH

Bit7

-

Bit6

P16

Bit5

P15

Bit4

P14

Bit3

P13

Bit2

P12

Bit1

P11

Bit0

P10

RW

W

ENDAC

ENAD1

CEND

ENAD0

ENDK13

AD05

ENDK12

AD04

ENDK11

AD03

ENDK10

AD02

ENDK9

AD01

ENDK8

AD00

$000D AD0 REG C0H

R

W

CSTA

$000E AD1 REG 00H

-

AD15

AD14

AD13

AD12

AD11

AD10

R

$000F

IEX

00H

IEINTS

IEINTD

IEINTA

IEINTR

IEINTE

IEINTV

W

V c c

Vcc

Data Out

.

I/O

I/P

Data OE

Data Input

Data In

Figure 9. Schmitt Input Structure

Figure 10. I/O Structure

24

NT68P61A

12.3. Port2: P20 - P27

Port2, an 8-bit bi-directional I/O port (Figure 10), which may be programmed as an input or output pin by the software

control. When setting the PT2DIR control bit to '0', its corresponding pin will act as output pin. Clearing PT2DIR bit to '1',

acts as an input pin. When programmed as an input, it has an internal pull-up resistor. When programmed as an output,

the data to be output is latched to the port data register and output to the pin with push-pull structure. If programmed as an

output pin, user can read out its correspondent control bit about what user has written before. If programmed as an input

pin, user can read out what the I/O pin status outside. This port acts as an input port after reset.

Addr.

Register INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$0002

$0003

PT2DIR

PT2

FFH

W

P27OE

P27

P26OE

P26

P25OE

P25

P24OE

P24

P23OE

P23

P22OE

P22

P21OE

P21

P20OE

P20

RW

12.4. Port3: P30 - P31

Port3 is an 2 bit bi-directional open-drain I/O port (Figure 11). Each pin of Port3 may be bit programmed as an input or

output pin with open drain structure. When Port3 works as an output, the data to be output is latched to the port data

register and output to the pin. For Port3 pins that have '1's written to them, user must connect PORT3 with external pulled-

up resistor and then PORT3 can be used as input (the input signal can be read). This port outputs high after reset .

P30, BP3 include Schmitt Trigger buffer for noise immunity and can be configured as the I²C pins SDA & SCL respectively.

ENDDC

If set

to LOW in IISTS control register, P30, P31 will act as SDA, SCL respectively. After the chip is reset,

ENDDC

will be in HIGH and PORT3 will act as I/O pins.

Addr.

$0004

$0015

Register

PT3

INIT

03H

0FH

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

P31

Bit0

-

P30

RW

II STS

START

STOP

RXAK

R

W

TRX

ENDDC

I/O

Data Out

Data In

Figure 11. Open Drain I/O Structure

25

NT68P61A

13. H/V Sync Signals Processor

The functions of the sync processor include polarity

VCNTOV bit (in HVCON register) to HIGH (see Figure

14). Once the VCNTOV sets to HIGH, it keeps in HIGH

state unless cleared by CLRVOV bit (in CLRFLG

register) to HIGH. When user clears the CLRVOV bit, the

VCNT counter will be reset to zero and begin to count

again.

detection,

Hsync

&

Vsync

signals

counting,

programmable sync signals output, free running signal

generator and composite sync separation. The processor

properly handles either composite or separate sync

signal inputs as well as no sync signal input. The input at

HSYNCI can be either a pure horizontal sync signal or a

composite sync signal. For the sync waveform refer to

Figures 12 and 13.

The sync processor block diagram is shown in

Figure 17. Both VSYNCI & HSYNCI pins have a Schmitt

Trigger and filtering process to improve noise immunity.

Any pulse that is shorter than 125ns will be regarded as

a glitch and will be ignored.

Hsync counter: HCNTL/H, the other 12-bit read only

register pairs contain the numbers of Hsync pulse

between two Vsync pulses (see Figure 15), and the data

can be read to determine if the frequency is valid and to

HSEL

determine the VIDEO mode. If the

HIGH, the internal counter counts the Hsync pulses

HSEL

bit sets to

between two Vsync pulses. If the

bit clears to

LOW, the internal counter will be reset and begin

counting the Hsync pulses in each 8.192ms interval (see

Figure 16). The counted value will be latched by the

HCNTL/H register pairs which are updated by every

Vsync pulse or 8.192ms interval. If the counter

overflows, the HCNTOV bit (in HVCON register) will be

set to HIGH. Once the HCNTOV sets to HIGH, it remains

in the overflow HIGH state unless cleared by CLRHOV

(in CLRFLG register) to HIGH. When user clears the

CLRHOV bit, the HCNT counter will be reset to zero.

13.1. V & H Counter Register: VCNTL/H, HCNTL/H

Vsync counter: VCNTL/H, the 12-bit read only register,

contains information of the Vsync frequency. An internal

counter counts the numbers of 8µs pulse between two

Vsync pulses. When the next Vsync signal is recognized,

the counter is stopped and the VCNT register latches the

counter value. The counted data can be converted to the

time duration between two successive Vsync pulses by

8µs. If no Vsync comes, the counter will overflow and set

(a) Positive polarity

(b) Negative polarity

Figure 12. Separate H Sync. Waveform

(a) Positive Polarity

(b) Negative Polarity

Figure 13. Composite H Sync. Waveform

26

NT68P61A

Latch VCNT register

Reset V sync. counter

Start pulse counting

Latch VCNT register

Reset V sync. counter

Start pulse counting

VSYNCI

Sampling Clock

8

µ

s

Figure 14. Vsync Counter Operation

Latch HCNT register

Reset H sync. counter

Start pulse counting

Latch HCNT register

Reset H sync. counter

Start pulse counting

VSYNCI

HSYNCI

Figure 15. Hsync Counter Operation Using Vsync Pulse

Latch HCNT register

Reset H sync. counter

Start pulse counting

Latch HCNT register

Reset H sync. counter

Start pulse counting

HSEL = Low

8.192 ms

HSYNCI

Figure 16. Hsync Counter Operation Using 8.192ms Time Interval

27

NT68P61A

VCNTL

VCNTH

Control

Logic

Enable

V

sync.

Latch

S/C

Enable

Reset

8

µ

s

VSYNC

INPUT

Schmitt

Trigger

Digital

Filter

V

sync.

V

1

0

counter

HSEL

8.192 ms

0

1

Enable

Reset

H

sync.

counter

Enable

H

Latch

sync.

H

Sync.

& V

H

HSYNC

INPUT

Digital

Filter

Polarity

Detector

Schmitt

Trigger

Sync

Separator

HCNTL

HCNTH

HPOLO

HPOLI

H

Sync.

HSYNCO

Output

H

Control

FREE_RUN

Control

S/C

VPOLI

V

Sync.

Output

Control

V

0

1

VSYNCO

VPOLO

Figure 17. Sync. Processor Block Diagram

28

NT68P61A

13.2. Sync Processor Control Register:

Composite sync: User has to determine whether the

incoming signal is separate sync or composite sync and

bits in the HVCON register, '1' represents positive

polarity and '0', negative polarity.

C

HSEL

bit properly. If composite sync signal

set S/

&

Sync output: In pin assignment, VSYNCO & HSYNCO

represent Vsync & Hsync output which are shared with

C

is input, after set S/ to '0', the sync separator block will

be activated ( please refer figure 18). During Vsync pulse

the Hsync will be inserted Hsync pulse by hardware

circuit and the pulse width of inserted pulse is 2µs fixed.

According to the last Hsync pulse outside the Vsync

pulse duration, the hardware will arrange the interval of

these hardware interpolated pulse. So the insertion of

these Hsync pulse will be continued inside the Vsync

pulse duration no matter what the Hsync pulse originally

exist or not. These inserted Hsync pulse have 0.5µs

phase deviation maximum. The Vsync pulse can be

extracted by hardware from composite signal, and the

output of Vsync signal delay time will be limited bellow

20ns. For inserting Hsync pulse safely, the extracted

Vsync pulse will be widen about 9µs. Because evenly

putting the Hsync pulse, the last inserted Hsync pulse

will have different frequency from original ones.

ENV

ENH

to '0' in

P06 & P07 respectively. If set

&

SYNCON register, P06 & P07 will act as VSYNCO &

HSYNCO pin. When input sync is separate signal, the

V/HSYNCO will output the same signal as input sync

signal without delay. But if input sync is composite

signal, the VSYNCO signal will have a delay time of

about 4µs to 8µs. The HSYNCO has no delay output and

still has Vsync pulse among Hsync pulse (i.e. the signal

on HSYNCI pin directly output to HSYNCO pin.)

FRUN

Free run signal output: The user can set

to '0' bit

in SYNCON register, then VSYNCO will output 61Hz

Vsync signal and HSYNCO will output 62.5KHz Hsync

signal default (Refer to Figure 20). When FRFREQ bit

clears to '0', the HSYNCO pin will output 41.7 KHz Hsync

signal. The free run signal has negative or positive

polarity depending on the HPOLO & VPOLO bit setting in

the HV_CON control register, '1' is positive and '0' is

System will not implement this insertion function, user

INSEN

must clear

bit in the MD_CON control register to

activate this function.

ENV , ENH ,

negative polarity. After chip reset,

FRFREQ

FRUN

I/O pins.

&

will enter HIGH state and P06 & P07 will act as

HSEL

C

INSEN

& bits default value

After reset, the

, S/

is HIGH and clear the VCNT | HCNT counter latches to

zero.

Half frequency input and output: In this pin assignment,

ENHALF sets to

when

'0' in SYNCON register, the

Polarity: The detection of Hsync or Vsync polarity is

achieved by hardware circuits sample the sync signal's

voltage level periodically. The user can read HPOLI &

VPOLI bit in HVCON register, from which bit = '1'

representing positive polarity and '0', negative polarity.

The user can read HSYNCI and VSYNCI bit in HVCON

register to detect H & V sync input signal. The user can

control the polarity of H & V sync output signal by

writing the appropriate data to the HPOLO and VPOLO

HALFHO pin will act as an output pin and output half of

input signal in the HALFHI pin with 50% duty

NOHALF

(Refer to Figure 21). If

sets to '0', HALFHO will

output the same signal in the HALFHI pin and user can

control its polarity output of HALFHO by setting

HALFPOL bit, '1' for positive and '0' for negative polarity.

ENHALF , NOHALF

After chip reset,

in the HIGH state and P13 & P17 will act as I/O pins.

& HALFPOL will be

29

NT68P61A

(1) HSYNCI

(2) HSYNCI

Composite H sync. waveform (H EOR V)

Composite H sync. waveform (H OR V)

No matter Hsync pulse existing or not,

the output signal of Hsync will be inserted.

2 s

µ

HSYNCO

Original

Hsync Pulse

Original

Hsync Pulse

Inserted Hsync Pulse

VSYNCO

Widen 9 s

µ

Figure 18. Composite H & V Sync. Processing

30

NT68P61A

Sync. Mode

Processing

Set S/C

Clear VCNTOV

=

&

'0'

System Default:

Freq.

Calculating

HCNTOV

S/C

=

'1'

& HSEL = '1'

Open INTV

& clear INTV flag

Open INTV

&

clear INTV flag

Set S/C

=

'1'

&

HSEL

= '0'

Clear VCNTOV

&

HCNTOV Delay 10ms

No

INTV

?

1. Extract VCNTL/H 12 bit data

2. HSEL

12 bit data

Vsync. time duration

= '1'

Delay 60ms

Yes

X

8µs

=

Yes

Off Mode

HCNTH

=

'00'

No

3. Its reciprocal

is Vsync. freq.

Delay 31 ms

?

4. HSEL

12 bit data

Vsync. freq.

= '0'

X

8.192ms

=

Yes

Suspend Mode

Yes

VCNTOV

= '1'

VCNTOV

?

= '1'

?

No

STAND-BY Mode

Yes

No

1. Extract HCNTL/H 12 bit data

2. 12 bit data Vsync. freq.

Hsync. freq.

3. Its reciprocal

is Hsync. time duration.

HCNTH

?

=

'00'

No

*

Worng Mode

Yes

=

HCNTH ='00'

?

NORMAL Mode

Seperate Sync.

No

Read VCNT|HCNT

Counter Register

Read VCNT|HCNT

Counter Register

Return

NORMAL Mode

Composite Sync.

Freq.

Calculating

Return

Figure 19. H & V Sync. Software Control Flowchart (for reference only)

31

NT68P61A

61Hz

Pulse width 64

s

µ

(a) Free run output Vsync. signal

(1) 62.5KHz

(2) 41.7KHz

Pulse width 1

s

µ

(b) Option 2 of free run output Hsync. signal

Figure 20. Free Running Sync. Waveform

HALFHI

HALFHO: Half freq. output signal (50% duty)

HALFHO output signal when NOHALF bit clears to LOW

(the same signal as in the HALFHI pin)

Figure 21. Half Freq. Sync. Waveform

32

NT68P61A

13.3. Power Saving Mode Detect:

The VIDEO mode is listed below. Power saving is from mode 2 to mode 4. All modes can be detected by setting the

control register properly. Refer to Figure 15 control flow chart for software reference.

Mode

(1) Normal

H-Sync

Active

V-Sync

Active

(2) Stand by

(3) Suspend

(4) Off

Inactive

Active

Inactive

Control bit description:

Addr.

Register INIT

Bit7

Bit6

Bit5

Bit4

Bit3

-

Bit2

-

Bit1

Bit0

$0005

MD CON 07H

-

R

S/ C

MD1/ 2

W

HSEL

INSEN

$0006

HV CON 2FH HCNTOV

VCNTOV

HSYNCI

VSYNCI

HPOLI

VPOLI

R

HPOLO

HCL1

HCH1

VCL1

VPOLO

HCL0

HCH0

VCL0

W

$0007

$0008

$0009

$000A

HCNT L

HCNT H

VCNT L

VCNT H

00H

HCL7

HCL6

HCL5

HCL4

HCL3

HCH3

VCL3

VCH3

HCL2

HCH2

R

-

VCL7

-

VCL6

-

VCL4

-

VCL5

VCL2

R

-

VCH2

VCH1

VCH0

R

$000B SYNCON FFH

HALFPOL

W

NOHALF

ENHALF

CLRVOV

FRUN

FRFREQ

ENH

ENV

$0011 CLR FLG 00H CLRHOV

CLRINTS CLRINTD CLRINTA

CLRINTR

CLRINTE CLRINTV

W

MDCON control register:

HSYNCI & VSYNCI:User can instantaneously detect

input of H & V Sync pulse at any

time.

HPOLI & VPOLI:The polarity of input H & V Sync pulse

- '1' for positive polarity and '0' for

negative polarity.

HPOLO & VPOLO:To control the output polarity of H & V

Sync pulse - '1' for positive polarity

and '0' for negative polarity.

C

S/ : The SYNC MODE control. If the input of V & H

Sync are separate signals, set this bit to

'1' (system default). If the input is composite

signal, clear this bit. Under the COMPOSITE

mode,

NT68P61A will extract the V Sync form H Sync

signal.

HSEL

: When clearing this bit, system will reset

HCNTL|H counter to zero. The number of Hsync

pulse at the 8.192ms interval is obtained.

HCNTL|H & VCNTL|H control registers:

The 12 bits counter for H & V Sync pulse.

SYNCON control register:

INSEN :

User can clear this bit for inserting Hsync pulse

when processing the composite signal. System

will disable this function after reset.

ENH

ENV

&

: Enable the output of H & V Sync. The P06

& P07 will switch to VSYNCO & HSYNCO

output.

HVCON control register:

HCNTOV: The overflow bit of H Sync. After setting

FRUN

: Open free run signal at the VSYNCO & HSYNCO

output.

HSEL

bit

'1' without any input Vsync pulses and

there are more than 4096 Hsync pulses

coming ,this bit will be set. It will keep '1' and

user can clears it by setting CLRHOV bit to '1'

at the CLRFLG control register. After cleared,

the H Sync counter will reset to '0' and start

counting for every Hsync pulse.

FRFREQ :Select the free run frequency of H Sync

output.

ENHALF

: P12 & P13 will switch to HALFHO & HALFHI

pin. The HALFHO will output the half signal at

the HALFHI pin with 50% duty.

NOHALF

pin.

ENHALF

:User must clear first. The HALFHO

will output the same signal at the HALFHI

VCNTOV: The overflow bit of V Sync. The operation is

the same as HCNTOV. After cleared, the

Vsync counter will reset to '0' and start

counting for every 8µs.

ENHALF

HALFPOL: User must clear

the

first and control

33

NT68P61A

polarity at the HALFHO output pin - '1' for

positive polarity and '0' for negative polarity.

14. BASE TIMER (BT)

The Base Timer is an 8-bit counter whose clock source must be chosen with 1µs or 1ms by setting or clearing the TBS bit

ENBT

('0' for 1µs and '1' for 1ms). The BT can be enabled/disabled by the

this control bit to '0', the BT will start counting, otherwise setting this bit to '1' will stop the counting. After chip is reset, the

ENBT

bit in the BTCON register. When user clearing

TBS and

bits are set to '1' (the BT is disabled). BT, can be preset by writing BT7 - BT0 to the BT register (write

only) at any time and the BT will start count-up from preset value. When the value reaches FFH, it generates a timer

interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and

begin counting at 00H. The timer interval can be within 256 ms maximum if set TBS to '1'. The timer interval can be within

256µs maximum if set TBS to '0'.

1 s

µ

0

BT7

BT6

BT5

BT4

BT3

BT2

BT1

BT0

TMR INT

1

1ms

TBS

Control bit description:

Addr. Register

INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$0016

BT

00H

BT7

BT6

-

BT5

-

BT4

-

BT3

-

BT2

BT1

BT0

W

$0017 BT CON

03H

-

TBS

ENBT

BT control register :

BT0 - BT7: Preloaded value of the base timer. The timer will count-up from this value.

BTCON control register:

ENBT

: When clearing this bit, the base timer will be activated.

TBS: Select the input clock source of base timer - '1' for 1ms and '0' for 1µs.

34

NT68P61A

15. I²C Bus Interface: DDC1 & DDC2B Slave Mode

I²C bus interface is a two-wire, bi-directional serial bus which provides a simple, efficient way for data communication

between devices. Its structure minimizes the cost of connecting various peripheral devices. In short, the wired-AND

connection of all I²C interface to I²C bus is the most important structure. Two modes of operation have been implemented

2

in NT68P61A: UNI-DIRECTIONAL mode (DDC1 mode) and BI-DIRECTIONAL mode (DDC2B mode). If the MD1/ bit is

2

set to '1', the device will operate in the DDC1 mode, and if the MD 1/ bit is cleared to '0', the device will operate in the

DDC2B mode. All of these I²C functions will be activated only when

bus

bit clears to '0' (in IISTS register). When I²C

ENDDC

function is activated, the P30 & P31 will switch to SCL & SDA pin. System works on the DDC1 mode transmission default.

The SCL pin will remain high and SDA will transfer one bit of data at every rising edge of Vsync pulse.

SCL

VSYNC

0

Shift Register (IIDAT)

SDA

clock source

1

MD1/2

15.1. DDC1 Bus Interface

Vsync input and SDA pin: In DDC1 data transfer, the

Vsync input pin is used as an input clock for data

transmission and SDA output pin, as serial data line.

This function comprises of two data buffers: one is a

preloaded data buffer for user placing one bit of data in

advance, and one is shift register for system shifting out

one bit of data to the SDA pin. These two data buffer

cooperate properly. Refer to Figure 18. After system

reset, the I²C bus interface is in DDC1 mode.

INTD interrupt to remind user to replace next byte data

into IIDAT register. After eight rising clocks, there are

eight bits shifted out in proper order and the shift register

becomes empty again. At the ninth rising clock, it will

shift the ninth bit (null bit '1') out to SDA. And on the next

rising edge of Vsync clock, system will generate a INTD

interrupt again. NT68P61A will also load new data in the

IIDAT register to internal shift register and shift out one

bit immediately. User must input new data to IIDAT

register properly before the shift register is empty (the

next INTD interrupt).

Data transfer: In advance, put one byte transmitted data

into IIDAT register and activate I²C bus by setting

Vsync clock: In the separate sync signal, the Vsync pulse

is used as a data transfer clock. Its frequency allows

25KHz maximum. If no Vsync input signal is found,

NT68P61A can not transmit any data to SDA pin

regardless what the Vsync has extracted from composite

Hsync signal.

ENDDC

bit to '0' and open INTD interrupt source by

setting IEINTD to '1'. On the first 9 rising edge of Vsync,

system will shift out any invalid bit in shift register to

SDA pin to empty shift register. When shift register is

empty and on next rising edge of Vsync, it will load data

in the IIDAT register to internal shift register. At the same

time, NT68P61A will shift out MSB bit and generate an

35

NT68P61A

Control bit description:

Addr. Register INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

-

$0005 MD CON 07H

-

R

W

S/ C

MD1/ 2

HSEL

INSEN

$000F

$0010

IEX

00H

-

IEINTS

IEINTD

IEINTA

IEINTR

IEINTE

IEINTV

W

IRQX

IRQINTS

IRQINTD

IRQINTA

IRQINTR

IRQINTE

IRQINTV

R

$0011 CLR FLG 00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV

W

$0014

$0015

II DAT

II STS

00H

08H

SR7

-

SR6

-

SR5

SR4

SR3

SR2

SR1

SR0

RW

START

STOP

RXAK

-

R

W

TRX

TXAK

ENDDC

MDCON control register:

2

MD1/ : Select the DDC mode - '1' for DDC1 and '0' for DDC2B mode. System will be DDC1 mode by default.

When transmission mode is changed form DDC1 to DDC2B, system automatically clears this bit.

IEX control register:

At DDC1 mode, only open INTD interrupt, as well as open INTS interrupt to detect if has changed to DDC2B mode.

II_DAT control register: Data buffer for transmission.

II_STS control register:

ENDDC

: When clearing this bit, system will activate DDC transmission. P30 & P31 will switch to SDA & SCL pin.

ENDDC

(in IISTS register)

Vsync Pulse

9

1

2

3

4

5

6

7

8

9

1

2

1

2

3

4

INTV

Load data in the IIDAT register to shift register

INTD

User can load next byte data to IIDAT register

Null

Bit

Null

Bit

8

7

6

SDA

1

8

7

6

5

4

3

2

1

8

5

Invalid data

7

Second Byte Data

Shift

register

8

7

6

5

4

3

2

1

MSB

LSB

First Byte Data

Figure 22. DDC1 Mode Timing Diagram

36

NT68P61A

15.2 DDC2B Slave Mode Bus Interface

The DDC2B I²C Bus Interface features are as follows:

- SLAVE mode (NT68P61A addressed by a master

which drive SCL signal)

generating a INTS interrupt and switch to DDC2B mode

2

automatically. When user sets MD1/ to '1' at this time,

the NT68P61A will still proceed with DDC1

a

- Fully compatible with I²C bus standard

- Interrupt and generation of acknowledge handled by

user for communication

communication. The DDC2B bus consists of two wires,

SCL and SDA; SCL is for the data transmission clock

and SDA is for the data line. Data transfers follow the

format shown in Figure 19. The standard communication

of I²C bus protocol includes four parts: a START signal,

slave ADDRESS, transferred data (proceed byte by byte)

and a STOP signal. In the wired-AND connection, any

slow devices can hold the SCL line LOW to force the fast

device into a wait state until the slow device is ready for

the next bit or byte transfer in a type of handshake

procedure.

- Interrupt driven byte by byte data transfer

- Calling address identification interrupt

- Detection of START and STOP signals

Enable I²C and INTS: The NT68P61A included the use in

applications requiring storage and serial transmission of

configuration and control information. User can place

address data into IIADR register and set IEINTS to '1' (in

IEX register) in advance. In the DDC1 mode (after

ENDDC

clearing

to '0') and when the low level on the

SCL pin occurs, NT68P61A will remind user by

S T O P

CONDITION

START

CONDITION

S D A

8

9

8

9

8

9

1

-

7

1 - 7

1

- 7

S C L

A D D R E S S

R / W

A C K

D A T A

A C K

D A T A

A C K

IIDAT Reg.

bit stream

4

A C K

8

7

6

5

1

8

7

6

5

4

3

2

1

8

7

A C K

M S B

L S B

M S B

Figure 23. DDC2B Data Transfer

37

NT68P61A

Start condition: When SCL & SDA lines are in HIGH

state, an external device (master) may initiate

communication by sending a START signal (defined as

SDA from high to low transition while SCL is in high

state). When there is a START condition, NT68P61A will

set the 'START' bit to '1' and user can poll this status bit

to control DDC2B transmission at any time. This bit will

keep '1' until user clears it. After sending a START signal

for DDC2B communication, an external device can

repeatedly send start conditions without sending a STOP

signal to terminate this communication. This is used by

the external device to communicate with another slave or

with the same slave in different mode (READ or WRITE

mode) without releasing the bus.

Data validity and transfer: The data on the SDA line mu

be stable during the HIGH period of the clock on the SCL

line. The HIGH and LOW state of the SDA line can only

change when the clock signal on the SCL line is LOW.

Each byte data is eight bits long and one clock pulse for

one bit of data transfer. Data is transferred with the most

significant bit (MSB) first. If a receiver (external device or

NT68P61A) cannot receive another complete byte of

data until it has performed some other function, for

example servicing an internal interrupt, it can hold the

clock line SCL LOW to force the transmitter into a wait

state. Data transfer then continues when the receiver is

ready for another byte of data and release clock line

SCL. Each byte data is followed by an acknowledge bit.

Address matched and INTA: After the START condition,

a slave address is sent by external device. When I²C bus

interface changes to DDC2B mode, NT68P61A will first

act as a receiver to receive this one byte data. This

address data is 7 bits long followed by the eighth bit that

Acknowledge: The acknowledgment will be generated at

ninth clock by whom receive data. In the WRITE mode,

NT68P61A

system

must

respond

to

this

acknowledgment. After receiving one byte data from

external device, NT68P61A will automatically send an

acknowledgment by pulling SDA line to 'LOW'. In the

READ MODE, external device must respond to this

acknowledgment and at every byte data sent, user can

read RXAK bit in IISTS register to check if external sent

a ACK or not.

W

indicates the data transfer direction (R/ ). When

NT68P61A system receives address data from external

device, it will store if in IIDAT register. System support

'A0' address by default and another one set of DDC2

address for user. When user enable DDC2 function, the

system will compare address data getting from external

device with the default address 'A0' and data in the

$0013 II_ADR control register written by user. Either of

these address matched, the system will generate an

INTA interrupt flag and this DDC2 communication will be

continued. If user sets IEINTA bit to '1' in advanced and

address data matched, the NT68P61A system will

generate a INTA interrupt. Under the address matching

condition, the NT68P61A will send an acknowledgment

to external device. If address data not matched, the

NT68P61A will not generate INTA interrupt and not care

the data change on SDA line in the future.

The INTD interrupt: After NT68P61A receive the START

condition, it will generate an INTD interrupt at the falling

edge of the ninth clock. User can control the flow of

DDC2B transmission at this INTD interrupt.

The INTD on the WRITE mode: NT68P61A read data

from external device. At INTD interrupt, the SCL will be

hold LOW by NT68P61A. When getting one byte data

from II_DAT register, user can write '00' into II_DAT

register and the SCL will be released. External device

can continue sending next byte data to NT68P61A.

Refer to Figure 24.

Data Transmission direction: At INTA interrupt servicing

routine, user must check the LSB of address data in

IIDAT register. According to I²C bus protocol, this bit

indicates the DDC2B data transfer direction in later

transmission - a '1' indicates a request for 'READ

MODE' action (external read data from system); a '0'

indicates a 'WRITE MODE' action (external write data to

system). For READ mode and WRITE mode timing

diagram refer to Figure 24 and 25. The data transfer can

be proceeded byte by byte in a direction specified by the

The INTD on the READ mode: External device read data

from NT68P61A. At INTD interrupt, the SCL will be hold

LOW by NT68P61A. User can check RXACK bit in the

IISTS register whether external device has sent an ACK

or not after one byte data transfer. If external device has

sent an ACK, the RXACK will be '0' (assume the

acknowledgment is LOW signal). When user puts one

new byte data into II_DAT register, the SCL will be

released for generation of SCL transmission clock. The

next byte data will be shifted out properly. Refer to

Figure 25.

W

R/

bit after a successful slave address is received.

User must set TRX bit in the IISTS register for

NT68P61A transmission mode - '1' for READ mode and

'0' for WRITE mode.

38

NT68P61A

STOP condition: When SCL & SDA lines have been

released (remain in 'HIGH' state), DDC2B data transfer

is always terminated by a STOP condition generated by

external device. A STOP signal is defined as a low to

high transition of SDA while SCL is in HIGH state. When

there is a STOP condition, NT68P61A will set the 'STOP'

bit to '1' and user can poll this status bit to control

DDC2B transmission at any time. This bit keeps '1' until

user clears it. Notice the SCL and SDA lines must

conform to I²C bus specifications. (Refer to Figure 26).

Refer to the standard I²C bus specification for details.

Changing to DDC1 mode: After an external device

2

terminates DDC2 transmission, set MDI/

to 1 for

changing to DCC1 mode. When the SCL line has been

released (pulled-up), user can force NT68P61A to DDC1

mode communication at any time. This function is

supporting the 'error' recovery protocol in the VESA DDC

standard Ver 2.0.

Control bit description:

Addr. Register INIT

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

$0005 MD CON 07H

R

W

-

S/ C

MD1/ 2

HSEL

INSEN

$000F

$0010

IEX

00H

-

IEINTS

IEINTD

IEINTA

IEINTR

IEINTE

IEINTV

W

IRQX

IRQINTS

IRQINTD

IRQINTA

IRQINTR

IRQINTE

IRQINTV

R

$0011 CLR FLG 00H CLRHOV CLRVOV CLRINTS CLRINTD CLRINTA CLRINTR CLRINTE CLRINTV

W

$0013

$0014

$0015

II ADR

II DAT

II STS

FFH

00H

08H

AR7

SR7

-

AR6

SR6

-

AR5

SR5

AR4

SR4

AR3

SR3

AR2

SR2

AR1

SR1

-

SR0

-

W

RW

START

STOP

RXAK

R

W

TRX

ENDDC

MDCON control register:

II_ADR control register: User can define the address of

DDC2B device. If an external

device sends the same address

data as this control register

(calling NT68P61A), NT68P61A

will generate an INTA interrupt.

2

MD1/ : Select the DDC mode - '1' for DDC1 and '0' for

DDC2B mode. System will be DDC1 mode by

default.

When transmission mode is changed form

DDC1 to DDC2B, system will automatically

II_STS control register:

clear

this bit.

ENDDC

: When clearing this bit, the system will activate

DDC transmission. P30 and P31 will switch to

SDA and SCL pin.

IEX control register:

In DDC2 mode, user use INTS, INTA & INTD interrupt

and II_STS control register to control DDC2B

transmission.

TRX: In the READ mode of DDC2B transmission, user

must set this bit '1'.

RXAK: In the WRITE mode of DDC2B transmission,

after

II_DAT control register: Data buffer for transmission

one byte has been sent out to the SDA line,

there will be an INTD interrupt. At INTD interrupt

service routine, user can check this bit to see if

external device has responded to NT68P61A.

39

NT68P61A

S

NT68P61A Address

R / W

A

D A T A

A

D A T A

A

P

Data transferred

from external device

0

From external device to NT68P61A

A

S

P

=

acknowledge

START

STOP

From NT68P61A to external device

(a) WRITE_Mode Data Format

wait

S C L

R / W

S T O P

S T A R T

S D A

1

0

1

0

(external device)

D A T A

INTS

INTA

I NT D

S D A

(NT68P61A)

A

(b) WRITE_Mode Timing Diagram

Figure 24. DDC2B Write_Mode Spec

.

40

NT68P61A

A

D A T A

A

P

S

NT68P61A Address

R / W

D A T A

A

Data transferred

from external device

1

From external device to NT68P61A

A

=

acknowledge

no acknowledge

From NT68P61A to external device

(a) Read_Mode Data Format

wait

S C L

R / W

S T O P

S T A R T

S D A

(external device)

1

0

1

0

1

INTS

INTA

I NT D

S D A

(NT68P61A)

A

D A T A

(b) READ_Mode Timing Diagram

Figure 25. DDC2B Read_Mode Spec

.

41

NT68P61A

Interrupt Service Routine

Polling

No

Need

Polling

INTS

Need

Polling

INTD

Need

Polling

INTA

Need

Polling

INTV

Need

Polling

INTR

Main Program

?

yes

Open

INTV INTS

No

&

No

INTA

?

INTV

?

INTS

?

INTD

?

INTR

?

yes

DDC1

DDC2

yes

Set ENDDC

= 0

Reset EDID Buffer Index

From IIDAT Reg.

LSB

To Decide

Write/Read Mode

Change To

DDC2 Mode

Change To

DDC1 Mode

MD_CON = 1

DDC2B

Write_Mode

Operation

?

No

DDC1

Transfer

?

MD 1/2

=

0

(Auto Switch)

yes

DDC2B

Read_Mode

Operation

Wait Interrupt

or

Doing something

Reset EDID

Buffer Index

Put One Byte

Data Into

Read One Byte

Data From

IIDAT Reg.

To Set EDID

Buffer Index

From EDID

Buffer Index

Put One Byte

Data Into

Put Addr.

Into

IIADR Reg.

DDC2B

No

Other INT.

Service

Write_Mode

Operation

?

IIDAT Reg.

From EDID

Buffer Index

Put One Byte

Data Into

yes

Open

Setting IISTS:

Write '00'

To IIDAT

For releasing SCL

Setting IISTS:

TRX

(Trans. Mode)

INTS

& INTD

TRX

= 0

IIDAT Reg.

Setting IISTS:

TRX

=

1

(Recv. Mode)

=

0

(Recv. Mode)

NO

DDC2 Idle

For Sec.

2

?

No

Put First Byte

Data Into

IIDAT Reg.

For releaseing SCL

For Transfer data

DDC2 Operate

Open

INTA INTR

Over

?

Write '00'

To IIDAT

For releasing SCL

INTS

& INTD

&

yes

&

Return To

DDC1 Mode

Open INTV

Reset EDID

Buffer Index

Open

INTA

& INTD

Open

& INTV

INTA

& INTD

INTA

Return

Figure 26. DDC1/2B Software Flow Chart

42

NT68P61A

Absolute Maximum Ratings*

*Comments

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of

this device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied or intended. Exposed to the absolute

maximum rating conditions for extended periods may

affect device reliability.

DD

SS

DC Supply Voltage V - V . . . . . . . . . . . .-0.3V to 7V

CC

Input Voltage . . . . . . . . . . . . . . GND -0.2V to V +0.2V

Operating Temperature . . . . . . . . . . . . . . . . 0°C to

+70°C

Storage Temperature . . . . . . . . . . . . . . . -50°C to

+125°C

DD

A

DC Electrical Characteristics (V = 5V, T = 25°C, oscillator freq. = 8MHz, unless otherwise specified)

Symbol

Parameter

Min Typ. Max Unit

Conditions

.

Operating Current

20

mA No loading

DD

I

VIH1

Input High Voltage

2

3

V

P00 - P07, P10-P16, P20-P27, P30, P31,

RESET ,

VSYNCI, HSYNCI, HALFHI, INTE

VIH2

VIL1

Input High Voltage

Input Low Voltage

V

SCL, SDA pins

0.8

P00 - P07, P10 - P16, P20 - P27, P30, P31,

RESET ,

VSYNCI, HSYNCI, HALFHI, INTE

VIL2

IIH

Input Low Voltage

Input High Current

1.5

V

SCL, SDA pins

-200 -350

P00 - P07, P10 - P16 ,P20 -P27, VSYNCI,

µA

RESET

HSYNCI, HALFHI,

(VIH = 2.4V)

VOH1 Output High Voltage

2.4

V

OH

P00 - P07, P10 - P15 (I = -100µA)

OH

VSYNCO, HSYNCO (I = -4mA)

OH

HALFHO (I = -4mA)

OH

P20-P27 (I = -10mA)

VOH2 Output High Voltage (DAC8 -

DAC13)

5

V

external applied voltage

VOH3 Output High Voltage (DAC0 - DAC7)

12

V

external applied voltage

VOL

Output Low Voltage

0.4

OL

P00 - P07, P10 - P15, DAC0 - 13 (I

=

OL

4mA) SCL/P30, SDA/P31 (I = 5mA)

OL

VSYNCO, HSYNCO (I = 4mA)

OL

HALFHO (I = 4mA)

OL

P20 - P27 (I = 10mA)

VLVR

ROL

Low Voltage Threshold

4.0

V

25K 50K 75K

Ω

RESET )

Pull Down Resistor (

ROH1 Pull Up Resistor (INTE)

11K 22K 33K

Ω

ROH2 Pull Up Resistor (PORT0 & PORT1)

ROH3 Pull Up Resistor (HSYNCI &

VSYNCI)

43

NT68P61A

DD

A

AC Electrical Characteristics(V = 5V, T = 25°C, oscillator freq. = 8MHz, unless otherwise specified)

Symbol

Parameter

Min.

Typ.

Max.

Unit

MHz

µs

Condition

Fsys

System Clock

8

A/D Conversion Time

375

CNVT

t

Voffset

Vlinear

A/D Converter Offset Error

39

mV

Vin = 2V for A/D converter

A/D Input Dynamic Range of Linearity

Conversion

0.3

0.7

DD

V

tinst

tdev

The Inserted Hsync Pulse Width

2

Composite sync

(Refer Figure 18)

µs

The time deviation at the end edge of

inserted Hsync pulse

250

ns

Composite mode &

insertion function activated

Reset Pulse Width Low

2

32

8

RESET

CYCLE

t

= 2/Fsys

Fvsync

Vsync Input Frequency

25K

300

120

7

Hz

VSYNC

HSYNC

= 1/Fvsync

Vsync Input Pulse Width

µs

VPW

t

Fhsync

Hsync Input Frequency

30

0.5

8

KHz

t

= 1/Fhsync

Hsync Input Pulse Width High

Hsync Input Pulse Width Low

Counting Deviation of Base Timer

µs

HPW1

t

Composite sync

HPW2

t

1

µs

1µs clock source

ERROR1

t

ms

1ms clock source

ERROR2

t

44

NT68P61A

DDC1 Mode

Symbol

Parameter

Vsync High Time

Min.

0.5

Typ.

Max.

300

25K

500

Unit

us

Condition

VPW

t

Fvsync

Vsync Input Frequency

Data Valid

32

Hz

ns

VSYNC

t

= 1/Fvsync

200

DD

t

Time for Transition to DDC2B

Mode

ns

MODE

t

SCL

t_MODE

t_DD

SDA

Bit 0

Null Bit

Bit 7

Bit 6

VSYNC

t_VPW

Composite

Hsync Input

HPW2

t

HPW1

t

Extracted

Vsync Output

(no loading)

45

NT68P61A

DDC2B Mode

Symbol

Parameter

SCL Clock Frequency

Min.

Typ.

Max.

Unit

KHz

µs

fSCL

100

Bus Free Between a STOP and START Condition

Hold Time for START Condition

LOW Period of the SCL Clock

4.7

4

t^BUF

t^HD; STA

t^LOW

µs

ns

4.7

4

HIGH Period of the SCL Clock

t^HIGH

Set-up Time for a Repeated START Condition

Data Hold Time

4.7

300

t^SU; STA

t^HD; DAT

t^SU; DAT

t^R

Data Set-up Time

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

Set-up Time for STOP Condition

1

µs

ns

µs

300

F

t

4

t^SU; STO

SDA

t_BUF

t

F

t

LOW

t

R

t

^HD; STA

SCL

^SU; STA

t_HD; STA

t_HD; DAT

t_SU; DAT

t_SU; STO

t

HIGH

STOP

START

STOP

START

46

NT68P61A

Ordering Information

Part No.

Package

NT68P61A

40L DIP

47

NT68P61A

Package Information

DIP 40L Outline Dimensions

unit: inches/mm

D

40

21

1

20

E

S

Base Plane

Seating Plane

B

e

A

α

e

1

B

1

Symbol

Dimensions in inches

0.210 Max.

Dimensions in mm

5.33 Max.

A

A₁

A₂

0.010 Min.

0.25 Min.

0.155±0.010

3.94±0.25

B

B₁

C

0.018 +0.004

-0.002

0.46 +0.10

-0.05

0.050 +0.004

-0.002

1.27 +0.10

-0.05

0.010 +0.004

-0.002

0.25 +0.10

-0.05

D

E

2.055 Typ. (2.075 Max.)

0.600±0.010

52.20 Typ. (52.71 Max.)

15.24±0.25

E₁

e₁

L

0.550 Typ. (0.562 Max.)

0.100±0.010

13.97 Typ. (14.27 Max.)

2.54±0.25

0.130±0.010

3.30±0.25

0 ~ 15

° °

α

°

e_A

S

0.655±0.035

0.093 Max.

16.64±0.89

2.36 Max.

Notes:

1. The maximum value of dimension D includes end flash.

1

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

48


型号：	NT68P61A
厂家：	ETC
描述：	8-Bit Microcontroller for Monitor (24K OTP ROM Type) 8位微控制器监视器（ 24K OTP ROM类型）微控制器监视器 OTP只读存储器
文件：	总48页 (文件大小：1057K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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