NT68P81-D01014 [ETC]
USB Keyboard Micro-Controller; USB键盘微控制器
| 型号： | NT68P81-D01014 |
| 厂家： | 
ETC |
| 描述： | USB Keyboard Micro-Controller |
| 文件： | 总30页 (文件大小：1002K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NT68P81
USB Keyboard Micro-Controller
n3 LED direct sink pins with internal serial resistors
Features
nBuilt-in 6502C 8-bit CPU
n3 MHz CPU operation frequency when oscillator is nOn-chip oscillator (Crystal or Ceramic Resonator)
running at 6 MHz
n6K bytes of OTP (one time programming) ROM
n256 bytes of SRAM
nWatch-dog timer reset
nBuilt-in power-on reset
nUSB interface
nOne 8-bit programmable base timer with pre-divider n3 supported endpoints
circuit nRemote wakeup provided
n29 programmable bi-directional I/O pins including two nCMOS technology for low power consumption
external interrupts
n40-pin DIP package, 42-pad Dice form and COB
General Description
The NT68P81 is a single chip micro-controller for USB
keyboard applications. It incorporates a 6502C 8-bit
CPU core, 6K bytes of OTP ROM, and 256 bytes of RAM
used as working RAM and stack area. It also includes 29
programmable bi-directional I/O pins with built-in
resistors, and one 8-bit pre-loadable base timer.
Additionally, it includes a built-in power-on reset, a built-
in low voltage reset, an oscillator that requires crystal or
ceramic resonator applied, and a watch-dog timer that
prevents system standstill.
Pin Configuration
Pad Configuration
P
1
P
1
P
1
P
1
P
1
P
1
P
0
P
0
P
0
5
4
3
2
1
0
7
6
5
GND
VCP
1
40
39
38
37
OSCI
25
24
23
22
21
20
19
18
17
2
OSCO
VDP
3
VDD
16
15
P04
268
P16
P17
VDM
4
LED2 [MODE2]
LED1 [MODE1]
LED0 [MODE0]
P03
P02
27
28
[OE] P30
[PGM] P31
INT0/P32
INT1/P33
P34
5
36
35
34
33
32
31
30
29
28
27
14
13
P20
P21
6
P01
29
7
P27 [DB7]
P26 [DB6]
P25 [DB5]
12
11
P00
8
P22
P23
30
31
NT68P81
RESET
9
10
P34
P33
[VPP] RESET
[A0] P00
10
11
12
13
14
15
16
17
18
19
20
P24 [DB4]
P23 [DB3]
P22 [DB2]
P21 [DB1]
P20 [DB0]
P17
32
33
P24
P25
9
8
P32
P31
P30
[A1] P01
[A2] P02
[A3] P03
[A4] P04
34
35
P26
P27
7
6
LED0
LED1
36
37
26
25
1
4
5
[A5] P05
[A6] P06
[A7] P07
[A8] P10
[A9] P11
P16
39
40
3
38
41
42
2
24
23
P15 [CE]
P14 [A12]
P13 [A11]
P12 [A10]
L
E
D
2
V
C
C
V
C
C
O
S
C
O
S
C
I
G
N
D
G
N
D
V
C
P
V
D
P
V
D
M
22
21
O
1
V2.0
NT68P81
Block Diagram
VCP
VDP
VDM
OSCI
Transceiver
SIE
Power Down/Up
Timing Generator
OSCO
6K Bytes
OTP ROM
6502
CPU
Serial Bus
Manager
256 Bytes
SRAM
Interrupt
Controller
FIFOs
Watch Dog
Timer
LED0
VDD
GND
LED1
Power-On
Reset
LED2
P00~P07
P10~P17
P20~P27
P30~P34
I/O PORTs
RESET
Base Timer
2
NT68P81
Pin and Pad Descriptions
Pin No.
Pad No.
Designation
GND
I/O
P
Shared with OTP[I/O]
Description
1
2
3
4
1,2
3
Ground
VCP
O
USB 3.3V driver
USB data plus
4
VDP
I/O
I/O
5
VDM
USB data minus
Bi-directional I/O pin
5
6
6
7
P30
P31
I/O
I/O
Program output enable
Bi-directional I/O pin
Program control
OE [I]
PGM [I]
7
8
9
8
9
P32/INT0
P33/INT1
P34
I/O
I/O
I/O
Bi-directional I/O shared with INT0
Bi-directional I/O shared with INT1
Bi-directional I/O pin
10
I
Internally pulled down resistor
RESET
P00 ~ P07
P10 ~ P14
P15
10
11
VPP [P]
A0 ~ A7 [I]
A8 ~ A12
CE [I]
Program supply voltage
Bi-directional I/O pin
Program address buffer
Bi-directional I/O pin
Program address buffer
Bi-directional I/O pin
Program chip enable
Bi-directional I/O pin
OTP Program Input Voltage High
Bi-directional I/O pin
Bi-directional I/O pin
Program data buffer
LED direct sink
I/O
I/O
I/O
I/O
11 ~ 18
19 ~ 23
24
12 ~ 19
20 ~ 24
25
P16
25
26
VPIH[I]
26
27
P17
I/O
I/O
P20 ~ P27
27 ~ 34
28 ~ 35
DB0 ~ DB7 [I/O]
MODE0 [I]
LED0
LED1
LED2
O
O
O
35
36
37
36
37
38
Mode selection
LED direct sink
MODE1 [I]
Mode selection
LED direct sink
MODE2 [I]
Mode selection
38
39
39,40
41
VDD
P
Power supply (+5V)
Crystal oscillator output
Program Clock
OSCO
O
CLK[I]
3
NT68P81
OSCI
I
Crystal oscillator input
OTP Program Input Voltage Low
40
42
VPIL[I]
* [ ]: OTP Mode
4
NT68P81
Functional Description
1. 6502C CPU
The 6502C is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory
range, and an interrupt input. Other features are also included.
The CPU clock cycle is 3MHz (6MHz system clock divided by 2). Please refer to 6502 data sheet for more detailed
information.
7
7
7
0
0
0
8
Accumulator A
Index Register Y
Index Register X
15
Program Counter PCH
PCL
7
7
0
0
Stack Pointer SP
7
0
N
V
B
D
I
Z
C
Status Register P
Carry
1 = TRUE
Zero
1 = Result ZERO
1 = DISABLE
1 = TRUE
IRQ Disable
Decimal Mode
BRK Command
Overflow
Negative
1 = BRK
1 = TRUE
1 = NEG
Figure 1. 6502 CPU Registers and Status Flags
5
NT68P81
2.Instruction Set List
Instruction Code
Meaning
Add with carry
Logical AND
Operation
ADC
AND
ASL
BCC
BCS
BEQ
BIT
A + M + C → A，C
A‧ M → A
Shift left one bit
C ← M7‧ ‧ ‧ M0 ← 0
Branch on C＝0
Branch on C＝1
Branch on Z＝1
A‧ M，M7 → N，M6 → V
Branch on N＝1
Branch on Z＝0
Branch on N＝0
Forced interrupt PC + 2↓ PC↓
Branch on V＝0
Branch on V＝1
0 → C
Branch if carry clear
Branch if carry set
Branch if equal to zero
Bit test
BMI
BNE
BPL
BRK
BVC
BVS
CLC
CLD
CLI
Branch if minus
Branch if not equal to zero
Branch if plus
Break
Branch if overflow clear
Branch if overflow set
Clear carry
Clear decimal mode
Clear interrupt disable bit
Clear overflow
0 → D
0 → I
CLV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
0 → V
Compare accumulator to memory
Compare with index register X
Compare with index register Y
Decrement memory by one
Decrement index X by one
Decrement index Y by one
Logical exclusive-OR
Increment memory by one
Increment index X by one
Increment index Y by one
Jump to new location
Jump to subroutine
A － M
X － M
Y － M
M － 1 → M
X － 1 → X
Y － 1 → Y
A ⊕ M→A
M + 1 → M
INX
X + 1 → X
INY
Y + 1 → Y
JMP
JSR
(PC + 1) → PCL，(PC + 2) → PCH
PC + 2↓，(PC + 1) → PCL，(PC + 2) → PCH
6
NT68P81
Instruction Set List (contiuned)
Instruction Code
Meaning
Operation
LDA
LDX
LDY
LSR
Load accumulator with memory
Load index register X with memory
Load index register Y with memory
Shift right one bit
M → A
M → X
M → Y
0 → M7‧ ‧ ‧ M0 → C
NOP
ORA
No operation
Logical OR
No operation (2 cycles)
A + M → A
PHA
PHP
PLA
PLP
ROL
ROR
RTI
Push accumulator on stack
Push status register on stack
Pull accumulator from stack
Pull status register from stack
Rotate left through carry
A ↓
P ↓
A ↑
P ↑
C ← M7‧ ‧ ‧ M0 ← C
C → M7‧ ‧ ‧ M0 → C
P ↑，PC ↑
PC ↑，PC+1 → PC
A － M － C → A，C
1 → C
Rotate right through carry
Return from interrupt
RTS
SBC
SEC
SED
SEI
Return from subroutine
Subtract with borrow
Set carry
Set decimal mode
1 → D
Set interrupt disable status
Store accumulator in memory
Store index register X in memory
Store index register Y in memory
Transfer accumulator to index X
Transfer accumulator to index Y
Transfer stack pointer to index X
Transfer index X to accumulator
Transfer index X to stack pointer
Transfer index Y to accumulator
1 → I
STA
STX
STY
TAX
TAY
TSX
TXA
A → M
X → M
Y → M
A → X
A → Y
S → X
X → A
TXS
X → S
TYA
Y → A
*For more detailed specifications, please refer to 6502 programming data book.
7
NT68P81
3. OTP ROM: 6K X 8 bits
The built-in OTP ROM program code, executed by the 6502 CPU, has a capacity of 6K x 8-bit and is addressed from
E800H to FFFFH. It can be programmed by the universal EPROM writer through a conversion adapter and programming
configuration such as INTEL - 27C64. In the OPERATING mode, the OTP ROM is integrated with the system and it cannot
be directly accessed. When the user wants to work with the OTP ROM alone, the user must first enter the
PROGRAMMING mode by setting: PIN < RESET = VPP>. At this time, through multiplex pins, we can use familiar
procedures to program and verify the OTP ROM block with the universal programmer.
OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode)
(VDD = 5V, TA = 25℃, unless otherwise specified)
Symbol
Parameter
Min.
VDD - 0.3
-0.3
Typ.
Max.
VDD + 0.3
0.3
Unit
V
Test Conditions
Note
V
IH
Input Voltage
1
1
V
IL
V
IIL
IOH
Input Current
+/-10
µA
µA
mA
mA
µA
Output Voltage
-400
1
VDD = 5V, VOH = 4.5V
VDD = 5V, VOL = 0.5V
F = 3MHz
IOL
IDD
Operating Current
Standby Current
1
2
3
ISTB1
100
Note:
1. All inputs and outputs are CMOS compatible
2. F = 3MHz, lout = 0mA, CE = V . VDD = 5V
IH
3. CE = V , OE = V , VDD = 5V
IH
IL
OTP ROM Mega Cell A.C. Electrical Characteristics (READ Mode)
(VDD = 5V, TA = 25℃, unless otherwise specified)
Symbol
Tcyc
Parameter
Min.
Max.
Unit
ns
Conditions
Cycle Time
250
5
T12
Non-overlap Time to PH1 & PH2
Address Access Time
65
ns
Tacc
Tce
145
145
ns
4.5V < VDD < 5.5V
OTPCE to Output Valid
Output Data Setup Time
Output Data Hold Time
ns
Tst
20
0
ns
Toh
ns
OTP ROM Mega Cell A.C. Test Conditions
Output Load
1 CMOS Gate and CL = 10pF
10ns Max.
Input Pulse Rise and Fall Times
Input Pulse Levels
0V to 5V
Timing Measurement Reference Level
Inputs 0V and 5V Outputs 0.3V and 4.7V
8
NT68P81
OTP ROM Mega Cell Timing Waveforms (READ mode)
T12
Tcyc
PH1
PH2
A0 - A14
OTPCE
DB0 - DB7
Tacc & Tce
Tst
Toh
OTP ROM Mega Cell D.C. Electrical Characteristics (PROGRAMMING Mode)
(VDD = 5V, TA = 25℃, unless otherwise specified)
Symbol
VDD
Parameter
Min.
Typ.
Max.
6.5
Unit
V
Test Conditions
Note
Supply Voltage
6
4
VPP
10.5
2
12.75
VDD + 0.3
0.6
V
V
IH
Input Voltage
V
V
IL
-0.3
V
IIL
IOH
Output Current
Output Current
+/-10
μA
μA
mA
mA
mA
MHz
V
-400
1
VDD = 5V, VOH = 4.5V
VDD = 5V, VOL = 0.5V
IOL
IDD
Operating Current
30
20
IPP
VPP = 12.75V
CLK
VPIH
VPIL
Input Clock
53.203424
Input Voltage
2
VDD + 0.3
-0.3
0.6
V
9
NT68P81
Note: 4. For reliability concerns, we suggest V = 6V & VPP = 12.75V for testing OTP ROM AC characteristics in
DD
PROGRAMMING mode, and the same condition is suggested for universal programmer supply voltage.
OTP ROM Mega Cell A.C. Electrical Characteristics (PROGRAMMING Mode)
(TA = 25℃, unless otherwise specified)
Symbol
Tms
Tmh
Tas
Parameter
Mode Decode Setup Time
Mode Decode Hold Time
Address Setup Time
Address Hold Time
CE Setup Time
Min.
2
Typ.
Max.
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
Test Conditions
Note
2
2
Tah
2
Tces
Tceh
Tds
2
CE Hold Time
2
Date Setup Time
2
Tdh
Data Hold Time
2
Tvs
VPP Setup Time
2
Tpw
Tdv
Program Pulse Width
100
150
OE to Output Valid
Tdf
90
ns
CE = V
IL
OE to Output High-Z
OTP ROM Mega Cell A.C. Test Conditions
Output Load
1 TTL Gate and C L = 100pF
10ns max.
Input Pulse Rise and Fall Times
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level
Inputs 0.8V and 2.2V
Outputs 0.8V and 2.4V
10
NT68P81
OTP ROM Mega Cell Timing Waveform (Program)
Tms
Tmh
MODE DEC.
TEST = VPP, MODE [0..2] = 000;
Tvs
VPP
Tas
Tah
A0 - A14
CE
OE
Tceh
Tces
Tdf
DOUT
DB0 - DB7
PGM
D IN
Tdv
Tds
Tpw
Tdh
Note:
5. VDD must be applied simultaneously or before VPP and cut off simultaneously or after VPP.
6. Removing the device from the socket or setting the device in socket with VPP = 12.75V may cause permanent
damage.
11
NT68P81
OTP ROM Mega Cell Mode Selection
Mode [0..2]
Mode
CE
VPP
DB0-DB7
RESET = 12.75V, VPIL = VIL,
OE
VPIH = VIH
not VPP
VPP
－
Normal Operating
Output Disable
－
－
－
－
－
000
000
000
000
001
010
011
100
101
V
IH
－
high-Z
data in
data out
high-Z
data in
－
VPP
Program
V
IH
V
IH
VPP
－
VPP
Program Verify
V
IH
V
IL
VPP
Program Inhibit (Standby)
Security (Program)
Word-line Stress
Bit-line Stress
V
IL
－
－
－
－
VPP
VPP
VPP
VPP
VPP
VPP
VPP
V
IH
VPP
－
－
VPP
“0”
VPP
OTP Row (after pkg)
OTP Column (after pkg)
V
IH
V
IH
data in
data in
VPP
V
IH
V
IH
*The security byte is at $0000 address.
When the VPP input is at 12.75V and CE is at V , the chip
is in the PROGRAMMING mode.
IH
READ MODE
The NT68P81's OTP ROM mega cell has 2 control pins.
The CE (chip enable) controls the operation power and is
PROGRAM VERLFY MODE
used for device selection. The OE (output enable)
controls the output buffers.
The VERIFY mode will check to see that the desired data
is correctly programmed on the programmed bit. The
VERIFY is accomplished with CE at V , VPP input is at
IH
OUTPUT DISABLE MODE
12.75V, and OE = V .
IL
If OE = V , the outputs will be in a high impedance state.
IH
So two or more ROMs can be connected together on a
common bus.
PROGRAM INHIBIT
Using this mode, programming of two or more OTP ROMs
in parallel with different data is accomplished. All inputs
STANDBY MODE
except for CE and OE may be commonly connected. The
TTL high level program pulse is only applied to the CE of
the desired device and TTL high level signal is applied to
the other devices.
By applying a low level to the chip is in standby mode, it
will reduce the operating current to 100µA.
PROGRAM MODE
Initially, all bits are in "1" state which is an erased state.
Thus the program operation is to introduce "0" data into
the desired bit locations by electronic programming.
12
NT68P81
4. SRAM: 256 X 8 bits
The built-in SRAM is used for general purpose data memory and for stack area. SRAM is addressed from 0080H to
017FH. Because the 6502C default stack pointer is 01FFH, the stack area will map $01FF-$0180 to $00FF-$0080, thus
the programmer can set the “ S” register to 7FH when starting program, allowing stack point to be 017FH.
as;
LDX
TXS
#$7F
$0000
$001F
System Registers
Unused
$0080
$00FF
RAM
$0100
$017F
RAM
stack pointer
Unused
$E800
$FFFA
ROM
NMI Vector
NMI-L
NMI-H
RST-L
RST-H
IRQ-L
IRQ-H
$FFFB
$FFFC
$FFFD
RESET Vector
IRQ Vector
$FFFE
$FFFF
13
NT68P81
5. System Reserved Registers
Address Register
Reset
00H
00H
00H
00H
00H
00H
00H
01H
Bit 7
－
Bit 6
－
Bit 5
－
Bit 4
－
Bit 3
KBD
CKBD
EKBD
IN2
Bit 2
INT1
CINT1
EINT1
IN1
Bit 1
INT0
CINT0
EINT0
OT0
Bit 0
TMR
CTMR
ETMR
IN0
R/W
R
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
IRQFUNC
IRQCLRF
IE_FUNC
IRQUSB
IRQCLRU
IE_USB
BT
－
－
－
－
W
－
－
－
－
R/W
R
SUSP
CSUSP
ESUSP
BT7
STUP
CSTUP
ESTUP
BT6
－
－
－
－
CIN2
EIN2
BT3
CIN1
EIN1
BT2
COT0
EOT0
BT1
CIN0
EIN0
BT0
W
－
－
R/W
W
BT5
－
BT4
－
TCON
－
－
－
－
－
W
ENBT
TM0
P00
P10
P20
P30
LED0
1
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
TMOD
PORT0
PORT1
PORT2
PORT3
LED
00H
FFH
FFH
FFH
1FH
07H
00H
02H
－
P07
P17
P27
－
－
P06
P16
P26
－
－
P05
P15
P25
－
－
P04
P14
P24
P34
－
－
P03
P13
P23
P33
－
TM2
P02
P12
P22
P32
LED2
1
TM1
P01
P11
P21
P31
LED1
0
R/W
R/W
R/W
R/W
R/W
W
－
－
－
CLRWDT
MODE_FG
0
1
0
1
0
W
－
－
－
－
－
－
POF
SUSF
R/W
－ : no effect
6. Power-on Reset
7. Timing Generator
Built-in power-on reset circuit can generate a minimum of
5ms pulse to reset the entire chip. The user also can use
This block generates the system timing and control
signals supplied to the CPU and on-chip peripherals. The
crystal oscillator generates a 6MHz system clock. It only
generates 3MHz clock for CPU.
an external RESET pin to reset the entire chip.
14
NT68P81
8. Base Timer (BT)
The Base Timer is an 8-bit counter with a programmable clock source selection. The BT can be enabled/disabled by the
CPU. After reset, the BT is disabled and cleared. The BT can be preset by writing a preset value to BT7 ~ BT0 of the BT
register at any time. When the BT is enabled, the BT starts counting from the preset value. When the value reaches FFH, it
generates a timer interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the BT will wrap
around and begin counting at 00H. The BT can be enabled by writing a "0" to "ENBT " bit in the TCON (Timer Control)
register. The ENBT signal is level trigger.
The input clock source of BT is controlled by the TMOD register. The following table shows 8 ranges of the BT.
TM2
0
TM1
0
TM0
0
Pre-scalar Ratio
Min. Count
1.33 µs
Max. Count
341.33 µs
682.66 µs
1.36 ms
3
System Clock/2
4
0
0
1
System Clock/2
2.66 µs
5
0
1
0
System Clock/2
5.32 µs
6
0
1
1
System Clock/2
10.64 µs
21.28 µs
42.56 µs
85.12 µs
170.24 µs
2.72 ms
7
1
0
0
System Clock/2
5.44 ms
8
1
0
1
System Clock/2
10.89 ms
21.79 ms
43.58 ms
9
1
1
0
System Clock/2
10
1
1
1
System Clock/2
For counting accuracy, please set the TMOD register first, then preset the BT register, and enable the base timer finally.
(TM2, TM1, TM0) = (1, 1, 1) is reserved for USB driver use.
15
NT68P81
9. Interrupt Controller
There are 10 interrupt sources: Timer, INT0, INT1, KBD, SUSP, IN0, IN1, IN2, OT0 and STUP.
9.1. Timer Interrupt
When the BASE TIMER overflows, it will set the TMR flag, If the interrupt is enabled by writing "1" to the bit 0 in IE_FUNC
($0002H), then it will interrupt 6502 CPU. The TMR flag can be read by the software. Once set by an interrupt source, it can
read from bit0 in IRQFUNC ($0000H) and remains high unless cleared by writing "1" to the bit 0 in IRQCLRF ($0001H). All
of register's data is cleared to "0" at initialization by the system reset. When an interrupt occurs, the CPU jumps to $FFFEH
& $FFFFH to execute the interrupt service routine, thus the TMR flag must be cleared by the software.
9.2. INT0 Interrupt
As soon as INT0 pin detects a falling edge trigger, NT68P81 sets the INT0 flag ($0000H, bit1). After that, the 6502 CPU is
interrupted if this interrupt has been already been enabled by writing “ 1” to EINT0 ($0002H, bit1). If the EINT0 flag is
cleared, the 6502 CPU can’ t be INT0 interrupted even if the INT0 flag is set. INT0 flag can be only be set by hardware and
cannot be set or cleared directly by the software except for writing “ 1” to CINT0 ($0001H, bit1) flag to clear INT0 flag. When
an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine so the INT0 flag must
be cleared by software.
9.3. INT1 Interrupt
As soon as the INT1 pin detects a falling edge trigger, NT68P81 sets the INT1 flag ($0000H, bit2). Then the 6502 CPU is
interrupted if the interrupt has already been enabled by writing “ 1” to EINT1 ($0002H, bit2). If EINT0 flag is cleared, the
6502 CPU can’ t be INT1 interrupted even if INT1 flag is set. INT1 flag can only be set by the hardware and can not be set
or cleared directly by the software except for writing “ 1” to CINT1 ($0001H, bit2) flag to clear INT1 flag.
When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the INT1 flag must be
cleared by the software.
9.4. KBD Interrupt
This interrupt will set the KBD flag ($0000H, bit3) every 4ms(HID 1.00 version) to indicate that keyboard scan data is ready
to send for endpoint1. Then the 6502 CPU is interrupted if this interrupt has been enabled already by writing “1” to EKBD
($0002H, bit3). If the EKBD flag is cleared, the 6502 CPU can’ t be KBD interrupted even if the KBD flag is set. The KBD
flag can only be set by the hardware and can not be set or cleared directly by the software except for writing “ 1 ” to CKBD
($0001H, bit 3) flag to clear KBD flag.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the KBD flag must
be cleared by the software.
9.5. IN0 Token Interrupt
When an IN TOKEN for endpoint 0 is done, it will set the IN0 flag. If this interrupt is enabled by writing "1" to EIN0 ($0005H,
bit0), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN0 flag must
be cleared by the software.
9.6. OT0 (OUT 0) Token Interrupt
When an OUT TOKEN for endpoint 0 is done, it will set the OT0 flag. If this interrupt is enabled by writing "1" to EOT0
($0005H, bit1), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the OT0 flag must
be cleared by the software.
16
NT68P81
9.7. IN1 Token Interrupt
When an IN TOKEN for endpoint 1 is done, it will set the IN1 flag. If this interrupt is enabled by writing "1" to EIN1 ($0005H,
bit2), it will interrupt the 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN1 flag must
be cleared by the software.
9.8. IN2 Token Interrupt
When an IN TOKEN for endpoint 2 is done, it will set the IN2 flag. If this interrupt is enabled by writing "1" to EIN2 ($0005H,
bit3), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN2 flag must
be cleared by the software.
9.9. STUP (SETUP) Token Interrupt
When a SETUP TOKEN for endpoint 0 is done, it will set the STUP flag. If this interrupt is enabled by writing "1" to ESTUP
($0005H, bit6), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the STUP flag
must be cleared by the software.
9.10. SUSP Interrupt
When USB SIE detects a suspend signal, it sets the SUSP flag. Then the 6502 CPU is interrupted if the interrupt has
already been enabled by writing “ 1” to ESUSP ($0005H, bit7). If ESUSP flag is cleared, 6502 CPU can’ t be SUSP
interrupted even if SUSP flag is set. SUSP flag can be set by H/W only and can’ t be set/cleared directly by the software
except for writing “1” to CSUSP ($0004H, bit 7) flag to clear SUSP flag.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the SUSP flag
must be cleared by the software.
10. I/O PORTs
The NT68P81 has 32 pins dedicated to input and output. These pins are grouped into 5 ports, as follows:
PORT0 (P00~P07)
PORT0 is an 8-bit bi-directional CMOS I/O port that is internally pulled high by PMOS. Each pin of PORT0 can be bit
programmed as an input or output port under software control. When programmed as output, data is latched to the port
data register and output to the pin. PORT0 pins with “ 1” written to them are pulled high by the internal PMOS pull-ups, and
can be used as inputs in that state, then these input signals can be read. The port will output high after the reset.
PORT1 (P10~P17): Functions the same as PORT0.
PORT2 (P20~P27): Functions the same as PORT0.
PORT3 (P30~P34): Functions the same as PORT0. Except for P33/P32 is shared with INT1/INT0 pin. It is also a Schmitt
Trigger input with an interrupt source of falling edge sensitive.
LED: There are three LED direct sink pins which require no external serial resistors.
The address is mapped to $000DH.
17
NT68P81
11. Watch-Dog Timer (WDT)
The NT68P81 has a watch-dog timer reset function that protects programs against system standstill. The clock of the
WDT is derived from the crystal oscillator. The WDT interval is about 0.15 seconds when the operation frequency is 6MHz.
The timer must be cleared every 0.15 second during normal operation; otherwise, it will overflow and cause a system
reset (This cannot be disabled by the software). Before watch-dog reset occurs, the software will clear the watch-dog
register by writing #55H to CLRWDT ($000EH) register.
For example:
LDA #$55H
STA $000E
12. Power Control
The power-off flag (POF) in the MODE_FG register indicates whether a reset is a warm start or a cold start reset. POF is
set by hardware when an external power VCC arises to its normal operating level, and must be cleared by the software in
the cold reset initialization procedure. A warm start reset (POF = 0) occurs at a watch-dog reset or resume reset.
Address Register
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
$000FH MODE_FG
02H
-
-
-
-
-
-
POF
SUSF
R/W
13. Universal Serial Bus Interface
Please refer to the UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7, 8, and 9.
14. Suspend and Resume
Suspend:
When SIE receives the suspend signal, NT68P81 generates a SUSP interrupt request. In the SUSP interrupt service
routine, the software will carry out the following steps:
1) Clear SUSP IRQ flag,
2) Store all the port status,
3) Force return lines (PORT2) pull-high,
4) Force scan lines (PORT0, PORT1 and P30, P31 or P32) pull-low,
5) Turn off LED output,
6) Clear watch-dog register
After the above action has been completed, the software will then set SUSLO ($1EH) to #55H and SUSHI ($1FH) to #AAH
in order to enter the SUSPEND mode. The oscillator will stop for in order to save power.
Resume:
When the SIE detects a resume signal, the NT68P81 trigger oscillator to oscillate and resets whole chip. After a reset,
software checks the status of POF bit in MODE_FG register to see whether a cold start reset or a warm start reset
occurred. If cold reset, it executes all initial procedure. If warm reset, software checks the status of SUSF bit in MODE_FG
register to see whether a watch-dog reset or resume reset. Under resume reset condition, programmer should restores
all port status. After a warm start, user software should clear the SUSF bit. When any key stroked in suspend mode, it
remotely resume NT68P81 functions. The action is same as host resume.
18
NT68P81
15. Reset Source Summary
These are 5 reset sources in NT68P81 as shown below.
No.
Type
Function
Description
1
Cold
Applied Externally
External Pin ( RESET )
Power-on Reset
2
3
4
5
Cold
Cold
Reset after Power-on
10 ms Reset Period
USB Reset Signaling
Resume Reset
Warm-1
Warm-2
USB Reset Period
Watch-dog Reset
Reset every 0.15S (OSC = 6MHz)
NT68P81 can also be reset externally through the RESET pin. A reset is initialed when the signal at the RESET pin is
held Low for at least 10 system clocks. When RESET signal goes high, the NT68P81 begins to work. The following
shows the definition of RESET input low pulse width.
V
DD
V
DD
20%VDD
20%VDD
Trstb
16. PS/2 Mouse Application
A PS/2 mouse interface is implemented in P32 (CLK), P33 (DATA) and P34 (Power Control). The timing diagrams are
described as follows.
1st
CLK
2nd
CLK
10th
CLK
11th
CLK
CLK
T4
T1A
T3
T1
T5
T2
DATA
Start Bit
Bit 0
Parity Bit
Stop Bit
Auxiliary Device Sending Data Timings
Timing
Description
MIN/MAX
u
u
T1
T1A
T2
T3
T4
Time from DATA transaction to falling edge of CLK 1
Time from DATA transaction to falling edge of CLK 2-11
Time from rising edge of CLK to DATA transaction
Duration of CLK inactive (LOW)
5/25
5/25
s
s
5/T4-5u s
30/50
30-50
u
u
s
s
Duration of CLK active (HIGH)
Time to Auxiliary Device inhibit after clock 11 to ensure the Auxiliary Device
does not start another transmission
u
T5
>0/50
s
19
NT68P81
10th
CLK
11th
CLK
2nd
CLK
1st
CLK
9th
CLK
CLK
I/O Inhibit
T7
T6
T9
T10
T8
Bit 0
DATA
Start Bit
Parity Bit
Stop Bit
Line Control Bit
Auxiliary Device Receiving Data Timings
Timing
Description
MIN/MAX
T6
T7
Duration of CLK interface (LOW)
Duration of CLK active (HIGH)
30/50us
u
30/50 s
Time from inactive to active CLK transition, used to time when the Auxiliary Device samples
DATA
Time from falling edge of line control bit to falling edge of clock 11 CLK
T8
5/25u s
5u s/
T9
u
5/25 s
T10
Time from rising edge of clock 11 to rising edge of line control bit
20
NT68P81
Absolute Maximum Rating*
*Comments
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
DC Supply Voltage . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
Input/Output Voltage . . . . . . . .GND - 0.2V to VDD + 0.2V
°
°
Operating Ambient Temperature . . . . . . . . .0 C to 70 C
°
°
Storage Temperature . . . . . . . . . . . . . .-55 C to +125 C
Operating Voltage (VDD) . . . . . . . . . . . . .+4.4V to +5.25V
DC Electrical characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 6MHz, unless otherwise noted)
Symbol
VDD
Parameters
Operating Voltage
Min.
Typ.
Max.
5.25
20
Unit
V
Conditions
4.4
5
IOP
Operating Current
mA
µA
V
No load
ISP
Suspend Current
500
V
IH
Input High Voltage
2
V
IL
Input Low Voltage
0.8
V
VOH
VOL1
VOL2
ILED
Output High Voltage
2.4
V
IOH = -100µA
IOL1 = 4mA
IOL2 = 5mA
VOL = 3.2V
Output Low Voltage (P0/P1/P2)
Output Low Voltage (P3)
LED Sink Current
0.4
0.4
14
2
V
V
6
10
1.7
1.1
mA
V
VSTIH
VSTIH
Schmitt Trigger Input High Voltage
Schmitt Trigger Input Low Voltage
0.8
V
AC Electrical characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 6MHz, unless otherwise noted)
Symbol
FOSC
Parameters
Oscillator Frequency
Min.
5.97
1.67
Typ.
Max.
Unit
MHz
ms
Conditions
6
6.03
OSC within +/- 0.5%
10 system clocks
TRSTB
RESET Input Low Pulse Width
Power-on Reset Time
TPOR
5
30
ms
USB DC/AC SPECIFICATIONS
Please refer to the UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7.
21
NT68P81
Application Circuit 1 (Simple Keyboard with PS/2 Mouse)
VC C
PS/2 Mouse CLK
PS/2 Mouse DATA
PS/2 Mouse Power Control
P32
P33
P34
Vcc
GND
LED0
LED1
LED2
0.1 mF
10 mF
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
Scroll Lock
Num Lock
Caps Lock
NT68P81
RESET
*1
*1: RESET can be direct
connect to VCC if the
external reset is not
used for module test.
4.7KO
OSCI
6Mhz Crystal
OSCO
P20
P21
P22
P23
P24
P25
P26
P27
D+
VDP
VDM
To USB Cable
D-
1.5KO
VCP
4.7mF
P21
P23
P20
P22
P24
P25
P26
P27
#
F3
D
F
J
F4
C
K133
F2
E
3
P00
%
5
$
4
R
U
G
V
T
Y
B
N
P01
P02
P03
^
&
7
*
8
(
M
H
6
+
=
<
,
}
]
F6
I
K
K56
APP
>
.
O
L
F7
F8
9
P04
P05
+
Enter
(Num)
K107
6
Home
Page
End
(Num)
.
9
3
*
-
Page
Down
Del
PgDn
PgUp
8
(Num)
/
(Num) Up
P06
P07
5
2
0
Ins
Insert
Kor_R
Kor_L
(Num)
(Num)
7
1
End
Num
Lock
4
Space
Delete
Home
P10
P11
L-Shift R-Shift
Back
Space
|
K14
P
F11
Enter
F12
F9
F10
\(K29)
:
;
_
-
P12
P13
P14
P15
{
[
|
)
0
?
/
"
'
\(K42)
Scroll
Lock
Print
Screen
L-Alt
R-Alt
000
00
Pause
L-Ctrl
R-Ctrl
F5
L-WIN
TAB
P16
P17
Kor_L
Q
R-Win
Kor_R
!
1
@
2
~
`
Esc
K45
Z
X
K131
K132
A
S
P30
P31
Caps
Lock
W
F1
Notice: “ Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
22
NT68P81
Application Circuit 2 (Windows 2000 Compatible Keyboard)
V CC
Vcc
GND
0.1 mF
10 mF
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
LED0
LED1
LED2
Scroll Lock
Num Lock
Caps Lock
P14 NT68P81
P15
P16
P17
P30
P31
P32
RESET
*1
*1: RESETB can be
4.7KO
direct connect to VCC if
the external reset is not
used for module test.
OSCI
6Mhz Crystal
OSCO
P20
P21
P22
P23
P24
P25
P26
P27
D +
VDP
VDM
To USB Cable
D-
1.5KO
VCP
4.7mF
P21
P23
P20
P22
P24
P25
P26
P27
#
3
E
F3
D
F4
C
K133
F2
P00
$
4
%
5
R
U
I
G
H
V
T
Y
F
J
B
N
P01
P02
P03
^
6
+
=
&
7
*
8
M
<
,
}
]
K
F6
K56
APP
>
.
(
9
O
L
F7
Bass+
F8
P04
P05
+
Enter
(Num)
Scan
Next
K107
6
Home
End
(Num)
.
9
3
Page
Up
*
-
Page
Down
Del
PgDn
PgUp
(Num) (Num)
P06
P07
P10
/
8
5
2
0
Ins
Insert
Sleep
(Num)
(Num)
7
1
End
Num
Lock
Power
Down
4
Space
Delete
Mute
F9
Home
Scan
Previous
Wake
Up
Play/
Stop
L-Shift
R-Shift
Volume+
Pause
P11
P12
P13
P14
P15
Back
|
K14
P
F11
Enter
F12
F10
Space
\(K29)
_
-
:
;
{
[
|
)
0
"
'
?
/
\(K42)
Scroll
Lock
Euro
Key
Print
Screen
Bass-
000
00
L-Alt
R-Alt
Treble+
.
Power
Down
Wake
Up
Sleep
Pause
R-Ctrl
L-Ctrl
F5
WWW WWW
Search Home
Bass
Boost
WWW
Backward
Volume-
L-WIN Email
P16
P17
WWW
Forward
WWW
WWW
Stop
WWW
Kor_L
Q
R-Win
Kor_R
Refresh Favorite
!
1
~
`
Z
X
Esc
K131
K132
A
S
TAB
P30
P31
P32
Caps
Lock
@
2
W
K45
F1
Media
Select
My
Treble-
Calculator
Computer
Notice: “ Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
23
NT68P81
Application Circuit 3 (Mini Keyboard)
V CC
Vcc
GND
0.1 mF
10 mF
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
LED0
LED1
LED2
Scroll Lock
Num Lock
Caps Lock
P14 NT68P81
P15
P16
P17
P30
P31
P32
RESET
*1
*1: RESETB can be
4.7KO
direct connect to VCC if
the external reset is not
used for module test.
OSCI
6Mhz Crystal
OSCO
P20
P21
P22
P23
P24
P25
P26
P27
D +
VDP
VDM
To USB Cable
D-
1.5KO
VCP
4.7mF
P21
F3
*FN_K3
P23
F4
*FN_K4
P20
P22
P24
P25
P26
P27
#
3
F2
E
D
C
K133
*FN_K2
P00
$
4
%
5
R
U
G
H
V
T
Y
F
B
N
P01
P02
P03
M
*0 Ins
J
^
6
+
=
F8
&
7
*1 End
*4
*7 Home
<
,
}
]
F6
*
8
I
K
K56
APP
*8
*5(Num)
*FN_K6
*2
F7
*FN_K7
L
>
.
(
9
O
Bass+
*6
*3 PgDn
*. Del
*FN_K8
*9 PgUp
P04
P05
+
Enter
(Num)
Scan
Next
Home
End
K107
6
(Num)
*FN_K21
*FN_K22 *FN_K16 *FN_K19
.
Page Up
Page Down
*FN_K17 *FN_K20
9
3
*
-
Del
PgDn
PgUp
(Num) (Num)
/
P06
P07
P10
8
5
2
0
Ins
Insert
*FN_K24
(Num)
Sleep
*FN_K15
(Num)
Delete
*FN_K18
7
1
End
Num
Power
Down
4
Space
*FN_K23
Lock
Home
Scan
Previous
Wake
Up
Play/
Stop
L-Shift
R-Shift
Mute
Volume+
Pause
P11
P12
P13
P14
P15
F12
F9
F10
Back
|
F11
K14
Enter
*FN_K11
*FN_K12 *FN_K9 *FN_K10
Space
\(K29)
_
-
P
{
[
:
;
|
?
/
)
0
"
'
* -(Num)
\(K42)
* +(Num)
* /(Num)
* *(Num)
Print Screen
Scroll Lock
*Num Lock
Euro
Key
Bass-
000
L-Alt
R-Alt
Treble+
*FN_K13
.
Pause
*FN_K14
Power
Down
Wake
Up
F5
*FN_K5
Sleep
00
R-Ctrl
L-Ctrl
WWW WWW
Search Home
Bass
Boost
WWW
Backward
Volume-
L-WIN Email
P16
P17
WWW
Forward
WWW
WWW
Stop
WWW
FN
Kor_L
Q
R-Win
Kor_R
Refresh Favorite
!
1
~
`
Z
X
Esc
K131
K132
A
S
TAB
P30
P31
P32
F1
*FN_K1
Caps
Lock
Media
Select
@
2
W
K45
My
Treble-
Calculator
Computer
Notice: “ Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
*: For FN key model usage
24
NT68P81
FN Key Model Usage for Keypad
FN+Scroll
Num Lock
Lock
FN+&
FN+U
FN+J
FN+M
7
7 Home
4 ¬
FN+*
FN+I
FN+K
8
8 •
FN + (
FN+O
FN+L
FN+>
9
9 PgUp
6 ®
FN+)
FN+P
FN+:
FN+?
0
*(Num)
-(Num)
+(Num)
/(Num)
5(Num)
2 ¯
1 End
0 Ins
3 PgDn
. Del
;
/
.
FN Key Model Usage for Consumer Keys
FN_K1
FN_K3
FN_K5
FN_K7
FN_K9
FN_K11
FN+F1
FN+F3
FN+F5
FN+F7
FN+F9
FN+F11
WWW Backward
FN_K2
FN+F2
FN+F4
FN+F6
FN+F8
FN+F10
FN+F12
WWW Forward
WWW Refresh
WWW Favorite
Email
WWW Stop
FN_K4
FN_K6
FN_K8
FN_K10
FN_K12
WWW Search
WWW Home
My Computer
Media Select
Calculator
Mute
FN+Print
Screen
FN_K13
Bass Boost
FN_K14
FN+Pause
Sleep
FN_K15
FN_K17
FN_K19
FN_K21
FN_K23
FN+Insert
FN+Page Up
FN+End
FN+ •
Volume+
Treble+
Bass-
FN_K16
FN_K18
FN_K20
FN_K22
FN_K24
FN+Home
FN+Delete
FN+Page Down
FN+ ¬
Bass+
Volume-
Treble-
Stop
Scan Previous Track
Scan Next Track
FN+ ¯
Play/Pause
FN+ ®
25
NT68P81
Bonding Diagram
25 24 23 22
21 20 19 18 17
16
P04
P03
P02
P01
P00
Reset B
P34
P33
P32
P31
P30
26
27
28
29
30
31
32
33
34
35
36
37
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
LED0
LED1
15
14
13
12
11
10
9
NT68P81
(0,0)
5470 mm
8
7
6
1
4
5
39 40
3
38
41 42
2
3400 mm
Substrate connect to VCC
Unit: mm
Pad No.
Designation
X
Y
21
P11
303.90
2545.00
Pad No.
Designation
X
Y
1
2
3
4
5
6
7
8
9
GND
GND
VCP
VDP
VDM
P30
P31
P32
P33
P34
264.50 -2460.05
424.50 -2481.00
734.95 -2470.00
1069.35 -2466.00
1368.85 -2466.00
1443.05 -2069.05
1443.05 -1768.65
1443.05 -1468.25
1443.05 -1167.85
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
LED0
LED1
LED2
VCC
VCC
-308.10
-598.10
-888.10
2545.00
2545.00
2545.00
2545.00
1012.50
670.80
370.40
70.00
-1178.10
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00 -1131.60
-1478.00 -1432.00
-1478.00 -1732.40
-1478.00 -2037.15
-1478.00 -2337.55
-1112.85 -2481.00
-812.45 -2470.55
-626.85 -2470.55
10
1443.05
-867.45
-230.40
-530.80
-831.20
11
12
13
14
15
16
17
18
19
20
RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
1443.05
1443.05
1443.05
1443.05
1443.05
1443.05
1463.90
1173.90
883.90
-560.45
-235.35
65.05
365.45
659.85
1007.20
2545.00
2545.00
2545.00
2545.00
593.90
26
NT68P81
41
OSCO
-326.45 -2481.00
42
OSCI
-7.75 -2481.00
27
NT68P81
Ordering Information
Part No.
NT68P81H
NT68P81
Packages
CHIP FORM
40L DIP
Standard code functional descriptions
Code Number
Name
Reference application
circuit
Functional Description
NT68P81-D01012
Simple Keyboard with
PS/2 Mouse
Application circuit 1
1. PS/2 mouse port
2. '000' and '00' keys
1. ACPI keys
NT68P81-D01013
NT68P81-D01014
Windows 2000
Compatible Keyboard
Application circuit 2
2. '000', '00' and Euro keys
3. Consumer keys (Windows 2000)
1. ACPI keys
Mini Keyboard
Application circuit 3
2. ‘000’, ‘00’ and Euro keys
3. Consumer keys (Windows 2000)
4. FN key and 40 Translated keys
28
NT68P81
Package Information
P-DIP 40L Outline Dimensions
unit: inches/mm
D
40
21
1
20
E
S
Base Plane
Seating Plane
B
e
A
a
e
1
B
1
Symbol
Dimensions in inches
0.210 Max.
0.010 Min.
Dimensions in mm
5.33 Max.
0.25 Min.
3.94±0.25
0.46 +0.10
-0.05
A
A1
A2
B
0.155±0.010
0.018 +0.004
-0.002
B1
C
0.050 +0.004
-0.002
1.27 +0.10
-0.05
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
E
2.055 Typ. (2.075 Max.) 52.20 Typ. (52.71 Max.)
0.600±0.010 15.24±0.25
0.550 Typ. (0.562 Max.) 13.97 Typ. (14.27 Max.)
E1
e1
L
0.100±0.010
0.130±0.010
0°~ 15°
2.54±0.25
3.30±0.25
0°~ 15°
α
eA
S
0.655±0.035
0.093 Max.
16.64±0.89
2.36 Max.
Note:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
29
NT68P81
Product Spec. Change Notice
NT68P81 Specification Revision History
Version
Content
Data
2.1
FN Key Model Usage for Consumer Keys
modified - FN_K22 and FN_K24 (Page
24)
Oct. 2002
Sep. 2002
Volume Knob Application deleted (Page
18)
PS/2 Mouse Application added (Page 18
and 19)
Application circuit 2 and 3 modified (Page
22 and 23)
2.0
FN key usage added (Page 24)
Standard code functional descriptions
modified (Page 26)
Application circuits modified (Page 20, 21
and 22)
Standard code functional description
added (Page 24)
1.3
1.0
July 2002
Nov. 1998
Original
30
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