NT7701H-TABF3中文资料_数据手册_规格书

NT7701

160 Output LCD Segment/Common Driver

Features

(Segment mode)

ꢀ Available in a single mode (160-bits shift register) or in a

dual mode (80-bits shift register x 2)

ꢀ Shift Clock frequency :

1. Y1 → Y160

Single mode

Dual mode

14 MHz (Max.) (VDD = 5V ± 10%)

2. Y160 → Y1

8 MHz (Max.) (VDD = 2.5V - 4.5V)

3. Y1 → Y80, Y81 → Y160

4. Y160 → Y81, Y80 → Y1

ꢀ Adopts a data bus system

ꢀ 4-bit/8-bit parallel input modes are selectable with a

mode (MD) pin

The above 4 shift directions are pin-selectable

(Both segment mode and common mode)

ꢀ Automatic transfer function with an enable signal

ꢀ Automatic counting function when in the chip select

mode, causes the internal clock to be stopped by

automatically counting 160 bits of input data

ꢀ Supply voltage for LCD drive: 15.0 to 30.0V

ꢀ Number of LCD driver outputs: 160

ꢀ Low output impedance

(Common mode)

ꢀ Low power consumption

ꢀ Shift clock frequency:

ꢀ Supply voltage for the logic system: +2.5 to +5.5V

ꢀ COMS process

4.0MHz (Max.)

ꢀ Built-in 160-bits bidirectional shift register (divisible into ꢀ Package : 190pin TCP (Tape Carrier Package)

80-bits x 2)

ꢀ Not designed or rated as radiation hardened

General Description

The NT7701 is a 160-bit output segment/common driver LSI

suitable for driving the large scale dot matrix LCD panels

used by PDA's, personal computers and work stations for

example. Through the use of SST (Super Slim TCP)

technology, it is ideal for substantially decreasing the size of

the frame section of the LCD module. The NT7701 is good

as both a segment driver and a common driver, and a low

power consuming, high-precision LCD panel display can be

assembled using the NT7701. In the segment mode, the

data input is selected 4bit parallel input mode or as 8bit

parallel input mode by a mode (MD) pin. In common mode,

the data input/output pins are bi-directional and the four data

shift directions are pin-selectable.

Pin Configuration

D

U

M

Y

D

U

M

Y

D

U

M

Y

D

U

M

Y

1

6

0

Y

1

5

9

Y

1

5

8

Y

1

5

7

Y

1

5

6

Y

1

5

Y

8

3

Y

8

2

Y

8

1

Y

8

0

Y

7

9

Y

7

8

Y

6

Y

5

Y

4

Y

3

Y

2

Y

1

190 189 188 187 186 185

113 112 111 110 109 108

36 35 34 33 32 31

NT7701

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

D

U

M

Y

V

0

L

V

1

2

L

V

4

3

L

V

5

L

V

S

L

/

V

D

S

/

E

I

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

X

C

K

D

I

L

E

I

F

M

D

T

E

S

T

1

T

E

S

T

2

V

S

V

5

V

4

V

1

V

O

R

D

U

M

Y

P

R

C

O

2

S

P

O

F

O

1

R

3

2

R

1

V2.0

NT7701

Pad Configuration

199

54

200

53

NT7701

216

37

1

36

Block Diagram

Y1

Y2

Y159 Y160

V

0R

V

12R

V

43R

V

5R

V

5L

FR

160 Bits 4 Level Driver

Level

V

43L

Shifter

V12L

DISPOFF

/160

V0L

160 Bits Level Shifter

V

5R

EIO

1

/160

Active

Control

160 Bits Line Latch/Shift Register

EIO

2

/16 /16 /16 /16 /16 /16 /16 /16 /16 /16

8Bits x 2

Data

Latch

LP

Control

Logic

XCK

Data Latch Control

/8

L/R

MD

S/C

SP Conversion & Data Control

(4 to 8 or 8 to 8)

V

DD

V

SS

V

SS

DI

0

DI

1

DI

2

DI

3

DI

4

DI

5

DI

6

DI

7

2

NT7701

Pin Description

Pin No.

Designation

V_0L

I/O

P

I

Description

Power supply for LCD driver

1

2

V_12L

V_43L

V_5L

Power supply for LCD driver

3

4

5

V_SS

Ground (0V), these two pads must be connected to each other

Display data shift direction selection

6

L/R

7

V_DD

P

I

Power supply for the logic system (+2.5 to +5.5V)

Segment mode / common mode selection

Input / output for chip select or data of shift register

Display data input for segment mode

8

S/C

9

EIO₂

D0 - D6

D7

I/O

I

10 - 16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 - 190

I

Display data input for Segment mode / Dual mode data input

Display data shift clock input for segment mode

Control input for deselect output level

Latch pulse input/shift clock input for the shift register

Input / output for chip select or data of the shift register

AC-converting signal input for LCD driver waveform

Mode selection input

XCK

I

DISPOFF

LP

I

EIO₁

FR

I/O

I

MD

I

TEST1

TEST2

V_SS

I

Test pin, no connection for user

I

Test pin, no connection for user

P

O

Ground (0V), these two pads must be connected to each other

Power supply for LCD driver

V_5R

V_43R

Power supply for LCD driver

V_12R

Power supply for LCD driver

V_0R

Power supply for LCD driver

Y1 - Y160

LCD driver output

3

NT7701

Pad Description

Pad No.

1, 2

Designation

L/R

I/O

I

Description

Display data shift direction selection

3, 4

V_DD

P

I

Power supply for the logic system (+2.5 to + 5.5V)

Segment mode/common mode selection

Input/output for chip select or data of shift register

Display data input for segment mode

5, 6

S/C

7, 8

EIO₂

I/O

I

9,10 - 21, 22

23, 24

D0 - D6

D7

I

Display data input for Segment mode / Dual mode data input

Display data shift clock input for segment mode

Control input for deselect output level

Latch pulse input / shift clock input for the shift register

Input/output for chip select or data of the shift register

AC-converting signal input for LCD driver waveform

Mode selection input

25, 26

XCK

I

27, 28

I

DISPOFF

LP

29, 30

I

31, 32

EIO₁

FR

I/O

I

33, 34

35, 36

MD

I

37, 38,

39, 40

V_SS

P

O

P

Ground (0V), these two pads must be connected to each other

Power supply for LCD driver

V_5R

41, 42

V_43R

V_12R

V_0R

Power supply for LCD driver

43, 44

Power supply for LCD driver

45, 46

Power supply for LCD driver

47 - 206

207, 208

209, 210

211, 212

213, 214

215, 216

Y1 - Y160

V_0L

LCD driver output

Power supply for LCD driver

V_12L

V_43L

V_5L

Power supply for LCD driver

V_SS

Ground (0V), these two pads must be connected to each other

4

NT7701

Input / Output Circuits

V

DD

I

Input Signal

Applicable Pins

L/R, S/C, D0 - D6,

, LP, FR, MD

DISPOFF

V

SS

Input Circuit (1)

V

DD

I

Input Signal

Applicable Pins

D7, XCK

Control Signal

V

SS

VSS

Input Circuit (2)

5

NT7701

V

DD

Input Signal

Control Signal

V

SS

V

SS

V

DD

Output Signal

Control Signal

I/O

Applicable Pins

EIO1, EIO2

V

SS

Input / Output Circuit

V0

V12

Control Signal 1

Control Signal 3

Control Signal 2

O

Control Signal 4

Applicable Pins

Y1 to Y160

V43

VSS

V5

LCD Driver Output circuit

6

NT7701

Pad Description

Segment mode

Symbol

Function

Logic system power supply pin connects to +2.5 to +5.5V

VDD

VSS

Ground pin connects to 0V

Power supply pin for LCD driver voltage bias

VOR, VOL

V12R, V12L

V43R, V43L

V5R, V5L

ꢁNormally, the bias voltage used is set by a resistor divider

ꢁEnsure that the voltages are set such that VSS ≤ V5 < V43 < V12 < V0

ꢁTo further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y160,

externally connect ViR and ViL (I = 0, 12, 43)

Input pin for display data

D0 - D7 ꢁIn 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD

ꢁIn 8-bit parallel input mode, input data into the 8 pins D0 - D7

Clock input pin for taking display data

XCK

ꢁData is read on the falling edge of the clock pulse

Latch pulse input pin for display data

LP

ꢁData is latched on the falling edge of the clock pulse

Direction selection pin for reading display data

L/R ꢁWhen set to VSS level "L", data is read sequentially from Y160 to Y1

ꢁWhen set to VDD level "H", data is read sequentially from Y1 to Y160

Control input pin for output deselect level

ꢁThe input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD

driver circuit

ꢁWhen set to VSS level “L”, the LCD driver output pins (Y1 - Yl60) are set to level V5

ꢁWhile DISPOFF is set to “L”, the contents of the line latch are reset, but the display data in the data latch

DISPOFF

are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver

outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge

of the LP.

That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, can not

output the reading data correctly

AC signal input for LCD driving waveform

ꢁThe input signal is level-shifted from the logic voltage level to the driver voltage level, and controls LCD

FR

driver circuit

ꢁNormally inputs a frame inversion signal

The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal

Mode selection pin

MD ꢁWhen set to VSS level “L”, 4-bit parallel input mode is set

ꢁWhen set to VDD level “H", 8-bit parallel input mode is set

7

NT7701

Segment mode continued

Symbol

Function

Segment mode/common mode selection pin

ꢁWhen set to VDD level "H", segment mode is set.

ꢁWhen set to VSS level "L", common mode is set.

S/C

Input/output pin for chip selection

ꢁWhen L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input.

ꢁWhen L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output.

EIO1, EIO2

ꢁDuring output, it is set to “H” while LP* XCK is “H” and after 160-bits of data have been read, it is set to

“L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H”

ꢁDuring input, after the LP signal is input, the chip is selected while EI is set to “L”. After 160-bits of

data have been read, the chip is deselected

LCD driver output pins

Y1 - Y160

These corresponding directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and

output

Common mode

Symbol

VDD

Function

Logic system power supply pin connects to +2.5 to +5.5V

Ground pin connects to 0V

VSS

Power supply pin for LCD driver voltage bias.

V0R, V0L

V12R, V12L

V43R, V43L

V5R, V5L

ꢁNormally, the bias voltage used is set by a resistor divider

ꢁEnsure that the voltages are set such that VSS ≤ V5 <V43 < V12 < V0

ꢁTo further reduce the differences between the output waveforms of the LCD driver output pins Y1 and

Y160, externally connect ViR and ViL (I = 0, 12, 43)

Bi-directional shift register shift data input/output pin

ꢁIs an Output pin when L/R is at VSS level “L” and an input pin when L/R is at VDD level “H”

ꢁWhen EIO1 is used as an input pin, it will be pulled-down

EIO1

EIO2

ꢁWhen EIO1 is used as an output pin, it won’t be pulled-down

Bi-directional shift register shift data input/output pin

ꢁIs an Input pin when L/R is at VSS level “L” and an output pin when L/R is at VDD level “H”

ꢁWhen EIO2 is used as an input pin, it will be pulled-down

ꢁWhen EIO2 is used as an output pin, it won’t be pulled-down

Bi-directional shift register shift clock pulse input pin

LP

ꢁData is shifted on the falling edge of the clock pulse

Bi-directional shift register shift direction selection pin

L/R

ꢁData is shifted from Y160 to Y1 when it is set to VSS level “L”, and data is shifted from Y1 to Y160 when it is

set to VDD level “H”

8

NT7701

Common mode continued

Symbol

Function

Control input pin for output deselect level

ꢁThe input signal is level-shifted from the logic voltage level to the LCD driver voltage level and it controls

the LCD driver circuit

ꢁWhen set to VSS level “L”, the LCD driver output pins (Y1 - Y160) are set to level V5

ꢁWhile set to “L”, the contents of the shift resister are reset and not reading data. When the DISPOFF

function is canceled, the driver outputs deselect level (V12 or V34), and the shift data is read on the falling

DISPOFF

edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC

characteristics, the shift data is not reading correctly

AC signal input for LCD driving waveform

ꢁThe input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the

LCD driver circuit

FR

ꢁNormally, inputs a frame inversion signal

The LCD driver output pin’s output voltage level can be set using the shift register output signal and the FR

signal

Mode selection pin

MD

ꢁWhen set to VSS level “L”, Single Mode operation is selected. When set to VDD level “H”, Dual Mode

operation is selected

Dual Mode data input pin

ꢁAccording to the data shift direction of the data shift register, data can be input starting from the 81st bit

When the chip is used as Dual Mode, D7 will be pulled-down

When the chip is used as Single Mode, D7 won’t be pulled-down

D7

Segment mode/common mode selection pin

S/C

D0 - D6

XCK

ꢁWhen set to VSS level “L”, common mode is set

Not used

ꢁConnect D0-D6 to VSS or VDD. Avoiding floating

Not used

ꢁXCK is pulled-down in common mode, so connect to VSS or open

LCD driver output pins

Y1 - Y160 ꢁThese corresponding directly Corresponding directly to each bit of the shift register, one level (V0, V12, V43,

or V5) is selected and output

9

NT7701

Functional Description

1. Block description

1.1. Active Control

1.5. Line Latch / Shift Register

In the case of segment mode, controls the selection or

deselection of the chip. Following a LP signal input, and after

the select signal is input, a select signal is generated

internally until 160 bits of data have been read in. Once data

input has been completed, a select signal for cascade

connection is output, and the ship is deselected.

In the case of the segment mode, all 160 bits which have

been read into the data latch, are simultaneously latched on

to the falling edge of the LP signal, and output to the level

shift block.

In the case of the common mode, shifts data from the data

input pin on to the falling edge of the LP signal.

In the case of common mode, controls the input/output data

1.6. Level Shifter

of bidirectional pins.

The logic voltage signal is level-shifted to the LCD driver

1.2. SP Conversion & Data Control

voltage level, and output to the driver block.

In the case of segment mode, keep input data which are 2

clocks of XCK at 4-bit parallel mode into latch circuit, or keep

input data which are 1 clock of XCK at 8-bit parallel mode

into latch circuit, after that they are put on the internal data

bus 8 bits at a time.

1.7. 4-Level Driver

It drives the LCD driver output pins from the line latch/shift

register data, selecting one of 4 levels (V0, V12, V43, VSS)

based on the S/C, FR and DISPOFF signals.

1.8. Control Logic

1.3. Data Latch Control

In the case of the segment mode, it selects the state of the

data latch, which reads in the data bus signals. The shift

direction is controlled by the control logic and for every 16

bits of data read in, the selection signal shifts one bit, based

on the state of the control circuit.

It controls the operation of each block. In the case of the

segment mode, when an LP signal has been input, all blocks

are reset and the control logic waits for the selection signal

output from the active control block. Once the selection

signal has been output, operation of the data latch and data

transmission are controlled, 160 bits of data are read in, and

the chip is deselected.

1.4. Data Latch

In the case of the segment mode, it latches the data on the

data bus. The latched state of each LCD driver output pin is

controlled by the control logic and the data latch control 160

bits of data are read in 20 sets of 8 bits.

In the case of the common mode, it controls the direction of

the data shift.

10

NT7701

2. LCD Driver Output Voltage Level

The relationship amongst the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table

below:

2.1. Segment Mode

FR

Latch Data

Driver Output Voltage Level (Y1 - Y160)

DISPOFF

L

H

L

H

L

V43

V5

H

X

V12

V0

H

X

V5

Here, VSS ≤ V5 < V43 < V12 <V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care

2.2. Common Mode

FR

Latch Data

Driver Output Voltage Level (Y1 - Y160)

DISPOFF

L

H

L

H

L

V43

V0

H

X

V12

V5

H

X

V5

Here, VSS ≤ V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care

Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular

voltage, which assigned by specification for each power pin.

That time "Don't care" should be fixed to "H" or "L", avoiding floating.

11

NT7701

3. Relationship between the Display Data and Driver Output Pins

3.1. Segment Mode:

(a) 4-bit Parallel Mode

Number of Clock

Data

MD

L/R

EIO1 EIO2

Input

40clock

Y1

Y2

Y3

Y4

Y160

Y159

Y158

Y157

39clock

Y5

Y6

Y7

Y8

Y156

Y155

Y154

Y153

38clcok

~

3clock

Y149

Y150

Y151

Y152

Y12

Y11

Y10

Y9

2clock

Y153

Y154

Y155

Y156

Y8

Y7

Y6

Y5

1clock

Y157

Y158

Y159

Y160

Y4

Y3

Y2

Y1

D0

D1

D2

D3

D0

D1

D2

D3

Y9

Y10

Y11

Y12

Y152

Y151

Y150

Y149

L

Output Input

L

H

Input Output

(b) 8-bit Parallel Mode

Number of Clock

Data

MD

L/R

EIO1 EIO2

Input

20clock

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y160

Y159

Y158

Y157

Y156

Y155

Y154

Y153

19clock

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y152

Y151

Y150

Y149

Y148

Y147

Y146

Y145

18clcok

Y17

~

3clock

Y137

Y138

Y139

Y140

Y141

Y142

Y143

Y144

Y24

Y23

Y22

Y21

Y20

2clock

Y145

Y146

Y147

Y148

Y149

Y150

Y151

Y152

Y16

Y15

Y14

Y13

Y12

1clock

Y153

Y154

Y155

Y156

Y157

Y158

Y159

Y160

Y8

Y7

Y6

Y5

Y4

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y144

Y143

Y142

Y141

Y140

Y139

Y138

Y137

H

L

Output Input

H

Input Output

Y19

Y18

Y17

Y11

Y10

Y9

Y3

Y2

Y1

12

NT7701

3.2. Common Mode

MD

L/R

Data Transfer Direction

Y160 to Y1

EIO1

Output

Input

EIO2

D7

L (shift to left)

H (shift to right)

Input

X

L

(Single)

Y1 to Y160

Output

X

Y160 to Y81

Y80 to Y1

L (shift to left)

Output

Input

H

(Dual)

Y1 to Y80

H (shift to right)

Output

Input

Y81 to Y160

Here, L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care

Note: "Don't care" should be fixed to "H" or "L", avoiding floating.

13

NT7701

4. Connection Examples of Segment Drivers

4.1. Case of L/R = “L”

first data

last data

(data taking flow)

Y160 ---------------------->Y1

EIO2

EIO1

L/R

EIO2

EIO1

EIO2

EIO1

L/R

XCK

LP

MD

FR

D0 - D7

/8

V

SS

4.2 Case of L/R = “H”

V

DD

D0 - D7

/8

FR

MD

LP

XCK

L/R

EIO1

V

SS

EIO1

EIO2

EIO1

EIO2

Y1 ---------------------->Y160

(data taking flow)

first data

Y1 ---------------------->Y160

last data

14

NT7701

5. Timing Waveform of 4-Device Cascade Connection of Segment Drivers.

FR

LP

XCK

First data

Last data

n 1 2

D0 - D7

device A

device B

device C

device D

EI

H

L

(device A)

EO

(device A)

EO

(device B)

EO

(device C)

n: 4-bit parallel mode 40

8-bit parallel mode 20

15

NT7701

6. Connection Examples for Common Drivers

First

Last

Y160

EIO2

Y1

Y160

EIO2

Y1

Y160

EIO2

Y1

EIO1

D

LP

SS(VDD

V )

V

SS

V

DISPOFF

FR

Single Mode (Shifting towards the left)

FR

CS

DISPOFF

V

DD

SS

SS(VDD

V

)

LP

EIO1

EIO2

Y160

DI

EIO1

Y1

EIO2

EIO1

EIO2

Y1

Y160

Y1

Y160

First

Last

Single Mode (Sifting towards the right)

16

NT7701

First1

Last1 First2

Last2

Y160

EIO2

Y1

Y160 Y81 Y80

EIO2

Y1

Y160

EIO2

Y1

EIO1

D1

LP

D2

V

SS (VDD

)

V

DD

V

SS

DISPOFF

FR

Dual mode (Shifting towards the left)

FR

DISPOFF

V

DD

SS (VDD

V

)

D2

LP

D1

EIO1

Y1

EIO2

Y160

EIO1

Y1

EIO2

EIO1

EIO2

Y160

Y80 Y81 Y160

Y1

First1

Last1 First2

Last2

Dual mode (Shifting towards the right)

17

NT7701

7. Precaution

Be careful when connecting or disconnecting the power

This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur, if a voltage is

supplied to the LCD driver power supply while the logic system power supply is floating.

The details are as follows:

ꢀ

When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore,

when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power.

We recommend that you connect a serial resistor (50-100Ω) or fuse to the LCD driver power V0 of the system as a current

limiting device. Also, set a suitable value for the resistor in consideration of the LCD display grade.

In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore connect the LCD

driver power supply after resetting logic condition of this LSI inside on DISPOFF function. After that, the DISPOFF cancel the

function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver

output pins to level VSS on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD

driver power.

When connecting the power supply, follow the recommended sequence shown.

V

DD

V

DD

V

SS

V

DD

DISPOFF

V

SS

V

0

V

0

V

SS

18

NT7701

Absolute Maximum Rating*

*Comments

DC Supply Voltage VDD . . . . . . . . . . . . -0.3V to +7.0V

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to this device.

These are stress ratings only. Functional operation of this

device under these or any other conditions above those

indicated in the operational sections of this specification is

not implied or intended. Exposure to the absolute maximum

rating conditions for extended periods may affect device

reliability.

DC Supply Voltage V0 . . . . . . . . . . . . . -0.3V to +30V

Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V

Operating Ambient Temperature . . . . -30°C to +85°C

Storage Temperature . . . . . . . . . . . . .-45°C to +125°C

Electrical Characteristics

DC Characteristics

Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted)

Parameter

Operating Voltage

Input high voltage

Input low voltage

Output high voltage

Output low voltage

Symbol

VDD

V0

Min.

2.5

Typ.

Max.

Unit

V

Condition

-

5.5

15

30

V

V_IH

0.8 V_DD

-

0.2 V_DD

-

V

D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO₁,

EIO₂and

pins

DISPOFF

V_IL

V

V_OHV_DD- 0.4

V

EIO₁, EIO₂pins, I_OH= -0.4mA

V_OL

-

+0.4

V

EIO₁, EIO₂pins, I_OL= +0.4mA

D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO₁,

Input leakage current 1

Input leakage current 2

I_IH

-

+1

-1

µA

kΩ

EIO₂and

pins, V_I= V_DD

DISPOFF

D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO₁,

I_IL

-

EIO₂and

pins, V_I= V_SS

Y_{1 -}Y₁₆₀pins,

DISPOFF

-

1.0

1.5

-

1.5

2.0

5

V₀= +30.0V

V₀= +20.0V

V_SSpin, Note 1

Output resistance

Stand-by current

R_ON

= 0.5V

∆V ON

I_SB

µA

Consumed current (1)

(Deselection)

I_DD1

-

2.0

mA

V_DDpin, Note 2

Consumed current (2)

(Selection)

I_DD2

I₀

-

8.0

1.0

mA

V_DDpin, Note 3

V₀pin, Note 4

Consumed current

Note:

1. VDD = +5.0V, V0 = +30V, VI = VSS

2. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load, EI = VDD

The input data is turned over by the data taking clock (4-bit parallel input mode)

3. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, No-load. EI = VSS

The input data is turned over by the data taking clock (4-bit parallel input mode)

4. VDD = +5.0V, V0 = +30V, fXCK = 14MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load

The input data is turned over by the data taking clock (4-bit parallel-input mode)

19

NT7701

Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted)

Parameter

Operating Voltage

Symbol

VDD

V0

Min.

2.5

Typ.

Max.

Unit

V

Condition

-

5.5

Operating Voltage

Input high voltage

Input low voltage

Output high voltage

Output low voltage

15

30

V

V_IH

0.8 V_DD

-

0.2 V_DD

-

V

D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO₁,

EIO₂and pins

DISPOFF

V_IL

V

V_OHV_DD- 0.4

V

EIO₁, EIO₂pins, I_OH= -0.4mA

EIO₁, EIO₂pins, I_OL= +0.4mA

D0 - 6, LP, L/R, FR, MD, S/C and

V_OL

-

+0.4

V

Input leakage current 1

Input leakage current 2

Output resistance

I_IH

-

+10.0

-10.0

µA

kΩ

pins, V_I= V_DD

DISPOFF

D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1,

I_IL

-

EIO2 and

pins, V_I= V_SS

Y_{1 -}Y₁₆₀pins,

DISPOFF

-

1.0

1.5

2.0

50

V₀= +30.0V

R_ON

= 0.5V

∆V ON

1.5

V₀= +20.0V

Stand-by current

I_SB

I_DD

I₀

-

V_SSpin, Note 1

V_DDpin, Note 2

V₀pin, Note 2

µA

Consumed current (1)

Consumed current (2)

80

160

Note:

1. VDD = +5.0V, V0 = +30V, fLP = 0 - 41.6kHz

2. VDD = +5.0V, V0 = +30V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load

20

NT7701

AC Characteristics

Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30, and TA = -30 to +85°C, unless otherwise noted)

Parameter

Shift clock period

Symbol

t_WCK

t_WCKH

t_WCKL

t_DS

Min.

71

23

10

20

23

0

Typ.

Max.

Unit

ns

Condition

≦

-

tr, tf

10ns, Note 1

Shift clock "H" pulse width

Shift clock "L" pulse width

Data setup time

Data hole time

t_DH

Latch pulse "H" pulse width

Shift clock rise to Latch pulse rise time

Shift clock fall to Latch pulse fall time

Latch pulse rise to Shift clock rise time

Latch pulse fall to Shift clock rise time

Input signal rise time

t_WLPH

t_LD

t_SL

25

t_LS

t_LH

t_r

50

Note 2

Input signal fall time

t_f

Enable setup time

t_S

21

t_SD

100

-

ns

Removal time

DISPOFF

t_WDL

1.2

µs

enable pulse width

Output delay time (1)

Output delay time (2)

Output delay time (3)

t_D

-

40

1.2

ns

µs

CL = 15pF

t_pd1, t_pd2

t_pd3

Note

1. Take the cascade connection into consideration.

2. (Tck - tWCKII - twckl)/2 is the maximum in the case of high speed operation.

21

NT7701

Segment Mode 2 (VSS = V5 = 0V, VDD = 2.5 - 4.5V, V0 = 15 to 30, and TA = -30 to +85°C, unless otherwise noted)

Parameter

Shift clock period

Symbol

t_WCK

t_WCKH

t_WCKL

t_DS

Min.

125

51

30

40

51

0

Typ.

Max.

Unit

ns

Condition

11ns, Note 1

≦

-

tr, tf

Shift clock "H" pulse width

Shift clock "L" pulse width

Data setup time

Data hole time

t_DH

Latch pulse "H" pulse width

Shift clock rise to Latch pulse rise time

Shift clock fall to Latch pulse fall time

Latch pulse rise to Shift clock rise time

Latch pulse fall to Shift clock fall time

Input signal rise time

t_WLPH

t_LD

t_SL

51

t_LS

t_LH

t_r

50

Note 2

Input signal fall time

t_f

Enable setup time

t_S

36

t_SD

100

-

ns

Removal time

DISPOFF

t_WDL

1.2

µs

ns

µs

enable pulse width

Output delay time (1)

Output delay time (2)

Output delay time (3)

t_D

-

78

1.2

CL = 15pF

t_pd1, t_pd2

t_pd3

Note

1. Take the cascade connection into consideration.

2. (tCK - tWCKII - tWCKL)/2 is the maximum in the case of high speed operation.

22

NT7701

Timing waveform of the Segment Mode

t

WLPH

LP

t

LD

t

SL

t

LH

t

LS

t

WCKH

t

WCKL

t

r

t

r

XCK

t

WCK

DS

tDH

D0 - D7

LAST DATA

TOP DATA

t

WDL

tSD

DISPOFF

LP

1

t

2

n

XCK

S

EI

t

D

EO

n: 4-bit parallel mode 40

8-bit parallel mode 20

FR

LP

t

pd1

t

pd2

DISPOFF

Y1 - Y160

t

pd3

23

NT7701

Common Mode (V_SS= V₅= 0V, V_DD= 2.5 - 5.5V, V₀= 15 to 30V and T_A= -30 to +85°C, unless otherwise noted)

Parameter

Shift clock period

Symbol

Min.

Typ.

Max.

Unit

Condition

≦

t_r, t_f20ns

t_WLP

250

-

ns

±

15

30

-

ns

VDD = +5.0V

10%

Shift clock "H" pulse width

t_WLPH

V

_DD= +2.5 - +4.5V

Data setup time

t_SU

t_H

Data hole time

50

-

50

-

ns

µs

ns

µs

Input signal rise time

Input signal fall time

t_r

t_f

t_SD

100

Removal time

DISPOFF

t_WDL

t_DL

t_pd1, t_pd2

t_pd3

1.2

-

enable pulse width

Output delay time (1)

Output delay time (2)

Output delay time (3)

-

200

1.2

C_L= 15pF

24

NT7701

Timing Characteristics of Common Mode

tWLP

tr

tWLPH

tSU

tf

LP

tH

EIO2

(D7)

tDL

EIO1

tWDL

tSD

DISPOFF

FR

LP

tpd1

tpd2

DISPOFF

Y1 - Y160

tpd3

L/R = "L"

25

NT7701

Application Circuit (for reference only)

EIO1

MD

SEG640

SEG639

Y1~Y160

FR

LP

S/C

L/R

D0~D7

EIO2

DISPOFF

XCK

EIO1

MD

FR

LP

S/C

L/R

D0~D7

EIO2

DISPOFF

XCK

640*480 DOT MATRIX

LCD PANEL

EIO1

MD

FR

S/C

LP

L/R

D0~D7

EIO2

DISPOFF

XCK

EIO1

MD

SEG3

SEG2

SEG1

FR

LP

S/C

L/R

C

O

M

4

C

O

M

4

C

O

M

1

C

O

M

2

C

O

M

3

D0~D7

EIO2

DISPOFF

XCK

7

8

9

0

R

(n-4)R

R

LCD controller

V

EE

V

0

V

1

V

2

V

3

V

4

V

5

V

DD

V

SS

26

NT7701

Bonding Diagram

7664um

199

54

200

53

Y

NT7701

986um

37

X

( 0 , 0 )

ALK_L

ALK_R

216

1

36

Pad Location

Pad No.

1

Designation

X

Y

Pad No.

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

Designation

EIO1

FR

X

Y

LR

VDD

SC

-3600

-3440

-3280

-3120

-2000

-1840

-1680

-1520

-1360

-1200

-1040

-880

-720

-560

-400

-240

-80

80

240

400

560

720

880

1040

1200

1360

1520

-440

2160

2320

2480

2640

2800

2960

3779

3635

3575

3525

3475

-440

-410

-350

-300

-250

-200

-150

-100

-50

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

FR

MD

SC

EIO2

D0

D1

D2

D3

D4

D5

D6

D7

GND

V5R

V43R

V12R

V0R

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

0

50

100

150

200

250

300

350

410

440

D7

XCK

Y10

Y11

DISPOFF

28

29

30

1680

1840

2000

-440

58

59

60

Y12

Y13

Y14

3425

3375

3325

440

DISPOFF

LP

27

NT7701

Pad Location (continued)

Pad No.

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Designation

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

Y31

Y32

Y33

Y34

Y35

Y36

Y37

Y38

Y39

Y40

Y41

Y42

Y43

Y44

Y45

Y46

Y47

Y48

Y49

Y50

Y51

Y52

Y53

Y54

X

Y

Pad No.

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

139

140

Designation

Y55

Y56

Y57

Y58

Y59

Y60

Y61

Y62

Y63

Y64

Y65

Y66

Y67

Y68

Y69

Y70

Y71

Y72

Y73

Y74

Y75

Y76

Y77

Y78

Y79

Y80

Y81

Y82

Y83

Y84

Y85

Y86

Y87

Y88

Y89

Y90

Y91

Y92

Y93

Y94

X

Y

3275

3225

3175

3125

3075

3025

2975

2925

2875

2825

2775

2725

2675

2625

2575

2525

2475

2425

2375

2325

2275

2225

2175

2125

2075

2025

1975

1925

1875

1825

1775

1725

1675

1625

1575

1525

1475

1425

1375

1325

440

1275

1225

1175

1125

1075

1025

975

925

875

825

775

725

675

625

575

525

475

425

375

325

275

225

175

125

75

440

25

-25

-75

-125

-175

-225

-275

-325

-375

-425

-475

-525

-575

-625

-675

28

NT7701

Pad Location (continued)

Pad No.

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Designation

Y95

X

-725

-775

-825

-875

-925

-975

Y

Pad No.

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

Designation

Y135

Y136

Y137

Y138

Y139

Y140

Y141

Y142

Y143

Y144

Y145

Y146

Y147

Y148

Y149

Y150

Y151

Y152

Y153

Y154

Y155

Y156

Y157

Y158

Y159

Y160

V0L

X

Y

440

-2725

-2775

-2825

-2875

-2925

-2975

-3025

-3075

-3125

-3175

-3225

-3275

-3325

-3375

-3425

-3475

-3525

-3575

-3635

-3779

-3438

3438

440

410

350

300

250

200

150

100

50

Y96

Y97

Y98

Y99

Y100

Y101

Y102

Y103

Y104

Y105

Y106

Y107

Y108

Y109

Y110

Y111

Y112

Y113

Y114

Y115

Y116

Y117

Y118

Y119

Y120

Y121

Y122

Y123

Y124

Y125

Y126

Y127

Y128

Y129

Y130

Y131

Y132

Y133

Y134

-1025

-1075

-1125

-1175

-1225

-1275

-1325

-1375

-1425

-1475

-1525

-1575

-1625

-1675

-1725

-1775

-1825

-1875

-1925

-1975

-2025

-2075

-2125

-2175

-2225

-2275

-2325

-2375

-2425

-2475

-2525

-2575

-2625

-2675

V0L

0

-50

V12L

V43L

V5L

-100

-150

-200

-250

-300

-350

-410

-323

V5L

GND

ALK_L

ALK_R

29

NT7701

Dummy Pad Location (Total: 10 pin)

NO

0

X

Y

NO

3

X

Y

NO

6

X

Y

NO

9

X

3600

Y

-440

-2960

-2800

-2640

-440

-2480

-2320

-2160

-440

3120

3280

3440

-440

1

4

7

2

5

8

30

NT7701

Package Information

A1

D3

A1

×

D1

144 m2

A2

n3

A2

n3

m3

C2

C1

D3

C1

D3

n2

m3

m2

m3

n2A

n2B

n2A n2B

n2B n2A

D1

m2

J

m2

J

m2

NT7701

n2

×

15 n2

r

e

f

e

f

H

D3

C1

D3

C1

m1

m3

n1

n3

C2

D2

×

B

37 m1

B

Chip Outline Dimensions

unit: µm

Symbol

Dimensions in µm

A1

A2

B

197

53

232

83

53

50

160

60

54

32

52

n1

n2

n2A

n2B

n3

r

e

f

H

J

56

67

35

32

60

35

24

23

120

202

C1

C2

D1

D2

D3

m1

m2

m3

31

NT7701

TCP Pin Layout

DUMMY

Y1

31

32

33

34

35

36

Y2

Y3

Y5

Y4

Y6

DUMMY

V0R

V12R

V43R

V5R

VSS

TEST2

TEST1

MD

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

FR

EIO1

LP

DISPOFF

XCK

D7

Y78

Y79

Y80

Y81

Y82

Y83

108

109

110

111

112

113

D6

D5

D4

D3

D2

D1

D0

EIO2

S/C

8

7

VDD

6

L/R

5

VSS

4

V5L

3

V43L

V12L

V0L

2

1

DUMMY

Y155

Y156

Y157

Y158

Y159

Y160

185

186

187

188

189

190

DUMMY

(COPPER SIDE VIEW)

32

NT7701

External view of TCP pins

33

NT7701

Cautions concerning storage:

1. When storing the product, it is recommended that it be left in its shipping package.

After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere.

2. Storage conditions :

Storage state

Storage conditions

Temperature: 5 to 30℃; humidity: 80%RH or less

unopened (less than 90 days)

After seal of broken (less than 30 days) Room temperature, dry nitrogen atmosphere

3. Don't store in a location exposed to corrosive gas or excessive dust.

4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature.

5. Don't store the product such that it is subjected to an excessive load weight, such as by stacking.

6. Deterioration of the plating may occur after long-term storage, so special care is required.

It is recommended that the products be inspected before use.

34

NT7701

Tray Information

f

e

c

W1 W2

T2 T1

X

d

g

h

W1

W2

a

b

e

g

f

h

T2

T1

SECTION X-X

Symbol Dimensions in mm

a

b

c

d

e

f

1.46

2.04

8.16

9.50

1.60

1.40

g

h

W1

W2

T1

T2

0.84

4.20

76.0

68.0

71.0

68.3

35

NT7701

Ordering Information

Part No.

Package

Au bump on chip tray

TCP Form

NT7701H-BDT

NT7701H-TABF3

36

NT7701

Product Spec. Change Notice

Version

NT7701 Specification Revision History

Content

Date

˙Chip size modified ( Due to scribe-line modified, change

7720μm x 1030μm to 7664μm x 986μm , Page 27 )

˙Gold bump size modified ( Page 31 )

2.0

1.0

Jul. 2002

Oct. 2000

Formal version release

37

型号	制造商	描述	价格	文档
NT7702	ETC	240 Output LCD Segment/Common Driver	获取价格
NT7702H-BDT	ETC	240 Output LCD Segment/Common Driver	获取价格
NT7702H-TABF4	ETC	240 Output LCD Segment/Common Driver	获取价格
NT7703	ETC	160 Output LCD Segment/Common Driver	获取价格
NT7703H-BDT	ETC	160 Output LCD Segment/Common Driver	获取价格
NT7703H-TAB18	ETC	160 Output LCD Segment/Common Driver	获取价格
NT7704	ETC	240 Output LCD Segment/Common Driver	获取价格
NT7704H-BDT	ETC	240 Output LCD Segment/Common Driver	获取价格
NT7704H-TABF4	ETC	240 Output LCD Segment/Common Driver	获取价格
NT77A10DC12V	DBLECTRO	Switching capacity up to 12A.	获取价格

NT7701H-TABF3

NT7701H-TABF3 概述

NT7701H-TABF3 数据手册

NT7701H-TABF3 相关器件

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