NTMD3P03R2/D [ETC]
Power MOSFET -3.05 Amps， -30 Volts ; 功率MOSFET -3.05安培，伏特-30\n
| 型号： | NTMD3P03R2/D |
| 厂家： | 
ETC |
| 描述： | Power MOSFET -3.05 Amps， -30 Volts
|
| 文件： | 总12页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NTMD3P03R2
Product Preview
Power MOSFET
-3.05 Amps, -30 Volts
Dual P–Channel SO–8
Features
http://onsemi.com
• High Efficiency Components in a Dual SO–8 Package
• High Density Power MOSFET with Low R
• Miniature SO–8 Surface Mount Package – Saves Board Space
• Diode Exhibits High Speed with Soft Recovery
DS(on)
–3.05 AMPERES
–30 VOLTS
• I
Specified at Elevated Temperature
• Avalanche Energy Specified
DSS
0.085 W @ V
= –10 V
GS
• Mounting Information for the SO–8 Package is Provided
P–Channel
Applications
• DC–DC Converters
D
• Low Voltage Motor Control
• Power Management in Portable and Battery–Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
G
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Rating
Symbol
Value
Unit
S
Drain–to–Source Voltage
V
–30
V
V
DSS
MARKING
DIAGRAM
Gate–to–Source Voltage – Continuous
V
±20
GS
Thermal Resistance –
Junction–to–Ambient (Note 1.)
R
P
D
I
I
171
0.73
–2.34
–1.87
–8.0
°C/W
W
A
A
A
θJA
Total Power Dissipation @ T = 25°C
A
SO–8
CASE 751
STYLE 11
ED3P03
LYWW
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4.)
D
D
8
I
DM
1
Thermal Resistance –
Junction–to–Ambient (Note 2.)
R
P
D
I
I
100
1.25
–3.05
–2.44
–12
°C/W
W
A
A
A
θJA
Total Power Dissipation @ T = 25°C
A
ED3P03 = Device Code
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4.)
D
D
L
= Assembly Location
Y
= Year
I
DM
WW
= Work Week
Thermal Resistance –
Junction–to–Ambient (Note 3.)
R
P
I
I
62.5
2.0
–3.86
–3.1
–15
°C/W
W
A
A
A
θJA
D
D
D
PIN ASSIGNMENT
Total Power Dissipation @ T = 25°C
A
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4.)
1
2
3
4
8
7
6
5
Drain–1
Drain–1
Drain–2
Drain–2
Source–1
Gate–1
I
DM
Operating and Storage
Temperature Range
T , T
J
–55 to
+150
°C
stg
Source–2
Gate–2
Single Pulse Drain–to–Source Avalanche
E
140
mJ
AS
Top View
Energy – Starting T = 25°C
J
GS
(V
= –30 Vdc, V
= –4.5 Vdc, Peak
= –7.5 Apk, L = 5 mH, R = 25 Ω)
DD
I
L
G
ORDERING INFORMATION
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
260
°C
L
Device
Package
Shipping
2500/Tape & Reel
1. Minimum FR–4 or G–10 PCB, t = Steady State.
2. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t = steady state.
NTMD3P03R2
SO–8
3. Mounted onto a 2″ square FR–4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
This document contains information on a product under
development. ON Semiconductor reserves the right to
change or discontinue this product without notice.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
January, 2001 – Rev. 0
NTMD3P03R2/D
NTMD3P03R2
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) *
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
V
Vdc
(BR)DSS
(V
GS
= 0 Vdc, I = –250 µAdc)
Temperature Coefficient (Positive)
–30
–
–
–30
–
–
D
mV/°C
µAdc
Zero Gate Voltage Drain Current
I
DSS
(V
DS
(V
DS
(V
DS
= –24 Vdc, V
= –24 Vdc, V
= –30 Vdc, V
= 0 Vdc, T = 25°C)
–
–
–
–
–
–
–1.0
–20
–2.0
GS
GS
GS
J
= 0 Vdc, T = 125°C)
J
= 0 Vdc, T = 25°C)
J
Gate–Body Leakage Current
(V = –20 Vdc, V = 0 Vdc)
I
I
nAdc
nAdc
GSS
–
–
–
–
–100
100
GS
Gate–Body Leakage Current
(V = +20 Vdc, V = 0 Vdc)
DS
GSS
GS
DS
ON CHARACTERISTICS
Gate Threshold Voltage
V
Vdc
GS(th)
(V
DS
= V , I = –250 µAdc)
–1.0
–
–1.7
3.6
–2.5
–
GS
D
Temperature Coefficient (Negative)
Static Drain–to–Source On–State Resistance
R
Ω
DS(on)
(V
GS
(V
GS
= –10 Vdc, I = –3.05 Adc)
–
–
0.063
0.090
0.085
0.125
D
= –4.5 Vdc, I = –1.5 Adc)
D
Forward Transconductance (V
DS
= –15 Vdc, I = –3.05 Adc)
g
–
5.0
–
Mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
–
–
–
520
170
70
750
325
135
iss
(V
DS
= –24 Vdc, V
= 0 Vdc,
GS
f = 1.0 MHz)
Output Capacitance
C
oss
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Notes 5. and 6.)
Turn–On Delay Time
t
–
–
–
–
–
–
–
–
–
–
–
12
16
45
45
16
42
32
35
16
2.0
4.5
22
30
80
80
–
ns
ns
d(on)
(V
DD
= –24 Vdc, I = –3.05 Adc,
D
Rise Time
t
r
V
= –10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
t
t
d(off)
R
= 6.0 Ω)
t
f
Turn–On Delay Time
Rise Time
d(on)
(V
DD
= –24 Vdc, I = –1.5 Adc,
D
t
r
–
V
= –4.5 Vdc,
GS
Turn–Off Delay Time
Fall Time
–
d(off)
R
= 6.0 Ω)
G
t
f
–
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Q
tot
Q
gs
Q
gd
25
–
nC
(V
V
= –24 Vdc,
= –10 Vdc,
= –3.05 Adc)
DS
GS
I
D
–
BODY–DRAIN DIODE RATINGS (Note 5.)
Diode Forward On–Voltage
(I = –3.05 Adc, V
= 0 V)
V
–
–
–0.96
–0.78
–1.25
–
Vdc
ns
S
GS
= 0 V, T = 125°C)
SD
(I = –3.05 Adc, V
S
GS
J
Reverse Recovery Time
t
–
–
–
–
34
18
–
–
–
–
rr
(I = –3.05 Adc, V
= 0 Vdc,
S
GS
dI /dt = 100 A/µs)
t
a
S
t
16
b
Reverse Recovery Stored Charge
Q
0.03
µC
RR
5. Indicates Pulse Test: Pulse Width = 300 µs max, Duty Cycle = 2%.
6. Switching characteristics are independent of operating junction temperature.
* Handling precautions to protect against electrostatic discharge is mandatory.
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2
NTMD3P03R2
TYPICAL ELECTRICAL CHARACTERISTICS
6
5
4
3
2
1
0
6
V
= –10 V
GS
V > = –10 V
DS
V
= –4.4 V
GS
V
= –8 V
GS
= –6 V
5
4
3
2
1
0
V
= –4 V
GS
= –4.6 V
V
GS
V
GS
V
= –4.8 V
GS
T = 25°C
T = 100°C
J
J
V
= –3.6 V
= –3.2 V
GS
= –2.8 V
V
GS
= –5 V
T = 25°C
J
V
GS
V
GS
V
GS
= –3 V
T = –55°C
V
= –2.6 V
J
GS
0
0.25 0.5
0.75
1
1.25
1.5
1.75
2
1
2
3
4
5
–V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
–V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On–Region Characteristics
Figure 2. Transfer Characteristics
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
= –3.05 A
I
= –1.5 A
D
J
D
J
T = 25°C
T = 25°C
3
4
5
6
7
8
2
3
4
5
6
7
–V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
–V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
Figure 3. On–Resistance vs. Gate–to–Source
Voltage
Figure 4. On–Resistance vs. Gate–to–Source
Voltage
1.6
1.4
0.25
0.2
I
V
= –3.05 A
= –10 V
D
GS
T = 25°C
J
V
GS
= –4.5 V
= –10 V
1.2
0.15
0.1
1
0.8
0.6
V
GS
0.05
1
2
3
4
5
6
–50
–25
0
25
50
75
100
125 150
–I , DRAIN CURRENT (AMPS)
D
T , JUNCTION TEMPERATURE (°C)
J
Figure 5. On–Resistance vs. Drain Current and
Gate Voltage
Figure 6. On Resistance Variation with
Temperature
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3
NTMD3P03R2
10000
1000
V
= 0 V
V
= 0 V
GS
V
GS
= 0 V
DS
1200
C
iss
1000
800
T = 150°C
J
C
iss
C
600
rss
T = 125°C
J
100
10
400
200
C
oss
C
rss
T = 25°C
J
0
10
6
10
14
18
22
26
30
5
0
5
10
15
20
25
30
–V
–V
GS
DS
–V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE
VOLTAGE (VOLTS)
Figure 7. Drain–to–Source Leakage Current
vs. Voltage
Figure 8. Capacitance Variation
12
10
8
30
1000
100
10
V
I
= –24 V
DS
= –3.05 A
Q
T
D
25
20
V
GS
= –10 V
V
DS
t
t
d(off)
V
GS
6
4
2
15
10
5
t
f
t
r
Q
1
Q
2
d(on)
I
= –3.05 A
T = 25°C
D
J
0
0
16
1
0
2
4
6
8
10
12
14
1
10
R , GATE RESISTANCE (Ω)
G
100
Q , TOTAL GATE CHARGE (nC)
g
Figure 9. Gate–to–Source and
Drain–to–Source Voltage vs. Total Charge
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
1000
3
V = 0 V
GS
J
V
= –24 V
DS
= –1.5 A
T = 25°C
I
V
D
2.5
2
= –4.5 V
GS
1.5
1
100
t
r
t
d(off)
t
f
t
d(on)
0.5
0
10
1
10
, GATE RESISTANCE (Ω)
100
0.2
0.4
0.6
0.8
1
1.2
R
–V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
SD
G
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
Figure 12. Diode Forward Voltage vs. Current
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4
NTMD3P03R2
100
10
V
= 12 V
GS
SINGLE PULSE
= 25°C
1.0 ms
T
C
di/dt
10 ms
I
S
dc
1.0
t
rr
t
a
t
b
TIME
0.1
R
LIMIT
DS(on)
0.25 I
THERMAL LIMIT
PACKAGE LIMIT
t
p
S
I
S
0.01
1
1.0
10
100
–V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
Figure 14. Diode Reverse Recovery Waveform
1.0
D = 0.5
0.2
0.1
0.1
Normalized to R
at Steady State (1″ pad)
0.05
0.02
θJA
50.9 Ω
Chip
Junction
2.32 Ω
18.5 Ω
37.1 Ω
56.8 Ω
24.4 Ω
0.0014 F 0.0073 F 0.022 F
0.105 F
0.484 F
1E+02
3.68 F
0.01
Ambient
Single Pulse
1E–02
0.01
1E–03
1E–01
1E+00
1E+01
1E+03
t, TIME (s)
Figure 15. FET Thermal Response
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5
NTMD3P03R2
INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self–align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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6
NTMD3P03R2
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177–189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER
JOINT
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
200°C
150°C
100°C
5°C
160°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 16. Typical Solder Heating Profile
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7
NTMD3P03R2
PACKAGE DIMENSIONS
SO–8
CASE 751–07
ISSUE W
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
8
5
4
S
M
M
B
0.25 (0.010)
Y
1
K
–Y–
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
–Z–
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
M
J
H
D
K
M
N
S
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
0.020
0.244
M
S
S
X
0.25 (0.010)
Z
Y
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
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8
NTMD3P03R2
Notes
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9
NTMD3P03R2
Notes
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10
NTMD3P03R2
Notes
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11
NTMD3P03R2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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NTMD3P03R2/D
相关型号：
NTMD4102PR2G
6.5A, 20V, 0.019ohm, 2 CHANNEL, P-CHANNEL, Si, POWER, MOSFET, CASE 751-07, SOIC-8
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NTMD4184PF
Power MOSFET and Schottky Diode -30 V, -4.0 A, Single P-Channel with 20 V, 2.2 A, Schottky Barrier Diode
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NTMD4184PFR2G
Power MOSFET and Schottky Diode -30 V, -4.0 A, Single P-Channel with 20 V, 2.2 A, Schottky Barrier Diode
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