NX29F010-70W [ETC]
x8 Flash EEPROM ; X8闪存EEPROM\n
| 型号： | NX29F010-70W |
| 厂家： | 
ETC |
| 描述： | x8 Flash EEPROM
|
| 文件： | 总25页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NX29F010
1M-BIT (128K x 8-bit)
CMOS, 5.0V Only
ULTRA-FAST SECTORED FLASH MEMORY
JUNE 2000
FEATURES
• Ultra-fastPerformance
• Flexiblesectorarchitecture
– 35, 45, 55, 70, and 90 ns max. access times
– Erase any of eight uniform sectors or full chip erase
– Sectorprotection/unprotectionusingPROM
programmingequipment
• TemperatureRanges
– Commercial0oc-70oc
– Industrial-40oc-85oc
• 100,000Program/Erasecycles
• Single 5V-only Power Supply
• Embeddedalgorithms
– 5V ± 10% for Read, Program, and Erase
– Automatically programs and verifies data at
specifiedaddress
– Auto-programs and erases the chip or any
designatedsector
• CMOS Low Power Consumption
– 20 mA (typical) active read current
– 30 mA (typical) Program/Erase current
• CompatiblewithJEDEC-StandardPinouts
– 32-pin DIP, PLCC, TSOP
• Data/Polling and Toggle Bits
• Program/functionCompatiblewithAM29F010
– No system firmware changes
– Detect program or erase cycle completion
– UsessamePROMprogrameralgorithm
DESCRIPTION
Principles of Operation
TheNexFlashNX29F010isa1Megabit(131,072bytes)
single 5.0V-only Sectored Flash Memory. The NX29F010
providesin-systemprogrammingwiththestandardsystem
5.0V-onlyVccsupplyandcanbeprogrammedorerasedin
standard PROM programmers.
Onlyasingle5.0Vpowersupplyisrequiredforbothreadand
writefunctions.Programoreraseoperationsdonotrequire
12.0VVPP.Internallygeneratedandregulatedvoltagesare
provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single power supply Flash standard. Commands
are written to the command register using standard micro-
processorwritetimings.Registercontentsserveasinputto
an internal state machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
The NX29F010 offers access times of 35, 45, 55, 70, and
90 ns allowing high-speed controller and DSPs' to operate
without wait states. Byte-wide data appears on DQ0-DQ7.
Separate chip enable (CE), write enable (WE), and output
enable (OE) controls eliminates bus contention.
Power consumption is greatly reduced when the system
places the device into the Standby Mode.
The device is offered in 32-pin PLCC, TSOP, and PDIP
packages.
Executing the Program Command Sequence invokes the
Embedded Program Algorithm, an internal algorithm that
automatically times the program pulse widths and verifies
proper cell margin.
ThisdocumentcontainsPRELIMINARYdata.NexFlashreservestherighttomakechangestoitsproductsatanytimewithoutnoticeinordertoimprovedesignandsupplythebestpossibleproduct.We
assumenoresponsibilityforanyerrorswhichmayappearinthispublication.©Copyright1998,NexFlashTechnologies,Inc..
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Executing the Erase Command Sequence invokes the
Embedded Erase Algorithm, an internal algorithm that
automaticallypre-programsthearraytoallzeros(ifitisnot
alreadyprogrammed)beforeexecutingtheeraseoperation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin during erase.
the data contents of other sectors. The device is erased
before it is shipped to customers.
The hardware data protection includes a low Vcc detector
that automatically inhibits write operations during power
transitions. The hardware sector protection feature will
disablebothprogramanderaseoperationsinanycombina-
tion of the sectors of memory, and is implemented using
standardEPROMprogrammingalgorithm.
ByreadingtheDQ7(DataPolling)andDQ6(toggle)status
bits,thehostsystemcandetectwhetheraprogramorerase
operationiscomplete.Aftercompletion,thedeviceisready
to read array data or accept another command.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. Data are
programmedonebyteatatimeusingtheEPROMprogram-
ming algorithm of hot electron injection.
Thesectorerasearchitectureisdesignedtoallowmemory
sectors to be erased and reprogrammed without affecting
DQ7-DQ0
8
VCC
GND
ERASE VOLTAGE
GENERATOR
INPUT/OUTPUT
BUFFERS
STATE
CONTROL
WE
8
8
COMMAND
REGISTER
PGM VOLTAGE
GENERATOR
STB
DATA
LATCH
CHIP ENABLE/
OUTPUT ENABLE
LOGIC
CE
OE
8
STB
8
VCC
DETECTOR
TIMER
8
Y-DECODER
Y-GATING
CELL
MATRIX
A0-A16
X-DECODER
Figure 1. NX29F010 Block Diagram
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PIN CONFIGURATIONS
Table 1. Pin Descriptions
NC
A16
A15
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A0-A16
DQ0-DQ7
CE
Address Inputs
2
DataInputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
PowerSupplyVoltage
Ground
3
4
A14
A13
A8
OE
5
WE
A6
6
Vcc
A5
7
A9
A4
8
A11
OE
GND
NC
A3
9
NoInternalConnection
A2
10
11
12
13
14
15
16
A10
CE
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
Figure 2. NX29F010 32-pin Plastic DIP
INDEX
A11
A9
A8
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
4
3
2
1
32 31 30
2
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
5
6
7
8
9
A14
A13
A8
3
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
4
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
5
6
A9
7
8
A11
OE
9
A2 10
A1 11
10
11
12
13
14
15
16
A10
CE
A0 12
DQ0 13
DQ7
A6
A5
A4
A1
A2
A3
14 15 16 17 18 19 20
Figure 3. NX29F010 32-pin PLCC
Figure 4. NX29F010 32-pin TSOP
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BUSOPERATIONS
Table 2. Device Bus Operations(1, 2)
Operation
CE
OE
WE
Address(A16-A0)
DQ0-DQ7
Read
L
L
H
X
H
H
L
AIN
AIN
X
Data Out
Data In
High-Z
Write
L
VCC ± 0.5V
L
Standby
OutputDisable
X
H
X
High-Z
Notes:
1. L = VIL , H = VIH , X = Don't care, AIN = Address In.
2. The sector protect and sector unprotect functions must be implemented via programming equipment.
See the Sector Protection/Unprotection section.
Requirements for Reading Array Data
Upondevicepower-up,orafterahardwarereset,theinternal
state machine is set for reading array data. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device
address inputs produce valid data on the device data
outputs. The device remains enabled for read access until
the command register contents are altered.
Table 3. Sector Addresses Table
Sector
A16 A15 A14
AddressRange
00000H-03FFFH
04000H-07FFFH
08000H-0BFFFH
0C000H-0FFFFH
10000H-13FFFH
14000H-17FFFH
18000H-1BFFFH
1C000H-1FFFFH
Sector A0
Sector A1
Sector A2
Sector A3
Sector A4
Sector A5
Sector A6
Sector A7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The system must drive the CE and OE pins to VIL to read
array data from the outputs. CE is the power control and
selects the device. OE is the output control that passes
arraydatatotheoutputpins.DuringaREADoperation,WE
must remain at VIH.
After the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
DQ7-DQ0.Standardreadcycletimingsapplyinthismode.
Refertothe"Auto-selectModeandAuto-selectCommand
Sequence" sections for more information.
Write Commands/Command Sequences
The system must drive WE and CE to VIL, and OE to VIH to
write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory).
Program and Erase Operation Status
Aneraseoperationcaneraseonesector, multiplesectors,
ortheentiredevice.TheSectorAddressTable(seeTable3)
indicate the address space that each sector occupies. A
"sector address" consists of the address bits required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip.
By reading the status bits on DQ7-DQ0, the system may
checkthestatusoftheoperationduringaneraseorprogram
operation.
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Standby Mode
In the Standby Mode, current consumption is greatly
reduced,andtheoutputsareplacedinthehighimpedance
state, independent of the OE input. The system can place
the device in the standby mode when it is not reading or
writing to the device.
sector protection, the sector address must appear on the
appropriate highest order address bits. Refer to the corre-
sponding Sector Address Table (Table 3). The Command
Definitionstableshowstheremainingaddressbitsthatare
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
correspondingidentifiercodeonDQ7-DQ0.
The device enters the CMOS standby mode when the CE
pinisheldatVCC ± 0.5V.ThedeviceenterstheTTLstandby
mode when CE is held at VIH. The device requires the
standard access time (tCE) before it is ready to read data.
To access the auto-select codes in-system, the host
system can issue the auto-select command via the
command register, as shown in the Command Definitions
table. This method does not require VID. See "Command
Definitions" for details on using the auto-select mode.
Ifthedeviceisdeselectedduringerasureorprogramming,
the device draws active current until the operation is
completed.
Sector Protection/Unprotection
Output Disable Mode
The hardware sector protection feature disables both pro-
gram and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
When the OE = VIH, the output from the device is disabled
andtheoutputpinsareplacedinthehigh-impedancestate.
Auto-select Mode
Sector protection/unprotection procedure requires a high
voltage(VID)onaddresspinA9andthecontrolpins.Details
on this method are provided in a supplement. Contact an
NexFlashrepresentativetoobtainacopyoftheappropriate
document.
Theauto-selectmodeprovidesaccesstothemanufacturer
and device equivalent codes, as well as sector protection
verification codes, via the DQ7-DQ0 pins. This mode is
primarilyintendedforprogrammingequipmenttoautomatically
match a device to be programmed with its corresponding
programming algorithm. However, the auto-select codes
can also be accessed in-system through the command
register.
Thedeviceisshippedwithallsectorsunprotected.NexFlash
offers the option of programming and protecting sectors at
its factory prior to shipping the device. Contact a NexFlash
representative for details.
Whenusingprogrammingequipment,theauto-selectmode
requires VID (11.5V to 12.5V) on address pin A9. Address
pins A1 and A0 must be as shown in Auto-select Codes
(HighVoltageMethod),Table4.Inaddition,whenverifying
It is possible to determine whether a sector is protected or
unprotected. See "Auto-select Mode" for details.
Table 4. Auto-select Codes (High Voltage Method)
Description
CE
OE
WE
A16-A14
A13-A10
A9
A8-A2
A1
A0
DQ7-DQ0
Manufacturer
Equivalent ID
L
L
H
X
X
VID
X
L
L
01(Hex)
Device
Equivalent ID
L
L
L
L
H
H
X
X
X
VID
X
X
L
H
L
20(Hex)
Sector Protection
Verification
SA
VID
H
01H
(protected)
00H
(unprotected)
Note:
1. L = VIL , H = VIH , VID = 11.5 TO 12.5V , SA = ADDRESS SECTOR , X = Don't care.
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Hardware Data Protection
The system must issue the reset command to re-enable the
deviceforreadingarraydataiftheerrorstatusbit,DQ5,isset
high after an erase or program operation, or while in the
auto-select mode. See the "Reset Command" section, next.
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertentwrites(refertotheCommandDefinitionstable).
In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which
might otherwise be caused by spurious system level
signalsduringVCC power-upandpower-downtransitions,or
from system noise.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operation's table provides the read parameters, and
ReadOperationTimingsdiagramshowsthetimingdiagram.
Reset Command
Write Pulse "Glitch" Protection
Theresetcommandmaybewrittenbetweenthesequence
cycles in an erase command sequence before erasing
begins. Thisresetsthedeviceforreadingarraydata. Once
erasure begins, however, the device ignores reset com-
mands until the operation is complete.
Noise pulses of less than 5 ns (typical) on OE, CE, or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL,
CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE
must be a logical zero while OE is a logical one.
Theresetcommandmaybewrittenbetweenthesequence
cycles in a program command sequence before program-
ming begins. This resets the device to reading array data.
Once programming begins, however, the device ignores
reset commands until the operation is complete.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power-up, the device
does not accept commands on the rising edge of WE. The
internal state machine is automatically reset to reading
arraydataonpower-up.
Theresetcommandmaybewrittenbetweenthesequence
cycles in an auto-select command sequence.
Onceintheauto-selectmode, theresetcommandmustbe
written to return to reading array data.
If the error status bit, DQ5, goes high during a program or
erase operation, writing the reset command returns the
device to reading array data.
COMMAND DEFINITIONS
Writingspecificaddressanddatacommandsorsequences
intothecommandregisterinitiatesdeviceoperations. The
Command Definitions Table 5 defines the valid register
command sequences. Writing incorrect address and data
valuesorwritingthemintheimpropersequenceresetsthe
device to reading array data.
Auto-select Command Sequence
The auto-select command sequence allows the host sys-
tem to access the manufacturer and device equivalent
codes,anddetermineswhetherornotasectorisprotected.
The Command Definitions Table 5 shows the address and
data requirements. This method is an alternative to that
shown in the Auto-select Codes (High Voltage Method)
Table 4, which is intended for PROM programmers and
requires VID on address bit A9.
All addresses are latched on the falling edge of WE or CE,
whichever happens later. All data is latched on the rising
edge of WE or CE, whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
section.
The auto-select command sequence is initiated by writing
two unlock cycles, followed by the auto-select command.
The device then enters the auto-select mode, and the
system may read at any address any number of times,
withoutinitiatinganothercommandsequence.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
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Table 5. Command Definitions
Bus Cycles (2)
(Hexadecimal)
Command(1)
1st
2nd
3rd
4th
5th
6th
Sequence
Read(3,4)
Reset(5)
Cycles Addr Data Addr Data
Addr Data
Addr Data
Addr Data Addr Data
1
1
RA
RD
XXXX F0
Auto-select(6)
ManufacturerEquiv. ID 4
5555 AA
5555 AA
5555 AA
2AAA 55
2AAA 55
2AAA 55
5555 90
5555 90
5555 90
XX00 01
XX01 20
(SA) 00
X02 01
PA PD
5555 AA
5555 AA
Device Equiv. ID
Sector Protect
Verify(7,8)
4
4
Program(9)
4
6
6
5555 AA
5555 AA
5555 AA
2AAA 55
2AAA 55
2AAA 55
5555 A0
5555 80
5555 80
Chip Erase
2AAA 55
2AAA 55
5555 10
SA 30
Sector Erase
Notes:
1. Bus Operations are described in Table 2.
2. All command bus cycles are write operations, except when reading array or auto-select data.
3. No unlock or command cycles are required when reading array data.
4. RA = Address of the memory location to be read; RD = Data read from location RA during read operation
5. The Reset command is required to return to reading array data when device is in the auto-select mode, or if DQ5 goes high
(while the device is providing status data).
6. The fourth cycle of the "Auto-select Command Sequence" is a read operation.
7. The data is 00H for an unprotected sector and 01h for a protected sector. See "Auto-select Command Sequence" for more
information.
8. SA = Address of the sector to be verified (in auto-select mode) or erased. Address bits A16-A14 uniquely select any sector
9. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later; PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse,
whichever happens first.
10. Address bit A16 and A15 =x (don't care) for all address commands except for Program Address (PA), Read Address (RA) and
Sector Address (SA).
11. X = Don't Care.
A read cycle at address XX00H or retrieves the manufac-
turer code. A read cycle at address XX01H returns the
devicecode.Areadcyclecontainingasectoraddress(SA)
and the address 02H in returns 01H if that sector is
protected, or 00H if it is unprotected. Refer to the Sector
Address tables for valid sector addresses.
gram address and data are written next, which in turn initiate
theEmbeddedProgramalgorithm.Thesystemisnotrequired
to provide further controls or timings. The device automati-
callyprovidesinternallygeneratedprogrampulsesandverify
theprogrammedcellmargin.TheCommandDefinitionsTable
(Table 5) shows the address and data requirements for the
byteprogramcommandsequence.
The system must write the reset command to exit the
auto-select mode and return to reading array data.
When the Embedded Program algorithm is complete, the
devicethenreturnstoreadingarraydataandaddressesare
no longer latched. The system can determine the status of
the program operation by using DQ7 or DQ6.
See "Write Operation Status" for information on these
status bits.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program setup command. The pro-
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Commands written to the device while the Embedded
Program Algorithm is in progress are ignored.
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a setup command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogrampriortoerase.TheEmbeddedErasealgorithm
automatically preprograms and verifies the entire memory
for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings
during these operations. The Command Definitions table
showstheaddressanddatarequirementsforthechiperase
commandsequence.
Programmingisallowedinanysequenceandacrosssector
boundaries.Abitcannotbeprogrammedfroma'0'back
to a '1'. Attempting to do so may halt the operation and set
the error status bit, DQ5, to '1', or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is still
'0'. Only erase operations can convert a '0' to a '1'.
Note: See Command Definitions (Table 5) for program
command sequence.
Commands written to the chip while the Embedded Erase
Algorithm is in progress are ignored.
START
Thesystemcandeterminethestatusoftheeraseoperation
by using DQ7 or DQ6. See "Write Operation Status" for
information on these status bits. When the Embedded
Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
WRITE PROGRAM
COMMAND
SEQUENCE
Figure 6 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC Charac-
teristics" for parameters, and to the Chip/Sector Erase
Operation Timings for timing waveforms.
DATA POLL
FROM
SYSTEM
EMBEDDED
PROGRAM
ALGORITHM
IN PROGRESS
Sector Erase Command Sequence
NO
VERIFY
Sector erase is a six bus cycle operation. The sector erase
commandsequenceisinitiatedbywritingtwounlockcycles,
followed by a setup command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions Table (Table 5) shows the address and data
requirements for the sector erase command sequence.
DATA?
YES
NO
LAST
ADDRESS?
INCREMENT
ADDRESS
The device does not require the system to preprogram the
memory prior to erase. The embedded erase algorithm
automatically programs and verifies the sector for an all
zerodatapatternpriortoelectricalerase.Thesystemisnot
required to provide any controls or timings during these
operations.
YES
PROGRAMMING
COMPLETE
Figure 5. Program Operation
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After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period, addi-
tional sector addresses and sector erase commands may
be written. Loading the sector erase buffer may be done in
anysequence,andthenumberofsectorsmaybefromone
sector to all sectors. The time between these additional
cycles must be less than 50 µs, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts be
disabled during this time to ensure all commands are
accepted. The interrupts can be re-enabled after the last
Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be
less than 50 µs, the system need not monitor DQ3. Any
command during the time-out period resets the device to
readingarraydata.Thesystemmustrewritethecommand
sequence and any additional sector addresses and
commands.
START
WRITE ERASE
COMMAND
SEQUENCE
DATA POLL
FROM
SYSTEM
EMBEDDED
ERASE
ALGORITHM
IN PROGRESS
NO
DATA = FFH?
YES
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the "DQ3: Sector Erase
Timer"section.)Thetime-outbeginsfromtherisingedgeof
the final WE pulse in the command sequence.
ERASURE
COMPLETE
Once the sector erase operation has begun, all other
commandsareignored.
When the embedded erase algorithm is complete, the
device returns to reading array data and addresses are no
longerlatched. Thesystemcandeterminethestatusofthe
erase operation by using DQ7 or DQ6. Refer to
"WriteOperationStatus"forinformationonthesestatusbits.
Figure 6. Erase Operation
Notes:
1. For Erase Command Sequence. See Command Definitions
table.
2. See "DQ3: Sector Erase Timer" for more information.
Figure 6 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
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WRITE OPERATION STATUS
The device provides several bits to determine the status of
awriteoperation:DQ3,DQ5,DQ6,andDQ7.DQ7andDQ6
each offer a method for determining whether a program or
eraseoperationiscompleteorinprogress.Table6andthe
following subsections describe the functions of these bits.
START
READ
DQ7-DQ0
ADDR = VA
DQ7: Data Polling
The Data Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted. Data Polling is valid after the rising edge of the final
WE pulse in the program or erase command sequence.
YES
DQ7 = DATA?
NO
During the Embedded Program algorithm, the device
outputsonDQ7thecomplementofthedatumprogrammed
to DQ7. When the Embedded Program algorithm is com-
plete, the device outputs the true datum programmed to
DQ7.Thesystemmustprovidetheprogramaddresstoread
valid status information on DQ7. If a program address falls
within a protected sector, Data Polling on DQ7 is active for
approximately2µs,thenthedevicereturnstoreadingarray
data.
NO
DQ5 = 1?
YES
READ
DQ7-DQ0
ADDR = VA
During the Embedded Erase algorithm, Data Polling pro-
ducesa"0"onDQ7. WhentheEmbeddedErasealgorithm
is complete, Data Polling produces a "1" on DQ7. This is
analogoustothecomplement/truedatumoutputdescribed
for the Embedded Program algorithm: the erase function
changesallthebitsinasectorto"1";priortothis,thedevice
outputsthe"complement,"or"0".Thesystemmustprovide
anaddresswithinanyofthesectorsselectedforerasureto
read valid status information on DQ7.
YES
DQ7 = DATA?
NO
FAIL
PASS
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on DQ7 is
active for approximately 100 µs, then the device returns to
readingarraydata.Ifnotallselectedsectorsareprotected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within
any sector selected for erasure. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 ="1" because
DQ7 may change simultaneously with DQ5.
When the system detects DQ7 has changed from the
complementtotruedata,itcanreadvaliddataatDQ7-DQ0
on the following read cycles. This is because DQ7 may
changeasynchronouslywithDQ0-DQ6whileOutputEnable
(OE) is asserted low. The Data Polling Timings (During
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this.
Figure 7. Data Polling Algorithm
Table 6 shows the outputs for Data Polling on DQ7.
Figure 7 shows the Data Polling algorithm.
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DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final WE pulse in the command
sequence (prior to the program or erase operation), and
during the sector erase time-out.
START
ADDR = VA
READ DQ7-DQ0(1)
DuringanEmbeddedProgramorErasealgorithmoperation,
successive read cycles to any address cause DQ6 to
toggle. (ThesystemmayuseeitherOE orCE tocontrolthe
read cycles.) When the operation is complete, DQ6 stops
toggling.
OLD_DQ6 < DQ6
ADDR = VA
READ DQ7-DQ0
NEW_DQ6 < DQ6
After an erase command sequence is written, if all sectors
selectedforerasingareprotected,DQ6togglesforapproxi-
mately 100 µs, then returns to reading array data. If not all
selectedsectorsareprotected,theEmbeddedErasealgo-
rithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
YES
NEW_DQ6 =
OLD_DQ6?
NO
If a program address falls within a protected sector, DQ6
togglesforapproximately2µsaftertheprogramcommand
sequence is written, then returns to reading array data.
NO
DQ5 = 1?
YES
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 8 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram.
OLD_DQ6 < DQ6
ADDR = VA
READ DQ7-DQ0
NEW_DQ6 < DQ6
Reading Toggle Bit DQ6
RefertoFigure8forthefollowingdiscussion.Wheneverthe
systeminitiallybeginsreadingtogglebitstatus,itmustread
DQ7-DQ0 at least twice in a row to determine whether a
toggle bit is toggling.
YES
NEW_DQ6 =
OLD_DQ6?
Typically, a system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with
the first. If the toggle bit is not toggling, the device has
completedtheprogramoreraseoperation.Thesystemcan
read array data on DQ7-DQ0 on the following read cycle.
NO
FAIL
PASS
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as
DQ5 changes to '1'. See text.
3. VA = Valid Address.
Figure 8. Toggle Bit Algorithm
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However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the
section on DQ5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as DQ5 went high. If the
togglebitisnolongertoggling, thedevicehassuccessfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation suc-
cessfully, andthesystemmustwritetheresetcommandto
return to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the sys-
tem may read DQ3 to determine whether or not an erase
operationhasbegun.(Thesectorerasetimerdoesnotapply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
eachadditionalsectorerasecommand.Whenthetime-out
iscomplete,DQ3switchesfrom"0"to"1."Thesystemmay
ignore DQ3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50 µs. See also the "Sector Erase Command
Sequence" section.
The remaining scenario is that the system initially deter-
mines that the toggle bit is toggling and DQ5 has not gone
high.Thesystemmaycontinuetomonitorthetogglebitand
DQ5 through successive read cycles, determining the
status as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In this
case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 8).
After the sector erase command sequence is written, the
system should read the status on DQ7 (Data Polling) or
DQ6 (Toggle Bit I) to ensure the device has accepted the
command sequence, and then read DQ3. If DQ3 is "1", the
internally controlled erase cycle has begun; all further
commands are ignored until the erase operation is com-
plete. If DQ3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase
command. If DQ3 is high on the second status check, the
last command might not have been accepted. Table 6
shows the outputs for DQ3.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceededaspecifiedinternalpulsecountlimit.Underthese
conditions DQ5 produces a "1." This is a failure condition
that indicates the program or erase cycle as not success-
fully completed.
Table 6. Write Operation Status
TheDQ5failureconditionmayappearifthesystemtriesto
program a "1" to a location that is previously programmed
to "0." Only an erase operation can change a "0" back to a
"1."Underthiscondition,thedevicehaltstheoperation,and
when the operation has exceeded the timing limits, DQ5
produces a "1."
Operation
DQ7(1)
DQ7# Toggle
DQ6
DQ5(2) DQ3
Embedded
0
N/A
ProgramAlgorithm
Embedded
0
Toggle
0
1
EraseAlgorithm
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
Notes:
1. DQ7 requires a valid address when reading status
information.
2. DQ5 switches to '1' when an Embedded Program or
Embedded Erase operation has exceeded the maximum
timing limits. See "DQ5: Exceeded Timing Limits" for more
information.
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM
Terminal Voltage with Respect to GND
Any Pin Except A9
–2.0 to +7.0(2)
–2.0 to +12.5(2)
–2.0 to +7.0(2)
V
V
V
A9
VCC
ISC
TA
Output Short Circuit Current (Max. Limit)
Commercial Operating Temperature
Industrial Operating Temperature
StorageTemperature
200
mA
°C
°C
°C
0 to +70
TA
–40 to +85
–65 to +125
TSTG
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Minimum DC inputs, I/O, and A9 pins voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for
periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V, which may overshoot to Vcc + 2.0V
for periods less than 20 ns. Maximum DC voltage on A9 is +12.5V that may overshoot to +12.5V for periods less
than 20 ns.
3. No more than one output shorted at one time. Duration of short shall not exceed one second.
20 ns
20 ns
20 ns
Vcc + 2.0V
Vcc + 0.5V
+0.8V
—0.5V
—2.0V
+2.0V
20 ns
20 ns
20 ns
Figure 9. Maximum Negative Overshoot Waveform
Figure 10. Maximum Positive Overshoot Waveform
OPERATING RANGE
Range
Ambient Temperature
0°C to +70°C
VCC
Commercial
Industrial(1)
5V ± 10%
5V ± 10%
–40°C to +85°C
Note:
1. Operating ranges define those limits between which the
functionally of the device is guaranteed.
CAPACITANCE
Symbol
CIN
Parameter
Conditions
Typ.
Max.
Unit
InputCapacitance
VIN = 0V
3
6
pF
COC/C
OutputandControl
Capacitance
VOUT = 0V
7
12
pF
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DC CHARACTERISTICS: TTL/NMOS COMPATIBLE
Symbol
ParameterDescription
TestConditions
Min.
Max.
Unit
ILI
InputLeakageCurrent
A9 Input Current
VCC = VCC Max., VIN = VCC to GND
VCC = VCC Max., A9 = 12.5V
VCC = VCC Max., VOUT = GND to VCC
VCC = VCC Max., CE and OE = VIH
VCC = VCC Max., CE = VIL, OE = VIH
VCC = VCC Max., CE = VIL, OE = VIH
—
—
—
—
—
±1.0
50
±1.0
1.0
30
50
µA
µA
µA
mA
mA
mA
V
ILI2
ILO
OutputLeakageCurrent
VCC StandbyCurrent
VCC ActiveCurrent(1)
VCC Active Current(2,3)
Input Low Voltage
Input High Voltage
Voltage For Auto-select and
TemporarySectorUnprotect
ICCS
ICC1
ICC2
VIL
VIH
VID
—
–0.5
2.0
11.5
0.8
VCC + 0.5
12.5
V
V
VCC = 5.0V
VOL
VOH
OutputLowVoltage
OutputHighVoltage
IOL = 12 mA, VCC = VCC Min.
IOH = –2.5 mA, VCC = VCC Min.
—
2.4
0.45
—
V
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz with OE at VIH.
2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
3. Not 100% tested.
DC CHARACTERISTICS: CMOS COMPATIBLE
Symbol
ParameterDescription
TestConditions
Min.
Max.
Unit
ILI
InputLeakageCurrent
A9 Input Current
OutputLeakageCurrent
VCC StandbyCurrent
VCC = VCC Max., VIN = VCC or GND
VCC = VCC Max., A9 = 12.5V
VCC = VCC Max., VOUT = GND to VCC
VCC = VCC Max., CE = Vcc ± 0.5V,
OE = VIH
—
—
—
—
±1.0
50
±1.0
100
µA
µA
µA
µA
ILI2
ILO
ICCS
ICC1
ICC2
VIL
VCC ActiveCurrent(1)
VCC Active Current(2,3)
Input Low Voltage
Input High Voltage
Voltage For Auto-select and
TemporarySectorUnprotect
VCC = VCC Max., CE = VIL, OE = VIH
VCC = VCC Max., CE = VIL, OE = VIH
—
—
–0.5
30
50
0.8
mA
mA
V
V
V
VIH
VID
0.7 X VCC
11.5
VCC + 0.5
12.5
VCC = 5.0V
VOL
OutputLowVoltage
OutputHighVoltage
OutputHighVoltage
IOL = 12 mA, VCC = VCC Min.
IOH = –2.5 mA, VCC = VCC Min.
IOH = –100 µA, VCC = VCC Min.
—
0.45
—
—
V
V
V
VOH1
VOH2
0.85 x VCC
VCC – 0.4
Notes:
1. The ICC current listed is typically less than 2 mA/MHz with OE at VIH.
2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
3. Not 100% tested.
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AC CHARACTERISTICS: READ ONLY (Over Operating Range)
Std.
-35
-45
-55
-70
-90
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max. Unit
tRC
tCE
Read Cycle Time(1)
Chip Enable Access Time(2)
Address Access Time(3)
35
—
—
—
—
—
0
—
35
35
25
10
10
45
—
—
—
—
—
—
45
45
25
10
10
55
—
—
—
—
—
—
55
55
30
15
15
70
—
—
—
—
—
—
70
70
30
20
20
90
—
—
—
—
—
—
90
90
35
20
20
ns
ns
ns
ns
ns
ns
ns
tACC
tOE
tDF
Output Enable Access Time
Chip Enable to Output High Z(1,4)
Output Enable to Output High Z(1,4)
Output Enable Hold Time(1)Read
tDF
tOEH
—
—
0
10
—
—
0
10
—
—
0
10
—
—
0
10
—
—
Toggle & Data Polling 10
tOH
Output Hold from First of
0
—
0
—
0
—
0
—
0
—
ns
Address, CE or OE
Whichever Occurs First
Notes:
1. Not 100% tested.
2. OE = VIL.
3. CE and OE = VIL.
4. Output Driver Disable Time.
5. See Figure 12 and Table 6 for test specifications.
t
RC
ADDRESS
ADDRESS STABLE
ACC
t
t
CE
CE
OE
t
DF
t
OE
t
OEH
WE
t
OH
HIGH-Z
HIGH-Z
OUTPUTS
OUTPUT VALID
Figure 11. AC Waveform: READ Only
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TEST CONDITIONS
Table 6. AC Test Specifications
Vcc = 5.0V
2.7KΩ
TestConditions
35ns AllOthers Unit
OutputLoad
1 TTL Gate
100
OutputLoadCapacitance,CL 30
(includingjigcapacitance)
pF
DEVICE
UNDER
TEST
Input Rise and Fall Times
Input Pulse Levels
5
20
ns
V
6.2KΩ
C
L
0 to 3.0 0.45 to 2.4
InputTimingMeasurement
ReferenceLevels
1.5
0.8
V
OutputTimingMeasurement 1.5
ReferenceLevels
2.0
V
Figure 12. Test Setup
AC CHARACTERISTICS: ERASE AND PROGRAM
Std.
-35
Min. Max.
-45
Min. Max.
-55
Min. Max.
-70
Min. Max.
-90
Min. Max. Unit
Symbol Parameter
tWC
tAS
tAH
tDS
tDH
Write Cycle Time(1)
35
0
—
—
—
—
—
—
45
0
—
—
—
—
—
—
45
0
—
—
—
—
—
—
45
0
—
—
—
—
—
—
90
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
30
15
0
35
20
0
45
20
0
45
30
0
45
45
0
tGHWL Read Recovery Time before Write 0
0
0
0
0
(OE HIGH to WE LOW)
tCS
tCH
CE Setup Time
0
0
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
0
0
—
—
—
—
—
—
—
ns
ns
ns
ns
µs
sec
µs
CE Hold Time
tWP
Write Pulse Width
20
20
20
1.0
50
25
20
20
1.0
50
30
20
20
1.0
1.0
35
20
20
1.0
1.0
45
20
20
1.0
1.0
tWPH
Write Pulse Width HIGH
tWHWH1 ByteProgrammingOperation(2)
tWHWH2 SectorEraseOperation(2)
tVCS
VCC Setup Time(1)
Note:
1. Not 100% tested.
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PROGRAM COMMAND SEQUENCE (Last Two Cycles)
READ STATUS DATA (Last Two Cycles)
tWC
tAS
555H
PA
ADDRESS
CE
PA
PA
tAH
tCH
tGHWL
tWPH
OE
tWP
tDS
tWHWH1
WE
tCS
tDH
A0H
PD
STATUS
DOUT
DATA
tVCS
Vcc
Figure 13. AC Waveform: Program Operation
Note:
1. PA = Program Address, PD = Program Data, DOUT is the true data at the Program Address.
ERASE COMMAND SEQUENCE (Last Two Cycles)
READ STATUS DATA
tWC
tAS
SA
2AAH
ADDRESS
CE
VA
VA
(555H FOR CHIP ERASE)
tAH
tCH
tGHWL
tWPH
OE
tWP
tDS
tWHWH2
WE
tCS
tDH
IN
55H
30H
COMPLETE
DATA
Vcc
PROGRESS
10H FOR
CHIP ERASE
tVCS
Figure 14. AC Waveform: Erase Operation
Note:
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status").
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t
RC
VA
ACC
ADDRESS
CE
VA
VA
t
t
CE
t
CH
OE
t
OE
t
OEH
tDF
WE
t
OH
COMPLEMENT
STATUS DATA
COMPLEMENT
TRUE
TRUE
VALID DATA
DQ7
STATUS DATA
VALID DATA
DQ0-DQ6
Figure 15. AC Waveform:
Note:
1. VA = Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
t
RC
VA
ACC
ADDRESS
CE
VA
VA
VA
t
t
CE
t
CH
OE
t
OE
t
OEH
tDF
WE
t
OH
VALID STATUS
STATUS
STATUS
VALID DATA
DQ6
(FIRST READ)
(SECOND READ)
(STOPS TOGGLING)
Figure 16. AC Waveform: Erase and Program Operations, Alternate CE Controlled Writes
Note:
1. VA = Valid Address, not required for DQ6. Illustration shows first two status cycles after command sequence, last status read cycle,
and array data read cycle.
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AC ELECTRICAL CHARACTERISTICS
Std.
-35
-45
-55
-70
-90
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max. Unit
tWC
tAS
Write Cycle Time(1)
35
0
—
—
—
—
—
—
—
—
—
—
—
—
—
45
0
—
—
—
—
—
—
—
—
—
—
—
—
—
55
0
—
—
—
—
—
—
—
—
—
—
—
—
—
70
0
—
—
—
—
—
—
—
—
—
—
—
—
—
90
0
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
Addess Setup Time
tAH
Address Hold Time
30
20
0
35
20
0
45
20
0
45
30
0
45
45
0
tDS
Data Setup Time
tDH
Data Hold Time
tOES
tGHWL
tWS
Output Enable Setup Time(1)
Read Recovery Time Before Write
Write Enable Setup Time
Write Enable Hold Time
Chip Enable Pulse Width
Chip Enable Pulse Width HIGH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
tWH
0
0
0
0
0
tCP
20
20
20
1.0
25
20
20
1.0
30
20
20
1.0
35
20
20
1.0
45
20
20
1.0
tCPH
tWHWH1 Byte Programming Operation(2)
tWHWH2 Sector Erase Operation(2)
Note:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PA FOR PROGRAM
SA FOR SECTOR ERASE
555H FOR CHIP ERASE
555H FOR PROGRAM
2AAH FOR ERASE
DATA# POLLING
ADDRESS
WE
VA
t
WC
tAS
t
AH
t
WH
t
GHEL
OE
CE
t
CPH
t
CP
tWHWH1 OR 2
t
WS
t
DH
t
DS
DOUT
DQ7#
DATA
A0H FOR PROGRAM
55H FOR ERASE
PD FOR PROGRAM
30H FOR ERASE
10H FOR CHIP ERASE
Figure 17. AC Waveform:
Note:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
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ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ.(1) Max.(2) Unit
1.0 15 sec
27 300/1000 µs
Comments
Excludes 00H Programming Prior to Erase(4)
Chip/Sector Erase Time
Byte Programming Time
Commercial/IndustrialTemperature
Excludes System Level Overhead(5)
ChipProgrammingTime(3)
3.5
12.5
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V Vcc, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions for Commercial and Industrial temperature ranges, Vcc = 4.5V (4.75V for –35),
100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since
most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is
exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming.
See Table 2 for further information on command definitions.
6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaran-
teed.
LATCHUP CHARACTERISTIC
Parameter
Min.
–1.0V
Max.(2)
VCC + 1.0V
+100 mA
Input Voltage with Respect to GND on I/O Pins
Vcc Current
–100 mA
Note:
1. Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
Parameter
TestConditions
150°C
Min.
Unit
Minimum Pattern Data Retention Time
Vcc Current
10
20
Years
Years
125°C
20
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NX29F010
PACKAGING INFORMATION
600-mil Plastic DIP
PackageCode:W
N
E1
1
D
SEATING PLANE
S
B1
E
A
L
C
A1
α
e
B
e
A
600-mil Plastic DIP (W)
Inches
Symbol Min Max
Ref. Std.
Min Max
Min Max
N
A
28
32
40
0.160 0.185 0.165 0.180 0.165 0.200
A1 0.020 0.030 0.010
0.015 0.020 0.018
B1 0.050 0.065
—
0.020 0.045
0.015 0.022
0.045 0.067
0.008 0.015
B
0.050
0.010
C
D
E
0.008 0.012
1.420 1.460 1.645 1.655 2.045 2.055
0.600 0.620 0.590 0.610 0.600 0.620
Notes:
1. Controlling dimension: inches, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash
protrusions and should be measured from the
bottom of the package.
E1 0.530 0.555 0.540 0.555 0.530 0.560
0.610 0.660 0.620 0.680 0.600 0.680
0.100BSC 0.100BSC 0.100BSC
e
e
A
L
S
a
0.120 0.150 0.120 0.140 0.120 0.138
0.055 0.080 0.065 0.085 0.055 0.085
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
0°
15°
2°
8°
—
—
NexFlashTechnologies, Inc.
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NX29F010
PACKAGING INFORMATION
Plastic TSOP - 32-pins
Package Code: T (Type I)
1
E
H
N
D
SEATING PLANE
A
S
L
α
e
B
C
A1
Plastic TSOP (T—Type I)
Millimeters Inches
Symbol
Min
Max
Min
Max
Ref. Std.
No.Leads
32
A
A1
B
C
D
E
H
e
–
1.20
0.15
0.27
0.21
8.10
–
0.047
0.05
0.17
0.10
7.90
18.30 18.50
19.80 20.20
0.50 BSC
0.002 0.005
0.007 0.009
0.004 0.008
0.308 0.316
0.714 0.722
0.772 0.788
0.020 BSC
Notes:
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
L
a
0.50
0°
0.70
5°
0.016 0.024
0°
5°
22
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NX29F010
PACKAGING INFORMATION
PLCC(PlasticLeadedChipCarrier)
PackageCode:PL
C
PIN 1
b1
e
b
D2
D1 D
A
E
A3
E1
A1
A2
SEATING
PLANE
E2
Plastic Leaded Chip Carrier (PL)
Millimeters
Symbol Min Max
Ref. Std.
Inches
Min Max
No.Leads
32
3.33 3.56 0.131 0.140
0.50 0.020
A
A1
A2
A3
b
–
–
2.67 2.93 0.105 0.115
1.91 0.81 0.026 0.032
0.66 8.10 0.311 0.319
0.33 0.54 0.013 0.021
0.20 0.35 0.008 0.014
13.89 14.05 0.547 0.553
14.86 15.10 0.585 0.595
b1
C
Notes:
1. Controlling dimension: millimeters, unless other-
wise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash
protrusions.
4. Formed leads shall be planar with respect to one
another within 0.004 inches at the seating plane.
5. ND and NE represent the number of leads in D and
E directions, respectively.
6. D1 and E1 should be measured from the bottom of
the package.
D
D1
D2
E
–
7.62
–
0.400
11.35 11.51 0.447 0.453
12.32 12.57 0.485 0.495
E1
E2
e
–
7.62
1.27 BSC
0o 10o
–
0.300
0.050 BSC
10o
0o
NexFlashTechnologies, Inc.
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NX29F010
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed(ns) Order Part No.
Package
35
45
55
70
90
NX29F010-35W
NX29F010-45PL
NX29F010-35T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NX29F010-45W
NX29F010-45PL
NX29F010-45T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NX29F010-55W
NX29F010-55PL
NX29F010-45T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NX29F010-70W
NX29F010-70PL
NX29F010-70T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NX29F010-90W
NX29F010-90PL
NX29F010-90T
600-mil Plastic DIP
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
Note: Contact NexFlash Marketing for availability of DIP packages
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed(ns) Order Part No.
Package
45
55
70
90
NX29F010-45PLI
NX29F010-45TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NX29F010-55PLI
NX29F010-55TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NX29F010-70PLI
NX29F010-70TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
NX29F010-90PLI
NX29F010-90TI
PLCC – Plastic Leaded Chip Carrier
TSOP (Type 1)
24
NexFlashTechnologies, Inc.
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NX29F010
PRELIMINARY DESIGNATION
LIFE SUPPORT POLICY
The “Preliminary” designation on an NexFlash data sheet
indicates that the product is not fully characterized. The
specifications are subject to change and are not guaran-
teed.NexFlashoranauthorizedsalesrepresentativeshould
be consulted for current information before using this
product.
NexFlash does not recommend the use of any of it's
products in life support applications where the failure or
malfunctionoftheproductcanreasonablybeexpectedto
cause failure in the life support system or to significantly
affect its safety or effectiveness. Products are not
authorized for use in such applications unless NexFlash
receives written assurances, to it’s satisfaction, that:
IMPORTANT NOTICE
(a) the risk of injury or damage has been minimized;
(b) the user assumes all such risks; and
NexFlash reserves the right to make changes to the
products contained in this publication in order to improve
design, performance or reliability. NexFlash assumes no
responsibility for the use of any circuits described herein,
conveys no license under any patent or other right, and
makesnorepresentationthatthecircuitsarefreeofpatent
infringement. Charts and schedules contained herein re-
flect representative operating parameters, and may vary
depending upon a user’s specific application. While the
informationinthispublicationhasbeencarefullychecked,
NexFlash shall not be liable for any damages arising as a
result of any error or omission.
(c) potential liability of NexFlash is adequately protected
under the circumstances.
Trademarks:
NexFlash is a trademark of NexFlash Technologies, Inc. All
other marks are the property of their respective owner.
NexFlashTechnologies, Inc.
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