OMAP5910(DSP) [ETC]
Dual-Core Processor ; 双核处理器\n
| 型号： | OMAP5910(DSP) |
| 厂家： | 
ETC |
| 描述： | Dual-Core Processor
|
| 文件： | 总160页 (文件大小：1988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OMAP5910
Dual-Core Processor
Data Manual
Literature Number: SPRS197B
August 2002 − Revised August 2003
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS197A device-specific data
sheet to make it an SPRS197B revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the
specified release date and includes the following changes.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
Title
Replaced “Product Preview” description with “Production Data” description.
Page
Important Replaced “Important Notice” page.
Notice
All
1
Removed “Product Preview” banners from page margins.
Revised “USB2.0 Host Interface” to read “USB (Full/Low Speed) Host Interface” and “USB2.0 Function Interface” to read
“USB (Full Speed) Function Interface”.
4
Added paragraph that reads “In Table 2−1, signals with multiplexed functions are highlighted in gray. Signals with a
multiplexed pin name are separated with forward slashes as follows:”
7
7
Replaced Figure 2−2.
Added the following note below Figure 2−2: “The GDY package has not been released to production and is still in product
preview phase.”
7
Removed paragraph that reads “Figure 2−2 illustrates the ball locations for the 289-ball GDY ball grid array (BGA) package
and is used in conjun ction with Table 2−1 to locate signal names and ball grid numbers. GDY BGA ball numbers in
Table 2−2 are read from left-to-right, top-to-bottom.”
20−32
Table 2−4: Deleted “or 48 MHz” from BCLK description.
Changed signal type from O to I on the configuration input (CONF) and USB.VBUS signals.
Changed signal type from O to I on the USB.VBUS signal.
35
43
44
Revised “USB2.0 Host Interface” to read “USB Host Interface” and “USB2.0 Function Interface” to read “USB Function
Interface”.
Deleted sentence that read “This is necessary because of the large number of integrated peripherals on the OMAP5910
device” from paragraph 3.5.4.
Deleted 2.0 from USB Host Controller in paragraph 3.6.1. Also revised first paragraph to indicate the controller is USB
compliant.
45
50
Deleted 2.0 from USB Host Controller in paragraph 3.6.2.
Changed note from “DSR and DTR are not available on UART1 and UART3” to “DSR and DTR are only available on UART1
and UART3”.
104
109
120
121
137
Replaced note in Section 5.1.
Changed 30 Ω to 60 Ω in second paragraph of Section 5.6.2.
Updated Table 5−13.
Replaced Figure 5−12 and Figure 5−13.
Updated the MMC.CLK from low to high in Table 5−29.
iii
August 2002 − Revised August 2003
SPRS197B
Revision History
iv
SPRS197B
August 2002 − Revised August 2003
Contents
Contents
Section
Page
1
2
OMAP5910 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
2.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
2.1.2
TMS320C55x DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TI-Enhanced TI925T RISC Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
2.2
2.3
2.4
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Characteristics and Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
10
20
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
34
36
36
37
38
38
39
39
40
41
43
43
43
43
43
43
44
44
45
45
46
46
46
47
47
47
47
47
48
48
48
48
48
49
3.1
3.2
Functional Block Diagram Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
3.2.2
MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Subsystem Registers Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
DSP Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
3.3.2
3.3.3
3.3.4
DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Single-Access RAM (SARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP I/O Space Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
3.5
DSP External Memory (Managed by MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU and DSP Private Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32k Timer (MPU only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
MPU Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.6.6
3.6.7
3.6.8
3.6.9
3.6.10
3.6.11
3.6.12
3.6.13
3.6.14
USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Function Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
I C Master/Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multimedia Card/Secure Digital (MMC/SD) Interface . . . . . . . . . . . . . . . . . . . . . . . . .
HDQ/1-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPUIO/Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse-Width Light (PWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse-Width Tone (PWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Adjustment Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
DSP Public Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
3.7.2
Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Serial Interface (MCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
August 2002 − Revised August 2003
SPRS197B
Contents
Section
Page
3.8
Shared Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
49
50
50
51
52
52
53
53
53
54
54
54
54
54
55
55
56
57
58
65
74
81
81
87
92
94
99
3.8.1
3.8.2
3.8.3
Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9
System DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Traffic Controller (Memory Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10
3.11
3.12
3.12.1
3.12.2
3.12.3
MPU/DSP Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Interface (MPUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU/DSP Shared Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13
DSP Hardware Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.1
3.13.2
3.13.3
DCT/iDCT Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Motion Estimation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pixel Interpolation Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14
3.15
Power Supply Connection Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1
3.14.2
Core and I/O Voltage Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Voltage Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1
3.15.2
3.15.3
MPU Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16
DSP Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16.1
3.16.2
3.16.3
3.16.4
DSP Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU/DSP Shared Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
103
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
104
105
5.1
5.2
5.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
107
107
108
108
109
110
111
111
112
5.4
5.5
5.6
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1
5.6.2
5.6.3
32-kHz Oscillator and Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Base Oscillator (12 MHz or 13 MHz) and Input Clock . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Clock Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
5.7.2
OMAP5910 Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OMAP5910 MPU Core Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
SPRS197B
August 2002 − Revised August 2003
Contents
Page
Section
5.8
External Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
113
120
124
124
128
132
134
135
137
139
140
141
142
5.8.1
5.8.2
EMIFS/Flash Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIFF/SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.1
5.9.2
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
Multichannel Serial Interface (MCSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD Controller Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multimedia Card/Secure Digital (MMC/SD) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
I C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Serial Bus (USB) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDQ/1-Wire Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
7
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
147
147
148
7.1
7.2
GZG Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GDY Ball Grid Array Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
August 2002 − Revised August 2003
SPRS197B
Figures
Figure
List of Figures
Page
2−1
2−2
OMAP5910 GZG MicroStar BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OMAP5910 GDY Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
7
3−1
3−2
3−3
3−4
3−5
3−6
OMAP5910 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP MMU Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP MMU On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Connections for a Typical System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Connections for a System With 1.8-V SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
41
42
55
56
57
External RC Circuit for DPLL CV
Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal System Oscillator External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Core Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous 32-Bit Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Read − Page Mode ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
108
109
109
111
112
115
116
117
118
119
121
121
122
122
123
123
127
127
128
129
130
131
133
133
134
135
136
5−10 Asynchronous Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 Synchronous Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 32-Bit (2 x 16-Bit) SDRAM RD (Read) Command (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 32-Bit (2 x 16-Bit) SDRAM WRT (Write) Command (Active Row) . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 SDRAM ACTV (Activate Row) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−15 SDRAM DCAB (Precharge/Deactivate Row) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−16 SDRAM REFR (Refresh) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17 SDRAM MRS (Mode Register Set) Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−19 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−20 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5−21 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . .
5−22 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5−23 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . .
5−24 MCSI Master Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−25 MCSI Slave Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−26 Camera Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−27 TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK) . . . . . . . . . . . . . . . . . .
5−28 TFT Mode (LCD.HS/LCD.VS on Rising and LCD.Px on Falling LCD.PCLK) . . . . . . . . . . . . . . . . . .
viii
SPRS197B
August 2002 − Revised August 2003
Figures
Page
Figure
5−29 MMC/SD Host Command Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−30 MMC/SD Card Response Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−31 MMC/SD Host Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−32 MMC/SD Host Read and Card CRC Status Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
137
138
138
139
140
141
143
143
143
143
2
5−33 I C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−34 USB Integrated Transceiver Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−35 Microwire Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−36 OMAP5910 HDQ Interface Reading From HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−37 OMAP5910 HDQ Interface Writing to HDQ Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−38 Typical Communication Between OMAP5910 HDQ and HDQ Slave . . . . . . . . . . . . . . . . . . . . . . . . .
5−39 HDQ/1-Wire Break (Reset) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1
7−2
OMAP5910 289-Ball MicroStar BGA Plastic Ball Grid Array (GZG) Package . . . . . . . . . . . . . . . . .
OMAP5910 289-Ball Plastic Ball Grid Array (GDY) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
147
148
ix
August 2002 − Revised August 2003
SPRS197B
Tables
Table
List of Tables
Page
2−1
2−2
2−3
2−4
GZG BGA Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GDY BGA Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Characteristics and Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
8
11
20
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
OMAP5910 MPU Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU/DSP Shared Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Public Peripheral Registers (Accessible via MPUI Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Private Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Public Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP/MPU Shared Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Timer 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Level 1 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Level 2 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
37
37
37
38
38
38
39
39
40
40
40
40
58
58
58
58
59
60
61
64
66
66
67
67
68
69
71
71
72
72
72
72
72
72
73
73
75
75
76
77
3−9
3−10
3−11
3−12
3−13
3−14
3−15
3−16
3−17
3−18
3−19
3−20
3−21
3−22
3−23
3−24
3−25
3−26
3−27
3−28
3−29
3−30
3−31
3−32
3−33
3−34
3−35
3−36
3−37
3−38
3−39
3−40
3−41
2
I C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDQ/1-Wire Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMC/SD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Host Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Camera Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU I/O/Keyboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Pulse Generator 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Pulse Generator 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32k Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Adjustment Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OMAP 5910 Pin Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Bus Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Local Bus MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP MMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
SPRS197B
August 2002 − Revised August 2003
Tables
Page
Table
3−42
3−43
3−44
3−45
3−46
3−47
3−48
3−49
3−50
3−51
3−52
3−53
3−54
3−55
3−56
3−57
3−58
3−59
3−60
3−61
3−62
3−63
3−64
3−65
3−66
3−67
3−68
3−69
3−70
3−71
3−72
3−73
3−74
3−75
MPUI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIPB (Private) Bridge 1 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIPB (Public) Bridge 2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU UART TIPB Bus Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Traffic Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Clock/Reset/Power Mode Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPLL1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ultra Low-Power Device Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Die Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Identification Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP DMA Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Timer 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Interrupt Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Level 2 Interrupt Handler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCSI1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCSI2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Instruction Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP EMIF Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP TIPB Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP UART TIPB Bus Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Clock Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART3/IrDA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU/DSP Shared GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU/DSP Shared Mailbox Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU Level 1 and Level 2 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Level 1 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DSP Level 2 Interrupt Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
77
78
78
79
79
79
80
80
80
82
85
85
85
85
85
86
87
88
90
91
92
92
92
93
93
95
96
97
98
98
99
101
102
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
5−10
5−11
5−12
Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Input Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Base Oscillator Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Clock Speed Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OMAP5910 Device Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OMAP5910 Device Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU_RST Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU_RST Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIFS/Flash Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIFS/Flash Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIFF/SDRAM Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
108
109
110
110
111
111
112
112
113
114
120
xi
August 2002 − Revised August 2003
SPRS197B
Tables
Table
Page
5−13
5−14
5−15
5−16
5−17
5−18
5−19
5−20
5−21
5−22
5−23
5−24
5−25
5−26
5−27
5−28
5−29
5−30
5−31
5−32
5−33
5−34
5−35
EMIFF/SDRAM Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
MCSI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCSI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Camera Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD Controller Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMC/SD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMC/SD Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
124
126
128
128
129
129
130
130
131
131
132
132
134
135
137
137
139
140
141
141
142
142
2
I C Signals (I2C.SDA and I2C.SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Integrated Transceiver Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDQ/1-Wire Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HDQ/1-Wire Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
SPRS197B
August 2002 − Revised August 2003
Features
1
OMAP5910 Features
D
D
Low-Power, High-Performance CMOS
Technology
− 0.13-µm Technology
− 1.6-V Core Voltage
D
D
DSP Peripherals
− Three 32-Bit Timers and Watchdog Timer
− Level1/Level2 Interrupt Handlers
− Six-Channel DMA Controller
− Two Multichannel Buffered Serial Ports
− Two Multichannel Serial Interfaces
TI925T (MPU) ARM9TDMI Core
− Support 32-Bit and 16-Bit (Thumb
Mode) Instruction Sets
− 16K-Byte Instruction Cache
− 8K-Byte Data Cache
TI925T Peripherals
− Three 32-Bit Timers and Watchdog Timer
− 32-kHz Timer
− Data and Program Memory Management
Units (MMUs)
− Two 64-Entry Translation Look-Aside
Buffers (TLBs) for MMUs
− Level1/Level2 Interrupt Handlers
− USB (Full/Low Speed) Host Interface
With up to 3 Ports
− USB (Full Speed) Function Interface
− One Integrated USB Transceiver for
Either Host or Function
− 17-Word Write Buffer
D
TMS320C55x (C55x) DSP Core
− One/Two Instructions Executed per Cycle
− Dual Multipliers (Two Multiply-
Accumulates per Cycle)
− Two Arithmetic/Logic Units
− One Internal Program Bus
− Five Internal Data/Operand Buses
(3 Read Buses and 2 Write Buses)
− 32K x 16-Bit On-Chip Dual-Access RAM
(DARAM) (64K Bytes)
− 48K x 16-Bit On-Chip Single-Access RAM
(SARAM) (96K Bytes)
− 16K x 16-Bit On-Chip ROM (32K Bytes)
− Instruction Cache (24K Bytes)
− Video Hardware Accelerators for DCT,
iDCT, Pixel Interpolation, and Motion
Estimation for Video Compression
− Multichannel Buffered Serial Port
2
− Inter-Integrated Circuit (I C) Master and
Slave Interface
− Microwire Serial Interface
− Multimedia Card (MMC) and Secure
Digital (SD) Interface
− HDQ/1-Wire Interface
− Camera Interface for CMOS Sensors
− ETM9 Trace Module for TI925T Debug
− Keyboard Matrix Interface (6 x 5 or 8 x 8)
− Up to Ten MPU General-Purpose I/Os
− Pulse-Width Tone (PWT) Interface
− Pulse-Width Light (PWL) Interface
− Two LED Pulse Generators (LPGs)
− Real-Time Clock (RTC)
− LCD Controller With Dedicated System
DMA Channel
D
D
192K Bytes of Shared Internal SRAM
D
D
Shared Peripherals
Memory Traffic Controller (TC)
− Three Universal Asynchronous
Receiver/Transmitters (UARTs) (One
Supporting SIR Mode for IrDA)
− Four Interprocessor Mailboxes
− Up to 14 Shared General-Purpose I/Os
− 16-Bit EMIFS External Memory Interface
to Access up to 128M Bytes of Flash,
ROM, or ASRAM
− 16-Bit EMIFF External Memory Interface
to Access up to 64M Bytes of SDRAM
Individual Power-Saving Modes for
MPU/DSP/TC
D
D
D
D
9-Channel System DMA Controller
DSP Memory Management Unit
Endianism Conversion Logic
D
On-Chip Scan-Based Emulation Logic
†
D
IEEE Std 1149.1 (JTAG) Boundary Scan
Digital Phase-Locked Loop (DPLL) for
MPU/DSP/TC Clocking Control
Logic
D
Two 289-Ball Ball Grid Array Package
Options (GZG and GDY Suffixes)
TMS320C55x and C55x are trademarks of Texas Instruments.
ARM9TDMI is a trademark of ARM Limited.
Thumb is a registered trademark of ARM Limited.
Microwire is a trademark of National Semiconductor Corporation.
1-Wire is a registered trademark of Dallas Semiconductor Corporation.
†
IEEE Standard 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture.
1
August 2002 − Revised August 2003
SPRS197B
Introduction
2
Introduction
This section describes the main features of the OMAP5910 device, lists the terminal assignments, and
describes the function of each terminal. This data manual also provides a detailed description section,
electrical specifications, parameter measurement information, and mechanical data about the available
packaging.
2.1 Description
The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application
processing needs of next-generation embedded devices.
The OMAP platform enables OEMs and ODMs to quickly bring to market devices featuring rich user
interfaces, high processing performance, and long battery life through the maximum flexibility of a fully
integrated mixed processor solution.
The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a
TMS320C55x DSP core and a high-performance TI925T ARM core.
The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as
well as the Texas Instruments (TI) DSP/BIOS software kernel foundation, and is available in a 289-ball
MicroStar BGA package.
The OMAP5910 is targeted at the following applications:
•
•
Applications processing devices
Mobile communications
−
−
−
−
−
802.11
Bluetooth wireless technology
GSM (including GPRS and EDGE)
CDMA
Proprietary government and other
•
•
•
•
•
•
Video and image processing (MPEG4, JPEG, Windows Media Video, etc.)
Advanced speech applications (text-to-speech, speech recognition)
Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and other GSM speech codecs)
Graphics and video acceleration
Generalized web access
Data processing (fax, encryption/decryption, authentication, signature verification and watermarking)
2.1.1 TMS320C55x DSP Core
The DSP core of the OMAP5910 device is based on the TMS320C55x DSP generation CPU processor core.
The C55xDSP architecture achieves high performance and low power through increased parallelism and total
focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program
bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA
activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle.
In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
OMAP and DSP/BIOS are trademarks of Texas Instruments.
Bluetooth is a trademark owned by Bluetooth SIG, Inc.
Windows is a registered trademark of Microsoft Corporation.
Other trademarks are the property of their respective owners.
2
SPRS197B
August 2002 − Revised August 2003
Introduction
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication
in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of
the ALUs is under instruction set control, providing the ability to optimize parallel activity and power
consumption. These resources are managed in the address unit (AU) and data unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
instruction unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions
for the program unit (PU). The program unit decodes the instructions, directs tasks to AU and DU resources,
and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions. The OMAP5910 DSP core also includes a 24K-byte instruction cache to minimize
external memory accesses, improving data throughput and conserving system power.
2.1.1.1 DSP Tools Support
The 55x DSP core is supported by the industry’s leading eXpressDSP software environment including the
Code Composer Studio integrated development environment, DSP/BIOS software kernel foundation, the
TMS320 DSP Algorithm Standard, and the industry’s largest third-party network. Code Composer Studio
features code generation tools including a C-Compiler, Visual Linker, simulator, Real-Time Data Exchange
(RTDX), XDS510 emulation device drivers, and Chip Support Libraries (CSL). DSP/BIOS is a scalable
real-time software foundation available for no cost to users of Texas Instruments’ DSP products providing a
preemptive task scheduler and real-time analysis capabilities with very low memory and megahertz overhead.
The TMS320 DSP Algorithm Standard is a specification of coding conventions allowing fast integration of
algorithms from different teams, sites, or third parties into the application framework. Texas Instruments’
extensive DSP third-party network of over 400 providers brings focused competencies and complete solutions
to customers.
2.1.1.2 DSP Software Support
Texas Instruments has also developed foundation software available for the 55x DSP core. The C55x DSP
Library (DSPLIB) features over 50 C-callable software kernels (FIR/IIR filters, Fast Fourier Transforms (FFTs),
and various computational functions). The DSP Image/Video Processing Library (IMGLIB) contains over
20 software kernels highly optimized for C55x DSPs and is compiled with the latest revision of the C55x DSP
code generation tools. These imaging functions support a wide range of applications that include
compression, video processing, machine vision, and medical imaging.
2.1.2 TI-Enhanced TI925T RISC Processor
The MPU core is a TI925T reduced instruction set computer (RISC) processor. The TI925T is a 32-bit
processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core
uses pipelining so that all parts of the processor and memory system can operate continuously.
The MPU core incorporates:
•
•
•
A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
A separate 16K-byte instruction cache and 8K-byte data cache. Both are two-way associative with virtual
index virtual tag (VIVT).
•
A 17-word write buffer (WB)
The OMAP5910 device uses the TI925T core in little endian mode only.
To reduce effective memory access time, the TI925T has an instruction cache, a data cache, and a write buffer.
In general, these are transparent to program execution.
eXpressDSP, Code Composer Studio, TMS320, RTDX, and XDS510 are trademarks of Texas Instruments.
3
August 2002 − Revised August 2003
SPRS197B
Introduction
2.2 Terminal Assignments
Figure 2−1 illustrates the ball locations for the 289-ball GZG ball grid array (BGA) package and is used in
conjunction with Table 2−1 to locate signal names and ball grid numbers. GZG BGA ball numbers in Table 2−1
are read from left-to-right, top-to-bottom.
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21
2
4
6
8 10 12 14 16 18 20
Figure 2−1. OMAP5910 GZG MicroStar BGA Package (Bottom View)
In Table 2−1, signals with multiplexed functions are highlighted in gray. Signals with a multiplexed pin name
are separated with forward slashes as follows:
•
signal1/signal2/signal3 (for example, GPIO11/HDQ)
Signals which are associated with specific peripherals are denoted by using the peripheral name, followed
by a period, and then the signal name; as follows:
•
peripheral1.signal1 (for example, MCBSP1.DR)
Table 2−1. GZG BGA Terminal Assignments
GZG
BGA
GZG
BGA
GZG
BGA
GZG
BGA
SIGNAL
SIGNAL
SIGNAL
SIGNAL
BALL #
BALL #
BALL #
BALL #
A1
DV
DV
DV
V
A2
A9
SDRAM.RAS
A3
A11
A19
B2
CV
V
A5
A13
A20
B3
DV
V
DD4
DD4
DD1
SS
DD1
SS
DD4
A7
CV
DD
LCD.P[13]
SS
A15
A21
B4
A17
B1
DV
V
LCD.P[5]
DD1
V
V
SDRAM.DQML
SS
SS
SDRAM.D[13]
SDRAM.D[4]
B5
B6
SDRAM.D[8]
DV
B7
V
DV
V
SS
SS
B8
B9
SDRAM.D[0]
SDRAM.A[0]
B10
B15
B19
C2
B12
B16
B20
C3
DD4
DD4
SS
B13
B17
B21
C4
CV
B14
B18
C1
LCD.AC
DD3
LCD.P[11]
LCD.P[1]
V
SS
LCD.P[6]
CV
DD3
FLASH.A[3]
SDRAM.D[11]
SDRAM.CLK
SDRAM.A[4]
DV
SDRAM.WE
SDRAM.D[6]
SDRAM.A[10]
LCD.PCLK
DD5
SDRAM.D[14]
SDRAM.D[2]
SDRAM.A[7]
C5
C6
SDRAM.D[9]
SDRAM.BA[0]
SDRAM.A[1]
C7
C8
C9
C10
C14
C11
C15
C12
C13
MicroStar BGA is a trademark of Texas Instruments.
4
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−1. GZG BGA Terminal Assignments (Continued)
GZG
BGA
GZG
BGA
GZG
BGA
GZG
BGA
SIGNAL
SIGNAL
SIGNAL
SIGNAL
BALL #
BALL #
BALL #
BALL #
C16
C20
D4
LCD.P[14]
KB.C[5]
C17
C21
D5
LCD.P[10]
KB.C[4]
C18
D2
LCD.P[7]
FLASH.A[5]
SDRAM.D[12]
SDRAM.BA[1]
LCD.VS
C19
D3
LCD.P[2]
FLASH.A[2]
SDRAM.D[7]
SDRAM.A[9]
LCD.P[15]
KB.C[2]
SDRAM.DQMU
SDRAM.D[5]
SDRAM.A[6]
LCD.P[9]
SDRAM.D[15]
SDRAM.CKE
SDRAM.A[3]
LCD.P[8]
D6
D7
D8
D9
D10
D14
D18
E2
D11
D15
D19
E3
D12
D16
D20
E4
D13
D17
E1
LCD.P[0]
KB.C[1]
DV
V
FLASH.A[7]
KB.R[4]
DD5
RSVD
DV
SS
KB.C[3]
CV
FLASH.A[4]
KB.R[3]
E5
E18
F2
E19
F3
E20
F4
E21
F18
G2
FLASH.A[9]
DD1
DD
FLASH.A[6]
KB.C[0]
F19
G3
KB.R[1]
FLASH.A[11]
SDRAM.A[12]
LCD.P[3]
F20
G4
V
SS
G1
V
SS
FLASH.A[12]
SDRAM.D[1]
LCD.P[12]
FLASH.A[10]
SDRAM.A[8]
KB.R[0]
G8
SDRAM.D[3]
SDRAM.A[2]
G9
G10
G14
G21
H7
G11
G18
H2
G12
G19
H3
G13
G20
H4
PWRON_RESET
FLASH.A[15]
SDRAM.CAS
MCBSP1.CLKS
FLASH.A[14]
SDRAM.A[11]
MCBSP1.CLKX
FLASH.RDY
SDRAM.A[5]
DV
DD5
SDRAM.D[10]
H8
H9
H10
H11
H12
LCD.HS
MCBSP1.FSX/
MCBSP1.DX
MCBSP1.DX/
MCBSP1.FSX
H13
LCD.P[4]
H14
KB.R[2]
H15
H18
CAM.EXCLK/
ETM.SYNC/
UWIRE.SDO
H19
J3
H20
J4
MCBSP1.DR
FLASH.A[18]
J1
J7
FLASH.A[20]
FLASH.A[8]
J2
J8
FLASH.A[17]
FLASH.A[1]
FLASH.A[19]
CAM.D[5]/
ETM.D[5]/
UWIRE.SDI
CAM.LCLK/
ETM.CLK/
UWIRE.SCLK
CAM.D[7]/
ETM.D[7]/
UWIRE.CS0
CAM.D[6]/
ETM.D[6]/
UWIRE.CS3
J14
J15
J18
J19
J20
K4
V
J21
K7
CV
K2
K8
V
SS
K3
FLASH.A[23]
SS
DD3
CAM.D[1]/ETM.D[1]/
UART3.RTS
FLASH.A[22]
FLASH.A[16]
FLASH.A[13]
K14
CAM.D[2]/
ETM.D[2]/
UART3.CTS
CAM.D[4]/
ETM.D[4]/
UART3.TX
CAM.D[3]/
ETM.D[3]/
UART3.RX
K15
L1
K18
L3
K19
L4
K20
L7
V
SS
DV
FLASH.BE[0]
FLASH.ADV
FLASH.A[24]
DD5
CAM.HS/
ETM.PSTAT[1]/
UART2.CTS
UART3.RX/PWL/
UART2.RX
CAM.VS/
ETM.PSTAT[2]
L8
FLASH.A[21]
L14
L15
L18
CAM.D[0]/
ETM.D[0]/
MPUIO12
L19
M4
L21
M7
DV
M2
M8
CV
M3
FLASH.CS1
DD1
DD4
FLASH.CS2/
FLASH.BAA
GPIO2/
SPI.CLK
FLASH.CS0
FLASH.BE[1]
M14
M20
UART3.TX/
PWT/
UART2.TX
CAM.RSTZ/
ETM.PSTAT[0]/
UART2.RTS
GPIO7/
MMC.DAT2
GPIO15/
KB.R[7]
M15
M18
M19
N1
N7
V
N2
N8
FLASH.D[1]
N3
FLASH.CLK
N4
FLASH.D[0]
SS
UWIRE.CS0/
MCBSP3.CLKX
MPUIO2/
EXT_DMA_REQ0
FLASH.D[2]
FLASH.CS3
N14
N15
GPIO12/
MCBSP3.FSX
GPIO13/
KB.R[5]
GPIO11/
HDQ
GPIO14/
KB.R[6]
N18
P2
N19
P3
N20
P4
N21
P7
FLASH.D[3]
FLASH.D[11]
DV
FLASH.D[4]
FLASH.D[5]
DD5
USB0.DP
MCBSP2.DR/
MCBSP2.DX
P8
P9
P10
P11
MMC.CMD/SPI.DO
5
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−1. GZG BGA Terminal Assignments (Continued)
GZG
BGA
GZG
BGA
GZG
BGA
GZG
BGA
SIGNAL
SIGNAL
SIGNAL
SIGNAL
BALL #
BALL #
BALL #
BALL #
RST_HOST_OUT/
MCBSP3.DX/
USB1.SE0
UWIRE.CS3/
KB.C[6]
P12
P18
CV
P13
P19
CLK32K_IN
P14
P20
P15
R1
DD
GPIO3/
SPI.CS3/
MCBSP3.FSX/LED1
GPIO6/
SPI.CS1/
MCBSP3.FSX
GPIO4/
SPI.CS2/
MCBSP3.FSX
DV
DD5
R2
R9
FLASH.D[6]
R3
FLASH.D[7]
R4
FLASH.D[8]
R8
USB.DM
UART2.RX/
USB2.VM
MCLKREQ/EXT_
MASTER_REQ
R10
R11
MMC.DAT0/SPI.DI
R12
OSC32K_OUT
BCLKREQ/
UART3.CTS/
UART1.DSR
GPIO0/
SPI.RDY/
USB.VBUS
GPIO1/
UART3.RTS
R13
R20
T4
R14
R21
T18
U2
UART1.CTS
R18
T2
R19
T3
CV
V
SS
FLASH.D[9]
FLASH.D[10]
DD3
MPUIO4/
EXT_DMA_REQ1/
LED2
MPUIO5/
LOW_PWR
FLASH.D[14]
I2C.SCL
T19
U3
T20
U4
U1
FLASH.D[12]
V
SS
FLASH.D[13]
FLASH.OE
UWIRE.SDI/
UART3.DSR/
UART1.DSR/
MCBSP3.DR
U18
U19
MPUIO1
U20
V
U21
DV
V
SS
DD1
V2
V6
DV
V3
V7
FLASH.D[15]
V4
V8
FLASH.WP
MPUIO3
V5
V9
DD5
SS
UART2.TX/
USB2.TXD
MCBSP2.CLKR/
GPIO11
MCSI2.SYNC/
GPIO7
MMC.DAT1/
MPUIO7
MCSI1.SYNC/
USB1.VP
V10
V14
V18
V11
V15
V19
MMC.CLK
MPU_RST
V12
V16
V20
V
V13
V17
W1
SS
UART1.RX
CONF
EMU0
TMS
UWIRE.SCLK/
KB.C[7]
I2C.SDA
FLASH.RP
UART2.RTS/
USB2.SE0/
MPUIO5
USB.PUEN/
USB.CLKO
W2
FLASH.WE
W3
OSC1_OUT
W4
W5
MCBSP2.FSR/
GPIO12
MCSI2.DOUT/
USB2.TXEN
W6
W7
W11
W15
MCBSP2.FSX
W8
GPIO9
W9
MMC.DAT2/
MPUIO11
MMC.DAT3/
MPUIO6
MCSI1.DIN/
USB1.RCV
W10
W14
W12
W16
OSC32K_IN
W13
W17
MCSI1.DOUT/
USB1.TXD
MCBSP3.CLKX/
USB1.TXEN
RST_OUT
EMU1
UWIRE.SDO/
UART3.DTR/
UART1.DTR/
MCBSP3.DX
BFAIL/
EXT_FIQ
W18
TCK
W19
W20
V
SS
W21
Y1
Y5
CV
Y2
Y6
OSC1_IN
Y3
Y7
V
Y4
Y8
UART2.BCLK
DD2
SS
UART2.CTS/
USB2.RCV/
GPIO7
MCBSP2.CLKX
DV
GPIO8
DD3
CLK32K_OUT/
MPUIO0/
USB1.SPEED
BCLK/
UART3.RTS/
UART1.DTR
MCSI2.CLK/
USB2.SUSP
Y9
MCLK
Y10
Y12
Y13
STAT_VAL/
WKUP
Y14
Y18
AA1
UART1.TX
TRST
Y15
Y19
AA2
V
Y16
Y20
AA3
DV
Y17
Y21
AA5
SS
DD1
TDI
CV
CV
DDA
MCBSP2.DX/
MCBSP2.DR
DD
V
SS
DV
CV
DD2
DD2
6
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−1. GZG BGA Terminal Assignments (Continued)
GZG
BGA
GZG
BGA
GZG
BGA
GZG
BGA
SIGNAL
SIGNAL
SIGNAL
SIGNAL
BALL #
BALL #
BALL #
BALL #
MCSI2.DIN/
USB2.VP
MCSI1.CLK/
USB1.VM
AA7
V
SS
AA9
AA11
DV
AA13
DD1
MPU_BOOT/
MCBSP3.DR/
USB1.SUSP
AA15
AA21
UART1.RTS
AA17
AA19
TDO
AA20
CLK32K_CTRL
V
SS
Figure 2−2 illustrates the ball locations for the 289-ball GDY ball grid array (BGA) package and is used in
conjunction with Table 2−1 to locate signal names and ball grid numbers. GDY BGA ball numbers in
Figure 2−2 are read from left-to-right, top-to-bottom.
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17
10 12 14 16
2
4
6
8
Bottom View
NOTE: The GDY package has not been released to production and is still in product preview phase.
Figure 2−2. OMAP5910 GDY Package (Bottom View)
In Table 2−2, signals with multiplexed functions are highlighted in gray. Signals within a multiplexed pin name
are separated with forward slashes as follows:
•
signal1/signal2/signal3 (for example, GPIO11/HDQ)
Signals which are associated with specific peripherals are denoted by using the peripheral name, followed
by a period, and then the signal name; as follows:
•
peripheral1.signal1 (for example, MCBSP1.DR)
7
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−2. GDY BGA Terminal Assignments
GDY
BGA
GDY
BGA
GDY
BGA
GDY
BGA
SIGNAL
SIGNAL
SIGNAL
SIGNAL
BALL #
BALL #
BALL #
BALL #
A1
A5
SDRAM.WE
A2
A6
SDRAM.DQMU
SDRAM.D[0]
SDRAM.A[1]
A3
A7
SDRAM.D[9]
SDRAM.CLK
LCD.AC
A4
A8
SDRAM.D[6]
SDRAM.A[9]
LCD.PCLK
LCD.P[3]
DV
DD4
A9
SDRAM.A[5]
LCD.P[9]
A10
A14
B1
A11
A15
B2
A12
A16
B3
A13
A17
B4
DV
LCD.P[6]
DD1
KB.C[5]
FLASH.A[1]
SDRAM.D[11]
SDRAM.A[11]
LCD.P[11]
SDRAM.DQML
SDRAM.D[5]
SDRAM.A[2]
LCD.P[7]
CV
DD1
SDRAM.D[12]
SDRAM.BA[0]
LCD.P[13]
B5
B6
B7
SDRAM.D[2]
SDRAM.A[0]
LCD.P[4]
B8
B9
B10
B14
C1
B11
B15
C2
B12
B16
C3
B13
B17
C4
LCD.P[0]
KB.C[3]
FLASH.A[3]
SDRAM.D[14]
SDRAM.BA[1]
LCD.P[14]
FLASH.A[4]
SDRAM.D[10]
SDRAM.A[8]
LCD.P[8]
FLASH.RDY
SDRAM.D[3]
SDRAM.A[3]
LCD.P[5]
SDRAM.RAS
SDRAM.A[12]
C5
C6
C7
C8
C9
C10
C14
D1
C11
C15
D2
C12
C16
D3
DV
C13
C17
D4
DD1
LCD.P[1]
DV
KB.C[0]
DV
DV
DD5
DD4
FLASH.A[7]
SDRAM.D[7]
SDRAM.A[4]
KB.R[1]
SDRAM.D[15]
D5
DD4
D6
D7
SDRAM.CKE
LCD.VS
D8
DV
D9
SDRAM.A[6]
KB.R[0]
DD4
D10
D14
E1
D11
D15
E2
D12
D16
E3
LCD.P[15]
KB.C[4]
D13
D17
E4
LCD.P[2]
KB.R[4]
FLASH.A[12]
CV
FLASH.A[5]
SDRAM.D[1]
LCD.HS
FLASH.A[6]
DD
SDRAM.D[8]
E5
V
E6
E7
E8
CV
DD
SS
SDRAM.A[10]
E9
E10
E14
F1
DV
DV
DV
E11
E15
F2
E12
E16
F3
LCD.P[10]
KB.C[1]
DD4
DD1
DD5
E13
E17
F4
V
SS
KB.C[2]
KB.R[3]
FLASH.A[11]
FLASH.A[9]
SDRAM.D[4]
LCD.P[12]
KB.R[2]
FLASH.A[10]
SDRAM.CAS
F5
FLASH.A[8]
SDRAM.A[7]
F6
V
SS
F7
F8
F9
F10
F14
CV
F11
F15
DD3
F12
V
SS
F13
MCBSP1.CLKS
PWRON_RESET
MCBSP1.FSX/
MCBSP1.DX
MCBSP1.DX/
MCBSP1.FSX
F16
F17
G1
FLASH.A[16]
G2
FLASH.A[17]
FLASH.A[2]
G3
G7
FLASH.A[14]
G4
G8
FLASH.A[13]
SDRAM.D[13]
G5
G9
FLASH.A[15]
G6
V
SS
V
SS
G10
CV
DD3
CAM.D[6]/
ETM.D[6]/
UWIRE.CS3
CAM.EXCLK/
ETM.SYNC/
UWIRE.SDO
CAM.D[7]/
ETM.D[7]/
UWIRE.CS0
G11
G15
V
G12
G16
G13
G17
G14
H1
SS
CAM.D[3]/
ETM.D[3]/
UART3.RX
MCBSP1.CLKX
MCBSP1.DR
FLASH.A[18]
FLASH.ADV
FLASH.A[21]
H2
H6
FLASH.A[20]
FLASH.A[22]
H3
H7
H4
H8
FLASH.A[19]
H5
H9
DV
V
SS
V
SS
DD5
DD3
UART3.RX/PWL/
UART2.RX
H10
H14
V
SS
H11
H15
CV
H12
H16
H13
H17
DV
DD1
CAM.LCLK/
ETM.CLK/
UWIRE.SCLK
CAM.D[5]/
ETM.D[5]/
UWIRE.SDI
CAM.D[2]/
ETM.D[2]/
UART3.CTS
CAM.D[1]/ETM.D[1]/
UART3.RTS
J1
J5
J9
FLASH.BE[1]
FLASH.BE[0]
J2
J6
FLASH.CS0
J3
J7
FLASH.A[24]
J4
J8
FLASH.A[23]
V
V
V
V
V
V
SS
SS
SS
V
SS
J10
J11
J12
SS
SS
SS
8
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−2. GDY BGA Terminal Assignments (Continued)
GDY
BGA
GDY
BGA
GDY
BGA
GDY
BGA
SIGNAL
SIGNAL
SIGNAL
SIGNAL
BALL #
BALL #
BALL #
BALL #
UART3.TX/
PWT/
UART2.TX
CAM.RSTZ/
ETM.PSTAT[0]/
UART2.RTS
CAM.D[4]/
ETM.D[4]/
UART3.TX
CAM.D[0]/
ETM.D[0]/
MPUIO12
J13
J17
J14
K1
J15
K2
J16
K3
CAM.VS/
ETM.PSTAT[2]
FLASH.CS1
CV
FLASH.D[1]
DD4
FLASH.CS2/
FLASH.BAA
K4
K8
FLASH.CLK
K5
K9
K6
DV
V
K7
CV
CV
DD5
DD2
DD3
V
SS
V
SS
K10
K11
SS
GPIO3/
SPI.CS3/
MCBSP3.FSX/LED1
GPIO6/
SPI.CS1/
MCBSP3.FSX
CAM.HS/
ETM.PSTAT[1]/
UART2.CTS
GPIO13/
KB.R[5]
K12
K13
K14
K15
GPIO15/
KB.R[7]
GPIO14/
KB.R[6]
K16
L3
K17
L4
L1
L5
FLASH.CS3
FLASH.D[0]
L2
L6
DV
DD5
DV
FLASH.D[2]
FLASH.D[3]
DD5
SS
BCLKREQ/
UART3.CTS/
UART1.DSR
L7
V
L8
CV
L9
V
SS
L10
L14
DD2
GPIO4/
SPI.CS2/
MCBSP3.FSX
UWIRE.CS3/
KB.C[6]
MPUIO5/
LOW_PWR
L11
V
SS
L12
L13
GPIO12/
MCBSP3.FSX
GPIO11/
HDQ
GPIO7/
MMC.DAT2
L15
M2
M6
L16
M3
M7
L17
M4
M8
M1
M5
M9
FLASH.D[4]
FLASH.D[7]
FLASH.D[5]
FLASH.D[11]
FLASH.D[6]
GPIO9
UART2.RX/
USB2.VM
MMC.DAT1/
MPUIO7
V
SS
UWIRE.SCLK/
KB.C[7]
M10
UART1.CTS
M11
RST_OUT
M12
V
SS
M13
GPIO0/
SPI.RDY/
USB.VBUS
GPIO2/
SPI.CLK
GPIO1/
UART3.RTS
M14
N1
MPUIO1
M15
N2
M16
N3
M17
N4
FLASH.D[9]
FLASH.D[13]
FLASH.OE
FLASH.D[8]
UART2.CTS/
USB2.RCV/
GPIO7
MCLKREQ/
EXT_MASTER_REQ
N5
V
SS
N6
N7
DV
N8
DD3
CLK32K_OUT/
MPUIO0/
USB1.SPEED
MCSI1.DOUT/
USB1.TXD
N9
CLK32K_IN
N10
N14
N11
N15
RSVD
N12
N16
MPUIO4/
EXT_DMA_REQ1/
LED2
N13
V
SS
I2C.SDA
DV
DD1
MPUIO2/
EXT_DMA_REQ0
N17
P4
P1
P5
FLASH.D[10]
USB0.DP
P2
P6
FLASH.WE
P3
P7
OSC1_OUT
MPUIO3
MCBSP2.FSR/
GPIO12
USB.DM
BCLK/
UART3.RTS/
UART1.DTR
MCSI2.DIN/
USB2.VP
P8
P9
DV
P10
P14
CV
P11
P15
DD1
DD
MCBSP3.CLKX/
USB1.TXEN
P12
MPU_RST
P13
UART1.TX
I2C.SCL
9
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−2. GDY BGA Terminal Assignments (Continued)
GDY
BGA
GDY
BGA
GDY
BGA
GDY
BGA
SIGNAL
SIGNAL
SIGNAL
SIGNAL
BALL #
BALL #
BALL #
BALL #
UWIRE.SDO/
UART3.DTR/
UART1.DTR/
MCBSP3.DX
UWIRE.SDI/
UART3.DSR/
UART1.DSR/
MCBSP3.DR
P16
P17
R1
FLASH.D[12]
R2
OSC1_IN
UART2.TX/
USB2.TXD
MCBSP2.DX/
MCBSP2.DR
MCBSP2.DR/
MCBSP2.DX
R3
R7
FLASH.WP
R4
R8
R5
R9
R6
MCSI2.SYNC/
GPIO7
MMC.DAT2/
MPUIO11
MMC.DAT3/
MPUIO6
MCSI1.DIN/
USB1.RCV
R10
MPU_BOOT/
MCBSP3.DR/
USB1.SUSP
BFAIL/
EXT_FIQ
R11
UART1.RX
R12
R13
TMS
R14
UWIRE.CS0/
MCBSP3.CLKX
R15
T2
CV
R16
T3
R17
T4
EMU0
T1
T5
T9
FLASH.D[14]
DDA
USB.PUEN/
USB.CLKO
MCBSP2.CLKR/
GPIO11
FLASH.RP
UART2.BCLK
MCSI2.DOUT/
USB2.TXEN
MCSI2.CLK/
USB2.SUSP
T6
MCBSP2.FSX
T7
T8
OSC32K_OUT
EMU1
MCSI1.SYNC/
USB1.VP
T10
T14
OSC32K_IN
TCK
T11
T15
T12
T16
DV
T13
T17
DD1
CLK32K_CTRL
CONF
CV
DD
UART2.RTS/
USB2.SE0/
MPUIO5
U1
DV
U2
FLASH.D[15]
U3
DV
U4
DD5
DD2
U5
U9
MCBSP2.CLKX
U6
GPIO8
U7
MCLK
U8
MMC.CMD/SPI.DO
UART1.RTS
MCSI1.CLK/
USB1.VM
MMC.DAT0/SPI.DI
U10
MMC.CLK
U11
U12
RST_HOST_OUT/
MCBSP3.DX/
USB1.SE0
STAT_VAL/
WKUP
U13
U17
U14
U15
TRST
U16
TDO
TDI
2.3 Terminal Characteristics and Multiplexing
Table 2−3 describes terminal characteristics and the signals multiplexed on each ball. The table column
headers are explained below:
•
•
•
SIGNAL NAME: The names of all the signals that are multiplexed on each ball.
TYPE: The terminal type when a particular signal is multiplexed on the terminal.
MUX CTRL SETTING: The register field that controls multiplexing on the terminal and the proper register
field setting necessary to select the signal to be multiplexed on the terminal. The reset values of these
register fields are indicated in bold type.
•
•
DESELECTED INPUT STATE: The logic level internally driven to the signal when it is not selected to be
multiplexed on the corresponding terminal.
PULLUP/PULLDN: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can
be enabled or disabled via software.
•
•
BUFFER STRENGTH: Drive strength of the associated output buffer.
OTHER: Contains various terminal information, such as buffer type, boundary scan capability, and
gating/inhibit functionality. Certain terminals may be gated or 3-stated based on the state of other
terminals and/or software configuration register settings.
10
SPRS197B
August 2002 − Revised August 2003
Introduction
•
•
RESET STATE: The state of the terminal at reset.
SUPPLY: The voltage supply which powers the terminal’s I/O buffers.
NOTE: Due to the extensive pin multiplexing options which are available on the OMAP5910
device, a software utility is available to ease the process of configuring the pins based on the
peripheral set required by a specific application. The 5910 OMAP Pin Configuration Utility is
currently available from Texas Instruments.
NOTE: Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily avoided with proper software configuration.
Table 2−3. Terminal Characteristics and Multiplexing
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
SDRAM.WE
TYPE
OTHER
SUPPLY
‡
#
§
C3
A2
D4
B3
A1
C4
A2
B2
O/Z
O/Z
O/Z
O/Z
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
4 mA
4 mA
4 mA
4 mA
4 mA
A
A
A
A
E
1
1
1
1
0
DV
DV
DV
DV
DV
DD4
DD4
DD4
DD4
DD4
SDRAM.RAS
SDRAM.DQMU
SDRAM.DQML
SDRAM.D[15:0]
D5
C4
B4
D6
C5
H8
C6
B6
D7
C7
D8
B8
G8
C8
G9
B9
D4
C5
G8
B4
B5
C6
A3
E6
D6
A4
B6
F7
C7
B7
E7
A6
I/O/Z
D9
C9
H9
D7
A7
F8
SDRAM.CKE
SDRAM.CLK
SDRAM.CAS
SDRAM.BA[1:0]
O/Z
I/O/Z
O/Z
NA
NA
NA
NA
NA
NA
NA
NA
4 mA
8 mA
4 mA
4 mA
A
E
A
A
1
LZ
1
DV
DV
DV
DV
DD4
DD4
DD4
DD4
D10
C10
C9
B8
O/Z
0
G10
H10
C11
D11
G11
C12
D12
H11
C13
D13
G12
C14
B14
C8
B9
E9
A8
C10
F9
SDRAM.A[12:0]
O/Z
NA
NA
4 mA
A
0
DV
DD4
D9
A9
D10
C11
B10
A10
B11
D14
D11
LCD.VS
O
NA
NA
4 mA
J, A, G1
0
DV
DD1
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
11
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
TYPE
OTHER
SUPPLY
§
‡
#
H12
B15
C15
E11
A11
A12
LCD.HS
O
O
O
O
NA
NA
NA
NA
NA
NA
NA
NA
4 mA
4 mA
4 mA
4 mA
J, A, G1
J, A, G1
J, A, G1
J, A, G1
0
0
0
0
DV
DV
DV
DV
DD1
DD1
DD1
DD1
LCD.AC
LCD.PCLK
LCD.P[15:0]
D15
C16
A17
G13
B17
C17
D16
D17
C18
B19
A20
H13
G14
C19
B21
D18
D12
C13
B12
F11
B13
E12
A13
C14
B14
A15
C15
B15
A16
D15
C16
B16
C20
C21
E18
D19
D20
F18
A17
D16
B17
E15
E16
C17
KB.C[5:0]
KB.R[4:0]
O
NA
NA
NA
NA
4 mA
A, J
A, J
0
DV
DV
DD1
E19
E20
H14
F19
G18
D17
E17
F15
D14
D13
I
input
DD1
G19
G20
G21
H15
F14
F13
G15
F17
PWRON_RESET
MCBSP1.CLKS
MCBSP1.CLKX
MCBSP1.FSX
MCBSP1.DX
MCBSP1.DX
MCBSP1.FSX
MCBSP1.DR
CAM.EXCLK
ETM.SYNC
I
I
NA
NA
NA
NA
0
B, J
B, J
input
input
Z
DV
DV
DV
DV
DD1
DD1
DD1
DD1
NA
I/O/Z
NA
4 mA
4 mA
J, B, G1
J, B, G1
I/O/Z
reg4[14:12] = 000
reg4[14:12] = 001
reg4[17:15] = 000
reg4[17:15] = 001
NA
Z
O
O
NA
NA
0
H18
F16
4 mA
8 mA
8 mA
J, B, G1
0
DV
DD1
I/O/Z
I
H20
H19
G16
G13
NA
NA
NA
NA
0
PD20
B , J
input
0
DV
DV
DD1
O
reg4[23:21] = 000
reg4[23:21] = 001
reg4[23:21] = 010
reg4[26:24] = 000
reg4[26:24] = 001
reg4[26:24] = 010
J, A, G1
DD1
O
UWIRE.SDO
CAM.LCLK
O
J15
H15
I
B, J
input
DV
DD1
ETM.CLK
O
NA
NA
UWIRE.SCLK
O
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
12
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
TYPE
OTHER
SUPPLY
§
‡
#
J18
J19
J14
K18
K19
K15
K14
L19
G14
G12
H16
J15
CAM.D[7]
I
reg4[29:27] = 000
reg4[29:27] = 001
reg4[29:27] = 010
NA
NA
NA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
B, J
input
DV
DV
DV
DV
DV
DV
DV
DV
DD1
DD1
DD1
DD8
DD1
DD1
DD1
DD1
ETM.D[7]
O
O
UWIRE.CS0
CAM.D[6]
ETM.D[6]
I
reg5[2:0] = 000
reg5[2:0] = 001
reg5[2:0] = 010
NA
NA
NA
B, J
B, J
B, J
B, J
B, J
B, J
B, J
input
input
input
input
input
input
input
O
O
UWIRE.CS3
CAM.D[5]
ETM.D[5]
UWIRE.SDI
I
O
I
reg5[5:3] = 000
reg5[5:3] = 001
reg5[5:3] = 010
NA
NA
NA
PD20
CAM.D[4]
ETM.D[4]
UART3.TX
I
reg5[8:6] = 000
reg5[8:6] = 001
reg5[8:6] = 010
NA
NA
NA
O
O
G17
H17
H14
J16
CAM.D[3]
ETM.D[3]
UART3.RX
I
O
I
reg5[11:9] = 000
reg5[11:9] = 001
reg5[11:9] = 010
NA
NA
NA
PD20
PD20
CAM.D[2]
ETM.D[2]
I
O
I
reg5[14:12] = 000
reg5[14:12] = 001
reg5[14:12] = 010
NA
NA
NA
UART3.CTS
CAM.D[1]
ETM.D[1]
I
reg5[17:15] = 000
reg5[17:15] = 001
reg5[17:15] = 010
NA
NA
NA
O
O
UART3.RTS
CAM.D[0]
ETM.D[0]
MPUIO12
I
reg5[20:18] = 000
reg5[20:18] = 001
reg5[20:18] = 010
NA
NA
NA
O
I/O/Z
L18
L15
J17
CAM.VS
I
reg5[23:21] = 000
NA
NA
8 mA
8 mA
B, J
B, J
input
input
DV
DV
DD1
ETM.PSTAT[2]
O
reg5[23:21] = 001
K15
CAM.HS
I
O
I
reg5[26:24] = 000
reg5[26:24] = 001
reg5[26:24] = 010
NA
NA
NA
DD1
ETM.PSTAT[1]
UART2.CTS
PD20
M19
M18
J14
J13
CAM.RSTZ
O
O
O
reg5[29:27] = 000
reg5[29:27] = 001
reg5[29:27] = 010
NA
NA
NA
8 mA
4 mA
J, B, G1
J, A, G1
0
0
DV
DD1
ETM.PSTAT[0]
UART2.RTS
pin forced to drive low
UART3.TX
PWT
O
O
O
O
O
reg6[2:0] = 000
reg6[2:0] = 001
reg6[2:0] = 010
reg6[2:0] = 011
reg6[2:0] = 100
NA
NA
NA
NA
NA
DV
DD1
IRQ_OBS
UART2.TX
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
13
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
TYPE
OTHER
SUPPLY
§
‡
#
L14
H12
UART3.RX
I
reg6[5:3] = 000
reg6[5:3] = 001
reg6[5:3] = 010
reg6[5:3] = 011
reg6[8:6] = 000
1
4 mA
B, J
input
DV
DD1
PWL
O
O
I
NA
NA
NA
NA
DMA_REQ_OBS
UART2.RX
GPIO15
M20
K16
I/O/Z
I
PD20
4 mA
J, B, G1
input
DV
DD1
DD1
KB.R[7]
reg6[8:6] = 001
1
N21
N19
N18
N20
M15
P19
K17
K14
L15
L16
L17
K13
GPIO14
I/O/Z
I
reg6[11:9] = 000
reg6[11:9] = 001
reg6[14:12] = 000
reg6[14:12] = 001
reg6[17:15] = 000
reg6[17:15] = 001
reg6[20:18] = 000
reg6[20:18] = 001
reg6[23:21] = 000
reg6[23:21] = 001
reg6[26:24] = 000
reg6[26:24] = 001
reg6[26:24] = 010
reg6[29:27] = 000
reg6[29:27] = 001
reg6[29:27] = 010
reg7[2:0] = 000
reg7[2:0] = 001
NA
1
PD20
PD20
4 mA
4 mA
4 mA
4 mA
4 mA
4 mA
J, B, G1
J, B, G1
J, B, G1
J, B, G1
J, B, G1
J, B, G1
input
input
input
input
input
input
DV
KB.R[6]
GPIO13
I/O/Z
I
NA
1
DV
DV
DV
DD1
DD1
DD1
DD1
KB.R[5]
GPIO12
I/O/Z
I/O/Z
I/O/Z
I/O
NA
0
PD20
PD20
PD20
PD20
PD20
MCBSP3.FSX
GPIO11
NA
NA
NA
1
HDQ
GPIO7
I/O/Z
I/O/Z
I/O/Z
O
DV
MMC.DAT2
GPIO6
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
0
PD20
DV
DD1
DD1
DD1
SPI.CS1
MCBSP3.FSX
GPIO4
I/O/Z
I/O/Z
O
PD20
PD20
P20
P18
L14
K12
4 mA
4 mA
J, B, G1
J, B, G1
input
input
DV
DV
SPI.CS2
MCBSP3.FSX
GPIO3
I/O/Z
I/O/Z
O
PD20
PD20
SPI.CS3
MCBSP3.FSX
LED1
I/O/Z
O
reg7[2:0] = 010
PD20
PD20
PD20
PD20
reg7[2:0] = 011
M14
R19
R18
M15 GPIO2
SPI.CLK
I/O/Z
O
reg7[5:3] = 000
reg7[5:3] = 001
4 mA
4 mA
4 mA
J, B, G1
J, B, G1
J, B, G1
input
input
input
DV
DV
DV
DD1
DD1
DD1
M17 GPIO1
I/O/Z
O
reg7[8:6] = 000
reg7[8:6] = 001
UART3.RTS
M16 GPIO0
SPI.RDY
I/O/Z
I
reg7[11:9] = 000
reg7[11:9] = 001
reg7[11:9] = 010
reg7[14:12] = 000
reg7[14:12] = 001
USB.VBUS
I
PD20
PD20
T20
L13
MPUIO5
I/O/Z
O
NA
NA
4 mA
J, B, G1
input
DV
DD1
LOW_PWR
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
14
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
TYPE
OTHER
SUPPLY
§
‡
#
T19
N15
N15
MPUIO4
I/O/Z
reg7[17:15] = 000
reg7[17:15] = 001
reg7[17:15] = 010
reg7[20:18] = 000
reg7[20:18] = 001
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
1
PD20
4 mA
J, B, G1
input
DV
DD1
EXT_DMA_REQ1
LED2
I
O
N17
MPUIO2
I/O/Z
PD20
4 mA
J, B, G1
input
DV
DD1
EXT_DMA_REQ0
I
U19
T18
V20
U18
M14 MPUIO1
I/O/Z
4 mA
6 mA
6 mA
4 mA
B, J
J, D, H1
J, D, H1
B, J
input
Z
DV
DV
DV
DV
DD1
DD1
DD1
DD1
P15
N14
P17
I2C.SCL
I/O/Z
NA
I2C.SDA
I/O/Z
NA
Z
UWIRE.SDI
UART3.DSR
UART1.DSR
MCBSP3.DR
UWIRE.SDO
UART3.DTR
UART1.DTR
MCBSP3.DX
I
I
reg8[2:0] = 000
reg8[2:0] = 001
reg8[2:0] = 010
reg8[2:0] = 011
reg8[5:3] = 000
reg8[5:3] = 001
reg8[5:3] = 010
reg8[5:3] = 011
reg8[8:6] = 000
reg8[8:6] = 001
reg8[11:9] = 000
reg8[11:9] = 001
reg8[11:9] = 010
reg8[14:12] = 000
reg8[14:12] = 001
reg8[14:12] = 010
NA
PD20
PD20
PD20
PD20
input
I
1
I
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
W21
P16
O
O
O
O
O
O
Z
4 mA
J, A, G1
0
DV
DD1
V19
N14
M13 UWIRE.SCLK
KB.C[7]
4 mA
4 mA
J, A, G1
J, A
0
Z
DV
DD1
R16
pin forced to high-z
DV
DD1
UWIRE.CS0
MCBSP3.CLKX
pin forced to high-z
UWIRE.CS3
KB.C[6]
O
I/O/Z
Z
P15
L12
4 mA
J, A
Z
DV
DD1
O
O
I
W19
AA20
V18
R14
T15
T16
BFAIL/EXT_FIQ
CLK32K_CTRL
CONF
J, B
J, B
A
input
input
input
DV
DV
DV
DD1
DD1
DD1
I
NA
I
NA
PD10
0
Y19
U17
U16
R13
T14
U15
TDI
I
O
I
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
PD20
B
A
B
B
B
input
0
DV
DV
DV
DV
DV
DD1
DD1
DD1
DD1
DD1
AA19
V17
TDO
TMS
TCK
TRST
4 mA
PD20
PD20
input
input
input
W18
Y18
I
I
PD10
0
V16
W17
Y17
R17
T13
U14
EMU0
I/O/Z
I/O/Z
I
NA
NA
NA
NA
NA
NA
PU10
0
2 mA
2 mA
B
B
A
Z
Z
DV
DD1
EMU1
PU10
0
DV
DD1
STAT_VAL/WKUP
input
DV
DD1
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
15
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
TYPE
OTHER
SUPPLY
§
‡
#
AA17
P14
R12
U13
P14
MPU_BOOT
I
reg8[29:27] = 000
reg8[29:27] = 001
reg8[29:27] = 010
reg9[2:0] = 000
reg9[2:0] = 001
reg9[2:0] = 010
reg9[5:3] = 000
reg9[5:3] = 001
reg9[5:3] = 010
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
0
PD20
PD20
4 mA
4 mA
4 mA
J, B
input
DV
DD1
MCBSP3_DR
USB1_SUSP
RST_HOST_OUT
MCBSP3.DX
USB1.SE0
I
O
O
O
O
Z
J, A, G1
J, A, G1
0
Z
DV
DV
DV
DD1
W16
pin forced to high-z
MCBSP3.CLKX
USB1.TXEN
PD20
PD20
DD1
I/O/Z
O
V15
P12
M11
U12
MPU_RST
I
J, B
J, A
input
DD1
DD1
W15
AA15
RST_OUT
O
NA
4 mA
2 mA
0
0
DV
pin forced to drive low
UART1.RTS
O
reg9[14:12] = 000
reg9[14:12] = 001
NA
J, A, G1
DV
DD1
O
R14
V14
Y14
M10 UART1.CTS
I
PD20
PD20
J, B
J, B
input
input
0
DV
DV
DV
DD1
DD1
DD1
R11
P13
UART1.RX
pin forced to drive low
UART1.TX
I
NA
O
reg9[23:21] = 000
reg9[23:21] = 001
reg9[26:24] = 000
reg9[26:24] = 001
2 mA
2 mA
J, A, G1
O
W14
R13
Y13
N12
L10
P11
MCSI1.DOUT
USB1.TXD
UART1.TX
O
J, A, G1,
H1
0
input
0
DV
DV
DV
DD1
DD1
DD1
O
||
reg9[26:24] = 001
O
BCLKREQ
I
reg9[29:27] = 000
reg9[29:27] = 001
reg9[29:27] = 010
regA[2:0] = 000
regA[2:0] = 001
regA[2:0] = 010
regA[5:3] = 000
regA[5:3] = 001
regA[8:6] = 000
regA[8:6] = 001
PD20
PD20
PD20
J, B
UART3.CTS
UART1.DSR
BCLK
I
0
I
1
O
NA
NA
NA
0
4 mA
J, A, G1
UART3.RTS
UART1.DTR
MCSI1.SYNC
USB1.VP
O
O
V13
T11
U11
I/O/Z
PD20
PD20
PD20
PD20
PD20
PD20
PD20
PD20
2 mA
2 mA
J, B, G1
J, B, G1
input
input
DV
DV
DD1
I
NA
0
AA13
MCSI1.CLK
USB1.VM
I/O/Z
DD1
I
0
||
regA[8:6] = 001
UART1.RX
MCSI1.DIN
USB1.RCV
UART1.CTS
CLK32K_OUT
MPUIO0
I
0
W13
Y12
P13
R10
N10
N9
I
regA[11:9] = 000
NA
0
J, B
J, A
J, B
input
LZ
DV
DV
DV
DD1
DD1
DD1
I
regA[11:9] = 001
||
regA[11:9] = 001
I
O
0
regA[14:12] = 000
regA[14:12] = 001
regA[14:12] = 010
NA
NA
NA
NA
NA
8 mA
I/O/Z
O
USB1.SPEED
CLK32K_IN
I
input
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
16
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
OSC32K_IN
TYPE
OTHER
SUPPLY
§
‡
#
W12
R12
W11
T10
T9
−
NA
NA
NA
1
F
F
NA
NA
NA
OSC32K_OUT
MMC.DAT3
Reserved
−
NA
NA
R9
I/O/Z
NA
regD[14:12] = 000
regD[14:12] = 001
regD[14:12] = 010
NA
PU20
PU20
4 mA
input
DV
DD1
J, B, G1
NA
NA
NA
NA
1
MPUIO6
I/O/Z
O
V11
R11
W10
U10
U9
MMC.CLK
4 mA
4 mA
4 mA
J, A, G1
J, B, G1
J, B, G1
0
DV
DV
DV
DD1
DD1
DD1
MMC.DAT0/SPI.DI
MMC.DAT2
pin forced to hi-z
MPUIO11
I/O/Z
I/O/Z
Z
NA
PU20
PU20
input
input
R8
regA[20:18] = 000
regA[20:18] = 001
regA[20:18] = 010
regA[26:24] = 000
regA[26:24] = 001
regA[26:24] = 010
NA
NA
NA
1
I/O/Z
I/O/Z
NA
PU20
PU20
V10
M9
MMC.DAT1
Reserved
4 mA
J, B, G1
input
DV
DD1
NA
NA
NA
MPUIO7
I/O/Z
I/O/Z
PU20
P11
Y10
U8
T8
MMC.CMD/SPI.DO
PU10
0
4 mA
4 mA
J, B, G1
J, E
input
input
DV
DV
DD1
MCSI2.CLK
USB2.SUSP
MCSI2.DIN
USB2.VP
I/O/Z
O
regB[5:3] = 000
regB[5:3] = 001
regB[8:6] = 000
regB[8:6] = 001
regB[11:9] = 000
regB[11:9] = 001
regB[14:12] = 000
regB[14:12] = 001
NA
0
NA
NA
0
PD20
DD3
AA9
W9
V9
P8
T7
R7
I
PD20
PD20
J, B
J, A, G2
J, E
input
0
DV
DD3
I
MCSI2.DOUT
USB2.TXEN
MCSI2.SYNC
GPIO7
O
NA
NA
0
4 mA
4 mA
DV
DD3
DD3
O
I/O/Z
I/O/Z
O
PD20
PD20
input
DV
NA
NA
0
Y9
U7
N8
MCLK
4 mA
4 mA
J, A, G1
J, E
0
DV
DV
DD3
R10
MCLKREQ
EXT_MASTER_REQ
GPIO9
I
regB[20:18] = 000
regB[20:18] = 001
NA
PD20
input
DD3
O
NA
NA
NA
NA
NA
NA
0
W8
Y8
M8
U6
P7
R6
I/O/Z
I/O/Z
I/O/Z
I
PD20
PD20
PD20
PD20
4 mA
4 mA
4 mA
4 mA
J, E, G3
J, E, G3
J, E, G1
J, B, G2
input
input
input
input
DV
DD3
GPIO8
NA
DV
DD3
V8
MPUIO3
NA
DV
DD3
P10
MCBSP2.DR
MCBSP2.DX
MCBSP2.FSX
MCBSP2.CLKR
GPIO11
regC[2:0] = 000
regC[2:0] = 001
NA
DV
DD3
O
W7
V7
T6
T5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PD20
4 mA
4 mA
J, E, G2
J, E
input
Z
DV
DD3
DD3
regC[8:6] = 000
regC[8:6] = 001
NA
0
DV
NA
NA
0
PD20
PD20
Y6
U5
P6
MCBSP2.CLKX
MCBSP2.FSR
GPIO12
4 mA
4 mA
J, E, G2
J, E
input
Z
DV
DV
DD3
W6
regC[14:12] = 000
regC[14:12] = 001
DD3
NA
PD20
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
17
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
TYPE
OTHER
SUPPLY
§
‡
#
AA5
R9
R5
M7
N6
MCBSP2.DX
O
I
regC[17:15] = 000
regC[17:15] = 001
regC[20:18] = 000
regC[20:18] = 001
regC[23:21] = 000
regC[23:21] = 001
regC[23:21] = 010
regC[26:24] = 000
regC[26:24] = 001
regC[26:24] = 010
regC[26:24] = 011
regC[29:27] = 000
regC[29:27] = 001
regC[29:27] = 010
NA
NA
NA
1
4 mA
4 mA
4 mA
J, E, G2
J, B
0
DV
DD3
DD3
MCBSP2.DR
UART2.RX
USB2.VM
PD20
PD20
PD20
PD20
PD20
PD20
I
input
input
DV
I
0
Y5
UART2.CTS
USB2.RCV
GPIO7
I
1
J, B
J, B
DV
DD3
I
0
I/O/Z
O
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
J, E
W5
V6
U4
R4
pin forced to drive low
UART2.RTS
USB2.SE0
4 mA
4 mA
J, E, G2
0
DV
DD3
O
O
MPUIO5
I/O/Z
O
pin forced to drive low
UART2.TX
USB2.TXD
UART2.BCLK
USB.PUEN
USB.CLKO
USB.DP
J, A, G2
0
DV
DD3
DD3
O
O
Y4
T4
T3
O
4 mA
8 mA
J, A, G2
J, B, G1
0
0
DV
W4
O
regD[5:3] = 000
regD[5:3] = 001
NA
DV
DD2
O
P9
R8
Y2
W3
V4
W2
W1
U4
P5
P4
R2
P3
R3
P2
T2
N3
I/O/Z
I/O/Z
−
18.3 mA
18.3 mA
C
C
F
Z
Z
DV
DD2
USB.DM
NA
DV
DD2
OSC1_IN
NA
NA
NA
0
NA
NA
OSC1_OUT
FLASH.WP
FLASH.WE
FLASH.RP
FLASH.OE
FLASH.D[15:0]
−
NA
F
O/Z
O/Z
O/Z
O/Z
I/O/Z
NA
4 mA
4 mA
4 mA
4 mA
4 mA
A
A
A
A
E
DV
DD5
NA
1
DV
DD5
NA
0
DV
DV
DV
DD5
DD5
DD5
NA
1
V3
T4
U3
U1
P8
T3
T2
R4
R3
R2
P7
P4
P2
N7
N2
N4
U2
T1
N2
R1
M3
P1
N1
N4
M5
M4
M2
M1
L6
NA
0
L4
K3
L5
N3
N8
K4
L1
FLASH.CLK
FLASH.CS3
O/Z
O/Z
NA
NA
NA
NA
8 mA
4 mA
E, G1, H2
A
0
1
DV
DV
DD5
DD5
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
18
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−3. Terminal Characteristics and Multiplexing (Continued)
PU/
PD
GZG
BALL BALL
GDY
MUX CTRL
SETTING
DESELECTED
INPUT STATE
BUFFER
STRENGTH
RESET
STATE
†
¶
SIGNAL NAME
TYPE
OTHER
SUPPLY
§
‡
#
M4
K5
FLASH.CS2
O/Z
O/Z
O/Z
O/Z
O/Z
regD[8:6] = 000
NA
NA
NA
NA
NA
4 mA
A
1
DV
DD5
DD5
FLASH.BAA
FLASH.CS1
FLASH.CS0
FLASH.BE[1:0]
regD[8:6] = 001
M3
M7
K1
J2
NA
NA
NA
4 mA
4 mA
4 mA
A
A
A
1
1
0
DV
DV
DD5
M8
L3
J1
J5
DV
DD5
L4
H1
FLASH.ADV
O/Z
O/Z
NA
NA
NA
NA
4 mA
4 mA
A
1
0
DV
DV
DD5
L7
K3
K4
L8
J1
J3
J4
J2
K7
H3
H4
K8
G2
G3
G4
F3
J7
E3
F4
D2
E4
C1
D3
J8
J3
J4
FLASH.A[24:1]
A, G1
DD5
H6
H5
H2
H4
H3
G2
G1
G5
G3
G4
E1
F2
F4
F3
F5
D2
E4
E3
C2
C1
G6
B1
H7
E5
C3
FLASH.RDY
RSVD
I
NA
NA
NA
NA
B
input
NA
DV
DD5
N11
NA
NA
†
‡
§
¶
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
PD20 = 20-µA internal pulldown, PD100 = 100-µA pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
2
D = I C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#
||
Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
19
August 2002 − Revised August 2003
SPRS197B
Introduction
2.4 Signal Description
Table 2−4 provides a description of the signals on OMAP5910. Many signals are available on multiple pins
depending upon the software configuration of the pin multiplexing options. Ball numbers which are italicized
indicate the default pin muxings at reset. Ball numbers for busses are listed from MSB to LSB (left to right,
top to bottom).
Table 2−4. Signal Description
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
EMIFF SDRAM Interface
SDRAM.WE
C3
A2
D4
A1
C4
A2
SDRAM write enable. SDRAM.WE is active (low) during writes, DCAB, and MRS
commands to SDRAM memory.
O/Z
O/Z
O/Z
SDRAM.RAS
SDRAM row address strobe. SDRAM.RAS is active (low) during ACTV, DCAB,
REFR, and MRS commands to SDRAM memory.
SDRAM.DQMU
SDRAM upper data mask. Active-low data mask for the upper byte of the SDRAM
data bus (SDRAM.D[15:8]). The data mask outputs allow for both 16-bit-wide and
8-bit-wide accesses to SDRAM memories.
SDRAM.DQML
SDRAM.D[15:0]
B3
B2
SDRAM lower data mask. Active-low data mask for the lower byte of the SDRAM
data bus (SDRAM.D[7:0]). The data mask outputs allow for both 16-bit-wide and
8-bit-wide accesses to SDRAM memories.
O/Z
D5,
C4,
B4,
D6,
C5,
H8,
C6,
B6,
D7,
C7,
D8,
B8,
G8,
C8,
G9,
B9
D4,
C5,
G8,
B4,
B5,
C6,
A3,
E6,
D6,
A4,
B6,
F7,
C7,
B7,
D7,
A6
SDRAM data bus. SDRAM.D[15:0] provides data exchange between the Traffic
Controller and SDRAM memory.
I/O/Z
SDRAM.CKE
SDRAM.CLK
D9
C9
H9
D7
A7
F8
SDRAM clock enable. Active-high output which enables the SDRAM clock during
normal operation; SDRAM.CKE is driven inactive to put the memory into
low-power mode.
O/Z
SDRAM clock. Clock for synchronization SDRAM memory commands/accesses.
To minimize voltage undershoot and overshoot effects, it is recommended to place
a series resistor (typically ~33 Ω) close to the SDRAM.CLK driver pin.
I/O/Z
SDRAM.CAS
SDRAM column address strobe. SDRAM.CAS is active (low) during reads, writes,
and the REFR and MRS commands to SDRAM memory.
O/Z
O/Z
SDRAM.BA[1:0]
D10,
C10
C9,
B8
SDRAM bank address bus. Provides the bank address to SDRAM memories.
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
considerations with oscillator circuits.
SS
20
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
EMIFF SDRAM Interface (Continued)
SDRAM.A[12:0]
G10,
H10,
C11,
D11,
G11,
C12,
D12,
H11,
C13,
D13,
G12,
C14,
B14
C8,
B9,
E9,
A8,
C10,
F9,
D9,
SDRAM address bus. Provides row and column address information to the
SDRAM memory as well as MRS command data. SDRAM.A[10] also serves as a
control signal to define specific commands to SDRAM memory.
O/Z
A9,
D10,
C11,
B10,
A10,
B11
EMIFS FLASH and Asynchronous Memory Interface
FLASH.WP
V4
R3
EMIFS write protect. Active-low output for hardware write protection feature on
standard memory devices.
O/Z
O/Z
FLASH.WE
W2
P2
EMIFS write enable. Active-low write enable output for Flash or SRAM memories
or asynchronous devices.
FLASH.RP
FLASH.OE
W1
U4
T2
N3
EMIFS power down or reset output (Intel flash devices)
O/Z
O/Z
EMIFS output enable. Active-low output enable output for Flash or SRAM
memories or asynchronous devices.
FLASH.D[15:0]
V3,
T4,
U3,
U1,
P8,
T3,
T2,
R4,
R3,
R2,
P7,
P4,
P2,
N7,
N2,
N4
U2,
T1,
N2,
R1,
M3,
P1,
N1,
N4,
M5,
M4,
M2,
M1,
L6,
L4,
K3,
L5
EMIFS data bus. Bidirectional 16-bit data bus used to transfer read and write data
during EMIFS accesses.
I/O/Z
FLASH.CLK
N3
K4
EMIFS clock. Clock output that is active during synchronous modes of EMIFS
operation for synchronous burst Flash memories.
O/Z
O/Z
FLASH.CS3
FLASH.CS2
FLASH.CS1
FLASH.CS0
N8
M4
M3
M7
L1
K5
K1
J2
EMIFS chip selects. Active-low chip-select outputs that become active when the
appropriate address is decoded internal to the device. Each chip select decodes a
32M-byte region of memory space.
FLASH.BE[1:0]
FLASH.ADV
FLASH.BAA
M8,
L3
J1,
J5
EMIFS byte enables. Active-low byte enable signals used to perform byte-wide
accesses to memories or devices that support byte enables.
O/Z
O/Z
O/Z
L4
H1
EMIFS address valid. Active-low control signal used to indicate a valid address is
present on the FLASH.A[24:1] bus.
M4
K5
EMIFS burst advance acknowledge. Active-low control signal used with Advanced
Micro Devices burst Flash. FLASH.BAA is multiplexed with FLASH.CS2.
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
SS
considerations with oscillator circuits.
Intel is a registered trademark of Intel Corporation.
Advanced Micro Devices is a trademark of Advanced Micro Devices, Inc.
21
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
EMIFS FLASH and Asynchronous Memory Interface (Continued)
FLASH.A[24:1]
L7,
K3,
K4,
L8,
J1,
J3,
J4,
J2,
K7,
H3,
H4,
K8,
G2,
G3,
G4,
F3,
J7,
E3,
F4,
D2,
E4,
C1,
D3,
J8
J3,
J4,
EMIFS address bus. Address output bus for all EMIFS accesses. FLASH.A[24:1]
provides the upper 24 bits of a 25-bit byte address. The byte enables must be
used to implement 8-bit accesses.
O/Z
H6,
H5,
H2,
H4,
H3,
G2,
G1,
G5,
G3,
G4,
E1,
F2,
F4,
F3,
F5,
D2,
E4,
E3,
C2,
C1,
G6,
B1
FLASH.RDY
H7
C3
EMIFS ready. Active-high ready input used to suspend the EMIFS interface when
the external memory or asynchronous device is not ready to continue the current
cycle. It is recommended that this pin should be pulled high externally and
unused. See the OMAP5910 Dual-Core Processor Silicon Errata (literature
number SPRZ016) for more details.
I
LCD Interface
LCD.VS
D14
H12
B15
D11
E11
A11
LCD vertical sync output. LCD.VS is the frame clock which signals the start of a
new frame of pixels to the LCD panel. In TFT mode, LCD.VS is the vertical
synchronization signal.
O
O
O
LCD.HS
LCD.AC
LCD horizontal sync. LCD.HS is the line clock which signals the end of a line of
pixels to the LCD panel. In TFT mode, LCD.HS is the horizontal synchronization
signal.
LCD AC-bias. LCD.AC is used to signal the LCD to switch the polarity of the row
and column power supplies to counteract charge buildup causing DC offset. In
TFT mode, LCD.AC is used as the output enable to latch LCD pixel data using the
pixel clock.
LCD.PCLK
C15
A12
LCD pixel clock output. Clock output provided to synchronize pixel data to the
LCD panels. In passive mode, LCD.PCLK only transitions when LCD.P[15:0] is
valid. In active mode, LCD.PCLK transitions continuously and LCD.AC is used as
the output enable when LCD.P[15:0] is valid.
O
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
considerations with oscillator circuits.
SS
22
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
LCD Interface (Continued)
LCD.P[15:0]
D15,
C16,
A17,
G13,
B17,
C17,
D16,
D17,
C18,
B19,
A20,
H13,
G14,
C19,
B21,
D18
D12,
C13,
B12,
F11,
B13,
E12,
A13,
C14,
B14,
A15,
C15,
B15,
A16,
D15,
C16,
B16
LCD pixel data bus. Pixel data is transferred on this output bus to LCD panels.
O
Keyboard Matrix Interface
KB.C[7:0]
V19,
P15,
C20,
C21,
E18,
D19,
D20,
F18
M13,
L12,
A17,
D16,
B17,
E15,
E16,
C17
Keyboard matrix column outputs. KB.Cx column outputs are used in conjunction
with the KB.Rx row inputs to implement a 6x5 or 8x8 keyboard matrix.
O
KB.R[7:0]
M20,
N21,
N19,
E19,
E20,
H14,
F19,
G18
K16,
K17,
K14,
D17,
E17,
F15,
D14,
D13
Keyboard matrix row inputs. KB.Rx row inputs are used in conjunction with the
KB.Cx column outputs to implement a 6x5 or 8x8 keyboard matrix.
I
Multichannel Buffered Serial Ports (McBSPs)
MCBSP1.CLKS
G20
F13
McBSP1 clock source. Provides external clock reference for use with transmitter
or reciever. CLKS is only present on McBSP1.
I
MCBSP1.CLKX
MCBSP2.CLKX
MCBSP3.CLKX
G21
Y6
G15
U5
McBSP transmit clock. Serial shift clock reference for the transmitter. CLKX is
present on all McBSPs. In the case of McBSP1 and McBSP3, the clock input to
the McBSP receiver may also be provided on this terminal via an internal
loop-back connection between the transmitter and receiver clocks.
I/O/Z
W16, P6,
N14
R16
MCBSP1.FSX
H15,
H18
F17,
F16
McBSP transmit frame sync. Frame synchronization for transmitter. FSX is
present on all McBSPs. In the case of McBSP1 and McBSP3, the frame sync
input to the McBSP receiver may also be provided on this terminal via an internal
loop-back connection between the transmitter and receiver frame syncs.
I/O/Z
MCBSP2.FSX
MCBSP3.FSX
W7
T6
N18,
P18,
P19,
P20
L15,
K12,
K13,
L14
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
SS
considerations with oscillator circuits.
23
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
Multichannel Buffered Serial Ports (McBSPs) (Continued)
MCBSP1.DX
MCBSP2.DX
MCBSP3.DX
H18,
H15
F16,
F17
McBSP transmit data. Serial transmit data output. DX is present on all McBSPs.
O
AA5,
P10
R5,
R6
P14,
W21
U13,
P16
MCBSP2.CLKR
MCBSP2.FSR
V7
T5
McBSP2 receive clock. Serial shift clock reference for the receiver. CLKR is only
present on McBSP2.
I/O/Z
I/O/Z
I
W6
H20
P6
McBSP2 receive frame sync. Frame synchronization for the receiver. FSR is only
present on McBSP2.
MCBSP1.DR
MCBSP2.DR
G16
McBSP receive data. Serial receive data input. DR is present on all McBSPs.
P10,
AA5
R6,
R5
MCBSP3.DR
AA17, R12,
U18
P17
Camera Interface
CAM.EXCLK
H19
J15
L18
L15
G13
H15
J17
Camera interface external clock. Output clock used to provide a timing reference
to a camera sensor.
O
I
CAM.LCLK
CAM.VS
Camera interface line clock. Input clock to provide external timing reference from
camera sensor logic.
Camera interface vertical sync. Vertical synchronization input from external
camera sensor.
I
CAM.HS
K15
Camera interface horizontal sync. Horizontal synchronization input from external
camera sensor.
I
CAM.D[7:0]
J18,
J19,
J14,
K18,
K19,
K15,
K14,
L19
G14,
G12,
H16,
J15,
G17,
H17,
H14,
J16
Camera interface data. Data input bus to receive image data from an external
camera sensor.
I
CAM.RSTZ
M19
J14
Camera interface reset. Reset output used to reset or Initialize external camera
sensor logic.
O
ETM9 Trace Macro Interface
ETM.CLK
J15
H15
G13
ETM9 Trace Clock. Clock output for standard ETM9 test/debug equipment.
O
O
ETM.SYNC
H19
ETM9 Trace Synchronization. Trace Sync output for standard ETM9 test/debug
equipment.
ETM.D[7:0]
J18,
J19,
J14,
K18,
K19,
K15,
K14,
L19
G14,
G12,
H16,
J15,
G17,
H17,
H14,
J16
ETM9 Trace Packet data. Trace Packet outputs for standard ETM9 test/debug
equipment.
O
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
considerations with oscillator circuits.
SS
24
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
ETM9 Trace Macro Interface (Continued)
ETM.PSTAT[2:0]
L18,
L15,
M19
J17,
K15,
J14
ETM9 Trace Pipe State 2−0. Pipeline status outputs for standard ETM9 test/debug
equipment.
O
Microwire Interface
UWIRE.SCLK
V19,
J15
M13,
H15
Microwire serial clock. This pin drives a clock to a Microwire device. The active
edge is software configurable.
O
O
I
UWIRE.SDO
UWIRE.SDI
UWIRE.CS0
UWIRE.CS3
W21, P16,
H19
Microwire serial data out. Write data is transferred to a Microwire device on this
pin.
G13
U18,
J14
P17,
H16
Microwire serial data in. Read data is transferred from a Microwire device on this
pin.
N14,
J18
R16,
G14
Microwire chip select 0. The CS0 output selects a single Microwire device
(configurable as active high or active low).
O
O
P15,
J19
L12,
G12
Microwire chip select 3. The CS3 output selects a single Microwire device
(configurable as active high or active low).
HDQ/1-Wire Interface
HDQ
N20
L16
HDQ/1-wire interface. HDQ optionally implements one of two serial protocols:
HDQ or 1-Wire.
I/O
General-Purpose I/O (GPIO) and MPU I/O (MPUIO)
GPIO15
GPIO14
GPIO13
GPIO12
M20
N21
N19
K16
K17
K14
Shared General-Purpose I/O. Each GPIO pin can be used by either the DSP core
or the MPU core. Control of each GPIO pin between the two cores is selected by
the MPU via control registers. Each GPIO pin may also be configured to cause an
interrupt to its respective core processor.
I/O/Z
N18,
L15,
W6
P6
GPIO5 and GPIO10 are not available on the OMAP5910 device.
GPIO11
N20,
L16,
V7
T5
GPIO9
GPIO8
GPIO7
W8
Y8
M8
U6
M15,
Y5,
V9
L17,
N6,
R7
GPIO6
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
P19
P20
P18
M14
R19
R18
K13
L14
K12
M15
M17
M16
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
SS
considerations with oscillator circuits.
25
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−4. Signal Description (Continued)
†
TYPE
SIGNAL
GZG
GDY
DESCRIPTION
BALL BALL
General-Purpose I/O (GPIO) and MPU I/O (MPUIO) (Continued)
MPUIO12
MPUIO11
MPUIO7
MPUIO6
MPUIO5
L19
J16
R8
M9
R9
MPU General-Purpose I/O. MPUIO pins may only be used by the MPU core.
I/O/Z
W10
V10
W11
MPUIO8, MPUIO9, AND MPUIO10 are not available on the OMAP5910 device.
T20,
L13,
W5
U4
MPUIO4
MPUIO3
MPUIO2
MPUIO1
MPUIO0
T19
V8
N15
P7
N15
U19
Y12
N17
M14
N10
Pulse-Width Tone and Pulse-Width Light Interface
PWT
M18
J13
Pulse Width Tone output. The PWT output pin provides a modulated output for use
with an external buzzer.
O
O
PWL
L14
H12
Pulse Width Light output. The PWL output pin provides a pseudo-random
modulated voltage output used for LCD or keypad backlighting.
Multimedia Card/Secure Digital Interface (MMC/SD)
MMC.CLK
V11
P11
U10
U8
MMC/SD clock. Clock output to the MMC/SD card.
O
MMC.CMD/SPI.DO
MMC/SD command / SPI data output. MMC/SD commands are transferred to/from
this pin. The pin functions as the data output during SPI mode.
I/O/Z
MMC.DAT3
MMC.DAT2
W11
R9
SD card data bit 3. Data bit 3 used in 4-bit Secure Digital mode.
SD card data bit 2. Data bit 2 used in 4-bit Secure Digital mode.
I/O/Z
I/O/Z
W10, R8,
M15
V10
R11
L17
M9
U9
MMC.DAT1
SD card data bit 1. Data bit 1 used in 4 -bit Secure Digital mode.
I/O/Z
I/O/Z
MMC.DAT0/SPI.DI
MMC/SD dat0 / SPI input. MMC.DAT0/SPI.DI functions as data bit 0 during MMC
and Secure Digital operation. The pin functions as the data input in generic SPI
mode.
SPI.CLK
SPI.CS3
SPI.CS2
SPI.CS1
SPI.RDY
M14
P18
P20
P19
R18
M15
K12
L14
K13
M16
SPI clock. SPI clock output used during generic SPI mode operation.
SPI chip selects. SPI chip selects used during generic SPI mode operation.
O
O
SPI ready. SPI ready input from SPI device used only in generic SPI mode
operation.
I
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
considerations with oscillator circuits.
SS
26
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
Universal Asynchronous Receiver/Transmitter Interfaces
UART1.TX
UART2.TX
Y14
P13
UART transmit. Transmit data output. TX is present on all UARTs. On UART3, the
TX pin implements the TXIR function during SIR mode operation.
O
V6,
M18
R4,
J13
UART3.TX
M18,
K18
J13,
J15
UART1.RX
UART2.RX
V14
R11
UART receive. Receive data input. RX is present on all UARTs. On UART3, the
RX pin implements the RXIR function during SIR mode operation.
I
I
R9,
L14
M7,
H12
UART3.RX
L14,
K19
H12,
G17
UART1.CTS
UART2.CTS
R14
M10
UART clear-to-send. CTS is present on all UARTs.
Y5,
N6,
L15
K15
UART3.CTS
R13,
K15
L10,
H17
UART1.RTS
UART2.RTS
AA15 U12
UART request-to-send. RTS is present on all UARTs. On UART3 in IrDA mode,
this pin is SD_MODE.
O
W5,
M19
U4,
J14
UART3.RTS
UART1.DTR
Y13,
R19
P11,
M17
W21, P16,
Y13
UART data-terminal-ready. DTR is only present on UART1 and UART3.
UART data-set-ready. DSR is only present on UART1 and UART3.
O
I
P11
UART3.DTR
UART1.DSR
W21
P16
U18,
R13
P17,
L10
UART3.DSR
UART2.BCLK
U18
P17
Y4
T4
UART baud clock output. A clock of 16x of the UART2 baud rate is driven onto this
pin. This feature is only implemented on UART2.
O
Inter-Integrated Circuit Master and Slave Interface
2
2
I2C.SCL
I2C.SDA
T18
V20
P15
N14
I C serial clock. I2C.SCL provides the timing reference for I C transfers.
I/O/Z
I/O/Z
2
2
I C serial data. I2C.SDA provides control and data for I C transfers.
LED Pulse Generator Interface
LED1
P18
K12
N15
LED Pulse Generator output 1. LED1 produces a static or pulsing output used to
drive an external LED indicator.
O
O
LED2
T19
LED Pulse Generator output 2. LED2 produces a static or pulsing output used to
drive an external LED indicator.
Multichannel Serial Interfaces (MCSIs)
MCSI1.CLK
MCSI2.CLK
MCSI1.SYNC
AA13 U11
MCSI clock. Multichannel Serial Interface clock reference. The clock can be driven
in master mode or an external clock may be driven on this signal in slave mode.
I/O/Z
I/O/Z
Y10
V13
T8
T11
MCSI sync. Multichannel Serial Interface frame synchronization signal. The frame
sync can be driven in master mode or an external clock may be driven on this
signal in slave mode. MCSIx.SYNC may be configured as an active-low or
active-high sync.
MCSI2.SYNC
V9
R7
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
SS
considerations with oscillator circuits.
27
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
Multichannel Serial Interfaces (MCSIs) (Continued)
MCSI1.DIN
W13
AA9
W14
W9
R10
P8
MCSI data in. Multichannel Serial Interface data input pin.
I
MCSI2.DIN
MCSI1.DOUT
MCSI2.DOUT
N12
T7
MCSI data out. Multichannel Serial Interface data output pin.
O
USB (Integrated Transceiver Interface, can be used with Host or Function)
USB.DP
P9
P5
USB internal transceiver D+. The positive side of the integrated USB transceiver’s
differential bus. A series resistor of 27 Ω (5% tolerance) is required on the
USB.DP pin.
I/O/Z
I/O/Z
USB.DM
R8
P4
USB internal transceiver D−. The negative side of the integrated USB
transceiver’s differential bus. A series resistor of 27 Ω (5% tolerance) is required
on the USB.DM pin.
USB Pin Group 1 and 2 (Utilizing External Transceivers, can be used with Host or Function)
USB1.TXEN
USB2.TXEN
USB1.TXD
W16
W9
T6
USB transmit enable. Driven active (high) when the USB host or Function
peripheral is driving data onto the USB bus via the TXD output.
O
O
T7
W14
N12
USB transmit data. Single-ended logic output used to transmit data to the transmit
input of an external USB transceiver. USBx.TXD may also be used for
transceiverless connection between OMAP5910 and another transceiverless USB
device.
USB2.TXD
V6
R4
USB1.VP
USB2.VP
USB1.VM
USB2.VM
USB1.RCV
V13
AA9
T11
P8
USB vplus data. Single-ended input used to monitor the logical state of the D+ line
of the USB bus. USBx.VP should be driven by an external USB transceiver based
on the state of D+.
I
I
I
AA13 U11
USB vminus data. Single-ended input used to monitor the logical state of the D−
line of the USB bus. USBx.VM should be driven by an external USB transceiver
based on the state of D−.
R9
M7
W13
R10
USB receive data. Single-ended logic input used to receive data from the receive
output of an external USB transceiver. USBx.RCV may also be used for
transceiverless connection between OMAP5910 and another transceiverless USB
device.
USB2.RCV
Y5
N6
USB1.SUSP
USB2.SUSP
AA17 R12
USB bus segment suspend control. Active-high output indicates detection of IDLE
condition on the USB bus for greater than 5 ms. USBx.SUSP is implemented on
both USB ports 1 and 2.
O
Y10
T8
USB1.SE0
P14
W5
U13
U4
USB single-ended zero. Active-high output indicates detection of the single-ended
zero state on the USB bus. USBx.SE0 is implemented for both USB ports 1 and 2.
O
O
USB2.SE0
USB1.SPEED
Y12
N10
USB 1 bus segment speed control. Static control output used by the external
transceiver to determine whether USB port 1 is operating in full-speed or
low-speed mode. USB1.SPEED is only implemented on USB port 1.
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
considerations with oscillator circuits.
SS
28
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
USB Miscellaneous Signals
USB.CLKO
W4
T3
USB clock output. 6-MHz divided clock output of the internal USB DPLL provided
for reference. Common for all USB host and Function peripherals.
O
O
USB.PUEN
USB.VBUS
W4
T3
USB pullup enable. Control output used in conjunction with an external pullup
resistor to implement USB device connect and disconnect via software.
USB.PUEN is used with the USB Function peripheral.
R18
M16
USB voltage bus enable. USB.VBUS is used to provide a logic-high voltage level
which may be used to enable pullup resistors on the USB bus to indicate
connection or disconnection status of the OMAP5910 device as a USB Function
device.
I
JTAG/Emulation Interface
TCK
W18
Y19
T14
U17
IEEE Standard 1149.1 test clock. TCK is normally a free-running clock signal with
a 50% duty cycle. The changes on the test access port (TAP) of input signals TDI
and TMS are clocked into the TAP controller, instruction register, or selected test
data register on the rising edge of TCK. Changes at the TAP output signal TDO
occur on the falling edge of TCK.
I
TDI
IEEE Standard 1149.1 test data input. TDI is clocked into the selected register
(instruction or data) on the rising edge of TCK.
I
TDO
AA19 U16
IEEE Standard 1149.1 test data output. The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in
the high-impedance state except when the scanning of data is in progress.
O
TMS
V17
Y18
R13
U15
IEEE Standard 1149.1 test mode select. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
I
I
TRST
IEEE Standard 1149.1 test reset. TRST, when high, gives the IEEE standard
1149.1 scan system control of the operations of the device. If TRST is not
connected, or driven low, the device operates in its functional mode, and the IEEE
standard 1149.1 signals are ignored.
EMU0
EMU1
V16
R17
T13
Emulation pin 0. When TRST is driven high, EMU0 is used as an interrupt to or
from the emulator system and is defined as input/output by way of the IEEE
standard 1149.1 scan system.
I/O
I/O
W17
Emulation pin 1. When TRST is driven high, EMU1 is used as an interrupt to or
from the emulator system and is defined as input/output by way of the IEEE
standard 1149.1 scan system.
Device Clock Pins
CLK32K_IN
P13
Y12
N9
32-kHz clock input. Digital CMOS 32-kHz clock input driven by an external
32-kHz oscillator if the internal 32-kHz oscillator is not used.
I
CLK32K_OUT
CLK32K_CTRL
N10
32-kHz clock output. Clock output reflecting the internal 32-kHz clock.
O
I
AA20 T15
32-kHz clock selection control input. CLK32K_CTRL selects whether or not the
internal 32-kHz oscillator is used or if the 32-kHz clock is to be provided externally
via the CLK32K_IN input. If CLK32K_CTRL is high, the 32-kHz internal oscillator
is used; if CLK32K_CTRL is low, the CMOS input CLK32K_IN is used as a 32-kHz
clock source.
OSC32K_IN
OSC32K_OUT
OSC1_IN
W12
R12
Y2
T10
T9
32-kHz crystal XI connection. Analog clock input to 32-kHz oscillator for use with
external crystal.
analog
analog
analog
32-kHz crystal XO connection. Analog output from 32-kHz oscillator for use with
external crystal.
R2
Base crystal XI connection. Analog input to base oscillator for use with external
crystal or to be driven by external 12- or 13-MHz oscillator.
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
SS
considerations with oscillator circuits.
29
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−4. Signal Description (Continued)
†
TYPE
SIGNAL
GZG
GDY
DESCRIPTION
BALL BALL
Device Clock Pins (Continued)
OSC1_OUT
W3
P3
U7
Base crystal XO connection. Analog output from base oscillator for use with
external 12- or 13-MHz crystal.
analog
O
MCLK
Y9
M-Clock. General-purpose clock output which may be configured to run at 12 MHz
or 48 MHz. MCLK may be configured to drive constantly or only when the
MCLKREQ signal is asserted active high.
BCLK
Y13
P11
B-Clock. General purpose clock output which may be configured to run at
12 MHz. BCLK may be configured to drive constantly or only when the BCLKREQ
signal is asserted active high.
O
MCLKREQ
BCLKREQ
R10
R13
N8
M-Clock Request. Active high request input which allows an external device to
request that MCLK be driven.
I
I
L10
B-Clock Request. Active high request input which allows an external device to
request that BCLK be driven.
Reset Logic Pins
PWRON_RESET
G19
F14
Reset input to device. Active-low asynchronous reset input resets the entire
OMAP5910 device.
I
MPU_RST
RST_OUT
V15
P12
M11
MPU reset input. Active-low asynchronous reset input resets the MPU core.
I
W15
Reset output. Active-low output is asserted when MPUST is active (after
synchronization.)
O
Interrupts and Miscellaneous Control and Configuration Pins
MPU_BOOT
AA17 R12
MPU boot mode. When MPU_BOOT is low, the MPU boots from chip select 0 of
the EMIFS (Flash) interface. When MPU_BOOT is high, the MPU boots from chip
select 3 of EMIFS.
I
DMA_REQ_OBS
IRQ_OBS
L14
M18
T19
H12
J13
N15
DMA request external observation output.
IRQ external observation output.
O
O
I
EXT_DMA_REQ1
External DMA requests. EXT_DMA_REQ0 and EXT_DMA_REQ1 provide two
DMA request inputs which external devices may use to trigger System DMA
transfers. The System DMA must be configured in software to respond to these
external requests.
EXT_DMA_REQ0
BFAIL/EXT_FIQ
N15
N17
W19
R14
Battery power failure and external FIQ interrupt input. BFAIL/EXT_FIQ may be
used to gate certain input pins when battery power is low or failing. The pins which
may be gated are configured via software. This pin can also optionally be used as
an external FIQ interrupt source to the MPU. The function of this pin is
configurable via software.
I
EXT_MASTER_REQ
LOW_PWR
R10
T20
N8
External master request. If the 12-MHz clock is provided by an external device
instead of using the on-chip oscillator, a high level on this output indicates to the
external device that the clock must be driven. A low level indicates that the
OMAP5910 device is in sleep mode and the 12-MHz clock is not necessary.
O
O
L13
Low-power request output. This active-high output indicates that the OMAP5910
device is in a low-power sleep mode. During reset and functional modes,
LOW_PWR is driven low. This signal can be used to indicate a low-power state to
external power management devices in a system or it can be used as a chip
select to external SDRAM memory to minimize current consumption while the
SDRAM is in self-refresh and the OMAP5910 device is in sleep mode.
CONF
V18
T16
Configuration input. CONF selects reserved factory test modes. CONF should
always be pulled low during device operation.
I
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
considerations with oscillator circuits.
SS
30
SPRS197B
August 2002 − Revised August 2003
Introduction
Table 2−4. Signal Description (Continued)
†
SIGNAL
GZG
GDY
DESCRIPTION
TYPE
BALL BALL
Interrupts and Miscellaneous Control and Configuration Pins (Continued)
STAT_VAL/WKUP
Y17
U14
Static Valid / Chip wake-up input. STAT_VAL/WKUP may be configured via
software to function as an external wake-up signal to the OMAP5910 device to
request chip wake-up during sleep modes. STAT_VAL/WKUP is also sampled at
reset to select the MMC/SD port. If the MMC/SD peripheral is to be used, this pin
must be pulled high during reset. It is recommended that this pin be pulled high
during reset regardless of whether or not MMC/SD will be used.
I
RST_HOST_OUT
P14
E5
U13
N11
Reset Host output. A software controllable Reset or Shutdown output to an
external device.
O
−
RSVD
Reserved pin. This pin must be left unconnected.
Power Supplies
§
V
SS
A21,
B1,
B2,
B5,
B7,
B16,
B18,
E2,
N5,
H8,
G11,
M6,
L11,
K8,
Ground. Common ground return for all core and I/O voltage supplies.
power
J12,
J9,
F20,
G1,
J20,
K2,
G7,
E5,
J7,
J8,
K20,
N1,
R21,
U2,
U20,
V5,
J6,
J10,
K10,
H10,
F12,
L7,
V12,
F6,
W20, L9,
Y3,
K9,
Y15,
AA1,
AA7,
M12,
E13,
J11,
AA21 N13
‡
CV
A9,
F2,
E8,
E2,
Core supply voltage. Supplies power to OMAP5910 core logic and low-voltage
sections of I/O.
power
DD
P12,
Y20
T17,
P10
‡
‡
‡
CV
CV
CV
A3
B3
Core Supply Voltage 1. Supplies power to the on-chip shared SRAM memory
(192k-Bytes).
power
power
power
DD1
DD2
DD3
Y1,
AA3
K7,
L8
Core Supply Voltage 2. Supplies power to the MPU subsystem logic and memory.
B13,
B20,
J21,
R20
F10,
G10,
H11,
K11
Core Supply Voltage 3. Supplies power to the DSP subsystem logic and memory.
‡
CV
M2
K2
Core Supply Voltage 4. Supplies power to the DPLL which provides internal clocks
to the core and peripherals (excluding USB peripherals). NOTE: The voltage to
this supply pin should be kept as clean as possible to maximize performance.
power
DD4
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
SS
considerations with oscillator circuits.
31
August 2002 − Revised August 2003
SPRS197B
Introduction
Table 2−4. Signal Description (Continued)
†
TYPE
SIGNAL
Power Supplies (Continued)
GZG
BALL BALL
GDY
DESCRIPTION
‡
CV
Y21
R15
Analog supply voltage. Supplies power to ULPD DPLL which provides an internal
clock to the USB peripherals. NOTE: The voltage to this supply pin should be kept
as clean as possible to maximize performance.
power
power
DDA
DV
A15,
A19,
E21,
L21,
U21,
C12,
A14,
E14,
H13,
U21,
I/O Supply Voltage 1. Supplies power to the majority of peripheral I/O buffers.
DD1
DV
may be connected in common with the other DV supplies if the same
DD1
operating voltage is desired.
DD
AA11, P9,
Y16
T12
DV
DV
DV
DV
AA2
U3
I/O Supply Voltage 2. Supplies power to the internal USB transceiver buffers.
DV may optionally be used for USB connect & disconnect detection by
power
power
power
power
DD2
DD3
DD4
DD5
DD2
connecting DV
to the power from the USB bus in the system. DV
may be
DD2
DD2
supplies if the same operating voltage
connected in common with the other DV
is desired.
DD
Y7
N7
I/O Supply Voltage 3. Supplies power to the MCSI2 and McBSP2 peripheral I/O
buffers as well as GPIO[9:8] I/O buffers. The DV supply may operate within a
DD3
high-voltage or low-voltage range (see Section 5.2 for operating conditions).
DV may be connected in common with the other DV supplies if the same
DD3
operating voltage is desired.
DD
A1,
A5,
A7,
B10,
B12
D3,
D5,
A5,
D8,
E10
I/O Supply Voltage 4. Supplies power to the SDRAM interface I/O buffers. The
DV supply may operate within a high-voltage or low-voltage range (see
DD4
Section 5.2 for operating conditions). DV
may be connected in common with
DD4
supplies if the same operating voltage is desired.
the other DV
DD
C2,
E1,
H2,
L1,
P3,
R1,
V2
H7,
D1,
F1,
K6,
L2,
L3,
U1
I/O Supply Voltage 5. Supplies power to the FLASH interface I/O buffers. The
DV supply may operate within a high-voltage or low-voltage range (see
DD5
Section 5.2 for operating conditions). DV
may be connected in common with
DD5
supplies if the same operating voltage is desired.
the other DV
DD
†
‡
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§
See Sections 5.6.1 and 5.6.2 for special V
considerations with oscillator circuits.
SS
32
SPRS197B
August 2002 − Revised August 2003
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
Figure 3−1. OMAP5910 Functional Block Diagram
33
August 2002 − Revised August 2003
SPRS197B
Functional Overview
3.1 Functional Block Diagram Features
The OMAP5910 device includes the following functional blocks:
•
ARM9TDMI-based MPU core
−
−
−
−
16K-byte instruction cache and 8K-byte data cache
Memory Management Units (MMUs) for Instruction and Data
Two 64-entry Translation Look-Aside Buffers (TLBs) for MMUs
17-word write buffer
•
C55x DSP subsystem
−
−
−
−
−
−
48K-word single-access RAM (SARAM) (96K bytes)
32K-word dual-access RAM (DARAM) (64K bytes)
16K-word ROM (32K bytes)
24K-byte instruction cache
Six-channel DMA controller
Hardware Accelerators for DCT, iDCT, pixel interpolation, and motion estimation
•
•
Nine-channel system DMA controller
Traffic controller providing shared access to three memory interfaces:
−
−
EMIFF External Memory Interface providing 16-bit interface to 64M bytes of standard SDRAM
EMIFS External Memory Interface providing 16-bit interface to 128M bytes of Flash, ROM, or
asynchronous memories
−
Internal Memory Interface (IMIF) providing 32-bit interface to 192K bytes of internal SRAM
•
•
DSP Memory Management Unit (MMU) configured by the MPU
MPU Interface (MPUI) allowing MPU and System DMA to access DSP subsystem memory and DSP
public peripherals
•
•
Local Bus Interface (with MMU) allowing USB host peripheral direct access to system memories.
DSP Private Peripherals (accessible only by the DSP)
−
−
−
Three 32-bit general-purpose timers
Watchdog timer
Level 1/Level 2 interrupt handlers
•
•
DSP Public Peripherals (accessible by the DSP, DSP DMA, and the MPU via the MPU interface)
−
−
Two Multichannel Buffered Serial Ports (McBSPs)
Two Multichannel Serial Interfaces (MCSIs) ideal for voice data
MPU Private Peripherals (accessible only by the MPU)
−
−
−
−
−
Three 32-bit general-purpose timers
Watchdog Timer
Level 1/Level 2 interrupt handlers
Configuration Registers for pin-multiplexing and other device-level configurations
LCD controller supporting monochrome panels or STN and TFT color panels
34
SPRS197B
August 2002 − Revised August 2003
Functional Overview
•
MPU Public Peripherals (accessible by the MPU and the System DMA)
−
−
−
Multichannel Buffered Serial Port (McBSP)
USB Function interface (optional internal transceiver shared with USB Host interface)
USB Host interface with up to three ports (optional internal transceiver shared with USB Function
interface)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
One integrated USB transceiver for either host or Function
Inter-Integrated Circuit (I C) Multi-mode master and slave interface
Microwire serial interface
2
Camera interface providing connectivity to CMOS image sensors
Up to ten MPU general-purpose I/Os (MPUIOs)
32-kHz timer for use with MPU OS
Pulse-Width Tone (PWT) module for tone generation
Pulse-Width Light (PWL) module for LCD backlight control
Keyboard interface (6 x 5 or 8 x 8 matrix)
Multimedia Card or Secure Digital interface (MMC/SD) − also configurable as generic SPI port
Two LED Pulse Generator modules (LPG)
Real-Time Clock module (RTC)
HDQ or 1-Wire Master interface for serial communication to battery management devices
Frame Adjustment Counter (FAC)
•
•
MPU/DSP Shared Peripherals (Controlling processor is selected by the MPU)
−
−
−
Four Mailboxes for interprocessor communications
Up to 14 General-Purpose I/O pins with interrupt capability to either processor
Three UARTs (UART3 has SIR mode for IrDA functionality)
Clock/Reset/Power Management modules
−
−
−
−
Configurable Digital Phase-Locked Loop (DPLL) providing clocks to MPU, DSP, and TC
Dedicated USB DPLL providing clocking to USB modules
Integrated base (12- or 13-MHz) and 32-kHz oscillators utilizing external crystals
Reset, clocking and idle/sleep controls for power management
•
JTAG and ETM9 interfaces for emulation and debug
35
August 2002 − Revised August 2003
SPRS197B
Functional Overview
3.2 MPU Memory Maps
3.2.1 MPU Global Memory Map
The MPU has a unified address space. Therefore, the internal and external memories for program and data
as well as peripheral registers and configuration registers are all accessed within the same address space.
The MPU space is always addressed using byte addressing. Table 3−1 provides a high level illustration of
the entire MPU addressable space. Further detail regarding the peripheral and configuration registers is
provided in Sections 3.2.2, 3.15, and 3.17.
Table 3−1. OMAP5910 MPU Global Memory Map
BYTE ADDRESS RANGE
0x0000 0000 − 0x01FF FFFF
0x0200 0000 − 0x03FF FFFF
0x0400 0000 − 0x05FF FFFF
0x0600 0000 − 0x07FF FFFF
0x0800 0000 − 0x09FF FFFF
0x0A00 0000 − 0x0BFF FFFF
0x0C00 0000 − 0x0DFF FFFF
0x0E00 0000 − 0x0FFF FFFF
0x1000 0000 − 0x13FF FFFF
0x1400 0000 − 0x1FFF FFFF
0x2000 0000 − 0x2002 FFFF
ON-CHIP
EXTERNAL INTERFACE
EMIFS (Flash CS0)
32M bytes
Reserved
Reserved
Reserved
Reserved
Reserved
EMIFS (Flash CS1)
32M bytes
EMIFS (Flash CS2)
32M bytes
EMIFS (Flash CS3)
32M bytes
EMIFF (SDRAM)
64M bytes
IMIF Internal SRAM
192K bytes
0x2003 0000 − 0x2FFF FFFF
0x3000 0000 − 0x5FFF FFFF
0x6000 0000 − 0xDFFF FFFF
Reserved
Reserved
Local Bus space for USB Host
DSP public memory space
(accessible via MPUI)
16M bytes
0xE000 0000 − 0xE0FF FFFF
DSP public peripherals
(accessible via MPUI)
0xE100 0000 − 0xEFFF FFFF
0xF000 0000 − 0xFFFA FFFF
0xFFFB 0000 − 0xFFFB FFFF
0xFFFC 0000 − 0xFFFC FFFF
0xFFFD 0000 − 0xFFFE FFFF
0xFFFF 0000 − 0xFFFF FFFF
Reserved
Reserved
†
MPU public peripherals
MPU/DSP shared peripherals
MPU private peripherals
†
Some peripherals within this memory region are actually shared peripherals (UART 1,2,3).
36
SPRS197B
August 2002 − Revised August 2003
Functional Overview
3.2.2 MPU Subsystem Registers Memory Map
The MPU accesses peripheral and configuration registers in the same way that internal and external memory
is accessed. The following tables specify the MPU base addresses where each set of registers is accessed.
All accesses to these registers must utilize the appropriate access width (8-, 16-, or 32-bit-wide accesses) as
indicated in the tables. Accessing registers with the incorrect access width may result in unexpected results
including a TI Peripheral Bus (TIPB) bus error and associated TIPB interrupt.
Refer to Sections 3.15, 3.16, and 3.17 for more detail about each of these register sets including individual
register addresses, register names, descriptions, supported access types (read, write or read/write) and reset
values.
Table 3−2. MPU Private Peripheral Registers
ACCESS
WIDTH
MPU BASE ADDRESS
REGISTER SET
0xFFFE 0000
0xFFFE C000
0xFFFE C500
0xFFFE C600
0xFFFE C700
0xFFFE C800
0xFFFE CB00
0xFFFE D800
MPU Level 2 Interrupt Handler Registers
LCD Controller Registers
32
32
MPU Timer1 Registers
32
MPU Timer2 Registers
32
MPU Timer3 Registers
32
MPU Watchdog Timer Registers
MPU Level 1 Interrupt Handler Registers
System DMA Controller Registers
32
32
16
Table 3−3. MPU Public Peripheral Registers
ACCESS
WIDTH
MPU BASE ADDRESS
REGISTER SET
0xFFFB 1000
0xFFFB 3000
0xFFFB 3800
0xFFFB 4000
0xFFFB 4800
0xFFFB 5000
0xFFFB 5800
0xFFFB 6000
0xFFFB 6800
0xFFFB 7800
0xFFFB 9000
0xFFFB A000
0xFFFB A800
0xFFFB C000
0xFFFB D000
0xFFFB D800
McBSP2 Registers
Microwire Registers
16
16
16
16
8
2
I C Registers
USB Function Registers
RTC Registers
MPUIO/Keyboard Registers
Pulse Width Light (PWL) Registers
Pulse Width Tone (PWT) Registers
Camera Interface Registers
MMC/SD Registers
16
8
8
32
16
32
32
16
8
Timer 32k Registers
USB Host Registers
Frame Adjustment Counter (FAC) Registers
HDQ/1-Wire Registers
LED Pulse Generator 1 (LPG1) Registers
LED Pulse Generator 2 (LPG2) Registers
8
8
Table 3−4. MPU/DSP Shared Peripheral Registers
ACCESS
WIDTH
MPU BASE ADDRESS
REGISTER SET
0xFFFB 0000
0xFFFB 0800
0xFFFB 9800
0xFFFC E000
0xFFFC F000
UART1 Registers
UART2 Registers
8
8
UART3 Registers
8
GPIO Interface Registers
Mailbox Registers
16
16
37
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−5. DSP Public Peripheral Registers (Accessible via MPUI Port)
ACCESS
WIDTH
MPU BASE ADDRESS
REGISTER SET
0xE101 1800
0xE101 2000
0xE101 2800
0xE101 7000
McBSP1 Registers
MCSI2 Registers
MCSI1 Registers
McBSP3 Registers
16
16
16
16
Table 3−6. MPU Configuration Registers
ACCESS
WIDTH
MPU BASE ADDRESS
REGISTER SET
0xFFFB C800
0xFFFE 0800
0xFFFE 1000
0xFFFE 1800
0xFFFE C100
0xFFFE C200
0xFFFE C900
0xFFFE CA00
0xFFFE CC00
0xFFFE CE00
0xFFFE CF00
0xFFFE D200
0xFFFE D300
0xFFFE D400
MPU UART TIPB Bus Switch Registers
Ultra Low-Power Device (ULPD) Registers
OMAP5910 Configuration Registers
Device Die Identification Registers
Local Bus Control Registers
16
16
32
32
32
32
32
32
32
32
32
32
16
32
Local Bus MMU Registers
MPU Interface (MPUI) Registers
TIPB (Private) Bridge 1 Config Registers
Traffic Controller Registers
MPU Clock/Reset/Power Control Registers
DPLL1 Configuration Registers
DSP MMU Registers
TIPB (Public) Bridge 2 Config Registers
JTAG Identification Registers
3.3 DSP Memory Maps
The DSP supports a unified program/data memory map (program and data accesses are made to the same
physical space), however peripheral registers are located in a separate I/O space which is accessed via the
DSP’s port instructions.
3.3.1 DSP Global Memory Map
The DSP Subsystem contains 160K bytes of on-chip SRAM (64K bytes of DARAM and 96K bytes of SARAM).
The MPU also has access to these memories via the MPUI (MPU Interface) port. The DSP also has access
to the shared system SRAM (192K bytes) and both EMIF spaces (EMIFF and EMIFS) via the DSP Memory
Management Unit (MMU) which is configured by the MPU.
Table 3−7 shows the high-level program/data memory map for the DSP subsystem. DSP data accesses
utilize 16-bit word addresses while DSP program fetches utilize byte addressing.
Table 3−7. DSP Global Memory Map
†
EXTERNAL MEMORY
BYTE ADDRESS RANGE
WORD ADDRESS RANGE
INTERNAL MEMORY
DARAM
64K bytes
0x00 0000 − 0x00 FFFF
0x00 0000 − 0x00 7FFF
SARAM
96K bytes
0x01 0000 − 0x02 7FFF
0x00 8000 − 0x01 3FFF
0x02 8000 − 0x04 FFFF
0x05 0000 − 0xFF 7FFF
0x01 4000 − 0x02 7FFF
0x02 8000 − 0x7F BFFF
Reserved
Managed by DSP MMU
PDROM
(MPNMC = 0)
Managed by DSP MMU
(MPNMC =1)
0xFF 8000 − 0xFF FFFF
0x7F C000 − 0x7F FFFF
†
This space could be external memory or internal shared system memory depending on the DSP MMU configuration.
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Functional Overview
3.3.2 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h−00FFFFh and is composed of eight blocks of
8K bytes each (see Table 3−8). Each DARAM block can perform two accesses per cycle (two reads, two
writes, or a read and a write).
Table 3−8. DARAM Blocks
BYTE ADDRESS RANGE
0x00 0000 − 0x00 1FFF
0x00 2000 − 0x00 3FFF
0x00 4000 − 0x00 5FFF
0x00 6000 − 0x00 7FFF
0x00 8000 − 0x00 9FFF
0x00 A000 − 0x00 BFFF
0x00 C000 − 0x00 DFFF
0x00 E000 − 0x00 FFFF
WORD ADDRESS RANGE
0x00 0000 − 0x00 0FFF
0x00 1000 − 0x001FFF
0x00 2000 − 0x00 2FFF
0x00 3000 − 0x00 3FFF
0x00 4000 − 0x00 4FFF
0x00 5000 − 0x00 5FFF
0x00 6000 − 0x00 6FFF
0x00 7000 − 0x00 7FFF
MEMORY BLOCK
DARAM 0
DARAM 1
DARAM 2
DARAM 3
DARAM 4
DARAM 5
DARAM 6
DARAM 7
3.3.3 On-Chip Single-Access RAM (SARAM)
The SARAM is located at the byte address range 010000h−03FFFFh and is composed of 12 blocks of 8K bytes
each (see Table 3−9). Each SARAM block can perform one access per cycle (one read or one write).
Table 3−9. SARAM Blocks
BYTE ADDRESS RANGE
0x01 0000 − 0x01 1FFF
0x01 2000 − 0x01 3FFF
0x01 4000 − 0x01 5FFF
0x01 6000 − 0x01 7FFF
0x01 8000 − 0x01 9FFF
0x01 A000 − 0x01 BFFF
0x01 C000 − 0x01 DFFF
0x01 E000 − 0x01 FFFF
0x02 0000 − 0x02 1FFF
0x02 2000 − 0x02 3FFF
0x02 4000 − 0x02 5FFF
0x02 6000 − 0x02 7FFF
WORD ADDRESS RANGE
0x00 8000 − 0x00 8FFF
0x00 9000 − 0x00 9FFF
0x00 A000 − 0x00 AFFF
0x00 B000 − 0x00 BFFF
0x00 C000 − 0x00 CFFF
0x00 D000 − 0x00 DFFF
0x00 E000 − 0x00 EFFF
0x00 F000 − 0x00 FFFF
0x01 0000 − 0x01 0FFF
0x01 1000 − 0x01 1FFF
0x01 2000 − 0x01 2FFF
0x01 3000 − 0x01 3FFF
MEMORY BLOCK
SARAM 0
SARAM 1
SARAM 2
SARAM 3
SARAM 4
SARAM 5
SARAM 6
SARAM 7
SARAM 8
SARAM 9
SARAM 10
SARAM 11
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Functional Overview
3.3.4 DSP I/O Space Memory Map
The DSP I/O space is a separate address space from the data/program memory space. The I/O space is
accessed via the DSP’s port instructions. The Public and Shared peripheral registers are also accessible by
the MPU through the MPUI (MPU Interface) port. The DSP I/O space is accessed using 16-bit word
addresses. The following tables specify the DSP base addresses where each set of registers is accessed.
All accesses to these registers must utilize the appropriate access width as indicated in the tables. Accessing
registers with the incorrect access width may cause unexpected results including a TI Peripheral Bus (TIPB)
bus error and associated TIPB interrupt.
Refer to Sections 3.16 and 3.17 for more detail about each of these register sets including individual register
addresses, register names, descriptions, supported access types (read, write or read/write) and reset values.
Table 3−10. DSP Private Peripheral Registers
DSP BASE ADDRESS
0x00 0C00
REGISTER SET
DSP DMA Controller Registers
DSP Timer1 Registers
ACCESS WIDTH
16
16
16
16
16
16
16
0x00 2800
0x00 2C00
DSP Timer2 Registers
0x00 3000
DSP Timer3 Registers
0x00 3400
DSP Watchdog Timer Registers
DSP Interrupt Interface Registers
Level2 Interrupt Handler Registers
0x00 3800
0x00 4800
Table 3−11. DSP Public Peripheral Registers
DSP BASE ADDRESS
REGISTER SET
McBSP1 Registers
MCSI2 Registers
MCSI1 Registers
McBSP3 Registers
ACCESS WIDTH
0x00 8C00
0x00 9000
0x00 9400
0x00 B800
16
16
16
16
Table 3−12. DSP/MPU Shared Peripheral Registers
DSP BASE ADDRESS
0x00 8000
REGISTER SET
UART1 Registers
ACCESS WIDTH
8
8
0x00 8400
UART2 Registers
0x00 CC00
UART3 Registers
8
0x00 F000
GPIO Interface Registers
Mailbox Registers
16
16
0x00 F800
Table 3−13. DSP Configuration Registers
REGISTER SET
DSP BASE ADDRESS
0x00 0000
ACCESS WIDTH
DSP TIPB Bridge Config Registers
DSP EMIF Config Registers
16
16
16
16
16
0x00 0800
0x00 1400
DSP I-Cache Registers
0x00 4000
DSP Clock Mode Registers
0x00 E400
DSP UART TIPB Bus Switch Registers
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Functional Overview
3.4 DSP External Memory (Managed by MMU)
When the DSP MMU is off, the 24 address lines are directly copied to the traffic controller without any
modification. There is no virtual-to-physical address translation. All the addresses between 0x05 0000 and
0x00FF F800 (0x00FF FFFF if DSP bit MP/MC = 1) are redirected to the first sector of flash (CS0) in the shared
memory space (shared by MPU and DSP).
Byte
Byte
Address
Shared Memory
Address
DSP Memory
Internal RAM
0x0000 0000
0x00 0000
0x05 0000
EMIFS
(FLASH CS0)
0x01FF FFFF
Reserved
0x0400 0000
0x05FF FFFF
EMIFS
(FLASH CS1)
Reserved
0x0800 0000
0x09FF FFFF
EMIFS
(FLASH CS2)
0xFF 8000
0xFF FFFF
Reserved
ROM
0x0C00 0000
0x0DFF FFFF
EMIFS
(FLASH CS3)
Reserved
0x1000 0000
0x13FF FFFF
EMIFF
(SDRAM)
Reserved
0x2000 0000
0x2002 FFFF
IMIF
(Internal SRAM)
Figure 3−2. DSP MMU Off
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Functional Overview
When the DSP MMU is on, the 24 address lines (virtual address) are relocated within a physical 32-bit address
by the DSP MMU. The DSP MMU is controlled by the MPU.
Byte
Address
Byte
Shared Memory
Address
DSP Memory
Internal RAM
0x0000 0000
0x00 0000
EMIFS
(FLASH CS0)
0x01FF FFFF
0x05 0000
Reserved
0x0400 0000
0x05FF FFFF
EMIFS
(FLASH CS1)
Reserved
0x0800 0000
0x09FF FFFF
EMIFS
(FLASH CS2)
FLASH CS0
0xFF 8000
0xFF FFFF
Reserved
ROM
0x0C00 0000
0x0DFF FFFF
EMIFS
(FLASH CS3)
Reserved
0x1000 0000
0x13FF FFFF
EMIFF
(SDRAM)
Reserved
0x2000 0000
0x2002 FFFF
IMIF
(Internal SRAM)
Figure 3−3. DSP MMU On
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Functional Overview
3.5 MPU and DSP Private Peripherals
The MPU and DSP each have their own separate private peripheral bus. Peripherals on each of these private
buses may only be accessed by their respective processors. For instance, the DSP timers on the DSP private
peripheral bus are not accessible by the MPU or the System DMA controller.
3.5.1 Timers
The MPU and DSP each have their own three 32-bit timers available on their respective private TI Peripheral
Bus (TIPB). These timers are used by the operating systems to provide general-purpose housekeeping
functions, or in the case of the DSP, to also provide synchronization of real-time processing functions. These
timers may be configured either in auto-reload or one-shot mode with on-the-fly read capability. The timers
generate an interrupt to the respective processor (MPU or DSP) when the timer’s down-counter is equal to
zero.
3.5.2 32k Timer (MPU only)
The MPU has one 32k Timer that runs on the 32-kHz clock as opposed to the MPU subsystem domain clock.
The MPU subsystem operating system (OS) requires interrupts at regular time intervals for OS scheduling
purpose (typically 1 ms to 30 ms). These time intervals can be generated using the MPU’s three 32-bit
general-purpose timers. However, these timers cannot be used in sleep modes when the system clock is not
operating. Therefore, a 32-kHz clock-based timer is needed to provide the required OS timing interval.
3.5.3 Watchdog Timer
The MPU and DSP each have a single Watchdog Timer. Each watchdog timer can be configured as either
a watchdog timer or a general-purpose timer.
A watchdog timer requires that the MPU or DSP software or OS periodically write to the appropriate WDT count
register before the counter underflows. If the counter underflows, the WDT generates a reset to the
appropriate processor (MPU or DSP). The DSP WDT resets only the DSP processor while the MPU WDT
resets both processors (MPU and DSP). The watchdog timers are useful for detecting user programs that are
stuck in an infinite loop, resulting in loss of program control or in a runaway condition.
When used as a general-purpose timer, the WDT is a 16-bit timer configurable either in autoreload or one-shot
mode with on-the-fly read capability. The timer generates an interrupt to the respective processor (MPU or
DSP) when the timer’s down-counter is equal to zero.
3.5.4 Interrupt Handlers
The MPU and DSP each have two levels of interrupt handling, allowing up to 39 interrupts to the DSP and
63 interrupts to the MPU.
3.5.5 LCD Controller
The OMAP5910 device includes an LCD Controller that interfaces with most industry-standard LCDs. The
LCD Controller is configured by the MPU and utilizes a dedicated channel on the System DMA to transfer data
from the frame buffer. The frame buffer can be implemented using the internal shared SRAM (192K bytes)
or optionally using external SDRAM via the EMIFF. Using the frame buffer as its data source, the System DMA
must provide data to the FIFO at the front end of the LCD controller data path at a rate sufficient to support
the chosen display mode and resolution. Optimal performance is achieved when using the internal SRAM as
the frame buffer.
The panel size is programmable, and can be any width (line length) from 16 to 1024 pixels in 16-pixel
increments. The number of lines is set by programming the total number of pixels in the LCD. The total frame
size is programmable up to 1024 x 1024. However, frame sizes and frame rates supported in specific
applications will depend upon the available memory bandwidth allowed by the specific application as well as
the maximum configurable pixel clock rate.
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Functional Overview
The screen is intended to be mapped to the frame buffer as one contiguous block where each horizontal line
of pixels is mapped to a set of consecutive bytes of words in the frame memory.
The principle features of the LCD controller are:
•
•
•
•
•
•
•
•
Dedicated 64-entry x 16-bit FIFO
Dedicated LCD DMA channel for LCD
Programmable display including support for 2-, 4-, 8-, 12-, and 16-bit graphics modes
Programmable display resolutions up to 1024 pixels by 1024 lines (assuming sufficient system bandwidth)
Support for passive monochrome (STN) displays
Support for passive color (STN) displays
Support for active color (TFT) displays
Patented dithering algorithm, providing:
−
−
−
−
15 grayscale levels for monochrome passive displays
3375 colors for color passive displays
65536 colors for active color displays
256-entry x 12-bit palette
•
•
•
•
•
•
Programmable pixel rate
Pixel clock plus horizontal and vertical synchronization signals
ac-bias drive signal
Active display enable signal
256-entry x 12-bit palette
Dual-frame buffers
3.6 MPU Public Peripherals
Peripherals on the MPU Public Peripheral bus may only be accessed by the MPU and the System DMA
Controller, which is configured by the MPU. This bus is called a public bus because it is accessible by the
System DMA controller. The DSP cannot access peripherals on this bus.
3.6.1 USB Host Controller
The OMAP5910 USB host controller communicates with USB devices at the USB low-speed (1.5M-bit/s
maximum) and full-speed (12M-bit/s maximum) data rates. The controller is USB compliant. For additional
information, see the Universal Serial Bus Specification, Revision 2.0 and the OpenHCI – Open Host Controller
Interface Specification for USB, Release 1.0a, hereafter called the OHCI Specification for USB.
The OMAP5910 USB host controller implements the register set and makes use of the memory data structures
which are defined in the OHCI Specification for USB. These registers and data structures are the mechanism
by which a USB host controller driver software package may control the OMAP5910 USB host controller.
The USB host controller is connected to the MPU public peripheral bus for MPU access to registers. The USB
host controller gains access to the data structures in system memory via the internal Local Bus interface. The
OMAP5910 device implements a variety of signal multiplexing options that allows use of the USB host
controller with any of the three available USB interfaces on the device. One of these interfaces utilizes an
integrated USB transceiver, while the other two require external transceivers. The host controller can support
up to three downstream ports.
The OMAP5910 USB host controller implementation does not implement every aspect of the functionality
defined in the OHCI Specification for USB. The differences focus on power switching, overcurrent reporting,
and the OHCI ownership change interrupt. Other restrictions are imposed by OMAP5910 system memory
addressing mechanisms and the effects of the OMAP5910 pin-multiplexing options.
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Functional Overview
3.6.2 USB Function Peripheral
The USB Function peripheral provides a full-speed Function interface between the MPU and the USB wire.
The module handles USB transactions with minimal MPU intervention and is fully compliant to USB standard.
The USB Function module supports one control endpoint (EP0), up to 15 IN endpoints, and up to 15 OUT
endpoints. The exact endpoint configuration is software-programmable. The specific items of a configuration
for each endpoint are: the size in bytes, the direction (IN, OUT), the type (bulk/interrupt or isochronous), and
the associated endpoint number. The USB Function module also supports the use of three System DMA
channels for IN endpoints and three System DMA channels for OUT endpoints for either bulk/interrupt or
isochronous transactions.
The OMAP5910 device implements a variety of signal-multiplexing options that allow use of the USB Function
peripheral with any one of the three available USB interfaces on the device. One of these interfaces utilizes
an integrated USB transceiver, while the other two require external transceivers. The USB Function can only
utilize one of these ports at a time. The other ports may be used simultaneously by the USB Host controller
peripheral.
3.6.3 Multichannel Buffered Serial Port (McBSP)
The Multichannel Buffered Serial Port (McBSP) provides a high-speed, full-duplex serial port that allow direct
interface to audio codecs, and various other system devices. The MPU public peripheral bus has access to
one McBSP, which is McBSP2.
The McBSP provides:
•
•
•
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSP has the following capabilities:
•
Direct interface to:
−
−
−
−
−
−
T1/E1 framers
MVIP switching-compatible and ST-BUS compliant devices
IOM-2 compliant device
AC97-compliant device
I2S-compliant device
Serial peripheral interface (SPI)
•
•
•
•
•
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
NOTE: All of the standard McBSP pins are not necessarily available on every McBSP on the
OMAP5910 device.
In the case of the MPU’s McBSP2, the following pins are available:
•
•
•
CLKX and CLKR (transmit and receive clocks)
FSX and FSR (transmit and receive frame syncs)
DX and RX (transmit and receive data)
The functional clock to the McBSP2 peripheral is configurable to the DPLL clock rate with a divider of 1, 2,
4, or 8.
McBSP2 does not have a CLKS external clock reference pin. Therefore, if the McBSP2 Sample Rate
Generator (SRG) is used, the only reference clock available to the Sample Rate Generator is a programmable
clock from the MPU domain.
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Functional Overview
2
3.6.4 I C Master/Slave Interface
2
2
2
The I C Master/Slave Interface is compliant to Philips I C-Bus Specification Version 2.1 master bus. The I C
controller supports the multimaster mode, which allows more than one device capable of controlling the bus
2
to be connected to it. Including the OMAP5910 device, each I C device is recognized by a unique address
and can operate as either transmitter or receiver, depending on the function of the device. In addition to being
2
a transmitter or receiver, a device connected to the I C bus can also be considered as master or slave when
performing data transfers.
2
The I C Interface supports the following features:
2
•
•
•
•
•
•
•
•
•
•
•
•
Compliant to Philips I C-Bus Specification Version 2.1
Support standard mode (up to 100K bits/s) and Fast mode (up to 400K bits/s)
7-bit and 10-bit device addressing modes
General call
Start/Restart/Stop
Multimaster transmitter/slave receiver mode
Multimaster receiver/slave transmitter mode
Combined master transmit/receive and receive/transmit mode
Built-in FIFO for buffered read or write
Module enable/disable capability
Programmable clock generation
Supports use of two DMA channels
2
The I C Interface does not support the following features:
•
•
High-speed (HS) mode for transfer rates up to 3.4M bits
C-bus compatibility mode
3.6.5 Microwire Serial Interface
The Microwire interface is a serial synchronous interface that can drive up to four serial external components.
The interface is compatible with the Microwire standard and is seen as the master.
Microwire is typically used to transmit control and status information to external peripheral devices or to
transmit data to or from small nonvolatile memories such as serial EEPROMs or serial Flash devices.
3.6.6 Multimedia Card/Secure Digital (MMC/SD) Interface
The MMC/SD Interface controller provides an interface to MMC or SD memory cards plus up to three serial
SPI flash cards or other SPI devices. The controller handles MMC/SD or SPI transactions with minimal MPU
intervention, allowing optional use of two system DMA channels for transfer of data.
The following combination of external devices is supported:
•
One or more MMC memory cards sharing the same bus plus up to three devices with 8-bit SPI protocol
interface (serial flash memories, etc.).
•
One single SD memory card plus up to three devices with 8-bit SPI protocol interface.
NOTE: Other combinations such as two SD cards or one MMC card with one SD card are not supported.
The MPU software must manage transaction semantics, while the MMC/SD controller deals with MMC/SD
protocol at the transmission level: packing data, adding the CRC, generating the start/end bit and checking
for syntactical correctness. SD mode wide bus width is also supported.
When interfacing with 8-bit SPI devices, the MMC/SD module does not perform any MMC specific function,
rather it provides a generic SPI interface. Several additional interface pins are utilized to provide the SPI clock
and SPI chip selects.
2
I C Bus is a trademark of Philips Electronics N.V.
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Functional Overview
3.6.7 HDQ/1-Wire Interface
This module allows implementation of both HDQ and the 1-Wire protocols. These protocols use a single wire
to communicate between a master and a slave. The HDQ/1-Wire pin is open-drain and requires an external
pullup resistor.
HDQ and 1-Wire interfaces can be found on commercially available battery management and power
management devices. The interface can be used to send command and status information between
OMAP5910 and such a battery or power management device.
3.6.8 Camera Interface
The camera interface is an 8-bit external port which may be used to accept data from an external camera
sensor. The interface handles multiple image formats synchronized on vertical and horizontal synchronization
signals. Data transfer to the camera interface may be done synchronously or asynchronously.
The camera interface module converts the 8-bit data transfers into 32-bit words and utilizes a 128-word buffer
to facilitate efficient data transfer to memory. Data may be transferred from the camera interface buffer to
internal memory by the system DMA controller or directly by the MPU. The interface may utilize an externally
driven clock at rates up to 13 MHz or may optionally provide an output reference clock at rates of 8 MHz,
9.6 MHz, or 24 MHz when the camera interface is configured for clocking from the internal 48 MHz. When the
camera interface is configured to obtain clocking from the base oscillator frequency (12 MHz or 13 MHz), the
camera interface clock is configurable to operate at the base frequency or one half the base frequency (6 MHz
or 6.5 MHz).
3.6.9 MPUIO/Keyboard Interface
The MPUIO pins may be used as either general-purpose I/O for the MPU or as a Keyboard Interface to a 6 x 5
or 8 x 8 keypad array. If a 6 x 5 keypad array is implemented, the unused MPUIO pins may be used as GPIO.
When used as GPIO, each pin may be configured individually as either an output or an input, and they may
be individually configured to generate MPU interrupts based on a level change (falling or rising) after a
debouncing process. These MPUIO interrupts may be used to wake up the device from deep-sleep mode
using the 32-kHz clock.
The MPUIO pins may also be used as a keyboard interface. The keyboard interface provides the following
pins:
•
•
KB.R[7:0] input pins for row lines
KB.C[7:0] output pins for column lines
To allow key-press detection, all input pins (KB.Rx) are pulled up to DV
and all output pins (KB.Cx) are driven
DD
low level. The KB.R[7:0] and KB.C[7:0] pins should be connected to an external keyboard matrix such that
when a key on the matrix is pressed, the corresponding row and column lines are shorted together. Any action
on a key generates an interrupt to the MPU, which then scans the column lines in a particular sequence to
determine which key or keys have been pressed.
3.6.10 Pulse-Width Light (PWL)
The Pulse-Width Light (PWL) module provides control of the LCD or keypad backlighting by employing a
random sequence generator. This voltage-level control technique decreases the spectral power at the
modulator harmonic frequencies. The module uses a switchable 32-kHz clock.
3.6.11 Pulse-Width Tone (PWT)
The Pulse-Width Tone (PWT) module generates a modulated frequency signal for use with an external buzzer.
The frequency is programmable between 349 Hz and 5276 Hz with 12 half-tone frequencies per octave. The
volume level of the output is also programmable.
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Functional Overview
3.6.12 LED Pulse Generator
There are two separate LED Pulse Generator (LPG) modules. Each LPG module provides an output for an
indication LED. The blinking period is programmable between 152 ms and 4 s or the LED can be switched
on or off permanently.
3.6.13 Real-Time Clock
The Real-Time Clock (RTC) module provides an embedded RTC for use in applications which need to track
real time. This peripheral is not an ultra-low-power module—meaning that the RTC module cannot be powered
independently without powering the OMAP5910 MPU core. Therefore, if an ultra-low-power RTC is desired
for a system application, an external RTC should be used.
The RTC module has the following features:
•
•
•
•
•
Time information (seconds/minutes/hours) directly in BCD code
Calendar information (day/month/year/day of the week) directly in BCD code up to year 2099
Interrupts generation, periodically (1s/1m/1h/1d period) or at a precise time of the day (alarm function)
30-s time correction
Oscillator frequency calibration
3.6.14 Frame Adjustment Counter
The frame adjustment counter (FAC) is a simple peripheral that counts the number of rising edges of one signal
(start of frame interrupt of the USB Function) during a programmable number of rising edges of a second signal
(transmit frame synchronization of McBSP2). The FAC may only be used with these specific USB Function
and McBSP2 signals. The count value can be used by system-level software to adjust the duration of the two
time domains with respect to each other to reduce overflow and underflow. If the data being transferred is audio
data, this module can be part of a solution that reduces pops and clicks. The FAC module generates one
second-level interrupt to the MPU.
3.7 DSP Public Peripherals
Peripherals on the DSP Public Peripheral bus are directly accessible by the DSP and DSP DMA. These
peripherals may also be accessed by the MPU and System DMA Controller via the MPUI interface. The MPUI
interface must be properly configured to allow this access.
3.7.1 Multichannel Buffered Serial Port (McBSP)
The Multichannel Buffered Serial Port (McBSP) provides a high-speed, full-duplex serial port that allow direct
interface to audio codecs and various other system devices. Refer to Section 3.6.3 for a list of features
provided by the McBSP. The DSP public peripheral bus has access to two McBSPs: McBSP1 and McBSP3.
NOTE: All of the standard McBSP pins are not necessarily available on every McBSP on the OMAP5910
device. In the case of the two DSP McBSPs, the following pins are available:
•
McBSP1 pins:
−
−
−
−
CLKX (transmit clock)
FSX (transmit frame sync)
DX and DR (transmit and receive data)
CLKS (external reference to Sample Rate Generator)
•
McBSP3 pins:
−
−
−
CLKX (transmit clock)
FSX (transmit frame sync)
DX and DR (transmit and receive data)
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Functional Overview
Because McBSP1 and McBSP3 do not have the CLKR and FSR pins available, the transmit clock and frame
sync pins (CLKX and FSX) must be used for bit clock and frame synchronization on both the transmit and
receive channels of these McBSPs.
The functional clock to McBSP1 and McBSP3 is fixed at the OMAP5910 base operating frequency (12 MHz
or 13 MHz). The bit-clock rate for these McBSPs is therefore limited to 6 or 6.5 MHz (one half the base
frequency).
Only McBSP1 has the CLKS pin available. If the sample rate generator (SRG) is used on McBSP1, the
reference clock to the SRG can be configured to be either an external reference provided on the CLKS pin,
or the internal base (12- or 13-MHz) device clock. However, if the SRG is used on McBSP3, the only reference
clock available to this SRG is the base device clock as clock reference.
3.7.2 Multichannel Serial Interface (MCSI)
The multichannel serial interface (MCSI) provides flexible serial interface with multichannel transmission
capability. The MCSI allows the DSP to access a variety of external devices, such as audio codecs and other
types of analog converters. The DSP public peripheral bus has access to two MCSIs: MCSI1 and MCSI2.
These MCSIs provide full-duplex transmission and master or slave clock control. All transmission parameters
are configurable to cover the maximum number of operating conditions. The MCSIs have the following
features:
•
•
Master or slave clock control (transmission clock and frame synchronization pulse)
Programmable transmission clock frequency (master mode) up to one half the OMAP5910 base
frequency (12 or 13 MHz)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Reception clock frequency (slave mode) of up to the base frequency (12 or 13 MHz)
Single-channel or multichannel (x16) frame structure
Programmable word length: 3 to 16 bits
Full-duplex transmission
Programmable frame configuration
Continuous or burst transmission
Normal or alternate framing
Normal or inverted frame and clock polarities
Short or long frame pulse
Programmable oversize frame length
Programmable frame length
Programmable interrupt occurrence time (TX and RX)
Error detection with interrupt generation on wrong frame length
System DMA support for both TX and RX data transfers
3.8 Shared Peripherals
The shared peripherals are connected to both the MPU Public Peripheral bus and the DSP Public Peripheral
bus. In the case of the UARTs, these connections are achieved via a TI Peripheral Bus Switch, which must
be configured to allow MPU or DSP access to the UARTs. The other shared peripherals have permanent
connections to both public peripheral buses, although read and write accesses to each peripheral register may
differ.
3.8.1 Universal Asynchronous Receiver/Transmitter (UART)
The OMAP5910 device has three Universal Asynchronous Receiver/Transmitter (UART) peripherals which
are accessible on the DSP public and MPU public peripheral buses. A TI peripheral bus switch configured by
the MPU allows either TIPB access to these UART peripherals. All three UARTs are standard
16C750-compatible UARTs implementing an asynchronous transfer protocol with various flow control options.
Two of the three UARTs (UART1 and UART2) have autobaud capability to automatically determine and adjust
to the baud rate of the external connected device. One of the UARTs (UART3) can function as a general UART
or can optionally function as an IrDA interface.
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Functional Overview
The main features of the UART peripherals include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Selectable UART/autobaud modes (autobauding on UART1 and UART2)
Dual 64-entry FIFOs for received and transmitted data payload
Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation
Programmable sleep mode
Complete status-reporting capabilities in both normal and sleep mode
Frequency prescaler values from 0 to 65535 to generate the appropriate baud rates
Interrupt request generated if multiple System DMA requests
Baud rate from 300 bits/s up to 1.5M bits/s
Autobauding between 1200 bits/s and 115.2K bits/s
Software/hardware flow control
Programmable XON/XOFF characters
Programmable auto-RTS and auto-CTS
Programmable serial interface characteristics
−
−
−
−
−
−
−
−
5-, 6-, 7-, or 8-bit characters
Even-, odd-, or no-parity bit generation and detection
1, 1.5, or 2 stop-bit generation
False start bit detection
Line break generation and detection
Fully prioritized interrupt system controls
Internal test and loopback capabilities
Modem control functions (CTS, RTS, DSR, DTR)
NOTE: DSR and DTR are only available on UART1 and UART3.
The IrDA functions available on UART3 are as follows:
•
•
•
Slow infrared (SIR) operations
Framing error, cyclic redundancy check (CRC) error, abort pattern (SIR) detection
8-entry status FIFO (with selectable trigger levels) available to monitor frame length and frame errors
3.8.2 General-Purpose I/O (GPIO)
There are up to 14 shared GPIO pins on the OMAP5910 device which may be accessed and controlled by
either the DSP public peripheral bus or the MPU public peripheral bus. Each GPIO pin is independently
configurable to be used by either the DSP or MPU. The MPU controls which processor owns each GPIO pin
by configuring a pin control register that only the MPU can access.
Each GPIO pin can be used as either an input or output pin with GPIO inputs being synchronized internally
to a peripheral clock. GPIO inputs may also optionally be configured to generate an interrupt condition to the
processor which owns the GPIO pin. The sense of the interrupt condition is configurable such that either a
high-to-low or low-to-high transition causes the interrupt condition.
Some of the GPIO pins are multiplexed with other interface pins specific to other device peripherals. Refer
to Table 2−3 to decide which GPIO pins are multiplexed with other peripheral signals.
3.8.3 Mailbox Registers
Four sets of shared mailbox registers are available for communication between the DSP and MPU. These
registers are discussed further in Section 3.12, Interprocessor Communication.
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Functional Overview
3.9 System DMA Controller
The System Direct Memory Access (DMA) controller transfers data between points in the memory space
without intervention by the MPU. The System DMA allows movements of data to and from internal memory,
external memory, and peripherals to occur in the background of MPU operation. It is designed to off-load the
block data transfer function from the MPU processor. The System DMA is configured by the MPU via the MPU
private peripheral bus.
The System DMA controller has nine independent general-purpose channels and seven ports that it may
transfer to/from. An additional tenth channel is dedicated for use with the LCD controller. Of the seven
available ports, the DMA transfers may occur between any two ports with the exception of the LCD port, which
may only be used as a destination with the EMIFF or IMIF as the source. For maximum transfer efficiency,
all nine channels are independent. This means that if multiple channels are exclusively accessing different
ports, then simultaneous transfers performed by the channels will occur uninhibited. If the multiple channels
are accessing common ports, however, some arbitration cycles will be necessary. Arbitration occurs in a
round-robin fashion with configurable priority for each channel (high or low).
The basic functional features of the system DMA controller are as follows:
•
•
•
•
•
•
•
•
•
•
•
Nine general-purpose and one dedicated (LCD) DMA channels
Round-robin arbitration scheme with programmable priorities
Concurrent DMA transfer capability
Start of transfer on peripheral request or host request
Byte-alignment and Byte-packing/unpacking capability
Burst transfer capability (IMIF, EMIFF, EMIFS, LCD, and Local ports)
Time-out counter for each DMA channel to prevent a channel locking on a memory location or peripheral.
Constant, post-incrementing, and Single- or Double-Indexed addressing modes
Autoinitialization for multiple block transfers without MPU intervention
Access available to all of the memory range (physical memory mapping and TIPB space)
Seven ports are available for different kinds of hardware resources.
−
−
−
−
−
−
−
EMIFS port (allowing access to external asynchronous memory or devices)
EMIFF port (allowing access to external SDRAM)
IMIF port (allowing access to 192K bytes of shared SRAM)
MPUI port (allowing access to DSP memory and peripherals)
TIPB port (allowing peripheral register access)
Local port (used for Host USB only)
LCD port (allowing transfers to the LCD controller)
•
Memory-to-memory transfer granularity of 8, 16, and 32 bits.
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Functional Overview
3.10 DSP DMA Controller
The DSP subsystem has its own dedicated DMA Controller, which is entirely independent of the MPU or the
System DMA Controller. The DSP DMA Controller has many of the same major features that the System DMA
Controller possesses (see Section 3.9).
The DSP DMA Controller has six generic channels and five physical ports available for source or destination
data. These five ports are the SARAM port, DARAM port, EMIF (External memory port), DSP TIPB port, and
MPUI port. The DSP may configure the DSP DMA Controller to transfer data between the SARAM, DARAM,
EMIF, and TIPB ports, but the MPUI port is a dedicated port used for MPU or System DMA initiated transfers
to DSP subsystem resources. The SARAM and DARAM ports are used to access local DSP memories and
the TIPB port is used to access the registers of the DSP peripherals. The EMIF port of the DSP DMA controller
is used to access the Traffic Controller via the DSP MMU (Memory Management Unit).
3.11 Traffic Controller (Memory Interfaces)
The Traffic Controller (TC) manages all accesses by the MPU, DSP, System DMA, and Local Bus to the
OMAP5910 system memory resources. The TC provides access to three different memory interfaces:
External Memory Interface Slow (EMIFS), External Memory Interface Fast (EMIFF), and Internal Memory
Interface (IMIF). The IMIF allows access to the 192K bytes of on-chip SRAM.
The EMIFS Interface provides 16-bit-wide access to asynchronous or synchronous memories or devices,
including the following:
•
•
•
•
•
•
•
Intel fast boot block flash (23FxxxF3)
AMD simultaneous read/write boot sector flash (AM29DLxxxG)
AMD burst-mode flash (AM29BLxxxC)
Intel StrataFlash memory (28FxxxJ3A)
Intel synchronous StrataFlash memory (28FxxxK3/K18)
Intel wireless flash memory (28FxxxW18)
Asynchronous SRAM
The EMIFF Interface provides access to 16-bit-wide access to standard SDRAM memories and the IMIF
provides access to the 192K bytes of on-chip SRAM.
The TC provides the functions of arbitrating contending accesses to the same memory interface from different
initiators (MPU, DSP, System DMA, Local Bus), synchronization of accesses due to the initiators and the
memory interfaces running at different clock rates, and the buffering of data allowing burst access for more
efficient multiplexing of transfers from multiple initiators to the memory interfaces.
The TC’s architecture allows simultaneous transfers between initiators and different memory interfaces
without penalty. For instance, if the MPU is accessing the EMIFF at the same time, the DSP is accessing the
IMIF, transfers may occur simultaneously since there is no contention for resources. There are three separate
ports to the TC from the System DMA (one for each of the memory interfaces), allowing for greater bandwidth
capability between the System DMA and the TC.
Intel and Intel StrataFlash are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
AMD is a trademark of Advanced Micro Devices, Inc.
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Functional Overview
3.12 Interprocessor Communication
Several mechanisms allow for communication between the MPU and the DSP on the OMAP5910 device.
These include mailbox registers, MPU Interface, and shared memory space.
3.12.1 MPU/DSP Mailbox Registers
The MPU and DSP processors may communicate with each other via a mailbox-interrupt mechanism. This
mechanism provides a very flexible software protocol between the processors. There are four sets of mailbox
registers located in public TIPB space. The registers are shared between the two processors, so the MPU and
DSP may both access these registers within their own public TIPB space, but read/write accessibility of each
register is different for each processor.
There are four sets of mailbox registers: two for the MPU to send messages and issue an interrupt to the DSP,
the other two for the DSP to send messages and issue an interrupt to the MPU. Each set of mailbox registers
consists of two 16-bit registers and a 1-bit flag register. The interrupting processor can use one 16-bit register
to pass a data word to the interrupted processor and the other 16-bit register to pass a command word.
Communication is achieved when one processor writes to the appropriate command word register which
causes an interrupt to the other processor and sets the appropriate flag register. The interrupted processor
acknowledges by reading the command word which causes the flag register to be cleared. An additional
data-word register is also available in each mailbox register set to optionally communicate two words of data
between the processors for each interrupt instead of just communicating the command word.
The information communicated by the command and data words are entirely user-defined. The data word may
be optionally used to indicate an address pointer or status word.
3.12.2 MPU Interface (MPUI)
The MPU interface (MPUI) allows the MPU and the system DMA controller to communicate with the DSP and
its peripherals. The MPUI allows access to the full memory space (16M bytes) of the DSP and the DSP public
peripheral bus. Thus, the MPU and System DMA Controller both have read and write access to the complete
DSP I/O space (128K bytes), including the control registers of the DSP public peripherals.
The MPUI port supports the following features:
•
Four access modes:
−
Shared-access mode (SAM) for MPU access of DSP SARAM, DARAM, and external memory
interface
−
−
−
Shared-access mode (SAM) for peripheral bus access
Host-only mode (HOM) for SARAM access
Host-only mode (HOM) for peripheral bus access
•
•
•
•
•
•
•
Interrupt to MPU if access time-out occurs
Programmable priority scheme (MPU vs. DMA)
Packing and unpacking of data (16 bits to 32 bits, and vice versa)
32-bit single access support
Software control endianism conversion
System DMA capability to full DSP memory space (16M bytes)
System DMA capability to the DSP public TIPB peripherals (up to 128K bytes space)
This port can be used for many functions, such as: MPU loading of program code into DSP program memory
space, sharing of data between MPU and DSP, implementing interprocessing communication protocols via
shared memory, or allowing MPU to use and control DSP Public TIPB Peripherals.
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Functional Overview
3.12.3 MPU/DSP Shared Memory
The OMAP5910 device implements a shared memory architecture via the Traffic Controller. Therefore, the
MPU and DSP both have access to the same shared SRAM memory (192K bytes) as well as to the EMIFF
and EMIFS memory space. Through the DSP Memory Management Unit (MMU), the MPU controls which
regions of shared memory space the DSP is allowed to access. By setting up regions of shared memory, and
defining a protocol for the MPU and DSP to access this shared memory, an interprocessor communication
mechanism may be implemented. This method may be used in conjunction with the mailbox registers to create
handshaking interrupts which will properly synchronize the MPU and DSP accesses to shared memory.
Utilizing the shared memory in this fashion may be useful when the desired data to be passed between the
MPU and DSP is larger than the two 16-bit words provided by each set of mailbox command and data registers.
For example, the MPU may need to provide the DSP with a list of pointers to perform a specific task as opposed
to a single command and single pointer. Using shared memory and the mailboxes, the DSP could read the
list of pointers from shared memory after receiving the interrupt caused by an MPU write to the mailbox
command register.
3.13 DSP Hardware Accelerators
The TMS320C55x DSP core within the OMAP5910 device utilizes three powerful hardware accelerator
modules which assist the DSP core in implementing specific algorithms that are commonly used in video
compression applications such as MPEG4 encoders/decoders. These accelerators allow implementation of
such algorithms using fewer DSP instruction cycles and dissipating less power than implementations using
only the DSP core. The hardware accelerators are utilized via functions from the TMS320C55x Image/Video
Processing Library available from Texas Instruments.
Utilizing the hardware accelerators, the Texas Instruments Image/Video Processing Library implements many
useful functions, which include the following:
•
•
•
•
•
•
•
Forward and Inverse Discrete Cosine Transform (DCT) (used for video compression/decompression)
Motion Estimation (used for compression standards such as MPEG video encoding and H.26x encoding)
Pixel Interpolation (enabling high-performance fractal-pixel motion estimation)
Quantization/Dequantization (useful for JPEG, MPEG, H.26x Encoding/Decoding)
Flexible 1D/2D Wavelet Processing (useful for JPEG2000, MPEG4, and other compression standards)
Boundary and Perimeter Computation (useful for Machine Vision applications)
Image Threshold and Histogram Computations (useful for various Image Analysis applications)
3.13.1 DCT/iDCT Accelerator
The DCT/iDCT hardware accelerator is used to implement Forward and Inverse DCT (Discrete Cosine
Transform) algorithms. These DCT/iDCT algorithms can be used to implement a wide range of video
compression standards including JPEG Encode/Decode, MPEG Video Encode/Decode, and H.26x
Encode/Decode.
3.13.2 Motion Estimation Accelerator
The Motion Estimation hardware accelerator implements a high-performance motion estimation algorithm,
enabling MPEG Video encoder or H.26x encoder applications. Motion estimation is typically one of the most
computation-intensive operations in video-encoding systems.
3.13.3 Pixel Interpolation Accelerator
The Pixel Interpolation Accelerator enables high-performance pixel-interpolation algorithms, which allows for
powerful fractal pixel motion estimation when used in conjunction with the Motion Estimation accelerator. Such
algorithms provide significant improvement to video-encoding applications.
54
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Functional Overview
3.14 Power Supply Connection Examples
3.14.1 Core and I/O Voltage Supply Connections
The OMAP5910 device is extremely flexible regarding the implementation of the core and I/O voltage supplies
of the device.
In a typical system, all of the core voltage supplies (CV
one common supply. Likewise, all of the I/O voltage supplies (DV
powered from a common supply. Figure 3−4 illustrates this common system configuration.
) may be connected together and powered from
DDx
) may be connected together and
DDx
OMAP5910
V
out
= 1.6 V
CV
CV
DD
DD1
DD2
DD3
1.6-V
Voltage
Supply
CV
CV
CV
CV
DD4
DDA
V
out
= 3.3 V
DV
DV
DD1
DD2
DD3
DD4
3.3-V
Voltage
Supply
DV
DV
DV
V
SS
DD5
Figure 3−4. Supply Connections for a Typical System
Several of the I/O voltage supplies (DV
, DV
and DV
) are capable of operating at lower voltages
DD3
DD4
DD5
(1.8 V nominal) while the other I/O supplies run at 3.3 V nominal. This is advantageous for systems which
mix standard 3.3-V devices with low voltage memory devices or other low voltage logic. Refer to Table 2−2
to determine which I/O pins are powered by each of the DV
of this type of mixed voltage system configuration.
supplies. Figure 3−5 illustrates an example
DDx
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August 2002 − Revised August 2003
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Functional Overview
OMAP5910
V
out
= 1.6 V
CV
CV
CV
CV
DD
1.6-V
Voltage
Supply
DD1
DD2
DD3
CV
CV
DD4
DDA
V
out
= 3.3 V
DV
DV
DV
DV
DD1
DD2
DD3
DD4
3.3-V
Voltage
Supply
DV
V
SS
DD5
V
out
= 1.8 V
1.8-V
Voltage
Supply
Figure 3−5. Supply Connections for a System With 1.8-V SDRAM
In the previous two examples, all CV
pins are connected in common. However, the OMAP5910 device
DDx
has dedicated CV
pins which supply power to different sections of the chip (as described in Table 2−3,
DD
Signal Descriptions). This feature could be useful in prototyping phases to troubleshoot power management
features and perform advanced power. By isolating each CV bus from the power source through isolation
DDx
jumpers or current sense resistors, the current draw into different domains may be measured separately. This
type of supply isolation should only be done during prototyping as production system designs should connect
all the CV
pins together, preferably to a common board plane.
DDx
NOTE: There is no specific power sequencing for the different voltage supplies as long as all CV
and
DDx
DV
voltages are ramped to valid operating levels within 500 ms of one another. Additionally, if certain I/O
DDx
pins are unused in a specific system application, the DV
supply pins which power these I/O must still be
DDx
connected to valid operating voltage levels. See Section 5.2, Recommended Operating Conditions, for
complete voltage requirements on all CV
and DV
power supply pins.
DDx
DDx
3.14.2 Core Voltage Noise Isolation
Two of the CV
pins on the OMAP5910 device, CV
and CV
, are dedicated to supply power for the
DD
DDA
DD4
ULPD DPLL and OMAP DPLL, respectively. In addition to using sound board design principles, these
dedicated pins allow for added supply noise isolation circuitry to enable maximum performance from the
OMAP5910 DPLLs. An example circuit is shown in Figure 3−6.
56
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Functional Overview
OMAP5910
Dedicated CV
DD
for
Dedicated CV for
DD
ULPD DPLL
(for USB)
ULPD DPLL
USB DPLL
OMAP DPLL
‡w
V
SS
CV
DD
CV
CV
Common CV
for
DDx
DDA
DD4
DD
Rest of Chip
V
Voltage
RegulatorW
C = 10 µF
R = 10 Ω
†
‡
This circuit is provided only as an example. Specific board layout implementation must minimize noise on the OMAP5910 voltage supply pins.
Except where stated otherwise in this document, all V pins on the OMAP5910 are common and must be connected directly to a common
SS
ground; however, the discrete capacitor in the RC filter circuit should be placed as close as possible to the V
E13/K9).
(GZG balls AA1/Y3 or GDY balls
SS
§
¶
For special consideration with respect to the connection of V
Clock.
The voltage regulator must be selected to provide a voltage source with minimal low frequency noise.
(GZG ball V12 or GDY ball F6), refer to Section 5.6.1, 32-kHz Oscillator and Input
SS
†
Figure 3−6. External RC Circuit for DPLL CV
Noise Isolation
DD
3.15 MPU Register Descriptions
The following tables describe the MPU registers including register addresses, descriptions, required access
widths, access types (R = read, W = write, RW = read/write) and reset values. These tables are organized
by function with like peripherals or functions together and are therefore not necessarily in the order of
ascending register addresses.
NOTE: All accesses to these registers must be of the data access widths indicated to avoid
a TIPB bus error condition and a corresponding interrupt. Reserved addresses should never
be accessed.
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Functional Overview
3.15.1 MPU Private Peripheral Registers
The MPU private peripheral registers include the following:
•
Timers
−
−
−
−
MPU Timer 1 Register
MPU Timer 2 Registers
MPU Timer 3 Registers
MPU Watchdog Timer Registers
•
•
Interrupt Handlers
−
−
MPU Level 1 Interrupt Handler Registers
MPU Level 2 Interrupt Handler Registers
System Peripherals
−
−
System DMA Controller Registers
LCD Controller Registers
Table 3−14. MPU Timer 1 Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
W
FFFE:C500 MPU_CNTL_TIMER_1
FFFE:C504 MPU_LOAD_TIM_1
FFFE:C508 MPU_READ_TIM_1
MPU Timer 1 Control Timer Register
MPU Timer 1 Load Timer Register
MPU Timer 1 Read Timer Register
32
0000 0000h
undef
32
32
R
undef
Table 3−15. MPU Timer 2 Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
W
FFFE:C600 MPU_CNTL_TIMER_2
FFFE:C604 MPU_LOAD_TIM_2
FFFE:C608 MPU_READ_TIM_2
MPU Timer 2 Control Timer Register
MPU Timer 2 Load Timer Register
MPU Timer 2 Read Timer Register
32
0000 0000h
undef
32
32
R
undef
Table 3−16. MPU Timer 3 Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
W
FFFE:C700 MPU_CNTL_TIMER_3
FFFE:C704 MPU_LOAD_TIM_3
FFFE:C708 MPU_READ_TIM_3
MPU Timer 3 Control Timer Register
MPU Timer 3 Load Timer Register
MPU Timer 3 Read Timer Register
32
0000 0000h
undef
32
32
R
undef
Table 3−17. MPU Watchdog Timer Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
W
FFFE:C800 MPU_CNTL_TIMER_WD
FFFE:C804 MPU_LOAD_TIM_WD
FFFE:C808 MPU_READ_TIM_WD
FFFE:C80C MPU_TIMER_MODE_WD
MPU WDT Control Timer Register
MPU WDT Load Timer Register
MPU WDT Read Timer Register
MPU WDT Timer Mode Register
32
0002h
FFFFh
FFFFh
8000h
32
32
R
32
RW
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Functional Overview
Table 3−18. MPU Level 1 Interrupt Handler Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
FFFE:CB00
FFFE:CB04
MPU_L1_ITR
MPU_L1_MIR
Interrupt Register
32
RW
0000 0000h
FFFF FFFFh
Mask Interrupt Register
Reserved
32
RW
FFFE:CB08 −
FFFE:CB0C
FFFE:CB10
FFFE:CB14
FFFE:CB18
FFFE:CB1C
FFFE:CB20
FFFE:CB24
FFFE:CB28
FFFE:CB2C
FFFE:CB30
FFFE:CB34
FFFE:CB38
FFFE:CB3C
FFFE:CB40
FFFE:CB44
FFFE:CB48
FFFE:CB4C
FFFE:CB50
FFFE:CB54
FFFE:CB58
FFFE:CB5C
FFFE:CB60
FFFE:CB64
FFFE:CB68
FFFE:CB6C
FFFE:CB70
FFFE:CB74
FFFE:CB78
FFFE:CB7C
FFFE:CB80
FFFE:CB84
FFFE:CB88
FFFE:CB8C
FFFE:CB90
FFFE:CB94
FFFE:CB98
FFFE:CB9C
MPU_L1_SIR_IRQ_CODE
MPU_L1_SIR_FIQ_CODE
MPU_L1_CONTROL_REG
MPU_L1_ILR0
IRQ Interrupt Encoded Source Register
FIQ Interrupt Encoded Source Register
Interrupt Control Register
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Interrupt 0 Priority Level Register
Interrupt 1 Priority Level Register
Interrupt 2 Priority Level Register
Interrupt 3 Priority Level Register
Interrupt 4 Priority Level Register
Interrupt 5 Priority Level Register
Interrupt 6 Priority Level Register
Interrupt 7 Priority Level Register
Interrupt 8 Priority Level Register
Interrupt 9 Priority Level Register
Interrupt 10 Priority Level Register
Interrupt 11 Priority Level Register
Interrupt 12 Priority Level Register
Interrupt 13 Priority Level Register
Interrupt 14 Priority Level Register
Interrupt 15 Priority Level Register
Interrupt 16 Priority Level Register
Interrupt 17 Priority Level Register
Interrupt 18 Priority Level Register
Interrupt 19 Priority Level Register
Interrupt 20 Priority Level Register
Interrupt 21 Priority Level Register
Interrupt 22 Priority Level Register
Interrupt 23 Priority Level Register
Interrupt 24 Priority Level Register
Interrupt 25 Priority Level Register
Interrupt 26 Priority Level Register
Interrupt 27 Priority Level Register
Interrupt 28 Priority Level Register
Interrupt 29 Priority Level Register
Interrupt 30 Priority Level Register
Interrupt 31 Priority Level Register
Software Interrupt Set Register
MPU_L1_ILR1
MPU_L1_ILR2
MPU_L1_ILR3
MPU_L1_ILR4
MPU_L1_ILR5
MPU_L1_ILR6
MPU_L1_ILR7
MPU_L1_ILR8
MPU_L1_ILR9
MPU_L1_ILR10
MPU_L1_ILR11
MPU_L1_ILR12
MPU_L1_ILR13
MPU_L1_ILR14
MPU_L1_ILR15
MPU_L1_ILR16
MPU_L1_ILR17
MPU_L1_ILR18
MPU_L1_ILR19
MPU_L1_ILR20
MPU_L1_ILR21
MPU_L1_ILR22
MPU_L1_ILR23
MPU_L1_ILR24
MPU_L1_ILR25
MPU_L1_ILR26
MPU_L1_ILR27
MPU_L1_ILR28
MPU_L1_ILR29
MPU_L1_ILR30
MPU_L1_ILR31
MPU_L1_ISR
59
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−19. MPU Level 2 Interrupt Handler Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
FFFE:0000
FFFE:0004
MPU_L2_ITR
MPU_L2_MIR
Interrupt Register
32
RW
0000 0000h
FFFF FFFFh
Mask Interrupt Register
Reserved
32
RW
FFFE:0008 −
FFFE:000C
FFFE:0010
FFFE:0014
FFFE:0018
FFFE:001C
FFFE:0020
FFFE:0024
FFFE:0028
FFFE:002C
FFFE:0030
FFFE:0034
FFFE:0038
FFFE:003C
FFFE:0040
FFFE:0044
FFFE:0048
FFFE:004C
FFFE:0050
FFFE:0054
FFFE:0058
FFFE:005C
FFFE:0060
FFFE:0064
FFFE:0068
FFFE:006C
FFFE:0070
FFFE:0074
FFFE:0078
FFFE:007C
FFFE:0080
FFFE:0084
FFFE:0088
FFFE:008C
FFFE:0090
FFFE:0094
FFFE:0098
FFFE:009C
MPU_L2_SIR_IRQ_CODE
MPU_L2_SIR_FIQ_CODE
MPU_L2_CONTROL_REG
MPU_L2_ILR0
IRQ Interrupt Encoded Source Register
FIQ Interrupt Encoded Source Register
Interrupt Control Register
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Interrupt 0 Priority Level Register
Interrupt 1 Priority Level Register
Interrupt 2 Priority Level Register
Interrupt 3 Priority Level Register
Interrupt 4 Priority Level Register
Interrupt 5 Priority Level Register
Interrupt 6 Priority Level Register
Interrupt 7 Priority Level Register
Interrupt 8 Priority Level Register
Interrupt 9 Priority Level Register
Interrupt 10 Priority Level Register
Interrupt 11 Priority Level Register
Interrupt 12 Priority Level Register
Interrupt 13 Priority Level Register
Interrupt 14 Priority Level Register
Interrupt 15 Priority Level Register
Interrupt 16 Priority Level Register
Interrupt 17 Priority Level Register
Interrupt 18 Priority Level Register
Interrupt 19 Priority Level Register
Interrupt 20 Priority Level Register
Interrupt 21 Priority Level Register
Interrupt 22 Priority Level Register
Interrupt 23 Priority Level Register
Interrupt 24 Priority Level Register
Interrupt 25 Priority Level Register
Interrupt 26 Priority Level Register
Interrupt 27 Priority Level Register
Interrupt 28 Priority Level Register
Interrupt 29 Priority Level Register
Interrupt 30 Priority Level Register
Interrupt 31 Priority Level Register
Software Interrupt Set Register
MPU_L2_ILR1
MPU_L2_ILR2
MPU_L2_ILR3
MPU_L2_ILR4
MPU_L2_ILR5
MPU_L2_ILR6
MPU_L2_ILR7
MPU_L2_ILR8
MPU_L2_ILR9
MPU_L2_ILR10
MPU_L2_ILR11
MPU_L2_ILR12
MPU_L2_ILR13
MPU_L2_ILR14
MPU_L2_ILR15
MPU_L2_ILR16
MPU_L2_ILR17
MPU_L2_ILR18
MPU_L2_ILR19
MPU_L2_ILR20
MPU_L2_ILR21
MPU_L2_ILR22
MPU_L2_ILR23
MPU_L2_ILR24
MPU_L2_ILR25
MPU_L2_ILR26
MPU_L2_ILR27
MPU_L2_ILR28
MPU_L2_ILR29
MPU_L2_ILR30
MPU_L2_ILR31
MPU_L2_ISR
60
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−20. System DMA Controller Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
R
FFFE:D800
FFFE:D802
FFFE:D804
FFFE:D806
FFFE:D808
FFFE:D80A
FFFE:D80C
FFFE:D80E
FFFE:D810
FFFE:D812
FFFE:D814
FFFE:D816
FFFE:D818
SYS_DMA_CSDP_CH0
SYS_DMA_CCR_CH0
SYS_DMA_CICR_CH0
SYS_DMA_CSR_CH0
SYS_DMA_CSSA_L_CH0
SYS_DMA_CSSA_U_CH0
SYS_DMA_CDSA_L_CH0
SYS_DMA_CDSA_U_CH0
SYS_DMA_CEN_CH0
SYS_DMA_CFN_CH0
SYS_DMA_CFI_CH0
Channel 0 Source/Destination Parameters Register
Channel 0 Control Register
16
0000h
16
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
Channel 0 Interrupt Control Register
Channel 0 Status Register
16
16
Channel 0 Source Start Address Register LSB
Channel 0 Source Start Address Register MSB
Channel 0 Destination Start Address Register LSB
Channel 0 Destination Start Address Register MSB
Channel 0 Element Number Register
Channel 0 Frame Number Register
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
16
16
16
16
16
Channel 0 Frame Index Register
16
SYS_DMA_CEI_CH0
Channel 0 Element Index Register
16
SYS_DMA_CPC_CH0
Channel 0 Progress Counter Register
16
FFFE:D81A −
FFFE:083E
Reserved
FFFE:D840
FFFE:D842
FFFE:D844
FFFE:D846
FFFE:D848
FFFE:D84A
FFFE:D84C
FFFE:D84E
FFFE:D850
FFFE:D852
FFFE:D854
FFFE:D856
FFFE:D858
SYS_DMA_CSDP_CH1
SYS_DMA_CCR_CH1
SYS_DMA_CICR_CH1
SYS_DMA_CSR_CH1
SYS_DMA_CSSA_L_CH1
SYS_DMA_CSSA_U_CH1
SYS_DMA_CDSA_L_CH1
SYS_DMA_CDSA_U_CH1
SYS_DMA_CEN_CH1
SYS_DMA_CFN_CH1
SYS_DMA_CFI_CH1
Channel 1 Source/Destination Parameters Register
Channel 1 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
Channel 1 Interrupt Control Register
Channel 1 Status Register
Channel 1 Source Start Address Register LSB
Channel 1 Source Start Address Register MSB
Channel 1 Destination Start Address Register LSB
Channel 1 Destination Start Address Register MSB
Channel 1 Element Number Register
Channel 1 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Channel 1 Frame Index Register
SYS_DMA_CEI_CH1
Channel 1 Element Index Register
SYS_DMA_CPC_CH1
Channel 1 Progress Counter Register
FFFE:D85A −
FFFE:D87E
Reserved
FFFE:D880
FFFE:D882
FFFE:D884
FFFE:D886
FFFE:D888
FFFE:D88A
FFFE:D88C
FFFE:D88E
FFFE:D890
FFFE:D892
FFFE:D894
FFFE:D896
FFFE:D898
SYS_DMA_CSDP_CH2
SYS_DMA_CCR_CH2
SYS_DMA_CICR_CH2
SYS_DMA_CSR_CH2
SYS_DMA_CSSA_L_CH2
SYS_DMA_CSSA_U_CH2
SYS_DMA_CDSA_L_CH2
SYS_DMA_CDSA_U_CH2
SYS_DMA_CEN_CH2
SYS_DMA_CFN_CH2
SYS_DMA_CFI_CH2
Channel 2 Source/Destination Parameters Register
Channel 2 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
Channel 2 Interrupt Control Register
Channel 2 Status Register
Channel 2 Source Start Address Register LSB
Channel 2 Source Start Address Register MSB
Channel 2 Destination Start Address Register LSB
Channel 2 Destination Start Address Register MSB
Channel 2 Element Number Register
Channel 2 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Channel 2 Frame Index Register
SYS_DMA_CEI_CH2
Channel 2 Element Index Register
SYS_DMA_CPC_CH2
Channel 2 Progress Counter Register
61
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−20. System DMA Controller Registers (Continued)
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
FFFE:D89A −
FFFE:D8BE
Reserved
FFFE:D8C0
FFFE:D8C2
FFFE:D8C4
FFFE:D8C6
FFFE:D8C8
FFFE:D8CA
FFFE:D8CC
FFFE:D8CE
FFFE:D8D0
FFFE:D8D2
FFFE:D8D4
FFFE:D8D6
FFFE:D8D8
SYS_DMA_CSDP_CH3
SYS_DMA_CCR_CH3
SYS_DMA_CICR_CH3
SYS_DMA_CSR_CH3
SYS_DMA_CSSA_L_CH3
SYS_DMA_CSSA_U_CH3
SYS_DMA_CDSA_L_CH3
SYS_DMA_CDSA_U_CH3
SYS_DMA_CEN_CH3
SYS_DMA_CFN_CH3
SYS_DMA_CFI_CH3
Channel 3 Source/Destination Parameters Register
Channel 3 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
Channel 3 Interrupt Control Register
Channel 3 Status Register
Channel 3 Source Start Address Register LSB
Channel 3 Source Start Address Register MSB
Channel 3 Destination Start Address Register LSB
Channel 3 Destination Start Address Register MSB
Channel 3 Element Number Register
Channel 3 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Channel 3 Frame Index Register
SYS_DMA_CEI_CH3
Channel 3 Element Index Register
SYS_DMA_CPC_CH3
Channel 3 Progress Counter Register
FFFE:D8DA −
FFFE:D8FE
Reserved
FFFE:D900
FFFE:D902
FFFE:D904
FFFE:D906
FFFE:D908
FFFE:D90A
FFFE:D90C
FFFE:D90E
FFFE:D910
FFFE:D912
FFFE:D914
FFFE:D916
FFFE:D918
SYS_DMA_CSDP_CH4
SYS_DMA_CCR_CH4
SYS_DMA_CICR_CH4
SYS_DMA_CSR_CH4
SYS_DMA_CSSA_L_CH4
SYS_DMA_CSSA_U_CH4
SYS_DMA_CDSA_L_CH4
SYS_DMA_CDSA_U_CH4
SYS_DMA_CEN_CH4
SYS_DMA_CFN_CH4
SYS_DMA_CFI_CH4
Channel 4 Source/Destination Parameters Register
Channel 4 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
Channel 4 Interrupt Control Register
Channel 4 Status Register
Channel 4 Source Start Address Register LSB
Channel 4 Source Start Address Register MSB
Channel 4 Destination Start Address Register LSB
Channel 4 Destination Start Address Register MSB
Channel 4 Element Number Register
Channel 4 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Channel 4 Frame Index Register
SYS_DMA_CEI_CH4
Channel 4 Element Index Register
SYS_DMA_CPC_CH4
Channel 4 Progress Counter Register
FFFE:D91A −
FFFE:D93E
Reserved
FFFE:D940
FFFE:D942
FFFE:D944
FFFE:D946
FFFE:D948
FFFE:D94A
FFFE:D94C
FFFE:D94E
FFFE:D950
FFFE:D952
FFFE:D954
FFFE:D956
SYS_DMA_CSDP_CH5
SYS_DMA_CCR_CH5
SYS_DMA_CICR_CH5
SYS_DMA_CSR_CH5
SYS_DMA_CSSA_L_CH5
SYS_DMA_CSSA_U_CH5
SYS_DMA_CDSA_L_CH5
SYS_DMA_CDSA_U_CH5
SYS_DMA_CEN_CH5
SYS_DMA_CFN_CH5
SYS_DMA_CFI_CH5
Channel 5 Source/Destination Parameters Register
Channel 5 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
Channel 5 Interrupt Control Register
Channel 5 Status Register
Channel 5 Source Start Address Register LSB
Channel 5 Source Start Address Register MSB
Channel 5 Destination Start Address Register LSB
Channel 5 Destination Start Address Register MSB
Channel 5 Element Number Register
Channel 5 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
Channel 5 Frame Index Register
SYS_DMA_CEI_CH5
Channel 5 Element Index Register
62
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−20. System DMA Controller Registers (Continued)
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
Channel 5 Progress Counter Register
Reserved
WIDTH
TYPE
FFFE:D958
SYS_DMA_CPC_CH5
16
RW
undef
FFFE:D95A −
FFFE:D97E
FFFE:D980
FFFE:D982
FFFE:D984
FFFE:D986
FFFE:D988
FFFE:D98A
FFFE:D98C
FFFE:D98E
FFFE:D990
FFFE:D992
FFFE:D994
FFFE:D996
FFFE:D998
SYS_DMA_CSDP_CH6
SYS_DMA_CCR_CH6
SYS_DMA_CICR_CH6
SYS_DMA_CSR_CH6
SYS_DMA_CSSA_L_CH6
SYS_DMA_CSSA_U_CH6
SYS_DMA_CDSA_L_CH6
SYS_DMA_CDSA_U_CH6
SYS_DMA_CEN_CH6
SYS_DMA_CFN_CH6
SYS_DMA_CFI_CH6
Channel 6 Source/Destination Parameters Register
Channel 6 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
Channel 6 Interrupt Control Register
Channel 6 Status Register
Channel 6 Source Start Address Register LSB
Channel 6 Source Start Address Register MSB
Channel 6 Destination Start Address Register LSB
Channel 6 Destination Start Address Register MSB
Channel 6 Element Number Register
Channel 6 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Channel 6 Frame Index Register
SYS_DMA_CEI_CH6
Channel 6 Element Index Register
SYS_DMA_CPC_CH6
Channel 6 Progress Counter Register
FFFE:D99A −
FFFE:D9BE
Reserved
FFFE:D9C0
FFFE:D9C2
FFFE:D9C4
FFFE:D9C6
FFFE:D9C8
FFFE:D9CA
FFFE:D9CC
FFFE:D9CE
FFFE:D9D0
FFFE:D9D2
FFFE:D9D4
FFFE:D9D6
FFFE:D9D8
SYS_DMA_CSDP_CH7
SYS_DMA_CCR_CH7
SYS_DMA_CICR_CH7
SYS_DMA_CSR_CH7
SYS_DMA_CSSA_L_CH7
SYS_DMA_CSSA_U_CH7
SYS_DMA_CDSA_L_CH7
SYS_DMA_CDSA_U_CH7
SYS_DMA_CEN_CH7
SYS_DMA_CFN_CH7
SYS_DMA_CFI_CH7
Channel 7 Source/Destination Parameters Register
Channel 7 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
Channel 7 Interrupt Control Register
Channel 7 Status Register
Channel 7 Source Start Address Register LSB
Channel 7 Source Start Address Register MSB
Channel 7 Destination Start Address Register LSB
Channel 7 Destination Start Address Register MSB
Channel 7 Element Number Register
Channel 7 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
Channel 7 Frame Index Register
SYS_DMA_CEI_CH7
Channel 7 Element Index Register
SYS_DMA_CPC_CH7
Channel 7 Progress Counter Register
FFFE:D9DA −
FFFE:D9FE
Reserved
FFFE:DA00
FFFE:DA02
FFFE:DA04
FFFE:DA06
FFFE:DA08
FFFE:DA0A
FFFE:DA0C
FFFE:DA0E
FFFE:DA10
FFFE:DA12
FFFE:DA14
SYS_DMA_CSDP_CH8
SYS_DMA_CCR_CH8
SYS_DMA_CICR_CH8
SYS_DMA_CSR_CH8
SYS_DMA_CSSA_L_CH8
SYS_DMA_CSSA_U_CH8
SYS_DMA_CDSA_L_CH8
SYS_DMA_CDSA_U_CH8
SYS_DMA_CEN_CH8
SYS_DMA_CFN_CH8
SYS_DMA_CFI_CH8
Channel 8 Source/Destination Parameters Register
Channel 8 Control Register
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
Channel 8 Interrupt Control Register
Channel 8 Status Register
Channel 8 Source Start Address Register LSB
Channel 8 Source Start Address Register MSB
Channel 8 Destination Start Address Register LSB
Channel 8 Destination Start Address Register MSB
Channel 8 Element Number Register
Channel 8 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
Channel 8 Frame Index Register
63
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−20. System DMA Controller Registers (Continued)
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
FFFE:DA16
FFFE:DA18
SYS_DMA_CEI_CH8
SYS_DMA_CPC_CH8
Channel 8 Element Index Register
Channel 8 Progress Counter Register
16
RW
undef
16
RW
undef
FFFE:DA1A −
FFFE:DAFE
Reserved
FFFE:DB00
FFFE:DB02
SYS_DMA_LCD_CTRL
LCD Channel Control Register
16
16
RW
RW
0000h
undef
LCD Channel Top Address Frame Buffer 1 Register
LSB
SYS_DMA_LCD_TOP_F1_L
LCD Channel Top Address Frame Buffer 1 Register
MSB
FFFE:DB04
FFFE:DB06
FFFE:DB08
FFFE:DB0A
FFFE:DB0C
FFFE:DB0E
FFFE:DB10
SYS_DMA_LCD_TOP_F1_U
SYS_DMA_LCD_BOT_F1_L
SYS_DMA_LCD_BOT_F1_U
SYS_DMA_LCD_TOP_F2_L
SYS_DMA_LCD_TOP_F2_U
SYS_DMA_LCD_BOT_F2_L
SYS_DMA_LCD_BOT_F2_U
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
undef
undef
undef
undef
undef
undef
undef
LCD Channel Bottom Address Frame Buffer 1
Register LSB
LCD Channel Bottom Address Frame Buffer 1
Register MSB
LCD Channel Top Address Frame Buffer 2 Register
LSB
LCD Channel Top Address Frame Buffer 2 Register
MSB
LCD Channel Bottom Address Frame Buffer 2
Register LSB
LCD Channel Bottom Address Frame Buffer 2
Register MSB
FFFE:DB12 −
FFFE:DBFE
Reserved
FFFE:DC00
SYS_DMA_GCR
DMA Global Control Register
16
RW
0008h
Table 3−21. LCD Controller Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
RW
RW
RW
FFFE:C000 LCD_CONTROL
FFFE:C004 LCD_TIMING0
FFFE:C008 LCD_TIMING1
FFFE:C00C LCD_TIMING2
FFFE:C010 LCD_STATUS
FFFE:C014 LCD_SUBPANEL
LCD Control Register
32
0x0000 0000
undef
LCD Timing 0 Register
LCD Timing 1 Register
LCD Timing 2 Register
LCD Status Register
32
32
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
32
32
LCD Subpanel Display Register
32
64
SPRS197B
August 2002 − Revised August 2003
Functional Overview
3.15.2 MPU Public Peripheral Registers
The MPU public peripheral registers include the following:
•
Serial Ports
−
−
−
−
−
−
−
McBSP2 Registers
Microwire Registers
2
I C Registers
HDQ/1-Wire Interface Registers
MMC/SD Registers
USB Function Registers
USB Host Registers
•
•
Parallel Ports
−
Camera Interface Registers
Human Interface support
−
−
−
−
−
MPUIO/Keyboard Registers
PWL Registers
PWT Registers
LED Pulse Generator 1 Registers
LED Pulse Generator 2 Registers
•
Timers and Counters
−
−
−
32k Timer Registers
Real-Time Clock Registers
Frame Adjustment Counter Registers
65
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−22. McBSP2 Registers
BYTE
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
ADDRESS
FFFB:1000
FFFB:1002
FFFB:1004
FFFB:1006
FFFB:1008
WIDTH
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
VALUE
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
2000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
MCBSP2_DRR2
MCBSP2_DRR1
MCBSP2_DXR2
MCBSP2_DXR1
MCBSP2_SPCR2
McBSP2 Data receive register 2
McBSP2 Data receive register 1
McBSP2 Data transmit register 2
McBSP2 Data transmit register 1
McBSP2 Serial port control register 2
FFFB:100A MCBSP2_SPCR1
FFFB:100C MCBSP2_RCR2
FFFB:100E MCBSP2_RCR1
McBSP2 Serial port control register 1
McBSP2 Receive control register 2
McBSP2 Receive control register 1
FFFB:1010
FFFB:1012
FFFB:1014
FFFB:1016
FFFB:1018
MCBSP2_XCR2
MCBSP2_XCR1
MCBSP2_SRGR2
MCBSP2_SRGR1
MCBSP2_MCR2
McBSP2 Transmit control register 2
McBSP2 Transmit control register 1
McBSP2 Sample rate generator register 2
McBSP2 Sample rate generator register 1
McBSP2 Multichannel register 2
FFFB:101A MCBSP2_MCR1
FFFB:101C MCBSP2_RCERA
FFFB:101E MCBSP2_RCERB
McBSP2 Multichannel register 1
McBSP2 Receive channel enable register partition A
McBSP2 Receive channel enable register partition B
McBSP2 Transmit channel enable register partition A
McBSP2 Transmit channel enable register partition B
McBSP2 Pin control register 0
FFFB:1020
FFFB:1022
FFFB:1024
FFFB:1026
FFFB:1028
MCBSP2_XCERA
MCBSP2_XCERB
MCBSP2_PCR0
MCBSP2_RCERC
MCBSP2_RCERD
McBSP2 Receive channel enable register partition C
McBSP2 Receive channel enable register partition D
McBSP2 Transmit channel enable register partition C
McBSP2 Transmit channel enable register partition D
McBSP2 Receive channel enable register partition E
McBSP2 Receive channel enable register partition F
McBSP2 Transmit channel enable register partition E
McBSP2 Transmit channel enable register partition F
McBSP2 Receive channel enable register partition G
McBSP2 Receive channel enable register partition H
McBSP2 Transmit channel enable register partition G
McBSP2 Transmit channel enable register partition H
FFFB:102A MCBSP2_XCERC
FFFB:102C MCBSP2_XCERD
FFFB:102E MCBSP2_RCERE
FFFB:1030
FFFB:1032
FFFB:1034
FFFB:1036
FFFB:1038
MCBSP2_RCERF
MCBSP2_XCERE
MCBSP2_XCERF
MCBSP2_RCERG
MCBSP2_RCERH
FFFB:103A MCBSP2_XCERG
FFFB:103C MCBSP2_XCERH
Table 3−23. Microwire Registers
BYTE
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
ADDRESS
DESCRIPTION
WIDTH
TYPE
FFFB:3000
FFFB:3000
FFFB:3004
FFFB:3008
TD
Microwire Transmit Data Register
Microwire Receive Data Register
Microwire Control and Status Register
Microwire Setup Register 1
16
W
undef
RD
16
R
undef
undef
undef
undef
0000h
0000h
0000h
CSR
SR1
16
RW
RW
RW
RW
RW
RW
16
FFFB:300C SR2
Microwire Setup Register 2
16
FFFB:3010
FFFB:3014
FFFB:3018
SR3
SR4
SR5
Microwire Setup Register 3
16
Microwire Setup Register 4
16
Microwire Setup Register 5
16
66
SPRS197B
August 2002 − Revised August 2003
Functional Overview
2
Table 3−24. I C Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
R
VALUE
0011h
0000h
0000h
0000h
2
I C Module Version Register
FFFB:3800
FFFB:3804
FFFB:3808
I2C_REV
I2C_IE
16
2
I C Interrupt Enable Register
16
2
I2C_STAT
I C Status Register
16
2
FFFB:380C I2C_IV
FFFB:3810
I C Interrupt Vector Register
16
R
Reserved
2
FFFB:3814
FFFB:3818
I2C_BUF
I2C_CNT
I C Buffer Configuration Register
16
16
16
RW
RW
RW
0000h
0000h
0000h
2
I C Data Counter Register
2
FFFB:381C I2C_DATA
FFFB:3820
I C Data Access Register
Reserved
2
FFFB:3824
FFFB:3828
I2C_CON
I2C_OA
I C Configuration Register
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
0000h
0000h
03FFh
0000h
0000h
0000h
0000h
2
I C Own Address Register
2
I C Slave Address Register
FFFB:382C I2C_SA
2
I C Clock Prescaler Register
FFFB:3830
FFFB:3834
FFFB:3838
I2C_PSC
I2C_SCLL
I2C_SCLH
2
I C SCL Low Timer Register
2
I C SCL High Timer Register
2
FFFB:383C I2C_SYSTEST
I C System Test Register
Table 3−25. HDQ/1-Wire Interface Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
R
VALUE
FFFB:C000 TXR
FFFB:C004 RXR
FFFB:C008 CSR
FFFB:C00C ISR
TX Write Data Register
8
8
8
8
00h
RX Receive Buffer Register
Control and Status Register
Interrupt Status Register
undef
00h
RW
RW
00h
67
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−26. MMC/SD Registers
BYTE
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
ADDRESS
FFFB:7800
FFFB:7804
FFFB:7808
WIDTH
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
VALUE
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
1F00h
0000h
0000h
2000h
−
MMC_CMD
MMC_ARGL
MMC_ARGH
MMC command
MMC argument low
MMC argument high
FFFB:780C MMC_CON
MMC system configuration
MMC status
FFFB:7810
FFFB:7814
FFFB:7818
MMC_STAT
MMC_IE
MMC system interrupt enable
MMC command timeout
MMC data timeout
MMC_CTO
FFFB:781C MMC_DTO
FFFB:7820
FFFB:7824
FFFB:7828
MMC_DATA
MMC_BLEN
MMC_NBLK
MMC TX/RX FIFO data
MMC block length
MMC number of blocks
MMC buffer configuration
MMC serial port interface
MMC SDIO mode configuration
MMC system test
FFFB:782C MMC_BUF
FFFB:7830
FFFB:7834
FFFB:7838
MMC_SPI
MMC_SDIO
MMC_SYST
FFFB:783C MMC_REV
MMC module version
FFFB:7840
FFFB:7844
FFFB:7848
MMC_RSP0
MMC_RSP1
MMC_RSP2
MMC command response 0
MMC command response 1
MMC command response 2
MMC command response 3
MMC command response 4
MMC command response 5
MMC command response 6
MMC command response 7
R
undef
undef
undef
undef
undef
undef
undef
undef
R
R
FFFB:784C MMC_RSP3
R
FFFB:7850
FFFB:7854
FFFB:7858
MMC_RSP4
MMC_RSP5
MMC_RSP6
R
R
R
FFFB:785C MMC_RSP7
R
68
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−27. USB Function Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
REV
DESCRIPTION
WIDTH
TYPE
VALUE
FFFB:4000
FFFB:4004
FFFB:4008
FFFB:400C
FFFB:4010
FFFB:4014
FFFB:4018
FFFB:401C
FFFB:4020
FFFB:4024
FFFB:4028
FFFB:402C
FFFB:4030
FFFB:4034
FFFB:4038
FFFB:403C
FFFB:4040
FFFB:4044
FFFB:4048
FFFB:404C
FFFB:4050
FFFB:4054
FFFB:4058
FFFB:405C
FFFB:4060
FFFB:4064
FFFB:4068
Revision Register
16
R
−
EP_NUM
DATA
Endpoint Selection Register
Data Register
16
RW
RW
RW
R
0000h
undef
0000h
0202h
0000h
0000h
0000h
undef
0000h
undef
undef
0000h
0000h
0000h
16
CTRL
Control Register
16
STAT_FLG
RXFSTAT
SYSCON1
SYSCON2
DEVSTAT
SOF
Status Flag Register
16
Receive FIFO Status Register
System Configuration 1 Register
System Configuration 2 Register
Device Status Register
16
R
16
RW
RW
R
16
16
Start of Frame Register
16
R
IRQ_EN
Interrupt Enable Register
DMA Interrupt Enable Register
Interrupt Source Register
Endpoint Interrupt Status Register
DMA Endpoint Interrupt Status Register
Reserved
16
RW
RW
RW
R
DMA_IRQ_EN
IRQ_SRC
EPN_STAT
DMAN_STAT
16
16
16
16
R
RXDMA_CFG
TXDMA_CFG
DATA_DMA
Receive Channels DMA Configuration Register
Transmit Channels DMA Configuration Register
DMA FIFO Data Register
Reserved
16
16
16
RW
RW
RW
0000h
0000h
undef
TXDMA0
TXDMA1
TXDMA2
Transmit DMA Control 0 Register
Transmit DMA Control 1 Register
Transmit DMA Control 2 Register
Reserved
16
16
16
RW
RW
RW
0000h
0000h
0000h
RXDMA0
RXDMA1
RXDMA2
Receive DMA Control 0 Register
Receive DMA Control 1 Register
Receive DMA Control 2 Register
16
16
16
RW
RW
RW
0000h
0000h
0000h
FFFB:406C −
FFFB:407C
Reserved
FFFB:4080
FFFB:4084
FFFB:4088
FFFB:408C
FFFB:4090
FFFB:4094
FFFB:4098
FFFB:409C
FFFB:40A0
FFFB:40A4
FFFB:40A8
FFFB:40AC
FFFB:40B0
FFFB:40B4
FFFB:40B8
EP0
Endpoint Configuration 0 Register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
EP1_RX
EP2_RX
EP3_RX
EP4_RX
EP5_RX
EP6_RX
EP7_RX
EP8_RX
EP9_RX
EP10_RX
EP11_RX
EP12_RX
EP13_RX
EP14_RX
Receive Endpoint Configuration 1 Register
Receive Endpoint Configuration 2 Register
Receive Endpoint Configuration 3 Register
Receive Endpoint Configuration 4 Register
Receive Endpoint Configuration 5 Register
Receive Endpoint Configuration 6 Register
Receive Endpoint Configuration 7 Register
Receive Endpoint Configuration 8 Register
Receive Endpoint Configuration 9 Register
Receive Endpoint Configuration 10 Register
Receive Endpoint Configuration 11 Register
Receive Endpoint Configuration 12 Register
Receive Endpoint Configuration 13 Register
Receive Endpoint Configuration 14 Register
69
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−27. USB Function Registers (Continued)
BYTE
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
ADDRESS
FFFB:40BC
FFFB:40C0
FFFB:40C4
FFFB:40C8
FFFB:40CC
FFFB:40D0
FFFB:40D4
FFFB:40D8
FFFB:40DC
FFFB:40E0
FFFB:40E4
FFFB:40E8
FFFB:40EC
FFFB:40F0
FFFB:40F4
FFFB:40F8
FFFB:40FC
WIDTH
TYPE
VALUE
EP15_RX
Receive Endpoint Configuration 15 Register
Reserved
16
RW
undef
EP1_TX
EP2_TX
EP3_TX
EP4_TX
EP5_TX
EP6_TX
EP7_TX
EP8_TX
EP9_TX
EP10_TX
EP11_TX
EP12_TX
EP13_TX
EP14_TX
EP15_TX
Transmit Endpoint Configuration 1 Register
Transmit Endpoint Configuration 2 Register
Transmit Endpoint Configuration 3 Register
Transmit Endpoint Configuration 4 Register
Transmit Endpoint Configuration 5 Register
Transmit Endpoint Configuration 6 Register
Transmit Endpoint Configuration 7 Register
Transmit Endpoint Configuration 8 Register
Transmit Endpoint Configuration 9 Register
Transmit Endpoint Configuration 10 Register
Transmit Endpoint Configuration 11 Register
Transmit Endpoint Configuration 12 Register
Transmit Endpoint Configuration 13 Register
Transmit Endpoint Configuration 14 Register
Transmit Endpoint Configuration 15 Register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
70
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−28. USB Host Controller Registers
BYTE
ADDRESS
ACCESS ACCESS
REGISTER NAME
DESCRIPTION
RESET VALUE
WIDTH
TYPE
FFFB:A000
FFFB:A004
FFFB:A008
FFFB:A00C
FFFB:A010
FFFB:A014
FFFB:A018
HcRevision
OHCI Revision Register
32
R
0000 0010h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
HcControl
Host Controller Operating Mode Register
Host Controller Command and Status Register
Host Controller Interrupt Status Register
Host Controller Interrupt Enable Register
Host Controller Interrupt Disable Register
LB Virtual Address HCCA Register
32
RW
RW
RW
RW
R
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
32
32
32
32
32
RW
LB Virtual Address Current Periodic EP Descriptor
Register
FFFB:A01C
FFFB:A020
FFFB:A024
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
32
32
32
RW
RW
RW
0000 0000h
0000 0000h
0000 0000h
LB Virtual Address Control EP Descriptor List Head
Register
LB Virtual Address Current Control EP Descriptor
Register
FFFB:A028
FFFB:A02C
HcBulkHeadED
LB Virtual Address Bulk EP Descriptor List Head Register
LB Virtual Address Current Bulk EP Descriptor Register
32
32
RW
RW
0000 0000h
0000 0000h
HcBulkCurrentED
LB Virtual Address Retired Transfer Descriptor List Head
Register
FFFB:A030
HcDoneHead
32
R
undef
FFFB:A034
FFFB:A038
FFFB:A03C
FFFB:A040
FFFB:A044
FFFB:A048
FFFB:A04C
FFFB:A050
FFFB:A054
FFFB:A058
FFFB:A05C
HcFmInterval
Frame Interval Register
32
32
32
32
32
32
32
32
32
32
32
RW
R
0000 2EDFh
0000 0000h
0000 0000h
0000 0000h
0000 0628h
0A00 1203h
0000 0000h
0000 0000h
0000 0100h
0000 0100h
0000 0100h
HcFmRemaining
HcFmNumber
Remaining Frame Time Register
Remaining Frame Number Register
Periodic Start Time Register
R
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
RW
RW
RW
RW
RW
RW
RW
RW
Low Speed Start Threshold Register
USB Root Hub Descriptor Register A
USB Root Hub Descriptor Register B
USB Root Hub Status Register
Port 1 Control and Status Register
Port 2 Control and Status Register
Port 3 Control and Status Register
HcRhPortStatus1
HcRhPortStatus2
HcRhPortStatus3
FFFB:A060 −
FFFB:A0DC
Reserved
FFFB:A0E0
FFFB:A0E4
FFFB:A0E8
FFFB:A0EC
HostUEAddr
LB Virtual Address Last Unrecoverable Error Register
LB Cycle Type Last Unrecoverable Error Register
USB Host Mastered Local Bus Time-out Enable Register
USB Host Controller Revision Register
32
32
32
32
R
R
0000 0000h
0000 0000h
0000 0000h
−
HostUEStatus
HostTimeoutCtrl
HostRevision
RW
R
Table 3−29. Camera Interface Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
R
FFFB:6800
FFFB:6804
FFFB:6808
CTRLCLOCK
IT_STATUS
MODE
Clock Control Register
Interrupt Status Register
Mode Configuration Register
Status Register
32
0000 0000h
0000 0000h
0000 0200h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
32
32
RW
R
FFFB:680C STATUS
32
FFFB:6810
FFFB:6814
FFFB:6818
CAMDATA
GPIO
Image Data Register
GPIO Register
32
R
32
RW
RW
PEAK_COUNTER
Fifo Peak Counter Register
32
71
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−30. MPU I/O/Keyboard Registers
BYTE
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
ADDRESS
FFFB:5000
FFFB:5004
FFFB:5008
FFFB:500C
FFFB:5010
FFFB:5014
FFFB:5018
WIDTH
TYPE
VALUE
INPUT_LATCH
OUTPUT_REG
IO_CNTL
Input Register
16
R
undef
Output Register
16
RW
RW
undef
Input Output Control Register
Reserved
16
FFFFh
KBR_LATCH
KBC_REG
Keyboard Row Inputs Register
Keyboard Column Outputs Register
16
16
16
16
16
16
16
16
16
16
R
undef
RW
RW
RW
R
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
GPIO_EVENT_MODE GPIO Event Mode Register
FFFB:501C GPIO_INT_EDGE
GPIO Interrupt Edge Register
Keyboard Interrupt Register
GPIO Interrupt Register
FFFB:5020
FFFB:5024
FFFB:5028
KBD_INT
GPIO_INT
KBD_MASKIT
R
Keyboard Mask Interrupt Register
GPIO Mask Interrupt Register
RW
RW
RW
R
FFFB:502C GPIO_MASKIT
FFFB:5030
FFFB:5034
GPIO_DEBOUNCING GPIO Debouncing Register
GPIO_LATCH
GPIO Latch Register
Table 3−31. PWL Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
VALUE
FFFB:5800
FFFB:5804
PWL_LEVEL
PWL_CTRL
PWL Level Register
PWL Control Register
8
8
RW
0000h
RW
0000h
Table 3−32. PWT Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
VALUE
0000h
0000h
0000h
FFFB:6000
FFFB:6004
FFFB:6008
PWT_FRC
PWT_VCR
PWT_GCR
PWT Frequency Control Register
8
8
8
RW
PWT Volume Control Register
PWT General Control Register
RW
RW
Table 3−33. LED Pulse Generator 1 Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
VALUE
FFFB:D000 LCR_1
FFFB:D004 PMR_1
LPG1 Control Register
8
8
RW
00h
LPG1 Power Management Register
RW
00h
Table 3−34. LED Pulse Generator 2 Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
VALUE
FFFB:D800 LCR_2
FFFB:D804 PMR_2
LPG2 Control Register
8
8
RW
00h
LPG2 Power Management Register
RW
00h
Table 3−35. 32k Timer Registers
REGISTER
NAME
ACCESS ACCESS
RESET
VALUE
BYTE ADDRESS
DESCRIPTION
WIDTH
TYPE
RW
R
FFFB:9000
FFFB:9004
FFFB:9008
TVR
TCR
CR
Tick Value Register
Tick Counter Register
Control Register
32
00FF FFFFh
00FF FFFFh
0000 0008h
32
32
RW
72
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−36. Real-Time Clock Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
SECONDS_REG
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
RW
RW
RW
RW
VALUE
FFFB:4800
FFFB:4804
FFFB:4808
FFFB:480C
FFFB:4810
FFFB:4814
FFFB:4818
FFFB:481C
FFFB:4820
FFFB:4824
FFFB:4828
FFFB:482C
FFFB:4830
FFFB:4834
RTC Seconds Register
RTC Minutes Register
RTC Hours Register
8
8
8
8
8
8
8
00h
MINUTES_REG
HOURS_REG
DAYS_REG
00h
00h
RTC Days Register
01h
MONTHS_REG
YEARS_REG
WEEK_REG
RTC Months Register
RTC Years Register
01h
00h
RTC Weeks Register
Reserved
00h
ALARM_SECOND_REG
ALARM_MINUTES_REG
ALARM_HOURS_REG
ALARM_DAYS_REG
RTC Alarm Seconds Register
RTC Alarm Minutes Register
RTC Alarm Hours Register
RTC Alarm Days Register
RTC Alarm Months Register
RTC Alarm Years Register
8
8
8
8
8
8
RW
RW
RW
RW
RW
RW
00h
00h
00h
01h
01h
00h
ALARM_MONTHS_REG
ALARM_YEARS_REG
FFFB:4838 −
FFFB:483C
Reserved
FFFB:4840
FFFB:4844
FFFB:4848
FFFB:484C
FFFB:4850
RTC_CTRL_REG
RTC Control Register
8
8
8
8
8
RW
RW
RW
RW
RW
00h
00h
00h
00h
00h
RTC_STATUS_REG
RTC Status Register
RTC_INTERRUPTS_REG
RTC_COMP_LSB_REG
RTC_COMP_MSB_REG
RTC Interrupts Register
RTC Compensation LSB Register
RTC Compensation MSB Register
Table 3−37. Frame Adjustment Counter Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
R
VALUE
0000h
0000h
0000h
0000h
undef
FFFB:A800 FARC
Frame Adjustment Reference Count Register
Frame Start Count Register
16
FFFB:A804 FSC
16
FFFB:A808 CTRL
Control and Configuration Register
Status Register
16
RW
R
FFFB:A80C STATUS
FFFB:A810 SYNC_CNT
FFFB:A814 START_CNT
16
Frame Synchronization Register
Frame Start Counter Register
16
R
16
R
undef
73
August 2002 − Revised August 2003
SPRS197B
Functional Overview
3.15.3 MPU Configuration Registers
The MPU Configuration Registers include the following:
•
•
Pin Multiplexing setup:
OMAP5910 Pin Configuration Registers
Local Bus and MMU setup:
−
−
−
−
Local Bus Control Registers
Local Bus MMU Registers
DSP MMU Registers
•
MPUI and TIPB setup:
−
−
−
−
−
MPU Interface (MPUI) Registers
TIPB (Private) Bridge 1 Configuration Registers
TIPB (Public) Bridge 2 Configuration Registers
MPU UART TI Peripheral Bus Switch Registers
Traffic Controller Registers
•
•
Clock and Power Management:
−
−
−
MPU Clock/Reset/Power Mode Control Registers
DPLL1 Configuration Register
Ultra Low-Power Device Module Registers
Device Identification:
−
−
Device Die Identification Registers
JTAG Identification Code Register
74
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−38. OMAP 5910 Pin Configuration Registers
BYTE
ADDRESS
ACCESS ACCESS
WIDTH
RESET
VALUE
REGISTER NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
FFFE:1000
FFFE:1004
FFFE:1008
FFFE:100C
FFFE:1010
FFFE:1014
FFFE:1018
FFFE:101C
FFFE:1020
FFFE:1024
FFFE:1028
FFFE:102C
FFFE:1030
FFFE:1034
FFFE:1038
FFFE:103C
FFFE:1040
FFFE:1044
FFFE:1048
FFFE:104C
FFFE:1050
FUNC_MUX_CTRL_0
FUNC_MUX_CTRL_1
FUNC_MUX_CTRL_2
COMP_MODE_CTRL_0
FUNC_MUX_CTRL_3
FUNC_MUX_CTRL_4
FUNC_MUX_CTRL_5
FUNC_MUX_CTRL_6
FUNC_MUX_CTRL_7
FUNC_MUX_CTRL_8
FUNC_MUX_CTRL_9
FUNC_MUX_CTRL_A
FUNC_MUX_CTRL_B
FUNC_MUX_CTRL_C
FUNC_MUX_CTRL_D
Functional Multiplexing Control 0 Register
Functional Multiplexing Control 1 Register
Functional Multiplexing Control 2 Register
Compatibility Mode Control 0 Register
Functional Multiplexing Control 3 Register
Functional Multiplexing Control 4 Register
Functional Multiplexing Control 5 Register
Functional Multiplexing Control 6 Register
Functional Multiplexing Control 7 Register
Functional Multiplexing Control 8 Register
Functional Multiplexing Control 9 Register
Functional Multiplexing Control A Register
Functional Multiplexing Control B Register
Functional Multiplexing Control C Register
Functional Multiplexing Control D Register
Reserved
32
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
32
32
32
32
32
32
32
32
32
32
32
32
32
32
PULL_DWN_CTRL_0
PULL_DWN_CTRL_1
PULL_DWN_CTRL_2
PULL_DWN_CTRL_3
GATE_INH_CTRL_0
Pulldown Control 0 Register
32
32
32
32
32
RW
RW
RW
RW
RW
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
Pulldown Control 1 Register
Pulldown Control 2 Register
Pulldown Control 3 Register
Gate and Inhibit Control 0 Register
FFFE:1054 −
FFFE:105C
Reserved
FFFE:1060
VOLTAGE_CTRL_0
TEST_DBG_CTRL_0
MOD_CONF_CTRL_0
REGISTER NAME
Voltage Control 0 Register
Reserved
32
32
32
RW
RW
RW
0000 0000h
0000 0000h
0000 0000h
FFFE:1064 −
FFFE:106C
FFFE:1070
Test Debug Control 0 Register
Reserved
FFFE:1074 −
FFFE:107C
FFFE:1080
Module Configuration Control 0 Register
Table 3−39. Local Bus Control Registers
BYTE
ADDRESS
ACCESS ACCESS
WIDTH
RESET
VALUE
DESCRIPTION
TYPE
RW
RW
RW
RW
R
FFFE:C100 LB_MPU_TIMEOUT
FFFE:C104 LB_HOLD_TIMER
FFFE:C108 LB_PRIORITY_REG
FFFE:C10C LB_CLOCK_DIV
FFFE:C110 LB_ABORT_ADD
FFFE:C114 LB_ABORT_DATA
FFFE:C118 LB_ABORT_STATUS
FFFE:C11C LB_IRQ_OUTPUT
FFFE:C120 LB_IRQ_INPUT
Local bus MPU access TIMEOUT
Local bus hold timer
32
0000 00FFh
0000 0000h
0000 0000h
0000 00FCh
FFFF FFFFh
FFFF FFFFh
0000 0000h
0000 0000h
0000 0000h
32
Local bus MPU access priority
32
Local bus clock divider
32
Local bus address of aborted MPU cycle
Local bus cycle data of aborted MPU write cycle
Local bus cycle type of aborted MPU write cycle
Local bus external interrupt output control
Local bus external interrupt status
32
32
R
32
R
32
RW
RW
32
75
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−40. Local Bus MMU Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
†
FFFE:C204 LB_MMU_WALKING_ST_REG
FFFE:C208 LB_MMU_CNTL_REG
FFFE:C20C LB_MMU_FAULT_AD_H_REG
FFFE:C210 LB_MMU_FAULT_AD_L_REG
FFFE:C214 LB_MMU_FAULT_ST_REG
FFFE:C218 LB_MMU_IT_ACK_REG
FFFE:C21C LB_MMU_TTB_H_REG
FFFE:C220 LB_MMU_TTB_L_REG
FFFE:C224 LB_MMU_LOCK_REG
FFFE:C228 LB_MMU_LD_TLB_REG
FFFE:C22C LB_MMU_CAM_H_REG
FFFE:C230 LB_MMU_CAM_L_REG
FFFE:C234 LB_MMU_RAM_H_REG
FFFE:C238 LB_MMU_RAM_L_REG
FFFE:C23C LB_MMU_GFLUSH_REG
Local bus MMU Walking Status
Local bus MMU Control
32
RW
RW
R
0000h
†
32
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Local bus MMU Fault Address High
Local bus MMU Fault Address Low
Local bus MMU Fault Status
32
32
R
32
R
Local bus MMU Interrupt Acknowledge
Local bus MMU TTB Register High
Local bus MMU TTB Register Low
Local bus MMU Lock Counter
32
W
†
†
32
RW
32
RW
32
RW
RW
RW
RW
RW
RW
RW
Local bus MMU TLB Load/Read Control
Local bus MMU CAM Entry High
Local bus MMU CAM Entry Low
Local bus MMU RAM Entry High
Local bus MMU RAM Entry Low
Local bus MMU Global Flush Control
Local bus MMU Individual Entry Flush
32
32
32
32
32
32
FFFE:C240 LB_MMU_FLUSH_ENTRY_REG
32
RW
0000h
Control
FFFE:C244 LB_MMU_READ_CAM_H_REG
FFFE:C248 LB_MMU_READ_CAM_L_REG
FFFE:C24C LB_MMU_READ_RAM_H_REG
FFFE:C250 LB_MMU_READ_RAM_L_REG
Local bus MMU CAM Read High
Local bus MMU CAM Read Low
Local bus MMU RAM Read High
Local bus MMU RAM Read Low
32
32
32
32
RW
RW
RW
RW
0000h
0000h
0000h
0000h
†
Write access in ARM supervisor mode only.
76
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−41. DSP MMU Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
TYPE
RW
R
FFFE:D200 DSP_MMU_PREFETCH_REG
FFFE:D204 DSP_MMU_WALKING_ST_REG
FFFE:D208 DSP_MMU_CNTL_REG
DSP MMU Prefetch Register
0000h
DSP MMU Prefetch Status Register
DSP MMU Control Register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
RW
R
FFFE:D20C DSP_MMU_FAULT_AD_H_REG
FFFE:D210 DSP_MMU_FAULT_AD_L_REG
FFFE:D214 DSP_MMU_F_ST_REG
DSP MMU Fault Address Register MSB
DSP MMU Fault Address Register LSB
DSP MMU Fault Status Register
DSP MMU IT Acknowledge Register
DSP MMU TTB Register MSB
R
R
FFFE:D218 DSP_MMU_IT_ACK_REG
FFFE:D21C DSP_MMU_TTB_H_REG
FFFE:D220 DSP_MMU_TTB_L_REG
FFFE:D224 DSP_MMU_LOCK_REG
W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DSP MMU TTB Register LSB
DSP MMU Lock Counter Register
DSP MMU Load Entry TLB Register
DSP MMU CAM Entry Register MSB
DSP MMU CAM Entry Register LSB
DSP MMU RAM Entry Register MSB
DSP MMU RAM Entry Register LSB
DSP MMU Global Flush Register
DSP MMU Individual Flush Register
DSP MMU Read CAM Register MSB
DSP MMU Read CAM Register LSB
DSP MMU Read RAM Register MSB
DSP MMU Read RAM Register LSB
FFFE:D228 DSP_MMU_LD_TLB_REG
FFFE:D22C DSP_MMU_CAM_H_REG
FFFE:D230 DSP_MMU_CAM_L_REG
FFFE:D234 DSP_MMU_RAM_H_REG
FFFE:D238 DSP_MMU_RAM_L_REG
FFFE:D23C DSP_MMU_GFLUSH_REG
FFFE:D240 DSP_MMU_FLUSH_ENTRY_REG
FFFE:D244 DSP_MMU_READ_CAM_H_REG
FFFE:D248 DSP_MMU_READ_CAM_L_REG
FFFE:D24C DSP_MMU_READ_RAM_H_REG
FFFE:D250 DSP_MMU_READ_RAM_L_REG
Table 3−42. MPUI Registers
BYTE
ACCESS ACCESS
RESET
REGISTER NAME
ADDRESS
DESCRIPTION
WIDTH
TYPE
RW
R
VALUE
0003 FF1Bh
01FF FFFFh
FFFF FFFFh
0800h
FFFE:C900 CTRL_REG
MPUI Control Register
32
FFFE:C904 DEBUG_ADDR
FFFE:C908 DEBUG_DATA
FFFE:C90C DEBUG_FLAG
FFFE:C910 STATUS_REG
FFFE:C914 DSP_STATUS_REG
FFFE:C918 DSP_BOOT_CONFIG
FFFE:C91C DSP_MPUI_CONFIG
MPUI Debug Address Register
MPUI Debug Data Register
MPUI Debug Flag Register
MPUI Status Register
32
32
R
32
R
32
R
0000h
MPUI DSP Status Register
MPUI Boot Configuration Register
MPUI DSP MPUI Configuration Register
32
R
undef
32
RW
RW
0000h
32
FFFFh
Table 3−43. TIPB (Private) Bridge 1 Configuration Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
RW
R
FFFE:CA00 TIPB_CNTL
Private TIPB Control Register
32
FF11h
0009h
0000h
0007h
FFFFh
FFFFh
FFFFh
00F8h
FFFE:CA04 TIPB_BUS_ALLOC
FFFE:CA08 MPU_TIPB_CNTL
FFFE:CA0C ENHANCED_TIPB_CNTL
FFFE:CA10 ADDRESS_DBG
FFFE:CA14 DATA_DEBUG_LOW
FFFE:CA18 DATA_DEBUG_HIGH
FFFE:CA1C DEBUG_CNTR_SIG
Private TIPB Bus Allocation Register
Private MPU TIPB Control Register
Private Enhanced TIPB Control Register
Private Debug Address Register
Private Debug Data LSB Register
Private Debug Data MSB Register
Private Debug Control Signals Register
32
32
32
32
32
R
32
R
32
R
77
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−44. TIPB (Public) Bridge 2 Configuration Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
RW
R
FFFE:D300 TIPB_CNTL
Public TIPB Control Register
16
FF11h
FFFE:D304 TIPB_BUS_ALLOC
FFFE:D308 MPU_TIPB_CNTL
FFFE:D30C ENHANCED_TIPB_CNTL
FFFE:D310 ADDRESS_DBG
FFFE:D314 DATA_DEBUG_LOW
FFFE:D318 DATA_DEBUG_HIGH
FFFE:D31C DEBUG_CNTR_SIG
Public TIPB Bus Allocation Register
Public MPU TIPB Control Register
Public Enhanced TIPB Control Register
Public Debug Address Register
Public Debug Data LSB Register
Public Debug Data MSB Register
Public Debug Control Signals Register
16
0009h
0000h
0007h
FFFFh
FFFFh
FFFFh
00F8h
16
16
16
16
R
16
R
16
R
Table 3−45. MPU UART TIPB Bus Switch Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
R
VALUE
FFFB:C800
FFFB:C804
RHSW_ARM_CNF1 UART1 TIPB Switch Configuration Register (MPU)
16
0001h
RHSW_ARM_STA1
UART1 TIPB Switch Status Register (MPU)
16
0001h
FFFB:C808 −
FFFB:C83C
Reserved
FFFB:C840
FFFB:C844
RHSW_ARM_CNF2 UART2 TIPB Switch Configuration Register (MPU)
RHSW_ARM_STA2 UART2 TIPB Switch Status Register (MPU)
16
16
RW
R
0001h
0001h
FFFB:C848 −
FFFB:C87C
Reserved
FFFB:C880
FFFB:C884
RHSW_ARM_CNF3 UART3 TIPB Switch Configuration Register (MPU)
RHSW_ARM_STA3 UART3 TIPB Switch Status Register (MPU)
16
16
RW
R
0001h
0001h
78
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−46. Traffic Controller Registers
BYTE
ADDRESS
ACCESS ACCESS
WIDTH
RESET
VALUE
REGISTER NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
FFFE:CC00 IMIF_PRIO
TC IMIF Priority Register
32
0000 0000h
0000 0000h
0000 0000h
FFFE:CC04 EMIFS_PRIO_REG
FFFE:CC08 EMIFF_PRIO_REG
FFFE:CC0C EMIFS_CONFIG_REG
FFFE:CC10 EMIFS_CS0_CONFIG
FFFE:CC14 EMIFS_CS1_CONFIG
FFFE:CC18 EMIFS_CS2_CONFIG
FFFE:CC1C EMIFS_CS3_CONFIG
FFFE:CC20 EMIFF_SDRAM_CONFIG
FFFE:CC24 EMIFF_MRS
TC EMIFS Priority Register
32
TC EMIFF Priority Register
32
†
y00z0b
TC EMIFS Configuration Register
TC EMIFS CS0 Configuration Register
TC EMIFS CS1 Configuration Register
TC EMIFS CS2 Configuration Register
TC EMIFS CS3 Configuration Register
TC EMIFF SDRAM Configuration Register
TC EMIFF SDRAM MRS Register
TC Timeout 1 Register
32
32
0010 FFFBh
0010 FFFBh
0010 FFFBh
0010 FFFBh
0061 8800h
0000 0037h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0003h
0000 0000h
32
32
32
32
32
FFFE:CC28 TIMEOUT1
32
FFFE:CC2C TIMEOUT2
TC Timeout 2 Register
32
FFFE:CC30 TIMEOUT3
TC Timeout 3 Register
32
FFFE:CC34 ENDIANISM
TC Endianism Register
32
FFFE:CC38
Reserved
32
FFFE:CC3C EMIFF_SDRAM_CONFIG_2
FFFE:CC40 EMIFS_CFG_DYN_WAIT
TC EMIFF SDRAM Configuration Register 2
TC EMIFS Wait-State Configuration Register
32
32
†
The value of y is dependent upon the state of the FLASH.RDY pin and the value of z is dependent upon the state of the MPU_BOOT pin upon
power-on reset.
Table 3−47. MPU Clock/Reset/Power Mode Control Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
RW
RW
RW
RW
FFFE:CE00 ARM_CKCTL
FFFE:CE04 ARM_IDLECT1
FFFE:CE08 ARM_IDLECT2
FFFE:CE0C ARM_EWUPCT
FFFE:CE10 ARM_RSTCT1
FFFE:CE14 ARM_RSTCT2
FFFE:CE18 ARM_SYSST
MPU Clock Control Register
MPU Idle Control 1 Register
MPU Idle Control 2 Register
MPU External Wakeup Control Register
MPU Reset Control 1 Register
MPU Reset Control 2 Register
MPU System Status Register
32
3000h
32
0400h
0100h
003Fh
0000h
0000h
0038h
32
32
32
32
32
Table 3−48. DPLL1 Register
DESCRIPTION
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
WIDTH
TYPE
FFFE:CF00 DPLL1_CTL_REG
DPLL1 Control Register
32
RW
0000 2002h
79
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−49. Ultra Low-Power Device Module Registers
BYTE
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
VALUE
0001h
0001h
0001h
0000h
0000h
0000h
FFFE:0800
FFFE:0804
FFFE:0808
FFFE:080C
FFFE:0810
FFFE:0814
COUNTER_32_LSB
ULPD 32-kHz Counter Register LSB
ULPD 32-kHz Counter Register MSB
ULPD High-Frequency Counter LSB Register
ULPD High-Frequency Counter MSB Register
ULPD Gauging Control Register
16
R
COUNTER_32_MSB
16
R
COUNTER_HIGH_FREQ_LSB
COUNTER_HIGH_FREQ_MSB
GAUGING_CTRL_REG
IT_STATUS_REG
16
R
16
R
16
RW
R
ULPD Interrupt Status Register
16
FFFE:0818 −
FFFE:0820
Reserved
FFFE:0824
SETUP_ULPD1_REG
ULPD Wakeup Time Setup Register
Reserved
16
RW
03FFh
FFFE:0828 −
FFFE:082C
FFFE:0830
FFFE:0834
FFFE:0838
FFFE:083C
FFFE:0840
FFFE:0844
FFFE:0848
FFFE:084C
FFFE:0850
CLOCK_CTRL_REG
SOFT_REQ_REG
ULPD Clock Control Register
ULPD Soft Clock Request Register
ULPD Modem Shutdown Delay Register
ULPD USB DPLL Control Register
ULPD Hardware Request Status Register
Reserved
16
16
16
16
16
RW
RW
RW
RW
RW
0000h
0000h
0001h
2211h
undef
COUNTER_32_FIQ_REG
DPLL_CTRL_REG
STATUS_REQ_REG
LOCK_TIME_REG
APLL_CTRL_REG
POWER_CTRL_REG
ULPD APLL Lock Time Register
ULPD APLL Control Register
ULPD Power Control Register
16
16
16
RW
RW
RW
0960h
undef
0008h
Table 3−50. Device Die Identification Registers
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
FFFE:1800
FFFE:1804
DIE_ID_LSB
DIE_ID_MSB
Device Die Identification Register (LSB)
Device Die Identification Register (MSB)
32
R
R
−
−
32
Table 3−51. JTAG Identification Code Register
BYTE
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
FFFE:D404 JTAG_ID
JTAG Identification Code Register
32
R
−
80
SPRS197B
August 2002 − Revised August 2003
Functional Overview
3.16 DSP Register Descriptions
The following tables describe the DSP registers including register addresses, descriptions, required access
widths, access types (R-read, W-write, RW-read/write) and reset values. These tables are organized by
function with like peripherals or functions together and are therefore not necessarily in the order of ascending
register addresses.
NOTE: All accesses to these registers must be of the data access widths indicated to avoid
a TIPB bus error condition and a corresponding interrupt. Reserved addresses should never
be accessed
3.16.1 DSP Private Peripheral Registers
The DSP private peripheral registers include the following:
•
•
DMA Controller:
−
DSP DMA Controller Registers
Timers:
−
−
−
−
DSP Timer 1 Registers
DSP Timer 2 Registers
DSP Timer 3 Registers
DSP Watchdog Timer Registers
•
Interrupt Control:
−
−
DSP Interrupt Interface Registers
DSP Level 2 Interrupt Handler Registers
81
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−52. DSP DMA Controller Registers
DSP WORD
ACCESS ACCESS
REGISTER NAME
DESCRIPTION
RESET VALUE
ADDRESS
0x00 0C00h
0x00 0C01h
0x00 0C02h
0x00 0C03h
0x00 0C04h
0x00 0C05h
0x00 0C06h
0x00 0C07h
0x00 0C08h
0x00 0C09h
0x00 0C0Ah
0x00 0C0Bh
0x00 0C0Ch
0x00 0C0Dh
0x00 0C0Eh
0x00 0C0Fh
WIDTH
TYPE
RW
RW
RW
R
DMA_CSDP0
DMA_CCR0
Channel 0 Source/Destination Parameters Register
Channel 0 Control Register
16
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
16
DMA_CICR0
DMA_CSR0
Channel 0 Interrupt Control Register
16
Channel 0 Status Register
16
DMA_CSSA_L0
DMA_CSSA_U0
DMA_CDSA_L0
DMA_CDSA_U0
DMA_CEN0
Channel 0 Source Start Address Register LSB
Channel 0 Source Start Address Register MSB
Channel 0 Destination Start Address Register LSB
Channel 0 Destination Start Address Register MSB
Channel 0 Element Number Register
Channel 0 Frame Number Register
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
16
16
16
16
DMA_CFN0
16
DMA_CSFI0
DMA_CSEI0
DMA_CSAC0
DMA_CDAC0
DMA_CDFI0
DMA_CDEI0
Channel 0 Frame Index Register
16
Channel 0 Element Index Register
16
Channel 0 Source Address Counter Register
Channel 0 Destination Address Counter Register
Channel 0 Destination Frame Index
16
16
16
Channel 0 Destination Element Index
16
0x00 0C10h −
0x00 0C1Fh
Reserved
0x00 0C20h
0x00 0C21h
0x00 0C22h
0x00 0C23h
0x00 0C24h
0x00 0C25h
0x00 0C26h
0x00 0C27h
0x00 0C28h
0x00 0C29h
0x00 0C2Ah
0x00 0C2Bh
0x00 0C2Ch
0x00 0C2Dh
0x00 0C2Eh
0x00 0C2Fh
DMA_CSDP1
DMA_CCR1
Channel 1 Source/Destination Parameters Register
Channel 1 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
DMA_CICR1
DMA_CSR1
Channel 1 Interrupt Control Register
Channel 1 Status Register
DMA_CSSA_L1
DMA_CSSA_U1
DMA_CDSA_L1
DMA_CDSA_U1
DMA_CEN1
Channel 1 Source Start Address Register LSB
Channel 1 Source Start Address Register MSB
Channel 1 Destination Start Address Register LSB
Channel 1 Destination Start Address Register MSB
Channel 1 Element Number Register
Channel 1 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DMA_CFN1
DMA_CSFI1
DMA_CSEI1
DMA_CSAC1
DMA_CDAC1
DMA_CDFI1
DMA_CDEI1
Channel 1 Frame Index Register
Channel 1 Element Index Register
Channel 1 Source Address Counter Register
Channel 1 Destination Address Counter Register
Channel 1 Destination Frame Index
Channel 1 Destination Element Index
0x00 0C30h −
0x00 0C3Fh
Reserved
0x00 0C40h
0x00 0C41h
0x00 0C42h
0x00 0C43h
0x00 0C44h
0x00 0C45h
0x00 0C46h
0x00 0C47h
DMA_CSDP2
DMA_CCR2
Channel 2 Source/Destination Parameters Register
Channel 2 Control Register
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
DMA_CICR2
Channel 2 Interrupt Control Register
DMA_CSR2
Channel 2 Status Register
DMA_CSSA_L2
DMA_CSSA_U2
DMA_CDSA_L2
DMA_CDSA_U2
Channel 2 Source Start Address Register LSB
Channel 2 Source Start Address Register MSB
Channel 2 Destination Start Address Register LSB
Channel 2 Destination Start Address Register MSB
RW
RW
RW
RW
82
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−52. DSP DMA Controller Registers (Continued)
DSP WORD
ADDRESS
ACCESS ACCESS
REGISTER NAME
DESCRIPTION
RESET VALUE
WIDTH
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
0x00 0C48h
0x00 0C49h
0x00 0C4Ah
0x00 0C4Bh
0x00 0C4Ch
0x00 0C4Dh
0x00 0C4Eh
0x00 0C4Fh
DMA_CEN2
DMA_CFN2
DMA_CSFI2
DMA_CSEI2
DMA_CSAC2
DMA_CDAC2
DMA_CDFI2
DMA_CDEI2
Channel 2 Element Number Register
Channel 2 Frame Number Register
Channel 2 Frame Index Register
16
undef
undef
undef
undef
undef
undef
undef
undef
16
16
Channel 2 Element Index Register
16
Channel 2 Source Address Counter Register
Channel 2 Destination Address Counter Register
Channel 2 Destination Frame Index
Channel 2 Destination Element Index
16
16
16
16
0x00 0C50h −
0x00 0C5Fh
Reserved
0x00 0C60h
0x00 0C61h
0x00 0C62h
0x00 0C63h
0x00 0C64h
0x00 0C65h
0x00 0C66h
0x00 0C67h
0x00 0C68h
0x00 0C69h
0x00 0C6Ah
0x00 0C6Bh
0x00 0C6Ch
0x00 0C6Dh
0x00 0C6Eh
0x00 0C6Fh
DMA_CSDP3
DMA_CCR3
Channel 3 Source/Destination Parameters Register
Channel 3 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
DMA_CICR3
DMA_CSR3
Channel 3 Interrupt Control Register
Channel 3 Status Register
DMA_CSSA_L3
DMA_CSSA_U3
DMA_CDSA_L3
DMA_CDSA_U3
DMA_CEN3
Channel 3 Source Start Address Register LSB
Channel 3 Source Start Address Register MSB
Channel 3 Destination Start Address Register LSB
Channel 3 Destination Start Address Register MSB
Channel 3 Element Number Register
Channel 3 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DMA_CFN3
DMA_CSFI3
DMA_CSEI3
DMA_CSAC3
DMA_CDAC3
DMA_CDFI3
DMA_CDEI3
Channel 3 Frame Index Register
Channel 3 Element Index Register
Channel 3 Source Address Counter Register
Channel 3 Destination Address Counter Register
Channel 3 Destination Frame Index
Channel 3 Destination Element Index
0x00 0C70h −
0x00 0C7Fh
Reserved
0x00 0C80h
0x00 0C81h
0x00 0C82h
0x00 0C83h
0x00 0C84h
0x00 0C85h
0x00 0C86h
0x00 0C87h
0x00 0C88h
0x00 0C89h
0x00 0C8Ah
0x00 0C8Bh
0x00 0C8Ch
0x00 0C8Dh
0x00 0C8Eh
0x00 0C8Fh
DMA_CSDP4
DMA_CCR4
Channel 4 Source/Destination Parameters Register
Channel 4 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
DMA_CICR4
DMA_CSR4
Channel 4 Interrupt Control Register
Channel 4 Status Register
DMA_CSSA_L4
DMA_CSSA_U4
DMA_CDSA_L4
DMA_CDSA_U4
DMA_CEN4
Channel 4 Source Start Address Register LSB
Channel 4 Source Start Address Register MSB
Channel 4 Destination Start Address Register LSB
Channel 4 Destination Start Address Register MSB
Channel 4 Element Number Register
Channel 4 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DMA_CFN4
DMA_CSFI4
DMA_CSEI4
DMA_CSAC4
DMA_CDAC4
DMA_CDFI4
DMA_CDEI4
Channel 4 Frame Index Register
Channel 4 Element Index Register
Channel 4 Source Address Counter Register
Channel 4 Destination Address Counter Register
Channel 4 Destination Frame Index
Channel 4 Destination Element Index
83
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−52. DSP DMA Controller Registers (Continued)
DSP WORD
ADDRESS
ACCESS ACCESS
REGISTER NAME
DESCRIPTION
RESET VALUE
WIDTH
TYPE
0x00 0C90h −
0x00 0C9Fh
Reserved
0x00 0CA0h
0x00 0CA1h
0x00 0CA2h
0x00 0CA3h
0x00 0CA4h
0x00 0CA5h
0x00 0CA6h
0x00 0CA7h
0x00 0CA8h
0x00 0CA9h
0x00 0CAAh
0x00 0CABh
0x00 0CACh
0x00 0CADh
0x00 0CAEh
0x00 0CAFh
DMA_CSDP5
DMA_CCR5
Channel 5 Source/Destination Parameters Register
Channel 5 Control Register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
R
0000h
0000h
0003h
0000h
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
undef
DMA_CICR5
DMA_CSR5
Channel 5 Interrupt Control Register
Channel 5 Status Register
DMA_CSSA_L5
DMA_CSSA_U5
DMA_CDSA_L5
DMA_CDSA_U5
DMA_CEN5
Channel 5 Source Start Address Register LSB
Channel 5 Source Start Address Register MSB
Channel 5 Destination Start Address Register LSB
Channel 5 Destination Start Address Register MSB
Channel 5 Element Number Register
Channel 5 Frame Number Register
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DMA_CFN5
DMA_CSFI5
DMA_CSEI5
DMA_CSAC5
DMA_CDAC5
DMA_CDFI5
DMA_CDEI5
Channel 5 Frame Index Register
Channel 5 Element Index Register
Channel 5 Source Address Counter Register
Channel 5 Destination Address Counter Register
Channel 5 Destination Frame Index
Channel 5 Destination Element Index
0x00 0CB0h −
0x00 0DFFh
Reserved
0x00 0E00h
0x00 0E01h
0x00 0E02h
DMA_GCR
DMA_GTCR
DMA_GSCR
Global Control Register
16
16
16
RW
RW
RW
0008h
0000h
0000h
Global Timeout Control Register
Global Software Incompatible Control Register
84
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−53. DSP Timer 1 Registers
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
0x00 2800h
0x00 2801h
0x00 2802h
0x00 2803h
0x00 2804h
0x00 2805h
DSP_CNTL_TIMER_1
DSP Timer 1 Control Timer Register
Reserved
16
RW
0000h
DSP_LOAD_TIM_HI_1
DSP Timer 1 Load Timer High Register
16
16
16
16
W
W
R
undef
undef
undef
undef
DSP_LOAD_TIM_LO_1 DSP Timer 1 Load Timer Low Register
DSP_READ_TIM_HI_1 DSP Timer 1 Read Timer High Register
DSP_READ_TIM_LO_1 DSP Timer 1 Read Timer Low Register
R
Table 3−54. DSP Timer 2 Registers
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
0x00 2C00h
0x00 2C01h
0x00 2C02h
0x00 2C03h
0x00 2C04h
0x00 2C05h
DSP_CNTL_TIMER_2
DSP Timer 2 Control Timer Register
Reserved
16
RW
0000h
DSP_LOAD_TIM_HI_2
DSP Timer 2 Load Timer High Register
16
16
16
16
W
W
R
undef
undef
undef
undef
DSP_LOAD_TIM_LO_2 DSP Timer 2 Load Timer Low Register
DSP_READ_TIM_HI_2 DSP Timer 2 Read Timer High Register
DSP_READ_TIM_LO_2 DSP Timer 2 Read Timer Low Register
R
Table 3−55. DSP Timer 3 Registers
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
0x00 3000h
0x00 3001h
0x00 3002h
0x00 3003h
0x00 3004h
0x00 3005h
DSP_CNTL_TIMER_3
DSP Timer 3 Control Timer Register
Reserved
16
RW
0000h
DSP_LOAD_TIM_HI_3
DSP Timer 3 Load Timer High Register
16
16
16
16
W
W
R
undef
undef
undef
undef
DSP_LOAD_TIM_LO_3 DSP Timer 3 Load Timer Low Register
DSP_READ_TIM_HI_3 DSP Timer 3 Read Timer High Register
DSP_READ_TIM_LO_3 DSP Timer 3 Read Timer Low Register
R
Table 3−56. DSP Watchdog Timer Registers
DSP WORD
ADDRESS
ACCESS ACCESS
REGISTER NAME
DESCRIPTION
RESET VALUE
WIDTH
TYPE
0x00 3400h
0x00 3401h
0x00 3402h
0x00 3402h
0x00 3403h
0x00 3404h
DSP_CNTL_TIMER_WD
DSP WDT Control Timer Register
Reserved
16
RW
0002h
DSP_LOAD_TIM_WD
DSP_READ_TIM_WD
DSP WDT Load Timer Register
DSP WDT Read Timer Register
Reserved
16
16
W
R
FFFFh
FFFFh
DSP_TIMER_MODE_WD
DSP WDT Timer Mode Register
16
RW
8000h
Table 3−57. DSP Interrupt Interface Registers
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
W
0x00 3800h
0x00 3801h
0x00 3802h
0x00 3803h
ET_LS_CTRL_HI
ET_LS_CTRL_LO
RST_LVL_LO
Edge Triggered/Level Sensitive Control Register High
Edge Triggered/Level Sensitive Control Register Low
Level Sensitive Clear Low Register
16
0000h
0000h
0000h
0000h
16
16
RST_LVL_HI
Level Sensitive Clear High Register
16
W
85
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−58. DSP Level 2 Interrupt Handler Registers
DSP WORD
ADDRESS
ACCESS ACCESS
REGISTER NAME
DESCRIPTION
RESET VALUE
WIDTH
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
TYPE
RW
RW
R
0x00 4800h
0x00 4802h
0x00 4804h
0x00 4806h
0x00 4808h
0x00 480Ah
0x00 480Ch
0x00 480Eh
0x00 4810h
0x00 4812h
0x00 4814h
0x00 4816h
0x00 4818h
0x00 481Ah
0x00 481Ch
0x00 481Eh
0x00 4820h
0x00 4822h
0x00 4824h
0x00 4826h
0x00 4828h
0x00 482Ah
DSP_L2_ITR
DSP_L2_MIR
Interrupt Register
0000h
FFFFh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Mask Interrupt Register
DSP_L2_SIR_IRQ_CODE
DSP_L2_SIR_FIQ_CODE
DSP_L2_CONTROL_REG
DSP_L2_ISR
IRQ Interrupt Encoded Source Register
FIQ Interrupt Encoded Source Register
Interrupt Control Register
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Software Interrupt Set Register
Interrupt 0 Priority Level Register
Interrupt 1 Priority Level Register
Interrupt 2 Priority Level Register
Interrupt 3 Priority Level Register
Interrupt 4 Priority Level Register
Interrupt 5 Priority Level Register
Interrupt 6 Priority Level Register
Interrupt 7 Priority Level Register
Interrupt 8 Priority Level Register
Interrupt 9 Priority Level Register
Interrupt 10 Priority Level Register
Interrupt 11 Priority Level Register
Interrupt 12 Priority Level Register
Interrupt 13 Priority Level Register
Interrupt 14 Priority Level Register
Interrupt 15 Priority Level Register
DSP_L2_ILR0
DSP_L2_ILR1
DSP_L2_ILR2
DSP_L2_ILR3
DSP_L2_ILR4
DSP_L2_ILR5
DSP_L2_ILR6
DSP_L2_ILR7
DSP_L2_ILR8
DSP_L2_ILR9
DSP_L2_ILR10
DSP_L2_ILR11
DSP_L2_ILR12
DSP_L2_ILR13
DSP_L2_ILR14
DSP_L2_ILR15
86
SPRS197B
August 2002 − Revised August 2003
Functional Overview
3.16.2 DSP Public Peripheral Registers
The DSP public peripheral registers include the following:
•
Serial Ports:
−
−
−
−
McBSP1 Registers
McBSP3 Registers
MCSI1 Registers
MCSI2 Registers
Table 3−59. McBSP1 Registers
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
0x00 8C00h E101:1800 MCBSP1_DRR2
0x00 8C01h E101:1802 MCBSP1_DRR1
0x00 8C02h E101:1804 MCBSP1_DXR2
0x00 8C03h E101:1806 MCBSP1_DXR1
0x00 8C04h E101:1808 MCBSP1_SPCR2
0x00 8C05h E101:180A MCBSP1_SPCR1
0x00 8C06h E101:180C MCBSP1_RCR2
0x00 8C07h E101:180E MCBSP1_RCR1
0x00 8C08h E101:1810 MCBSP1_XCR2
0x00 8C09h E101:1812 MCBSP1_XCR1
0x00 8C0Ah E101:1814 MCBSP1_SRGR2
0x00 8C0Bh E101:1816 MCBSP1_SRGR1
0x00 8C0Ch E101:1818 MCBSP1_MCR2
0x00 8C0Dh E101:181A MCBSP1_MCR1
McBSP1 data receive register 2
McBSP1 data receive register 1
McBSP1 data transmit register 2
McBSP1 data transmit register 1
McBSP1 serial port control register 2
McBSP1 serial port control register 1
McBSP1 receive control register 2
McBSP1 receive control register 1
McBSP1 transmit control register 2
McBSP1 transmit control register 1
McBSP1 sample rate generator register 2
McBSP1 sample rate generator register 1
McBSP1 multichannel register 2
McBSP1 multichannel register 1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
2000h
0001h
0000h
0000h
McBSP1 receive channel enable register
partition A
0x00 8C0Eh E101:181C MCBSP1_RCERA
0x00 8C0Fh E101:181E MCBSP1_RCERB
0x00 8C10h E101:1820 MCBSP1_XCERA
16
16
16
RW
RW
RW
0000h
0000h
0000h
McBSP1 receive channel enable register
partition B
McBSP1 transmit channel enable register
partition A
McBSP1 transmit channel enable register
partition B
0x00 8C11h E101:1822 MCBSP1_XCERB
0x00 8C12h E101:1824 MCBSP1_PCR0
0x00 8C13h E101:1826 MCBSP1_RCERC
16
16
16
RW
RW
RW
0000h
0000h
0000h
McBSP1 pin control register 0
McBSP1 receive channel enable register
partition C
McBSP1 receive channel enable register
partition D
0x00 8C14h E101:1828 MCBSP1_RCERD
0x00 8C15h E101:182A MCBSP1_XCERC
0x00 8C16h E101:182C MCBSP1_XCERD
0x00 8C17h E101:182E MCBSP1_RCERE
0x00 8C18h E101:1830 MCBSP1_RCERF
0x00 8C19h E101:1832 MCBSP1_XCERE
0x00 8C1Ah E101:1834 MCBSP1_XCERF
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
0000h
0000h
0000h
0000h
0000h
0000h
0000h
McBSP1 transmit channel enable register
partition C
McBSP1 transmit channel enable register
partition D
McBSP1 receive channel enable register
partition E
McBSP1 receive channel enable register
partition F
McBSP1 transmit channel enable register
partition E
McBSP1 transmit channel enable register
partition F
87
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−59. McBSP1 Registers (Continued)
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
McBSP1 receive channel enable register
partition G
0x00 8C1Bh E101:1836 MCBSP1_RCERG
0x00 8C1Ch E101:1838 MCBSP1_RCERH
0x00 8C1Dh E101:183A MCBSP1_XCERG
0x00 8C1Eh E101:183C MCBSP1_XCERH
16
RW
0000h
McBSP1 receive channel enable register
partition H
16
RW
0000h
0000h
0000h
McBSP1 transmit channel enable register
partition G
16
RW
McBSP1 transmit channel enable register
partition H
16
RW
Table 3−60. McBSP3 Registers
MPU BYTE
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
ADDRESS
(VIA MPUI)
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
0x00 B800h E101:7000 MCBSP3_DRR2
0x00 B801h E101:7002 MCBSP3_DRR1
0x00 B802h E101:7004 MCBSP3_DXR2
0x00 B803h E101:7006 MCBSP3_DXR1
0x00 B804h E101:7008 MCBSP3_SPCR2
0x00 B805h E101:700A MCBSP3_SPCR1
0x00 B806h E101:700C MCBSP3_RCR2
0x00 B807h E101:700E MCBSP3_RCR1
0x00 B808h E101:7010 MCBSP3_XCR2
0x00 B809h E101:7012 MCBSP3_XCR1
0x00 B80Ah E101:7014 MCBSP3_SRGR2
0x00 B80Bh E101:7016 MCBSP3_SRGR1
0x00 B80Ch E101:7018 MCBSP3_MCR2
0x00 B80Dh E101:701A MCBSP3_MCR1
McBSP3 data receive register 2
McBSP3 data receive register 1
McBSP3 data transmit register 2
McBSP3 data transmit register 1
McBSP3 serial port control register 2
McBSP3 serial port control register 1
McBSP3 receive control register 2
McBSP3 receive control register 1
McBSP3 transmit control register 2
McBSP3 transmit control register 1
McBSP3 sample rate generator register 2
McBSP3 sample rate generator register 1
McBSP3 multichannel register 2
McBSP3 multichannel register 1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
2000h
0001h
0000h
0000h
McBSP3 receive channel enable register
partition A
0x00 B80Eh E101:701C MCBSP3_RCERA
0x00 B80Fh E101:701E MCBSP3_RCERB
0x00 B810h E101:7020 MCBSP3_XCERA
16
16
16
RW
RW
RW
0000h
0000h
0000h
McBSP3 receive channel enable register
partition B
McBSP3 transmit channel enable register
partition A
McBSP3 transmit channel enable register
partition B
0x00 B811h E101:7022 MCBSP3_XCERB
0x00 B812h E101:7024 MCBSP3_PCR0
0x00 B813h E101:7026 MCBSP3_RCERC
16
16
16
RW
RW
RW
0000h
0000h
0000h
McBSP3 pin control register 0
McBSP3 receive channel enable register
partition C
McBSP3 receive channel enable register
partition D
0x00 B814h E101:7028 MCBSP3_RCERD
0x00 B815h E101:702A MCBSP3_XCERC
0x00 B816h E101:702C MCBSP3_XCERD
0x00 B817h E101:702E MCBSP3_RCERE
0x00 B818h E101:7030 MCBSP3_RCERF
16
16
16
16
16
RW
RW
RW
RW
RW
0000h
0000h
0000h
0000h
0000h
McBSP3 transmit channel enable register
partition C
McBSP3 transmit channel enable register
partition D
McBSP3 receive channel enable register
partition E
McBSP3 receive channel enable register
partition F
88
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−60. McBSP3 Registers (Continued)
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
RW
RW
RW
McBSP3 transmit channel enable register
partition E
0x00 B819h E101:7032 MCBSP3_XCERE
0x00 B81Ah E101:7034 MCBSP3_XCERF
0x00 B81Bh E101:7036 MCBSP3_RCERG
0x00 B81Ch E101:7038 MCBSP3_RCERH
0x00 B81Dh E101:703A MCBSP3_XCERG
0x00 B81Eh E101:703C MCBSP3_XCERH
16
0000h
McBSP3 transmit channel enable register
partition F
16
0000h
0000h
0000h
0000h
0000h
McBSP3 receive channel enable register
partition G
16
McBSP3 receive channel enable register
partition H
16
McBSP3 transmit channel enable register
partition G
16
McBSP3 transmit channel enable register
partition H
16
89
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−61. MCSI1 Registers
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
0x00 9400h
0x00 9401h
0x00 9402h
0x00 9403h
0x00 9404h
E101:2800 MCSI1_CONTROL_REG
MCSI1 control register
16
16
16
16
16
RW
RW
RW
RW
RW
0000h
E101:2802 MCSI1_MAIN_PARAMETERS_REG MCSI1 main parameters register
0000h
0000h
0000h
0000h
E101:2804 MCSI1_INTERRUPTS_REG
E101:2806 MCSI1_CHANNEL_USED_REG
E101:2808 MCSI1_OVER_CLOCK_REG
MCSI1 interrupts register
MCSI1 channel used register
MCSI1 over-clock register
MCSI1_CLOCK_FREQUENCY_
0x00 9405h
0x00 9406h
E101:280A
REG
MCSI1 clock frequency register
MCSI1 status register
16
16
RW
RW
0000h
0000h
E101:280C MCSI1_STATUS_REG
Reserved
0x00 9407h−
0x00 941Fh
0x00 9420h
0x00 9421h
0x00 9422h
0x00 9423h
0x00 9424h
0x00 9425h
0x00 9426h
0x00 9427h
0x00 9428h
0x00 9429h
0x00 942Ah
0x00 942Bh
0x00 942Ch
0x00 942Dh
0x00 942Eh
0x00 942Fh
0x00 9430h
0x00 9431h
0x00 9432h
0x00 9433h
0x00 9434h
0x00 9435h
0x00 9436h
0x00 9437h
0x00 9438h
0x00 9439h
0x00 943Ah
0x00 943Bh
0x00 943Ch
0x00 943Dh
0x00 943Eh
0x00 943Fh
E101:2840 MCSI1_TX0
E101:2842 MCSI1_TX1
E101:2844 MCSI1_TX2
E101:2846 MCSI1_TX3
E101:2848 MCSI1_TX4
E101:284A MCSI1_TX5
E101:284C MCSI1_TX6
E101:284E MCSI1_TX7
E101:2850 MCSI1_TX8
E101:2852 MCSI1_TX9
E101:2854 MCSI1_TX10
E101:2856 MCSI1_TX11
E101:2858 MCSI1_TX12
E101:285A MCSI1_TX13
E101:285C MCSI1_TX14
E101:285E MCSI1_TX15
E101:2860 MCSI1_RX0
E101:2862 MCSI1_RX1
E101:2864 MCSI1_RX2
E101:2866 MCSI1_RX3
E101:2868 MCSI1_RX4
E101:286A MCSI1_RX5
E101:286C MCSI1_RX6
E101:286E MCSI1_RX7
E101:2870 MCSI1_RX8
E101:2872 MCSI1_RX9
E101:2874 MCSI1_RX10
E101:2876 MCSI1_RX11
E101:2878 MCSI1_RX12
E101:287A MCSI1_RX13
E101:287C MCSI1_RX14
E101:287E MCSI1_RX15
MCSI1 transmit word register 0
MCSI1 transmit word register 1
MCSI1 transmit word register 2
MCSI1 transmit word register 3
MCSI1 transmit word register 4
MCSI1 transmit word register 5
MCSI1 transmit word register 6
MCSI1 transmit word register 7
MCSI1 transmit word register 8
MCSI1 transmit word register 9
MCSI1 transmit word register 10
MCSI1 transmit word register 11
MCSI1 transmit word register 12
MCSI1 transmit word register 13
MCSI1 transmit word register 14
MCSI1 transmit word register 15
MCSI1 receive word register 0
MCSI1 receive word register 1
MCSI1 receive word register 2
MCSI1 receive word register 3
MCSI1 receive word register 4
MCSI1 receive word register 5
MCSI1 receive word register 6
MCSI1 receive word register 7
MCSI1 receive word register 8
MCSI1 receive word register 9
MCSI1 receive word register 10
MCSI1 receive word register 11
MCSI1 receive word register 12
MCSI1 receive word register 13
MCSI1 receive word register 14
MCSI1 receive word register 15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
90
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−62. MCSI2 Registers
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
0x00 9000h
0x00 9001h
0x00 9002h
0x00 9003h
0x00 9004h
E101:2000 MCSI2_CONTROL_REG
MCSI2 control register
16
16
16
16
16
RW
RW
RW
RW
RW
0000h
E101:2002 MCSI2_MAIN_PARAMETERS_REG MCSI2 main parameters register
0000h
0000h
0000h
0000h
E101:2004 MCSI2_INTERRUPTS_REG
E101:2006 MCSI2_CHANNEL_USED_REG
E101:2008 MCSI2_OVER_CLOCK_REG
MCSI2 interrupts register
MCSI2 channel used register
MCSI2 over-clock register
MCSI2_CLOCK_FREQUENCY_
0x00 9005h
0x00 9006h
E101:200A
REG
MCSI2 clock frequency register
MCSI2 status register
16
16
RW
RW
0000h
0000h
E101:200C MCSI2_STATUS_REG
Reserved
0x00 9007h −
0x00 901Fh
0x00 9020h
0x00 9021h
0x00 9022h
0x00 9023h
0x00 9024h
0x00 9025h
0x00 9026h
0x00 9027h
0x00 9028h
0x00 9029h
0x00 902Ah
0x00 902Bh
0x00 902Ch
0x00 902Dh
0x00 902Eh
0x00 902Fh
0x00 9030h
0x00 9031h
0x00 9032h
0x00 9033h
0x00 9034h
0x00 9035h
0x00 9036h
0x00 9037h
0x00 9038h
0x00 9039h
0x00 903Ah
0x00 903Bh
0x00 903Ch
0x00 903Dh
0x00 903Eh
0x00 903Fh
E101:2040 MCSI2_TX0
E101:2042 MCSI2_TX1
E101:2044 MCSI2_TX2
E101:2046 MCSI2_TX3
E101:2048 MCSI2_TX4
E101:204A MCSI2_TX5
E101:204C MCSI2_TX6
E101:204E MCSI2_TX7
E101:2050 MCSI2_TX8
E101:2052 MCSI2_TX9
E101:2054 MCSI2_TX10
E101:2056 MCSI2_TX11
E101:2058 MCSI2_TX12
E101:205A MCSI2_TX13
E101:205C MCSI2_TX14
E101:205E MCSI2_TX15
E101:2060 MCSI2_RX0
E101:2062 MCSI2_RX1
E101:2064 MCSI2_RX2
E101:2066 MCSI2_RX3
E101:2068 MCSI2_RX4
E101:206A MCSI2_RX5
E101:206C MCSI2_RX6
E101:206E MCSI2_RX7
E101:2070 MCSI2_RX8
E101:2072 MCSI2_RX9
E101:2074 MCSI2_RX10
E101:2076 MCSI2_RX11
E101:2078 MCSI2_RX12
E101:207A MCSI2_RX13
E101:207C MCSI2_RX14
E101:207E MCSI2_RX15
MCSI2 transmit word register 0
MCSI2 transmit word register 1
MCSI2 transmit word register 2
MCSI2 transmit word register 3
MCSI2 transmit word register 4
MCSI2 transmit word register 5
MCSI2 transmit word register 6
MCSI2 transmit word register 7
MCSI2 transmit word register 8
MCSI2 transmit word register 9
MCSI2 transmit word register 10
MCSI2 transmit word register 11
MCSI2 transmit word register 12
MCSI2 transmit word register 13
MCSI2 transmit word register 14
MCSI2 transmit word register 15
MCSI2 receive word register 0
MCSI2 receive word register 1
MCSI2 receive word register 2
MCSI2 receive word register 3
MCSI2 receive word register 4
MCSI2 receive word register 5
MCSI2 receive word register 6
MCSI2 receive word register 7
MCSI2 receive word register 8
MCSI2 receive word register 9
MCSI2 receive word register 10
MCSI2 receive word register 11
MCSI2 receive word register 12
MCSI2 receive word register 13
MCSI2 receive word register 14
MCSI2 receive word register 15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
91
August 2002 − Revised August 2003
SPRS197B
Functional Overview
3.16.3 DSP Configuration Registers
The DSP configuration registers include the following:
•
•
•
I-Cache and EMIF setup
−
−
DSP Instruction Cache Registers
DSP EMIF Configuration Registers
TIPB setup
−
−
DSP TIPB Bridge Configuration Registers
DSP UART TI Peripheral Bus Switch Registers
Clock Control:
DSP Clock Mode Registers
−
Table 3−63. DSP Instruction Cache Registers
DSP WORD
ADDRESS
ACCESS ACCESS
RESET
VALUE
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
RW
RW
R
0x00 1400h ICGC
0x00 1401h
I-Cache Global Control Register
Reserved
16
C006h
16
0000h
0000h
000Dh
0000h
000Dh
0000h
000Dh
0000h
0x00 1402h
Reserved
16
0x00 1403h ICWC
0x00 1404h ICST
0x00 1405h ICRC1
0x00 1406h ICRTAG1
0x00 1407h ICRC2
0x00 1408h ICRTAG2
I-Cache Way Control Register
I-Cache Status Register
16
16
I-Cache Ramset 1 Control Register
I-Cache Remset 1 TAG Register
I-Cache Ramset 2 Control Register
I-Cache Remset 2 TAG Register
16
RW
RW
RW
RW
16
16
16
Table 3−64. DSP EMIF Configuration Register
DSP WORD
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
RW
RW
VALUE
0020h
undef
0x00 0800h DSP_EMIF_GCR
0x00 0801h DSP_EMIF_GRR
DSP EMIF Global Control Register
DSP EMIF Global Reset Register
16
16
Table 3−65. DSP TIPB Bridge Configuration Registers
DSP WORD
ACCESS ACCESS RESET
REGISTER NAME
ADDRESS
DESCRIPTION
WIDTH
TYPE
VALUE
FE4Dh
0000h
0x00 0000h TIPB_CMR
0x00 0001h TIPB_ICR
0x00 0002h TIPB_ISTR
DSP TIPB Bridge Control Mode Register
DSP TIPB Bridge Idle Control Register
DSP TIPB Bridge Idle Status Register
16
RW
16
RW
R
16
0000h
92
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−66. DSP UART TIPB Bus Switch Registers
DSP WORD
ADDRESS
ACCESS ACCESS RESET
REGISTER NAME
DESCRIPTION
WIDTH
TYPE
VALUE
0x00 E400h RHSW_DSP_CNF1
0x00 E402h RHSW_DSP_STA1
UART1 TIPB Switch Configuration Register (DSP)
UART1 TIPB Switch Status Register (DSP)
16
RW
0001h
16
R
0001h
0x00 E404−
0x00 E0Eh
Reserved
0x00 E410h RHSW_DSP_CNF2
0x00 E412h RHSW_DSP_STA2
UART2 TIPB Switch Configuration Register (DSP)
UART2 TIPB Switch Status Register (DSP)
16
16
RW
R
0001h
0001h
0x00 E414−
0x00 E1Eh
Reserved
0x00 E420h RHSW_DSP_CNF3
0x00 E422h RHSW_DSP_STA3
UART3 TIPB Switch Configuration Register (DSP)
UART3 TIPB Switch Status Register (DSP)
16
16
RW
R
0001h
0001h
Table 3−67. DSP Clock Mode Registers
MPU BYTE
DSP WORD
ACCESS ACCESS
RESET
VALUE
ADDRESS
REGISTER NAME
DESCRIPTION
ADDRESS
WIDTH
TYPE
(VIA MPUI)
0x00 4000h
0x00 4002h
0x00 4004h
E100:8000
E100:8004
E100:8008
DSP_CKCTL
DSP_IDLECT1
DSP_IDLECT2
DSP Clock Control Register
DSP Idle Control 1 Register
DSP Idle Control 2 Register
16
16
16
RW
RW
RW
0000h
0000h
0000h
0x00 4006h −
0x00 4008h
Reserved
0x00 400Ah
0x00 400Ch
E100:8014
E100:8018
DSP_RSTCT2
DSP_SYSST
DSP Peripheral Reset Control Register
DSP System Status Register
16
16
RW
RW
0000h
0000h
93
August 2002 − Revised August 2003
SPRS197B
Functional Overview
3.16.4 MPU/DSP Shared Peripheral Register Descriptions
The following tables describe the MPU/DSP shared peripheral registers including register addresses,
descriptions, required access widths, access types (R-read, W-write, RW-read/write) and reset values. These
tables are organized by function with like peripherals or functions together and are therefore not necessarily
in order of ascending register addresses. Reserved addresses should never be accessed.
NOTE: All accesses to these registers must be of the data access widths indicated to avoid
a TIPB bus error condition and a corresponding interrupt. Reserved addresses should never
be accessed.
The MPU/DSP shared peripheral registers include the following:
•
UARTs:
−
−
−
UART1 Registers
UART2 Registers
UART3/IrDA Registers
•
GPIO and Mailboxes
−
−
MPU/DSP Shared GPIO Registers
MPU/DSP Shared Mailbox Registers
94
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−68. UART1 Registers
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD
ADDRESS
MPU BYTE
ADDRESS
REGISTER
DESCRIPTION
NAME
ACCESS ACCESS
RESET
VALUE
WIDTH
TYPE
†
0x00 8000h
0x00 8000h
0x00 8000h
0x00 8001h
0x00 8001h
FFFB:0000
FFFB:0000
FFFB:0000
FFFB:0004
FFFB:0004
E101:0000
E101:0000
E101:0000
E101:0002
E101:0002
UART1_RHR
UART1 receive holding register
UART1 transmit holding register
UART1 divisor latch low register
UART1 interrupt enable register
UART1 divisor latch high register
8
8
8
8
8
R
Undefined
Undefined
00h
†
UART1_THR
‡§
W
UART1_DLL
RW
RW
RW
†
UART1_IER
00h
‡§
UART1_DLH
00h
UART1 interrupt identification
register
†‡
0x00 8002h
0x00 8002h
0x00 8002h
FFFB:0008
FFFB:0008
FFFB:0008
E101:0004
E101:0004
E101:0004
UART1_IIR
UART1_FCR
UART1_EFR
8
8
8
R
W
01h
00h
00h
†‡¶
§
UART1 FIFO control register
UART1 enhanced
feature register
RW
0x00 8003h
0x00 8004h
0x00 8004h
0x00 8005h
0x00 8005h
0x00 8006h
FFFB:000C
FFFB:0010
FFFB:0010
FFFB:0014
FFFB:0014
FFFB:0018
E101:0006
E101:0008
E101:0008
E101:000A
E101:000A
E101:000C
UART1_LCR
UART1_MCR
UART1_XON1
UART1 line control register
UART1 modem control register
UART1 XON1 register
8
8
8
8
8
8
RW
RW
RW
R
00h
†‡¶
00h
§
00h
†‡
UART1_LSR
UART1 mode register
60h
§
UART1_XON2
UART1 XON2 register
RW
R
00h
†‡
UART1_MSR
UART1 modem status register
Undefined
UART1 transmission
control register
#
0x00 8006h
FFFB:0018
E101:000C
UART1_TCR
8
RW
0Fh
§
0x00 8006h
0x00 8007h
0x00 8007h
0x00 8007h
FFFB:0018
FFFB:001C
FFFB:001C
FFFB:001C
E101:000C
E101:000E
E101:000E
E101:000E
UART1_XOFF1
†‡
UART1 XOFF1 register
UART1 scratchpad register
UART1 trigger level register
UART1 XOFF2 register
8
8
8
8
RW
RW
RW
RW
00h
00h
00h
00h
UART1_SPR
#
UART1_TLR
§
UART1_XOFF2
UART1 mode definition
1 register
0x00 8008h
FFFB:0020
E101:0010
UART1_MDR1
8
RW
07h
0x00 8009h − FFFB:0024 −
Reserved
0x00 800Dh
0x00 800Eh
0x00 800Fh
0x00 8010h
FFFB:0034
FFFB:0038
FFFB:003C
FFFB:0040
UART1 autobauding
status register
‡§
E101:001C
UART1_UASR
8
R
00h
Reserved
UART1 supplementary
control register
E101:0020
E101:0022
UART1_SCR
UART1_SSR
8
8
RW
R
00h
00h
UART1 supplementary
status register
0x00 8011h
0x00 8012h
0x00 8013h
0x00 8014h
FFFB:0044
FFFB:0048
FFFB:004C
FFFB:0050
Reserved
UART1_OSC_
UART1 12-/13-MHz oscillator
select register
E101:0026
E101:0028
8
8
W
R
00h
−
†
12M_SEL
UART1_MVR
UART1 module version register
†
‡
§
¶
#
Register is accessible when LCR[7] = 0 (normal operating mode)
Register is accessible when LCR[7] = 1 and LCR[7:0] ꢀ 0BFh
Register is accessible when LCR[7] = 0BFh
Register is write accessible when EFR[4] = 1
Register is accessible when EFR[4] = 1 and MCR[6] = 1
95
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−69. UART2 Registers
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD MPU BYTE
REGISTER
DESCRIPTION
NAME
ACCESS ACCESS
RESET
VALUE
ADDRESS
ADDRESS
WIDTH
TYPE
†
0x00 8400h FFFB:0800
0x00 8400h FFFB:0800
0x00 8400h FFFB:0800
0x00 8401h FFFB:0804
0x00 8401h FFFB:0804
E101:0800
E101:0800
E101:0800
E101:0802
E101:0802
UART2_RHR
UART2 receive holding register
UART2 transmit holding register
UART2 divisor latch low register
UART2 interrupt enable register
UART2 divisor latch high register
8
8
8
8
8
R
Undefined
Undefined
00h
†
UART2_THR
‡§
W
UART2_DLL
RW
RW
RW
†
UART2_IER
00h
‡§
UART2_DLH
00h
UART2 interrupt identification
register
†‡
0x00 8402h FFFB:0808
E101:0804
UART2_IIR
8
R
01h
†‡¶
§
0x00 8402h FFFB:0808
0x00 8402h FFFB:0808
0x00 8403h FFFB:080C
0x00 8404h FFFB:0810
0x00 8404h FFFB:0810
0x00 8405h FFFB:0814
0x00 8405h FFFB:0814
0x00 8406h FFFB:0818
0x00 8406h FFFB:0818
0x00 8406h FFFB:0818
0x00 8407h FFFB:081C
0x00 8407h FFFB:081C
0x00 8407h FFFB:081C
0x00 8408h FFFB:0820
E101:0804
E101:0804
E101:0806
E101:0808
E101:0808
E101:080A
E101:080A
E101:080C
E101:080C
E101:080C
E101:080E
E101:080E
E101:080E
E101:0810
UART2_FCR
UART2_EFR
UART2_LCR
UART2_MCR
UART2_XON1
UART2 FIFO control register
UART2 enhanced feature register
UART2 line control register
UART2 modem control register
UART2 XON1 register
8
8
8
8
8
8
8
8
8
8
8
8
8
8
W
00h
RW
RW
RW
RW
R
00h
00h
†‡¶
00h
§
00h
†‡
UART2_LSR
UART2 mode register
60h
§
UART2_XON2
UART2 XON2 register
RW
R
00h
†‡
UART2_MSR
UART2 modem status register
UART2 transmission control register
UART2 XOFF1 register
Undefined
0Fh
00h
#
UART2_TCR
UART2_XOFF1
†‡
RW
RW
RW
RW
RW
RW
§
UART2_SPR
UART2 scratchpad register
UART2 trigger level register
UART2 XOFF2 register
00h
#
UART2_TLR
00h
§
UART2_XOFF2
00h
UART2_MDR1
UART2 mode definition 1 register
07h
0x00 8409 − FFFB:0824 −
0x00840Dh FFFB:0834
Reserved
‡§
0x00 840Eh FFFB:0838
0x00 840Fh FFFB:083C
E101:081C
UART2_UASR
UART2 autobauding status register
Reserved
8
R
00h
UART2 supplementary control
register
0x00 8410h FFFB:0840
E101:0820
E101:0822
UART2_SCR
UART2_SSR
8
8
RW
R
00h
00h
UART2 supplementary status
register
0x00 8411h FFFB:0844
0x00 8412h FFFB:0848
0x00 8413h FFFB:084C
0x00 8414h FFFB:0850
Reserved
UART2_OSC_
UART2 12-/13-MHz oscillator select
register
E101:0826
E101:0828
8
8
W
R
00h
†
12M_SELV
UART2_MVR
UART2 module version register
−
†
‡
§
¶
#
Register is accessible when LCR[7] = 0 (normal operating mode)
Register is accessible when LCR[7] = 1 and LCR[7:0] ꢀ 0BFh
Register is accessible when LCR[7] = 0BFh
Register is write accessible when EFR[4] = 1
Register is accessible when EFR[4] = 1 and MCR[6] = 1
96
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−70. UART3/IrDA Registers
MPU BYTE
ADDRESS
(VIA MPUI)
DSP WORD
ADDRESS
MPU BYTE
ADDRESS
REGISTER
DESCRIPTION
NAME
ACCESS ACCESS
RESET
VALUE
WIDTH
TYPE
†
0x00 CC00h FFFB:9800
0x00 CC00h FFFB:9800
0x00 CC00h FFFB:9800
0x00 CC01h FFFB:9804
0x00 CC01h FFFB:9804
E101:9800
E101:9800
E101:9800
E101:9802
E101:9802
UART3_RHR
UART3 receive holding register
UART3 transmit holding register
UART3 divisor latch low register
UART3 interrupt enable register
UART3 divisor latch high register
8
8
8
8
8
R
Undefined
Undefined
00h
†
UART3_THR
‡§
W
UART3_DLL
RW
RW
RW
†
UART3_IER
00h
‡§
UART3_DLH
00h
UART3 interrupt identification
register
†‡
0x00 CC02h FFFB:9808
E101:9804
UART3_IIR
8
R
01h
†‡¶
§
0x00 CC02h FFFB:9808
0x00 CC02h FFFB:9808
0x00 CC03h FFFB:980C
0x00 CC04h FFFB:9810
0x00 CC04h FFFB:9810
0x00 CC05h FFFB:9814
0x00 CC05h FFFB:9814
0x00 CC06h FFFB:9818
E101:9804
E101:9804
E101:9806
E101:9808
E101:9808
E101:980A
E101:980A
E101:980C
UART3_FCR
UART3_EFR
UART3_LCR
UART3_MCR
UART3_XON1
UART3 FIFO control register
UART3 enhanced feature register
UART3 line control register
UART3 modem control register
UART3 XON1 register
8
8
8
8
8
8
8
8
W
RW
RW
RW
RW
R
00h
00h
00h
†‡¶
00h
§
00h
†‡
UART3_LSR
UART3 mode register
60h
§
UART3_XON2
UART3 XON2 register
RW
R
00h
†‡
UART3_MSR
UART3 modem status register
Undefined
UART3 transmission control
register
#
0x00 CC06h FFFB:9818
E101:980C
UART3_TCR
8
RW
0Fh
§
0x00 CC06h FFFB:9818
0x00 CC07h FFFB:981C
0x00 CC07h FFFB:981C
0x00 CC07h FFFB:981C
0x00 CC08h FFFB:9820
0x00 CC09h FFFB:9824
0x00 CC0Ah FFFB:9828
E101:980C
E101:980E
E101:980E
E101:980E
E101:9810
E101:9812
E101:9814
UART3_XOFF1
†‡
UART3 XOFF1 register
8
8
8
8
8
8
8
RW
RW
RW
RW
RW
RW
R
00h
00h
00h
00h
07h
00h
00h
UART3_SPR
UART3 scratchpad register
UART3 trigger level register
UART3 XOFF2 register
#
UART3_TLR
§
UART3_XOFF2
UART3_MDR1
UART3_MDR2
UART3_SFLSR
UART3 mode definition 1 register
UART3 mode definition register 2
UART3 status FIFO line status
register
0x00 CC0Ah FFFB:9828
0x00 CC0Bh FFFB:982C
0x00 CC0Bh FFFB:982C
0x00 CC0Ch FFFB:9830
0x00 CC0Ch FFFB:9830
0x00 CC0Dh FFFB:9834
0x00 CC0Dh FFFB:9834
0x00 CC0Eh FFFB:9838
0x00 CC0Fh FFFB:983C
0x00 CC0Fh FFFB:983C
0x00 CC10h FFFB:9840
E101:9814
E101:9816
E101:9816
E101:9818
E101:9818
E101:981A
E101:981A
E101:981C
E101:981E
E101:981E
E101:9820
UART3_TXFLL
UART3 transmit frame length low
8
8
8
8
8
8
8
8
8
8
8
W
R
00h
UART3_RESUME UART3 resume register
00h
UART3_TXFLH
UART3_SFREGL
UART3_RXFLL
UART3 transmit frame length high
W
00h
UART3 status FIFO low register
UART3 receive frame length low
R
Undefined
00h
W
UART3_SFREGH UART3 status FIFO high register
R
Undefined
00h
UART3_RXFLH
UART3 receive frame length high
UART3 BOF control register
UART3 auxiliary control register
UART3 divide 1.6 register
W
†
UART3_BLR
RW
RW
RW
RW
40h
†
UART3_ACREG
00h
‡§
UART3_DIV16
00h
UART3_SCR
UART3 supplementary control
register
00h
†
‡
§
¶
#
Register is accessible when LCR[7] = 0 (normal operating mode)
Register is accessible when LCR[7] = 1 and LCR[7:0] ꢀ 0BFh
Register is accessible when LCR[7] = 0BFh
Register is write accessible when EFR[4] = 1
Register is accessible when EFR[4] = 1 and MCR[6] = 1
97
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−71. MPU/DSP Shared GPIO Registers
DSP WORD
ADDRESS
MPU BYTE
ADDRESS
ACCESS
WIDTH
MPU
DSP
RESET
VALUE
REGISTER NAME
DATA_INPUT
DESCRIPTION
ACCESS ACCESS
0x00 F000h FFFC:E000
0x00 F002h FFFC:E004
Data Input Register
Data Output Register
16
R
R
0000h
DATA_OUTPUT
16
RW
RW
FFFFh
Direction Control
Register
0x00 F004h FFFC:E008
0x00 F006h FFFC:E00C
DIRECTION_CONTROL
16
16
RW
RW
RW
RW
FFFFh
Interrupt Control
Register
INTERRUPT_CONTROL
FFFFh
0x00 F008h FFFC:E010
0x00 F00Ah FFFC:E014
0x00 F00Ch FFFC:E018
INTERRUPT_MASK
INTERRUPT_STATUS
PIN_CONTROL
Interrupt Mask Register
Interrupt Status Register
Pin Control Register
16
16
16
RW
RW
RW
RW
RW
R
FFFFh
0000h
FFFFh
Table 3−72. MPU/DSP Shared Mailbox Registers
MPU
DSP
DSP WORD
ADDRESS
MPU BYTE
ADDRESS
ACCESS
WIDTH
RESET
VALUE
REGISTER NAME
DESCRIPTION
ACCESS ACCESS
TYPE
RW
RW
R
TYPE
R
0x00 F800h
0x00 F802h
0x00 F804h
0x00 F806h
0x00 F808h
0x00 F80Ah
0x00 F80Ch
0x00 F80Eh
0x00 F810h
0x00 F812h
0x00 F814h
0x00 F816h
FFFC:F000
FFFC:F004
FFFC:F008
ARM2DSP1
ARM2DSP1B
DSP2ARM1
MPU to DSP 1 Data Register
MPU to DSP 1 Command Register
DSP to MPU 1 Data Register
DSP to MPU 1 Command Register
DSP to MPU 2 Data Register
DSP to MPU 2 Command Register
MPU to DSP 1 Flag Register
DSP to MPU 1 Flag Register
DSP to MPU 2 Flag Register
MPU to DSP 2 Data Register
MPU to DSP 2 Command Register
MPU to DSP 2 Flag Register
16
16
16
16
16
16
16
16
16
16
16
16
0000h
0000h
0000h
0000h
0000h
0000h
undef
undef
undef
0000h
0000h
undef
R
RW
RW
RW
RW
R
FFFC:F00C DSP2ARM1B
R
FFFC:F010
FFFC:F014
FFFC:F018
DSP2ARM2
R
DSP2ARM2B
R
ARM2DSP1_FLAG
R
FFFC:F01C DSP2ARM1_FLAG
R
R
FFFC:F020
FFFC:F024
FFFC:F028
DSP2ARM2_FLAG
ARM2DSP2
R
R
RW
RW
R
R
ARM2DSP2B
R
FFFC:F02C ARM2DSP2_FLAG
R
98
SPRS197B
August 2002 − Revised August 2003
Functional Overview
3.17 Interrupts
Table 3−73. MPU Level 1 and Level 2 Interrupt Mappings
DEFAULT
SENSITIVITY
LEVEL 1
MAPPING
LEVEL 2
MAPPING
INTERRUPT
FUNCTION
Level 2 Interrupt handler FIQ
CAMERA_IF_INTERRUPT
Reserved
Level
IRQ_0
IRQ_1
IRQ_2
IRQ_3
IRQ_4
IRQ_5
−
−
−
−
FIQ Interrupt from Level 2 Handler
Camera Interface Interrupt
Reserved, keep masked
External FIQ Interrupt
Level
−
External FIQ
Edge
Edge
Edge
McBSP2 TX INT
−
McBSP2 Transmit Interrupt
McBSP2 Receive Interrupt
McBSP2 RX INT
−
Real-Time Data Exchange Interrupt
(for RTDX Emulation Tools)
IRQ_RTDX
Level
IRQ_6
−
IRQ_DSP_MMU_ABORT
IRQ_HOST_INT
IRQ_ABORT
Level
Level
Level
Level
Level
−
IRQ_7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
DSP MMU Abort Interrupt
IRQ_8
IRQ_9
IRQ_DSP_MAILBOX1
IRQ_DSP_MAILBOX2
Reserved
IRQ_10
IRQ_11
IRQ_12
IRQ_13
IRQ_14
IRQ_15
IRQ_16
IRQ_17
IRQ_18
IRQ_19
IRQ_20
IRQ_21
IRQ_22
IRQ_23
IRQ_24
IRQ_25
IRQ_26
IRQ_27
IRQ_28
IRQ_29
IRQ_30
IRQ_31
IRQ_0
DSP2ARM1 Mailbox Interrupt
DSP2ARM2 Mailbox Interrupt
Reserved, keep masked
IRQ_TIPB_BRIDGE_PRIVATE
IRQ_GPIO
Level
Level
Level
Edge
Level
−
TIPB Private Bridge Interrupt
MPU Interrupt for MPU-owned shared GPI
UART3 Interrupt
IRQ_UART3
IRQ_TIMER3
MPU Timer 3 Interrupt
IRQ_LB_MMU
Local Bus MMU Interrupt
Reserved
Reserved, keep masked
IRQ_DMA_CH0_CH6
IRQ_DMA_CH1_CH7
IRQ_DMA_CH2_CH8
IRQ_DMA_CH3
IRQ_DMA_CH4
IRQ_DMA_CH5
IRQ_DMA_CH_LCD
IRQ_TIMER1
Level
Level
Level
Level
Level
Level
Level
Edge
Edge
Level
Level
Edge
Level
Level
Edge
Edge
Edge
Edge
Level
System DMA Channel 0 and 6 Interrupt
System DMA Channel 1 and 7 Interrupt
System DMA Channel 2 and 8 Interrupt
System DMA Channel 3 Interrupt
System DMA Channel 4 Interrupt
System DMA Channel 5 Interrupt
System DMA LCD Channel Interrupt
MPU Timer 1 Interrupt
IRQ_WD_TIMER
IRQ_TIPB_BRIDGE_PUBLIC
IRQ_LOCAL_BUS_IF
IRQ_TIMER2
MPU Watchdog Timer Interrupt
TIPB Public Bridge Interrupt
Local Bus Interrupt
MPU Timer 2 Interrupt
IRQ_LCD_CTRL
FAC
LCD Controller Interrupt
IRQ_0
IRQ_1
IRQ_2
IRQ_3
IRQ_4
IRQ_5
Frame Adjustment Counter Interrupt
Keyboard Interrupt
KBD
IRQ_0
MICROWIRE_TX
MICROWIRE_RX
I2C
IRQ_0
Microwire Transmit Interrupt
Microwire Receive Interrupt
IRQ_0
2
IRQ_0
I C Interrupt
MPUIO
IRQ_0
MPUIO Interrupt
99
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−73. MPU Level 1 and Level 2 Interrupt Mappings (Continued)
DEFAULT
SENSITIVITY
LEVEL 1
MAPPING
LEVEL 2
MAPPING
INTERRUPT
FUNCTION
USB_HHC1
Reserved
Level
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_6
USB Host HHC1 Interrupt
−
IRQ_7
Reserved
−
IRQ_8
Reserved
−
IRQ_9
MCBSP3_TX_INT
MCBSP3_RX_INT
MCBSP1_TX_INT
MCBSP1_RX_INT
UART1
Edge
Edge
Edge
Edge
Level
Level
IRQ_10
IRQ_11
IRQ_12
IRQ_13
IRQ_14
IRQ_15
McBSP3 Transmit Interrupt
McBSP3 Receive Interrupt
McBSP1 Transmit Interrupt
McBSP1 Receive Interrupt
UART1 Interrupt
UART2
UART2 Interrupt
MCSI1 Combined
Transmit/Receive/Frame Error Interrupt
MCSI1_TX_RX_FE_INT
MCSI2_TX_RX_FE_INT
Level
Level
IRQ_0
IRQ_0
IRQ_16
IRQ_17
MCSI2 Combined
Transmit/Receive/Frame Error Interrupt
Reserved
−
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_0
IRQ_18
IRQ_19
IRQ_20
IRQ_21
IRQ_22
IRQ_23
IRQ_24
IRQ_25
IRQ_26
IRQ_27
IRQ_28
IRQ_29
Reserved, keep masked
Reserved
−
Reserved, keep masked
USB_CLNT_GENI_INT
1WIRE_INT
Level
Level
Edge
Level
Level
Edge
Level
−
USB Function General-Purpose Interrupt
1-Wire Interface Interrupt
TIMER_32K_INT
MMC_INT
32k Timer Interrupt
MMC/SD Interrupt
ULPD_INT
Ultra-Low Power Device module Interrupt
Real-Time Clock Periodic Timer Interrupt
Real-Time Clock Alarm Interrupt
RTC_PERIODIC_TIMER
RTC_ALARM
Reserved
DSPMMU_IRQ
USB_FUNC_IRQ_ISO_ON
Level
Level
DSP MMU Interrupt
USB Function Isochronous On Interrupt
USB Function Non-Isochronous On
Interrupt
USB_FUNC_IRQ_NONISO_ON
MCBSP2_RX_OVERFLOW_INT
Level
Edge
IRQ_0
IRQ_0
IRQ_30
IRQ_31
McBSP2 Receive Overflow Interrupt
100
SPRS197B
August 2002 − Revised August 2003
Functional Overview
Table 3−74. DSP Level 1 Interrupt Mappings
DSP
IFR/IMR
REGISTER
BIT
VECTOR
LOCATION
(BYTE
DSP
INTERRUPT
INTERRUPT
PRIORITY
FUNCTION
ADDRESS)
RESET
NMI
−
−
−
FFF00h
FFF08h
FFF10h
0
1
3
DSP Reset Interrupt
−
2
DSP Nonmaskable Interrupt
DSP Emulator/Test Interrupt
EMULATOR_TEST
INT2
FIQ Interrupt from DSP Level 2
Handler
LEVEL2_INTH_FIQ
INT3
3
FFF18h
5
TC_ABORT
INT4
INT5
INT6
4
5
6
FFF20h
FFF28h
FFF30h
6
7
9
Traffic Controller Abort Interrupt
MPU-to-DSP Mailbox 1 Interrupt
Unused, keep masked
MAILBOX_1 (ARM2DSP1)
Reserved
Interrupt for DSP-owned Shared
GPIO
GPIO
INT7
7
FFF38h
10
TIMER3
INT8
8
FFF40h
FFF48h
FFF50h
FFF58h
FFF60h
FFF68h
FFF70h
FFF78h
11
13
14
15
17
18
21
22
DSP Timer 3 Interrupt
DMA_CHANNEL_1
MPU
INT9
9
DSP DMA Channel 1 Interrupt
MPU Interrupt to DSP
INT10
INT11
INT12
INT13
INT14
INT15
10
11
12
13
14
15
Reserved
Unused, keep masked
UART3
UART Interrupt
WDGTIMER
DMA_CHANNEL_4
DMA_CHANNEL_5
DSP Watchdog Timer Interrupt
DSP DMA Channel 4 Interrupt
DSP DMA Channel 5 Interrupt
Interrupt for DMA EMIF interface to
Traffic Controller
EMIF
INT16
16
FFF80h
4
LOCAL_BUS
INT17
INT18
INT19
INT20
INT21
INT22
INT23
17
18
19
20
21
22
23
FFF88h
FFF90h
FFF98h
FFFA0h
FFFA8h
FFFB0h
FFFB8h
8
Local Bus Interrupt
DMA_CHANNEL_0
MAILBOX2 (ARM2DSP2)
DMA_CHANNEL_2
DMA_CHANNEL_3
TIMER2
12
16
19
20
23
24
DSP DMA Channel 0 Interrupt
MPU-to-DSP Mailbox 2 Interrupt
DSP DMA Channel 2 Interrupt
DSP DMA Channel 3 Interrupt
DSP Timer 2 Interrupt
TIMER1
DSP Timer 1 Interrupt
101
August 2002 − Revised August 2003
SPRS197B
Functional Overview
Table 3−75. DSP Level 2 Interrupt Mappings
DEFAULT
SENSITIVITY
LEVEL 1
MAPPING
LEVEL 2
MAPPING
INTERRUPT
FUNCTION
MCBSP3_TX
MCBSP3_RX
MCBSP1_TX
MCBSP1_RX
UART2
Edge
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
INT3
IRQ_0
IRQ_1
IRQ_2
IRQ_3
IRQ_4
IRQ_5
IRQ_6
IRQ_7
IRQ_8
IRQ_9
IRQ_10
IRQ_11
IRQ_12
IRQ_13
IRQ_14
IRQ_15
McBSP3 Transmit Interrupt
McBSP3 Receive Interrupt
McBSP1 Transmit Interrupt
McBSP1 Receive Interrupt
UART2 Interrupt
Edge
Edge
Edge
Level
Level
Level
Level
Level
Level
Level
Level
−
UART1
UART1 Interrupt
MCSI1_TX
MCSI1 Transmit Interrupt
MCSI1 Receive Interrupt
MCSI2 Transmit Interrupt
MCSI2 Receive Interrupt
MCSI1 Frame Error Interrupt
MCSI2 Frame Error Interrupt
Reserved, keep masked
Reserved, keep masked
Reserved, keep masked
Reserved, keep masked
MCSI1_RX
MCSI2_TX
MCSI2_RX
MCSI1_FRAME_ERROR_INT
MCSI2_FRAME_ERROR_INT
Reserved
Reserved
−
Reserved
−
Reserved
−
102
SPRS197B
August 2002 − Revised August 2003
Documentation Support
4
Documentation Support
Extensive documentation supports all OMAP platform of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the OMAP platform of dual-core processor devices:
•
•
•
Device-specific data sheets
Development-support tools
Hardware and software application reports
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding Texas Instruments (TI) OMAP and DSP products is also available on the Worldwide
Web at http://www.ti.com uniform resource locator (URL).
4.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a
final product and Texas Instruments reserves the right to change or discontinue these products without notice.
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TMS320 is a trademark of Texas Instruments.
103
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
OMAP5910 device.
All electrical and switching characteristics in this data manual are valid over the recommended operating
conditions unless otherwise specified.
5.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 5.2, Recommended Operating Conditions, is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. All supply voltage
values (core and I/O) are with respect V
.
SS
NOTE: The OMAP5910 device has undergone Charged Device Model Electrostatic Discharge
(ESD) testing, passing at the 500 V level. Human Body Model (HBM) ESD testing per
EIA/JESD22-A114 has also been performed. Test results indicate that the OMAP5910 passes
at a 500 V HBM (maximum) level. Caution in handling devices is advised.
This section provides the absolute maximum ratings for the OMAP5910 device.
Supply voltage range (core), CV ,CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 1.8 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
DD
DD1/2/3/4/A
Supply voltage range (I/O), DV
DD1/2/3/4/5
Input voltage range, V (12-MHz and 32-kHz oscillator) . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to CV
+ 0.5 V
+ 0.5 V
I
DD
DD
Input voltage range, V (standard LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV
I
Input voltage range, V (fail-safe LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
I
Input voltage range, V (USB transceivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV
+ 0.5 V
I
I
DD
2
Input voltage range, V (I C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Output voltage range, V (standard LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV
+ 0.5 V
O
DD
Output voltage range, V (fail-safe LVCMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
O
Output voltage range, V (USB transceivers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV
+ 0.5 V
O
O
DD
2
Output voltage range, V (I C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.5 V
Operating temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
C
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
104
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August 2002 − Revised August 2003
Electrical Specifications
5.2 Recommended Operating Conditions
MIN
1
NOM
1.1
MAX
1.675
1.675
3.6
UNIT
‡
Low Power Standby mode
CV
CV
DD
DD1/2/3/4/A
†
Device supply voltage, core
V
Active mode
1.525
2.5
1.6
DV
DV
Device supply voltage, I/O (Peripheral I/O)
Device supply voltage, I/O (USB transceiver)
2.75 or 3.3
3.3
V
V
DD1
DD2
3
3.6
§
Low-voltage range
1.65
2.5
1.8
1.95
3.6
Device supply voltage, I/O
(MCSI2, McBSP2, GPIO[9:8])
DV
DV
DV
V
V
V
DD3
DD4
DD5
§
High-voltage range
2.75 or 3.3
1.8
§
Low-voltage range
1.65
2.5
1.95
3.6
Device supply voltage, I/O
(SDRAM interface)
§
§
High-voltage range
2.75 or 3.3
1.8
§
Low-voltage range
1.65
2.5
2
Device supply voltage, I/O
(FLASH interface)
High-voltage range
2.75 or 3.3
3.6
¶
¶
CV
DV
− DV
− CV
Device supply voltage difference
Device supply voltage difference
Supply voltage, GND
1.65
2.6
V
V
V
DD
DD
DD
DD
V
SS
0
Standard LVCMOS
Fail-safe LVCMOS
USB.DP, DM (mode 1)
0.7 DV
DV
DV
DV
DV
DD
DD
DD
DD
DD
0.7 DV
DD
V
High-level input voltage, I/O
Low-level input voltage, I/O
V
V
IH
IL
2
2
I C
0.7 DV
DD
Standard LVCMOS
Fail-safe LVCMOS
USB.DP, DM (mode 1)
0
0
0.3 DV
0.3 DV
0.8
DD
DD
V
0
2
I C
0
0.3 DV
2.5
DD
USB.DP, DM (mode 2)
OSC1 and OSC32K pins
USB.DP, DM (mode 2)
0.8
V
V
Input voltage
V
I
CV
DD
Differential input voltage, I/O
200
mV
ID
2-mA drive strength buffers
4-mA drive strength buffers
8-mA drive strength buffers
−2
−4
−8
I
High-level output current
mA
OH
18.3-mA drive strength
buffers
−18.3
2-mA drive strength buffers
4-mA drive strength buffers
6-mA drive strength buffers
8-mA drive strength buffers
2
4
6
8
I
Low-level output current
mA
OL
18.3-mA drive strength
buffers
18.3
85
T
C
Operating case temperature
−40
°C
†
‡
§
¶
All core voltage supplies should be tied to the same voltage level (within 0.3 V).
Low Power Standby is defined as follows: the device is in Deep Sleep mode and LOW_PWR = 1. The device runs from 32 kHz clock in this mode.
High and low voltage ranges are selectable via software configuration.
In systems where the CV
and DV power supplies are ramped at generally the same time (within 500 ms of one another), there are no
DDx
DDx
specific power sequencing requirements for the supplies. The only sequencing requirement is that the maximum voltage difference between
CV and DV is not exceeded for greater than 500 ms. Likewise, if different voltages are used for the separate DV supplies, all DV
DD
DD DDx DDx
supplies should be ramp up to valid voltage levels within 500ms of one another.
105
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.3 Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Standard LVCMOS
DV
DV
= 3.3 V, I
= 3.3 V, I
= MAX
= MAX
0.8 DV
DD
DD
OH
DD
High-level output
voltage
Fail-safe LVCMOS
USB.DP, DM
0.8 DV
DV
V
OH
V
OH
DD
I
O
= −12 mA
− 0.5
DD
Standard LVCMOS
Fail-safe LVCMOS
USB.DP, DM
DV
DV
= 3.3 V, I
= MAX
= MAX
0.22 DV
DD
DD
DD
OL
= 3.3 V, I
0.22 DV
OL
DD
0.5
I
O
= 12 mA
Low-level output
voltage
V
OL
V
Fast mode at 6-mA load
Fast mode at 3-mA load
0.6
0.4
2
I C
Standard mode at 3-mA
load
0.4
Fail-safe LVCMOS inputs
without internal
pullups/pulldowns enabled
V = V MAX to V MIN
− 20
20
I
I
I
Other Inputs without internal
pullups/pulldowns enabled
V = V MAX to V MIN
−1
6
1
I
I
I
Input pins with 20-µA
pulldowns enabled
DV
V = V
I
= MAX,
DD
20
100
60
to V
SS
DD
I
I
Input current
µA
Input pins with 100-µA
pulldowns enabled
DV
= MAX,
DD
V = V
30
300
− 6
to V
SS DD
= MAX,
I
Input pins with 20-µA
pullups enabled
CV
DD
V = V
− 60
− 20
to V
DD
I
SS
Input pins with 100-µA
pullups enabled
DV
= MAX,
to V
SS DD
DD
V = V
− 20
− 20
− 100
− 30
20
I
I
I
Input current for outputs in high-impedance
Core voltage supply current, quiescent
µA
µA
OZ
Sum of CV
DDx
(Deep sleep mode
with CV = 1.6V)
currents.
115
50
DD
DDC(Q)
Sum of CV
currents.
DDx
(Deep sleep mode
with CV = 1.1V)
DD
Sum of CV
(Case 1 ).
currents
DDx
DDx
DDx
150
170
45
mA
mA
mA
mA
†
I
I
Core voltage supply current, active
DDC (A)
Sum of CV
currents
‡
(Case 2 ).
Sum of CV
currents (Case 3 ).
and DV
DDx
§
Core and I/O voltage supply current, active
DDCP(A)
Sum of CV and DV
DDx
DDx
6
¶
currents (Case 4 ).
USB.DP,DM
7
4
7
4
C
C
Input capacitance
Output capacitance
pF
pF
i
All other I/O pins
USB.DP,DM
O
All other I/O pins
†
‡
§
Case 1: MPU running OS, DSP running GSM Vocoder from internal memory, DSP MMU and all clock domains active, no LCD activity.
Case 2: Same conditions as Case 1 only DSP running from external memory with I-cache enabled.
Case 3: Only LCD activity (MPU and DSP idled with clocks off). LCD running 320x240 TFT at 70 Frames per second with frame buffer in internal
memory (DPLL at 120MHz).
¶
Case 4: Same as Case 3 only LCD running at 10 Frames per second with DPLL at 6MHz.
106
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
I
OL-test
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH-test
Where:
I
I
V
5 mA (all outputs)
300 µA (all outputs)
5 V
OL-test
OH-test
Load
=
=
=
=
C
10 pF maximum and 5 pF minimum for EMIFF (50 pF maximum and 5 pF minimum for EMIFS and all other I/O pads).
T
Figure 5−1. 3.3-V Test Load Circuit
5.4 Package Thermal Resistance Characteristics
Table 5−1 provides the thermal resistance characteristics for the recommended package types used on the
OMAP5910 device.
Table 5−1. Thermal Resistance Characteristics
†
R
(°C/W)
R
(°C/W)
BOARD TYPE
ΘJA
34.01
63.26
ΘJC
7.43
7.13
High-K
Low-K
†
Board types are as defined by JEDEC. Reference JEDEC Standard JESD51−9,
Test Boards for Area Array Surface Mount Package Thermal Measurements.
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
107
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.6 Clock Specifications
This section provides the timing requirements and switching characteristics for the OMAP5910 system clock
signals.
5.6.1 32-kHz Oscillator and Input Clock
The 32.768-kHz clock signal (often abbreviated to 32-kHz) may be supplied by either the on-chip 32-kHz
oscillator (requiring an external crystal) or an external CMOS signal. The state of the CLK32K_CTRL pin
determines which is used.
The on-chip oscillator requires an external 32.768-kHz crystal connected across the OSC32K_IN and
OSC32K_OUT pins. The connection of the required circuit, consisting of the crystal and two load capacitors,
is shown in Figure 5−2. The load capacitors, C and C , should be chosen such that the equation below is
1
2
satisfied (recommended values are C = C = 10 pF). C in the equation is the load specified for the crystal.
1
2
L
All discrete components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (OSC32K_IN and OSC32K_OUT) and to the V pin closest to the oscillator pins
SS
(GZG ball V12 or GDY ball F6).
NOTE: The 32.768-kHz oscillator is powered by the CV
of using the on-chip oscillator, care must be taken that the voltage level driven onto the OSC32K_IN and
supply. If an external clock source is used instead
DD
OSC32K_OUT pins is no greater than the CV
voltage level.
DD
C1C2
(C1 ) C2)
CL +
OSC32K_IN
OSC32K_OUT
V
SS
Crystal
32.768 kHz
C1
C2
Figure 5−2. 32-kHz Oscillator External Crystal
Table 5−2 shows the switching characteristics of the 32-kHz oscillator and Table 5−3 shows the input
requirements of the 32-kHz clock input.
Table 5−2. 32-kHz Oscillator Switching Characteristics
PARAMETER
MIN
TYP
200
MAX
UNIT
ms
Start-up time (from power up until oscillating at stable frequency of 32.768 kHz)
800
I , active current consumption
DDA
4
µA
Oscillation frequency
32.768
kHz
108
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
Table 5−3. 32-kHz Input Clock Timing Requirements
NO.
CK1
CK2
CK3
CK4
CK5
MIN
NOM
MAX
UNIT
kHz
ns
t
t
t
Frequency
Fall time
32.768
cyc
25
25
f
Rise time
ns
r
Duty cycle (high-to-low ratio)
Frequency stability
30%
−70
70%
70
%
ppm
CK3
CK2
CK1
CLK32K_IN
Figure 5−3. 32-kHz Input Clock
5.6.2 Base Oscillator (12 MHz or 13 MHz) and Input Clock
The internal base system oscillator is enabled following a device reset. The oscillator requires an external
crystal to be connected across the OSC1_IN and OSC1_OUT pins. If the internal oscillator is not used
(configured in software), an external clock source must be applied to the OSC1_IN pin and the OSC1_OUT
pin must be left unconnected. Because the internal oscillator can be used as a clock source to the OMAP
DPLL, the 12- or 13-MHz crystal oscillation frequency can be multiplied to generate the DSP clock, MPU clock,
traffic controller clock.
The crystal must be in fundamental-mode operation, and parallel resonant, with a maximum effective series
resistance of 60 Ω maximum. The connection of the required circuit, consisting of the crystal and two load
capacitors, is shown in Figure 5−4. The load capacitors, C and C , must be chosen such that the equation
1
2
below is satisfied (recommended values are C = C = 10 pF). C in the equation is the load specified for the
1
2
L
crystal. All discrete components used to implement the oscillator circuit must be placed as close as possible
to the associated oscillator pins (OSC1_IN and OSC1_OUT) and to the V pins closest to the oscillator pins
SS
(GZG balls AA1/Y3 or GDY balls E13/K9).
NOTE: The base oscillator is powered by the CV
supply. If an external clock source is used instead of using
DD
the on-chip oscillator, care must be taken that the voltage level driven onto the OSC1_IN pin is no greater than
the CV voltage level.
DD
C1C2
(C1 ) C2)
CL +
OSC1_IN
OSC1_OUT
12 or 13 MHz crystal
C2
C1
Figure 5−4. Internal System Oscillator External Crystal
109
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
If USB host function is used, it is recommended that a very low PPM crystal (≤ 50 ppm) be used for the
12- or 13-MHz oscillator circuit. If the USB host function is not used, then a crystal of ≤ 180 ppm is
recommended. When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 5−4 shows the switching characteristics of the base oscillator.
Table 5−4. Base Oscillator Switching Characteristics
PARAMETER
MIN
TYP
1
MAX
UNIT
ms
Start-up time (from power up until oscillating at stable frequency of 12 or 13 MHz)
4
I , active current consumption
DDA
350
µA
Oscillation frequency
12 or 13
MHz
5.6.3 Internal Clock Speed Limitations
Table 5−5 provides a summary of the maximum frequencies that each clock domain may be configured to run
on the OMAP5910 device
Table 5−5. Internal Clock Speed Limitations
CLOCK
MPU (CLKM1)
DSP (CLKM2)
TC (CLKM3)
DPLL1
MAX OPERATING FREQUENCY
UNIT
MHz
MHz
MHz
MHz
150
150
75
150
All clock domains must be derived from the same DPLL1 frequency setting; therefore, the following conditions
must be satisfied where ‘m’, ‘n’, and ‘o’ are each equal to either 1, 2, 4, or 8:
•
•
•
MPU frequency = (DPLL1 clock frequency) / m
DSP frequency = (DPLL1 clock frequency) / n
TC frequency = (DPLL1 clock frequency) / o
For example, the following configuration is valid:
MPU/DSP/TC = 150 MHz/150 MHz/75 MHz, where m = n = 1 and o = 2
•
110
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
5.7 Reset Timings
This section provides the timing requirements for the OMAP5910 hardware reset signals.
5.7.1 OMAP5910 Device Reset
The PWRON_RESET signal is the active-low asynchronous reset input responsible for the reset of the entire
OMAP5910 device. When using an external crystal to supply the 32-kHz system clock, PWRON_RESET must
be asserted low a minimum of two 32-kHz clock cycles longer than the worst-case start-up time of the 32-kHz
oscillator after stable power supplies (see Figure 5−5). If an external CMOS input signal is used to source
32 kHz, PWRON_RESET must be asserted low a minimum of two 32-kHz clock cycles after stable power
supplies. See Table 5−6 and Table 5−7.
Table 5−6. OMAP5910 Device Reset Timing Requirements
NO.
MIN
MAX
UNIT
RS1
t
Pulse duration, PWRON_RESET low
800
ms
w(PWRON_RST)
†
Table 5−7. OMAP5910 Device Reset Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
RS2
t
Delay time, PWRON_RESET high to RST_OUT high
T + 10
µs
d(PWRONH-RSTH)
†
P = period of 32-kHz clock, C = Value of ULPD wakeup time setup register, SETUP_ULPD1_REG (Default 03FFh), T = P*C
CV
DDx
DV
DDx
RS1
2 Cycles
Worst-case Oscillator Start-up Time
OSC32K_IN
PWRON_RESET
RST_OUT
RS2
Figure 5−5. Device Reset Timings
111
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.7.2 OMAP5910 MPU Core Reset
The MPU_RST signal is the active-low asynchronous input responsible for the reset of the OMAP5910 MPU
core. Stable power supplies are assumed prior to MPU_RST assertion. Figure 5−6 illustrates the behavior of
MPU_RST and RST_OUT. In Figure 5.6, a logic high level is assumed on the PWRON_RESET input. In the case
where an application ties the PWRON_RESET and MPU_RST together, the behavior described in
Section 5.7.1, OMAP5910 Device Reset, will override. See Table 5−8 and Table 5−9.
Table 5−8. MPU_RST Timing Requirements
NO.
M3
MIN
MAX
UNIT
t
Pulse duration, MPU_RST low
50
µs
w(MPU_RST)
†
Table 5−9. MPU_RST Switching Characteristics
PARAMETER
NO.
MIN
MAX
UNIT
M1
t
Delay time, MPU_RST low to RST_OUT low
1
µs
d(MPUL−RSTL)
MPU_RST asserted during
OMAP5910 awake state
10
M2
t
Delay time, MPU_RST high to RST_OUT high
µs
d(MPUH−RSTH)
MPU_RST asserted during
OMAP5910 deep sleep state
T + 10
†
P = period of 32-kHz clock, C = Value of ULPD wakeup time setup register, SETUP_ULPD1_REG (Default 03FFh), T = P*C
M3
MPU_RST
M1
M2
RST_OUT
Figure 5−6. MPU Core Reset Timings
112
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
5.8 External Memory Interface Timing
5.8.1 EMIFS/Flash Interface Timing
Table 5−10 and Table 5−11 assume testing over recommended operating conditions (see Figure 5−7 through
Figure 5−11).
Table 5−10. EMIFS/Flash Interface Timing Requirements
DV
= 1.8 V DV
= 2.75 V DV
= 3.3 V
DD5
DD5
DD5
Nominal
Nominal
Nominal
NO.
UNIT
MIN MAX
MIN MAX
MIN MAX
†
Async modes (RT = 0)
18
2
18
2
15
2
ns
ns
ns
ns
Setup time, read data valid
before FLASH.CLK high
F6
F7
t
su(DV−CLKH)
†
Sync Modes (RT = 1)
†
Async modes (RT = 0)
29
2
29
2
26
2
Hold time, read data valid
after FLASH.CLK high
t
h(CLKH−RDV)
†
Sync Modes (RT = 1)
†
When the RT field in the EMIFS configuration register is set, input data is retimed to the external FLASH.CLK signal. RT=1 setting is only valid
in synchronous modes (protocols 1 and 2). For async modes, t ) with respect to internal FLASH.CLK is given as 0 to allow for other
d(CLKH−CSV
signals reference to FLASH.CSx. The external FLASH.CLK is disabled for async modes.
113
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
Table 5−11. EMIFS/Flash Interface Switching Characteristics
DV
= 1.8 V
DD5
Nominal
DV
= 2.75 V
DD5
Nominal
DV
= 3.3 V
DD5
Nominal
NO.
F1
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
async
modes
Delay time,
0
0
−1
−9
−1
−9
−1
−7
0
0
†
†
†
†
†
†
†
†
†
†
FLASH.CLK high
to FLASH.CSx
transition
t
ns
d(CLKH−CSV)
sync
modes
−1
−9
12
2
4
2
4
6
9
6
9
1
3
1
4
1
4
7
7
7
7
16
7
11
2
4
2
4
6
8
6
8
1
3
1
3
1
3
7
6
7
6
15
6
−1
10
2
3
2
3
6
7
6
7
1
2
1
3
1
3
7
6
7
6
14
6
async
modes
Delay time,
FLASH.CLK high
to FLASH.BEx
valid
−9
−1
−9
−1
−7
0
F2
F3
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKH−BEV)
sync
modes
−1
async
modes
Delay time,
FLASH.CLK high
to FLASH.BEx
invalid
−9
t
d(CLKH−BEIV)
sync
modes
−1
async
modes
−7
Delay time,
FLASH.CLK high
to address valid
F4
t
d(CLKH−AV)
d(CLKH−AIV)
sync
modes
−1
async
modes
−7
−7
−1
−7
−1
−9
−1
−8
−1
−8
−1
−14
−3
−15
−3
Delay time,
FLASH.CLK high
to address invalid
F5
t
sync
modes
−1
async
modes
Delay time,
−10
−1
−10
−1
FLASH.CLK high
to FLASH.ADV
transition
F8
t
d(CLKH−ADV)
sync
modes
async
modes
Delay time,
−8
−8
FLASH.CLK high
to FLASH.OE
transition
F9
t
d(CLKH−OEV)
sync
modes
−1
−1
async
modes
Delay time,
−8
−8
FLASH.CLK high
to FLASH.WE
transition
F12
F13
F14
t
d(CLKH−WEV)
sync
modes
−1
−1
async
modes
−15
−4
−15
−3
Delay time,
FLASH.CLK high
to write data valid
t
d(CLKH−WDV)
sync
modes
async
modes
Delay time,
FLASH.CLK high
to write data
invalid
−15
−4
−15
−3
t
d(CLKH−WDIV)
sync
modes
Delay time, FLASH.CLK high
to data bus high-impedance
F15
F16
F17
t
ns
ns
ns
d(CLKH−DHZ)
†
Delay time, FLASH.CLK high
to data bus driven
t
−4
−3
−3
d(CLKH−DLZ)
Delay time, FLASH.CLK high
to FLASH.BAA transition
†
t
−1 + 0.5P
8 + 0.5P −1 + 0.5P 7.5 + 0.5P −1 + 0.5P 7.5 + 0.5P
d(CLKH−BAAV)
‡
†
Data is referenced to the internal FLASH.CLK. For async modes, t
signals reference to FLASH.CSx. The external FLASH.CLK is disabled for async modes.
P = period of undivided Traffic Controller clock regardless of FLASH.CLK divider configuration
) with respect to internal FLASH.CLK is given as 0 to allow for other
d(CLKH−CSV
‡
114
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
‡
N cycles
†
FLASH.CLK
(internal)
F1
F2
F4
F1
F3
FLASH.CSx
FLASH.BE[1:0]
FLASH.A[24:1]
Valid
A1
F5
F6
F7
FLASH.D[15:0]
FLASH.ADV
D1
F8
F9
F8
F9
FLASH.OE
FLASH.WE
†
‡
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to
express relative timings.
Number of cycles is configurable via EMIFS setup registers.
Figure 5−7. Asynchronous Memory Read Timing
115
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
‡
N cycles
‡
M cycles
†
FLASH.CLK
(internal)
F1
F2
F4
F1
F3
FLASH.CSx
Valid
A1
FLASH.BE[1:0]
FLASH.A[24:1]
F5
F6
F6
F7
F7
D1 upper
FLASH.D[15:0]
FLASH.ADV
D1 lower
F8
F9
F8
F9
FLASH.OE
FLASH.WE
†
‡
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to
express relative timings.
Number of cycles is configurable via EMIFS setup registers.
Figure 5−8. Asynchronous 32-Bit Read
116
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
‡
P cycles
‡
P cycles
‡
‡
M cycles
P cycles
†
FLASH.CLK
(internal)
F1
F1
FLASH.CSx
F2
F4
F3
FLASH.BE[1:0]
FLASH.A[24:3]
Valid
A1
F5
F5
F7
F4
F4
F5
FLASH.A[2:1]
Word 0
Word 1
Word 2
D3
Word 3
F6
F6
F7
D2
FLASH.D[15:0]
FLASH.ADV
D1
D4
F8
F9
F8
F9
FLASH.OE
FLASH.WE
†
‡
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to
express relative timings.
Number of cycles is configurable via EMIFS setup registers.
Figure 5−9. Asynchronous Read − Page Mode ROM
117
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
Wait-states
M cycles
WE width
P cycles
ADV width
CS hold
Q cycles
‡
‡
‡
‡
N cycles
†
FLASH.CLK
(internal)
F1
F2
F4
F1
F3
FLASH.CSx
Valid
FLASH.BE[1:0]
FLASH.A[24:1]
F5
A1
D1
F13
F15
F14
F16
F8
FLASH.D[15:0]
FLASH.ADV
F8
FLASH.OE
FLASH.WE
F12
F12
†
‡
FLASH.CLK is not driven during this mode of operation. The signal shown represents the internal FLASH.CLK signal given as a reference to
express relative timings.
Number of cycles is configurable via EMIFS setup registers.
Figure 5−10. Asynchronous Memory Write Timing
118
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
ADV width
‡
N cycles
Wait-states
‡
CLK start
M cycles
‡
Q cycles
†
FLASH.CLK
(external)
F1
F2
F4
F1
F3
FLASH.CSx
FLASH.BE[1:0]
FLASH.A[24:1]
Valid
F5
A1
F7
D2
F7
F6
F8
F6
D3
FLASH.D[15:0]
FLASH.ADV
FLASH.BAA
D1
D4
F8
F9
F17
F17
F9
FLASH.OE
FLASH.WE
†
‡
FLASH.CLK is only driven during the active portion of the cycle. For reference, the dashed line shows FLASH.CLK as if it were continuous.
Number of cycles is configurable via EMIFS setup registers.
Figure 5−11. Synchronous Burst Read
119
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.8.2 EMIFF/SDRAM Interface Timing
Table 5−12 and Table 5−13 assume testing over recommended operating conditions (see Figure 5−12
through Figure 5−17).
†
Table 5−12. EMIFF/SDRAM Interface Timing Requirements
DV
= 1.8 V
DD4
Nominal
DV
= 2.75 V
DD4
Nominal
DV
= 3.3 V
DD4
Nominal
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, read data valid before
SDRAM.CLK high
SD7
SD8
t
t
2
2
2
ns
ns
su(DV-CLKH)
Hold time, read data valid after
SDRAM.CLK high
1
1
1
h(CLKH-DV)
†
Timing requirements are with the SD_RET field equal to 1 in the EMIFF configuration register.
Table 5−13. EMIFF/SDRAM Interface Switching Characteristics
DV
= 1.8 V
DD4
Nominal
DV
= 2.75 V
DD4
Nominal
DV = 3.3 V
DD4
Nominal
NO.
PARAMETER
UNIT
MIN
MAX
MIN MAX
MIN MAX
‡
‡
‡
H
SD1
SD2
t
t
Cycle time, SDRAM.CLK
H
H
ns
ns
c(CLK)
Pulse duration, SDRAM.CLK high/low
2.5
1.5
2.5
1.5
2.5
w(CLK)
Delay time, SDRAM.CLK high to
SDRAM.DQMx valid
SD3
SD4
t
t
t
t
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
1.5
9
9
9
9
9
9
9
9
9
9
9
9
9
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKH-DQMV)
d(CLKH-DQMIV)
d(CLKH-AV)
Delay time, SDRAM.CLK high to
SDRAM.DQMx invalid
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Delay time, SDRAM.CLK high to
SDRAM.A[12:0] address valid
SD5
Delay time, SDRAM.CLK high to
SDRAM.A[12:0] address invalid
SD6
d(CLKH-AIV)
Delay time, SDRAM.CLK high to
SDRAM.CAS low
SD9
t
d(CLKH-SDCASL)
Delay time, SDRAM.CLK high to
SDRAM.CAS high
SD10
SD11
SD12
SD13
SD14
SD15
SD16
SD17
SD18
t
d(CLKH-SDCASH)
Delay time, SDRAM.CLK high to
SDRAM.D[15:0] data valid
t
d(CLKH-DV)
Delay time, SDRAM.CLK high to
SDRAM.D[15:0] data invalid
t
t
d(CLKH-DIV)
d(CLKH-SDWEL)
Delay time, SDRAM.CLK high to
SDRAM.WE low
Delay time, SDRAM.CLK high to
SDRAM.WE high
t
d(CLKH-SDWEH)
Delay time, SDRAM.CLK high to
SDRAM.BA[1:0] valid
t
d(CLKH-BAV)
d(CLKH-BAIV)
d(CLKH-RASL)
d(CLKH-RASH)
Delay time, SDRAM.CLK high to
SDRAM.BA[1:0] invalid
t
t
t
Delay time, SDRAM.CLK high to
SDRAM.RAS low
Delay time, SDRAM.CLK high to
SDRAM.RAS high
‡
H = 1/2 CPU cycle.
120
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
READ
READ
BURST TERMINATE
SD2
SDRAM.CLK
SDRAM.CKE
SD2
SD1
SD3
SD5
SDRAM.DQMx
SDRAM.A[12:0]
SDRAM.BA[1:0]
SD6
CA2
CA1
SD15
Bank Address
SD16
SD7
SD8
D2
D1
SDRAM.D[15:0]
SDRAM.RAS
SD9
SD10
SDRAM.CAS
SDRAM.WE
Figure 5−12. 32-Bit (2 x 16-Bit) SDRAM RD (Read) Command (Active Row)
WRITE
BURST
WRITE
SDRAM.CLK
SDRAM.CKE
TERMINATE
SD3
BE1
SD15
CA1
SD4
BE2
SDRAM.DQMx
SD16
CA2
SDRAM.A[12:0]
SDRAM.BA[1:0]
SD15
SD16
Bank Address
SD12
D2
SD11
D1
SDRAM.D[15:0]
SDRAM.RAS
SDRAM.CAS
SD10
SD9
SD13
SD14
SDRAM.WE
Figure 5−13. 32-Bit (2 x 16-Bit) SDRAM WRT (Write) Command (Active Row)
121
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
ACTV
SDRAM.CLK
SDRAM.CKE
SDRAM.DQMx
SD5
SDRAM.A[12:0]
Row Address
Bank Activate
SD15
SDRAM.BA[1:0]
SDRAM.D[15:0]
SD17
SD18
SDRAM.RAS
SDRAM.CAS
SDRAM.WE
Figure 5−14. SDRAM ACTV (Activate Row) Command
DCAB
SDRAM.CLK
SDRAM.CKE
SDRAM.DQMx
SDRAM.A[12:11, 9:0]
SDRAM.BA[1:0]
SDRAM.D[15:0]
SD5
SD6
SDRAM.A[10]
SD17
SD18
SDRAM.RAS
SDRAM.CAS
SD13
SD14
SDRAM.WE
Figure 5−15. SDRAM DCAB (Precharge/Deactivate Row) Command
122
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
REFR
SDRAM.CLK
SDRAM.CKE
SDRAM.DQMx
SDRAM.A[12:11, 9:0]
SDRAM.BAx
SDRAM.D[15:0]
SDRAM.A[10]
SD5
SD6
SD17
SD18
SDRAM.RAS
SD9
SD10
SDRAM.CAS
SDRAM.WE
Figure 5−16. SDRAM REFR (Refresh) Command
MRS
SDRAM.CLK
SDRAM.CKE
SDRAM.DQMx
SD5
SD6
SDRAM.A[9:0]
MRS Value
SDRAM.BA[1:0]
SDRAM.D[15:0]
SDRAM.A10
SD5
SD6
SD17
SD18
SDRAM.RAS
SD9
SD10
SD14
SDRAM.CAS
SDRAM.WE
SD13
Figure 5−17. SDRAM MRS (Mode Register Set) Command
123
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.9 Multichannel Buffered Serial Port (McBSP) Timings
5.9.1 McBSP Transmit and Receive Timings
Table 5−14 and Table 5−15 assume testing over recommended operating conditions (see Figure 5−18 and
Figure 5−19). In Table 5−14 and Table 5−15, “ext” indicates that the device pin is configured as an input (slave)
driven by an external device and “int” indicates that the pin is configured as an output (master).
†‡
Table 5−14. McBSP Timing Requirements
NO.
M11
M12
MIN
2P
MAX UNIT
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
ns
c(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
0.45P
ns
12
w(CKRX)
McBSP1
McBSP2
CLKR/X ext,
MCBSP2.FS
R/X ext
12
M13
M14
t
Rise time, CLKR/X, MCBSP2.FSR/X
Fall time, CLKR/X, MCBSP2.FSR/X
ns
ns
r
f
McBSP3
McBSP1
CLKR/X ext
CLKR/X ext
6
12
CLKR/X ext,
MCBSP2.FS
R/X ext
McBSP2
McBSP3
12
6
t
CLKR/X ext
§
CLKX int
25
31
25
7
McBSP1
(FSX)
§
CLKX ext
CLKR int
Setup time, external receiver frame sync (FSR/X)
high before CLKR/X low
McBSP2
(FSR)
M15
M16
M17
t
ns
ns
ns
su(FRH-CKRL)
§
CLKR ext
§
CLKX int
24
15
3
McBSP3
(FSX)
§
§
CLKX ext
§
CLKX int
CLKX ext
CLKR int
McBSP1
(FSX)
16
3
Hold time, external receiver frame sync (FSR/X) high McBSP2
t
h(CKRL-FRH)
§
after CLKR/X low
(FSR)
CLKR ext
3
§
CLKX int
CLKX ext
13
13
21
3
McBSP3
(FSX)
§
§
§
CLKX int
CLKX ext
CLKR int
McBSP1
McBSP2
McBSP3
22
3
§
Setup time, DR valid before CLKR/X low
t
su(DRV-CKRL)
CLKR ext
§
CLKX int
CLKX ext
19
10
§
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡
§
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP 2. Base frequency is 12
or 13 MHz.
For McBSP1 and McBSP2, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled
via software configuration.
124
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
†‡
Table 5−14. McBSP Timing Requirements (Continued)
NO.
M18
MIN
3
MAX UNIT
§
CLKX int
McBSP1
McBSP2
McBSP3
McBSP1
McBSP2
McBSP3
McBSP1
McBSP2
McBSP3
§
CLKX ext
3
CLKR int
3
§
t
t
t
Hold time, DR valid after CLKR/X low
ns
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
CLKR ext
3
§
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
3
§
3
30
25
28
27
28
27
3
M19
Setup time, external FSX high before CLKX low
ns
10
3
M20
Hold time, external FSX high after CLKX low
ns
3
3
3
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡
§
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP 2. Base frequency is 12
or 13 MHz.
For McBSP1 and McBSP2, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled
via software configuration.
125
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
†‡§
Table 5−15. McBSP Switching Characteristics
NO.
PARAMETER
MIN
MAX UNIT
Delay time, CLKS high to CLKR/X high for internal
McBSP1
M0
t
CLKR/X int
2
33
ns
d(CKSH-CKRXH)
CLKR/X generated from CLKS input
M1
M2
M3
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
2P
0.45D
0.45C
−1
−3
−4
7
ns
ns
ns
ns
ns
c(CKRX)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
0.55D
0.55C
13
24
13
39
4
w(CKRXH)
w(CKRXL)
M4
t
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
McBSP2
McBSP1
McBSP2
McBSP3
McBSP1
McBSP2
McBSP3
McBSP1
McBSP2
McBSP3
d(CKRH-FRV)
−1
2
M5
t
ns
ns
ns
d(CKXH-FXV)
24
9
−1
2
37
7
−2
7
40
10
27
10
16
28
25
30
27
10
27
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted
when in Data Delay 0 (XDATDLY=00b) mode.
0
M7
t
d(CKXH-DXV)
3
−1
1
FSX ext
¶
Delay time, FSX high to DX valid
FSX int
M9
t
d(FXH-DXV)
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
FSX ext
FSX int
FSX ext
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
‡
§
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
T=CLKRX period = (1 + CLKGDV) * P
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
Only DXENA=0 is supported for all OMAP5910 McBSPs.
¶
126
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
MCBSP1.CLKS
M1, M11
M2, M12
M3, M12
M0
M13
†
CBSPx.CLKR/X
M4
M4
M14
MCBSP2.FSR (int)
M13
M14
†
MCBSPx.FSR/X
(ext)
M15
M16
M18
M17
MCBSPx.DR
(RDATDLY=00b)
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
M18
MCBSPx.DR
(RDATDLY=01b)
Bit (n−1)
(n−3)
(n−2)
M17
M18
MCBSPx.DR
(RDATDLY=10b)
Bit (n−1)
†
For McBSP1 and McBSP3, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections enabled
via software configuration. The M13 and M14 descriptors are applicable only to McBSP2.
Figure 5−18. McBSP Receive Timings
M1, M11
M2, M12
M13
M14
M3, M12
MCBSPx.CLKX
M5
M5
MCBSPx.FSX (int)
M19
M20
MCBSPx.FSX
(ext)
M9
M7
M7
MCBSPx.DX
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(n−4)
(n−3)
(n−2)
(XDATDLY=00b)
M7
Bit (n−1)
MCBSPx.DX
(XDATDLY=01b)
Bit 0
Bit 0
M7
Bit (n−1)
MCBSPx.DX
(XDATDLY=10b)
Figure 5−19. McBSP Transmit Timings
127
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.9.2 McBSP as SPI Master or Slave Timing
Table 5−16 to Table 5−23 assume testing over recommended operating conditions (see Figure 5−20 through
Figure 5−23).
†‡
Table 5−16. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
15
2
MAX
M30
M31
t
t
Setup time, MCBSPx.DR valid before MCBSPx.CLKX low
Hold time, MCBSPx.DR valid after MCBSPx.CLKX low
2 − 6P
6 + 6P
21
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
McBSP1
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX high
M32
M33
t
McBSP2
McBSP3
5
ns
ns
su(BFXL-CKXH)
10
t
Cycle time, MCBSPx.CLKX
2P
16P
c(CKX)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
†‡
Table 5−17. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
¶
#
M24
M25
M26
M29
t
t
t
t
Hold time, MCBSPx.FSX low after MCBSPx.CLKX low
0.45T
0.45C
−1
0.55T
0.55C
7
ns
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
d(FXL-DXV)
Delay time, MCBSPx.FSX low to MCBSPx.CLKX high
Delay time, MCBSPx.CLKX high to MCBSPx.DX valid
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
3P + 2
5P+ 18
4P + 18
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
CLKX period = (1 + CLKGDV) * P
T
=
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (MCBSPx.CLKX).
#
M33
MSB
LSB
M32
CLKX
FSX
M24
M25
M29
M26
(n-2)
DX
DR
Bit 0
Bit(n-1)
(n-3)
(n-4)
M30
M31
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 5−20. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
128
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
†‡
Table 5−18. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
15
2
MAX
M39
M40
t
t
Setup time, MCBSPx.DR valid before MCBSPx.CLKX high
Hold time, MCBSPx.DR valid after MCBSPx.CLKX high
2 − 6P
6 +6P
21
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
McBSP1
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX high
M41
M42
t
t
McBSP2
McBSP3
5
ns
ns
su(FXL-CKXH)
10
Cycle time, MCBSPx.CLKX
2P
16P
c(CKX)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
†‡
Table 5−19. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
M34
M35
M36
M38
t
t
t
t
Hold time, MCBSPx.FSX low after MCBSPx.CLKX low
0.45C 0.55C
0.45T 0.55T
ns
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
d(FXL-DXV)
#
Delay time, MCBSPx.FSX low to MCBSPx.CLKX high
Delay time, MCBSPx.CLKX low to MCBSPx.DX valid
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
−1
7
3P + 2
5P + 18
4P + 18
D +20
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
CLKX period = (1 + CLKGDV) * P
T
=
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (MCBSPx.CLKX).
M42
MSB
LSB
M41
MCBSPx.CLKX
M35
M34
MCBSPx.FSX
MCBSPx.DX
MCBSPx.DR
M36
(n-2)
M38
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
M39
M40
(n-2)
(n-3)
(n-4)
Figure 5−21. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
129
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
†‡
Table 5−20. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
MIN
UNIT
MIN
15
2
MAX
M49
M50
t
t
Setup time, MCBSPx.DR valid before MCBSPx.CLKX high
Hold time, MCBSPx.DR valid after MCBSPx.CLKX high
McBSP1
2 − 2P
6 + 6P
21
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX low
M51
M52
t
t
McBSP2
McBSP3
5
ns
ns
su(FXL-CKXL)
10
Cycle time, MCBSPx.CLKX
2P
16P
c(CKX)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
†‡
Table 5−21. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
M43
M44
M45
M48
t
t
t
t
Hold time, MCBSPx.FSX low after MCBSPx.CLKX high
0.45T 0.55T
0.45D 0.55D
ns
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
d(FXL-DXV)
#
Delay time, MCBSPx.FSX low to MCBSPx.CLKX low
Delay time, MCBSPx.CLKX low to MCBSPx.DX valid
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
−1
7
3P + 2
5P + 18
4P + 18
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
CLKX period = (1 + CLKGDV) * P
T
=
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (MCBSPx.CLKX).
#
M52
MSB
M51
LSB
MCBSPx.CLKX
MCBSPx.FSX
M43
M44
M48
M45
MCBSPx.DX
MCBSPx.DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M49
M50
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5−22. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
130
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
†‡
Table 5−22. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
MIN
UNIT
MIN
15
2
MAX
M58
M59
t
t
Setup time, MCBSPx.DR valid before MCBSPx.CLKX low
Hold time, MCBSPx.DR valid after MCBSPx.CLKX low
McBSP1
2 − 6P
6 + 6P
21
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX low
M60
M61
t
t
McBSP2
McBSP3
5
ns
ns
su(FXL-CKXL)
10
Cycle time, MCBSPx.CLKX
2P
16P
c(CKX)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
†‡
Table 5−23. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
§
MASTER
SLAVE
MIN
NO.
M53
PARAMETER
UNIT
MIN
MAX
MAX
Hold time, MCBSPx.FSX low after MCBSPx.CLKX
t
0.45D
0.55D
ns
h(CKXH-FXL)
¶
high
#
M54
M55
M57
t
t
t
Delay time, MCBSPx.FSX low to MCBSPx.CLKX low
0.45T
−1
0.55T
7
ns
ns
ns
d(FXL-CKXL)
d(CKXH-DXV)
d(FXL-DXV)
Delay time, MCBSPx.CLKX high to MCBSPx.DX valid
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
3P + 2
5P + 18
4P + 18
C + 20
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
CLKX period = (1 + CLKGDV) * P
T
=
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (MCBSPx.CLKX).
M61
M60
MSB
M54
LSB
MCBSPx.CLKX
M53
MCBSPx.FSX
MCBSPx.DX
MCBSPx.DR
M55
M57
Bit 0
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M58
M59
(n-2)
Bit(n-1)
(n-3)
(n-4)
Figure 5−23. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
131
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.10 Multichannel Serial Interface (MCSI)
Table 5−24 and Table 5−25 assume testing over recommended operating conditions (see Figure 5−24 and
Figure 5−25).
Table 5−24. MCSI Timing Requirements
NO.
MIN
MAX UNIT
‡
†
†
MC11
MC12
MC13
MC14
MC15
f
t
t
t
t
Operating frequency, MCSIx.CLK
Pulse duration, MCSIx.CLK high
Pulse duration, MCSIx.CLK low
Rise time, MCSIx.CLK
Slave
Slave
Slave
Slave
Slave
B
0.55P
0.55P
MHz
ns
op(CLK)
w(CLKH)
w(CLKL)
r(CLK)
†
†
0.45P
0.45P
ns
12
12
ns
Fall time, MCSIx.CLK
ns
f(CLK)
MC16
MC17
t
t
Setup time, external MCSIx.SYNC high before MCSIx.CLK low Slave
18
6
ns
ns
su(FSH-CLKL)
Hold time, external MCSIx.SYNC high after MCSIx.CLK low
Slave
Master
Slave
Master
Slave
h(CLKL-FSH)
27
18
0
MC18
MC19
t
Setup time, MCSIx.DIN valid before MCSIx.CLK low
ns
ns
su(DIV-CLKL)
h(CLKL-DIV)
t
Hold time, MCSIx.DIN valid after MCSIx.CLK low
6
†
‡
P = MCSIx.CLK period [t
] in nanoseconds.
B = Base frequency for OMAP5910 (12 or 13 MHz).
c(CLK)
Table 5−25. MCSI Switching Characteristics
NO.
MC1
MC2
MC3
MC4
PARAMETER
Operating frequency, MCSIx.CLK
MIN
MAX UNIT
‡
f
t
t
t
Master
0.5B
0.55P
0.55P
MHz
ns
op(CLK)
†
†
†
†
Pulse duration, MCSIx.CLK high
Master
Master
0.45P
w(CLKH)
w(CLKL)
Pulse duration, MCSIx.CLK low
0.45P
ns
Delay time, MCSIx.CLK high to MCSIx.SYNC transition
Master
Master
Slave
0
0
2
0
2
5
5
ns
d(CLKH-FS)
MC7
MC8
t
Delay time, MCSIx.CLK high to MCSIx.DOUT valid
ns
ns
d(CLKH-DOV)
en(CLKH-DO)
30
Master
Slave
t
Enable time, MCSIx.DOUT driven from MCSIx.CLK high
] in nanoseconds.
†
‡
P = MCSIx.CLK period [t
c(CLK)
B = Base frequency for OMAP5910 (12 or 13 MHz).
132
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
1/MC1
MC2
MC3
MCSIx.CLK
MC4
MC4
MC4
MC4
MCSIx.SYNC
(normal short)
MC4
MCSIx.SYNC
(alt. short)
MC4
MC4
MCSIx.SYNC
(normal long)
MC4
MCSIx.SYNC
(alt. long)
MC8
MC7
(0)
Bit (n)
MC18
(n−1)
MCSIx.DOUT
MCSIx.DIN
MC18
MC19
Bit (n)
(0)
(n−1)
MC19
Figure 5−24. MCSI Master Mode Timings
1/MC11
MC12
MC14
MC13
MCSIx.CLK
MC17
MC16
MC16
MC15
MC17
MCSIx.SYNC
(normal short)
MC16
MCSIx.SYNC
(alt. short)
MC17
M17
MCSIx.SYNC
(normal long)
MC16
MCSIx.SYNC
(alt. long)
MC7
MC8
(0)
Bit (n)
MC18
(n−1)
MCSIx.DOUT
MCSIx.DIN
MC18
MC19
Bit (n)
(n−1)
(0)
MC19
Figure 5−25. MCSI Slave Mode Timings
133
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.11 Camera Interface Timings
Table 5−26 assumes testing over recommended operating conditions (see Figure 5−26).
Table 5−26. Camera Interface Timing Requirements
NO.
C1
C2
C3
C5
C6
C7
C8
MIN
MAX
13
UNIT
MHz
MHz
ns
1 / [ t
1 / [ t
]
Operating frequency, CAM.LCLK
c(LCKH−HSV)
]
Operating frequency, CAM.EXCLK
24
c(XCKH−HSV)
†
‡
†
0.55P
t
t
t
t
t
Pulse duration, CAM.LCLK high or low
0.45P
w(LCK)
Setup time, CAM.D[7:0] data valid before CAM.LCLK high
Hold time, CAM.D[7:0] data valid after CAM.LCLK high
Setup time, CAM.VS/CAM.HS active before CAM.LCLK high
Hold time, CAM.VS/CAM.HS active after CAM.LCLK high
1
ns
su(LCKH−DV)
h(DV−LCKH)
su(LCKH−DV)
h(DV−CLKH)
9‡
ns
‡
1
ns
9‡
ns
†
‡
P = period of CAM.LCLK in nanoseconds (ns).
Polarity of CAM.LCLK is selectable via the POLCLK bit in the CTRLCLOCK register. Although data is latched on rising CAM.LCLK in the timing
diagrams, these timing parameters also apply to falling CAM.LCLK when POLCLK = 1.
C1
C3
C3
CAM.LCLK
C7
C8
CAM.VS
C8
C7
C5
CAM.HS
C6
Y1
C5
V1
C6
CAM.D[7:0]
U1
Yn
Figure 5−26. Camera Interface Timings
134
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
5.12 LCD Controller Timings
Table 5−27 assumes testing over recommended operating conditions (see Figure 5−27 and Figure 5−28).
†
Table 5−27. LCD Controller Switching Characteristics
NO.
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
PARAMETER
MIN
1
MAX
11
UNIT
ns
t
t
t
t
t
t
t
t
t
t
Delay time, LCD.PCLK high to LCD.HS transition
Delay time, LCD.PCLK low to LCD.HS transition
Delay time, LCD.PCLK high to LCD.VS transition
Delay time, LCD.PCLK low to LCD.VS transition
Delay time, LCD.PCLK high to pixel data valid (LCD.P[15:0])
Delay time, LCD.PCLK high to pixel data invalid (LCD.P[15:0])
Delay time, LCD.PCLK low to pixel data valid (LCD.P[15:0])
Delay time, LCD.PCLK low to pixel data invalid (LCD.P[15:0])
Delay time, LCD.PCLK high to LCD.AC transition
Delay time, LCD.PCLK low to LCD.AC transition
d(CLKH−HSV)
d(CLKL−HSV)
d(CLKH−VSV)
d(CLKL−VSV)
d(CLKH−PV)
d(CLKH−PIV)
d(CLKL−PV)
d(CLKL−PIV)
d(CLKL−ACV)
d(CLKL−ACV)
1
11
ns
1
11
ns
1
11
ns
11
ns
1
ns
11
ns
1
1
1
ns
‡
‡
5+P
ns
5+P
ns
†
‡
Although timing diagrams illustrate the logical function of the TFT mode, static timings apply to all supported modes of operation. Likewise,
LCD.HS, LCD.VS, and LCD.AC are shown as active-low, but each may optionally be configured as active-high.
P = period of internal undivided pixel clock
†
†
†
HFP
HBP
VSW
†
PPL
†
VFP
†
HSW
LCD.PCLK
L4
L4
LCD.VS
L2
L2
LCD.HS
L5
D1
L6
L9
LCD.P[15:0]
D2
D3
Dn
L9
LCD.AC
†
Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VFP (Vertical Front Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch)
and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers.
Figure 5−27. TFT Mode (LCD.HS/LCD.VS on Falling and LCD.Px on Rising LCD.PCLK)
135
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
†
†
†
HFP
HBP
VSW
†
†
VFP
†
PPL
HSW
LCD.PCLK
L3
L3
LCD.VS
L1
L1
LCD.HS
L7
D1
L8
LCD.P[15:0]
D2
D3
Dn
L10
L10
LCD.AC
†
Delays for HSW (LCD.HS Width), VSW (LCD.VS Width), VFP (Vertical Front Porch), HFP (Horizontal Front Porch), HBP (Horizontal Back Porch)
and PPL (Pixels per Line) are programmable in number of LCD.PCLK cycles via the LCD configuration registers.
Figure 5−28. TFT Mode (LCD.HS/LCD.VS on Rising and LCD.Px on Falling LCD.PCLK)
136
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
5.13 Multimedia Card/Secure Digital (MMC/SD) Timings
Table 5−28 and Table 5−29 assume testing over recommended operating conditions (see Figure 5−29
through Figure 5−32).
Table 5−28. MMC/SD Timing Requirements
NO.
M1
M2
M3
M4
MIN
12
2
MAX
UNIT
ns
t
Setup time, MMC.CMD valid before MMC.CLK high
Hold time, MMC.CMD invalid after MMC.CLK high
Setup time, MMC.DATx valid before MMC.CLK high
Hold time, MMC.DATx invalid after MMC.CLK high
su(CMDV−CLKH)
t
t
t
ns
h(CLKH−CMDV)
su(DATV−CLKH)
h(CLKH−DATV)
12
2
ns
ns
Table 5−29. MMC/SD Switching Characteristics
NO.
M7
PARAMETER
MIN
MAX
UNIT
ns
41.7
t
Cycle time, MMC.CLK
c(CLK)
5.31
us
†
†
M8
M9
t
t
t
t
Pulse Duration, MMC.CLK high
20
ns
w(CLKH)
Pulse Duration, MMC.CLK low
20
ns
w(CLKL)
M10
M11
Delay time, MMC.CLK high to MMC.CMD transition
Delay time, MMC.CLK high to MMC.DATx transition
4
4
48
48
ns
d(CLKH−CMD)
d(CLKH−DAT)
ns
†
MMC.CLK period and pulse duration depends upon software configuration.
M7
M9
M8
MMC.CLK
MMC.CMD
M10
M10
M10
M10
End
Valid
Valid
Valid
XMIT
Start
Figure 5−29. MMC/SD Host Command Timings
M9
M7
M8
MMC.CLK
MMC.CMD
M1
M1
M2
M2
Valid
XMIT
Start
Valid
Valid
End
Figure 5−30. MMC/SD Card Response Timings
137
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
M9
M7
M8
MMC.CLK
M11
M11
M11
D0
M11
End
Start
MMC.DATx
D1
D2
Dx
Figure 5−31. MMC/SD Host Write Timings
M7
M9
M8
MMC.CLK
M3
M3
Dx
M4
M4
D0
MMC.DATx
Start
D1
D2
End
Figure 5−32. MMC/SD Host Read and Card CRC Status Timings
138
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
2
5.14 I C Timings
Table 5−30 assumes testing over recommended operating conditions (see Figure 5−33).
2
Table 5−30. I C Signals (I2C.SDA and I2C.SCL) Switching Characteristics
STANDARD
FAST
MODE
MODE
NO.
PARAMETER
UNIT
MIN MAX
MIN MAX
†
IC1
IC2
t
Cycle time, I2C.SCL
10
2.5
µs
µs
c(SCL)
Setup time, I2C.SCL high before I2C.SDA low (for a repeated START
condition)
t
4.7
4
0.6
0.6
su(SCLH-SDAL)
Hold time, I2C.SCL low after I2C.SDA low (for a repeated START
condition)
IC3
t
µs
h(SCLL-SDAL)
IC4
IC5
t
Pulse duration, I2C.SCL low
4.7
4
1.3
0.6
µs
µs
ns
µs
µs
w(SCLL)
t
Pulse duration, I2C.SCL high
w(SCLH)
‡
IC6
t
Setup time, I2C.SDA valid before I2C.SCL high
250
0
100
su(SDA-SDLH)
2
IC7
t
Hold time, I2C.SDA valid after I2C.SCL low (for I C bus devices)
0
0.9
h(SDA-SDLL)
w(SDAH)
r(SDA)
IC8
t
t
t
t
t
Pulse duration, I2C.SDA high between STOP and START conditions
Rise time, I2C.SDA
4.7
1.3
IC9
1000
1000
300
300
300
300
300
ns
ns
IC10
IC11
IC12
IC13
IC14
IC15
Rise time, I2C.SCL
r(SCL)
Fall time, I2C.SDA
f(SDA)
Fall time, I2C.SCL
300
f(SCL)
t
Setup time, I2C.SCL high before I2C.SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4.0
0.6
0
µs
ns
pF
su(SCLH-SDAH)
t
50
w(SP)
§
C
400
400
b
†
‡
§
2
In the master-only I C operating mode of OMAP5910, minimum cycle time for I2C.SCL is 12 µs.
The maximum t has only to be met if the device does not stretch the low period (t
) of the I2C.SCL signal.
h(SCLL-SDAL)
= The total capacitance of one bus line in pF.
w(SCLL)
C
b
I2C.SDA
IC6
IC8
IC14
IC13
IC4
IC5
IC10
I2C.SCL
IC1
IC3
IC12
IC3
IC2
IC7
Stop
Start
Repeated
Start
Stop
of the I2C.SCL signal)
NOTES: A. A device must internally provide a hold time of at least 300 ns for the I2C.SDA signal (referred to the V
to bridge the undefined region of the falling edge of I2C.SCL.
IHmin
) of the I2C.SCL signal.
w(SCLL)
B. The maximum t
2
has only to be met if the device does not stretch the LOW period (t
2
h(SCLL−SDAL)
C. A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement t
• 250 ns must
su(SDA−SDLH)
then be met. This will automatically be the case if the device does not stretch the LOW period of the I2C.SCL signal. If such a device
does stretch the LOW period of the I2C.SCL signal, it must output the next data bit to the I2C.SDA line t max + t
1000 + 250 = 1250 ns (according to the standard-mode I C-bus specification) before the I2C.SCL line is released.
=
r
su(SDA−SDLH)
2
D.
C
= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall times are allowed.
b
2
Figure 5−33. I C Timings
139
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.15 Universal Serial Bus (USB) Timings
All OMAP5910 USB interfaces are compliant with the Universal Serial Bus Specification, Revision 2.0.
Table 5−31 assumes testing over recommended operating conditions (see Figure 5−34).
Table 5−31. USB Integrated Transceiver Interface Switching Characteristics
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
†
†
†
‡
†
†
†
‡
†
§
†
†
‡
†
†
†
‡
†
§
U1
U2
U3
U4
U5
U6
t
t
t
Rise time, USB.DP and USB.DM signals
75
75
300
300
125
2.0
25
4
4
20
20
ns
ns
%
V
r
†
Fall time, USB.DP and USB.DM signals
f
‡
Rise/Fall time matching
80
90
1.3
111.11
2.0
RFM
†
V
Output signal cross-over voltage
1.3
CRS
§
§
−25
§
−2
t
f
Differential propagation jitter
2
ns
jr
¶
Operating frequency
1.5
12 MHz
op
†
‡
§
¶
Low Speed: C = 200 pF, Full Speed: C = 50 pF
L
L
t
t
f
(t /t ) x 100
RFM = r f
t
− t
jr = px(1) px(0)
1/t
op = per
†
REF clock
t
t
px(0)
px(1)
t
t
per − jr
90%
USB.DM
V
OH
V
OL
V
CRS
USB.DP
10%
U2
U1
†
“REF clock” is not an actual device signal, but an ideal reference clock against which relative timings are specified. REF clock is assumed to be
12 MHz for full-speed mode or 1.5 MHz for low-speed mode).
Figure 5−34. USB Integrated Transceiver Interface Timings
140
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
5.16 Microwire Interface Timings
Table 5−32 and Table 5−33 assume testing over recommended operating conditions (see Figure 5−35).
Table 5−32. Microwire Timing Requirements
NO.
W5
W6
MIN
21
6
MAX
UNIT
ns
†
Setup time, UWIRE.SDI valid before UWIRE.SCLK active edge
t
t
su(SDI−SCLK)
†
Hold time, UWIRE.SDI invalid after UWIRE.SCLK active edge
ns
h(SCLK−SDI)
†
Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software
configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data
and capture input data.
Table 5−33. Microwire Switching Characteristics
NO.
W1
W2
W3
W4
PARAMETER
MIN
MAX
UNIT
MHz
ns
f
t
t
t
Operating Frequency, UWIRE.SCLK
3
op(SCLK)
‡
‡
0.55P
Pulse Duration, UWIRE.SCLK high/low
0.45P
w(SCLK)
†
Delay time, UWIRE.SCLK active edge to UWIRE.SDO transition
−3
6
ns
d(SCLK−SDO)
d(CS−SCLK)
†
‡
1.5P
Delay time, UWIRE.CSx active to UWIRE.SCLK active
ns
†
‡
Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software
configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data
and capture input data.
P = UWIRE.SCLK cycle time in ns.
UWIRE.CSx
W2
W4
[1/W1]
W2
W4
UWIRE.SCLK
W3
W3
UWIRE.SDO
UWIRE.SDI
Valid
Valid
Valid
W5
W6
Valid Valid
Valid
NOTE: The polarities of UWIRE.CSx and UWIRE.SCLK and the active UWIRE.SCLK edges on which SDO is driven and SDI is sampled are all
software configurable.
Figure 5−35. Microwire Timings
141
August 2002 − Revised August 2003
SPRS197B
Electrical Specifications
5.17 HDQ/1-Wire Interface Timings
Table 5−34 and Table 5−35 assume testing over recommended operating conditions (see Figure 5−36
through Figure 5−39).
†
Table 5−34. HDQ/1-Wire Timing Requirements
MIN
190
32
MAX
250
50
UNIT
µs
H1
H2
H3
t
c
t
v
t
v
Cycle time, master read
Read one data valid after HDQ low
Read zero data hold after HDQ low
µs
80
145
µs
OMAP5910 base
frequency = 12 MHz
190
190
320
303
µs
µs
H4
t
v
Response time from HDQ slave device
OMAP5910 base
frequency = 13 MHz
W1
W2
W3
t
t
t
Cycle time, master read
190
12
1
µs
µs
µs
c
Read data valid after HDQ low (master sample window)
Recovery time after slave device inactive
13.6
v
dis
†
HDQ timing is OMAP5910 default. 1-Wire timing is selectable through software.
Table 5−35. HDQ/1-Wire Switching Characteristics
PARAMETER
MIN
190
32
MAX
UNIT
µs
H5
H6
t
t
Cycle time, master write
c
Write one data valid after HDQ low
50
µs
d
OMAP5910 base
frequency = 12 MHz
100
92
145
µs
µs
H7
t
d
Write zero data hold after HDQ low
OMAP5910 base
frequency = 13 MHz
145
H8
H9
t
t
t
t
t
t
Pulse width, HDQ low for break pulse (reset)
Pulse width, HDQ high for break pulse recovery
Cycle time, master write
190
40
µs
µs
µs
µs
µs
µs
w
w
c
W4
W5
W6
W7
190
15
Write zero master inactive after HDQ low
Write one master inactive after HDQ low
Recovery time after master inactive
90
d
1.1
1
1.4
d
dis
142
SPRS197B
August 2002 − Revised August 2003
Electrical Specifications
Read 1
Read 0
HDQ
H2
H3
H1
Figure 5−36. OMAP5910 HDQ Interface Reading From HDQ Slave Device
Write 1
Write 0
HDQ
H6
H7
H5
Figure 5−37. OMAP5910 HDQ Interface Writing to HDQ Slave Device
Break
Command Byte
(Written by OMAP5910)
Data Byte
(Received by OMAP5910 from Slave)
Register Address
0
0
7
7
6
1
1
6
(LSB)
(LSB)
(MSB)
(MSB)
HDQ
H4
Figure 5−38. Typical Communication Between OMAP5910 HDQ and HDQ Slave
HDQ
H9
H8
Figure 5−39. HDQ/1-Wire Break (Reset) Timing
143
August 2002 − Revised August 2003
SPRS197B
Glossary
6
Glossary
ACRONYM
DEFINITION
1-wire
AAC
a serial protocol defined by Dallas Semiconductor Corporation
Advanced Audio Coding (standard) (ISO/IEC 13818-7)
Interface Standard for Codecs
arithmetic/logic unit
AC97
ALU
AMR
ASRAM
AU
Adaptive Multi-Rate
asynchronous static RAM
address unit
BCD
BGA
CMOS
CP15
CRC
CSL
binary coded decimal
ball grid array
complementary metal oxide semiconductor
coprocessor 15
cyclic redundancy check
Chip Support Library
CTS
clear-to-send
DARAM
DCT
dual-access RAM
discrete cosine transform
direct memory access
digital phase-locked loop
digital signal processor
DSP Library
DMA
DPLL
DSP
DSPLIB
DSR
DTR
data-set-ready
data-terminal-ready
DU
data unit
EMIFF
EMIFS
EP
external memory interface fast
external memory interface slow
endpoint
ESD
electrostatic discharge
ETM
FAC
frame adjustment counter
Fast Fourier Transform
first-in first out
FFT
FIFO
FIQ
fast interrupt request
GPRS
GSM
H.26x
HBM
HBP
General Packet Radio Service
Global System for Mobile Communications
an ITU-TSS standard
Human Body Model
Horizontal Back Porch
144
SPRS197B
August 2002 − Revised August 2003
Glossary
ACRONYM
DEFINITION
HDQ
HFP
a single-wire serial interface protocol defined by Benchmarq Controls Inc.
Horizontal Front Porch
HOM
HS
host-only mode
high-speed
I-cache
instruction cache
2
I C
Inter-integrated circuit
2
I S
Inter-IC Sound (specification)
Inverse Discrete Cosine Transform
interface
iDCT
I/F
IFR
Interrupt Flag Register
IMGLIB
IMIF
Image/Video Processing Library
internal memory interface
Interrupt Mask Register
IMR
IOM-2
IrDA
ISDN Oriented Modular Interface Revision 2
infrared data adapter
IRQ
low-priority interrupt request
instruction unit
IU
JPEG
LB
Joint Photographic Experts Group − standard for compressed still-picture data
local bus
LCD
liquid crystal display
LPG
LED pulse generator
LSB
least significant bit
LVCMOS
MAC
MCSI
McBSP
MMC
MMC/SD
MMU
MPEG
MPU
MPUI
MPUIO
MSB
MVIP
ODM
OEM
OHCI
OS
low-voltage CMOS
multiply-accumulate
multichannel serial interface
multichannel buffered serial port
multimedia card
multimedia card/secure digital
memory management unit
Moving Picture Experts Group − proposed standard for compressed video data
microprocessor unit
microprocessor unit interface
microprocessor unit I/O
most significant bit
multi-vendor integration protocol
original design manufacturer
original equipment manufacturer
Open Host Controller Interface
operating system
Benchmarq is a trademark of Texas Instruments.
145
August 2002 − Revised August 2003
SPRS197B
Glossary
ACRONYM
DEFINITION
PPL
pixels per line
PU
program unit
PWL
PWT
RISC
RTC
RTS
pulse-width light
pulse-width tone
reduced instruction set computer
real-time clock
request-to-send
SAM
SARAM
SD
shared-access mode
single-access RAM
secure digital
SDRAM
SDW
SIR
synchronous dynamic RAM
short distance wireless
slow infrared
SPI
serial peripheral interface
static RAM
SRAM
SRG
STN
Sample Rate Generator
super twisted nematic
T1/E1
T1 is a digital transmission link with a capacity of 1.544 Mbps. It uses two pairs of nor-
mal twisted-wires and can handle 24-voice conversations, each digitized using mu-law
coding at 64 kbps. T1 is used in USA, Canada, Hong Kong, and Japan. E1 is a digital
transmission link with a capacity of 2.048 Mbps. It is the European equivalent of T1. It
can handle 30-voice conversations, each digitized using A-law coding at 64 kbps.
TAP
test access port
TC
traffic controller
TFT
thin-film transistor
TI
Texas Instruments
TIPB
TLB
TI peripheral bus
Translation Look-Aside Buffer
Translation Table Base
universal asynchronous receiver/transmitter
ultra low-power device
uniform resource locator
universal serial bus
TTB
UART
ULPD
URL
USB
USB2.0
VFP
VIVT
WB
Universal Serial Bus Specification Revision 2.0
Vertical Front Porch
virtual index virtual tag
write buffer
WDT
WMA
WMV
watchdog timer
Windows Media Audio
Windows Media Video
146
SPRS197B
August 2002 − Revised August 2003
Mechanical Data
7
Mechanical Data
7.1 GZG Ball Grid Array Mechanical Data
GZG (S-PBGA-N289)
PLASTIC BALL GRID ARRAY
12,10
SQ
10,00 TYP
11,90
0,50
AA
W
U
R
N
L
Y
V
T
P
M
K
H
F
J
G
E
D
B
C
A
A1 Corner
1
3
5
7
9
11 13 15 17 19 21
2
4
6
8 10 12 14 16 18 20
Bottom View
0,95
0,85
1,20 MAX
Seating Plane
0,08
0,35
0,25
M
∅ 0,05
0,30
0,20
4173512-6/D 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
Figure 7−1. OMAP5910 289-Ball MicroStar BGA Plastic Ball Grid Array (GZG) Package
MicroStar BGA is a trademark of Texas Instruments.
147
August 2002 − Revised August 2003
SPRS197B
Mechanical Data
7.2 GDY Ball Grid Array Mechanical Data
GDY (S-PBGA-N289)
PLASTIC BALL GRID ARRAY PACKAGE
19,20
SQ
18,80
16,00 TYP
1,00
17,70
SQ
17,30
U
R
N
L
T
P
M
K
H
F
1,00
J
G
E
C
A
D
B
A1 Corner
1
3
5
7
9
11 13 15 17
10 12 14 16
2
4
6
8
Bottom View
1,22
1,12
2,32 MAX
Seating Plane
0,15
0,60
0,40
0,10
0,50
0,30
4204662/A 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 7−2. OMAP5910 289-Ball Plastic Ball Grid Array (GDY) Package
148
SPRS197B
August 2002 − Revised August 2003
相关型号：
OMAP5910JZZG2
This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date and includes the following changes
TI
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