P4C1024-35P3I [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | P4C1024-35P3I |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总8页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1024
HIGH SPEED 128K x 8
CMOS STATIC RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and
OE Inputs
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down
Packages
Common Data I/O
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
DESCRIPTION
The P4C1024 is a 1,048,576-bit high-speed CMOS The P4C1024 device provides asynchronous opera-
static RAM organized as 128Kx8. The CMOS memory tions with matching access and cycle times. Memory
requires no clocks or refreshing, and has equal access locations are specified on address pinsA0 toA16. Read-
and cycle times. Inputs are fully TTL-compatible. The ing is accomplished by device selection (CE1 low and
RAM operates from a single 5V±10% tolerance power CE2 high) and output enabling (OE) while write enable
supply.
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
Access times of 15 nanoseconds permit greatly en- location is presented on the data input/output pins. The
hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either
reduce power consumption to a low level. The P4C1024 CE1 or OE is HIGH or WE or CE2 is LOW.
is a member of a family of PACE RAM™ products offer-
ing fast access times.
Package options for the P4C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
V
A
NC
A
CC
15
2
262,144-
A
16
14
BIT
(9)
A
A
A
3
CE
MEMORY
ARRAY
2
4
WE
12
A
7
5
A
13
A
6
6
A
8
I/O1
I/O2
A
5
7
A
9
INPUT
DATA
A
8
A
11
COLUMN
I/O
4
CONTROL
A
9
OE
A
3
2
1
0
0
A
A
10
11
12
13
14
10
CE1
A
I/O
7
I/O
I/O
6
COLUMN
SELECT
I/O
I/O
I/O
5
1
I/O
4
18
17
15
16
2
WE
GND
I/O
3
• • • • • •
CONTROL
CIRCUIT
CE
CE
1
2
DIP (P300), SOJ (J300, J400)
TOP VIEW
A
(8)
A
OE
Means Quality, Service and Speed
1Q97
141
P4C1024
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Supply Voltage
4.5V ≤ VCC ≤ 5.5V
4.5 ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C)
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
Parameter
Symbol
VCC
Max
7.0
Unit
Min
-0.5
-0.5
-55
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
V
V
VTERM
TA
VCC + 0.5
125
°C
Storage Temperature
STG
IOUT
ILAT
-65
150
°C
mA
mA
Output Current into Low Outputs
Latch-up Current
25
>200
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Unit
Symbol
Parameter
Min
Max
Test Conditions
IOH = –4mA, VCC = 4.5V
VOH
Output High Voltage
(I/O0 - I/O7)
2.4
V
VOL
I
OL = 8 mA
V
V
V
Output Low Voltage
(I/O0 - I/O7)
0.4
0.5
IOL = 10 mA
VIH
Input High Voltage
Input Low Voltage
Input Leakage Current
2.2
VCC + 0.3
0.8
V
-0.5
VIL
ILI
GND ≤ VIN ≤ VCC
Ind'l.
Com'l.
+10
+5
-10
-5
µA
GND ≤ VOUT ≤ VCC
CE1 ≥ VIH or CE2 ≤ VIL
Ind'l.
Com'l.
+10
+5
Output Leakage Current
µA
ILO
-10
-5
IOS
Output Short-Circuit
Current
VOUT = GND, VCC = Max (Single
output) not to exceed 30 second
duration
-350
mA
20
VCC Current
CMOS Standby Current
(CMOS Input Levels)
VCC = 5.5V, IOUT = 0 mA
mA
ISB1
(Standard)
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V
142
P4C1024
CAPACITANCES
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
Parameter
Symbol
Unit
Test Conditions
Max
8
CIN
pF
pF
Input Capacitance
VIN = 0V
COUT
Output Capacitance
VOUT = 0V
10
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
-15
-20
-25
Range
-17
-35 -45
Commercial
Industrial
ICC
190 180 160
N/A N/A 175
145 N/A
160 155
mA
mA
150
165
Dynamic Operating Current
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1, and WE ≤ VIL (max). Switching inputs are 0V
and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-15
-35
-45
-17
-20
-25
Unit
Parameter
Symbol
Min
Max Min
Max Min Max
Max Min Max Min
Max
Min
tRC
15
17
20
25
Read Cycle Time
Address Access Time
35
45
ns
ns
45
45
tAA
tAC
tOH
tLZ
15
15
20
20
17
17
25
25
35
35
Chip Enable Access
Time
ns
ns
ns
Output Hold from
Address Change
3
3
3
3
3
3
3
3
3
3
3
3
Chip Enable to
Output in Low Z
8
6
11
10
ns
ns
ns
tHZ
Chip Disable to
Output in High Z
9
7
9
9
15
15
20
20
Output Enable Low
to Data Valid
tOE
0
0
Output Enable Low
to Low Z
0
0
0
0
0
0
0
0
0
0
tOLZ
tOHZ
tPU
9
15
20
7
Output Enable High
to High Z
6
11
20
20
25
ns
ns
Chip Enable to
Power Up Time
tPD
12
20
ns
Chip Disable to
15
Power Down Time
143
P4C1024
READ CYCLE NO. 1 (OE CONTROLLED)(1)
(5)
RC
t
ADDRESS
t
AA
OE
t
t
OH
OE
t
OLZ
CE
CE
2
t
t
AC
OHZ
t
HZ
t
LZ
DATA OUT
NOTES:
1. WE is HIGH for READ cycle.
4. Transition is measured ± 200 mV from steady state voltage
prior to change, with loading as specified in Figure1. This
parameter is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to
the first transitioning address.
2. CE1 and OE is LOW and CE2 is HIGH for read cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE1 transition LOW or CE2 transition HIGH.
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5)
t
RC
ADDRESS
t
AA
t
OH
DATA OUT
DATA VALID
PREVIOUS DATA VALID
READ CYCLE NO. 3 (CE CONTROLLED)
t
RC
CE1
CE2
t
HZ
t
AC
t
LZ
DATA OUT
SUPPLY
DATA VALID
HIGH IMPEDANCE
t
t
I
I
PD
PU
CC
SB
V
CC
CURRENT
144
P4C1024
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-15
-17
-20
-25
-35
-45
Symbol
Parameter
Unit
Max
Max
Min
15
Min
Min Max
Max Min Max
Min Max Min
Write Cycle Time
17
13
20
15
25
18
35
22
45
ns
ns
tWC
tCW
Chip Enable Time 12
to End of Write
30
35
Address Valid to
End of Write
12
13
15
20
25
ns
tAW
tAS
tWP
tAH
Address Set-up
Time
0
0
0
0
0
0
ns
ns
12
15
Write Pulse Width 12
18
22
25
0
7
0
Address Hold Time
0
7
0
0
8
0
10
0
0
15
0
0
20
0
ns
ns
Data Valid to End
of Write
tDW
Data Hold Time
0
ns
ns
tDH
tWZ
15
Write Enable to
Output in High Z
8
8
10
11
18
tOW
Output Active from
End of Write
3
3
3
3
3
3
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)(6)
(9)
t
WC
ADDRESS
t
CW
CE1
CE2
t
AW
t
t
t
WP
AH
DH
WE
t
t
AS
DW
DATA IN
DATA VALID
(4,7)
(4)
WZ
t
t
OW
(7)
DATA OUT
DATA UNDEFINED
HIGH IMPEDANCE
Notes:
6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
145
P4C1024
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)
(9)
t
WC
ADDRESS
t
t
AS
CW
CE
1
t
AH
t
AW
CE
2
t
WP
WE
t
t
DH
DW
DATA VALID
DATA IN
DATA OUT(12)
HIGH IMPEDANCE
TRUTH TABLE
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Mode
CE1 CE2 OE WE I/O
Power
Standby
Standby
H
X
X
X
High Z
High Z
High Z
Standby
Standby
X
L
X
X
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
L
H
H
H
Active
DOUT Disabled
See Figures 1 and 2
DOUT
L
L
H
H
L
H
L
Read
Write
Active
X
High Z Active
+5V
R
= 166.5 Ω
= 1.73 V
480 Ω
TH
V
D
TH
OUT
D
OUT
30pF* (5pF* for t , t , t
,
HZ LZ OHZ
255 Ω
,
30pF* (5pF* for t , t
t
,
HZ LZ OHZ
,
)
t
t
and t
OLZ WZ OW
,
)
t
t
and t
OLZ WZ OW
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.73V (Thevenin Voltage) at the comparator input, and a
116Ω resistor must be used in series with DOUT to match 166Ω
(Thevenin Resistance).
Becauseoftheultra-highspeedoftheP4C1024,caremustbetaken
when testing this device; an inadequate setup can cause a normal
functioningparttoberejectedasfaulty. Longhigh-inductanceleads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
frequency capacitor is also required between VCC and ground.
146
P4C1024
TEMPERATURE RANGE SUFFIX
PACKAGE SUFFIX
Temperature
Description
Range Suffix
Package
Description
Suffix
C
P3
J3
J4
Commercial Temperature Range,
0˚C to +70˚C
Plastic DIP, 300 mil wide standard
Plastic SOJ, 300 mil wide standard
Plastic SOJ, 400 mil wide standard
Industrial Temperature Range,
-40˚C to +85˚C
I
ORDERING INFORMATION
Performance Semiconductor's part numbering scheme is as follows:
P4C 1024
ss
p
t
Temperature Range: C, I
Package Code: P3, J3, J4
Speed (Access/Cycle Time): 15, 17, etc.
Device Number: 1024
Static RAM Prefix
SELECTION GUIDE
The P4C1024 is available in the following temperature, speed and package options.
Speed (ns)
-20
Temperature
Range
Package
-15
-17
-25
-35
Plastic DIP 300
Plastic SOJ 300
Plastic SOJ 400
-15P3C -17P3C -20P3C -25P3C -35P3C
-15J3C -17J3C -20J3C -25J3C -35J3C
-15J4C -17J4C -20J4C -25J4C -35J4C
Commercial
Temperature
Industrial
Temperature Plastic SOJ 300
Plastic SOJ 400
Plastic DIP 300
N/A
N/A
N/A
N/A
N/A
N/A
-20P3I -25P3I -35P3I
-20J3I -25J3I -35J3I
-20J4I -25J4I -35J4I
N/A = Not Available
147
148
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