PDM31584SA20TITR [ETC]
256 X 16 CMOS 3.3V STATIC RAM; 256× 16的3.3V CMOS静态RAM
| 型号： | PDM31584SA20TITR |
| 厂家： | 
ETC |
| 描述： | 256 X 16 CMOS 3.3V STATIC RAM |
| 文件： | 总9页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDM31564
PRELIMINARY
256K x 16 CMOS
3.3V Static RAM
1
2
Features
Description
■ High-speed access times
- Com’l: 8, 10, 12, 15, and 20 ns
- Ind: 12, 15, and 20 ns
■ Low power operation (typical)
- PDM31564SA
The PDM31564 is a high-performance CMOS static
RAM organized as 262,144 x 16 bits. The PDM31564
features low power dissipation using chip enable
(CE) and has an output enable input (OE) for fast
memory access. Byte access is supported by upper
and lower byte controls.
Active: 300 mW
Standby: 25mW
The PDM31564 operates from a single 3.3V power
supply and all inputs and outputs are fully TTL-
compatible.
3
■ High-density 256K x 16 architecture
■ 3.3V (±0.3V) power supply
■ Fully static operation
■ TTL-compatible inputs and outputs
■ Output buffer controls: OE
■ Data byte controls: LB, UB
■ Packages:
The PDM31564 is available in a 44-pin 400-mil plas-
tic SOJ and a plastic TSOP package for high-density
surface assembly and is suitable for use in high-
speed applications requiring high-speed storage.
4
5
Plastic SOJ (400 mil) - SO
Plastic TSOP (II) - T
6
Functional Block Diagram
Vcc
8
Vss
A8 - A0
Memory
Cell
Array
256 x 128 x 32
512 x 256 x 32
9
Data
Input/
Output
Buffer
I/O15-I/O0
Sense Amp
10
11
12
Column
Decoder
WE
OE
UB
LB
Control
Logic
Column
Address
Buffer
Clock
Generator
CE
A17 - A9
Rev. 1.2 - 3/31/98
1
PRELIMINARY
PDM31564
Pin Configuration
SOJ
TSOP (II)
A4
A3
44
43
42
41
40
39
38
37
A5
1
A4
A3
44
43
42
41
40
39
38
37
A5
1
2
3
4
5
6
7
8
2
A6
A6
A2
A7
3
A2
A7
A1
OE
4
A1
OE
A0
UB
5
A0
UB
CE
LB
6
CE
LB
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O15
I/O14
7
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
I/O15
I/O14
I/O13
I/O12
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
8
36 I/O13
35 I/O12
9
36
35
34
33
32
31
30
29
9
10
11
12
13
10
11
12
13
14
34
33
32
31
30
29
Vss
Vcc
I/O11
I/O10
I/O9
I/O8
NC
I/O5 14
I/O6
15
15
16
17
18
I/O7
16
WE
17
28
27
26
25
28
27
26
25
24
23
A17
A16
A15
A14
A13
18
A8
A8
A9
19
20
21
22
A9
19
20
21
22
A10
A10
A11
A12
24 A11
A12
23
Pin Description
Name
Description
A17-A0
I/O15-I/O0
CE
Address Inputs
Data Inputs
Chip Enable Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
No Connect
WE
OE
LB, UB
NC
V
Ground
ss
V
Power (+3.3V)
CC
Capacitance (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Conditions
Max.
Unit
C
C
Input Capacitance
Output Capacitance
V
= V
SS
6
8
pF
pF
IN
IN
V
= V
SS
I/O
I/O
NOTE: This parameter is determined by device characterization, but is not production tested.
2
Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
Operating Mode
Mode
CE
OE
WE
LB
UB
I/O7-I/O0
I/O15-I/O8
Power
1
2
Read
L
L
H
L
H
L
L
L
Output
High Impedance
Output
Output
Output
I
I
I
I
I
I
I
I
CC
CC
CC
CC
CC
CC
CC
CC
H
L
High Impedance
Input
Write
L
X
L
L
Input
H
L
L
High Impedance
Input
Input
H
x
High Impedance
High Impedance
High Impedance
High Impedance
Output Disable
Standby
L
L
H
X
X
H
X
X
X
H
X
High Impedance
High Impedance
High Impedance
3
H
X
H
I
SB
NOTE: H = V , L = V , X = DON’T CARE
IH
IL
4
(1)
Absolute Maximum Ratings
Symbol
Rating
Com’l.
Ind.
Unit
5
V
Terminal Voltage with Respect to V
Temperature Under Bias
Storage Temperature
–0.5 to +4.6
–55 to +125
–55 to +125
1.5
–0.5 to +4.6
–65 to +135
–65 to +150
1.5
V
°C
°C
W
TERM
BIAS
STG
SS
T
T
6
P
Power Dissipation
T
I
DC Output Current
50
50
mA
°C
OUT
(2)
T
Maximum Junction Temperature
125
145
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
8
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form: T = T + P * θ where T is the ambient tempera-
j
a
ja
a
ture, P is average operating power and θ the thermal resistance of the package. For
ja
9
this product, use the following θ values:
ja
o
SOJ: 59 C/W
o
TSOP: 87 C/W
10
11
12
Recommended DC Operating Conditions
Symbol
Description
Min.
Typ.
Max.
Unit
V
V
Supply Voltage
3.0
0
3.3
0
3.6
0
V
V
CC
SS
Supply Voltage
Industrial
Ambient Temperature
Ambient Temperature
–40
0
25
25
85
70
°C
°C
Commercial
Rev. 1.2 - 3/31/98
3
PRELIMINARY
PDM31564
DC Electrical Characteristics (V = 3.3V ± 0.3V)
CC
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
Input Leakage Current
V
= Max., V = Vss to V
Com’l/
Ind.
–5
5
µA
LI
CC
IN
CC
I
Output Leakage Current
V
= Max.,
Com’l/
Ind.
–5
5
µA
LO
CC
CE = V , V
= Vss to V
CC
IH OUT
(1)
V
V
Input Low Voltage
Input High Voltage
–0.3
2.2
0.8
V
V
IL
Vcc +
0.3
IH
V
V
Output Low Voltage
Output High Voltage
I
I
= 8 mA, V = Min.
—
0.4
—
V
V
OL
OL
CC
= –4 mA, V = Min.
2.4
OH
OH
CC
NOTE: 1. V (min) = –3.0V for pulse width less than 20 ns.
IL
Power Supply Characteristics
-8
-10
-12
-15
-20
Symbol Parameter
Operating Current
CE = V
Com’l Com’l Com’l Ind. Com’l Ind. Com’l Ind. Unit
I
220
210
200
210
190
200
185
195
mA
CC
IL
f = f
= 1/t
RC
MAX
V
= Max.
= 0 mA
CC
I
OUT
I
Standby Current
CE = V
50
10
45
10
40
10
45
15
35
10
40
15
30
10
35
15
mA
mA
SB
IH
f = f
= 1/t
RC
MAX
V
= Max.
CC
I
Full Standby Current
SB1
CE ≥ V – 0.2V
CC
f = 0
V
V
= Max.,
CC
≥ V – 0.2V or ≤ 0.2V
IN
CC
NOTES: All values are maximum guaranteed values.
4
Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
AC Test Conditions
Input pulse levels
V
to 3.0V
SS
1
2
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
2.5 NS
1.5V
1.5V
See Figures 1 and 2
3
4
+3.3V
5
+3.3V
317Ω
317Ω
DOUT
351Ω
DOUT
351Ω
6
30 pF
5 pF
Figure 2. Output Load Equivalent
(for t , t , t , t
Figure 1. Output Load
LZCE HZCE LZWE HZWE,
t
, t
, t
, t
)
LZBE HZBE LZOE HZOE
8
9
10
11
12
Rev. 1.2 - 3/31/98
5
PRELIMINARY
PDM31564
Read Timing Diagram
t
RC
ADDRESSES
t
AA
t
t
OH
ACE
CE
OE
t
(1)
AOE
t
HZCE
t
(1)
t
BA
HZOE
(1)
UB, LB
(1)
t
LZBE
t
HZBE
(1)
t
LZOE
(1)
t
LZCE
D
OUT
Output Data Valid
AC Electrical Characteristics
Description
READ Cycle
-8*
-10*
Max Min
–12
–15
Max Min
–20
Symbol Min
Max Min
Max Min
Max Unit
READ cycle time
t
8
–
–
–
4
0
–
3
–
–
0
–
–
8
8
5
–
–
4
–
4
4
–
4
10
–
–
–
4
0
–
3
–
–
0
–
–
10
10
6
12
—
—
—
4
—
12
12
7
15
—
15
15
8
20
—
—
—
4
—
20
20
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address access time
Chip enable access time
Byte access time
t
—
—
—
4
AA
t
ACE
t
BA
Output hold from address change
t
–
—
—
8
—
—
9
—
—
9
OH
(1)
Byte disable to output in low-Z
t
–
0
0
0
LZBE
HZBE
(1)
Byte enable to output in high-Z
t
5
—
4
—
4
—
5
(1)
Chip enable to output in low-Z
t
–
—
6
—
7
—
8
LZCE
HZCE
(1, 2)
Chip disable to output high-Z
t
5
—
—
0
—
—
0
—
—
0
Output enable access time
t
5
6
7
10
—
6
AOE
(1)
Output enable to output in low-Z
t
–
—
5
—
6
LZOE
HZOE
(1, 2)
Output disable to output in high-Z
t
5
—
—
—
* V = 3.3V +5%
CC
6
Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
Write Cycle 1 Timing Diagram (WE Controlled)
t
WC
1
2
ADDRESSES
t
AW
t
t
t
AH
AS
WP
WE
CE
t
CW
3
t
BW
UB, LB
4
(1)
(1)
t
t
LZWE
HZWE
High Impedance
(3)
(4)
D
OUT
t
t
5
DS
DH
D
IN
Data Stable
6
Write Cycle 2 Timing Diagram (CE Controlled)
t
WC
ADDRESSES
t
AW
t
AS
t
t
AH
WP
8
WE
CE
t
CW
9
t
BW
UB, LB
(1)
(1)
10
11
12
t
t
HZWE
LZBE
(1)
t
LZCE
High Impedance
D
OUT
t
t
DH
DS
D
IN
Data Stable
Rev. 1.2 - 3/31/98
7
PRELIMINARY
PDM31564
Write Cycle 3 Timing Diagram (UB, LB Controlled)
t
WC
ADDRESSES
t
AW
t
AS
t
t
AH
WP
WE
CE
t
CW
t
BW
UB, LB
(1)
(1)
t
t
LZCE
(1)
HZWE
t
LZBE
High Impedance
D
OUT
t
t
DH
DS
D
IN
Data Stable
AC Electrical Characteristics
Description
-8*
-10*
-12
-15
-20
WRITE Cycle
Sym Min. Max Min. Max Min. Max. Min. Max. Min. Max. Unit
WRITE cycle time
t
t
8
7
—
—
—
—
—
—
—
—
—
—
6
10
8
—
—
—
—
—
—
—
—
—
—
6
12
10
10
10
0
—
—
—
—
—
—
—
—
—
—
7
15
11
11
12
0
—
—
—
—
—
—
—
—
—
—
8
20
13
13
13
0
—
—
—
—
—
—
—
—
—
—
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Chip enable to end of write
Address valid to end of write
Byte pulse width
CW
t
7
8
AW
t
7
8
BW
Address setup time
Address hold from end of write
Write pulse width
t
0
0
AS
AH
WP
t
0
0
0
0
0
t
t
7
8
8
9
10
9
Data setup time
t
5
6
7
8
DS
DH
Data hold time
0
0
0
0
0
(1, 3, 4)
Byte disable to output in low Z
t
0
0
0
0
0
LZBE
HZBE
(1, 3, 4)
Byte enable to output in high Z
t
—
—
—
—
—
(1, 3, 4)
Output disable to output in low Z
t
0
—
6
0
—
6
0
—
7
0
—
7
0
—
8
ns
ns
LZOE
(1, 3, 4)
Output enable to output in high Z
t
t
—
—
—
—
—
HZOE
(1,3, 4)
Write disable to output in low Z
0
—
6
0
6
—
—
0
—
7
0
—
7
0
—
9
ns
ns
LZWE
HZWE
(1, 3, 4)
Write enable to output in high Z
t
—
—
—
—
* V = 3.3v +5%
CC
8
Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
NOTES:
1. Parameter is determined by device characterization and is not production tested. See Figure 2 for load conditions.
2. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high imped-
ance state.
3. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high imped-
ance state.
1
2
4. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period.
3
4
5
Ordering Information
XXXXX
X
XX
X
X
X
Speed
Device Type Power
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
6
Blank Tubes
TR
TY
Tape & Reel
Tray
Blank
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
Automotive (–40°C to +105°C)
I
A
SO
T
44-pin 400-mil Plastic SOJ
44-pin Plastic TSOP (II)
8
8
10
12
15
20
Commercial Only
Commercial Only
9
SA
Standard Power
10
11
12
PDM31564 - (256Kx16) Static RAM
Faster Memories for a FasterWorld ™
Rev. 1.2 - 3/31/98
9
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