PDM41024LA15SOI [ETC]
1 Megabit Static RAM 128K x 8-Bit; 1兆位静态RAM 128K ×8位
| 型号： | PDM41024LA15SOI |
| 厂家： | 
ETC |
| 描述： | 1 Megabit Static RAM 128K x 8-Bit |
| 文件： | 总8页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDM41024
1 Megabit Static RAM
128K x 8-Bit
1
2
Description
Features
The PDM41024 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE1) inputs are both LOW and CE2 is
HIGH. Reading is accomplished when WE and CE2
remain HIGH and CE1 and OE are both LOW.
■ High-speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
■ Low power operation (typical)
- PDM41024SA
3
Active: 450 mW
Standby: 50 mW
- PDM41024LA
Active: 400 mW
The PDM41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41024 comes in two versions:
the standard power version (SA) and the low power
version (LA). The two versions are functionally the
same and differ only in their power consumption.
Standby: 25mW
■ Single +5V (±10%) power supply
■ TTL-compatible inputs and outputs
■ Packages
The PDM41024 is available in a 32-pin plastic TSOP
(I), and a 300-mil and 400-mil plastic SOJ.
5
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP (I)- T
6
Functional Block Diagram
7
A0
Decoder
Memory
•
•
•
8
•
•
•
Addresses
Matrix
•
•
•
•
•
A16
9
• • • • •
Column I/O
I/O0
Input
Data
Control
•
•
10
11
12
I/O7
•
•
•
CE1
CE2
WE
OE
Control
Rev. 3.3 - 4/09/98
1
PDM41024
Pin Configuration
SOJ
TSOP (I)
Vcc
A15
CE2
WE
A13
A8
1
2
3
4
5
6
7
8
32
31
30
29
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
A11
A9
A8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
28
27
26
25
24
23
A6
A9
A5
9
A11
OE
A4
10
11
12
13
14
15
16
9
A3
10
11
12
13
14
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A2
A1
22
21
20
19
18
17
A6
A5
A4
A1
A2
A3
A0
I/O0
I/O1
I/O2
Vss
15
16
Pin Description
Name
Description
Address Inputs
(1)
Truth Table
A16-A0
I/O7-I/O0
OE
OE
WE
CE1
CE2
I/O
MODE
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Inputs
No Connect
X
X
L
X
X
H
L
H
X
L
L
L
X
L
Hi-Z
Hi-Z
Standby
Standby
Read
WE
H
H
H
D
OUT
CE1, CE2
NC
X
H
D
Write
IN
H
Hi-Z
Output Disable
V
Power (+5V)
CC
SS
V
Ground
NOTE: 1. H = V , L = V , X = DON’T CARE
IH
IL
(1)
Absolute Maximum Ratings
Symbol
Rating
Com’l.
Ind.
Unit
V
Terminal Voltage with Respect to V
Temperature Under Bias
Storage Temperature
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
V
°C
°C
W
TERM
BIAS
STG
SS
T
T
P
Power Dissipation
T
I
DC Output Current
50
50
mA
°C
OUT
(2)
T
Maximum Junction Temperature
125
145
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device.This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form: T = T + P * θ where T is the ambient temperature, P
j
a
ja
a
is average operating power and θ the thermal resistance of the package. For this
ja
product, use the following θ values:
ja
o
SOJ: 72 C/W
o
TSOP: 95 C/W
2
4/09/98 - Rev. 3.3
PDM41024
Recommended DC Operating Condition
Symbol
Parameter
Min.
Typ.
Max.
Unit
1
2
V
V
Supply Voltage
4.5
0
5.0
0
5.5
0
V
V
CC
Supply Voltage
SS
Industrial
Ambient Temperature
Ambient Temperature
–40
0
25
25
85
70
°C
°C
Commercial
DC Electrical Characteristics (V = 5.0V ± 10%)
CC
3
PDM41024SA
PDM41024LA
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
I
Input Leakage Current
V
= MAX., V = V to V
CC
Com’l/
Ind.
–5
5
–1
1
µA
LI
CC
IN
SS
I
Output Leakage Current
V
= MAX.,
Com’l/
Ind.
–5
5
–1
1
µA
LO
CC
CE1 = V and CE2 = V
IH
IL,
V
= V to V
OUT
SS CC
(1)
(1)
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.5
2.2
0.8
6.0
–0.5
2.2
0.8
6.0
V
V
IL
5
IH
OL
V
I
I
= 8 mA, V = Min.
—
—
0.4
0.5
—
—
0.4
0.5
V
V
OL
OL
CC
= 10 mA, V = Min.
CC
6
V
Output High Voltage
I
= –4 mA, V = Min.
2.4
—
2.4
—
V
OH
OH
CC
NOTE: 1. V (min) = –3.0V for pulse width less than 20 ns
IL
7
Power Supply Characteristics
-10
-12
-15
Symbol Parameter
Power Com’l. Com’l. Ind. Com’l. Ind.
8
I
Operating Current
CE1 = V and CE2 = V
SA
250
230
230
240
185
195
CC
IL
IH
f = f
= 1/t
RC
LA
210
220
165
175
MAX
V
I
= Max.
= 0 mA
CC
9
OUT
I
I
Standby Current
CE1 = V and CE2 = V
SA
LA
SA
LA
80
75
20
10
70
65
20
10
70
65
25
10
55
50
10
5
55
50
15
10
SB
IH
IL
f = f
V
= 1/t
RC
MAX
= Max.
10
11
12
CC
Full Standby Current
CE1 ≥ V and CE2 ≤ V
SB1
HC
LC
f = 0
V
V
= Max.
CC
≥ V – 0.2V or ≤ 0.2V
IN
CC
SHADED AREAS = PRELIMINARY DATA
NOTES: All values are maximum guaranteed values.
≤ 0.2V, V ≥ V – 0.2V
V
LC
HC
CC
Rev. 3.3 - 4/09/98
3
PDM41024
(1)
Capacitance (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Max.
Unit
C
C
Input Capacitance
Output Capacitance
8
8
pF
pF
IN
OUT
NOTE:1. This parameter is determined by device characterization but is not production tested.
AC Test Conditions
Input pulse levels
V
to 3.0V
3 ns
SS
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
1.5V
1.5V
See Figures 1 and 2
+5V
+5V
480Ω
480Ω
DOUT
255Ω
DOUT
255Ω
5 pF
30 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t , t , t , t , t
,
LZCE HZCE LZWE HZWE LZOE
t
)
HZOE
Typical Delta t
AA
vs Capacitive Loading
5
4
3
2
1
0
0
30
60
90
120
Additional Lumped Capacitive Loading (pF)
Figure 3.
4
4/09/98 - Rev. 3.3
PDM41024
(4, 5)
Read Cycle No. 1
1
2
t
RC
ADDR
t
AA
t
OH
D
PREVIOUS DATA VALID
DATA VALID
OUT
(2, 4, 6)
3
Read Cycle No. 2
t
RC
ADDR
t
AA
t
ACE
CE1
CE2
5
t
t
HZCE
LZCE
OE
6
t
t
HZOE
LZOE
D
OUT
DATA VALID
t
AOE
7
AC Electrical Characteristics
8
(7)
(7)
Description
-10
-12
-15
READ Cycle
Sym
Min. Max. Min. Max. Min. Max. Units
9
READ cycle time
t
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address access time
t
10
10
12
12
15
15
AA
Chip enable access time
Output hold from address change
t
ACE
t
3
5
3
5
3
5
10
11
12
OH
(1,3)
Chip enable to output in low Z
t
LZCE
HZCE
(1,2,3)
Chip disable to output in high Z
t
6
6
7
(3)
Chip enable to power up time
t
t
0
0
0
0
0
0
PU
PD
(3)
Chip disable to power down time
Output enable access time
10
6
12
6
15
6
t
AOE
LZOE
HZOE
(1,3)
(1,3)
Output enable to output in low Z
t
Output disable to output in high Z
t
6
6
6
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table.
Rev. 3.3 - 4/09/98
5
PDM41024
Write Cycle No. 1 (Write Enable Controlled)
t
WC
ADDR
t
t
AH
AW
t
CW
CE2
CE1
t
AS
t
WP2
WE
t
t
DH
DS
D
IN
DATA VALID
t
HZWE
t
LZWE
HIGH-Z
D
OUT
Write Cycle No. 2 (Write Enable Controlled)
t
WC
ADDR
t
t
AH
AW
t
CW
CE2
CE1
t
AS
t
WP1
WE
t
t
DH
DS
D
IN
DATA VALID
HIGH-Z
D
OUT
NOTE: Output Enable (OE) is inactive (high)
6
4/09/98 - Rev. 3.3
PDM41024
Write Cycle No. 3 (Chip Enable Controlled)
t
WC
1
2
ADDR
t
t
AH
AW
t
t
AS
CW
CE2
CE1
t
3
WP1
WE
t
t
DH
DS
D
DATA VALID
IN
HIGH-Z
D
OUT
NOTE: Output Enable (OE) is inactive (high)
5
6
AC Electrical Characteristics
(7)
(7)
Description
-10
-12
-15
WRITE Cycle
Sym
Min. Max. Min. Max. Min. Max. Units
7
WRITE cycle time
t
t
10
10
10
0
12
10
10
0
15
11
11
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Chip enable active time
Address valid to end of write
Address setup time
CW
t
AW
8
t
AS
AH
Address hold from end of write
Write pulse width
t
0
0
0
t
8
8
11
12
7
WP1
WP2
Write pulse width
t
8
8
9
Data setup time
t
7
7
DS
Data hold time
t
0
0
0
DH
(1,3)
(1,3)
Write disable to output in low Z
t
0
0
0
LZWE
HZWE
10
11
12
Write enable to output in high Z
t
7
7
7
SHADED AREA = PRELIMINARY DATA
Notes referenced are after Data Retention Table
Rev. 3.3 - 4/09/98
7
PDM41024
Low V Data Retention Waveform
CC
Data Retention Mode
V
4.5V
4.5V
CC
V
DR
t
t
CDR
R
V
V
DR
IH
CE1
CE2
V
IL
DON'T CARE
V
IH
≤ 0.2V
V
IL
Data Retention Electrical Characteristics (LA Version Only) for JEDEC Version
Symbol Parameter
for Retention Data
Test Conditions
Min.
Typ.
Max.
Unit
V
V
2
—
—
—
—
V
DR
CC
I
Data Retention Current
CE1 ≥ V – 0.2V or
V
V
= 2V
= 3V
—
—
500
750
µA
µA
CCDR
CC
CC
CE2 ≤ V + 0.2V
SS
CC
V
≥ V – 0.2V
IN
CC
or ≤ 0.2V
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
—
—
—
—
ns
ns
CDR
(3)
t
t
RC
R
NOTES: (For three previous Electrical Characteristics tables)
1. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
2. At any given temperature and voltage condition, t
3. This parameter is sampled.
is less than t
.
HZCE
LZCE
4. WE is high for a READ cycle.
5. The device is continuously selected. All the Chip Enables are held in their active state.
6. The address is valid prior to or coincident with the latest occurring Chip Enable.
7. Vcc = 5V ± 5%.
Ordering Information
XXXXX
X
XX
Speed
X
X
X
Device Type Power
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Blank Tubes
TR
TY
Tape & Reel
Tray
Blank
I
A
Commercial (0° to +70°C)
Industrial (-40° to +85°C)
Automotive (-40° to +105°C)
TSO 32-pin 300-mil Plastic SOJ
SO
T
32-pin 400-mil Plastic SOJ
32-pin Plastic TSOP (I)
10
12
15
Commercial Only
(use 15 ns for slower designs)
SA
LA
Standard Power
Low Power
PDM41024 - 1 Meg (128Kx8) Static RAM
8
4/09/98 - Rev. 3.3
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