PDU108HSERIES [ETC]
3-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE ; 3位。 ECL -接口可编程延迟线\n
| 型号： | PDU108HSERIES |
| 厂家： | 
ETC |
| 描述： | 3-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE
|
| 文件： | 总5页 (文件大小：48K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDU108H
Ò
3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU108H)
data
delay
devices,
3
inc.
FEATURES
PACKAGES
GND
ENB
GND
OUT
1
2
16
15
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OUT
N/C
N/C
N/C
N/C
A1
GND
ENB
N/C
N/C
N/C
IN
·
·
·
·
·
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits standard 16-pin DIP socket
A0
VEE
IN
A0
6
7
8
A2
A1
A2
10
VEE
9
PDU108H-xx DIP
PDU108H-xxC3 SMD
PDU108H-xxM Military DIP PDU108H-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PDU108H-series device is a 3-bit digitally programmable delay line.
The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on
the address code (A2-A0) according to the following formula:
IN
Signal Input
OUT Signal Output
A2
A1
A0
Address Bit 2
Address Bit 1
Address Bit 0
TDA = TD0 + TINC * A
ENB Output Enable
VEE -5 Volts
GND Ground
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (ENB) is held LOW during
normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not
latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
DASH NUMBER SPECIFICATIONS
·
Total programmed delay tolerance: 5% or 1ns,
whichever is greater
Inherent delay (TD0): 2.8ns typical
Setup time and propagation delay:
Part
Number
Incremental Delay
Per Step (ns)
0.5 ± 0.3
Total
Delay (ns)
3.5 ± 1.0
7.0 ± 1.0
14 ± 1.0
21 ± 1.0
35 ± 1.7
PDU108H-.5
PDU108H-1
PDU108H-2
PDU108H-3
PDU108H-5
PDU108H-10
PDU108H-20
PDU108H-40
PDU108H-50
·
·
1.0 ± 0.4
2.0 ± 0.4
3.0 ± 0.5
5.0 ± 0.6
10.0 ± 1.0
20.0 ± 1.5
40.0 ± 2.0
50.0 ± 2.5
Address to input setup (TAIS):
3.6ns
Disable to output delay (TDISO): 1.7ns typical
Operating temperature: 0° to 70° C
Temperature coefficient: 100PPM/°C (excludes TD0)
Supply voltage VEE: -5VDC ± 5%
Power Dissipation: 290mw typical (no load)
Minimum pulse width: 25% of total delay
·
·
·
·
·
70 ± 3.5
140 ± 7.0
280 ± 14.0
350 ± 17.5
NOTE: Any dash number between .5 and 50
not shown is also available.
Ó2001 Data Delay Devices
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU108H
APPLICATION NOTES
spurious signals persists until the required TDISH
has elapsed.
ADDRESS UPDATE
The PDU108H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay tolerance
specifications and monotonicity are guaranteed.
The suggested conditions are those for which
signals will propagate through the unit without
significant distortion. The absolute conditions
are those for which the unit will produce some
type of output for a given input.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, TOAX
is required before the address lines can change.
This time is given by the following relation:
,
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
When operating the unit between the
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT pin.
The possibility of spurious signals persists until
the required TOAX has elapsed.
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will remain
constant from pulse to pulse if the input pulse
width and period remain fixed. In other words,
the delay of the unit exhibits frequency and pulse
width dependence when operated beyond the
recommended conditions. Please consult the
technical staff at Data Delay Devices if your
application has specific high-frequency
requirements.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
TDISH = Ai * TINC
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
Violation of this constraint may, depending on the
history of the input signal, cause spurious signals
to appear on the OUT pin. The possibility of
A2-A0
ENB
IN
A i-1
Ai
TAENS
TOAX
TAIS
TENIS
PWIN
TDISH
TDA
PWOUT
TDISO
OUT
Figure 1: Timing Diagram
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
PDU108H
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER
Total Programmable Delay
Inherent Delay
Disable to Output Low Delay
Address to Enable Setup Time
Address to Input Setup Time
Enable to Input Setup Time
Output to Address Change
Disable Hold Time
SYMBOL
TDT
MIN
TYP
7
2.8
1.7
UNITS
TINC
ns
ns
ns
TD0
TDISO
TAENS
TAIS
TENIS
TOAX
TDISH
PERIN
PERIN
PERIN
PWIN
PWIN
PWIN
1.0
3.6
3.6
ns
ns
See Text
See Text
20
Absolute
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
% of TDT
Input Period
Suggested
Recommended
Absolute
50
200
10
25
Input Pulse Width
Suggested
Recommended
100
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VEE
VIN
TSTRG
TLEAD
MIN
-7.0
VEE - 0.3
-55
MAX
0.3
0.3
150
300
UNITS NOTES
V
V
C
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER
SYMBOL
MIN
TYP
-0.960
-1.650
-0.980
-1.650
10
MAX
UNITS
NOTES
VIH = MAX,50W to -2V
VIL = MIN, 50W to -2V
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
VOH
VOL
VIH
VIL
IIH
V
V
V
V
mA
mA
VIH = MAX
VIL = MIN
IIL
-20
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
PDU108H
PACKAGE DIMENSIONS
16 15
10
7
9
8
.400
TYP.
1
2
6
.800 TYP.
.320
MAX.
.020
TYP.
.150
.030
±
.010 TYP.
.100
.018
TYP.
TYP.
.300
TYP.
.700 TYP.
PDU108H-xx (Commercial DIP)
PDU108H-xxM (Military DIP)
.020 TYP.
.040
.010 .002
±
TYP.
16 15 14 13 12 11 10
9
.882
.005
.710 .590
MAX.
±
.005
±
.007
.005
±
1
2
3
4
5
6
7
8
.090
.100
.320
MAX.
.050
.010
.700
.880 .020
±
±
PDU108H-xxC3 (Commercial SMD)
PDU108H-xxMC3 (Military SMD)
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
PDU108H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): -5.0V ± 0.1V
Load:
Cload
50W to -2V
5pf ± 10%
:
Input Pulse:
Standard 10KH ECL
Threshold: (VOH + VOL) / 2
levels
(Rising & Falling)
Source Impedance:
Rise/Fall Time:
50W Max.
2.0 ns Max. (measured
between 20% and 80%)
PWIN = 1.5 x Total Delay
PERIN = 10 x Total Delay
Pulse Width:
Period:
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
REF
PULSE
GENERATOR
OUT
IN
OUT
IN
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
TRIG
TRIG
ADDRESS SELECT
Test Setup
PERIN
PWIN
TRISE
TFALL
INPUT
SIGNAL
VIH
80%
50%
20%
80%
50%
20%
VIL
DRISE
DFALL
OUTPUT
SIGNAL
VOH
50%
50%
VOL
Timing Diagram For Testing
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5
相关型号：
©2020 ICPDF网 联系我们和版权申明