PDU13F--.5MC3

更新时间:2025-06-29 02:50:26
品牌:ETC
描述:Delay Line

PDU13F--.5MC3 概述

Delay Line 延迟线\n

PDU13F--.5MC3 数据手册

通过下载PDU13F--.5MC3数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载
PDU13F  
Ò
3-BIT PROGRAMMABLE  
DELAY LINE  
(SERIES PDU13F)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
·
·
·
·
·
·
·
·
Digitally programmable in 8 delay steps  
Monotonic delay-versus-address variation  
Two separate outputs: inverting & non-inverting  
Precise and stable delays  
IN  
N/C  
VCC  
N/C  
N/C  
N/C  
A0  
IN  
N/C  
VCC  
N/C  
N/C  
N/C  
N/C  
A0  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
N/C  
N/C  
OUT  
OUT/  
EN/  
N/C  
Input & outputs fully TTL interfaced & buffered  
10 T2L fan-out capability  
OUT  
OUT/  
EN/  
Fits standard 14-pin DIP socket  
Auto-insertable  
A1  
GND  
A2  
A1  
8
GND  
A2  
PDU13F-xx  
DIP  
PDU13F-xxA2 Gull-Wing  
PDU13F-xxB2 J-Lead  
PDU13F-xxM Military DIP  
PDU13F-xxMC3  
Military Gull-Wing  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
IN  
Delay Line Input  
The PDU13F-series device is a 3-bit digitally programmable delay line.  
The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)  
depends on the address code (A2-A0) according to the following formula:  
OUT Non-inverted Output  
OUT/ Inverted Output  
A2  
A1  
A0  
Address Bit 2  
Address Bit 1  
Address Bit 0  
TDA = TD0 + TINC * A  
EN/ Output Enable  
VCC +5 Volts  
GND Ground  
where A is the address code, TINC is the incremental delay of the device,  
and TD0 is the inherent delay of the device. The incremental delay is  
specified by the dash number of the device and can range from 0.5ns  
through 50ns, inclusively. The enable pin (EN/) is held LOW during  
normal operation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH  
states, respectively. The address is not latched and must remain asserted during normal operation.  
DASH NUMBER SPECIFICATIONS  
SERIES SPECIFICATIONS  
Part  
Number  
Incremental Delay  
Per Step (ns)  
.5 ± .3  
Total Delay  
Change (ns)  
3.5 ± 1.0  
7 ± 1.0  
14 ± 1.0  
21 ± 1.1  
35 ± 1.8  
70 ± 3.5  
105 ± 5.3  
140 ± 7.0  
280 ± 14.0  
350 ± 17.5  
·
·
·
Total programmed delay tolerance: 5% or 1ns,  
whichever is greater  
Inherent delay (TD0): 6ns typical (OUT)  
5.5ns typical (OUT/)  
Setup time and propagation delay:  
Address to input setup (TAIS): 6ns  
Disable to output delay (TDISO): 6ns typ. (OUT)  
Operating temperature: 0° to 70° C  
Temperature coefficient: 100PPM/°C (excludes TD0)  
Supply voltage VCC: 5VDC ± 5%  
Supply current: ICCH = 45ma  
PDU13F-.5  
PDU13F-1  
PDU13F-2  
PDU13F-3  
PDU13F-5  
PDU13F-10  
PDU13F-15  
PDU13F-20  
PDU13F-40  
PDU13F-50  
1 ± .4  
2 ± .4  
3 ± .5  
5 ± .6  
10 ± 1.0  
15 ± 1.3  
20 ± 1.5  
40 ± 2.0  
50 ± 2.5  
·
·
·
·
NOTE: Any dash number between .5 and 50 not  
shown is also available.  
ICCL = 20ma  
Minimum pulse width: 20% of total delay  
·
Ó1997 Data Delay Devices  
Doc #97001  
1/10/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
PDU13F  
APPLICATION NOTES  
possibility of spurious signals persists until the  
required TDISH has elapsed.  
ADDRESS UPDATE  
The PDU13F is a memory device. As such,  
special precautions must be taken when  
changing the delay address in order to prevent  
spurious output signals. The timing restrictions  
are shown in Figure 1.  
INPUT RESTRICTIONS  
There are three types of restrictions on input  
pulse width and period listed in the AC  
Characteristics table. The recommended  
conditions are those for which the delay  
After the last signal edge to be delayed has  
appeared on the OUT pin, a minimum time,  
TOAX, is required before the address lines can  
change. This time is given by the following  
relation:  
tolerance specifications and monotonicity are  
guaranteed. The suggested conditions are  
those for which signals will propagate through the  
unit without significant distortion. The absolute  
conditions are those for which the unit will  
produce some type of output for a given input.  
TOAX = max { (Ai - A i-1) * TINC , 0 }  
where A i-1 and Ai are the old and new address  
codes, respectively. Violation of this constraint  
may, depending on the history of the input signal,  
cause spurious signals to appear on the OUT  
pin. The possibility of spurious signals persists  
until the required TOAX has elapsed.  
When operating the unit between the  
recommended and absolute conditions, the  
delays may deviate from their values at low  
frequency. However, these deviations will  
remain constant from pulse to pulse if the input  
pulse width and period remain fixed. In other  
words, the delay of the unit exhibits frequency  
and pulse width dependence when operated  
beyond the recommended conditions. Please  
consult the technical staff at Data Delay Devices  
if your application has specific high-frequency  
requirements.  
A similar situation occurs when using the EN/  
signal to disable the output while IN is active. In  
this case, the unit must be held in the disabled  
state until the device is able to “clear” itself. This  
is achieved by holding the EN/ signal high and  
the IN signal low for a time given by:  
Please note that the increment tolerances listed  
represent a design goal. Although most delay  
increments will fall within tolerance, they are not  
guaranteed throughout the address range of the  
unit. Monotonicity is, however, guaranteed over  
all addresses.  
TDISH = Ai * TINC  
Violation of this constraint may, depending on  
the history of the input signal, cause spurious  
signals to appear on the OUT pin. The  
A2-A0  
EN/  
A i-1  
Ai  
TAENS  
TOAX  
TAIS  
TENIS  
PWIN  
TDISH  
IN  
TDA  
PWOUT  
TDISO  
OUT  
OUT/  
TSKEW  
Figure 1: Timing Diagram  
Doc #97001  
1/10/97  
DATA DELAY DEVICES, INC.  
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
PDU13F  
DEVICE SPECIFICATIONS  
TABLE 1: AC CHARACTERISTICS  
PARAMETER  
Total Programmable Delay  
Inherent Delay  
SYMBOL  
TDT  
MIN  
TYP  
7
6.0  
1.5  
6.0  
UNITS  
TINC  
ns  
TD0  
Output Skew  
TSKEW  
TDISO  
TAENS  
TAIS  
TENIS  
TOAX  
TDISH  
PERIN  
PERIN  
PERIN  
PWIN  
PWIN  
PWIN  
ns  
ns  
ns  
ns  
Disable to Output Low Delay  
Address to Enable Setup Time  
Address to Input Setup Time  
Enable to Input Setup Time  
Output to Address Change  
Disable Hold Time  
2.0  
6.0  
6.0  
ns  
See Text  
See Text  
20  
Absolute  
% of TDT  
% of TDT  
% of TDT  
% of TDT  
% of TDT  
% of TDT  
Input Period  
Suggested  
Recommended  
Absolute  
50  
200  
10  
25  
Input Pulse Width  
Suggested  
Recommended  
100  
TABLE 2: ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
DC Supply Voltage  
Input Pin Voltage  
Storage Temperature  
Lead Temperature  
SYMBOL  
VCC  
VIN  
TSTRG  
TLEAD  
MIN  
-0.3  
-0.3  
-55  
MAX  
7.0  
VDD+0.3  
150  
UNITS NOTES  
V
V
C
300  
C
10 sec  
TABLE 3: DC ELECTRICAL CHARACTERISTICS  
(0C to 70C, 4.75V to 5.25V)  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
High Level Output Voltage  
VOH  
2.5  
3.4  
V
VCC = MIN, IOH = MAX  
VIH = MIN, VIL = MAX  
VCC = MIN, IOL = MAX  
VIH = MIN, VIL = MAX  
Low Level Output Voltage  
VOL  
0.35  
0.5  
V
High Level Output Current  
Low Level Output Current  
High Level Input Voltage  
Low Level Input Voltage  
Input Clamp Voltage  
Input Current at Maximum  
Input Voltage  
High Level Input Current  
Low Level Input Current  
Short-circuit Output Current  
Output High Fan-out  
IOH  
IOL  
VIH  
VIL  
VIK  
IIHH  
-1.0  
20.0  
mA  
mA  
V
V
V
2.0  
-60  
0.8  
-1.2  
0.1  
VCC = MIN, II = IIK  
VCC = MAX, VI = 7.0V  
mA  
IIH  
IIL  
IOS  
20  
-0.6  
-150  
25  
VCC = MAX, VI = 2.7V  
VCC = MAX, VI = 0.5V  
VCC = MAX  
mA  
mA  
mA  
Unit  
Load  
Output Low Fan-out  
12.5  
Doc #97001  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
3
1/10/97  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
PDU13F  
PACKAGE DIMENSIONS  
.020 TYP.  
14 13 12 11 10  
.040  
TYP.  
.010 TYP.  
9
6
8
7
14 13 12 11 10  
9
6
8
7
.270  
TYP.  
.430  
TYP.  
Lead Material:  
Nickel-Iron alloy 42  
TIN PLATE  
1
2
3
4
5
.090  
.100  
.300  
MAX.  
.050  
TYP.  
.600  
1
2
3
4
5
.790 MAX.  
.280  
MAX.  
.820 MAX.  
Commercial Gull-Wing (PDU13F-xxA2)  
.290  
MAX.  
.040  
TYP.  
.020 TYP.  
.050 TYP.  
14 13 12 11 10  
9
6
8
7
.320  
TYP.  
.015 TYP.  
.070 MAX.  
.270  
TYP.  
±
.010 .002  
1
2
3
4
5
.018  
TYP.  
.350  
MAX.  
±
.600 .010  
6 Equal spaces  
.110  
.100  
.350  
MAX.  
.110  
TYP.  
each .100±.010  
Non-Accumulative  
.600  
.790 MAX.  
Commercial DIP (PDU13F-xx)  
Commercial J-Lead (PDU13F-xxB2)  
14 13 12 11 10  
9
6
8
7
.410  
TYP.  
.020 TYP.  
.040  
±
.010 .002  
1
2
3
4
5
TYP.  
16 15 14 13 12 11 10  
9
.820 MAX.  
.882  
.710 .590  
MAX.  
±
.005  
±
.005  
.007  
.320  
MAX.  
.020  
TYP.  
±
.005  
1
2
3
4
5
6
7
8
.130  
±
.030  
.020 TYP.  
.090  
.100  
.280  
.050  
±
.010  
.100  
TYP.  
.018 TYP.  
.600 TYP.  
MAX.  
.700  
.300  
TYP.  
.880±.020  
Military DIP (PDU13F-xxM)  
Military Gull-Wing (PDU13F-xxMC3)  
Doc #97001  
1/10/97  
DATA DELAY DEVICES, INC.  
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com  
Powered by ICminer.com Electronic-Library Service CopyRight 2003  
PDU13F  
DELAY LINE AUTOMATED TESTING  
TEST CONDITIONS  
INPUT:  
OUTPUT:  
Ambient Temperature: 25oC ± 3oC  
Supply Voltage (Vcc): 5.0V ± 0.1V  
Load:  
Cload  
1 FAST-TTL Gate  
5pf ± 10%  
:
Input Pulse:  
High = 3.0V ± 0.1V  
Threshold: 1.5V (Rising & Falling)  
Low = 0.0V ± 0.1V  
Source Impedance:  
Rise/Fall Time:  
50W Max.  
3.0 ns Max. (measured  
between 0.6V and 2.4V )  
PWIN = 1.5 x Total Delay  
PERIN = 4.5 x Total Delay  
Pulse Width:  
Period:  
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.  
PRINTER  
COMPUTER  
SYSTEM  
REF  
PULSE  
GENERATOR  
OUT  
IN  
OUT  
IN  
TIME INTERVAL  
COUNTER  
DEVICE UNDER  
TEST (DUT)  
TRIG  
TRIG  
Test Setup  
PERIN  
PWIN  
VIH  
TRISE  
TFALL  
INPUT  
SIGNAL  
2.4V  
1.5V  
0.6V  
2.4V  
1.5V  
0.6V  
VIL  
TDAR  
TDAF  
OUTPUT  
SIGNAL  
VOH  
1.5V  
1.5V  
VOL  
Timing Diagram For Testing  
Doc #97001  
1/10/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
5
Powered by ICminer.com Electronic-Library Service CopyRight 2003  

PDU13F--.5MC3 相关器件

型号 制造商 描述 价格 文档
PDU13F-.5 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-.5A2 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-.5B2 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-.5M DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-.5MC3 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-1 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-10 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-10A2 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-10B2 DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
PDU13F-10M DATADELAY 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) 获取价格
Hi,有什么可以帮您? 在线客服 或 微信扫码咨询